"A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS."

Kuan-Yueh James Shen et al. (2018)

> Home

Details and statistics

DOI: 10.1109/TCSI.2017.2784319

access: closed

type: Journal Article

metadata version: 2021-05-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/ShenFFNWNKE18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/ShenFFNWNKE18
Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Mark Neidengard, Nasser A. Kurd, Amr Elshazly:
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2109-2117 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.