"Design and Experimental Verification of a 6.25-GHz PLL for Harsh ..."

Marco Mestice et al. (2024)

> Home

Details and statistics

DOI: 10.1109/TIM.2024.3488132

access: closed

type: Journal Article

metadata version: 2024-12-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tim/MesticeCRS24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tim/MesticeCRS24
Marco Mestice, Gabriele Ciarpi, Daniele Rossi, Sergio Saponara:
Design and Experimental Verification of a 6.25-GHz PLL for Harsh Temperature Conditions in 65-nm CMOS Technology. IEEE Trans. Instrum. Meas. 73: 1-16 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.