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Energy Reduction Method by Compiler Optimization

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Artificial Intelligence and Security (ICAIS 2022)

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Abstract

As nanoscale processing becomes the mainstream in IC manufacturing, the crosstalk problem rises as a serious challenge, not only for energy-efficiency and performance but also for security requirements. In this paper, we propose a register reallocation algorithm called Nearby Access based Register Reallocation (NARR) to reduce the crosstalk between instruction buses. The method includes construction of the software Nearby Access Aware Interference Graph (NAIG), using data flow analysis at assembly level, and reallocation of the registers to the software. Experimental results show that the crosstalk could be dramatically minimized, especially for 4C crosstalk, with a reduction of 80.84% in average, and up to 99.99% at most.

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References

  1. Hemalatha, P., Dhanalakshmi, K.: Cellular automata based energy efficient approach for improving security in IoT. Intell. Autom. Soft Comput. 32(2), 811–825 (2022)

    Article  Google Scholar 

  2. Mahmoud, S., Salman, A.: Cost estimate and input energy of floor systems in low seismic regions. Comput. Mater. Continua 71(2), 2159–2173 (2022)

    Article  Google Scholar 

  3. Maharajan, M., Abirami, T.: Energy efficient QoS aware cluster based multihop routing protocol for WSN. Comput. Syst. Sci. Eng. 41(3), 1173–1189 (2022)

    Article  Google Scholar 

  4. Zaini, H.G.: Forecasting of appliances house in a low-energy depend on grey wolf optimizer. Comput. Mater. Continua 71(2), 2303–2314 (2022)

    Article  Google Scholar 

  5. Bamberg, L., Najafi, A., Garciaortiz, A.: Edge effect aware low-power crosstalk avoidance technique for 3D integration. Integration 69(1), 98–110 (2019)

    Article  Google Scholar 

  6. Chen, W., Lueh, G., Ashar, P.J., Chen, K., Cheng, B.: Register allocation for Intel processor graphics. In: Symposium on Code Generation and Optimization, pp. 352–364 (2018)

    Google Scholar 

  7. Cui, X., Ni, Y., Miao, M., Yufeng, J.: An enhancement of crosstalk avoidance code based on fibonacci numeral system for through silicon vias. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(5), 1601–1610 (2017)

    Google Scholar 

  8. Duan, C., Calle, V.H.C., Khatri, S.P.: Efficient on-chip crosstalk avoidance codec design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(4), 551–560 (2009)

    Google Scholar 

  9. Florea, A., Geliert, A.: E-learning approach of the graph coloring problem applied to register allocation in embedded systems. In: The Sixth International Conference on Innovative Computing Technology (INTECH 2016), pp. 173–178 (2016)

    Google Scholar 

  10. Gupta, U., Ranganathan, N.: A utilitarian approach to variation aware delay, power, and crosstalk noise optimization. IEEE Educ. Activities Dept. 19(9), 1723–1726 (2011)

    Google Scholar 

  11. Guthaus, M.R., Ringenberg, J., Ernst, D.J., Austin, T., Mudge, T., et al.: MiBench: a free, commercially representative embedded benchmark suite. In: The 4th Annual IEEE International Workshop on Workload Characterization (WWC 2001), pp. 3–14 (2001)

    Google Scholar 

  12. Halak, B., Yakovlev, A.: Throughput optimization for area-constrained links with crosstalk avoidance methods. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18(6), 1016–1019 (2010)

    Google Scholar 

  13. Jiao, H., Wang, R.R., He, Y.: Crosstalk-noise-aware bus coding with low-power ground-gated repeaters. Int. J. Circuit Theory Appl. 46(2), 280–289 (2018)

    Article  Google Scholar 

  14. Kananizadeh, S., Kononenko, K.: Improving on linear scan register allocation. Int. J. Autom. Comput. 15(2), 228–238 (2018). https://doi.org/10.1007/s11633-017-1100-0

    Article  Google Scholar 

  15. Kuo, W.A., Chiang, Y.L., Hwang, T.T., Wu, A.C.H.: Performance-driven crosstalk elimination at postcompiler level-the case of low-crosstalk op-code assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), 564–573 (2007)

    Article  Google Scholar 

  16. Liu, F., Yarom, Y., Ge, Q., Heiser, G., Lee, R.B.: Last-level cache side-channel attacks are practical. In: IEEE Symposium on Security and Privacy (SP), pp. 605–622 (2015)

    Google Scholar 

  17. Lozano, R.C., Carlsson, M., Blindell, G.H., Schulte, C.: Combinatorial register allocation and instruction scheduling. arXiv:1804.02452 (2018)

  18. Lucas, A.H., Moraes, F.: Crosstalk fault tolerant NOC: design and evaluation. In: IFIP IEEE International Conference on Very Large Scale Integration, pp. 81–93 (2009)

    Google Scholar 

  19. Mangard, S., Oswald, E., Standaert, F.X.: One for all-all for one: unifying standard differential power analysis attacks. IET Inf. Secur. 5(2), 100–110 (2011)

    Article  Google Scholar 

  20. Moll, F., Roca, M., Isern, E.: Analysis of dissipation energy of switching digital CMOS gates with coupled outputs. Microelectron. J. 34(9), 833–842 (2003)

    Article  Google Scholar 

  21. Mutyam, M.: Selective shielding technique to eliminate crosstalk transitions. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 14(3), 1–43 (2009)

    Article  Google Scholar 

  22. Odaira, R., Nakaike, T., Inagaki, T., Komatsu, H., Nakatani, T.: Coloring-based coalescing for graph coloring register allocation. In: IEEE/ACM International Symposium on Code Generation & Optimization, pp. 160–169 (2010)

    Google Scholar 

  23. Ohama, Y., Yotsuyanagi, H., Hashizume, M., Higami, Y., Takahashi, H.: On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects. In: International Symposium on Communications and Information Technologies, pp. 1–5 (2017)

    Google Scholar 

  24. Park, J., Xu, X., Jin, Y., Forte, D., Tehranipoor, M.: Power-based side-channel instruction-level disassembler. In: IEEE 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pp. 1–6 (2018)

    Google Scholar 

  25. Poletto, M., Sarkar, A.V.: Linear scan register allocation. ACM Trans. Program. Lang. Syst. (TOPLAS) 21(5), 895–913 (1999)

    Article  Google Scholar 

  26. Shirmohammadi, Z., Mozafari, F., Miremadi, S.G.: An efficient numerical-based crosstalk avoidance codec design for NoCs. Microprocess. Microsyst. 50(1), 127–137 (2017)

    Article  Google Scholar 

  27. Shirmohammadi, Z., Sabzi, H.Z.: DR: overhead efficient RLC crosstalk avoidance code. In: International Conference on Computer and Knowledge Engineering, pp. 1–6 (2018)

    Google Scholar 

  28. Su, X., Wu, H., Xue, J.: An efficient WCET-aware instruction scheduling and register Al-location approach for clustered VLIW processors. ACM Trans. Embed. Comput. Syst. 16(5), 1–21 (2017)

    Article  Google Scholar 

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Funding

This work was supported by the Foundation Project of Philosophy and Social Science of Hunan (17YBA115, Sheng Xiao, 2018); Project of Hunan Social Science Achievement Evaluation Committee (XSP20YBZ090, Sheng Xiao, 2020).

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Correspondence to Sheng Xiao .

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Xiao, S., He, J.S., Yang, J., Hong, X., Luo, J. (2022). Energy Reduction Method by Compiler Optimization. In: Sun, X., Zhang, X., Xia, Z., Bertino, E. (eds) Artificial Intelligence and Security. ICAIS 2022. Lecture Notes in Computer Science, vol 13338. Springer, Cham. https://doi.org/10.1007/978-3-031-06794-5_54

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  • DOI: https://doi.org/10.1007/978-3-031-06794-5_54

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  • Print ISBN: 978-3-031-06793-8

  • Online ISBN: 978-3-031-06794-5

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