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Multichannel High-Speed Data Caching System on FPGA for RAID Storage

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Communications, Signal Processing, and Systems (CSPS 2018)

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 517))

Abstract

Channelization RAID storage system requests multichannel data transmission and high transmission bandwidth. We design a data caching system which is inserted between fore-end data source interface and the back-end RAID interface on a FPGA implementation. The caching system uses DDR3 as the external memory because of its large storage capacity and high storage rate. It uses a special channel management system and only needs three clock cycles to complete the read–write scheduling of different channels. The caching system provides the AXI4-Lite interface, so it can be dynamically configured by the AXI4-Lite bus. After testing, the caching system can satisfy the request of multichannel storage task.

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Correspondence to Qiongzhi Wu .

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Wang, H., Bai, X., Wu, Q. (2020). Multichannel High-Speed Data Caching System on FPGA for RAID Storage. In: Liang, Q., Liu, X., Na, Z., Wang, W., Mu, J., Zhang, B. (eds) Communications, Signal Processing, and Systems. CSPS 2018. Lecture Notes in Electrical Engineering, vol 517. Springer, Singapore. https://doi.org/10.1007/978-981-13-6508-9_58

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  • DOI: https://doi.org/10.1007/978-981-13-6508-9_58

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-6507-2

  • Online ISBN: 978-981-13-6508-9

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