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Memory Reliability Improvement Based on Maximized Error-Correcting Codes

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Abstract

Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some widespread ECCs. A method is proposed for the selection of multi-bit errors that can be additionally corrected with a minimal impact on ECC decoder latency. These methods were applied to single-bit error correction (SEC) codes and double-bit error correction (DEC) codes. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are independent and identically distributed. It is shown that the application of the proposed methods to conventional DEC codes can improve the mean-time-to-failure (MTTF) of memories with up to 30 %. Maximized versions of the DEC codes are also proposed in which all adjacent triple-bit errors become correctable without affecting the maximum number of triple-bit errors that can be made correctable.

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Acknowledgments

We are very grateful to Ken Mackay and Jérémy Alvarez-Hérault from Crocus Technology for their support and valuable advices.

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Authors and Affiliations

  1. CEA, LIST, Saclay Nano-INNOV, PC 172, 91191, Gif sur Yvette Cedex, France

    Valentin Gherman, Samuel Evain & Yannick Bonhomme

Authors
  1. Valentin Gherman
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  2. Samuel Evain
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  3. Yannick Bonhomme
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Corresponding author

Correspondence to Valentin Gherman.

Additional information

Responsible Editor: M. Violante

Submission based on an ETS2012 paper and solicited by ETS. This work has been funded by the French national research agency under the framework of the ANR-10-SEGI-007 EMYR (Enhancement of MRAM Memory Yield and Reliability) project.

This work has been funded by the French national research agency under the framework of the ANR-10-SEGI-007 EMYR (Enhancement of MRAM Memory Yield and Reliability) project.

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Gherman, V., Evain, S. & Bonhomme, Y. Memory Reliability Improvement Based on Maximized Error-Correcting Codes. J Electron Test 29, 601–608 (2013). https://doi.org/10.1007/s10836-013-5396-6

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  • DOI: https://doi.org/10.1007/s10836-013-5396-6

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