Abstract
In low-power SRAMs, power gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting off one or more memory blocks (core-cell array, address decoder, I/O logic, etc.), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we first present a detailed analysis based on electrical simulations to identify faulty behaviors caused by realistic defects that may affect power gating mechanisms embedded in low-power SRAMs. Based on this analysis, we present an efficient test solution targeting detection of observed faulty behaviors. As a final contribution, we propose novel techniques to mitigate the impact of studied defects, once detected by test methods, therefore providing significant yield improvement.
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Responsible Editor: S. Hamdioui
This paper is an extended version of a previously published paper [26]. Main contributions of this paper with respect to [26] are:
• A more detailed analysis of experimental results that characterize the impacts of studied resistive-open defects.
• A comprehensive analysis of experimental results showing that the impacts of the most critical defect (Df6) can be mitigated at the expense of increased wake up time or clock cycle.
• A more detailed analysis of conditions to coverage faulty behaviors caused by Df6.
• A detailed and comprehensive analysis on techniques to estimate the adjusted wake up time and clock cycle that must be used to in order to mitigate the impact of Df6 on SRAM devices that are in presence of such defect.
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Bonet Zordan, L.H., Bosio, A., Dilillo, L. et al. On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J Electron Test 30, 611–627 (2014). https://doi.org/10.1007/s10836-014-5479-z
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DOI: https://doi.org/10.1007/s10836-014-5479-z