Abstract
Quantum circuits are one of the best platforms to implement quantum algorithms. Concerning fault-tolerant quantum circuit, the Clifford + T gate set supports quantum circuits against decoherence error. However, they cause physical resource overheads like many qubits and the use of T gates as a high-cost computing element. This work focuses on low T-cost fault tolerant quantum ALU implementation using Clifford + T gate set. Three new different designs of quantum ALU are proposed by introducing a new quantum logic unit, and new low-cost fault tolerant implementations of full adder and subtractor circuits. We present a novel lemma in synthesizing quantum NCV-based circuits to Clifford + T quantum circuits. This lemma shows how an NCV-based structure with less CNOT layer can lead to an improvement in T-count and T-depth criteria in Clifford + T equivalent circuit. We analyze the effect of applying our proposed lemma in implementing low-cost fault tolerant Clifford + T circuits by some examples on adder and subtractors and ALUs. Comparison of the designs shows 50%, 40%, 36%, and 69% superior functionality of our proposed ALU module in terms of T-count, T-depth, number of qubits, and number of calculated operations compared to the existing counterpart, respectively. The proposed lemma can be used as a simplification step in quantum circuit synthesis algorithms and can be extended to use in quantum synthesis tools.
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References
Moore, G.E.: Gramming more components onto integrated circuits. Electronics 38, 8 (1965)
Zarandi, A.D., Reshadinezhad, M.R., Rubio, A.: A systematic method to design efficient ternary high performance CNTFET-based logic cells. IEEE Access 8, 58585–58593 (2020). https://doi.org/10.1109/ACCESS.2020.2982738
Fatemieh, S.E., Reshadinezhad, M.R., TaheriNejad, N.: Fast and compact serial imply-based approximate full adders applied in image processing. IEEE J. Emerg. Sel. Top. Circuits Syst. 13(1), 175–188 (2023). https://doi.org/10.1109/JETCAS.2023.3241012
Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183–191 (1961). https://doi.org/10.1147/rd.53.0183
Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973). https://doi.org/10.1147/rd.176.0525
Biswal, L., Bandyopadhyay, C., Ghosh, S., Rahaman, H.: Fault-tolerant implementation of quantum arithmetic and logical unit (QALU) using Clifford+T-group, pp. 833–844. Springer, (2021). https://doi.org/10.1007/978-981-15-7834-2_78
Paler, A., Polian, I., Nemoto, K., Devitt, S.J.: Fault-tolerant, high-level quantum circuits: form, compilation and description. Quantum Sci. Technol. 2(2), 025003 (2017). https://doi.org/10.1088/2058-9565/aa66eb
Zhou, X., Leung, D.W., Chuang, I.L.: Methodology for quantum logic gate construction. Phys. Rev. A 62, 052316 (2000). https://doi.org/10.1103/PhysRevA.62.052316
Thapliyal, H., Muñoz-Coreas, E., Khalus, V.: Quantum circuit designs of carry lookahead adder optimized for t-count t-depth and qubits. Sustain. Comput. Inform. Syst. 29, 100457 (2021)
Amy, M., Maslov, D., Mosca, M.: Polynomial-time T-depth optimization of Clifford+T circuits via matroid partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10), 1476–1489 (2014). https://doi.org/10.1109/TCAD.2014.2341953
Haghparast, M., Bolhassani, A.: Optimization approaches for designing quantum reversible arithmetic logic unit. Int. J. Theor. Phys. 55, 1423–1437 (2016). https://doi.org/10.1007/s10773-015-2782-0
Deeptha, A., Muthanna, D., Dhrithi, M., Pratiksha, M., Kariyappa, B. S.: Design and optimization of 8 bit ALU using reversible logic. 1632–1636 (2016). https://ieeexplore.ieee.org/abstract/document/7808109
Kamaraj, A., Marichamy, P.: Design and implementation of arithmetic and logic unit (ALU) using novel reversible gates in quantum cellular automata. 1–8 (2017). https://ieeexplore.ieee.org/document/8014578
Khatter, P., Pandey, N., Gupta, K.: An arithmetic and logical unit using reversible gates. 476–480 (2018). https://ieeexplore.ieee.org/abstract/document/8675034
Navimipour, N.J., Ahmadpour, S.-S., Yalcin, S.: A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots. J. Supercomput. 80(1), 1–18 (2023). https://doi.org/10.1007/s11227-023-05491-x
Venna, R.K.R., Jayakumar, G.D.: Design of novel area-efficient coplanar reversible arithmetic and logic unit with an energy estimation in quantum-dot cellular automata. J. Supercomput. 79(2), 1908–1925 (2023). https://doi.org/10.1007/s11227-022-04740-9
Aliabadian, R., Golsorkhtabaramiri, M., Heikalabad, S.R., Sohrabi, M.K.: Design of an ultra-high-speed coplanar QCA reversible ALU with a novel coplanar reversible full adder based on MTSG. Eur. Phys. J. Plus 138(5), 481 (2023). https://doi.org/10.1140/epjp/s13360-023-04007-z
Aliabadian, R., Golsorkhtabaramiri, M., Heikalabad, S.R., Sohrabi, M.K.: Design of a reversible ALU using a novel coplanar reversible full adder and mf gate in QCA nanotechnology. Opt. Quantum Electron. 55(2), 191 (2023). https://doi.org/10.1007/s11082-022-04382-4
Pahuja, S., Kaur, G.: Design of parity preserving arithmetic and logic unit using reversible logic gates. 1–9 (2021). https://ieeexplore.ieee.org/abstract/document/9498539
Moghimi, S., Reshadinezhad, M.R.: A novel 4\(\times \) 4 universal reversible gate as a cost efficient full adder/subtractor in terms of reversible and quantum metrics. Int. J. Modern Edu. Comput. Sci. 7(11), 28–34 (2015)
Bhat, H.A., Khanday, F.A., Kaushik, B.K.: Optimized quantum implementation of novel controlled adders/subtractors. Quantum Inf. Process. 22, 174 (2023). https://doi.org/10.1007/s11128-023-03896-4
Li, H.-S., Fan, P., Xia, H., Peng, H., Long, G.-L.: Efficient quantum arithmetic operation circuits for quantum image processing. Sc. China Phys. Mech. Astron. 63, 1–13 (2020). https://doi.org/10.1007/s11433-020-1582-8
Moghimi, S., Reshadinezhad, M.R., Rubio, A.: Toward designing high-speed cost-efficient quantum reversible carry select adders. IEEE Trans. Emerg. Top. Comput. 1–15 (2023). https://doi.org/10.1109/TETC.2023.3332426
Acampora, G., Di Martino, F., Massa, A., Schiattarella, R., Vitiello, A.: D-NISQ: a reference model for distributed noisy intermediate-scale quantum computers. Inf. Fusion 89, 16–28 (2023)
Barenco, A., et al.: Elementary gates for quantum computation. Phys. Rev. A 52, 3457–3467 (1995)
Buhrman, H., et al.: New limits on fault-tolerant quantum computation. 411–419 (2006)
Thapliyal, H., MuNoz-Coreas, E., Varun, T.S.S., Humble, T.S.: Quantum circuit designs of integer division optimizing t-count and t-depth. IEEE Trans. Emerg. Top. Comput. 9(2), 1045–1056 (2021). https://doi.org/10.1109/TETC.2019.2910870
Moallem, P., Ehsanpour, M., Bolhasani, A., Montazeri, M.: Optimized reversible arithmetic logic units. J. Electron. 31, 394–405 (2014). https://doi.org/10.1007/s11767-014-4081-y
Gayathri, S.S., et al.: T-count optimized quantum circuit for floating point addition and multiplication. Quantum Inf. Process. 20, 378 (2021). https://doi.org/10.1007/s11128-021-03296-6
Orts, F., et al.: Efficient design of a quantum absolute-value circuit using Clifford+T gates. J. Supercomput. 79, 12656–12670 (2023). https://doi.org/10.1007/s11227-023-05162-x
Orts, F., Filatovas, E., Ortega, G., SanJuan-Estrada, J.F., Garzón, E.M.: Improving the number of \(T\) gates and their spread in integer multipliers on quantum computing. Phys. Rev. A 107, 042621 (2023). https://doi.org/10.1103/PhysRevA.107.042621
Xu, L., Xu, J., Qian, D., Hu, G.: Analysis on simplified method of IoT-based HHL algorithm corresponding quantum circuit for quantum computer application. Period. Polytech. Electr. Eng. Comput. Sci. 2023, 1063505 (2023). https://doi.org/10.1155/2023/1063505
Mirizadeh, S.M.A., Asghar, P.: Fault-tolerant quantum reversible full adder/subtractor: design and implementation. Optik 253, 168543 (2022). https://doi.org/10.1016/j.ijleo.2021.168543
PourAliAkbar, E., Navi, K., Haghparast, M., Reshadi, M.: Novel optimum parity-preserving reversible multiplier circuits. Circuits Syst. Signal Process. 39, 5148–5168 (2020). https://doi.org/10.1007/s00034-020-01406-w
Fredkin, E., Toffoli, T.: Conservative logic. Int. J. Theor. Phys. 21(3–4), 219–253 (1982). https://doi.org/10.1007/BF01857727
Misra, N.K., Wairya, S., Sen, B.: Design of conservative, reversible sequential logic for cost efficient emerging nano circuits with enhanced testability. Ain Shams Eng. J. 9(4), 2027–2037 (2018)
Thakral, S., Bansal, D.: Novel reversible ALU architecture using DSG gate, pp. 149–156. Springer, (2020). https://doi.org/10.1007/978-981-15-1518-7_12
Norouzi, M., Heikalabad, S.R., Salimzadeh, F.: A reversible ALU using HNG and Ferdkin gates in QCA nanotechnology. Int. J. Circuit Theory Appl. 48(8), 1291–1303 (2020). https://doi.org/10.1002/cta.2799
Miller, D.M., Soeken, M., Drechsler, R.: Mapping NCV circuits to optimized Clifford+ t circuits, pp. 163–175. Springer, (2014). https://doi.org/10.1007/978-3-319-08494-7_13
Muñoz-Coreas, E., Thapliyal, H. Everything you always wanted to know about quantum circuits. (2022) arXiv:2208.11725
Zhou, R.-G., Li, Y.-C., Zhang, M.-Q.: Novel designs for fault tolerant reversible binary coded decimal adders. Int. J. Electron. 101(10), 1336–1356 (2014). https://doi.org/10.1080/00207217.2013.832388
Thabah, S.D., Saha, P.: A low quantum cost implementation of reversible binary-coded-decimal adder. Period. Polytech. Electr. Eng. Comput. Sci. 64(4), 343–351 (2020). https://doi.org/10.3311/PPee.15659
Gidney, C.: Halving the cost of quantum addition. Quantum 2, 74 (2018). https://doi.org/10.22331/q-2018-06-18-74
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SK and SM made substantial contributions to the conception or design of the work; or the acquisition, analysis, or interpretation of data for the work. SK, MRR, and SM involved in drafting the work or revising it critically for important intellectual content. MRR gave final approval of the version to be published. Agreement to be accountable for all aspects of the work in ensuring that questions related to the accuracy or integrity of any part of the work are appropriately investigated and resolved by SK, MRR, and SM.
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Keshavarz, S., Reshadinezhad, M.R. & Moghimi, S. T-count and T-depth efficient fault-tolerant quantum arithmetic and logic unit. Quantum Inf Process 23, 245 (2024). https://doi.org/10.1007/s11128-024-04456-0
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DOI: https://doi.org/10.1007/s11128-024-04456-0