Abstract
Because of its ability to effectively suppress off-leakage current with its gate-around configuration, the Si nanowire FET is considered to be the ultimate structure for ultra-small CMOS devices to the extent that the devices would be approaching their downsized limits. Recently, several experimental studies of Si nanowire FETs with on-currents much larger than those of planar MOSFETs have been published. Consequently, Si nanowire FETs are now gaining significant attention as the most promising candidate for mainstream CMOS devices in the 2020s. To enable the introduction of the Si nanowire FETs into integrated circuits, good compact models, which circuit designers can easily handle, are essential. However, it is a very challenging task to establish such a compact model, because the I D–V D characteristics of Si nanowire FETs are affected by the band structure of the nanowire, which is very sensitive to the nanowire diameter, cross-sectional shape, crystal orientation, mechanical stress and interface states. In this paper, the recent status of research on Si nanowire FETs in experimental and theoretical studies is described.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Iwai H. Roadmap for 22 nm and beyond. Microelectron Eng, 2009, 86: 1520–1528
Suk S D, Lee S Y, Kim S M, et al. High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer, characteristics, and reliability. In: IEDM, 2005. 717–720
Singh N, Lim F Y, Fang W W, et al. Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance. In: IEDM, 2006. 383–386
Ernst T, Dupre C, Isheden C, et al. Novel 3D integration process for highly scalable nano-beam stacked-channels GAA (NBG) Fin FETs with HfO2/TiN gate stack. In: IEDM, 2006. 997–1001
Tian Y, Huang R, Wang Y, et al. New self-aligned silicon nanowire transistors on bulk substrate fabricated by Epi-free compatible CMOS technology: Process integration, Experimental characterization of carrier transport and low frequency noise. In: IEDM, 2007. 895–899
Ernst T, Duraffourg L, Dupre C, et al. Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration? In: IEDM, San Francisco, CA, USA, 2008. 745–749
Bidal G, Boeul F, Denorme S, et al. High velocity Si-nano-dot: a candidate for SRAM applications at 16 nm node and below. In: Symp VLSI Tech, 2009. 240–241
Bangsaruntip S, Cohen G M, Majumdar A, et al. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling. In: IEDM, 2009. 297–300
Tachi K, Casse M, Jang D, et al. Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires. In: IEDM, 2009. 313–316
Sato S, Kamimura H, Arai H, et al. High-performance Si nanowire FET with a semi gate-around structure suitable for integration. Solid-State Electron, 2010, 54: 925–928
ITRS 2009 Ed: http://www.itrs.net/Links/2009ITRS/Home2009.htm
Sakaki H. Scattering suppression and high-mobility effect of size-quantized electrons in ultrafine semiconductor wire structures. Jpn J Appl Phys, 1980, 19: L735–L738
Ohno T, Shiraishi K, Ogawa T. Intrinsic origin of visible light emission from silicon quantum wires: electronics structure and geometrically restricted exciton. Phys Rev Lett, 1992, 69: 2400
Lee Y, Nagata T, Kakushima K, et al. A study on electronic structure of silicon nanowires with diverse diameters and orientations for high performance FET. In: IWDTF, 2008. 83–84
Lee Y, Kakushima K, Shiraishi K, et al. Size-dependent properties of ballistic silicon nanowire field effect transistors. J Appl Phys, 2010, 107: 113705
Lee Y, Kakushima K, Shiraishi K. Trade-off between density of states and gate capacitance in size-dependent injection velocity of ballistic n-channel silicon nanowire transistors. Appl Phys Lett. 2010, 97: 032101
Iwata J, Takahashi D, Oshiyama A, et al. A massively-parallel electronic-structure calculation based on real-space density functional theory. J Comput Phys, 2010, 229: 2339–2363
Natori K. Ballistic metal-oxide-semiconductor field effect transistor. J Appl Phys, 1994, 76: 4879–4890
Natori K. Compact modeling of ballistic nanowire MOSFETs. IEEE Trans ED, 2008, 55: 2877–2885
Landauer R. Conductance from transmission: Common sense points. Phys Scripta, 1992, T42: 110–114
Gnani E, Reggiani S, Gnudi A, et al. Band-structure effects in ultra-scaled silicon nanowires. IEEE Trans ED, 2007, 54: 2243–2254
Lundstrom M, Ren Z. Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans ED, 2002, 49: 133–141
Natori K. New solution to high-field transport in semiconductors: I Elastic scattering without energy relaxation. Jpn J Appl Phys, 2009, 48: 034503
Natori K. New solution to high-field transport in semiconductors: II Velocity saturation and ballistic transmission. Jpn J Appl Phys, 2009, 48: 034504
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Iwai, H., Natori, K., Shiraishi, K. et al. Si nanowire FET and its modeling. Sci. China Inf. Sci. 54, 1004–1011 (2011). https://doi.org/10.1007/s11432-011-4220-0
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11432-011-4220-0