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Advanced strain engineering for state-of-the-art nanoscale CMOS technology

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Abstract

The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies.

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Authors and Affiliations

  1. Globalfoundries, 2070 Rt. 52, Hopewell Junction, New York, NY, 12533, USA

    Bin (Frank) Yang

  2. IBM Semiconductor Research & Development Center, 2070 Rt. 52, Hopewell Junction, New York, NY, 12533, USA

    Ming Cai

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  1. Bin (Frank) Yang
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  2. Ming Cai
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Correspondence to Bin (Frank) Yang.

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Yang, B.(., Cai, M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci. China Inf. Sci. 54, 946–958 (2011). https://doi.org/10.1007/s11432-011-4224-9

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