Sorter Design with Structured Low Power Techniques

Abstract

Sorting is a very important function which is widely used in several applications like signal processing and other data center acceleration. Sorting is generally implemented on CPU or GPU, which takes several cycles to finish the sorting process. Further improvement in performance in sorting is possible through hardware acceleration either in FPGA or ASIC. The performance improvement and reducing the power consumption are the primary goals for researchers to improve the hardware acceleration of sorting algorithms. The sorting techniques like Bubble sort, Bitonic sort and Odd–even sort are found suitable for hardware implementation and widely discussed in the research literature. It is evident from the literature survey endeavors from researchers to make these sorting techniques more modular and low power, which is required to design large-scale sorting for data center-based applications. In this paper, we investigate application of generic and structured low-power technique like clock gating and Multi-Vth in designing the low-power sorters. The bubble sort, bitonic sort and odd–even sorting techniques are redesigned to make them low power using clock gating and multi-Vth technique. The implementation results show that the clock gating reduces the dynamic power consumption on sorters by 47.5% without much impact on the performance. Further performance improvement is achieved through adopting multi-Vth libraries without compromising the dynamic power reduction achieved through clock gating. The power reduction results obtained are comparable with state-of-the-art low-power sorters which are complex in design. The proposed sorters are implemented and results are presented for Saed90nm standard cell libraries.