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The 193 [[nanometre|nm]] wavelength was introduced by many (but not all) companies for [[photolithography|lithography]] of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new [[photoresist]]s) were reflected in the high costs associated with this transition.
Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;<ref name="urlNo More Nanometers – EEJournal">{{cite web |url=https://www.eejournal.com/article/no-more-nanometers/ |title=No More Nanometers – EEJournal |date=23 July 2020 |format= }}</ref> neither gate length, metal pitch or gate pitch on a "90nm" device is ninety nanometers.<ref>{{cite web|url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|title=A Brief History of Process Node Evolution|last=Shukla|first=Priyank|website=design-reuse.com|access-date=2019-07-09}}</ref><ref>{{cite web|url=https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|title=14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists...|last=Hruska|first=Joel|website=[[ExtremeTech]]}}</ref><ref>{{cite web|url=https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|title=Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022|website=wccftech.com|date=2016-09-10}}</ref><ref>{{cite web|url=https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|title=Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms|website=eejournal.com|date=2018-03-12}}</ref>
==History==
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Toshiba, Sony and Samsung developed a 90{{nbsp}}nm process during 2001{{ndash}}2002, before being introduced in 2002 for Toshiba's [[eDRAM]] and Samsung's 2{{nbsp}}[[Gibibit|Gb]] [[NAND flash]] memory.<ref>{{cite news |title=Toshiba and Sony Make Major Advances in Semiconductor Process Technologies |url=https://www.toshiba.co.jp/about/press/2002_12/pr0301.htm |access-date=26 June 2019 |work=[[Toshiba]] |date=3 December 2002}}</ref><ref name="samsung2000s">{{cite web |title=Our Proud Heritage from 2000 to 2009 |url=https://www.samsung.com/semiconductor/about-us/history-03/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref> IBM demonstrated a 90{{nbsp}}nm [[silicon-on-insulator]] (SOI) [[CMOS]] process, with development led by Shahidi, in 2002. The same year, Intel demonstrated a 90{{nbsp}}nm [[strained-silicon]] process.<ref>{{cite news |title=IBM, Intel wrangle at 90 nm |url=https://www.eetimes.com/document.asp?doc_id=1145379 |access-date=17 September 2019 |work=[[EE Times]] |date=13 December 2002}}</ref> Fujitsu commercially introduced its 90{{nbsp}}nm process in 2003<ref name="fujitsu">{{Cite web |url=http://www.fujitsu.com/downloads/MICRO/fma/pr/PressKit/65nmProcessTechnology.pdf |title=65nm CMOS Process Technology |access-date=20 June 2019 |archive-date=16 May 2020 |archive-url=https://web.archive.org/web/20200516015827/https://www.fujitsu.com/downloads/MICRO/fma/pr/PressKit/65nmProcessTechnology.pdf |url-status=dead }}</ref> followed by TSMC in 2004.<ref>{{cite web |title=90nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/90nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>
[[Gurtej Sandhu|Gurtej Singh Sandhu]] of Micron Technology initiated the development of [[atomic layer deposition]] high-k [[Thin film|films]] for [[Dynamic random-access memory|DRAM]] memory devices. This helped drive cost-effective implementation of [[semiconductor memory]], starting with 90{{nbsp}}nm [[Semiconductor node|node]] DRAM.<ref name="ieee">{{cite web |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |archive-url=https://web.archive.org/web/20180909112404/https://www.ieee.org/about/awards/bios/grove-recipients.html |url-status=dead |archive-date=9 September 2018 |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=4 July 2019}}</ref>
Intel's 90nm process has a transistor density of 1.45 million transistors per square milimeter (MTr/mm2).<ref>{{cite web | url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3 | title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review }}</ref>
==Example: Elpida 90 nm DDR2 SDRAM process==
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[[Category:International Technology Roadmap for Semiconductors lithography nodes|*00090]]
[[Category:American inventions]]
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