RDNA 3: Difference between revisions

| caption = <!-- A caption for the image -->

| soldby designfirm = [[Advanced Micro Devices|AMD]]

| process = {{ubl |[[TSMC]] [[5 nm process|N4]] (APUs)|[[TSMC]] [[5 nm process|N5]] (GCD)|[[TSMC]] [[7 nm process|N6]] (Navi 33 and MCD)}}

| codename = {{ubl |Navi 31: Plum Bonito |Navi 32: Wheat Nas |Navi 33: Hotpink Bonefish}}

| products-desktop1 = [[Radeon RX 7000 series]]

| compute = {{ubl |Up to 122.8{{nbsp}}TFLOPS (FP16) |Up to 61.42{{nbsp}}TFLOPS (FP32) |Up to 1.919{{nbsp}}TFLOPS (FP64)}}

| l3-cache = up to 96{{nbsp}}MB (16{{nbsp}}MB per MCD)

| memory-clock = 20up to 20&nbsp;Gbps

| successor = [[RDNA 4]]

'''RDNA 3''' is a [[Graphics processing unit|GPU]] microarchitecture designed by [[Advanced Micro Devices|AMD]], released with the [[Radeon]] [[Radeon RX 7000 series|RX 7000 series]] on December 13, 2022. Alongside powering the RX 7000 series, RDNA 3 is also featured in the SoCs designed by AMD for the [[Asus ROG Ally]] and, [[Lenovo Legion|Lenovo Legion Go]], and the [[PlayStation 5|PlayStation 5 Pro]] consoles.

== Architectural detailsArchitecture ==

For the first time ever in a consumer GPU, RDNA 3 utilizes modular [[Multi-chip module|chiplets]] rather than a single large monolithic [[Die (integrated circuit)|die]]. AMD previously had great success with its use of chiplets in its [[Ryzen]] desktop and [[Epyc]] server processors.<ref>{{Cite web |last1=James |first1=Dave |date=June 24, 2022 |title=AMD suggests a Ryzen-like design for RDNA 3 chiplets would be 'a reasonable inference' |url=https://www.pcgamer.com/amd-suggests-a-ryzen-like-chiplet-design-for-rdna-3-gpus-would-be-a-reasonable-inference/ |website=PC Gamer |language=en-US |access-date=April 8, 2023}}</ref> The decision to move to a chiplet-based GPU microarchitecture was led by AMD Senior Vice President [[Sam Naffziger]] who had also lead the chiplet initiative with Ryzen and Epyc.<ref>{{Cite web |last1=Alcorn |first1=Paul |last2=Walton |first2=Jarred |date=June 23, 2022 |title=Into the GPU Chiplet Era: An Interview With AMD's Sam Naffziger |url=https://www.tomshardware.com/features/gpu-chiplet-era-interview-amd-sam-naffziger |website=Tom's Hardware |language=en-US |access-date=April 8, 2023}}</ref> The development of RDNA 3's chiplet architecture began towards the end of 2017 with Naffziger leading the AMD graphics team in the effort.<ref name="Brosdahl">{{Cite web |last1=Brosdahl |first1=Peter |date=November 22, 2022 |title=AMD Lead Engineer Sam Naffziger Explains Advantages of RDNA3 Chiplet Design |url=https://www.thefpsreview.com/2022/11/22/amd-lead-engineer-sam-naffziger-explains-advantages-of-rdna3-chiplet-design/ |website=The FPS Review |language=en-US |access-date=April 8, 2023}}</ref> The benefit of using chiplets is that dies can be [[Semiconductor device fabrication|fabricated]] on different process nodes depending on their functions and intended purpose. According to Naffziger, cache and SRAM do not scale as linearly as logic does on advanced nodes like N5 in terms of density and power consumption so they can instead be fabricated on the cheaper, more mature N6 node. The use of smaller dies rather than one large monolithic die is beneficial for maximizing wafer yields as more dies can be fitted onto a single wafer.<ref name="Brosdahl"/> Alternatively, a large monolithic RDNA 3 die built on N5 would be more expensive to produce with lower yields.

TheRDNA decision3 touses movetwo totypes aof chipletchiplets: the Graphics Compute Die (GCD) and Memory Cache Dies (MCDs). On Ryzen and Epyc processors, AMD used its [[PCI Express|PCIe]]-based GPUInfinity microarchitectureFabric wasprotocol ledwith bythe AMDpackage's Seniordies Viceconnected Presidentvia traces on an organic substrate. This approach is easily scalable in a cost-effective manner but has the drawbacks of increased [[SamLatency Naffziger(engineering)|latency]], whoincreased hadpower alsoconsumption leadwhen themoving chipletdata initiativebetween withdies Ryzenat around 1.5 picojoules per bit, and Epycit cannot achieve the connection density needed for high-bandwidth GPUs.<ref>{{Citecite web |last1=Alcorn |first1=Paul |last2=Walton |first2first1=Jarred |date=June 235, 20222023 |title=IntoAMD theRDNA 3 GPU ChipletArchitecture EraDeep Dive: AnThe InterviewRyzen With AMD'sMoment Samfor NaffzigerGPUs |url=https://www.tomshardware.com/featuresnews/amd-rdna-3-gpu-chipletarchitecture-eradeep-interviewdive-the-ryzen-moment-for-gpus#section-amd-samrdna-3-and-gpu-naffzigerchiplets |website=Tom's Hardware |language=en-US |access-date=April 829, 20232024}}</ref> TheAn developmentorganic ofpackage RDNAcould 3'snot chiplet architecture began towardshost the endnumber of 2017wires withthat Naffzigerwould leadingbe theneeded AMDto graphicsconnect teammultiple dies in thea effortGPU.<ref name="Brosdahl">{{Citecite web |last1=BrosdahlRidley |first1=PeterJacob |date=November 2214, 2022 |title=AMD's LeadInfinity EngineerLinks Samis Naffzigerthe Explainsunsung Advantageshero of RDNA3RDNA Chiplet3 Designand chiplet gaming GPUs |url=https://www.thefpsreviewpcgamer.com/2022/11/22/amd-leadinfinity-engineerlinks-samrdna-naffziger-explains-advantages-of-rdna3-chiplet-design3/ |website=The FPSPC ReviewGamer |language=en-US |access-date=April 829, 20232024}}</ref>

==== ChipletMemory interconnectsCache Dies (MCDs) ====

==== ProcessGraphics nodeCompute Die (GCD) ====

==== RayClock tracingspeeds ====

==== Cache and memory subsystem ====

==== Media engine ====

RDNA 3 is the first RDNA architecture to have a dedicated media engine. It is built into the GCD and is based on [[Video Core Next|VCN 4.0]] encoding and decoding core.<ref>{{cite web |last1=Shilov |first1=Anton |date=May 4, 2022 |title=First Details About AMD’s Next Generation Video Engine Revealed |url=https://www.tomshardware.com/news/next-amd-video-engine-may-lack-av1 |website=Tom's Hardware |language=en-US |access-date=April 10, 2023}}</ref> AMD's AMF [[AV1]] encoder is comparable in quality to Nvidia's [[Nvidia NVENC|NVENC]] AV1 encoder but can handle a higher number of simultaneous encoding streams compared to the limit of 3 on the [[GeForce 40 series|GeForce RTX 40 series]].<ref>{{Cite web |last1=Klotz |first1=Aaron |date=December 12, 2022 |title=AMD's Radeon RX 7900 AV1 encoder is almost on par with Intel Arc and Nvidia's RTX 40 series |url=https://www.techspot.com/news/96945-amd-radeon-rx-7900-av1-encoder-almost-par.html |website=TechSpot |language=en-US |access-date=April 8, 2023}}</ref>

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| 360

| 360

| 360

! style="text-align: left;" | {{midsizeresize|1440p1440p60}}

| 360

| 360

| 360

! style="text-align: left;" | {{midsizeresize|4K4K60}}

! style="text-align: left;" | {{midsizeresize|8K8K60}}

! colspan="3" | Graphics Compute Die <br> (GCD)

! rowspan="2" | Memory Cache Die <br /> (MCD)

! style="width:8em" | [https://www.techpowerup.com/gpu-specs/amd-navi-31.g998 Navi 31]<ref name="Walton" />

! style="width:8em" | [https://www.techpowerup.com/gpu-specs/amd-navi-32.g1000 Navi 32]<ref>https://www.tomshardware.com/news/amd-rdna-3-gpu-architecture-deep-dive-the-ryzen-moment-for-gpus</ref>

! style="text-align: left;" colspan="3" | {{midsizeresize|{{Tooltip|Ref.|Reference(s)}}Launch}}

| {{dts|2023|AugustSeptember|2506|format=my|abbr=on}}

| {{dts|2023|January|404|format=my|abbr=on}}

! style="text-align: left;" colspan="3" | {{midsizeresize|Codename}}

! style="text-align: left;" colspan="3" | {{midsizeresize|Compute units <br/> (Stream processors) <br/> [FP32 cores]}}

! style="text-align: left;" colspan="3" | {{midsizeresize|Process}}

! style="text-align: left;" colspan="3" | {{midsizeresize|Transistors}}

! style="text-align: left;" colspan="3" | {{midsizeresize|Transistor density}}

! style="text-align: left;" colspan="3" | {{midsizeresize|Die size}}

| 200196&nbsp;mm²

! style="text-align: left;" colspan="3" | {{midsizeresize|Max TDP}}

! style="text-align: left;" rowspan="4" | {{midsizeresize|Products}}

! style="text-align: left;" rowspan="2" | {{midsizeresize|Consumer}}

! style="text-align: left;" | {{midsizeresize|Desktop}}

| {{ubl|RX 7600|RX 7600 XT}}

! style="text-align: left;" | {{midsizeresize|Mobile}}

! style="text-align: left;" rowspan="2" | {{midsizeresize|Workstation}}

! style="text-align: left;" | {{midsizeresize|Desktop}}

| {{NAubl|W7700}}

| {{ubl|W7700 (4×)|W7800 (4×)|W7900 (6×)}}

! style="text-align: left;" | {{midsizeresize|Mobile}}

=== DesktopGaming ===

==== Mobile ====

==== Desktop Workstationworkstation ====

=== Integrated graphics processorsprocessing units (iGPsiGPUs) ===

{| class="wikitable" style="text-align: center; font-size: 85%; white-space:nowrap;"

! rowspan="2" | Die <br /> size

! style="width:4em;" | Clock{{efn|name="Boost"}} <br /> ([[Hertz|MHz]])

! style="width:4em;" | [[Half-precision floating-point format|Half]] <br/> [FP16]

! style="width:4em;" | [[Single-precision floating-point format|Single]] <br/> [FP32]

! style="width:4em;" | [[Double-precision floating-point format|Double]] <br/> [FP64]

! style="text-align:left; height:3em;" | {{Nowrap|[https://www.amd.com/en/products/apu/amd-ryzen-5-7540u Radeon 740M]}}

| rowspan="53" | {{dts|2023|April|format=mdy|abbr=on}}

| rowspan="5" | Phoenix<br/>Hawk Point

| rowspan="5" | [[RDNA 3]] <br /> [[TSMC]]{{nbsp}}[[5 nm process|N4]]

| rowspan="2" | 4 CUCUs <br /> 256:16:8:4

| rowspan="2" | 64{{nbsp}}KB

| rowspan="2" | 512{{nbsp}}KB

| 35–54rowspan="2" | 15–65{{nbsp}}W

| 6440.80

| 16,58820.0

| rowspan="2" | 1.5192{{nbsp}}MBKB

| 35–541.5{{nbsp}}WMB

| 9–30192{{nbsp}}WKB

{{efn|name="Core config"|[[Graphics Core Next#Compute units|Compute Units (CUs)]] <br/> [[Unified shader model|UnifiedStream shadersProcessors]] : [[Texture mapping unit|Texture mapping units]]s : [[Render output unit|Render output units]]s : [[Ray tracing (graphics)|Ray accelerators]] and [[Graphics Core Next#Compute units|Compute units (CU)]]}}