Common features of Ryzen 7045 notebook CPUs:
- Socket: FL1.
- All the CPUs support DDR5-5200 in dual-channel mode.
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 1 MB per core.
- All the CPUs support 28 PCIe 5.0 lanes.
- Includes integrated RDNA 2 GPU on the I/O die.
- Fabrication process: TSMC 5 nm FinFET (6 nm FinFET for the I/O die).
Branding and model | CPU | GPU | TDP | Release date | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|
Cores (threads) |
Clock (GHz) | L3 cache (total) |
Chiplets | Core config[a] |
Model | Clock (GHz) | |||||
Base | Boost | ||||||||||
Ryzen 9 | 7945HX3D | 16 (32) | 2.3 | 5.4 | 128 MB[i] | 2 × CCD 1 × I/OD |
2 × 8 | 610M 2 CU |
2.2 | 55–75 W | 17 Jul, 2023 |
7945HX | 2.5 | 64 MB | 28 Feb, 2023 [1] | ||||||||
7845HX | 12 (24) | 3.0 | 5.2 | 2 × 6 | 45–75 W | ||||||
Ryzen 7 | 7745HX | 8 (16) | 3.6 | 5.1 | 32 MB | 1 × CCD 1 × I/OD |
1 × 8 | ||||
Ryzen 5 | 7645HX | 6 (12) | 4.0 | 5.0 | 1 × 6 |
- ^ Core Complexes (CCX) × cores per CCX
- ^ Only one of the two CCXes has additional 64 MB of 3D V-Cache. Only the CCX without 3D V-Cache will be able to reach the maximum boost clocks. The CCX with 3D V-Cache will clock lower.
Template documentation
Common place to discuss layout and style of the AMD APU tables at: Talk:List of AMD accelerated processing units |
You can | .