3 nm process

In semiconductor manufacturing, the 3nm process is the next die shrink after the 5 nm MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. South Korean chipmaker Samsung started shipping its 3 nm gate all around (GAA) process, named 3GAA, in mid-2022. On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its 3 nm semiconductor node (N3) was underway with good yields. An enhanced 3 nm chip process called "N3E" may have started production in 2023. American manufacturer Intel planned to start 3 nm production in 2023.

Samsung's 3 nm process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's 3nm process still uses FinFET (fin field-effect transistor) technology, despite TSMC developing GAAFET transistors. Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor). Intel's process (dubbed "Intel 3", without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography, and power and area improvement.

Projected node properties according to International Roadmap for Devices and Systems (2021)

Node name	Gate pitch	Metal pitch	Year
5 nm	51 nm	30 nm	2020
3 nm	48 nm	24 nm	2022
2 nm	45 nm	20 nm	2025
1 nm	40 nm	16 nm	2027

The term "3 nanometer" has no direct relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3nm node is expected to have a contacted gate pitch of 48 nanometers, and a tightest metal pitch of 24 nanometers.

However, in real world commercial practice, 3nm is used primarily as a marketing term by individual microchip manufacturers (foundries) to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption. There is no industry-wide agreement among different manufacturers about what numbers would define a 3nm node. Typically the chip manufacturer refers to its own previous process node (in this case the 5nm node) for comparison. For example, TSMC has stated that its 3nm FinFET chips will reduce power consumption by 25–30% at the same speed, increase speed by 10–15% at the same amount of power and increase transistor density by about 33% compared to its previous 5 nm FinFET chips. On the other hand, Samsung has stated that its 3nm process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous 5 nm process. EUV lithography faces new challenges at 3 nm which lead to the required use of multipatterning.

History

Research and technology demos

In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes. In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology.

Commercialization history

In late 2016, TSMC announced plans to construct a 5 nm–3 nm node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.

In 2017, TSMC announced it was to begin construction of the 3nm semiconductor fabrication plant at the Tainan Science Park in Taiwan. TSMC plans to start volume production of the 3nm process node in 2023.

In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out 3nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.

In early 2019, Samsung presented plans to manufacture 3nm GAAFET (gate-all-around field-effect transistors) at the 3nm node in 2021, using its own MBCFET transistor structure that uses nanosheets; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with 7 nm. Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm nodes.

In December 2019, Intel announced plans for 3nm production in 2025.

In January 2020, Samsung announced the production of the world's first 3nm GAAFET process prototype, and said that it is targeting mass production in 2021.

In August 2020, TSMC announced details of its "N3" process, which is new rather than being an improvement over its N5 process. Compared with the N5 process, the N3 process should offer a 10–15% (1.10–1.15×) increase in performance, or a 25–35% (1.25–1.35×) decrease in power consumption, with a 1.7× increase in logic density (a scaling factor of 0.58), a 20% increase (0.8 scaling factor) in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC was planning volume production in the second half of 2022.

In July 2021, Intel presented brand new process technology roadmap, according to which Intel 3 process (previously named Intel 7nm), the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, is now scheduled to enter product manufacturing phase in H2 2023.

In October 2021, Samsung adjusted earlier plans and announced that the company is scheduled to start producing its customers' first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023.

In June 2022, at TSMC Technology Symposium, the company shared details of its N3E process technology scheduled for volume production in 2023 H2: 1.6× higher logic transistor density, 1.3× higher chip transistor density, 10-15% higher performance at iso power or 30-35% lower power at iso performance compared to TSMC N5 v1.0 process technology, FinFLEX technology, allowing to intermix libraries with different track heights within a block etc. TSMC also introduced new members of 3nm process family: high-density variant N3S, high-performance variants N3P and N3X, and N3RF for RF applications.

In June 2022, Samsung started "initial" production of a low-power, high-performance chip using 3nm process technology with GAA architecture. According to industry sources, Qualcomm has reserved some of 3nm production capacity from Samsung.

On 25 July 2022, Samsung celebrated the first shipment of 3nm Gate-All-Around chips to a Chinese cryptocurrency mining firm PanSemi. It was revealed that the newly introduced 3 nm MBCFET process technology offers 16% higher transistor density, 23% higher performance or 45% lower power draw compared to an unspecified 5 nm process technology. Goals for the second-generation 3nm process technology include up to 35% higher transistor density, further reduction of power draw by up to 50% or higher performance by 30%.

On 29 December 2022, TSMC announced that volume production using its 3nm process technology N3 is underway with good yields. The company plans to start volume manufacturing using refined 3nm process technology called N3E in the second half of 2023.

In December 2022, at IEDM 2022 conference, TSMC disclosed a few details about their 3nm process technologies: contacted gate pitch of N3 is 45 nm, minimum metal pitch of N3E is 23 nm, and SRAM cell area is 0.0199 μm² for N3 and 0.021 μm² for N3E (same as in N5). For N3E process, depending on the number of fins in cells used for design, area scaling compared to N5 2-2 fin cells ranges from 0.64x to 0.85x, performance gains range from 11% to 32% and energy savings range from 12% to 30% (the numbers refer to Cortex-A72 core). TSMC's FinFlex technology allows to intermix cells with different number of fins in a single chip.

Reporting from IEDM 2022, semiconductor industry expert Dick James stated that TSMC's 3nm processes offered only incremental improvements, because limits have been reached for fin height, gate length, and number of fins per transistor (single fin). After implementation of features such as single diffusion break, contact over active gate and FinFlex, there will be no more room left for improvement of FinFET-based process technologies.

In April 2023, at its Technology Symposium, TSMC revealed some details about their N3P and N3X processes the company had introduced earlier: N3P will offer 5% higher speed or 5%–10% lower power and 1.04× higher "chip density" compared to N3E, while N3X will offer 5% speed gain at the cost of ~3.5× higher leakage and the same density compared to N3P. N3P is scheduled to enter volume production in the second half of 2024, and N3X will follow in 2025.

In July 2023, semiconductor industry research firm TechInsights said it has found that Samsung's 3 nm GAA (gate-all-around) process has been incorporated into the crypto miner ASIC (Whatsminer M56S++) from a Chinese manufacturer, MicroBT.

On 7 September 2023, MediaTek and TSMC announced that MediaTek have developed their first 3nm chip, volume production is expected to commence in 2024.

3 nm process nodes

	Samsung		TSMC				Intel
Process name	3GAE SF3E	3GAP SF3	N3 (a.k.a. N3B)	N3E	N3P	N3X	3
Transistor type	MBCFET		FinFET
Transistor density	150 μm−2	190 μm−2	197 μm−2	216 μm−2	224 μm−2		Un­known
SRAM bit-cell size	Un­known	Un­known	0.0199 μm2	0.021 μm2	Un­known	Un­known	Un­known
Transistor gate pitch	40 nm	Un­known	45 nm	48 nm	Un­known	Un­known	50 nm
Interconnect pitch	32 nm	Un­known	Un­known	23 nm	Un­known	Un­known	30 nm
Release status	2022 risk production 2022 production 2022 shipping	2024 Q1 risk production 2024 H2 production	2021 risk production 2022 H2 volume production 2023 H1 shipping for revenue	2023 H2 production	2024 H2 production	2025 production	2024 H1 product manufacturing 2024 H2 shipping for revenue

Further reading

• Lapedus, Mark (21 June 2018), "Big Trouble At 3nm", semiengineering.com
• Bae, Geumjong; Bae, D.-I.; Kang, M.; Hwang, S.M.; Kim, S.S.; Seo, B.; Kwon, T.Y.; Lee, T.J.; Moon, C.; Choi, Y.M.; Oikawa, K.; Masuoka, S.; Chun, K.Y.; Park, S.H.; Shin, H.J.; Kim, J.C.; Bhuwalka, K.K.; Kim, D.H.; Kim, W.J.; Yoo, J.; Jeon, H.Y.; Yang, M.S.; Chung, S.-J.; Kim, D.; Ham, B.H.; Park, K.J.; Kim, W.D.; Park, S.H.; Song, G.; et al. (December 2018). 3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications. 2018 IEEE International Electron Devices Meeting (IEDM). pp. 28.7.1–28.7.4. doi:10.1109/IEDM.2018.8614629. ISBN 978-1-7281-1987-8. S2CID 58673284.

External links

• 3 nm lithography process

Preceded by 5 nm (FinFET)

MOSFET semiconductor device fabrication process

Succeeded by 2 nm (GAAFET)