diff --git a/.github/workflows/MarkdwonLinksCheck.yml b/.github/workflows/MarkdwonLinksCheck.yml
index 5525a3050d..5f2220b8ad 100644
--- a/.github/workflows/MarkdwonLinksCheck.yml
+++ b/.github/workflows/MarkdwonLinksCheck.yml
@@ -11,6 +11,9 @@ on:
- '**.md'
# Allows you to run this workflow manually from the Actions tab
workflow_dispatch:
+ schedule:
+ # Run every day at 12 AM UTC to check url.
+ - cron: "0 11 * * *"
jobs:
linkinator:
runs-on: ubuntu-latest
diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json
index c47e35a460..7cdc1022ca 100644
--- a/CI/build/conf/cores_config.json
+++ b/CI/build/conf/cores_config.json
@@ -760,6 +760,7 @@
"GENERIC_L412K8UX",
"GENERIC_L412KBTX",
"GENERIC_L412KBUX",
+ "GENERIC_L412RBIXP",
"GENERIC_L422KBTX",
"GENERIC_L431CBTX",
"GENERIC_L431CBUX",
@@ -823,6 +824,8 @@
"GENERIC_L4S5VITX",
"GENERIC_L4S5ZITX",
"GENERIC_L4S5ZIYX",
+ "GENERIC_L552QCIXQ",
+ "GENERIC_L552QEIXQ",
"GENERIC_L552ZCTXQ",
"GENERIC_L552ZETXQ",
"GENERIC_MP153AACX",
diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json
index 8dff66d592..267c32f85c 100644
--- a/CI/build/conf/cores_config_ci.json
+++ b/CI/build/conf/cores_config_ci.json
@@ -760,6 +760,7 @@
"GENERIC_L412K8UX",
"GENERIC_L412KBTX",
"GENERIC_L412KBUX",
+ "GENERIC_L412RBIXP",
"GENERIC_L422KBTX",
"GENERIC_L431CBTX",
"GENERIC_L431CBUX",
@@ -823,6 +824,8 @@
"GENERIC_L4S5VITX",
"GENERIC_L4S5ZITX",
"GENERIC_L4S5ZIYX",
+ "GENERIC_L552QCIXQ",
+ "GENERIC_L552QEIXQ",
"GENERIC_L552ZCTXQ",
"GENERIC_L552ZETXQ",
"GENERIC_MP153AACX",
diff --git a/README.md b/README.md
index f8b7b0bd73..70b2e3275a 100644
--- a/README.md
+++ b/README.md
@@ -136,6 +136,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F302R8 | [Nucleo F302R8](http://www.st.com/en/evaluation-tools/nucleo-f302r8.html) | *1.1.0* | |
| :green_heart: | STM32F303RE | [Nucleo F303RE](http://www.st.com/en/evaluation-tools/nucleo-f303re.html) | *0.1.0* | |
| :green_heart: | STM32F401RE | [Nucleo F401RE](http://www.st.com/en/evaluation-tools/nucleo-f401re.html) | *0.2.1* | |
+| :yellow_heart: | STM32F410RB | [Nucleo F410RB](http://www.st.com/en/evaluation-tools/nucleo-f410rb.html) | **2.11.0** | |
| :green_heart: | STM32F411RE | [Nucleo F411RE](http://www.st.com/en/evaluation-tools/nucleo-f411re.html) | *0.2.1* | |
| :green_heart: | STM32F446RE | [Nucleo F446RE](http://www.st.com/en/evaluation-tools/nucleo-f446re.html) | *1.1.1* | |
| :green_heart: | STM32G070RB | [Nucleo G070RB](https://www.st.com/en/evaluation-tools/nucleo-g070rb.html) | *2.3.0* | |
@@ -148,6 +149,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32L053R8 | [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) | *0.1.0* | |
| :green_heart: | STM32L073RZ | [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) | *1.4.0* | |
| :green_heart: | STM32L152RE | [Nucleo L152RE](http://www.st.com/en/evaluation-tools/nucleo-l152re.html) | *1.0.0* | |
+| :yellow_heart: | STM32L412RB-P | [Nucleo L412RC-P](https://www.st.com/en/evaluation-tools/nucleo-l412rb-p.html) | **2.11.0** | |
| :green_heart: | STM32L433RC-P | [Nucleo L433RC-P](https://www.st.com/en/evaluation-tools/nucleo-l433rc-p.html) | *1.9.0* | |
| :green_heart: | STM32L452RE | [Nucleo L452RE](http://www.st.com/en/evaluation-tools/nucleo-l452re.html) | *1.5.0* | |
| :green_heart: | STM32L452RE-P | [Nucleo L452RE-P](http://www.st.com/en/evaluation-tools/nucleo-l452re-p.html) | *1.8.0* | |
@@ -704,6 +706,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| Status | Device(s) | Name | Release | Notes |
| :----: | :-------: | ---- | :-----: | :---- |
| :green_heart: | STM32L412K8
STM32L412KB
STM32L422KB | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L412RBIxP
STM32L412RBTxP | Generic Board | **2.11.0** | |
| :green_heart: | STM32L431CB
STM32L431CC | Generic Board | *2.8.1* | |
| :green_heart: | STM32L431RB
STM32L431RC | Generic Board | *2.3.0* | |
| :green_heart: | STM32L432KB
STM32L432KC
STM32L442KC | Generic Board | *2.0.0* | |
@@ -818,7 +821,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F446VE | [RUMBA32](https://github.com/Aus3D/RUMBA32) | *1.5.0* | |
| :green_heart: | STM32F401VE | [STEVAL-3DP001V1](https://www.st.com/en/evaluation-tools/steval-3dp001v1.html) | *1.6.0* | |
| :green_heart: | STM32F446RE | VAkE v1.0 | *1.6.0* | |
-| :green_heart: | STM32F446VE | [FYSETC_S6](https://wiki.fysetc.com/FYSETC_S6/) | *1.9.0* | |
+| :green_heart: | STM32F446VE | [FYSETC_S6](https://wiki.fysetc.com/docs/FYSETCS6) | *1.9.0* | |
| :green_heart: | STM32G0B1CB | [BTT EBB42 CAN V1.1](https://github.com/bigtreetech/EBB/tree/master) | *2.4.0* | |
### [Blues](https://blues.com/) boards
diff --git a/boards.txt b/boards.txt
index aaebef7be9..737597a70c 100644
--- a/boards.txt
+++ b/boards.txt
@@ -586,6 +586,21 @@ Nucleo_64.menu.pnum.NUCLEO_F401RE.build.variant=STM32F4xx/F401R(B-C-D-E)T
Nucleo_64.menu.pnum.NUCLEO_F401RE.openocd.target=stm32f4x
Nucleo_64.menu.pnum.NUCLEO_F401RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F401.svd
+# NUCLEO_F410RB board
+Nucleo_64.menu.pnum.NUCLEO_F410RB=Nucleo F410RB
+Nucleo_64.menu.pnum.NUCLEO_F410RB.node="NOD_F410RB,NUCLEO"
+Nucleo_64.menu.pnum.NUCLEO_F410RB.upload.maximum_size=131072
+Nucleo_64.menu.pnum.NUCLEO_F410RB.upload.maximum_data_size=32768
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.mcu=cortex-m4
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.fpu=-mfpu=fpv4-sp-d16
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.float-abi=-mfloat-abi=hard
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.board=NUCLEO_F410RB
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.series=STM32F4xx
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.product_line=STM32F410Rx
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.variant=STM32F4xx/F410R(8-B)(I-T)
+Nucleo_64.menu.pnum.NUCLEO_F410RB.openocd.target=stm32f4x
+Nucleo_64.menu.pnum.NUCLEO_F410RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F410.svd
+
# NUCLEO_F411RE board
Nucleo_64.menu.pnum.NUCLEO_F411RE=Nucleo F411RE
Nucleo_64.menu.pnum.NUCLEO_F411RE.node="NODE_F411RE,NUCLEO"
@@ -758,6 +773,21 @@ Nucleo_64.menu.pnum.NUCLEO_L152RE.build.variant=STM32L1xx/L151RET_L152RET_L162RE
Nucleo_64.menu.pnum.NUCLEO_L152RE.openocd.target=stm32l1
Nucleo_64.menu.pnum.NUCLEO_L152RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd
+# NUCLEO_L412RB_P board
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P=Nucleo L412RB-P
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.node=NODE_L412RB
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.upload.maximum_size=131072
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.upload.maximum_data_size=40960
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.mcu=cortex-m4
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.fpu=-mfpu=fpv4-sp-d16
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.float-abi=-mfloat-abi=hard
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.board=NUCLEO_L412RB_P
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.series=STM32L4xx
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.product_line=STM32L412xx
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.variant=STM32L4xx/L412RB(I-T)xP
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.openocd.target=stm32l4x
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd
+
# NUCLEO_L433RC_P board
Nucleo_64.menu.pnum.NUCLEO_L433RC_P=Nucleo L433RC-P
Nucleo_64.menu.pnum.NUCLEO_L433RC_P.node=NODE_L433RC
@@ -11471,6 +11501,24 @@ GenL4.menu.pnum.GENERIC_L412KBUX.build.product_line=STM32L412xx
GenL4.menu.pnum.GENERIC_L412KBUX.build.variant=STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)
GenL4.menu.pnum.GENERIC_L412KBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd
+# Generic L412RBIxP
+GenL4.menu.pnum.GENERIC_L412RBIXP=Generic L412RBIxP
+GenL4.menu.pnum.GENERIC_L412RBIXP.upload.maximum_size=131072
+GenL4.menu.pnum.GENERIC_L412RBIXP.upload.maximum_data_size=40960
+GenL4.menu.pnum.GENERIC_L412RBIXP.build.board=GENERIC_L412RBIXP
+GenL4.menu.pnum.GENERIC_L412RBIXP.build.product_line=STM32L412xx
+GenL4.menu.pnum.GENERIC_L412RBIXP.build.variant=STM32L4xx/L412RB(I-T)xP
+GenL4.menu.pnum.GENERIC_L412RBIXP.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd
+
+# Generic L412RBTxP
+GenL4.menu.pnum.GENERIC_L412RBTXP=Generic L412RBTxP
+GenL4.menu.pnum.GENERIC_L412RBTXP.upload.maximum_size=131072
+GenL4.menu.pnum.GENERIC_L412RBTXP.upload.maximum_data_size=40960
+GenL4.menu.pnum.GENERIC_L412RBTXP.build.board=GENERIC_L412RBTXP
+GenL4.menu.pnum.GENERIC_L412RBTXP.build.product_line=STM32L412xx
+GenL4.menu.pnum.GENERIC_L412RBTXP.build.variant=STM32L4xx/L412RB(I-T)xP
+GenL4.menu.pnum.GENERIC_L412RBTXP.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd
+
# Generic L422KBTx
GenL4.menu.pnum.GENERIC_L422KBTX=Generic L422KBTx
GenL4.menu.pnum.GENERIC_L422KBTX.upload.maximum_size=131072
diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
index 24a946c9dd..ea28c93087 100644
--- a/cmake/boards_db.cmake
+++ b/cmake/boards_db.cmake
@@ -93548,6 +93548,170 @@ target_compile_options(GENERIC_L412KBUX_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# GENERIC_L412RBIXP
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L412RBIXP_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L412RB(I-T)xP")
+set(GENERIC_L412RBIXP_MAXSIZE 131072)
+set(GENERIC_L412RBIXP_MAXDATASIZE 40960)
+set(GENERIC_L412RBIXP_MCU cortex-m4)
+set(GENERIC_L412RBIXP_FPCONF "-")
+add_library(GENERIC_L412RBIXP INTERFACE)
+target_compile_options(GENERIC_L412RBIXP INTERFACE
+ "SHELL:-DSTM32L412xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L412RBIXP_MCU}
+)
+target_compile_definitions(GENERIC_L412RBIXP INTERFACE
+ "STM32L4xx"
+ "ARDUINO_GENERIC_L412RBIXP"
+ "BOARD_NAME=\"GENERIC_L412RBIXP\""
+ "BOARD_ID=GENERIC_L412RBIXP"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L412RBIXP INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/
+ ${GENERIC_L412RBIXP_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L412RBIXP INTERFACE
+ "LINKER:--default-script=${GENERIC_L412RBIXP_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=131072"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=40960"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L412RBIXP_MCU}
+)
+
+add_library(GENERIC_L412RBIXP_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBIXP_serial_generic INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L412RBIXP_serial_none INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L412RBIXP_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L412RBIXP_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L412RBIXP_usb_HID INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L412RBIXP_usb_none INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBIXP_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBIXP_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L412RBIXP_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_L412RBTXP
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L412RBTXP_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L412RB(I-T)xP")
+set(GENERIC_L412RBTXP_MAXSIZE 131072)
+set(GENERIC_L412RBTXP_MAXDATASIZE 40960)
+set(GENERIC_L412RBTXP_MCU cortex-m4)
+set(GENERIC_L412RBTXP_FPCONF "-")
+add_library(GENERIC_L412RBTXP INTERFACE)
+target_compile_options(GENERIC_L412RBTXP INTERFACE
+ "SHELL:-DSTM32L412xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L412RBTXP_MCU}
+)
+target_compile_definitions(GENERIC_L412RBTXP INTERFACE
+ "STM32L4xx"
+ "ARDUINO_GENERIC_L412RBTXP"
+ "BOARD_NAME=\"GENERIC_L412RBTXP\""
+ "BOARD_ID=GENERIC_L412RBTXP"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L412RBTXP INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/
+ ${GENERIC_L412RBTXP_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L412RBTXP INTERFACE
+ "LINKER:--default-script=${GENERIC_L412RBTXP_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=131072"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=40960"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L412RBTXP_MCU}
+)
+
+add_library(GENERIC_L412RBTXP_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBTXP_serial_generic INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L412RBTXP_serial_none INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L412RBTXP_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L412RBTXP_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L412RBTXP_usb_HID INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L412RBTXP_usb_none INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBTXP_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBTXP_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L412RBTXP_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# GENERIC_L422KBTX
# -----------------------------------------------------------------------------
@@ -100108,6 +100272,170 @@ target_compile_options(GENERIC_L4S9ZIYX_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# GENERIC_L552QCIXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L552QCIXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ")
+set(GENERIC_L552QCIXQ_MAXSIZE 262144)
+set(GENERIC_L552QCIXQ_MAXDATASIZE 262144)
+set(GENERIC_L552QCIXQ_MCU cortex-m33)
+set(GENERIC_L552QCIXQ_FPCONF "-")
+add_library(GENERIC_L552QCIXQ INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ INTERFACE
+ "SHELL:-DSTM32L552xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L552QCIXQ_MCU}
+)
+target_compile_definitions(GENERIC_L552QCIXQ INTERFACE
+ "STM32L5xx"
+ "ARDUINO_GENERIC_L552QCIXQ"
+ "BOARD_NAME=\"GENERIC_L552QCIXQ\""
+ "BOARD_ID=GENERIC_L552QCIXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L552QCIXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/
+ ${GENERIC_L552QCIXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L552QCIXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_L552QCIXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=262144"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L552QCIXQ_MCU}
+)
+
+add_library(GENERIC_L552QCIXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QCIXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L552QCIXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L552QCIXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L552QCIXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L552QCIXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L552QCIXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QCIXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QCIXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L552QCIXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_L552QEIXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L552QEIXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ")
+set(GENERIC_L552QEIXQ_MAXSIZE 524288)
+set(GENERIC_L552QEIXQ_MAXDATASIZE 262144)
+set(GENERIC_L552QEIXQ_MCU cortex-m33)
+set(GENERIC_L552QEIXQ_FPCONF "-")
+add_library(GENERIC_L552QEIXQ INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ INTERFACE
+ "SHELL:-DSTM32L552xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L552QEIXQ_MCU}
+)
+target_compile_definitions(GENERIC_L552QEIXQ INTERFACE
+ "STM32L5xx"
+ "ARDUINO_GENERIC_L552QEIXQ"
+ "BOARD_NAME=\"GENERIC_L552QEIXQ\""
+ "BOARD_ID=GENERIC_L552QEIXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L552QEIXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/
+ ${GENERIC_L552QEIXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L552QEIXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_L552QEIXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=524288"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L552QEIXQ_MCU}
+)
+
+add_library(GENERIC_L552QEIXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QEIXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L552QEIXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L552QEIXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L552QEIXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L552QEIXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L552QEIXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QEIXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QEIXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L552QEIXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# GENERIC_L552ZCTXQ
# -----------------------------------------------------------------------------
@@ -100272,6 +100600,88 @@ target_compile_options(GENERIC_L552ZETXQ_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# GENERIC_L562QEIXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L562QEIXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ")
+set(GENERIC_L562QEIXQ_MAXSIZE 524288)
+set(GENERIC_L562QEIXQ_MAXDATASIZE 196608)
+set(GENERIC_L562QEIXQ_MCU cortex-m33)
+set(GENERIC_L562QEIXQ_FPCONF "-")
+add_library(GENERIC_L562QEIXQ INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ INTERFACE
+ "SHELL:-DSTM32L562xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L562QEIXQ_MCU}
+)
+target_compile_definitions(GENERIC_L562QEIXQ INTERFACE
+ "STM32L5xx"
+ "ARDUINO_GENERIC_L562QEIXQ"
+ "BOARD_NAME=\"GENERIC_L562QEIXQ\""
+ "BOARD_ID=GENERIC_L562QEIXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L562QEIXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/
+ ${GENERIC_L562QEIXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L562QEIXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_L562QEIXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=524288"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L562QEIXQ_MCU}
+)
+
+add_library(GENERIC_L562QEIXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L562QEIXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L562QEIXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L562QEIXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L562QEIXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L562QEIXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L562QEIXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L562QEIXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L562QEIXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L562QEIXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# GENERIC_L562ZETXQ
# -----------------------------------------------------------------------------
@@ -106718,6 +107128,88 @@ target_compile_options(NUCLEO_F401RE_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# NUCLEO_F410RB
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_F410RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F4xx/F410R(8-B)(I-T)")
+set(NUCLEO_F410RB_MAXSIZE 131072)
+set(NUCLEO_F410RB_MAXDATASIZE 32768)
+set(NUCLEO_F410RB_MCU cortex-m4)
+set(NUCLEO_F410RB_FPCONF "fpv4-sp-d16-hard")
+add_library(NUCLEO_F410RB INTERFACE)
+target_compile_options(NUCLEO_F410RB INTERFACE
+ "SHELL:-DSTM32F410Rx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_F410RB_MCU}
+)
+target_compile_definitions(NUCLEO_F410RB INTERFACE
+ "STM32F4xx"
+ "ARDUINO_NUCLEO_F410RB"
+ "BOARD_NAME=\"NUCLEO_F410RB\""
+ "BOARD_ID=NUCLEO_F410RB"
+ "VARIANT_H=\"variant_NUCLEO_F410RB.h\""
+)
+target_include_directories(NUCLEO_F410RB INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F4xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/
+ ${NUCLEO_F410RB_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_F410RB INTERFACE
+ "LINKER:--default-script=${NUCLEO_F410RB_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=131072"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_F410RB_MCU}
+)
+
+add_library(NUCLEO_F410RB_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_F410RB_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_F410RB_serial_generic INTERFACE)
+target_compile_options(NUCLEO_F410RB_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_F410RB_serial_none INTERFACE)
+target_compile_options(NUCLEO_F410RB_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_F410RB_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_F410RB_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_F410RB_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_F410RB_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_F410RB_usb_HID INTERFACE)
+target_compile_options(NUCLEO_F410RB_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_F410RB_usb_none INTERFACE)
+target_compile_options(NUCLEO_F410RB_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_F410RB_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_F410RB_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_F410RB_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_F410RB_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_F410RB_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_F410RB_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# NUCLEO_F411RE
# -----------------------------------------------------------------------------
@@ -109260,6 +109752,88 @@ target_compile_options(NUCLEO_L412KB_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# NUCLEO_L412RB_P
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_L412RB_P_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L412RB(I-T)xP")
+set(NUCLEO_L412RB_P_MAXSIZE 131072)
+set(NUCLEO_L412RB_P_MAXDATASIZE 40960)
+set(NUCLEO_L412RB_P_MCU cortex-m4)
+set(NUCLEO_L412RB_P_FPCONF "fpv4-sp-d16-hard")
+add_library(NUCLEO_L412RB_P INTERFACE)
+target_compile_options(NUCLEO_L412RB_P INTERFACE
+ "SHELL:-DSTM32L412xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_L412RB_P_MCU}
+)
+target_compile_definitions(NUCLEO_L412RB_P INTERFACE
+ "STM32L4xx"
+ "ARDUINO_NUCLEO_L412RB_P"
+ "BOARD_NAME=\"NUCLEO_L412RB_P\""
+ "BOARD_ID=NUCLEO_L412RB_P"
+ "VARIANT_H=\"variant_NUCLEO_L412RB_P.h\""
+)
+target_include_directories(NUCLEO_L412RB_P INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/
+ ${NUCLEO_L412RB_P_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_L412RB_P INTERFACE
+ "LINKER:--default-script=${NUCLEO_L412RB_P_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=131072"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=40960"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_L412RB_P_MCU}
+)
+
+add_library(NUCLEO_L412RB_P_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_L412RB_P_serial_generic INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_L412RB_P_serial_none INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_L412RB_P_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_L412RB_P_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_L412RB_P_usb_HID INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_L412RB_P_usb_none INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_L412RB_P_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_L412RB_P_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_L412RB_P_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# NUCLEO_L432KC
# -----------------------------------------------------------------------------
@@ -112664,6 +113238,88 @@ target_compile_options(STM32H747I_DISCO_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# STM32L562E_DK
+# -----------------------------------------------------------------------------
+
+set(STM32L562E_DK_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ")
+set(STM32L562E_DK_MAXSIZE 524288)
+set(STM32L562E_DK_MAXDATASIZE 196608)
+set(STM32L562E_DK_MCU cortex-m33)
+set(STM32L562E_DK_FPCONF "fpv4-sp-d16-hard")
+add_library(STM32L562E_DK INTERFACE)
+target_compile_options(STM32L562E_DK INTERFACE
+ "SHELL:-DSTM32L562xx "
+ "SHELL:-DCUSTOM_PERIPHERAL_PINS"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${STM32L562E_DK_MCU}
+)
+target_compile_definitions(STM32L562E_DK INTERFACE
+ "STM32L5xx"
+ "ARDUINO_STM32L562E_DK"
+ "BOARD_NAME=\"STM32L562E_DK\""
+ "BOARD_ID=STM32L562E_DK"
+ "VARIANT_H=\"variant_STM32L562E_DK.h\""
+)
+target_include_directories(STM32L562E_DK INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/
+ ${STM32L562E_DK_VARIANT_PATH}
+)
+
+target_link_options(STM32L562E_DK INTERFACE
+ "LINKER:--default-script=${STM32L562E_DK_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=524288"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${STM32L562E_DK_MCU}
+)
+
+add_library(STM32L562E_DK_serial_disabled INTERFACE)
+target_compile_options(STM32L562E_DK_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(STM32L562E_DK_serial_generic INTERFACE)
+target_compile_options(STM32L562E_DK_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(STM32L562E_DK_serial_none INTERFACE)
+target_compile_options(STM32L562E_DK_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(STM32L562E_DK_usb_CDC INTERFACE)
+target_compile_options(STM32L562E_DK_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(STM32L562E_DK_usb_CDCgen INTERFACE)
+target_compile_options(STM32L562E_DK_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(STM32L562E_DK_usb_HID INTERFACE)
+target_compile_options(STM32L562E_DK_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(STM32L562E_DK_usb_none INTERFACE)
+target_compile_options(STM32L562E_DK_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(STM32L562E_DK_xusb_FS INTERFACE)
+target_compile_options(STM32L562E_DK_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(STM32L562E_DK_xusb_HS INTERFACE)
+target_compile_options(STM32L562E_DK_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(STM32L562E_DK_xusb_HSFS INTERFACE)
+target_compile_options(STM32L562E_DK_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# STM32MP157A_DK1
# -----------------------------------------------------------------------------
diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp
index 4dd8fd02a4..cde5cab7e0 100644
--- a/cores/arduino/HardwareSerial.cpp
+++ b/cores/arduino/HardwareSerial.cpp
@@ -446,13 +446,17 @@ void HardwareSerial::begin(unsigned long baud, byte config)
break;
}
- uart_init(&_serial, (uint32_t)baud, databits, parity, stopbits, _rx_invert, _tx_invert, _data_invert);
- enableHalfDuplexRx();
- uart_attach_rx_callback(&_serial, _rx_complete_irq);
+ _ready = uart_init(&_serial, (uint32_t)baud, databits, parity, stopbits, _rx_invert, _tx_invert, _data_invert);
+ if (_ready) {
+ enableHalfDuplexRx();
+ uart_attach_rx_callback(&_serial, _rx_complete_irq);
+ }
}
void HardwareSerial::end()
{
+ _ready = false;
+
// wait for transmission of outgoing data
flush(TX_TIMEOUT);
diff --git a/cores/arduino/HardwareSerial.h b/cores/arduino/HardwareSerial.h
index 3ed29a873d..be670e9540 100644
--- a/cores/arduino/HardwareSerial.h
+++ b/cores/arduino/HardwareSerial.h
@@ -146,7 +146,7 @@ class HardwareSerial : public Stream {
using Print::write; // pull in write(str) from Print
operator bool()
{
- return true;
+ return _ready;
}
void setRx(uint32_t _rx);
@@ -189,6 +189,7 @@ class HardwareSerial : public Stream {
#endif // HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY
private:
+ bool _ready;
bool _rx_enabled;
uint8_t _config;
unsigned long _baud;
diff --git a/libraries/SrcWrapper/inc/uart.h b/libraries/SrcWrapper/inc/uart.h
index 7f99d498e7..5d681407f8 100644
--- a/libraries/SrcWrapper/inc/uart.h
+++ b/libraries/SrcWrapper/inc/uart.h
@@ -255,7 +255,7 @@ struct serial_s {
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
-void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert);
+bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert);
void uart_deinit(serial_t *obj);
#if defined(HAL_PWR_MODULE_ENABLED) && (defined(UART_IT_WUF) || defined(LPUART1_BASE))
void uart_config_lowpower(serial_t *obj);
diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c
index 4aaa3f0e2e..d854061655 100644
--- a/libraries/SrcWrapper/src/stm32/uart.c
+++ b/libraries/SrcWrapper/src/stm32/uart.c
@@ -113,12 +113,12 @@ serial_t *get_serial_obj(UART_HandleTypeDef *huart)
/**
* @brief Function called to initialize the uart interface
* @param obj : pointer to serial_t structure
- * @retval None
+ * @retval boolean status
*/
-void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert)
+bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert)
{
if (obj == NULL) {
- return;
+ return false;
}
UART_HandleTypeDef *huart = &(obj->handle);
@@ -143,28 +143,28 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] Tx pin has no peripheral!\n");
}
- return;
+ return false;
}
/* Pin Rx must not be NP if not half-duplex */
if ((obj->pin_rx != NC) && (uart_rx == NP) && (uart_rx_swap == NP)) {
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] Rx pin has no peripheral!\n");
}
- return;
+ return false;
}
/* Pin RTS must not be NP if flow control is enabled */
if ((obj->pin_rts != NC) && (uart_rts == NP)) {
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] RTS pin has no peripheral!\n");
}
- return;
+ return false;
}
/* Pin CTS must not be NP if flow control is enabled */
if ((obj->pin_cts != NC) && (uart_cts == NP)) {
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] CTS pin has no peripheral!\n");
}
- return;
+ return false;
}
/*
@@ -184,7 +184,7 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] Rx/Tx/RTS/CTS pins peripherals mismatch!\n");
}
- return;
+ return false;
}
/* Enable USART clock */
@@ -364,6 +364,12 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
obj->irq = UART12_IRQn;
}
#endif
+ else {
+ if (obj != &serial_debug) {
+ core_debug("ERROR: [U(S)ART] Peripheral not supported!\n");
+ }
+ return false;
+ }
/* Configure UART GPIO pins */
#if defined(UART_ADVFEATURE_SWAP_INIT)
uint32_t pin_swap = UART_ADVFEATURE_SWAP_DISABLE;
@@ -432,6 +438,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
huart->AdvancedInit.DataInvert = UART_ADVFEATURE_DATAINV_ENABLE;
}
#endif
+#else /* UART_ADVFEATURE_NO_INIT */
+ UNUSED(rx_invert);
+ UNUSED(tx_invert);
+ UNUSED(data_invert);
#endif
#ifdef UART_ONE_BIT_SAMPLE_DISABLE
huart->Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
@@ -468,10 +478,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
/* Trying default LPUART clock source */
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) == HAL_OK) {
- return;
+ return true;
}
} else if (HAL_UART_Init(huart) == HAL_OK) {
- return;
+ return true;
}
/* Trying to change LPUART clock source */
/* If baudrate is lower than or equal to 9600 try to change to LSE */
@@ -494,10 +504,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
#endif
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) == HAL_OK) {
- return;
+ return true;
}
} else if (HAL_UART_Init(huart) == HAL_OK) {
- return;
+ return true;
}
}
}
@@ -517,10 +527,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
#endif
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) == HAL_OK) {
- return;
+ return true;
}
} else if (HAL_UART_Init(huart) == HAL_OK) {
- return;
+ return true;
}
}
if (obj->uart == LPUART1) {
@@ -544,10 +554,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
#endif
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) == HAL_OK) {
- return;
+ return true;
}
} else if (HAL_UART_Init(huart) == HAL_OK) {
- return;
+ return true;
}
#if defined(RCC_LPUART1CLKSOURCE_SYSCLK)
if (obj->uart == LPUART1) {
@@ -569,11 +579,12 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) != HAL_OK) {
- return;
+ return false;
}
} else if (HAL_UART_Init(huart) != HAL_OK) {
- return;
+ return false;
}
+ return true;
}
/**
@@ -821,10 +832,11 @@ void uart_config_lowpower(serial_t *obj)
* @note Call only if debug U(S)ART peripheral is not already initialized
* by a Serial instance
* Default config: 8N1
- * @retval None
+ * @retval boolean status
*/
-void uart_debug_init(void)
+bool uart_debug_init(void)
{
+ bool status = false;
if (DEBUG_UART != NP) {
#if defined(DEBUG_PINNAME_TX)
serial_debug.pin_tx = DEBUG_PINNAME_TX;
@@ -832,8 +844,9 @@ void uart_debug_init(void)
serial_debug.pin_tx = pinmap_pin(DEBUG_UART, PinMap_UART_TX);
#endif
/* serial_debug.pin_rx set by default to NC to configure in half duplex mode */
- uart_init(&serial_debug, DEBUG_UART_BAUDRATE, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1, false, false, false);
+ status = uart_init(&serial_debug, DEBUG_UART_BAUDRATE, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1, false, false, false);
}
+ return status;
}
/**
@@ -863,8 +876,7 @@ size_t uart_debug_write(uint8_t *data, uint32_t size)
if (serial_debug.index >= UART_NUM) {
/* DEBUG_UART not initialized */
- uart_debug_init();
- if (serial_debug.index >= UART_NUM) {
+ if (!uart_debug_init()) {
return 0;
}
}
diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt b/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt
index 2a4d55b6b1..14f4ef4bc2 100644
--- a/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt
+++ b/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt
@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
generic_clock.c
PeripheralPins.c
variant_generic.cpp
+ variant_NUCLEO_F410RB.cpp
)
target_link_libraries(variant_bin PUBLIC variant_usage)
diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp
new file mode 100644
index 0000000000..18c8d1d098
--- /dev/null
+++ b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp
@@ -0,0 +1,150 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2025, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_F410RB)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PA_3,
+ PA_2,
+ PA_10,
+ PB_3,
+ PB_5,
+ PB_4,
+ PB_10,
+ PA_8,
+ PA_9,
+ PC_7,
+ PB_6,
+ PA_7,
+ PA_6,
+ PA_5,
+ PB_9,
+ PB_8,
+ // ST Morpho
+ // CN7 Left Side
+ PC_10,
+ PC_12,
+ NC, //D18 - BOOT0
+ PA_13,
+ PA_14,
+ PA_15,
+ PB_7,
+ PC_13,
+ PC_14,
+ PC_15,
+ PH_0,
+ PH_1,
+ PC_2,
+ PC_3,
+ // CN7 Right Side
+ PC_11,
+ PB_11,
+ // CN10 Left Side
+ PC_9,
+ // CN10 Right side
+ PC_8,
+ PC_6,
+ PC_5,
+ PA_12,
+ PA_11,
+ PB_12,
+ NC, //D39
+ PB_2,
+ PB_1,
+ PB_15,
+ PB_14,
+ PB_13,
+ PC_4,
+ PA_0,
+ PA_1,
+ PA_4,
+ PB_0,
+ PC_1,
+ PC_0
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 46, //A0
+ 47, //A1
+ 48, //A2
+ 49, //A3
+ 50, //A4
+ 51, //A5
+ 11, //A6
+ 12, //A7
+ 13, //A8
+ 28, //A9
+ 29, //A10
+ 35, //A11
+ 41, //A12
+ 45, //A13
+ 0, //A14
+ 1 //A15
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * @brief System Clock Configuration
+ * SYSCLK = 100MHz for ARDUINO_NUCLEO_F410RB
+ * @param None
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 4;
+ RCC_OscInitStruct.PLL.PLLN = 100;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ Error_Handler();
+ }
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h
new file mode 100644
index 0000000000..8e05086ea0
--- /dev/null
+++ b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h
@@ -0,0 +1,140 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2025, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PA3 PIN_A14
+#define PA2 PIN_A15
+#define PA10 2
+#define PB3 3
+#define PB5 4
+#define PB4 5
+#define PB10 6
+#define PA8 7
+#define PA9 8
+#define PC7 9
+#define PB6 10
+#define PA7 PIN_A6
+#define PA6 PIN_A7
+#define PA5 PIN_A8 // LD2
+#define PB9 14
+#define PB8 15
+// ST Morpho
+// CN7 Left Side
+#define PC10 16
+#define PC12 17
+// 18 is NC - BOOT0
+#define PA13 19 // SWD
+#define PA14 20 // SWD
+#define PA15 21
+#define PB7 22
+#define PC13 23 // USER_BTN
+#define PC14 24
+#define PC15 25
+#define PH0 26
+#define PH1 27
+#define PC2 PIN_A9
+#define PC3 PIN_A10
+// CN7 Right Side
+#define PC11 30
+#define PB11 31
+// CN10 Left Side
+#define PC9 32
+// CN10 Right side
+#define PC8 33
+#define PC6 34
+#define PC5 PIN_A11
+#define PA12 36
+#define PA11 37
+#define PB12 38
+// 39 is NC
+#define PB2 40
+#define PB1 PIN_A12
+#define PB15 42
+#define PB14 43
+#define PB13 44
+#define PC4 PIN_A13
+#define PA0 PIN_A0
+#define PA1 PIN_A1
+#define PA4 PIN_A2
+#define PB0 PIN_A3
+#define PC1 PIN_A4
+#define PC0 PIN_A5
+
+// Alternate pins number
+#define PA2_ALT1 = (PA2 | ALT1)
+#define PA3_ALT1 = (PA3 | ALT1)
+#define PB9_ALT1 = (PB9 | ALT1)
+
+#define NUM_DIGITAL_PINS 52
+#define NUM_ANALOG_INPUTS 16
+
+// On-board LED pin number
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN PA5
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PC13
+#endif
+
+
+// Timer Definitions
+// Use TIM9/TIM11 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM6
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM11
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 2 //Connected to ST-Link
+#endif
+
+// Default pin used for 'Serial' instance (ex: ST-Link)
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PA3
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PA2
+#endif
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #define SERIAL_PORT_MONITOR Serial
+ #define SERIAL_PORT_HARDWARE Serial
+#endif
diff --git a/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt b/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt
index 2a4d55b6b1..3eab75f214 100644
--- a/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt
+++ b/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt
@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
generic_clock.c
PeripheralPins.c
variant_generic.cpp
+ variant_NUCLEO_L412RB_P.cpp
)
target_link_libraries(variant_bin PUBLIC variant_usage)
diff --git a/variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld b/variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld
new file mode 100644
index 0000000000..9eb56d5d17
--- /dev/null
+++ b/variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld
@@ -0,0 +1,208 @@
+/*
+******************************************************************************
+**
+
+** File : LinkerScript.ld
+**
+** Author : STM32CubeMX
+**
+** Abstract : Linker script for STM32L412RBTxP series
+** 128Kbytes FLASH and 40Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+** Distribution: The file is distributed “as is,” without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** © COPYRIGHT(c) 2025 STMicroelectronics
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 8K
+FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(8);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(8);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(8);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(8);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(8);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(8);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(8);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(8);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(8);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(8);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(8);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(8);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(8);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+}
+
+
diff --git a/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp
new file mode 100644
index 0000000000..9b79190615
--- /dev/null
+++ b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp
@@ -0,0 +1,162 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2021, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_L412RB_P)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PA_10,
+ PA_9,
+ PA_12,
+ PB_3,
+ PB_5,
+ PA_15,
+ PB_10,
+ PC_7,
+ PB_6,
+ PA_8,
+ PA_11,
+ PB_15,
+ PB_14,
+ PB_13, // LED
+ PB_7,
+ PB_8,
+ // ST Morpho
+ // CN5 Left Side
+ PC_10,
+ PC_12,
+ PB_12,
+ PA_13,
+ PA_14,
+ PC_13, // User Button
+ PC_14,
+ PC_15,
+ PH_0,
+ PH_1,
+ PB_4,
+ PB_9,
+ // CN5 Right Side
+ PC_11,
+ // CN6 Left Side
+ PC_9,
+ // CN6 Right Side
+ PC_8,
+ PC_6,
+ PB_0,
+ PB_11,
+ PB_2,
+ PB_1,
+ PA_7,
+ PA_6,
+ PA_5,
+ PA_4,
+ PC_4,
+ PA_3, // STLink Rx
+ PA_2, // STLink Tx
+ PA_0,
+ PA_1,
+ PC_3,
+ PC_2,
+ PC_1,
+ PC_0,
+ PH_3
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 43, //A0
+ 44, //A1
+ 45, //A2
+ 46, //A3
+ 47, //A4
+ 48, //A5
+ 32, //A6
+ 35, //A7
+ 36, //A8
+ 37, //A9
+ 38, //A10
+ 39, //A11
+ 40 //A12
+};
+
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /* Configure LSE Drive Capability */
+ HAL_PWR_EnableBkUpAccess();
+ __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+ /*
+ * Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ /* MSI is enabled after System reset, activate PLL with MSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+ RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+ RCC_OscInitStruct.PLL.PLLM = 1;
+ RCC_OscInitStruct.PLL.PLLN = 40;
+ RCC_OscInitStruct.PLL.PLLR = RCC_PLLQ_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+ clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
+ /* Configure the main internal regulator output voltage */
+ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
+ Error_Handler();
+ }
+ /* Enable MSI Auto calibration */
+ HAL_RCCEx_EnableMSIPLLMode();
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ARDUINO_NUCLEO_L412RB_P */
diff --git a/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h
new file mode 100644
index 0000000000..a3bb945b4a
--- /dev/null
+++ b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h
@@ -0,0 +1,155 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2021, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * Pins
+ *----------------------------------------------------------------------------*/
+
+#define PA10 0 // SB33 ON / SB32 OFF
+#define PA9 1 // SB35 ON / SB34 OFF
+#define PA12 2
+#define PB3 3
+#define PB5 4
+#define PA15 5
+#define PB10 6
+#define PC7 7
+#define PB6 8
+#define PA8 9
+#define PA11 10
+#define PB15 11
+#define PB14 12
+#define PB13 13 // LED
+#define PB7 14
+#define PB8 15
+// ST Morpho
+// CN5 Left Side
+#define PC10 16
+#define PC12 17
+#define PB12 18
+#define PA13 19
+#define PA14 20
+#define PC13 21 // User Button
+#define PC14 22
+#define PC15 23
+#define PH0 24
+#define PH1 25
+#define PB4 26
+#define PB9 27
+// CN5 Right Side
+#define PC11 28
+// CN6 Left Side
+#define PC9 29
+// CN6 Right Side
+#define PC8 30
+#define PC6 31
+#define PB0 PIN_A6
+#define PB11 33
+#define PB2 34
+#define PB1 PIN_A7
+#define PA7 PIN_A8
+#define PA6 PIN_A9
+#define PA5 PIN_A10
+#define PA4 PIN_A11
+#define PC4 PIN_A12
+#define PA3 41 // STLink Rx
+#define PA2 42 // STLink Tx
+#define PA0 PIN_A0
+#define PA1 PIN_A1
+#define PC3 PIN_A2
+#define PC2 PIN_A3
+#define PC1 PIN_A4
+#define PC0 PIN_A5
+#define PH3 49
+
+// Alternate pins number
+#define PA1_ALT1 (PA1 | ALT1)
+#define PA2_ALT1 (PA2 | ALT1)
+#define PA3_ALT1 (PA3 | ALT1)
+#define PA4_ALT1 (PA4 | ALT1)
+#define PA6_ALT1 (PA6 | ALT1)
+#define PA15_ALT1 (PA15 | ALT1)
+#define PB1_ALT1 (PB1 | ALT1)
+#define PB3_ALT1 (PB3 | ALT1)
+#define PB4_ALT1 (PB4 | ALT1)
+#define PB5_ALT1 (PB5 | ALT1)
+#define PB13_ALT1 (PB13 | ALT1)
+#define PB14_ALT1 (PB14 | ALT1)
+#define PB15_ALT1 (PB15 | ALT1)
+
+#define NUM_DIGITAL_PINS 50
+#define NUM_ANALOG_INPUTS 13
+
+// On-board LED pin number
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN PB13
+#endif
+#ifndef LED_GREEN
+ #define LED_GREEN LED_BUILTIN
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PC13
+#endif
+
+// Timer Definitions (optional)
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM6
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM16
+#endif
+
+// UART Definitions
+// Define here Serial instance number to map on Serial generic name
+#define SERIAL_UART_INSTANCE 101
+
+// Default pin used for 'Serial' instance (ex: ST-Link)
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PA3
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PA2
+#endif
+
+// Enable QSPI
+#if !defined(HAL_QSPI_MODULE_DISABLED)
+ #define HAL_QSPI_MODULE_ENABLED
+#endif
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #define SERIAL_PORT_MONITOR Serial
+ #define SERIAL_PORT_HARDWARE Serial
+#endif
diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt
index 2a4d55b6b1..656acd547b 100644
--- a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt
+++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt
@@ -21,7 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage)
add_library(variant_bin STATIC EXCLUDE_FROM_ALL
generic_clock.c
PeripheralPins.c
+ PeripheralPins_STM32L562E_DK.c
variant_generic.cpp
+ variant_STM32L562E_DK.cpp
)
target_link_libraries(variant_bin PUBLIC variant_usage)