diff --git a/.github/workflows/compile-examples.yml b/.github/workflows/compile-examples.yml index 7de329e48..6e0bd2963 100644 --- a/.github/workflows/compile-examples.yml +++ b/.github/workflows/compile-examples.yml @@ -41,6 +41,7 @@ jobs: - fqbn: arduino:mbed:opta - fqbn: arduino:mbed:giga - fqbn: arduino:mbed:nicla_voice + - fqbn: arduino:mbed:edge_control # compile only the examples compatible with each board include: @@ -156,7 +157,6 @@ jobs: - libraries/USBHOST - libraries/USBMSD/examples/AccessFlashAsUSBDisk - libraries/WiFi - - libraries/GSM - ~/Arduino/libraries/ArduinoBLE - board: fqbn: arduino:mbed:nicla_voice @@ -171,6 +171,15 @@ jobs: version: v0.9.6 - name: arduino-libg722 source-url: https://github.com/pschatzmann/arduino-libg722.git + - board: + fqbn: arduino:mbed:edge_control + additional-libraries: | + - name: MicroNMEA + additional-sketch-paths: | + - libraries/GSM + - libraries/USBHID + - libraries/USBMSD/examples/Nano33BLE_FlashMassStorage + - libraries/ThreadDebug steps: - name: Checkout repository diff --git a/README.md b/README.md index 0d46f40fb..6b94a0f4a 100644 --- a/README.md +++ b/README.md @@ -47,7 +47,7 @@ To install ARM build tools, use the `Boards Manager` option in the Arduino IDE t ## mbed-os-to-arduino script -The backbone of the packaging process is the https://github.com/arduino/ArduinoCore-mbed/blob/master/mbed-os-to-arduino script. It basically compiles a blank Mbed OS project for any supported target board, recovering the files that will be needed at compile time and copying them to the right location. This script is not compatible with MacOS, it must be run on Linux. +The backbone of the packaging process is the https://github.com/arduino/ArduinoCore-mbed/blob/master/mbed-os-to-arduino script. It basically compiles a blank Mbed OS project for any supported target board, recovering the files that will be needed at compile time and copying them to the right location. This script is compatible only with Linux. If you are using macOS, use the https://github.com/arduino/ArduinoCore-mbed/blob/master/mbed-os-to-arduino-macos script. It can be used for a variety of tasks including: diff --git a/boards.txt b/boards.txt index 6a067f06c..6dea04908 100644 --- a/boards.txt +++ b/boards.txt @@ -47,6 +47,11 @@ edge_control.bootloader.config=-f target/nrf52.cfg edge_control.bootloader.programmer=-f interface/cmsis-dap.cfg edge_control.bootloader.file=EDGE_CONTROL/bootloader.hex +edge_control.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +edge_control.debug.server.openocd.scripts.1={programmer.transport_script} +edge_control.debug.server.openocd.scripts.2=target/nrf52.cfg +edge_control.debug.svd_file={runtime.platform.path}/svd/nrf52840.svd + ############################################################## menu.split=Flash split @@ -74,7 +79,7 @@ envie_m7.menu.target_core.cm7.build.fpu=-mfpu=fpv5-d16 envie_m7.menu.target_core.cm7.build.architecture=cortex-m7 envie_m7.menu.target_core.cm7.compiler.mbed.arch.define= -envie_m7.menu.target_core.cm4.build.variant=PORTENTA_H7_M4 +envie_m7.menu.target_core.cm4.build.variant=GENERIC_STM32H747_M4 envie_m7.menu.target_core.cm4.build.mcu=cortex-m4 envie_m7.menu.target_core.cm4.build.fpu=-mfpu=fpv4-sp-d16 envie_m7.menu.target_core.cm4.build.architecture=cortex-m4 @@ -99,7 +104,7 @@ envie_m7.compiler.mbed.defines={build.variant.path}/defines.txt envie_m7.compiler.mbed.ldflags={build.variant.path}/ldflags.txt envie_m7.compiler.mbed.cflags={build.variant.path}/cflags.txt envie_m7.compiler.mbed.cxxflags={build.variant.path}/cxxflags.txt -envie_m7.compiler.mbed.includes={build.variant.path}/includes.txt +envie_m7.compiler.mbed.includes={build.variant.path}/../PORTENTA_H7_M7/includes.txt envie_m7.compiler.mbed.extra_ldflags=-lstdc++ -lsupc++ -lm -lc -lgcc -lnosys envie_m7.compiler.mbed="{build.variant.path}/libs/libmbed.a" envie_m7.vid.0=0x2341 @@ -160,6 +165,12 @@ envie_m7.bootloader.programmer=-f interface/stlink.cfg envie_m7.bootloader.extra_action.preflash=stm32h7x option_write 0 0x01c 0xb86aaf0 envie_m7.bootloader.file=PORTENTA_H7/portentah7_bootloader_mbed_hs_v2.elf +envie_m7.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +envie_m7.debug.server.openocd.scripts.1={programmer.transport_script} +envie_m7.debug.server.openocd.scripts.2=target/stm32h7x_dual_bank.cfg +envie_m7.menu.target_core.cm7.debug.svd_file={runtime.platform.path}/svd/STM32H747_CM7.svd +envie_m7.menu.target_core.cm4.debug.svd_file={runtime.platform.path}/svd/STM32H747_CM4.svd + envie_m7_thread_debug.name=Arduino Portenta H7 (ThreadDebug) envie_m7_thread_debug.vid.0=0x2341 envie_m7_thread_debug.pid.0=0x025B @@ -277,6 +288,11 @@ nano33ble.bootloader.config=-f target/nrf52.cfg nano33ble.bootloader.programmer=-f interface/cmsis-dap.cfg nano33ble.bootloader.file=nano33ble/bootloader.hex +nano33ble.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +nano33ble.debug.server.openocd.scripts.1={programmer.transport_script} +nano33ble.debug.server.openocd.scripts.2=target/nrf52.cfg +nano33ble.debug.svd_file={runtime.platform.path}/svd/nrf52840.svd + ############################################################## nanorp2040connect.name=Arduino Nano RP2040 Connect @@ -333,6 +349,11 @@ nanorp2040connect.bootloader.tool.default=openocd nanorp2040connect.bootloader.config=-f target/rp2040.cfg nanorp2040connect.bootloader.programmer=-f interface/cmsis-dap.cfg +nanorp2040connect.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +nanorp2040connect.debug.server.openocd.scripts.1={programmer.transport_script} +nanorp2040connect.debug.server.openocd.scripts.2=target/rp2040-core0.cfg +nanorp2040connect.debug.svd_file={runtime.platform.path}/svd/rp2040.svd + ############################################################## pico.name=Raspberry Pi Pico @@ -377,6 +398,11 @@ pico.bootloader.tool.default=openocd pico.bootloader.config=-f target/rp2040.cfg pico.bootloader.programmer=-f interface/cmsis-dap.cfg +pico.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +pico.debug.server.openocd.scripts.1={programmer.transport_script} +pico.debug.server.openocd.scripts.2=target/rp2040-core0.cfg +pico.debug.svd_file={runtime.platform.path}/svd/rp2040.svd + ############################################################## nicla_sense.name=Arduino Nicla Sense ME @@ -424,6 +450,11 @@ nicla_sense.bootloader.config=-f target/nrf52.cfg nicla_sense.bootloader.programmer=-f interface/cmsis-dap.cfg nicla_sense.bootloader.file=NICLA/bootloader.hex +nicla_sense.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +nicla_sense.debug.server.openocd.scripts.1={programmer.transport_script} +nicla_sense.debug.server.openocd.scripts.2=target/nrf52.cfg +nicla_sense.debug.svd_file={runtime.platform.path}/svd/nrf52833.svd + ############################################################## nicla_voice.name=Arduino Nicla Voice @@ -472,6 +503,11 @@ nicla_voice.bootloader.config=-f target/nrf52.cfg nicla_voice.bootloader.programmer=-f interface/cmsis-dap.cfg nicla_voice.bootloader.file=NICLA_VOICE/bootloader_application.hex +nicla_voice.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +nicla_voice.debug.server.openocd.scripts.1={programmer.transport_script} +nicla_voice.debug.server.openocd.scripts.2=target/nrf52.cfg +nicla_voice.debug.svd_file={runtime.platform.path}/svd/nrf52833.svd + ############################################################## nicla_vision.name=Arduino Nicla Vision @@ -492,7 +528,7 @@ nicla_vision.menu.target_core.cm7.build.fpu=-mfpu=fpv5-d16 nicla_vision.menu.target_core.cm7.build.architecture=cortex-m7 nicla_vision.menu.target_core.cm7.compiler.mbed.arch.define= -nicla_vision.menu.target_core.cm4.build.variant=PORTENTA_H7_M4 +nicla_vision.menu.target_core.cm4.build.variant=GENERIC_STM32H747_M4 nicla_vision.menu.target_core.cm4.build.mcu=cortex-m4 nicla_vision.menu.target_core.cm4.build.fpu=-mfpu=fpv4-sp-d16 nicla_vision.menu.target_core.cm4.build.architecture=cortex-m4 @@ -510,7 +546,7 @@ nicla_vision.compiler.mbed.defines={build.variant.path}/defines.txt nicla_vision.compiler.mbed.ldflags={build.variant.path}/ldflags.txt nicla_vision.compiler.mbed.cflags={build.variant.path}/cflags.txt nicla_vision.compiler.mbed.cxxflags={build.variant.path}/cxxflags.txt -nicla_vision.compiler.mbed.includes={build.variant.path}/includes.txt +nicla_vision.compiler.mbed.includes={build.variant.path}/../NICLA_VISION/includes.txt nicla_vision.compiler.mbed.extra_ldflags=-lstdc++ -lsupc++ -lm -lc -lgcc -lnosys nicla_vision.compiler.mbed="{build.variant.path}/libs/libmbed.a" nicla_vision.vid.0=0x2341 @@ -567,6 +603,12 @@ nicla_vision.bootloader.programmer=-f interface/stlink.cfg nicla_vision.bootloader.extra_action.preflash=stm32h7x option_write 0 0x01c 0xb86aaf0 nicla_vision.bootloader.file=NICLA_VISION/bootloader.elf +nicla_vision.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +nicla_vision.debug.server.openocd.scripts.1={programmer.transport_script} +nicla_vision.debug.server.openocd.scripts.2=target/stm32h7x_dual_bank.cfg +nicla_vision.menu.target_core.cm7.debug.svd_file={runtime.platform.path}/svd/STM32H747_CM7.svd +nicla_vision.menu.target_core.cm4.debug.svd_file={runtime.platform.path}/svd/STM32H747_CM4.svd + ############################################################## opta.name=Opta @@ -590,7 +632,7 @@ opta.menu.target_core.cm7.build.fpu=-mfpu=fpv5-d16 opta.menu.target_core.cm7.build.architecture=cortex-m7 opta.menu.target_core.cm7.compiler.mbed.arch.define= -opta.menu.target_core.cm4.build.variant=PORTENTA_H7_M4 +opta.menu.target_core.cm4.build.variant=GENERIC_STM32H747_M4 opta.menu.target_core.cm4.build.mcu=cortex-m4 opta.menu.target_core.cm4.build.fpu=-mfpu=fpv4-sp-d16 opta.menu.target_core.cm4.build.architecture=cortex-m4 @@ -617,7 +659,7 @@ opta.compiler.mbed.defines={build.variant.path}/defines.txt opta.compiler.mbed.ldflags={build.variant.path}/ldflags.txt opta.compiler.mbed.cflags={build.variant.path}/cflags.txt opta.compiler.mbed.cxxflags={build.variant.path}/cxxflags.txt -opta.compiler.mbed.includes={build.variant.path}/includes.txt +opta.compiler.mbed.includes={build.variant.path}/../OPTA/includes.txt opta.compiler.mbed.extra_ldflags=-lstdc++ -lsupc++ -lm -lc -lgcc -lnosys opta.compiler.mbed="{build.variant.path}/libs/libmbed.a" opta.vid.0=0x2341 @@ -696,6 +738,12 @@ opta.bootloader.programmer=-f interface/stlink.cfg opta.bootloader.extra_action.preflash=stm32h7x option_write 0 0x01c 0xb86aaf0 opta.bootloader.file=OPTA/bootloader.elf +opta.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +opta.debug.server.openocd.scripts.1={programmer.transport_script} +opta.debug.server.openocd.scripts.2=target/stm32h7x_dual_bank.cfg +opta.menu.target_core.cm7.debug.svd_file={runtime.platform.path}/svd/STM32H747_CM7.svd +opta.menu.target_core.cm4.debug.svd_file={runtime.platform.path}/svd/STM32H747_CM4.svd + ############################################################## giga.name=Arduino Giga R1 @@ -716,7 +764,7 @@ giga.menu.target_core.cm7.build.fpu=-mfpu=fpv5-d16 giga.menu.target_core.cm7.build.architecture=cortex-m7 giga.menu.target_core.cm7.compiler.mbed.arch.define= -giga.menu.target_core.cm4.build.variant=PORTENTA_H7_M4 +giga.menu.target_core.cm4.build.variant=GENERIC_STM32H747_M4 giga.menu.target_core.cm4.build.mcu=cortex-m4 giga.menu.target_core.cm4.build.fpu=-mfpu=fpv4-sp-d16 giga.menu.target_core.cm4.build.architecture=cortex-m4 @@ -739,7 +787,7 @@ giga.compiler.mbed.defines={build.variant.path}/defines.txt giga.compiler.mbed.ldflags={build.variant.path}/ldflags.txt giga.compiler.mbed.cflags={build.variant.path}/cflags.txt giga.compiler.mbed.cxxflags={build.variant.path}/cxxflags.txt -giga.compiler.mbed.includes={build.variant.path}/includes.txt +giga.compiler.mbed.includes={build.variant.path}/../GIGA/includes.txt giga.compiler.mbed.extra_ldflags=-lstdc++ -lsupc++ -lm -lc -lgcc -lnosys giga.compiler.mbed="{build.variant.path}/libs/libmbed.a" giga.vid.0=0x2341 @@ -791,3 +839,9 @@ giga.bootloader.config=-f target/stm32h7x_dual_bank.cfg giga.bootloader.programmer=-f interface/stlink.cfg giga.bootloader.extra_action.preflash=stm32h7x option_write 0 0x01c 0xb86aaf0 giga.bootloader.file=GIGA/bootloader.elf + +giga.debug.server.openocd.scripts.0=interface/{programmer.protocol}.cfg +giga.debug.server.openocd.scripts.1={programmer.transport_script} +giga.debug.server.openocd.scripts.2=target/stm32h7x_dual_bank.cfg +giga.menu.target_core.cm7.debug.svd_file={runtime.platform.path}/svd/STM32H747_CM7.svd +giga.menu.target_core.cm4.debug.svd_file={runtime.platform.path}/svd/STM32H747_CM4.svd \ No newline at end of file diff --git a/bootloaders/GIGA/bootloader.bin b/bootloaders/GIGA/bootloader.bin index fe6455c4c..3f8cd581e 100644 Binary files a/bootloaders/GIGA/bootloader.bin and b/bootloaders/GIGA/bootloader.bin differ diff --git a/bootloaders/GIGA/bootloader.elf b/bootloaders/GIGA/bootloader.elf index 680bcaff0..d99da4575 100755 Binary files a/bootloaders/GIGA/bootloader.elf and b/bootloaders/GIGA/bootloader.elf differ diff --git a/cores/arduino/mbed/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h b/cores/arduino/mbed/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h index eb3bf5afd..6291bb11d 100644 --- a/cores/arduino/mbed/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +++ b/cores/arduino/mbed/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h @@ -109,7 +109,7 @@ class AT_CellularContext : public CellularContext { * @return NIDD context text, e.g. Non-IP or NONIP */ virtual const char *get_nonip_context_type_str(); - virtual void enable_access_technology(); + virtual nsapi_error_t enable_access_technology(); virtual void set_cid(int cid); private: @@ -135,8 +135,6 @@ class AT_CellularContext : public CellularContext { PinName _dcd_pin; bool _active_high; - RadioAccessTechnologyType _rat; - FrequencyBand _band; protected: char _found_apn[MAX_APN_LENGTH]; @@ -144,6 +142,8 @@ class AT_CellularContext : public CellularContext { bool _cp_req; bool _is_connected; ATHandler &_at; + RadioAccessTechnologyType _rat; + FrequencyBand _band; }; } // namespace mbed diff --git a/cores/arduino/mbed/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h b/cores/arduino/mbed/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h index 0645b2b87..24ff87bc0 100644 --- a/cores/arduino/mbed/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h +++ b/cores/arduino/mbed/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h @@ -34,6 +34,7 @@ class GEMALTO_CINTERION_CellularContext: public AT_CellularContext { virtual NetworkStack *get_stack(); #endif // NSAPI_PPP_AVAILABLE virtual nsapi_error_t do_user_authentication(); + virtual nsapi_error_t enable_access_technology(); }; } /* namespace mbed */ diff --git a/cores/arduino/pinDefinitions.h b/cores/arduino/pinDefinitions.h index 7df17a804..ebb36131d 100644 --- a/cores/arduino/pinDefinitions.h +++ b/cores/arduino/pinDefinitions.h @@ -1,3 +1,6 @@ +#ifndef PIN_DEFINITIONS_H +#define PIN_DEFINITIONS_H + #ifdef USE_ARDUINO_PINOUT #include "drivers/InterruptIn.h" @@ -36,4 +39,6 @@ PinName digitalPinToPinName(pin_size_t P); int PinNameToIndex(PinName P); -#endif \ No newline at end of file +#endif // USE_ARDUINO_PINOUT + +#endif // PIN_DEFINITIONS_H \ No newline at end of file diff --git a/debugger/select_hla.cfg b/debugger/select_hla.cfg new file mode 100644 index 000000000..fafd55d14 --- /dev/null +++ b/debugger/select_hla.cfg @@ -0,0 +1 @@ +transport select hla_swd \ No newline at end of file diff --git a/debugger/select_swd.cfg b/debugger/select_swd.cfg new file mode 100644 index 000000000..a5edd260b --- /dev/null +++ b/debugger/select_swd.cfg @@ -0,0 +1 @@ +transport select swd \ No newline at end of file diff --git a/edge.variables b/edge.variables index 8f43ae029..05e810b14 100644 --- a/edge.variables +++ b/edge.variables @@ -1,5 +1,5 @@ export FLAVOUR="edge" export VARIANTS=("EDGE_CONTROL") export FQBNS=("edge_control") -export LIBRARIES=("PDM SPI Wire MRI USBHID USBMSD ThreadDebug Scheduler") +export LIBRARIES=("SocketWrapper GSM GPS SPI Wire MRI USBHID USBMSD ThreadDebug Scheduler") export BOOTLOADERS=("EDGE_CONTROL") diff --git a/giga.variables b/giga.variables index 83045721f..eef4bae04 100644 --- a/giga.variables +++ b/giga.variables @@ -1,5 +1,5 @@ export FLAVOUR="giga" -export VARIANTS=("GIGA PORTENTA_H7_M4") +export VARIANTS=("GIGA GENERIC_STM32H747_M4") export FQBNS=("giga") export LIBRARIES=("MRI Portenta_SDRAM SPI WiFi ea_malloc openamp_arduino STM32H747_System ThreadDebug Himax_HM01B0 PDM Arduino_H7_Video USBAudio KernelDebug Portenta_Audio RPC USBHID Wire Portenta_lvgl Camera rpclib OV7670 mbed-memory-status Scheduler USBMSD USBMIDI SocketWrapper MCUboot Arduino_CAN") export BOOTLOADERS=("GIGA") diff --git a/libraries/Arduino_CAN/src/Arduino_CAN.h b/libraries/Arduino_CAN/src/Arduino_CAN.h index 095fc89db..b5d9fdd5a 100644 --- a/libraries/Arduino_CAN/src/Arduino_CAN.h +++ b/libraries/Arduino_CAN/src/Arduino_CAN.h @@ -24,7 +24,7 @@ * COMPILE TIME CHECKS **************************************************************************************/ -#if !(defined(ARDUINO_PORTENTA_H7_M7) || defined(ARDUINO_PORTENTA_H7_M4) || defined(ARDUINO_GIGA)) +#if !(defined(ARDUINO_PORTENTA_H7_M7) || defined(ARDUINO_GIGA)) # error "CAN only available on Arduino Portenta H7 and Arduino Giga (of all ArduinoCore-mbed enabled boards)." #endif diff --git a/libraries/Camera/src/camera.cpp b/libraries/Camera/src/camera.cpp index e82ddfe90..2cc3da2ef 100644 --- a/libraries/Camera/src/camera.cpp +++ b/libraries/Camera/src/camera.cpp @@ -28,7 +28,7 @@ #define ALIGN_PTR(p,a) ((p & (a-1)) ?(((uintptr_t)p + a) & ~(uintptr_t)(a-1)) : p) // Include all image sensor drivers here. -#if defined (ARDUINO_PORTENTA_H7_M7) || defined (ARDUINO_PORTENTA_H7_M4) +#if defined (ARDUINO_PORTENTA_H7_M7) #define DCMI_TIM (TIM1) #define DCMI_TIM_PIN (GPIO_PIN_1) @@ -80,7 +80,7 @@ arduino::MbedI2C CameraWire(I2C_SDA1, I2C_SCL1); // DCMI GPIO pins struct static const struct { GPIO_TypeDef *port; uint16_t pin; } dcmi_pins[] = { - #if defined (ARDUINO_PORTENTA_H7_M7) || defined (ARDUINO_PORTENTA_H7_M4) + #if defined (ARDUINO_PORTENTA_H7_M7) {GPIOA, GPIO_PIN_4 }, {GPIOA, GPIO_PIN_6 }, {GPIOI, GPIO_PIN_4 }, @@ -175,7 +175,7 @@ void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi) hgpio.Speed = GPIO_SPEED_FREQ_VERY_HIGH; hgpio.Alternate = GPIO_AF13_DCMI; - #if defined (ARDUINO_PORTENTA_H7_M7) || defined (ARDUINO_PORTENTA_H7_M4) + #if defined (ARDUINO_PORTENTA_H7_M7) /* Enable GPIO clocks */ __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); diff --git a/libraries/Ethernet/src/Ethernet.cpp b/libraries/Ethernet/src/Ethernet.cpp index 26d63e5a2..8d9c51a88 100644 --- a/libraries/Ethernet/src/Ethernet.cpp +++ b/libraries/Ethernet/src/Ethernet.cpp @@ -9,6 +9,10 @@ int arduino::EthernetClass::begin(uint8_t *mac, unsigned long timeout, unsigned if (eth_if == nullptr) return 0; } + if (mac != nullptr) { + eth_if->get_emac().set_hwaddr(mac); + } + unsigned long start = millis(); eth_if->set_blocking(false); eth_if->connect(); diff --git a/libraries/GPS/library.properties b/libraries/GPS/library.properties index cb0f09469..98f779b50 100644 --- a/libraries/GPS/library.properties +++ b/libraries/GPS/library.properties @@ -6,4 +6,4 @@ sentence=GPS Support Library paragraph= category=Other url=http://www.arduino.cc/en/Reference/GSM -architectures=mbed,ArduinoCore-mbed,mbed_portenta +architectures=mbed,ArduinoCore-mbed,mbed_portenta,mbed_edge diff --git a/libraries/GSM/examples/GNSSClient/GNSSClient.ino b/libraries/GSM/examples/GNSSClient/GNSSClient.ino index e263e42ae..cb6e1df9a 100644 --- a/libraries/GSM/examples/GNSSClient/GNSSClient.ino +++ b/libraries/GSM/examples/GNSSClient/GNSSClient.ino @@ -8,9 +8,20 @@ char username[] = SECRET_USERNAME; char pass[] = SECRET_PASSWORD; void setup() { + +#if defined(ARDUINO_EDGE_CONTROL) + // Power ON MKR2 + pinMode(ON_MKR2, OUTPUT); + digitalWrite(ON_MKR2, HIGH); +#endif + Serial.begin(115200); while (!Serial) {} + // To enable AT Trace debug uncomment the following lines + //GSM.trace(Serial); + //GSM.setTraceLevel(4); + Serial.println("Starting Carrier Network registration"); if(!GSM.begin(pin, apn, username, pass, CATNB)){ Serial.println("The board was not able to register to the network..."); diff --git a/libraries/GSM/examples/GSMClient/GSMClient.ino b/libraries/GSM/examples/GSMClient/GSMClient.ino index 0a6f61c01..14b031b0b 100644 --- a/libraries/GSM/examples/GSMClient/GSMClient.ino +++ b/libraries/GSM/examples/GSMClient/GSMClient.ino @@ -1,7 +1,5 @@ #include -REDIRECT_STDOUT_TO(Serial); - #include "arduino_secrets.h" char pin[] = SECRET_PIN; char apn[] = SECRET_APN; @@ -14,8 +12,20 @@ int port = 80; GSMClient client; void setup() { + +#if defined(ARDUINO_EDGE_CONTROL) + // Power ON MKR2 + pinMode(ON_MKR2, OUTPUT); + digitalWrite(ON_MKR2, HIGH); +#endif + Serial.begin(115200); while(!Serial) {} + + // To enable AT Trace debug uncomment the following lines + //GSM.trace(Serial); + //GSM.setTraceLevel(4); + Serial.println("Starting Carrier Network registration"); if(!GSM.begin(pin, apn, username, pass, CATNB, BAND_20 | BAND_19)){ Serial.println("The board was not able to register to the network..."); diff --git a/libraries/GSM/examples/GSMSSLClient/GSMSSLClient.ino b/libraries/GSM/examples/GSMSSLClient/GSMSSLClient.ino new file mode 100644 index 000000000..0aa85f669 --- /dev/null +++ b/libraries/GSM/examples/GSMSSLClient/GSMSSLClient.ino @@ -0,0 +1,85 @@ +/* + GSMSSLlient + + This sketch connects to a website (https://example.com) + using the Portenta CAT.M1/NB IoT GNSS Shield and TLS. + + */ + +#include +#include "arduino_secrets.h" + +#if defined(ARDUINO_EDGE_CONTROL) + #include "root_ca.h" +#endif + +char pin[] = SECRET_PIN; +char apn[] = SECRET_APN; +char username[] = SECRET_USERNAME; +char pass[] = SECRET_PASSWORD; + +const char server[] = "example.com"; +const char* ip_address; +int port = 443; +GSMSSLClient client; + +void setup() { + +#if defined(ARDUINO_EDGE_CONTROL) + // Power ON MKR2 + pinMode(ON_MKR2, OUTPUT); + digitalWrite(ON_MKR2, HIGH); + + // Configure root certificate + client.appendCustomCACert(root_ca); +#endif + + Serial.begin(115200); + while(!Serial) {} + + // To enable AT Trace debug uncomment the following lines + //GSM.trace(Serial); + //GSM.setTraceLevel(4); + + Serial.println("Starting Carrier Network registration"); + if(!GSM.begin(pin, apn, username, pass, CATM1, BAND_3 | BAND_20 | BAND_19)){ + Serial.println("The board was not able to register to the network..."); + // do nothing forevermore: + while(1); + } + Serial.println("\nStarting connection to server..."); + // if you get a connection, report back via serial: + if (client.connect(server, port)) { + Serial.println("connected to server"); + // Make a HTTP request: + client.println("GET / HTTP/1.1"); + client.print("Host: "); + client.println(server); + client.println("Connection: close"); + client.println(); + } else { + Serial.println("unable to connect to server"); + } + +} + +void loop() { + + // if there are incoming bytes available + // from the server, read them and print them: + while (client.available()) { + char c = client.read(); + Serial.write(c); + } + + // if the server's disconnected, stop the client: + if (!client.connected()) { + Serial.println(); + Serial.println("disconnecting from server."); + client.stop(); + + // do nothing forevermore: + while (true); + } + +} diff --git a/libraries/GSM/examples/GSMSSLClient/arduino_secrets.h b/libraries/GSM/examples/GSMSSLClient/arduino_secrets.h new file mode 100644 index 000000000..8c5842fa6 --- /dev/null +++ b/libraries/GSM/examples/GSMSSLClient/arduino_secrets.h @@ -0,0 +1,4 @@ +#define SECRET_PIN "" +#define SECRET_APN "" +#define SECRET_USERNAME "" +#define SECRET_PASSWORD "" diff --git a/libraries/GSM/examples/GSMSSLClient/root_ca.h b/libraries/GSM/examples/GSMSSLClient/root_ca.h new file mode 100644 index 000000000..c314f4cc2 --- /dev/null +++ b/libraries/GSM/examples/GSMSSLClient/root_ca.h @@ -0,0 +1,23 @@ +static const char root_ca[] = +"-----BEGIN CERTIFICATE-----\n" +"MIIDrzCCApegAwIBAgIQCDvgVpBCRrGhdWrJWZHHSjANBgkqhkiG9w0BAQUFADBh\n" +"MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3\n" +"d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBD\n" +"QTAeFw0wNjExMTAwMDAwMDBaFw0zMTExMTAwMDAwMDBaMGExCzAJBgNVBAYTAlVT\n" +"MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j\n" +"b20xIDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IENBMIIBIjANBgkqhkiG\n" +"9w0BAQEFAAOCAQ8AMIIBCgKCAQEA4jvhEXLeqKTTo1eqUKKPC3eQyaKl7hLOllsB\n" +"CSDMAZOnTjC3U/dDxGkAV53ijSLdhwZAAIEJzs4bg7/fzTtxRuLWZscFs3YnFo97\n" +"nh6Vfe63SKMI2tavegw5BmV/Sl0fvBf4q77uKNd0f3p4mVmFaG5cIzJLv07A6Fpt\n" +"43C/dxC//AH2hdmoRBBYMql1GNXRor5H4idq9Joz+EkIYIvUX7Q6hL+hqkpMfT7P\n" +"T19sdl6gSzeRntwi5m3OFBqOasv+zbMUZBfHWymeMr/y7vrTC0LUq7dBMtoM1O/4\n" +"gdW7jVg/tRvoSSiicNoxBN33shbyTApOB6jtSj1etX+jkMOvJwIDAQABo2MwYTAO\n" +"BgNVHQ8BAf8EBAMCAYYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUA95QNVbR\n" +"TLtm8KPiGxvDl7I90VUwHwYDVR0jBBgwFoAUA95QNVbRTLtm8KPiGxvDl7I90VUw\n" +"DQYJKoZIhvcNAQEFBQADggEBAMucN6pIExIK+t1EnE9SsPTfrgT1eXkIoyQY/Esr\n" +"hMAtudXH/vTBH1jLuG2cenTnmCmrEbXjcKChzUyImZOMkXDiqw8cvpOp/2PV5Adg\n" +"06O/nVsJ8dWO41P0jmP6P6fbtGbfYmbW0W5BjfIttep3Sp+dWOIrWcBAI+0tKIJF\n" +"PnlUkiaY4IBIqDfv8NZ5YBberOgOzW6sRBc4L0na4UU+Krk2U886UAb3LujEV0ls\n" +"YSEY1QSteDwsOoBrp+uvFRTp2InBuThs4pFsiv9kuXclVzDAGySj4dzp30d8tbQk\n" +"CAUw7C29C79Fv1C5qfPrmAESrciIxpg0X40KPMbp1ZWVbd4=\n" +"-----END CERTIFICATE-----\n"; diff --git a/libraries/GSM/keywords.txt b/libraries/GSM/keywords.txt new file mode 100644 index 000000000..b61108b00 --- /dev/null +++ b/libraries/GSM/keywords.txt @@ -0,0 +1,35 @@ +####################################### +# Syntax Coloring Map For GSM +####################################### + +####################################### +# Class (KEYWORD1) +####################################### + +GSM KEYWORD1 +GSMClient KEYWORD1 +GSMSSLClient KEYWORD1 +GSMUDP KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin +disconnect +end +getTime +getLocalTime +setTime +enableCmux +isCmuxEnable +trace +setTraceLevel +ping +isConnected +getNetwork + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/libraries/GSM/library.properties b/libraries/GSM/library.properties index 1b68bbc9d..f72c84a1d 100644 --- a/libraries/GSM/library.properties +++ b/libraries/GSM/library.properties @@ -6,4 +6,4 @@ sentence=GSM wrapper paragraph= category=Other url=http://www.arduino.cc/en/Reference/GSM -architectures=mbed,ArduinoCore-mbed,mbed_portenta +architectures=mbed,ArduinoCore-mbed,mbed_portenta,mbed_edge diff --git a/libraries/GSM/src/GSM.cpp b/libraries/GSM/src/GSM.cpp index 1da0d49b3..e510697b4 100644 --- a/libraries/GSM/src/GSM.cpp +++ b/libraries/GSM/src/GSM.cpp @@ -1,15 +1,32 @@ +/* + GSM.cpp - Library for GSM on mbed platforms. + Copyright (c) 2011-2023 Arduino LLC. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + #include "GSM.h" #include "mbed.h" #include "CellularLog.h" +#include "CellularDevice.h" #include "CellularContext.h" #include "CellularInterface.h" #include "GEMALTO_CINTERION_CellularStack.h" -#define MAXRETRY 3 - -bool _cmuxEnable = false; -arduino::CMUXClass * arduino::CMUXClass::get_default_instance() +arduino::CMUXClass *arduino::CMUXClass::get_default_instance() { static mbed::UnbufferedSerial serial(MBED_CONF_GEMALTO_CINTERION_TX, MBED_CONF_GEMALTO_CINTERION_RX, 115200); serial.set_flow_control(mbed::SerialBase::RTSCTS_SW, MBED_CONF_GEMALTO_CINTERION_CTS, NC); @@ -19,91 +36,80 @@ arduino::CMUXClass * arduino::CMUXClass::get_default_instance() mbed::CellularDevice *mbed::CellularDevice::get_default_instance() { - static auto cmux = arduino::CMUXClass::get_default_instance(); - static mbed::GEMALTO_CINTERION device(cmux->get_serial(0)); - nextSerialPort++; - device.enableCMUXChannel = mbed::callback(cmux, &arduino::CMUXClass::enableCMUXChannel); - return &device; + static auto cmux = arduino::CMUXClass::get_default_instance(); + static mbed::GEMALTO_CINTERION device(cmux->get_serial(0)); + nextSerialPort++; + device.enableCMUXChannel = mbed::callback(cmux, &arduino::CMUXClass::enableCMUXChannel); + return &device; } int arduino::GSMClass::begin(const char* pin, const char* apn, const char* username, const char* password, RadioAccessTechnologyType rat, uint32_t band, bool restart) { - if(restart || isCmuxEnable()) { - pinMode(PJ_10, OUTPUT); - digitalWrite(PJ_10, HIGH); - delay(800); - digitalWrite(PJ_10, LOW); - pinMode(PJ_7, OUTPUT); - digitalWrite(PJ_7, LOW); - delay(1); - digitalWrite(PJ_7, HIGH); - delay(1); - // this timer is to make sure that at boottime and when the CMUX is used, - // ^SYSTART is received in time to avoid stranger behaviour - // from HW serial - delay(2000); + if (restart || isCmuxEnable()) { + reset(); } _context = mbed::CellularContext::get_default_instance(); if (_context == nullptr) { - printf("Invalid context\n"); + DEBUG_ERROR("Invalid mbed::CellularContext"); return 0; } - pinMode(PJ_7, INPUT_PULLDOWN); + + pinMode(MBED_CONF_GEMALTO_CINTERION_ON, INPUT_PULLDOWN); static mbed::DigitalOut rts(MBED_CONF_GEMALTO_CINTERION_RTS, 0); _device = _context->get_device(); + _device->modem_debug_on(_at_debug); - _device->set_cmux_status_flag(_cmuxGSMenable); - - _context->set_sim_pin(pin); + if (!isReady()) { + DEBUG_ERROR("Cellular device not ready"); + return 0; + } + _device->set_cmux_status_flag(_cmuxGSMenable); + _device->set_retry_timeout_array(_retry_timeout, sizeof(_retry_timeout) / sizeof(_retry_timeout[0])); +#if GSM_DEBUG_ENABLE + _device->attach(mbed::callback(this, &GSMClass::onStatusChange)); +#endif _device->init(); - _context->set_authentication_type((mbed::CellularContext::AuthenticationType)1); - _pin = pin; _apn = apn; _username = username; _password = password; _rat = rat; _band = (FrequencyBand) band; - _context->set_credentials(apn, username, password); - _context->set_access_technology(rat); + _context->set_sim_pin(pin); + _context->set_authentication_type(mbed::CellularContext::AuthenticationType::PAP); + _context->set_credentials(_apn, _username, _password); + _context->set_access_technology(_rat); _context->set_band(_band); int connect_status = NSAPI_ERROR_AUTH_FAILURE; - uint8_t retryCount = 0; - while(connect_status != NSAPI_ERROR_OK && retryCount < MAXRETRY) { - - connect_status = _context->connect(pin, apn, username, password); - retryCount++; - - if (connect_status == NSAPI_ERROR_AUTH_FAILURE) { - tr_info("Authentication Failure. Exiting application.\n"); - } else if (connect_status == NSAPI_ERROR_OK || connect_status == NSAPI_ERROR_IS_CONNECTED) { - connect_status = NSAPI_ERROR_OK; - tr_info("Connection Established.\n"); - } else if (retryCount > 2) { - tr_info("Fatal connection failure: %d\n", connect_status); - } else { - tr_info("Couldn't connect, will retry...\n"); - continue; - } + DEBUG_INFO("Connecting..."); + connect_status = _context->connect(pin, apn, username, password); + + if (connect_status == NSAPI_ERROR_AUTH_FAILURE) { + DEBUG_ERROR("Authentication Failure. Exiting application."); + } else if (connect_status == NSAPI_ERROR_OK || connect_status == NSAPI_ERROR_IS_CONNECTED) { + connect_status = NSAPI_ERROR_OK; + DEBUG_INFO("Connection Established."); + } else { + DEBUG_ERROR("Couldn't connect."); } return connect_status == NSAPI_ERROR_OK ? 1 : 0; } -void arduino::GSMClass::enableCmux(){ +void arduino::GSMClass::enableCmux() { _cmuxGSMenable = true; } -bool arduino::GSMClass::isCmuxEnable(){ +bool arduino::GSMClass::isCmuxEnable() { return _cmuxGSMenable; } @@ -130,56 +136,49 @@ bool arduino::GSMClass::setTime(unsigned long const epoch, int const timezone) return _device->set_time(epoch, timezone); } -static PlatformMutex trace_mutex; - -static void trace_wait() -{ - trace_mutex.lock(); -} - -static void trace_release() -{ - trace_mutex.unlock(); -} - -static char* trace_time(size_t ss) +bool arduino::GSMClass::isConnected() { - static char time_st[50]; - auto ms = std::chrono::time_point_cast(rtos::Kernel::Clock::now()).time_since_epoch().count(); - //snprintf(time_st, 49, "[%08llums]", ms); - snprintf(time_st, 1, "\n"); - return time_st; -} - -static Stream* trace_stream = nullptr; -static void arduino_print(const char* c) { - if (trace_stream) { - trace_stream->println(c); + if (_context) { + return _context->is_connected(); + } else { + return false; } } -void arduino::GSMClass::debug(Stream& stream) { - -#if MBED_CONF_MBED_TRACE_ENABLE - mbed_trace_init(); - trace_stream = &stream; - mbed_trace_print_function_set(arduino_print); - mbed_trace_prefix_function_set( &trace_time ); - - mbed_trace_mutex_wait_function_set(trace_wait); - mbed_trace_mutex_release_function_set(trace_release); +NetworkInterface* arduino::GSMClass::getNetwork() { + return _context; +} - mbed_cellular_trace::mutex_wait_function_set(trace_wait); - mbed_cellular_trace::mutex_release_function_set(trace_release); +void arduino::GSMClass::reset() { + pinMode(MBED_CONF_GEMALTO_CINTERION_RST, OUTPUT); + digitalWrite(MBED_CONF_GEMALTO_CINTERION_RST, HIGH); + delay(800); + digitalWrite(MBED_CONF_GEMALTO_CINTERION_RST, LOW); + pinMode(MBED_CONF_GEMALTO_CINTERION_ON, OUTPUT); + digitalWrite(MBED_CONF_GEMALTO_CINTERION_ON, LOW); + delay(1); + digitalWrite(MBED_CONF_GEMALTO_CINTERION_ON, HIGH); + delay(1); +} -#endif +bool arduino::GSMClass::isReady(const int timeout) { + if (!_device) { + DEBUG_ERROR("No device found"); + return false; + } -} + const unsigned int start = millis(); + while (_device->is_ready() != NSAPI_ERROR_OK) { -NetworkInterface* arduino::GSMClass::getNetwork() { - return _context; + if (millis() - start > timeout) { + DEBUG_WARNING("Timeout waiting device ready"); + return false; + } + delay(100); + } + return true; } arduino::GSMClass GSM; diff --git a/libraries/GSM/src/GSM.h b/libraries/GSM/src/GSM.h index 8b48d3e84..43512cec1 100644 --- a/libraries/GSM/src/GSM.h +++ b/libraries/GSM/src/GSM.h @@ -1,14 +1,17 @@ /* GSM.h - Library for GSM on mbed platforms. - Copyright (c) 2011-2021 Arduino LLC. All right reserved. + Copyright (c) 2011-2023 Arduino LLC. All right reserved. + This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. + This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. + You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA @@ -30,11 +33,27 @@ #include "CMUXClass.h" #include "PTYSerial.h" -#define MBED_CONF_GEMALTO_CINTERION_TX PA_0 -#define MBED_CONF_GEMALTO_CINTERION_RX PI_9 -#define MBED_CONF_GEMALTO_CINTERION_RTS PI_10 -#define MBED_CONF_GEMALTO_CINTERION_CTS PI_13 -#define MBED_CONF_APP_SOCK_TYPE 1 +#if defined(ARDUINO_PORTENTA_H7_M7) || defined(ARDUINO_PORTENTA_H7_M4) + #define MBED_CONF_GEMALTO_CINTERION_TX PA_0 + #define MBED_CONF_GEMALTO_CINTERION_RX PI_9 + #define MBED_CONF_GEMALTO_CINTERION_RTS PI_10 + #define MBED_CONF_GEMALTO_CINTERION_CTS PI_13 + #define MBED_CONF_GEMALTO_CINTERION_RST PJ_10 + #define MBED_CONF_GEMALTO_CINTERION_ON PJ_7 +#elif defined (ARDUINO_EDGE_CONTROL) + /* IMPORTANT: turn on the module's 5V on demand by calling + pinMode(ON_MKR2, OUTPUT); + digitalWrite(ON_MKR2, HIGH); + */ + #define MBED_CONF_GEMALTO_CINTERION_TX p24 + #define MBED_CONF_GEMALTO_CINTERION_RX p25 + #define MBED_CONF_GEMALTO_CINTERION_RTS NC + #define MBED_CONF_GEMALTO_CINTERION_CTS NC + #define MBED_CONF_GEMALTO_CINTERION_RST p31 + #define MBED_CONF_GEMALTO_CINTERION_ON p2 +#else + #error Gemalto Cinterion cellular connectivity not supported +#endif #if defined __has_include #if __has_include ("GPS.h") @@ -44,6 +63,27 @@ #endif #endif +#if defined __has_include + #if __has_include ("Arduino_DebugUtils.h") + #include "Arduino_DebugUtils.h" + #define GSM_DEBUG_ENABLE 1 + #else + #define DEBUG_ERROR(fmt, ...) + #define DEBUG_WARNING(fmt, ...) + #define DEBUG_INFO(fmt, ...) + #define DEBUG_DEBUG(fmt, ...) + #define DEBUG_VERBOSE(fmt, ...) + #define GSM_DEBUG_ENABLE 0 + #endif +#else + #define DEBUG_ERROR(fmt, ...) + #define DEBUG_WARNING(fmt, ...) + #define DEBUG_INFO(fmt, ...) + #define DEBUG_DEBUG(fmt, ...) + #define DEBUG_VERBOSE(fmt, ...) + #define GSM_DEBUG_ENABLE 0 +#endif + namespace arduino { typedef void* (*voidPrtFuncPtr)(void); @@ -87,10 +127,14 @@ class GSMClass : public MbedSocketClass { bool setTime(unsigned long const epoch, int const timezone = 0); void enableCmux(); bool isCmuxEnable(); - void debug(Stream& stream); +#if MBED_CONF_MBED_TRACE_ENABLE + void trace(Stream& stream); + void setTraceLevel(int trace_level, bool timestamp = false, bool at_trace = false); +#endif int ping(const char* hostname, uint8_t ttl = 128); int ping(const String& hostname, uint8_t ttl = 128); int ping(IPAddress host, uint8_t ttl = 128); + bool isConnected(); friend class GSMClient; friend class GSMUDP; @@ -108,6 +152,29 @@ class GSMClass : public MbedSocketClass { NetworkInterface* gsm_if = nullptr; mbed::CellularContext* _context = nullptr; mbed::CellularDevice* _device = nullptr; + bool _at_debug = false; + + /* Internal cellular state machine retries. Values are in seconds. + * This array also defines the maximum number of retries to 6 + */ + const uint16_t _retry_timeout[6] = {1, 2, 4, 8, 16, 32}; + +#if GSM_DEBUG_ENABLE + static constexpr int RSSI_UNKNOWN = 99; + static const char * const sim_state_str[]; + static const char * const reg_type_str[]; + static const char * const rat_str[]; + static const char * const state_str[]; + static const char * const event_str[]; + static const char * getRATString(const mbed::CellularNetwork::RadioAccessTechnology rat); + static const char * getStateString(const mbed::CellularStateMachine::CellularState state); + static const char * getEventString(const cellular_event_status event); + static const char * getSIMStateString(const mbed::CellularDevice::SimState state); + static const char * getRegistrationStateString(const mbed::CellularNetwork::RegistrationStatus state); + void onStatusChange(nsapi_event_t ev, intptr_t in); +#endif + void reset(); + bool isReady(const int timeout = 5000); }; } @@ -115,6 +182,7 @@ class GSMClass : public MbedSocketClass { extern GSMClass GSM; #include "GSMClient.h" +#include "GSMSSLClient.h" #include "GSMUdp.h" #endif diff --git a/libraries/GSM/src/GSMClient.cpp b/libraries/GSM/src/GSMClient.cpp new file mode 100644 index 000000000..71043da70 --- /dev/null +++ b/libraries/GSM/src/GSMClient.cpp @@ -0,0 +1,24 @@ +/* + GSMClient.cpp + Copyright (c) 2023 Arduino SA. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "GSMClient.h" + +arduino::GSMClient::GSMClient(): MbedClient(100) { + +} diff --git a/libraries/GSM/src/GSMClient.h b/libraries/GSM/src/GSMClient.h index b2f4a9036..8ac465975 100644 --- a/libraries/GSM/src/GSMClient.h +++ b/libraries/GSM/src/GSMClient.h @@ -26,6 +26,10 @@ namespace arduino { class GSMClient : public MbedClient { +public: + GSMClient(); + +private: NetworkInterface *getNetwork() { return GSM.getNetwork(); } diff --git a/libraries/GSM/src/GSMDebug.cpp b/libraries/GSM/src/GSMDebug.cpp new file mode 100644 index 000000000..5ec49324d --- /dev/null +++ b/libraries/GSM/src/GSMDebug.cpp @@ -0,0 +1,274 @@ +/* + GSMDebug.cpp - Library for GSM on mbed platforms. + Copyright (c) 2011-2023 Arduino LLC. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include + +#if GSM_DEBUG_ENABLE + +constexpr const char * const arduino::GSMClass::sim_state_str[] = { + "Ready", + "PIN Needed", + "PUK Needed", + "Unknown" +}; + +constexpr const char * const arduino::GSMClass::reg_type_str[] = { + "Not Registered", + "Registered (Home Network)", + "Searching Network", + "Registration Denied", + "Registration Unknown", + "Registered (Roaming)", + "Registered (SMS Only Home)", + "Registered (SMS Only Roaming)", + "Attached (Emergency Only)", + "Registered (CSFB Not Preferred Home)", + "Registered (CSFB Not Preferred Roaming)", + "Already Registered" +}; + +constexpr const char * const arduino::GSMClass::rat_str[] = { + "GSM", + "GSM_COMPACT", + "UTRAN", + "EGPRS", + "HSDPA", + "HSUPA", + "HSDPA_HSUPA", + "E_UTRAN", + "CATM1", + "NB1", + "RAT unknown", +}; + +constexpr const char * const arduino::GSMClass::state_str[] = { + "Init", + "Power On", + "Device ready", + "SIM PIN", + "Signal quality", + "Registering network", + "Attaching network", + "Unknown" +}; + +constexpr const char * const arduino::GSMClass::event_str[] = { + "Device ready", + "SIM status", + "Registration status", + "Registration type", + "Cell ID", + "RAT", + "Attach network", + "Activate PDP context", + "Signal quality", + "Retry", + "Timeout", +}; + +const char * arduino::GSMClass::getRATString(const mbed::CellularNetwork::RadioAccessTechnology rat) { + switch (rat) { + case mbed::CellularNetwork::RadioAccessTechnology::RAT_GSM: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_GSM_COMPACT: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_UTRAN: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_EGPRS: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_HSDPA: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_HSUPA: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_HSDPA_HSUPA: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_E_UTRAN: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_CATM1: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_NB1: + return rat_str[rat]; + break; + + case mbed::CellularNetwork::RadioAccessTechnology::RAT_UNKNOWN: + case mbed::CellularNetwork::RadioAccessTechnology::RAT_MAX: + default: + return rat_str[mbed::CellularNetwork::RadioAccessTechnology::RAT_UNKNOWN]; + break; + } +} + +const char * arduino::GSMClass::getStateString(const mbed::CellularStateMachine::CellularState state) { + switch (state) { + case mbed::CellularStateMachine::CellularState::STATE_INIT: + case mbed::CellularStateMachine::CellularState::STATE_POWER_ON: + case mbed::CellularStateMachine::CellularState::STATE_DEVICE_READY: + case mbed::CellularStateMachine::CellularState::STATE_SIM_PIN: + case mbed::CellularStateMachine::CellularState::STATE_SIGNAL_QUALITY: + case mbed::CellularStateMachine::CellularState::STATE_REGISTERING_NETWORK: + case mbed::CellularStateMachine::CellularState::STATE_ATTACHING_NETWORK: + return state_str[state]; + break; + + case mbed::CellularStateMachine::CellularState::STATE_MAX_FSM_STATE: + default: + return state_str[mbed::CellularStateMachine::CellularState::STATE_MAX_FSM_STATE]; + break; + } +} + +const char * arduino::GSMClass::getEventString(const cellular_event_status event) { + switch (event) { + case cellular_event_status::CellularDeviceReady: + case cellular_event_status::CellularSIMStatusChanged: + case cellular_event_status::CellularRegistrationStatusChanged: + case cellular_event_status::CellularRegistrationTypeChanged: + case cellular_event_status::CellularCellIDChanged: + case cellular_event_status::CellularRadioAccessTechnologyChanged: + case cellular_event_status::CellularAttachNetwork: + case cellular_event_status::CellularActivatePDPContext: + case cellular_event_status::CellularSignalQuality: + case cellular_event_status::CellularStateRetryEvent: + case cellular_event_status::CellularDeviceTimeout: + return event_str[event - NSAPI_EVENT_CELLULAR_STATUS_BASE]; + break; + + default: + return "Unknown"; + break; + } +} + +const char * arduino::GSMClass::getSIMStateString(const mbed::CellularDevice::SimState state) { + switch (state) { + case mbed::CellularDevice::SimStateReady: + case mbed::CellularDevice::SimStatePinNeeded: + case mbed::CellularDevice::SimStatePukNeeded: + case mbed::CellularDevice::SimStateUnknown: + return sim_state_str[state]; + break; + + default: + return sim_state_str[mbed::CellularDevice::SimStateUnknown]; + } +} + +const char * arduino::GSMClass::getRegistrationStateString(const mbed::CellularNetwork::RegistrationStatus state) { + switch (state) { + case mbed::CellularNetwork::StatusNotAvailable: + case mbed::CellularNetwork::NotRegistered: + case mbed::CellularNetwork::RegisteredHomeNetwork: + case mbed::CellularNetwork::SearchingNetwork: + case mbed::CellularNetwork::RegistrationDenied: + case mbed::CellularNetwork::Unknown: + case mbed::CellularNetwork::RegisteredRoaming: + case mbed::CellularNetwork::RegisteredSMSOnlyHome: + case mbed::CellularNetwork::RegisteredSMSOnlyRoaming: + case mbed::CellularNetwork::AttachedEmergencyOnly: + case mbed::CellularNetwork::RegisteredCSFBNotPreferredHome: + case mbed::CellularNetwork::RegisteredCSFBNotPreferredRoaming: + case mbed::CellularNetwork::AlreadyRegistered: + return reg_type_str[state]; + break; + + default: + return reg_type_str[mbed::CellularNetwork::Unknown]; + } +} + +void arduino::GSMClass::onStatusChange(nsapi_event_t ev, intptr_t in) { + + const cell_callback_data_t *data = (const cell_callback_data_t *)in; + + switch(ev) + { + case CellularDeviceReady: + { + DEBUG_INFO("Modem is powered and ready to receive commands"); + } + break; + + case CellularSIMStatusChanged: + { + const mbed::CellularDevice::SimState state = static_cast(data->status_data); + DEBUG_INFO("SIM status: %s", getSIMStateString(state)); + } + break; + + case CellularRegistrationStatusChanged: + { + const mbed::CellularNetwork::RegistrationStatus state = static_cast(data->status_data); + DEBUG_INFO("Registration status: %s", getRegistrationStateString(state)); + } + break; + + case CellularRegistrationTypeChanged: + { + /* Never called from mbed driver */ + } + break; + + case CellularCellIDChanged: + { + DEBUG_INFO("Cellular ID changed: %d", data->status_data); + } + break; + + case CellularRadioAccessTechnologyChanged: + { + const mbed::CellularNetwork::RadioAccessTechnology rat = static_cast (data->status_data); + DEBUG_INFO("RAT changed: %s", getRATString(rat)); + } + break; + + case CellularAttachNetwork: + { + DEBUG_INFO("Network status: %s", data->status_data ? "Attached" : "Detached"); + } + break; + + case CellularActivatePDPContext: + { + DEBUG_INFO("Activate PDP context %s", (data->error != NSAPI_ERROR_OK) ? "Failure" : "Success"); + } + break; + + case CellularSignalQuality: + { + const cell_signal_quality_t * sig = (const cell_signal_quality_t *)data->data; + if((data->error != NSAPI_ERROR_OK) || (sig->rssi == RSSI_UNKNOWN)) { + DEBUG_INFO("RSSI: Unknown"); + } else { + DEBUG_INFO("RSSI: %d", sig->rssi); + } + } + break; + + case CellularStateRetryEvent: + { + const cell_retry_cb_t * retry_cb_data = (const cell_retry_cb_t *)data->data; + const cellular_event_status event = static_cast(data->status_data); + const mbed::CellularStateMachine::CellularState state = static_cast(retry_cb_data->state); + DEBUG_WARNING("Cellular event %s timed out. Cellular state %s, retry count %d", getEventString(event), getStateString(state), retry_cb_data->retry_count); + } + break; + + case CellularDeviceTimeout: + { + const cell_timeout_cb_t * timeout_cb_data = (const cell_timeout_cb_t *)data->data; + const cellular_event_status event = static_cast(data->status_data); + const mbed::CellularStateMachine::CellularState state = static_cast(timeout_cb_data->state); + DEBUG_DEBUG("Cellular state: %s, waiting for event %s. Timeout %d", getStateString(state), getEventString(event), timeout_cb_data->timeout); + } + break; + } +} + +#endif diff --git a/libraries/GSM/src/GSMSSLClient.cpp b/libraries/GSM/src/GSMSSLClient.cpp new file mode 100644 index 000000000..c953adb4f --- /dev/null +++ b/libraries/GSM/src/GSMSSLClient.cpp @@ -0,0 +1,24 @@ +/* + GSMSSLClient.cpp + Copyright (c) 2023 Arduino SA. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "GSMSSLClient.h" + +arduino::GSMSSLClient::GSMSSLClient(): MbedSSLClient(100) { + +} diff --git a/libraries/GSM/src/GSMSSLClient.h b/libraries/GSM/src/GSMSSLClient.h new file mode 100644 index 000000000..2ea0ae713 --- /dev/null +++ b/libraries/GSM/src/GSMSSLClient.h @@ -0,0 +1,42 @@ +/* + GSMSSLClient.h + Copyright (c) 2023 Arduino SA. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef GSMSSLCLIENT_H +#define GSMSSLCLIENT_H + +#include "GSM.h" +#include "MbedSSLClient.h" + +extern const char CA_CERTIFICATES[]; + +namespace arduino { + +class GSMSSLClient : public arduino::MbedSSLClient { +public: + GSMSSLClient(); + +private: + NetworkInterface *getNetwork() { + return GSM.getNetwork(); + } +}; + +} + +#endif /* GSMSSLCLIENT_H */ \ No newline at end of file diff --git a/libraries/GSM/src/GSMTrace.cpp b/libraries/GSM/src/GSMTrace.cpp new file mode 100644 index 000000000..6c87c54c4 --- /dev/null +++ b/libraries/GSM/src/GSMTrace.cpp @@ -0,0 +1,81 @@ +/* + GSM.h - Library for GSM on mbed platforms. + Copyright (c) 2011-2023 Arduino LLC. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include +#include + +#if MBED_CONF_MBED_TRACE_ENABLE + +static Stream* trace_stream = nullptr; +static PlatformMutex trace_mutex; +static char trace_timestamp[8]; + +static void trace_wait() { + trace_mutex.lock(); +} + +static void trace_release() { + trace_mutex.unlock(); +} + +static char* trace_time(size_t ss) { + auto ms = std::chrono::time_point_cast(rtos::Kernel::Clock::now()).time_since_epoch().count(); + snprintf(trace_timestamp, 8, "[%08llu]", ms); + return trace_timestamp; +} + +static void trace_println(const char* c) { + if (trace_stream) { + trace_stream->println(c); + } +} +#endif + +void arduino::GSMClass::setTraceLevel(int trace_level, bool timestamp, bool at_trace) { +#if MBED_CONF_MBED_TRACE_ENABLE + switch(trace_level) { + case 0: mbed_trace_config_set(TRACE_ACTIVE_LEVEL_NONE); break; + case 1: mbed_trace_config_set(TRACE_ACTIVE_LEVEL_CMD); break; + case 2: mbed_trace_config_set(TRACE_ACTIVE_LEVEL_ERROR); break; + case 3: mbed_trace_config_set(TRACE_ACTIVE_LEVEL_WARN); break; + case 4: mbed_trace_config_set(TRACE_ACTIVE_LEVEL_INFO); break; + case 5: mbed_trace_config_set(TRACE_ACTIVE_LEVEL_DEBUG); break; + case 6: mbed_trace_config_set(TRACE_ACTIVE_LEVEL_ALL); break; + default: mbed_trace_config_set(TRACE_ACTIVE_LEVEL_ALL); break; + } + + _at_debug = at_trace; + + if (timestamp) { + mbed_trace_prefix_function_set( &trace_time ); + } +#endif +} + +void arduino::GSMClass::trace(Stream& stream) { +#if MBED_CONF_MBED_TRACE_ENABLE + trace_stream = &stream; + + mbed_trace_init(); + mbed_trace_config_set(TRACE_ACTIVE_LEVEL_ALL); + mbed_trace_print_function_set(trace_println); + mbed_trace_mutex_wait_function_set(trace_wait); + mbed_trace_mutex_release_function_set(trace_release); +#endif +} diff --git a/libraries/GSM/src/GSMUdp.h b/libraries/GSM/src/GSMUdp.h index 6b93bd966..519adff50 100644 --- a/libraries/GSM/src/GSMUdp.h +++ b/libraries/GSM/src/GSMUdp.h @@ -1,5 +1,5 @@ /* - WiFiUdp.h + GSMUdp.h Copyright (c) 2021 Arduino SA. All right reserved. This library is free software; you can redistribute it and/or diff --git a/libraries/GSM/src/PTYSerial.cpp b/libraries/GSM/src/PTYSerial.cpp index 3a457fcd4..ef1be67fa 100644 --- a/libraries/GSM/src/PTYSerial.cpp +++ b/libraries/GSM/src/PTYSerial.cpp @@ -127,20 +127,17 @@ int PTYSerial::get_port() { } int PTYSerial::write(const void *buffer) { const char *buf_ptr = static_cast(buffer); - tr_info("%s", buffer); return write(buf_ptr, sizeof(buffer)); } int PTYSerial::write(const void *buffer, size_t length) { const char *buf_ptr = static_cast(buffer); - tr_info("%s", buffer); int ret = _parent->populate_tx_buffer(buf_ptr, length, this->get_port()); return ret; } int PTYSerial::write(const void *buffer, size_t length, int id) { const char *buf_ptr = static_cast(buffer); - tr_info("%s", buffer); int ret = _parent->populate_tx_buffer(buf_ptr, length, id); return ret; } diff --git a/libraries/PDM/src/STM32H747_dfsdm/audio.c b/libraries/PDM/src/STM32H747_dfsdm/audio.c index 4ce082c71..ab8d6e902 100644 --- a/libraries/PDM/src/STM32H747_dfsdm/audio.c +++ b/libraries/PDM/src/STM32H747_dfsdm/audio.c @@ -68,7 +68,9 @@ void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_ { xfer_status |= DMA_XFER_HALF; // Invalidate Data Cache to get the updated content of the SRAM + #ifdef CORE_CM7 SCB_InvalidateDCache_by_Addr((uint32_t*)&RecBuff[0],sizeof(RecBuff)/2); + #endif } PDMIrqHandler(true); } @@ -86,7 +88,9 @@ void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filt { xfer_status |= DMA_XFER_FULL; // Invalidate Data Cache to get the updated content of the SRAM + #ifdef CORE_CM7 SCB_InvalidateDCache_by_Addr((uint32_t*)&RecBuff[PDM_BUFFER_SIZE/2],sizeof(RecBuff)/2); + #endif } PDMIrqHandler(false); } diff --git a/libraries/Portenta_SDRAM/src/SDRAM.h b/libraries/Portenta_SDRAM/src/SDRAM.h index 687925b47..5c75c1f01 100644 --- a/libraries/Portenta_SDRAM/src/SDRAM.h +++ b/libraries/Portenta_SDRAM/src/SDRAM.h @@ -4,8 +4,13 @@ #include "Arduino.h" +#if !defined(CORE_CM4) #define SDRAM_END_ADDRESS (0x60800000) #define SDRAM_START_ADDRESS (0x60000000) +#else +#define SDRAM_END_ADDRESS (0xC0800000) +#define SDRAM_START_ADDRESS (0xC0000000) +#endif class SDRAMClass { public: diff --git a/libraries/RPC/src/RPC.cpp b/libraries/RPC/src/RPC.cpp index b7911c123..0c327ff82 100644 --- a/libraries/RPC/src/RPC.cpp +++ b/libraries/RPC/src/RPC.cpp @@ -178,8 +178,14 @@ int RPCClass::begin(long unsigned int np, uint16_t nd) { * The rpmsg service is initiate by the remote processor, on H7 new_service_cb * callback is received on service creation. Wait for the callback */ - OPENAMP_Wait_EndPointready(&rp_endpoints[ENDPOINT_RAW], millis() + 500); - OPENAMP_Wait_EndPointready(&rp_endpoints[ENDPOINT_RESPONSE], millis() + 500); + auto err = OPENAMP_Wait_EndPointready(&rp_endpoints[ENDPOINT_RAW], millis() + 500); + err |= OPENAMP_Wait_EndPointready(&rp_endpoints[ENDPOINT_RESPONSE], millis() + 500); + + if (err == 0) { + initialized = true; + } else { + return 0; + } // Send first dummy message to enable the channel uint8_t message = 0x00; @@ -226,6 +232,8 @@ int RPCClass::begin(long unsigned int np, uint16_t nd) { return 0; } + initialized = true; + return 1; } diff --git a/libraries/Scheduler/examples/MultipleBlinks/MultipleBlinks.ino b/libraries/Scheduler/examples/MultipleBlinks/MultipleBlinks.ino index d1e67e20a..f76ad67ae 100644 --- a/libraries/Scheduler/examples/MultipleBlinks/MultipleBlinks.ino +++ b/libraries/Scheduler/examples/MultipleBlinks/MultipleBlinks.ino @@ -43,6 +43,13 @@ #define led2 LEDG #define led3 LEDB +// On Edge Control there are no leds so we use GPIO and Serial +#elif defined(ARDUINO_EDGE_CONTROL) + +#define led1 CMD_TRIAC_3 +#define led2 CMD_TRIAC_4 +#define led3 NOT_A_PIN + #else int led1 = LEDR; diff --git a/libraries/SocketWrapper/library.properties b/libraries/SocketWrapper/library.properties index ed198c88b..95e4c0980 100644 --- a/libraries/SocketWrapper/library.properties +++ b/libraries/SocketWrapper/library.properties @@ -6,4 +6,4 @@ sentence=Wrapper for mbed Socket classes paragraph= category=Other url=http://www.arduino.cc/en/Reference/WiFi -architectures=mbed,ArduinoCore-mbed,mbed_portenta,mbed_nicla,mbed_opta,mbed_giga +architectures=mbed,ArduinoCore-mbed,mbed_portenta,mbed_nicla,mbed_opta,mbed_giga,mbed_edge diff --git a/libraries/SocketWrapper/src/MbedClient.cpp b/libraries/SocketWrapper/src/MbedClient.cpp index dfd856f77..49265c002 100644 --- a/libraries/SocketWrapper/src/MbedClient.cpp +++ b/libraries/SocketWrapper/src/MbedClient.cpp @@ -150,6 +150,11 @@ int arduino::MbedClient::connectSSL(SocketAddress socketAddress) { return 0; } + /* For TLS connection timeout needs to be configured before handshake starts + * otherwise socket timeout is not adopted. See TLSSocketWrapper::set_timeout(int timeout) + */ + sock->set_timeout(_timeout); + restart_connect: nsapi_error_t returnCode = static_cast(sock)->connect(socketAddress); int ret = 0; diff --git a/libraries/SocketWrapper/src/MbedClient.h b/libraries/SocketWrapper/src/MbedClient.h index a2132ebf3..eca0e5a34 100644 --- a/libraries/SocketWrapper/src/MbedClient.h +++ b/libraries/SocketWrapper/src/MbedClient.h @@ -49,6 +49,10 @@ class MbedClient : public arduino::Client { public: MbedClient(); + MbedClient(unsigned long timeout) { + _timeout = timeout; + } + // Copy constructor, to be used when a Client returned by server.available() // needs to "survive" event if it goes out of scope // Sample usage: Client* new_client = new Client(existing_client) diff --git a/libraries/SocketWrapper/src/MbedSSLClient.cpp b/libraries/SocketWrapper/src/MbedSSLClient.cpp index e0aa1d2dd..3233c8dba 100644 --- a/libraries/SocketWrapper/src/MbedSSLClient.cpp +++ b/libraries/SocketWrapper/src/MbedSSLClient.cpp @@ -1,5 +1,9 @@ #include "MbedSSLClient.h" +arduino::MbedSSLClient::MbedSSLClient(unsigned long timeout): MbedClient(timeout), _disableSNI{false} { + onBeforeConnect(mbed::callback(this, &MbedSSLClient::setRootCA)); +} + arduino::MbedSSLClient::MbedSSLClient(): _disableSNI{false} { onBeforeConnect(mbed::callback(this, &MbedSSLClient::setRootCA)); }; diff --git a/libraries/SocketWrapper/src/MbedSSLClient.h b/libraries/SocketWrapper/src/MbedSSLClient.h index c4705fc7b..ddedcb563 100644 --- a/libraries/SocketWrapper/src/MbedSSLClient.h +++ b/libraries/SocketWrapper/src/MbedSSLClient.h @@ -23,7 +23,6 @@ #include "MbedClient.h" #include #include -#include extern const char CA_CERTIFICATES[]; @@ -33,6 +32,9 @@ class MbedSSLClient : public arduino::MbedClient { public: MbedSSLClient(); + + MbedSSLClient(unsigned long timeout); + virtual ~MbedSSLClient() { stop(); } @@ -56,9 +58,12 @@ class MbedSSLClient : public arduino::MbedClient { private: int setRootCA() { + int err = 0; + +#if defined(MBEDTLS_FS_IO) mbed::BlockDevice* root = mbed::BlockDevice::get_default_instance(); - int err = root->init(); - if( err != QSPIF_BD_ERROR_OK) { + err = root->init(); + if( err != 0) { return err; } @@ -74,6 +79,7 @@ class MbedSSLClient : public arduino::MbedClient { if( err != NSAPI_ERROR_OK) { return err; } +#endif if(_ca_cert_custom != NULL) { err = ((TLSSocket*)sock)->append_root_ca_cert(_ca_cert_custom); diff --git a/libraries/SocketWrapper/src/SocketHelpers.cpp b/libraries/SocketWrapper/src/SocketHelpers.cpp index 2e52663fa..f40f76348 100644 --- a/libraries/SocketWrapper/src/SocketHelpers.cpp +++ b/libraries/SocketWrapper/src/SocketHelpers.cpp @@ -50,6 +50,13 @@ arduino::IPAddress arduino::MbedSocketClass::dnsServerIP() { return ipAddressFromSocketAddress(ip); } +arduino::IPAddress arduino::MbedSocketClass::dnsIP(int n) { + SocketAddress ip; + NetworkInterface* interface = getNetwork(); + interface->get_dns_server(n, &ip, nullptr); + return ipAddressFromSocketAddress(ip); +} + void arduino::MbedSocketClass::config(arduino::IPAddress local_ip) { nsapi_addr_t convertedIP = { NSAPI_IPv4, { local_ip[0], local_ip[1], local_ip[2], local_ip[3] } }; _ip = SocketAddress(convertedIP); diff --git a/libraries/SocketWrapper/src/SocketHelpers.h b/libraries/SocketWrapper/src/SocketHelpers.h index 6934cf888..eea38386d 100644 --- a/libraries/SocketWrapper/src/SocketHelpers.h +++ b/libraries/SocketWrapper/src/SocketHelpers.h @@ -99,6 +99,13 @@ class MbedSocketClass { */ IPAddress dnsServerIP(); + /* + * Get the DNS Server ip address. + * + * return: DNS Server ip address value + */ + IPAddress dnsIP(int n = 0); + virtual NetworkInterface* getNetwork() = 0; int download(char* url, const char* target, bool const is_https = false); diff --git a/libraries/SocketWrapper/src/utility/wl_definitions.h b/libraries/SocketWrapper/src/utility/wl_definitions.h index bbf3fd8fc..9ea1f9fe4 100644 --- a/libraries/SocketWrapper/src/utility/wl_definitions.h +++ b/libraries/SocketWrapper/src/utility/wl_definitions.h @@ -70,9 +70,9 @@ enum wl_enc_type { /* Values map to 802.11 encryption suites... */ ENC_TYPE_AUTO = 8 }; -#if defined(ARDUINO_PORTENTA_H7_M7) || defined(ARDUINO_PORTENTA_H7_M4) +#if defined(ARDUINO_PORTENTA_H7_M7) #include "whd_version.h" #define WIFI_FIRMWARE_LATEST_VERSION WHD_VERSION #endif -#endif /* WL_DEFINITIONS_H_ */ \ No newline at end of file +#endif /* WL_DEFINITIONS_H_ */ diff --git a/libraries/WiFi/src/WiFi.cpp b/libraries/WiFi/src/WiFi.cpp index 13bf90656..cea1949ae 100644 --- a/libraries/WiFi/src/WiFi.cpp +++ b/libraries/WiFi/src/WiFi.cpp @@ -238,12 +238,22 @@ void arduino::WiFiClass::MACAddress(uint8_t *mac_address) #define WIFI_FIRMWARE_PATH "/wlan/4343WA1.BIN" +#if defined(CORE_CM4) +#include "QSPIFBlockDevice.h" +mbed::BlockDevice *mbed::BlockDevice::get_default_instance() +{ + static QSPIFBlockDevice default_bd(PD_11, PD_12, PE_2, PF_6, PF_10, PG_6, QSPIF_POLARITY_MODE_1, 40000000); + return &default_bd; +} +#endif + bool firmware_available = false; #include "wiced_filesystem.h" #include "resources.h" void wiced_filesystem_mount_error(void) { + while (!Serial) {} Serial.println("Failed to mount the filesystem containing the WiFi firmware."); Serial.println("Usually that means that the WiFi firmware has not been installed yet" " or was overwritten with another firmware."); @@ -252,6 +262,7 @@ void wiced_filesystem_mount_error(void) { } void wiced_filesystem_firmware_error(void) { + while (!Serial) {} Serial.println("Please run the \"WiFiFirmwareUpdater\" sketch once to install the WiFi firmware."); whd_print_logbuffer(); while (1) {} @@ -274,7 +285,7 @@ wiced_result_t whd_firmware_check_hook(const char* mounted_name, int mount_err) return WICED_SUCCESS; } } - Serial.println("File not found"); + if (Serial) { Serial.println("File not found\n"); } closedir(dir); } wiced_filesystem_firmware_error(); diff --git a/libraries/WiFi/src/utility/wl_definitions.h b/libraries/WiFi/src/utility/wl_definitions.h index bbf3fd8fc..9ea1f9fe4 100644 --- a/libraries/WiFi/src/utility/wl_definitions.h +++ b/libraries/WiFi/src/utility/wl_definitions.h @@ -70,9 +70,9 @@ enum wl_enc_type { /* Values map to 802.11 encryption suites... */ ENC_TYPE_AUTO = 8 }; -#if defined(ARDUINO_PORTENTA_H7_M7) || defined(ARDUINO_PORTENTA_H7_M4) +#if defined(ARDUINO_PORTENTA_H7_M7) #include "whd_version.h" #define WIFI_FIRMWARE_LATEST_VERSION WHD_VERSION #endif -#endif /* WL_DEFINITIONS_H_ */ \ No newline at end of file +#endif /* WL_DEFINITIONS_H_ */ diff --git a/libraries/openamp_arduino/src/openamp.c b/libraries/openamp_arduino/src/openamp.c index 43180dadd..62c26bbc0 100644 --- a/libraries/openamp_arduino/src/openamp.c +++ b/libraries/openamp_arduino/src/openamp.c @@ -169,14 +169,16 @@ int OPENAMP_check_for_message(void) unsigned long millis(); -void OPENAMP_Wait_EndPointready(struct rpmsg_endpoint *rp_ept, size_t deadline) +int OPENAMP_Wait_EndPointready(struct rpmsg_endpoint *rp_ept, size_t deadline) { while(!is_rpmsg_ept_ready(rp_ept) && (millis() < deadline)) { MAILBOX_Poll(rvdev.vdev); } if (millis() >= deadline) { printf("OPENAMP_Wait_EndPointready %X timed out\n\r", (unsigned int)rp_ept); + return -1; } + return 0; } /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/openamp_arduino/src/openamp.h b/libraries/openamp_arduino/src/openamp.h index 44ada3b33..e604c0cec 100644 --- a/libraries/openamp_arduino/src/openamp.h +++ b/libraries/openamp_arduino/src/openamp.h @@ -49,7 +49,7 @@ int OPENAMP_create_endpoint(struct rpmsg_endpoint *ept, const char *name, int OPENAMP_check_for_message(void); /* Wait loop on endpoint ready ( message dest address is know)*/ -void OPENAMP_Wait_EndPointready(struct rpmsg_endpoint *rp_ept, size_t deadline); +int OPENAMP_Wait_EndPointready(struct rpmsg_endpoint *rp_ept, size_t deadline); #ifdef __cplusplus } diff --git a/libraries/rpclib/src/rpc/client.cc b/libraries/rpclib/src/rpc/client.cc deleted file mode 100644 index 13f57021e..000000000 --- a/libraries/rpclib/src/rpc/client.cc +++ /dev/null @@ -1,249 +0,0 @@ -#include "rpc/client.h" -#include "rpc/config.h" -#include "rpc/rpc_error.h" - -#include -#include -#include -#include -#include -#include -#include - -#include "asio.hpp" -#include "format.h" - -#include "rpc/detail/async_writer.h" -#include "rpc/detail/dev_utils.h" -#include "rpc/detail/response.h" - -using namespace RPCLIB_ASIO; -using RPCLIB_ASIO::ip::tcp; -using namespace rpc::detail; - -namespace rpc { - -static constexpr uint32_t default_buffer_size = rpc::constants::DEFAULT_BUFFER_SIZE; - -struct client::impl { - impl(client *parent, std::string const &addr, uint16_t port) - : parent_(parent), - io_(), - strand_(io_), - call_idx_(0), - addr_(addr), - port_(port), - is_connected_(false), - state_(client::connection_state::initial), - writer_(std::make_shared( - &io_, RPCLIB_ASIO::ip::tcp::socket(io_))), - timeout_(nonstd::nullopt) { - pac_.reserve_buffer(default_buffer_size); - } - - void do_connect(tcp::resolver::iterator endpoint_iterator) { - LOG_INFO("Initiating connection."); - RPCLIB_ASIO::async_connect( - writer_->socket_, endpoint_iterator, - [this](std::error_code ec, tcp::resolver::iterator) { - if (!ec) { - std::unique_lock lock(mut_connection_finished_); - LOG_INFO("Client connected to {}:{}", addr_, port_); - is_connected_ = true; - state_ = client::connection_state::connected; - conn_finished_.notify_all(); - do_read(); - } else { - LOG_ERROR("Error during connection: {}", ec); - } - }); - } - - void do_read() { - LOG_TRACE("do_read"); - constexpr std::size_t max_read_bytes = default_buffer_size; - writer_->socket_.async_read_some( - RPCLIB_ASIO::buffer(pac_.buffer(), max_read_bytes), - // I don't think max_read_bytes needs to be captured explicitly - // (since it's constexpr), but MSVC insists. - [this, max_read_bytes](std::error_code ec, std::size_t length) { - if (!ec) { - LOG_TRACE("Read chunk of size {}", length); - pac_.buffer_consumed(length); - - RPCLIB_MSGPACK::unpacked result; - while (pac_.next(result)) { - auto r = response(std::move(result)); - auto id = r.get_id(); - auto ¤t_call = ongoing_calls_[id]; - try { - if (r.get_error()) { - throw rpc_error("rpc::rpc_error during call", - std::get<0>(current_call), - r.get_error()); - } - std::get<1>(current_call) - .set_value(std::move(*r.get_result())); - } catch (...) { - std::get<1>(current_call) - .set_exception(std::current_exception()); - } - strand_.post( - [this, id]() { ongoing_calls_.erase(id); }); - } - - // resizing strategy: if the remaining buffer size is - // less than the maximum bytes requested from asio, - // then request max_read_bytes. This prompts the unpacker - // to resize its buffer doubling its size - // (https://github.com/msgpack/msgpack-c/issues/567#issuecomment-280810018) - if (pac_.buffer_capacity() < max_read_bytes) { - LOG_TRACE("Reserving extra buffer: {}", max_read_bytes); - pac_.reserve_buffer(max_read_bytes); - } - do_read(); - } else if (ec == RPCLIB_ASIO::error::eof) { - LOG_WARN("The server closed the connection."); - state_ = client::connection_state::disconnected; - } else if (ec == RPCLIB_ASIO::error::connection_reset) { - // Yes, this should be connection_state::reset, - // but on windows, disconnection results in reset. May be - // asio bug, may be a windows socket pecularity. Should be - // investigated later. - state_ = client::connection_state::disconnected; - LOG_WARN("The connection was reset."); - } else { - LOG_ERROR("Unhandled error code: {} | '{}'", ec, - ec.message()); - } - }); - } - - client::connection_state get_connection_state() const { return state_; } - - //! \brief Waits for the write queue and writes any buffers to the network - //! connection. Should be executed throught strand_. - void write(RPCLIB_MSGPACK::sbuffer item) { - writer_->write(std::move(item)); - } - - nonstd::optional get_timeout() { - return timeout_; - } - - void set_timeout(int64_t value) { - timeout_ = value; - } - - void clear_timeout() { - timeout_ = nonstd::nullopt; - } - - using call_t = - std::pair>; - - client *parent_; - RPCLIB_ASIO::io_service io_; - RPCLIB_ASIO::strand strand_; - std::atomic call_idx_; /// The index of the last call made - std::unordered_map ongoing_calls_; - std::string addr_; - uint16_t port_; - RPCLIB_MSGPACK::unpacker pac_; - std::atomic_bool is_connected_; - std::condition_variable conn_finished_; - std::mutex mut_connection_finished_; - std::thread io_thread_; - std::atomic state_; - std::shared_ptr writer_; - nonstd::optional timeout_; - RPCLIB_CREATE_LOG_CHANNEL(client) -}; - -client::client(std::string const &addr, uint16_t port) - : pimpl(new client::impl(this, addr, port)) { - tcp::resolver resolver(pimpl->io_); - auto endpoint_it = - resolver.resolve({pimpl->addr_, std::to_string(pimpl->port_)}); - pimpl->do_connect(endpoint_it); - std::thread io_thread([this]() { - RPCLIB_CREATE_LOG_CHANNEL(client) - name_thread("client"); - pimpl->io_.run(); - }); - pimpl->io_thread_ = std::move(io_thread); -} - -void client::wait_conn() { - std::unique_lock lock(pimpl->mut_connection_finished_); - if (!pimpl->is_connected_) { - if (auto timeout = pimpl->timeout_) { - auto result = pimpl->conn_finished_.wait_for( - lock, std::chrono::milliseconds(*timeout)); - if (result == std::cv_status::timeout) { - throw rpc::timeout(RPCLIB_FMT::format( - "Timeout of {}ms while connecting to {}:{}", *get_timeout(), - pimpl->addr_, pimpl->port_)); - } - } else { - pimpl->conn_finished_.wait(lock); - } - } -} - -int client::get_next_call_idx() { - ++(pimpl->call_idx_); - return pimpl->call_idx_; -} - -void client::post(std::shared_ptr buffer, int idx, - std::string const &func_name, - std::shared_ptr p) { - pimpl->strand_.post([=]() { - pimpl->ongoing_calls_.insert( - std::make_pair(idx, std::make_pair(func_name, std::move(*p)))); - pimpl->write(std::move(*buffer)); - }); -} - -void client::post(RPCLIB_MSGPACK::sbuffer *buffer) { - pimpl->strand_.post([=]() { - pimpl->write(std::move(*buffer)); - delete buffer; - }); -} - -client::connection_state client::get_connection_state() const { - return pimpl->get_connection_state(); -} - -nonstd::optional client::get_timeout() const { - return pimpl->get_timeout(); -} - -void client::set_timeout(int64_t value) { - pimpl->set_timeout(value); -} - -void client::clear_timeout() { - pimpl->clear_timeout(); -} - -void client::wait_all_responses() { - for (auto &c : pimpl->ongoing_calls_) { - c.second.second.get_future().wait(); - } -} - -RPCLIB_NORETURN void client::throw_timeout(std::string const& func_name) { - throw rpc::timeout( - RPCLIB_FMT::format("Timeout of {}ms while calling RPC function '{}'", - *get_timeout(), func_name)); -} - -client::~client() { - pimpl->io_.stop(); - pimpl->io_thread_.join(); -} - -} diff --git a/libraries/rpclib/src/rpc/detail/server_session.cc b/libraries/rpclib/src/rpc/detail/server_session.cc deleted file mode 100644 index d6f89177b..000000000 --- a/libraries/rpclib/src/rpc/detail/server_session.cc +++ /dev/null @@ -1,146 +0,0 @@ -#include "rpc/detail/server_session.h" - -#include "rpc/config.h" -#include "rpc/server.h" -#include "rpc/this_handler.h" -#include "rpc/this_server.h" -#include "rpc/this_session.h" - -#include "rpc/detail/log.h" - -namespace rpc { -namespace detail { - -static constexpr std::size_t default_buffer_size = - rpc::constants::DEFAULT_BUFFER_SIZE; - -server_session::server_session(server *srv, RPCLIB_ASIO::io_service *io, - RPCLIB_ASIO::ip::tcp::socket socket, - std::shared_ptr disp, - bool suppress_exceptions) - : async_writer(io, std::move(socket)), - parent_(srv), - io_(io), - read_strand_(*io), - disp_(disp), - pac_(), - suppress_exceptions_(suppress_exceptions) { - pac_.reserve_buffer(default_buffer_size); // TODO: make this configurable - // [sztomi 2016-01-13] -} - -void server_session::start() { do_read(); } - -void server_session::close() { - LOG_INFO("Closing session."); - exit_ = true; - write_strand_.post([this]() { - socket_.close(); - parent_->close_session(shared_from_base()); - }); -} - -void server_session::do_read() { - auto self(shared_from_base()); - constexpr std::size_t max_read_bytes = default_buffer_size; - socket_.async_read_some( - RPCLIB_ASIO::buffer(pac_.buffer(), default_buffer_size), - // I don't think max_read_bytes needs to be captured explicitly - // (since it's constexpr), but MSVC insists. - read_strand_.wrap([this, self, max_read_bytes](std::error_code ec, - std::size_t length) { - if (exit_) { return; } - if (!ec) { - pac_.buffer_consumed(length); - RPCLIB_MSGPACK::unpacked result; - while (pac_.next(result) && !exit_) { - auto msg = result.get(); - output_buf_.clear(); - - // any worker thread can take this call - auto z = std::shared_ptr( - result.zone().release()); - io_->post([this, msg, z]() { - this_handler().clear(); - this_session().clear(); - this_session().set_id(reinterpret_cast(this)); - this_server().cancel_stop(); - - auto resp = disp_->dispatch(msg, suppress_exceptions_); - - // There are various things that decide what to send - // as a response. They have a precedence. - - // First, if the response is disabled, that wins - // So You Get Nothing, You Lose! Good Day Sir! - if (!this_handler().resp_enabled_) { - return; - } - - // Second, if there is an error set, we send that - // and only third, if there is a special response, we - // use it - if (!this_handler().error_.get().is_nil()) { - LOG_WARN("There was an error set in the handler"); - resp.capture_error(this_handler().error_); - } else if (!this_handler().resp_.get().is_nil()) { - LOG_WARN("There was a special result set in the " - "handler"); - resp.capture_result(this_handler().resp_); - } - - if (!resp.is_empty()) { -#ifdef _MSC_VER - // doesn't compile otherwise. - write_strand_.post( - [=]() { write(resp.get_data()); }); -#else - write_strand_.post( - [this, resp, z]() { write(resp.get_data()); }); -#endif - } - - if (this_session().exit_) { - LOG_WARN("Session exit requested from a handler."); - // posting through the strand so this comes after - // the previous write - write_strand_.post([this]() { exit_ = true; }); - } - - if (this_server().stopping_) { - LOG_WARN("Server exit requested from a handler."); - // posting through the strand so this comes after - // the previous write - write_strand_.post( - [this]() { parent_->close_sessions(); }); - } - }); - } - - if (!exit_) { - // resizing strategy: if the remaining buffer size is - // less than the maximum bytes requested from asio, - // then request max_read_bytes. This prompts the unpacker - // to resize its buffer doubling its size - // (https://github.com/msgpack/msgpack-c/issues/567#issuecomment-280810018) - if (pac_.buffer_capacity() < max_read_bytes) { - LOG_TRACE("Reserving extra buffer: {}", max_read_bytes); - pac_.reserve_buffer(max_read_bytes); - } - do_read(); - } - } else if (ec == RPCLIB_ASIO::error::eof || - ec == RPCLIB_ASIO::error::connection_reset) { - LOG_INFO("Client disconnected"); - self->close(); - } else { - LOG_ERROR("Unhandled error code: {} | '{}'", ec, ec.message()); - } - })); - if (exit_) { - socket_.close(); - } -} - -} /* detail */ -} /* rpc */ diff --git a/libraries/rpclib/src/rpc/server.cc b/libraries/rpclib/src/rpc/server.cc deleted file mode 100644 index 1012c6d96..000000000 --- a/libraries/rpclib/src/rpc/server.cc +++ /dev/null @@ -1,138 +0,0 @@ -#include "rpc/server.h" - -#include -#include -#include -#include -#include - -#include "asio.hpp" -#include "format.h" - -#include "rpc/detail/dev_utils.h" -#include "rpc/detail/log.h" -#include "rpc/detail/log.h" -#include "rpc/detail/server_session.h" -#include "rpc/detail/thread_group.h" - -using namespace rpc::detail; -using RPCLIB_ASIO::ip::tcp; -using namespace RPCLIB_ASIO; - -namespace rpc { - -struct server::impl { - impl(server *parent, std::string const &address, uint16_t port) - : parent_(parent), - io_(), - acceptor_(io_, - tcp::endpoint(ip::address::from_string(address), port)), - socket_(io_), - suppress_exceptions_(false) {} - - impl(server *parent, uint16_t port) - : parent_(parent), - io_(), - acceptor_(io_, tcp::endpoint(tcp::v4(), port)), - socket_(io_), - suppress_exceptions_(false) {} - - void start_accept() { - acceptor_.async_accept(socket_, [this](std::error_code ec) { - if (!ec) { - LOG_INFO("Accepted connection."); - auto s = std::make_shared( - parent_, &io_, std::move(socket_), parent_->disp_, - suppress_exceptions_); - s->start(); - sessions_.push_back(s); - } else { - LOG_ERROR("Error while accepting connection: {}", ec); - } - start_accept(); - // TODO: allow graceful exit [sztomi 2016-01-13] - }); - } - - void close_sessions() { - for (auto &session : sessions_) { - session->close(); - } - sessions_.clear(); - } - - void stop() { - io_.stop(); - loop_workers_.join_all(); - } - - server *parent_; - io_service io_; - ip::tcp::acceptor acceptor_; - ip::tcp::socket socket_; - rpc::detail::thread_group loop_workers_; - std::vector> sessions_; - std::atomic_bool suppress_exceptions_; - RPCLIB_CREATE_LOG_CHANNEL(server) -}; - -RPCLIB_CREATE_LOG_CHANNEL(server) - -server::server(uint16_t port) - : pimpl(new server::impl(this, port)), disp_(std::make_shared()) { - LOG_INFO("Created server on localhost:{}", port); - pimpl->start_accept(); -} - -server::server(server&& other) noexcept { - *this = std::move(other); -} - -server::server(std::string const &address, uint16_t port) - : pimpl(new server::impl(this, address, port)), - disp_(std::make_shared()) { - LOG_INFO("Created server on address {}:{}", address, port); - pimpl->start_accept(); -} - -server::~server() { - if (pimpl) { - pimpl->stop(); - } -} - -server& server::operator=(server &&other) { - pimpl = std::move(other.pimpl); - other.pimpl = nullptr; - disp_ = std::move(other.disp_); - other.disp_ = nullptr; - return *this; -} - -void server::suppress_exceptions(bool suppress) { - pimpl->suppress_exceptions_ = suppress; -} - -void server::run() { pimpl->io_.run(); } - -void server::async_run(std::size_t worker_threads) { - pimpl->loop_workers_.create_threads(worker_threads, [this]() { - name_thread("server"); - LOG_INFO("Starting"); - pimpl->io_.run(); - LOG_INFO("Exiting"); - }); -} - -void server::stop() { pimpl->stop(); } - -void server::close_sessions() { pimpl->close_sessions(); } - -void server::close_session(std::shared_ptr const &s) { - auto it = std::find(begin(pimpl->sessions_), end(pimpl->sessions_), s); - if (it != end(pimpl->sessions_)) { - pimpl->sessions_.erase(it); - } -} - -} /* rpc */ diff --git a/mbed-os-to-arduino b/mbed-os-to-arduino index 6f5dcb7e9..7b0ca54cd 100755 --- a/mbed-os-to-arduino +++ b/mbed-os-to-arduino @@ -183,7 +183,7 @@ generate_flags () { for fl in c cxx ld; do jq -r '.flags | .[] | select(. != "-MMD")' ./BUILD/"$BOARDNAME"/GCC_ARM${PROFILE}/.profile-${fl} \ > "$ARDUINOVARIANT"/${fl}flags.txt - if [[ $ARDUINOVARIANT == *PORTENTA* || $ARDUINOVARIANT == *GIGA* || $ARDUINOVARIANT == *NICLA_VISION* || $ARDUINOVARIANT == *OPTA* ]]; then + if [[ $ARDUINOVARIANT == *PORTENTA* || $ARDUINOVARIANT == *GIGA* || $ARDUINOVARIANT == *NICLA_VISION* || $ARDUINOVARIANT == *OPTA* || $ARDUINOVARIANT == *GENERIC*M4 ]]; then echo "Patching '-fno-exceptions' flag for $ARDUINOVARIANT/${fl}flags.txt" sed -i '/-fno-exceptions/d' "$ARDUINOVARIANT"/${fl}flags.txt set +e diff --git a/mbed-os-to-arduino-macos b/mbed-os-to-arduino-macos new file mode 100755 index 000000000..077a4d7d0 --- /dev/null +++ b/mbed-os-to-arduino-macos @@ -0,0 +1,448 @@ +#!/usr/bin/env bash + +########################################################################################### +# mbed-os-to-arduino (macOS Version) +# +# This is an adapted version of the original 'mbed-os-to-arduino' script +# specifically tailored for macOS systems. +# +# Prerequisites: +# - jq (Installation: brew install jq) +# - rsync (Installation: brew install rsync) +# - gcc-arm-embedded (Installation: brew install gcc-arm-embedded) +# - hg (Installation: brew install hg) +# - bash (Installation: brew install bash) +# - python (Installation: brew install python) +# - gnu-utils (Installation: brew install gnu-utils) +# - gnu-sed (Installation: brew install gnu-sed) +# - coreutils (Installation: brew install coreutils) +# - ArduinoCore-mbed requirements (Installation: pip install -r requirements.txt) +# +# Troubleshooting for hidapi installation issues: +# If during the installation of ArduinoCore-mbed requirements 'hidapi' installation fails, +# you can modify the 'requirements.txt' file as follows: +# 1. Open 'requirements.txt' in a text editor +# 2. Locate the line that specifies 'hidapi>=...' +# 3. Change it to 'hidapi' +# 4. Save the file +# 5. Rerun this script to install requirements +# +# Initial Author: Martino Facchin @facchinm +# Authors who have contributed to updates: +# - Giampaolo Mancini @manchoz +# - Leonardo Cavagnis @leonardocavagnis +# +########################################################################################### + +set -ef + +check_tools () { + echo -n "Checking for prerequisites..." + if not hash jq &>/dev/null ; then + echo "Please, install jq." + exit 1 + fi + + if not hash rsync &>/dev/null ; then + echo "Please, install rsync." + exit 1 + fi + echo " done." +} + +mbed_new () { + echo -n "Creating MbedOS Application..." + #always work in /tmp + cd /tmp/ + + if [ ! -d mbed-os-program ]; then + mbed new mbed-os-program + fi + cd mbed-os-program + echo " done." +} + +mbed_revision () { + echo -n "Checking out preferred 'mbed-os' version..." + if [ "$MBED_UPDATE" -eq 1 ]; then + echo -n " Updating to latest..." + set +e + mbed update + set -e + fi + + if [ -n "$REMOTE_BRANCH" ]; then + echo -n " Checking out remote branch $REMOTE_BRANCH..." + # checkout the mbed-os version you prefer... + cd mbed-os + git checkout "$REMOTE_BRANCH" + cd .. + fi + + if [ -n "$LOCAL_REPO" ]; then + echo -n " Linking local repo $LOCAL_REPO..." + # ... or link your local repo + if [ -d mbed-os ]; then + if [ ! -L mbed-os ]; then + rm -rf mbed-os + ln -s "$LOCAL_REPO" mbed-os + fi + fi + fi + echo " done." + +} + +create_mbed_program () { + echo -n "Setting up Mbed Application..." + rm -rf .mbedignore + + mbed target "$BOARDNAME" + mbed toolchain GCC_ARM + + cat > main.cpp << MAIN_C +#include "mbed.h" +int main() {} +MAIN_C + + if [ ! -f "$ARDUINOVARIANT"/conf/mbed_app.json ]; then + echo "================================================" + echo "Please, consider creating a 'conf/mbed_app.json'" + echo "to avoid mbed-cli always recompile from scratch." + echo "================================================" + cat > mbed_app.json << MBED_APP +{ + "macros": [ + "MBED_HEAP_STATS_ENABLED=1", + "MBED_STACK_STATS_ENABLED=1", + "MBED_MEM_TRACING_ENABLED=1" + ], + "target_overrides": { + "*": { + "platform.stdio-buffered-serial": true, + "platform.stdio-baud-rate": 115200, + "platform.default-serial-baud-rate": 115200, + "rtos.main-thread-stack-size": 32768 + } + } +} +MBED_APP + fi + + if [ -d "$ARDUINOVARIANT"/conf ]; then + find "$ARDUINOVARIANT"/conf/ -type f -exec gcp -p '{}' . ';' + fi + + echo " done." +} + + +apply_patches () { + if [ "$APPLY_PATCHES" -eq 1 ]; then + echo -n "Applying patches..." + if [ -d "$MBED_CORE_LOCATION"/patches ]; then + cd mbed-os + find "$MBED_CORE_LOCATION"/patches/ -type f -print0 | sort -z | xargs -t -0 -n1 git apply + cd - + fi + echo " done." + if [ "$RESTORE_GDB_INFO" -eq 1 ]; then + echo "Restoring gdb info (this increases libmbed binary size, not suitable for release)" + cd mbed-os + git checkout tools/profiles/develop.json + cd - + fi + fi +} + +mbed_compile () { + echo -n "Compiling Mbed Application..." + if [ "$MBED_CLEAN" -eq 1 ]; then + echo -n "Cleaning..." + rm -rf BUILD + fi + + PROFILE_FLAG="" + if [ x"$PROFILE" != x ]; then + if [ -f "$ARDUINOVARIANT/conf/profile/$PROFILE.json" ]; then + PROFILE_FLAG=--profile="$ARDUINOVARIANT"/conf/profile/$PROFILE.json + else + PROFILE_FLAG=--profile="${PROFILE}" + fi + export PROFILE=-${PROFILE^^} + fi + + mbed compile $PROFILE_FLAG --source . -v \ + | tee >(cat | grep 'Compile \[' >&2) | grep "Macros:" > "$BOARDNAME".macros.txt + echo " done." +} + +generate_defines () { + echo -n "Generating defines..." + cut -f2 -d":" < "$BOARDNAME".macros.txt | tr ' ' '\n' | gsed 's#\"#\\"#g' | sort > "$ARDUINOVARIANT"/defines.txt + echo "-DMBED_NO_GLOBAL_USING_DIRECTIVE=1" >> "$ARDUINOVARIANT"/defines.txt + MAJOR=$(echo $VERSION| cut -d'.' -f 1) + MINOR=$(echo $VERSION| cut -d'.' -f 2) + PATCH=$(echo $VERSION| cut -d'.' -f 3) + echo "-DCORE_MAJOR=$MAJOR" >> "$ARDUINOVARIANT"/defines.txt + echo "-DCORE_MINOR=$MINOR" >> "$ARDUINOVARIANT"/defines.txt + echo "-DCORE_PATCH=$PATCH" >> "$ARDUINOVARIANT"/defines.txt + if [ -f "$ARDUINOVARIANT"/variant.cpp ]; then + echo '-DUSE_ARDUINO_PINOUT' >> "$ARDUINOVARIANT"/defines.txt + fi + echo " done." +} + +generate_includes () { + echo -n "Generating includes..." + + find ./BUILD/"$BOARDNAME"/GCC_ARM${PROFILE}/ -type f -name '.include*' -print0 | xargs -0 cat \ + | tr ' ' '\n' | tr -d '"' | gsed -e 's#-I./mbed-os#-iwithprefixbefore/mbed#g' \ + | gsed '/^-I./d' | gsed '/lwipstack/d' | cat \ + > "$ARDUINOVARIANT"/includes.txt + + echo -n " copying to destination... " + + cd mbed-os + cut -d'/' -f3- < "$ARDUINOVARIANT"/includes.txt | grep 'targets' \ + | xargs -I{} find {} -maxdepth 2 -name '*.h' \ + | xargs -I{} gcp --parent {} "$ARDUINOCOREMBED"/ + cd - + + echo " done." +} + +generate_flags () { + echo -n "Generating flags..." + for fl in c cxx ld; do + jq -r '.flags | .[] | select(. != "-MMD")' ./BUILD/"$BOARDNAME"/GCC_ARM${PROFILE}/.profile-${fl} \ + > "$ARDUINOVARIANT"/${fl}flags.txt + if [[ $ARDUINOVARIANT == *PORTENTA* || $ARDUINOVARIANT == *GIGA* || $ARDUINOVARIANT == *NICLA_VISION* || $ARDUINOVARIANT == *OPTA* ]]; then + echo "Patching '-fno-exceptions' flag for $ARDUINOVARIANT/${fl}flags.txt" + gsed -i '/-fno-exceptions/d' "$ARDUINOVARIANT"/${fl}flags.txt + set +e + HAS_OPENAMP_SECTION=`grep openamp_section "$ARDUINOVARIANT"/linker_script.ld` + set -e + if [ x"$HAS_OPENAMP_SECTION" == x ]; then + echo "Adding OpenAMP section to $ARDUINOVARIANT/linker_script.ld" + OPENAMP_SECTION=".openamp_section (NOLOAD) : {\n \ + . = ABSOLUTE(0x38000000);\n \ + *(.resource_table)\n \ + } >RAM_D3 AT > FLASH\n \ + .pdm_section (NOLOAD) : {\n \ + . = ABSOLUTE(0x3800FC00);\n \ + *(.pdm_buffer)\n \ + } > RAM_D3\n" + + if [[ $ARDUINOVARIANT == *PORTENTA*M7* || $ARDUINOVARIANT == *GIGA* || $ARDUINOVARIANT == *OPTA* ]]; then + OPENAMP_SECTION="${OPENAMP_SECTION} \ + _dtcm_lma = __etext + SIZEOF(.data);\n \ + .dtcm : AT(_dtcm_lma) {\n \ + _sdtcm = .;\n \ + *(.dtcm*)\n \ + _edtcm = .;\n \ + } > DTCMRAM" + fi + + gsed -i "s?.heap (COPY):?${OPENAMP_SECTION}\n .heap (COPY):?g" $ARDUINOVARIANT/linker_script.ld + OPENAMP_REGIONS="__OPENAMP_region_start__ = 0x38000400;\n__OPENAMP_region_end__ = 0x38000400 + LENGTH(RAM_D3) - 1K;" + gsed -i "s?ENTRY(Reset_Handler)?${OPENAMP_REGIONS}\nENTRY(Reset_Handler)?g" $ARDUINOVARIANT/linker_script.ld + fi + echo "Patching linker scripts" + gsed -i 's/0x8100000/CM4_BINARY_START/g' "$ARDUINOVARIANT"/linker_script.ld + gsed -i 's/LENGTH = 0x200000/LENGTH = CM4_BINARY_END - CM4_BINARY_START/g' "$ARDUINOVARIANT"/linker_script.ld + gsed -i 's/LENGTH = 0x1c0000/LENGTH = CM4_BINARY_START - 0x8040000/g' "$ARDUINOVARIANT"/linker_script.ld + fi + if [[ $ARDUINOVARIANT == *NANO_RP2040* ]]; then + set +e + HAS_2NDSTAGE_SECTION=`grep second_stage_ota "$ARDUINOVARIANT"/linker_script.ld` + set -e + if [ x"$HAS_2NDSTAGE_SECTION" == x ]; then + echo "Adding second stage bootloader section to Nano RP2040 Connect" + SECOND_STAGE_SECTION=".second_stage_ota : {\n \ + KEEP (*(.second_stage_ota))\n \ + } > FLASH" + gsed -i "s?.flash_begin?${SECOND_STAGE_SECTION}\n .flash_begin?g" $ARDUINOVARIANT/linker_script.ld + fi + fi + done + echo " done." +} + +generate_libs () { + echo -n "Generating libs..." + tr ' ' '\n' < ./BUILD/"$BOARDNAME"/GCC_ARM${PROFILE}/.link_options.txt | grep "\.o" | grep -v "/main\.o" \ + | xargs arm-none-eabi-ar rcs ./BUILD/mbed-core-"$BOARDNAME".a + + gcp ./BUILD/mbed-core-"$BOARDNAME".a "$ARDUINOVARIANT"/libs/libmbed.a + gcp ./BUILD/"$BOARDNAME"/GCC_ARM${PROFILE}/.link_script.ld "$ARDUINOVARIANT"/linker_script.ld + gcp ./BUILD/"$BOARDNAME"/GCC_ARM${PROFILE}/mbed_config.h "$ARDUINOVARIANT"/ + + gsed -i "s/custom_mbedtls_config.h/conf\/custom_mbedtls_config.h/" $ARDUINOVARIANT/mbed_config.h + + # TODO: discover needed libraries based on compile target + #find -L . -name 'lib*.a' -exec cp '{}' "$ARDUINOVARIANT"/libs/ ';' + echo " done." +} + +copy_core_files () { + echo -n "Copying generic MbedOS headers to core... " + + rsync -zar --exclude="targets/" --exclude="*TEST*/" --include="*/" --include="*.h" --exclude="*" \ + mbed-os/ "$ARDUINOCOREMBED"/ + + rsync -zar --exclude="targets/" --exclude="*TEST*/" --include="*/" --include="mstd_*" --exclude="*" \ + mbed-os/ "$ARDUINOCOREMBED"/ + + echo " done." +} + +patch_mbed_h () { + echo -n "Patching 'mbed.h'..." + if [ x`uname` == xLinux ]; then + gsed -i 's?#include "platform/mbed_version.h"?#include "platform/mbed_version.h"\n#include "mbed_config.h"?g' \ + "$ARDUINOCOREMBED"/mbed.h + else + ed "$ARDUINOCOREMBED"/mbed.h >/dev/null < .mbedignore +# #add ARDUINO_AS_MBED_LIBRARY=1 to macros section in mbed_app.json +# echo "https://github.com/arduino/ArduinoCore-mbed#bf6e64771ebe20285b0364756dff856ebbc679dc" > arduino.lib diff --git a/nicla.variables b/nicla.variables index 3952028a8..c894e0366 100644 --- a/nicla.variables +++ b/nicla.variables @@ -1,5 +1,5 @@ export FLAVOUR="nicla" -export VARIANTS=("NICLA NICLA_VISION PORTENTA_H7_M4") +export VARIANTS=("NICLA NICLA_VISION GENERIC_STM32H747_M4") export FQBNS=("nicla_sense nicla_voice nicla_vision") export LIBRARIES=("SPI Wire Scheduler Nicla_System WiFi ea_malloc openamp_arduino STM32H747_System ThreadDebug GC2145 Himax_HM01B0 PDM KernelDebug RPC USBHID Camera rpclib USBHOST mbed-memory-status USBMSD SocketWrapper MRI SE05X MLC NDP syntiant_ilib") export BOOTLOADERS=("NICLA NICLA_VISION NICLA_VOICE") diff --git a/opta.variables b/opta.variables index 593a7dd3b..dc36376d6 100755 --- a/opta.variables +++ b/opta.variables @@ -1,5 +1,5 @@ export FLAVOUR="opta" -export VARIANTS=("OPTA PORTENTA_H7_M4") +export VARIANTS=("OPTA GENERIC_STM32H747_M4") export FQBNS=("opta") export LIBRARIES=("Ethernet SPI WiFi openamp_arduino ThreadDebug KernelDebug RPC USBHID Wire rpclib USBHOST mbed-memory-status Scheduler USBMSD SocketWrapper STM32H747_System MRI") export BOOTLOADERS=("OPTA") diff --git a/package_full.sh b/package_full.sh index 4a32b2668..00e3dad29 100755 --- a/package_full.sh +++ b/package_full.sh @@ -1,5 +1,5 @@ #Get version from git(hub) tag -export VERSION="4.0.8" +export VERSION="4.0.10" FLAVOURS=`ls *.variables` diff --git a/patches/0208-STM32-fix-HRTIM-pwm-init-and-corner-case-31.patch b/patches/0208-STM32-fix-HRTIM-pwm-init-and-corner-case-31.patch new file mode 100644 index 000000000..fe37db1be --- /dev/null +++ b/patches/0208-STM32-fix-HRTIM-pwm-init-and-corner-case-31.patch @@ -0,0 +1,113 @@ +From 3636262ae786ae623451985dd40c7a54c40b9ab1 Mon Sep 17 00:00:00 2001 +From: Leonardo Cavagnis <45899760+leonardocavagnis@users.noreply.github.com> +Date: Fri, 29 Sep 2023 10:06:55 +0200 +Subject: [PATCH] STM32: fix HRTIM pwm init and corner case (#31) + +* STM32: fix HRTIM pwm corner cases (0-100%) in read function + +* STM32: fix HRTIM pwm init with default values + +* STM32: add helper fun to manage pwmout obj period +--- + targets/TARGET_STM/pwmout_api.c | 59 +++++++++++++++++++++------------ + 1 file changed, 38 insertions(+), 21 deletions(-) + +diff --git a/targets/TARGET_STM/pwmout_api.c b/targets/TARGET_STM/pwmout_api.c +index e20ac918a3..71a4839728 100644 +--- a/targets/TARGET_STM/pwmout_api.c ++++ b/targets/TARGET_STM/pwmout_api.c +@@ -53,6 +53,8 @@ static hrtim_t hrtim_timer; + static HRTIM_HandleTypeDef HrtimHandle; + static HRTIM_CompareCfgTypeDef sConfig_compare; + static HRTIM_TimeBaseCfgTypeDef sConfig_time_base; ++ ++static void _pwmout_obj_period_us(pwmout_t *obj, int us); + #endif + + /* Convert STM32 Cube HAL channel to LL channel */ +@@ -142,9 +144,9 @@ static void _pwmout_init_direct(pwmout_t *obj, const PinMap *pinmap) + pin_function(pinmap->pin, pinmap->function); + pin_mode(pinmap->pin, PullNone); + +- obj->period = 0; +- obj->pulse = 0; +- obj->prescaler = 0; ++ // Initialize obj with default values (period 550Hz, duty 0%) ++ _pwmout_obj_period_us(obj, 18000); ++ obj->pulse = (uint32_t)((float)obj->period * 1.0 + 0.5); + + // Initialize the HRTIM structure + HrtimHandle.Instance = HRTIM1; +@@ -444,6 +446,15 @@ float pwmout_read(pwmout_t *obj) + if (obj->period > 0) { + value = (float)(obj->pulse) / (float)(obj->period); + } ++ ++ if (obj->pwm == PWM_I) { ++ if (value <= (float)0.0) { ++ value = 1.0; ++ } else if (value >= (float)1.0) { ++ value = 0.0; ++ } ++ } ++ + return ((value > (float)1.0) ? (float)(1.0) : (value)); + } + +@@ -464,24 +475,7 @@ void pwmout_period_us(pwmout_t *obj, int us) + if (obj->pwm == PWM_I) { + float dc = pwmout_read(obj); + +- uint32_t frequency; +- uint32_t clocksource = __HAL_RCC_GET_HRTIM1_SOURCE(); +- switch (clocksource) { +- case RCC_HRTIM1CLK_TIMCLK: +- frequency = HAL_RCC_GetHCLKFreq(); +- break; +- case RCC_HRTIM1CLK_CPUCLK: +- frequency = HAL_RCC_GetSysClockFreq(); +- break; +- } +- +- /* conversion from us to clock tick */ +- obj->period = us * (frequency / 1000000) / 4; +- obj->prescaler = HRTIM_PRESCALERRATIO_DIV4; +- +- if (obj->period > 0xFFDFU) { +- obj->period = 0xFFDFU; +- } ++ _pwmout_obj_period_us(obj, us); + + sConfig_time_base.Mode = HRTIM_MODE_CONTINUOUS; + sConfig_time_base.Period = obj->period; +@@ -602,4 +596,27 @@ const PinMap *pwmout_pinmap() + return PinMap_PWM; + } + ++#if defined(HRTIM1) ++void _pwmout_obj_period_us(pwmout_t *obj, int us) { ++ uint32_t frequency; ++ uint32_t clocksource = __HAL_RCC_GET_HRTIM1_SOURCE(); ++ switch (clocksource) { ++ case RCC_HRTIM1CLK_TIMCLK: ++ frequency = HAL_RCC_GetHCLKFreq(); ++ break; ++ case RCC_HRTIM1CLK_CPUCLK: ++ frequency = HAL_RCC_GetSysClockFreq(); ++ break; ++ } ++ ++ /* conversion from us to clock tick */ ++ obj->period = us * (frequency / 1000000) / 4; ++ obj->prescaler = HRTIM_PRESCALERRATIO_DIV4; ++ ++ if (obj->period > 0xFFDFU) { ++ obj->period = 0xFFDFU; ++ } ++} ++#endif ++ + #endif +-- +2.42.0 + diff --git a/patches/0209-gcc-callback-prevent-wrong-optimizations.patch b/patches/0209-gcc-callback-prevent-wrong-optimizations.patch new file mode 100644 index 000000000..0902dabf6 --- /dev/null +++ b/patches/0209-gcc-callback-prevent-wrong-optimizations.patch @@ -0,0 +1,39 @@ +From 28a199761f80a8400da5cac8fbcaf138d29ea596 Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Mon, 13 Nov 2023 09:40:06 +0100 +Subject: [PATCH 209/217] gcc: callback: prevent wrong optimizations + +Porting of https://github.com/arduino/ArduinoCore-mbed/pull/755 +--- + platform/include/platform/Callback.h | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/platform/include/platform/Callback.h b/platform/include/platform/Callback.h +index e76a4f1979..3df0b9117f 100644 +--- a/platform/include/platform/Callback.h ++++ b/platform/include/platform/Callback.h +@@ -26,6 +26,14 @@ + #include + #include + ++#pragma GCC push_options ++// This prevents the GCC compiler from applying optimizations that assume the code follows strict aliasing rules. ++// In order to prevent bugs arising from undefined behavior that is tricky to find in the Callback implementation, ++// or simply from compiler bugs in GCC. ++#pragma GCC optimize("-fno-strict-aliasing") ++// This prevents the GCC compiler from generating incorrect inline code for the Callback constructor. ++#pragma GCC optimize("-fno-inline") ++ + // Controlling switches from config: + // MBED_CONF_PLATFORM_CALLBACK_NONTRIVIAL - support storing non-trivial function objects + // MBED_CONF_PLATFORM_CALLBACK_COMPARABLE - support memcmp comparing stored objects (requires zero padding) +@@ -835,4 +843,6 @@ Callback(R(*func)(const volatile T *, ArgTs...), const volatile U *arg) -> Callb + + } // namespace mbed + ++#pragma GCC pop_options ++ + #endif +-- +2.42.0 + diff --git a/patches/0209-portenta_h7-make-sure-configuration-is-only-executed.patch b/patches/0209-portenta_h7-make-sure-configuration-is-only-executed.patch new file mode 100644 index 000000000..54c977788 --- /dev/null +++ b/patches/0209-portenta_h7-make-sure-configuration-is-only-executed.patch @@ -0,0 +1,53 @@ +From 547edd2014933a15cd0e48fe1f2f5f9b9ce094fd Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Thu, 26 Oct 2023 16:37:54 +0200 +Subject: [PATCH 209/213] portenta_h7: make sure configuration is only executed + by M7 + +--- + .../TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp | 3 ++- + .../TARGET_PORTENTA_H7/system_clock_override.c | 2 ++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp +index 13ba1042de..59e6ac6cca 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp +@@ -26,6 +26,7 @@ + ******************************************************************************/ + void enableEthPowerSupply(void) + { ++#ifndef CORE_CM4 + /* Ensure ETH power supply */ + mbed::I2C i2c(PB_7, PB_6); + +@@ -48,5 +49,5 @@ void enableEthPowerSupply(void) + data[0] = 0x35; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); +- ++#endif + } +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c +index ae7821ede0..e47b7d258c 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c +@@ -129,6 +129,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) + } + } + ++#ifndef CORE_CM4 + /* Enable oscillator pin */ + __HAL_RCC_GPIOH_CLK_ENABLE(); + GPIO_InitTypeDef gpio_osc_init_structure; +@@ -139,6 +140,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) + HAL_GPIO_Init(GPIOH, &gpio_osc_init_structure); + HAL_Delay(10); + HAL_GPIO_WritePin(GPIOH, GPIO_PIN_1, 1); ++#endif + + /* Supply configuration update enable */ + #if HSE_VALUE == 27000000 +-- +2.42.0 + diff --git a/patches/0210-giga-remove-stray-function.patch b/patches/0210-giga-remove-stray-function.patch new file mode 100644 index 000000000..45718f6b3 --- /dev/null +++ b/patches/0210-giga-remove-stray-function.patch @@ -0,0 +1,44 @@ +From cb4587fa30a8f49bf27a16dda20fb21947d385ed Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Thu, 26 Oct 2023 16:38:15 +0200 +Subject: [PATCH 210/213] giga: remove stray function + +--- + .../TARGET_GIGA/giga_power.cpp | 23 ------------------- + 1 file changed, 23 deletions(-) + +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp +index a47a758e1d..1954ff50cc 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp +@@ -26,27 +26,4 @@ + ******************************************************************************/ + void enableEthPowerSupply(void) + { +- /* Ensure ETH power supply */ +- mbed::I2C i2c(PB_7, PB_6); +- +- char data[2]; +- +- // LDO3 to 1.2V +- data[0] = 0x52; +- data[1] = 0x9; +- i2c.write(8 << 1, data, sizeof(data)); +- data[0] = 0x53; +- data[1] = 0xF; +- i2c.write(8 << 1, data, sizeof(data)); +- +- // SW2 to 3.3V (SW2_VOLT) +- data[0] = 0x3B; +- data[1] = 0xF; +- i2c.write(8 << 1, data, sizeof(data)); +- +- // SW1 to 3.0V (SW1_VOLT) +- data[0] = 0x35; +- data[1] = 0xF; +- i2c.write(8 << 1, data, sizeof(data)); +- + } +-- +2.42.0 + diff --git a/patches/0211-stm32h7-dual-core-allow-override-of-HAL_RCC_GetSysCl.patch b/patches/0211-stm32h7-dual-core-allow-override-of-HAL_RCC_GetSysCl.patch new file mode 100644 index 000000000..2b9e1fadc --- /dev/null +++ b/patches/0211-stm32h7-dual-core-allow-override-of-HAL_RCC_GetSysCl.patch @@ -0,0 +1,27 @@ +From f0fb6a21e7eb398c0b7279bce7859ae77debcc64 Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Thu, 26 Oct 2023 16:39:04 +0200 +Subject: [PATCH 211/213] stm32h7 dual core: allow override of + HAL_RCC_GetSysClockFreq + +It's the only needed entry point to get the right timings for all peripherals +--- + .../STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c +index eb5485dc7d..f03be381a4 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c ++++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c +@@ -1354,7 +1354,7 @@ void HAL_RCC_DisableCSS(void) + * + * @retval SYSCLK frequency + */ +-uint32_t HAL_RCC_GetSysClockFreq(void) ++__attribute__((weak)) uint32_t HAL_RCC_GetSysClockFreq(void) + { + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue; + float_t fracn1, pllvco; +-- +2.42.0 + diff --git a/patches/0212-ble-remove-stray-specializations.patch b/patches/0212-ble-remove-stray-specializations.patch new file mode 100644 index 000000000..788377bc2 --- /dev/null +++ b/patches/0212-ble-remove-stray-specializations.patch @@ -0,0 +1,238 @@ +From 46653cb9d8015361327cb0a8f9b394d6c008c841 Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Thu, 26 Oct 2023 16:39:59 +0200 +Subject: [PATCH 212/213] ble: remove stray specializations + +the standard one from Cypress driver is fine +--- + .../TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp | 105 ------------------ + .../TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp | 105 ------------------ + 2 files changed, 210 deletions(-) + delete mode 100644 connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp + delete mode 100644 connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp + +diff --git a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp +deleted file mode 100644 +index 2d668fed9c..0000000000 +--- a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp ++++ /dev/null +@@ -1,105 +0,0 @@ +-/******************************************************************************* +-* \file cy_bt_cordio_cfg.cpp +-* \version 1.0 +-* +-* +-* Low Power Assist BT Pin configuration implementation. +-* +-******************************************************************************** +-* \copyright +-* Copyright 2019 Cypress Semiconductor Corporation +-* SPDX-License-Identifier: Apache-2.0 +-* +-* Licensed under the Apache License, Version 2.0 (the "License"); +-* you may not use this file except in compliance with the License. +-* You may obtain a copy of the License at +-* +-* http://www.apache.org/licenses/LICENSE-2.0 +-* +-* Unless required by applicable law or agreed to in writing, software +-* distributed under the License is distributed on an "AS IS" BASIS, +-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-* See the License for the specific language governing permissions and +-* limitations under the License. +-*******************************************************************************/ +- +-#include +-#include "ble/driver/CordioHCIDriver.h" +-#include "hci_api.h" +-#include "hci_cmd.h" +-#include "hci_core.h" +-#include "bstream.h" +-#include "assert.h" +-#include +-#include "hci_mbed_os_adaptation.h" +-#include "CyH4TransportDriver.h" +- +-#define cyhal_gpio_to_rtos(x) (x) +-#define CYCFG_BT_LP_ENABLED (1) +-#define CYCFG_BT_HOST_WAKE_IRQ_EVENT WAKE_EVENT_ACTIVE_LOW +-#define CYCFG_BT_DEV_WAKE_POLARITY WAKE_EVENT_ACTIVE_LOW +- +-/******************************************************************************* +-* Function Name: ble_cordio_get_h4_transport_driver +-******************************************************************************** +-* +-* Strong implementation of function which calls CyH4TransportDriver constructor and return it +-* +-* \param none +-* +-* \return +-* Returns the transport driver object +-*******************************************************************************/ +-ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_h4_transport_driver() +-{ +-#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) +- +-#if (defined(CYCFG_BT_LP_ENABLED)) +- if (CYCFG_BT_LP_ENABLED) { +- static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( +- /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), +- /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), +- /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), +- /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), +- /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), +- DEF_BT_BAUD_RATE, +- cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), +- cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE), +- CYCFG_BT_HOST_WAKE_IRQ_EVENT, +- CYCFG_BT_DEV_WAKE_POLARITY +- ); +- return s_transport_driver; +- } else { /* CYCFG_BT_LP_ENABLED */ +- static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( +- /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), +- /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), +- /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), +- /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), +- /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), +- DEF_BT_BAUD_RATE); +- return s_transport_driver; +- } +-#else /* (defined(CYCFG_BT_LP_ENABLED)) */ +- static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( +- /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), +- /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), +- /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), +- /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), +- /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), +- DEF_BT_BAUD_RATE), +- cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE) +- ); +- return s_transport_driver; +-#endif /* (defined(CYCFG_BT_LP_ENABLED)) */ +- +-#else /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ +- static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( +- /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), +- /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), +- /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), +- /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), +- /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), +- DEF_BT_BAUD_RATE); +- return s_transport_driver; +-#endif /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ +-} +diff --git a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp +deleted file mode 100644 +index 2d668fed9c..0000000000 +--- a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp ++++ /dev/null +@@ -1,105 +0,0 @@ +-/******************************************************************************* +-* \file cy_bt_cordio_cfg.cpp +-* \version 1.0 +-* +-* +-* Low Power Assist BT Pin configuration implementation. +-* +-******************************************************************************** +-* \copyright +-* Copyright 2019 Cypress Semiconductor Corporation +-* SPDX-License-Identifier: Apache-2.0 +-* +-* Licensed under the Apache License, Version 2.0 (the "License"); +-* you may not use this file except in compliance with the License. +-* You may obtain a copy of the License at +-* +-* http://www.apache.org/licenses/LICENSE-2.0 +-* +-* Unless required by applicable law or agreed to in writing, software +-* distributed under the License is distributed on an "AS IS" BASIS, +-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-* See the License for the specific language governing permissions and +-* limitations under the License. +-*******************************************************************************/ +- +-#include +-#include "ble/driver/CordioHCIDriver.h" +-#include "hci_api.h" +-#include "hci_cmd.h" +-#include "hci_core.h" +-#include "bstream.h" +-#include "assert.h" +-#include +-#include "hci_mbed_os_adaptation.h" +-#include "CyH4TransportDriver.h" +- +-#define cyhal_gpio_to_rtos(x) (x) +-#define CYCFG_BT_LP_ENABLED (1) +-#define CYCFG_BT_HOST_WAKE_IRQ_EVENT WAKE_EVENT_ACTIVE_LOW +-#define CYCFG_BT_DEV_WAKE_POLARITY WAKE_EVENT_ACTIVE_LOW +- +-/******************************************************************************* +-* Function Name: ble_cordio_get_h4_transport_driver +-******************************************************************************** +-* +-* Strong implementation of function which calls CyH4TransportDriver constructor and return it +-* +-* \param none +-* +-* \return +-* Returns the transport driver object +-*******************************************************************************/ +-ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_h4_transport_driver() +-{ +-#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) +- +-#if (defined(CYCFG_BT_LP_ENABLED)) +- if (CYCFG_BT_LP_ENABLED) { +- static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( +- /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), +- /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), +- /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), +- /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), +- /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), +- DEF_BT_BAUD_RATE, +- cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), +- cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE), +- CYCFG_BT_HOST_WAKE_IRQ_EVENT, +- CYCFG_BT_DEV_WAKE_POLARITY +- ); +- return s_transport_driver; +- } else { /* CYCFG_BT_LP_ENABLED */ +- static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( +- /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), +- /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), +- /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), +- /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), +- /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), +- DEF_BT_BAUD_RATE); +- return s_transport_driver; +- } +-#else /* (defined(CYCFG_BT_LP_ENABLED)) */ +- static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( +- /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), +- /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), +- /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), +- /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), +- /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), +- DEF_BT_BAUD_RATE), +- cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE) +- ); +- return s_transport_driver; +-#endif /* (defined(CYCFG_BT_LP_ENABLED)) */ +- +-#else /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ +- static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( +- /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), +- /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), +- /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), +- /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), +- /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), +- DEF_BT_BAUD_RATE); +- return s_transport_driver; +-#endif /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ +-} +-- +2.42.0 + diff --git a/patches/0213-stm32h747_m4-implement-a-standalone-target.patch b/patches/0213-stm32h747_m4-implement-a-standalone-target.patch new file mode 100644 index 000000000..7e0223455 --- /dev/null +++ b/patches/0213-stm32h747_m4-implement-a-standalone-target.patch @@ -0,0 +1,34503 @@ +From 918979ba0f901fb59b4c684358ba504d60d060b1 Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Thu, 26 Oct 2023 16:41:10 +0200 +Subject: [PATCH 213/213] stm32h747_m4: implement a standalone target + +--- + .../COMPONENT_CYW43XXX/CMakeLists.txt | 4 + + .../firmware/CMakeLists.txt | 6 + + .../COMPONENT_4343W_FS/CMakeLists.txt | 7 + + .../w_bt_firmware_controller.c | 2101 ++ + .../COMPONENT_WHD/CMakeLists.txt | 34 + + .../COMPONENT_WHD/generated_mac_address.txt | 9 + + .../COMPONENT_WHD/interface/cy_result.h | 228 + + .../COMPONENT_WHD/interface/cyabs_rtos.h | 711 + + .../COMPONENT_WHD/interface/cyabs_rtos_impl.h | 77 + + .../interface/cyabs_rtos_rtxv5.c | 863 + + .../COMPONENT_WHD/interface/cyhal_gpio.h | 247 + + .../COMPONENT_WHD/interface/cyhal_sdio.h | 366 + + .../COMPONENT_WHD/interface/cyhal_spi.h | 383 + + .../COMPONENT_WHD/port/cy_hal.c | 63 + + .../COMPONENT_WHD/port/cy_syslib.h | 592 + + .../COMPONENT_WHD/port/cy_utils.h | 81 + + .../COMPONENT_WHD/port/cybsp.h | 50 + + .../COMPONENT_WHD/port/cycfg.h | 20 + + .../COMPONENT_WHD/port/cyhal.h | 52 + + .../COMPONENT_WHD/port/cyhal_gpio.cpp | 104 + + .../COMPONENT_WHD/port/cyhal_hw_types.h | 112 + + .../COMPONENT_WHD/port/cyhal_sdio.c | 506 + + .../COMPONENT_WHD/port/cyhal_spi.c | 29 + + .../COMPONENT_WHD/port/cyhal_system.h | 20 + + .../COMPONENT_WHD/port/wiced_bd.h | 49 + + .../COMPONENT_WHD/port/wiced_filesystem.cpp | 225 + + .../COMPONENT_WHD/port/wiced_filesystem.h | 148 + + .../LICENSE-permissive-binary-license-1.0.txt | 49 + + .../firmware/COMPONENT_4343W_FS/4343WA1_bin.c | 25493 ++++++++++++++++ + .../COMPONENT_4343W_FS/4343WA1_clm_blob.c | 400 + + .../firmware/COMPONENT_4343W_FS/resources.h | 30 + + .../resources/nvram/wifi_nvram_image.h | 87 + + .../COMPONENT_WHD/whd_config.h | 61 + + .../PeripheralPins.c | 578 + + .../TARGET_GENERIC_STM32H747_M4/PinNames.h | 356 + + targets/targets.json | 50 +- + 36 files changed, 34179 insertions(+), 12 deletions(-) + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/CMakeLists.txt + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/CMakeLists.txt + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/CMakeLists.txt + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/generated_mac_address.txt + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cy_result.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_impl.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_gpio.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_sdio.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_spi.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_hal.c + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_syslib.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_utils.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cybsp.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cycfg.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_gpio.cpp + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_hw_types.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_sdio.c + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_spi.c + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_system.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_bd.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.cpp + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/whd_config.h + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PeripheralPins.c + create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PinNames.h + +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/CMakeLists.txt +new file mode 100644 +index 0000000000..82be36e1f0 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/CMakeLists.txt +@@ -0,0 +1,4 @@ ++# Copyright (c) 2020 ARM Limited. All rights reserved. ++# SPDX-License-Identifier: Apache-2.0 ++ ++add_subdirectory(firmware) +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/CMakeLists.txt +new file mode 100644 +index 0000000000..fbbc3b979d +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/CMakeLists.txt +@@ -0,0 +1,6 @@ ++# Copyright (c) 2020 ARM Limited. All rights reserved. ++# SPDX-License-Identifier: Apache-2.0 ++ ++if("4343W_FS" IN_LIST MBED_TARGET_LABELS) ++ add_subdirectory(COMPONENT_4343W) ++endif() +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt +new file mode 100644 +index 0000000000..31fecb8fe0 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt +@@ -0,0 +1,7 @@ ++# Copyright (c) 2020 ARM Limited. All rights reserved. ++# SPDX-License-Identifier: Apache-2.0 ++ ++target_sources(mbed-ble ++ INTERFACE ++ w_bt_firmware_controller.c ++) +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c +new file mode 100644 +index 0000000000..ac2bc973e1 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c +@@ -0,0 +1,2101 @@ ++/* ++ * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved ++ * SPDX-License-Identifier: LicenseRef-PBL ++ * ++ * This file and the related binary are licensed under the ++ * Permissive Binary License, Version 1.0 (the "License"); ++ * you may not use these files except in compliance with the License. ++ * ++ * You may obtain a copy of the License here: ++ * LICENSE-permissive-binary-license-1.0.txt and at ++ * https://www.mbed.com/licenses/PBL-1.0 ++ * ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++#include ++ ++/* labelling: appname-(chipname)(stepping)-frequency-(headset GIT SHA)-(generating SDK version)- ++ * Wiced-release.hcd */ ++const char brcm_patch_version[] = "BCM4343A1_001.002.009.0083.0000_Generic_UART_37_4MHz_wlbga_wiced"; ++const uint8_t brcm_patchram_format = 0x01; ++/* Configuration Data Records (Write_RAM) */ ++const uint8_t brcm_patchram_buf[] = { ++ 76, 252, 70, 16, 24, 33, 0, 66, 82, 67, 77, 99, 102, 103, 83, 0, 0, ++ 0, 0, 50, 0, 0, 0, 1, 1, 4, 24, 146, 0, 0, 0, 3, 6, 172, 31, 18, 161, ++ 67, 67, 0, 1, 28, 82, 24, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 254, 0, 0, 76, 252, 255, 82, 24, ++ 33, 0, 66, 82, 67, 77, 99, 102, 103, 68, 0, 0, 0, 0, 79, 133, 0, 0, ++ 3, 3, 40, 66, 67, 77, 52, 51, 52, 51, 65, 49, 32, 85, 65, 82, 84, 32, ++ 51, 55, 46, 52, 32, 77, 72, 122, 32, 119, 108, 98, 103, 97, 95, 114, ++ 101, 102, 32, 119, 105, 99, 101, 100, 0, 22, 3, 2, 83, 0, 2, 1, 248, ++ 3, 8, 1, 50, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 50, 0, 255, 15, 0, 0, ++ 98, 8, 0, 0, 112, 0, 100, 0, 128, 0, 0, 0, 128, 0, 0, 0, 172, 0, 50, ++ 0, 255, 255, 255, 1, 0, 0, 47, 0, 140, 0, 50, 0, 0, 240, 255, 15, 0, ++ 16, 17, 1, 120, 0, 50, 0, 255, 255, 255, 255, 185, 184, 184, 184, 96, ++ 44, 32, 0, 255, 0, 0, 0, 0, 0, 0, 0, 16, 1, 50, 0, 0, 0, 255, 255, 0, ++ 0, 24, 24, 108, 1, 96, 0, 255, 255, 255, 255, 11, 0, 0, 0, 112, 1, 96, ++ 0, 255, 255, 255, 255, 16, 0, 0, 0, 116, 1, 96, 0, 255, 255, 255, 255, ++ 21, 0, 0, 0, 120, 1, 96, 0, 255, 255, 255, 255, 25, 0, 0, 0, 124, 1, ++ 96, 0, 255, 255, 0, 0, 29, 0, 0, 0, 132, 1, 96, 0, 255, 255, 255, 255, ++ 33, 0, 0, 0, 96, 6, 65, 0, 255, 255, 0, 0, 51, 3, 0, 0, 100, 6, 65, ++ 76, 252, 255, 77, 25, 33, 0, 0, 255, 255, 0, 0, 41, 58, 0, 0, 100, 6, ++ 65, 0, 255, 255, 0, 0, 41, 58, 0, 0, 104, 6, 65, 0, 255, 255, 0, 0, ++ 104, 5, 0, 0, 108, 6, 65, 0, 255, 255, 0, 0, 168, 48, 0, 0, 112, 6, ++ 65, 0, 255, 255, 0, 0, 232, 62, 0, 0, 116, 6, 65, 0, 255, 255, 0, 0, ++ 28, 50, 0, 0, 120, 6, 65, 0, 255, 255, 0, 0, 187, 51, 0, 0, 124, 6, ++ 65, 0, 255, 255, 0, 0, 48, 9, 0, 0, 80, 3, 65, 0, 255, 255, 0, 0, 16, ++ 5, 0, 0, 84, 3, 65, 0, 255, 255, 0, 0, 9, 9, 0, 0, 92, 3, 65, 0, 255, ++ 255, 0, 0, 9, 8, 0, 0, 96, 3, 65, 0, 255, 255, 0, 0, 15, 7, 0, 0, 100, ++ 3, 65, 0, 255, 255, 0, 0, 5, 8, 0, 0, 108, 3, 65, 0, 255, 255, 0, 0, ++ 14, 9, 0, 0, 116, 3, 65, 0, 255, 255, 0, 0, 5, 9, 0, 0, 120, 3, 65, ++ 0, 255, 255, 0, 0, 16, 10, 0, 0, 64, 1, 65, 0, 255, 255, 0, 0, 16, 5, ++ 0, 0, 68, 1, 65, 0, 255, 255, 0, 0, 9, 9, 0, 0, 76, 1, 65, 0, 255, 255, ++ 0, 0, 9, 8, 0, 0, 80, 1, 65, 0, 255, 255, 0, 0, 15, 7, 0, 0, 84, 1, ++ 65, 0, 255, 255, 0, 0, 5, 8, 0, 0, 92, 1, 76, 252, 255, 72, 26, 33, ++ 0, 65, 0, 255, 255, 0, 0, 14, 9, 0, 0, 96, 1, 65, 0, 255, 255, 0, 0, ++ 5, 9, 0, 0, 100, 1, 65, 0, 255, 255, 0, 0, 16, 10, 0, 0, 224, 6, 65, ++ 0, 255, 255, 0, 0, 113, 32, 0, 0, 156, 1, 96, 0, 255, 0, 0, 0, 3, 0, ++ 0, 0, 100, 1, 96, 0, 255, 255, 255, 255, 0, 0, 0, 0, 9, 1, 4, 2, 1, ++ 0, 0, 34, 3, 2, 1, 0, 240, 1, 40, 4, 0, 0, 0, 32, 21, 50, 0, 255, 255, ++ 250, 255, 217, 3, 62, 254, 40, 21, 50, 0, 0, 0, 127, 254, 52, 16, 40, ++ 2, 44, 9, 100, 0, 14, 0, 0, 0, 12, 0, 0, 0, 240, 1, 40, 1, 0, 0, 0, ++ 32, 21, 50, 0, 255, 255, 250, 255, 221, 3, 62, 254, 40, 21, 50, 0, 0, ++ 0, 127, 254, 52, 16, 40, 2, 44, 9, 100, 0, 14, 0, 0, 0, 12, 0, 0, 0, ++ 240, 1, 40, 2, 0, 0, 0, 32, 21, 50, 0, 255, 255, 250, 255, 217, 3, 62, ++ 254, 40, 21, 50, 0, 0, 0, 127, 254, 52, 16, 40, 2, 44, 9, 100, 0, 14, ++ 0, 0, 0, 12, 0, 0, 0, 240, 1, 160, 1, 3, 0, 0, 0, 16, 21, 50, 0, 0, ++ 0, 0, 0, 240, 240, 240, 0, 20, 21, 50, 0, 0, 0, 0, 0, 240, 240, 240, ++ 0, 24, 21, 50, 0, 0, 0, 0, 0, 76, 252, 255, 67, 27, 33, 0, 240, 240, ++ 240, 0, 28, 21, 50, 0, 0, 0, 0, 0, 76, 76, 0, 0, 32, 21, 50, 0, 255, ++ 255, 250, 255, 221, 3, 62, 254, 36, 21, 50, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 40, 21, 50, 0, 0, 0, 127, 254, 52, 16, 40, 2, 52, 21, 50, 0, 0, 0, ++ 0, 0, 240, 0, 0, 0, 56, 21, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80, 21, 50, ++ 0, 0, 0, 0, 0, 202, 6, 0, 0, 44, 9, 100, 0, 14, 0, 0, 0, 12, 0, 0, 0, ++ 248, 0, 100, 0, 81, 0, 0, 0, 16, 0, 0, 0, 120, 8, 100, 0, 2, 0, 0, 0, ++ 0, 0, 0, 0, 1, 7, 181, 3, 4, 6, 10, 35, 60, 90, 110, 125, 5, 56, 4, ++ 136, 4, 156, 4, 136, 4, 216, 4, 116, 4, 196, 4, 216, 4, 196, 4, 20, ++ 5, 176, 4, 0, 5, 20, 5, 0, 5, 80, 5, 246, 4, 70, 5, 90, 5, 70, 5, 150, ++ 5, 60, 5, 140, 5, 160, 5, 140, 5, 220, 5, 130, 5, 210, 5, 230, 5, 210, ++ 5, 34, 6, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 168, ++ 2, 168, 2, 168, 2, 168, 2, 168, 2, 228, 2, 228, 2, 228, 2, 228, 2, 228, ++ 2, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 102, 3, 102, 3, 102, 3, 102, 3, ++ 102, 3, 172, 3, 76, 252, 255, 62, 28, 33, 0, 172, 3, 172, 3, 172, 3, ++ 172, 3, 242, 3, 242, 3, 242, 3, 242, 3, 242, 3, 20, 255, 20, 255, 20, ++ 255, 20, 255, 20, 255, 20, 255, 6, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, ++ 2, 255, 164, 2, 255, 168, 2, 255, 172, 2, 255, 0, 0, 96, 0, 5, 200, ++ 2, 255, 204, 2, 255, 208, 2, 255, 212, 2, 255, 216, 2, 255, 0, 0, 96, ++ 0, 5, 136, 3, 255, 140, 3, 255, 144, 3, 255, 148, 3, 255, 152, 3, 255, ++ 0, 0, 96, 0, 5, 156, 3, 255, 160, 3, 255, 164, 3, 255, 168, 3, 255, ++ 172, 3, 255, 0, 0, 96, 0, 5, 128, 3, 255, 132, 3, 255, 160, 6, 255, ++ 180, 2, 255, 56, 7, 255, 0, 0, 96, 0, 3, 164, 6, 255, 92, 6, 255, 152, ++ 6, 255, 76, 76, 76, 76, 76, 65, 65, 65, 65, 65, 133, 133, 133, 133, ++ 132, 166, 165, 165, 165, 165, 164, 244, 24, 3, 250, 101, 3, 204, 95, ++ 95, 95, 95, 95, 77, 77, 77, 77, 77, 132, 132, 132, 132, 131, 165, 164, ++ 164, 164, 164, 164, 244, 26, 3, 250, 102, 3, 204, 108, 108, 108, 108, ++ 108, 88, 88, 88, 88, 88, 132, 132, 132, 132, 131, 165, 164, 164, 164, ++ 164, 164, 244, 31, 3, 250, 102, 3, 204, 133, 133, 133, 133, 133, 105, ++ 105, 105, 105, 105, 132, 132, 132, 132, 131, 165, 164, 164, 164, 164, ++ 164, 76, 252, 255, 57, 29, 33, 0, 244, 31, 3, 250, 102, 3, 204, 153, ++ 153, 153, 153, 153, 116, 116, 116, 116, 116, 132, 132, 132, 132, 131, ++ 165, 164, 164, 164, 164, 164, 244, 31, 3, 250, 103, 3, 204, 179, 179, ++ 179, 179, 179, 130, 130, 130, 130, 130, 132, 132, 132, 132, 131, 165, ++ 164, 164, 164, 164, 164, 244, 31, 3, 250, 103, 35, 255, 1, 7, 181, 3, ++ 0, 6, 10, 35, 60, 90, 110, 125, 5, 92, 3, 62, 3, 72, 3, 92, 3, 72, 3, ++ 152, 3, 122, 3, 132, 3, 152, 3, 132, 3, 212, 3, 182, 3, 192, 3, 212, ++ 3, 192, 3, 26, 4, 252, 3, 6, 4, 26, 4, 6, 4, 96, 4, 66, 4, 76, 4, 96, ++ 4, 76, 4, 166, 4, 136, 4, 146, 4, 166, 4, 146, 4, 20, 255, 20, 255, ++ 20, 255, 20, 255, 20, 255, 20, 255, 68, 2, 48, 2, 38, 2, 18, 2, 28, ++ 2, 128, 2, 108, 2, 98, 2, 78, 2, 88, 2, 188, 2, 168, 2, 158, 2, 138, ++ 2, 148, 2, 2, 3, 238, 2, 228, 2, 208, 2, 218, 2, 72, 3, 52, 3, 42, 3, ++ 22, 3, 32, 3, 142, 3, 122, 3, 112, 3, 92, 3, 102, 3, 20, 255, 20, 255, ++ 20, 255, 20, 255, 20, 255, 20, 255, 6, 0, 0, 0, 96, 0, 5, 156, 2, 255, ++ 160, 2, 255, 164, 2, 255, 168, 2, 255, 172, 2, 255, 0, 0, 96, 0, 5, ++ 200, 2, 255, 204, 76, 252, 255, 52, 30, 33, 0, 2, 255, 208, 2, 255, ++ 212, 2, 255, 216, 2, 255, 0, 0, 96, 0, 5, 136, 3, 255, 140, 3, 255, ++ 144, 3, 255, 148, 3, 255, 152, 3, 255, 0, 0, 96, 0, 5, 156, 3, 255, ++ 160, 3, 255, 164, 3, 255, 168, 3, 255, 172, 3, 255, 0, 0, 96, 0, 5, ++ 128, 3, 255, 132, 3, 255, 160, 6, 255, 180, 2, 255, 56, 7, 255, 0, 0, ++ 96, 0, 3, 164, 6, 255, 92, 6, 255, 152, 6, 255, 67, 57, 55, 55, 56, ++ 56, 53, 53, 54, 53, 136, 134, 134, 134, 133, 168, 166, 166, 166, 164, ++ 164, 244, 24, 3, 250, 101, 3, 204, 76, 69, 65, 66, 67, 64, 60, 59, 59, ++ 60, 136, 134, 134, 134, 133, 168, 166, 166, 166, 164, 164, 244, 26, ++ 3, 250, 102, 3, 204, 92, 82, 82, 82, 82, 75, 71, 71, 71, 71, 136, 134, ++ 134, 134, 133, 168, 166, 166, 166, 164, 164, 244, 31, 3, 250, 102, 3, ++ 204, 106, 99, 95, 95, 100, 87, 83, 82, 82, 83, 136, 134, 134, 134, 133, ++ 168, 166, 166, 166, 164, 164, 244, 31, 3, 250, 102, 3, 204, 124, 113, ++ 110, 110, 113, 97, 93, 92, 92, 93, 136, 134, 134, 134, 133, 168, 166, ++ 166, 166, 164, 164, 244, 31, 3, 250, 103, 3, 204, 140, 129, 127, 127, ++ 129, 111, 104, 103, 103, 104, 136, 134, 134, 134, 133, 168, 166, 166, ++ 166, 164, 164, 244, 31, 3, 250, 103, 76, 252, 255, 47, 31, 33, 0, 35, ++ 255, 2, 7, 127, 4, 6, 5, 56, 4, 136, 4, 156, 4, 136, 4, 216, 4, 116, ++ 4, 196, 4, 216, 4, 196, 4, 20, 5, 176, 4, 0, 5, 20, 5, 0, 5, 80, 5, ++ 246, 4, 70, 5, 90, 5, 70, 5, 150, 5, 60, 5, 140, 5, 160, 5, 140, 5, ++ 220, 5, 130, 5, 210, 5, 230, 5, 210, 5, 34, 6, 20, 255, 20, 255, 20, ++ 255, 20, 255, 20, 255, 20, 255, 1, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, ++ 2, 255, 164, 2, 255, 168, 2, 255, 172, 2, 255, 76, 76, 76, 76, 76, 95, ++ 95, 95, 95, 95, 108, 108, 108, 108, 108, 133, 133, 133, 133, 133, 153, ++ 153, 153, 153, 153, 179, 179, 179, 179, 179, 2, 7, 127, 0, 6, 5, 92, ++ 3, 62, 3, 72, 3, 92, 3, 72, 3, 152, 3, 122, 3, 132, 3, 152, 3, 132, ++ 3, 212, 3, 182, 3, 192, 3, 212, 3, 192, 3, 26, 4, 252, 3, 6, 4, 26, ++ 4, 6, 4, 96, 4, 66, 4, 76, 4, 96, 4, 76, 4, 166, 4, 136, 4, 146, 4, ++ 166, 4, 146, 4, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, ++ 1, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, 2, 255, 164, 2, 255, 168, 2, ++ 255, 172, 2, 255, 67, 57, 55, 55, 56, 76, 69, 65, 66, 67, 92, 83, 82, ++ 82, 82, 106, 99, 95, 95, 76, 252, 255, 42, 32, 33, 0, 100, 124, 113, ++ 110, 110, 113, 140, 129, 127, 127, 129, 0, 7, 4, 63, 0, 0, 0, 3, 1, ++ 196, 1, 8, 10, 32, 0, 8, 8, 0, 0, 4, 4, 0, 0, 16, 16, 0, 0, 8, 8, 0, ++ 0, 24, 24, 0, 0, 40, 40, 0, 0, 32, 32, 0, 0, 44, 44, 0, 0, 40, 40, 0, ++ 0, 48, 48, 0, 0, 65, 65, 0, 0, 52, 52, 0, 0, 73, 73, 0, 0, 32, 32, 1, ++ 1, 80, 80, 0, 0, 36, 36, 1, 1, 88, 88, 0, 0, 64, 64, 1, 1, 138, 138, ++ 0, 0, 96, 96, 1, 1, 139, 139, 0, 0, 100, 100, 1, 1, 140, 140, 0, 0, ++ 96, 96, 2, 2, 141, 141, 0, 0, 100, 100, 2, 2, 142, 142, 0, 0, 104, 104, ++ 2, 2, 143, 143, 0, 0, 108, 108, 2, 2, 150, 150, 0, 0, 112, 112, 2, 2, ++ 165, 165, 0, 0, 80, 80, 3, 3, 166, 166, 0, 0, 84, 84, 3, 3, 221, 221, ++ 0, 0, 116, 116, 3, 3, 229, 229, 0, 0, 120, 120, 3, 3, 237, 237, 0, 0, ++ 152, 152, 3, 3, 238, 238, 0, 0, 252, 252, 3, 3, 239, 239, 0, 0, 188, ++ 188, 3, 3, 239, 239, 0, 0, 188, 188, 3, 3, 3, 1, 100, 200, 10, 32, 0, ++ 64, 0, 0, 1, 64, 0, 0, 1, 64, 0, 0, 1, 64, 0, 0, 1, 64, 0, 0, 1, 65, ++ 0, 4, 1, 73, 0, 76, 252, 255, 37, 33, 33, 0, 36, 1, 80, 0, 64, 1, 88, ++ 0, 96, 1, 82, 0, 72, 1, 83, 0, 76, 1, 84, 0, 80, 1, 85, 0, 84, 1, 86, ++ 0, 88, 1, 87, 0, 92, 1, 102, 0, 152, 1, 110, 0, 184, 1, 118, 0, 216, ++ 1, 126, 0, 248, 1, 127, 0, 252, 1, 127, 0, 252, 1, 127, 0, 252, 1, 127, ++ 0, 252, 1, 127, 0, 252, 1, 3, 1, 58, 40, 11, 32, 0, 1, 0, 0, 1, 0, 0, ++ 5, 0, 0, 13, 0, 0, 29, 0, 0, 14, 0, 0, 30, 0, 0, 62, 0, 0, 15, 0, 0, ++ 31, 0, 0, 63, 0, 0, 127, 0, 0, 255, 0, 0, 255, 0, 0, 255, 0, 0, 255, ++ 0, 0, 255, 0, 0, 255, 0, 0, 3, 1, 5, 8, 8, 32, 0, 6, 3, 1, 5, 12, 8, ++ 32, 0, 5, 3, 1, 5, 16, 8, 32, 0, 11, 3, 1, 5, 20, 8, 32, 0, 10, 4, 7, ++ 152, 1, 4, 50, 31, 0, 0, 29, 0, 0, 28, 1, 0, 26, 2, 0, 23, 2, 0, 21, ++ 18, 0, 19, 85, 0, 17, 100, 0, 15, 17, 0, 14, 3, 0, 13, 20, 0, 11, 80, ++ 0, 10, 100, 0, 9, 35, 0, 8, 35, 0, 7, 3, 0, 7, 22, 0, 6, 21, 0, 5, 19, ++ 0, 5, 22, 0, 4, 19, 0, 4, 38, 0, 4, 25, 0, 3, 5, 0, 3, 8, 0, 3, 42, ++ 0, 2, 3, 0, 2, 76, 252, 255, 32, 34, 33, 0, 22, 0, 2, 9, 0, 2, 43, 0, ++ 2, 61, 0, 2, 63, 0, 1, 2, 0, 1, 21, 0, 1, 24, 0, 1, 58, 0, 1, 29, 0, ++ 1, 31, 0, 1, 143, 0, 1, 239, 0, 1, 63, 1, 1, 143, 1, 1, 207, 1, 1, 15, ++ 2, 1, 79, 2, 1, 127, 2, 1, 175, 2, 1, 207, 2, 1, 0, 0, 1, 0, 0, 4, 7, ++ 152, 1, 0, 50, 31, 0, 0, 29, 0, 0, 28, 1, 0, 26, 2, 0, 23, 2, 0, 21, ++ 18, 0, 19, 85, 0, 17, 100, 0, 15, 17, 0, 14, 3, 0, 13, 20, 0, 11, 80, ++ 0, 10, 100, 0, 9, 35, 0, 8, 35, 0, 7, 3, 0, 7, 22, 0, 6, 21, 0, 5, 19, ++ 0, 5, 22, 0, 4, 19, 0, 4, 38, 0, 4, 25, 0, 3, 5, 0, 3, 8, 0, 3, 42, ++ 0, 2, 3, 0, 2, 22, 0, 2, 9, 0, 2, 43, 0, 2, 61, 0, 2, 63, 0, 1, 2, 0, ++ 1, 21, 0, 1, 24, 0, 1, 58, 0, 1, 29, 0, 1, 31, 0, 1, 143, 0, 1, 239, ++ 0, 1, 63, 1, 1, 143, 1, 1, 207, 1, 1, 15, 2, 1, 79, 2, 1, 127, 2, 1, ++ 175, 2, 1, 207, 2, 1, 0, 0, 1, 0, 0, 3, 7, 43, 1, 0, 0, 0, 1, 0, 0, ++ 0, 0, 20, 10, 0, 4, 0, 0, 0, 0, 0, 0, 10, 2, 254, 11, 228, 76, 252, ++ 255, 27, 35, 33, 0, 254, 28, 1, 228, 254, 28, 1, 10, 2, 254, 11, 241, ++ 255, 15, 0, 241, 255, 15, 0, 5, 7, 36, 255, 1, 8, 8, 12, 0, 8, 1, 4, ++ 2, 0, 3, 252, 4, 248, 5, 244, 6, 240, 7, 12, 0, 8, 1, 4, 2, 0, 3, 252, ++ 4, 248, 5, 244, 6, 240, 7, 15, 3, 40, 2, 120, 20, 127, 90, 0, 20, 2, ++ 20, 30, 0, 2, 3, 0, 30, 170, 51, 25, 5, 207, 0, 128, 10, 146, 0, 0, ++ 0, 0, 7, 0, 0, 162, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 5, 24, 19, 33, 0, ++ 144, 3, 1, 5, 201, 34, 32, 0, 0, 3, 1, 12, 220, 29, 32, 0, 1, 1, 48, ++ 0, 2, 10, 10, 0, 3, 1, 5, 72, 44, 32, 0, 1, 3, 1, 5, 36, 51, 32, 0, ++ 1, 3, 1, 5, 78, 5, 32, 0, 0, 3, 1, 6, 8, 30, 32, 0, 0, 0, 3, 1, 8, 184, ++ 40, 32, 0, 0, 0, 0, 0, 3, 1, 5, 237, 37, 32, 0, 0, 3, 1, 6, 198, 50, ++ 32, 0, 42, 14, 3, 1, 6, 172, 44, 32, 0, 240, 0, 3, 1, 6, 236, 39, 32, ++ 0, 128, 7, 3, 1, 5, 152, 52, 32, 0, 0, 4, 3, 12, 32, 0, 32, 0, 20, 20, ++ 26, 102, 10, 21, 0, 0, 5, 3, 32, 0, 27, 40, 80, 255, 255, 63, 0, 5, ++ 3, 31, 12, 194, 1, 76, 252, 255, 22, 36, 33, 0, 80, 80, 174, 56, 186, ++ 10, 5, 0, 255, 255, 7, 227, 50, 0, 184, 168, 198, 255, 17, 3, 4, 64, ++ 129, 0, 0, 10, 3, 4, 212, 48, 0, 0, 3, 1, 20, 96, 93, 13, 0, 60, 28, ++ 32, 0, 52, 28, 32, 0, 44, 28, 32, 0, 0, 10, 20, 0, 3, 1, 156, 19, 112, ++ 93, 13, 0, 156, 91, 32, 0, 184, 216, 32, 0, 24, 215, 32, 0, 76, 215, ++ 32, 0, 128, 215, 32, 0, 180, 215, 32, 0, 232, 215, 32, 0, 28, 216, 32, ++ 0, 80, 216, 32, 0, 132, 216, 32, 0, 0, 0, 0, 0, 119, 91, 3, 0, 71, 106, ++ 3, 0, 103, 15, 13, 0, 0, 0, 0, 0, 33, 15, 13, 0, 0, 0, 0, 0, 217, 15, ++ 13, 0, 185, 15, 13, 0, 235, 97, 3, 0, 141, 98, 3, 0, 59, 86, 3, 0, 93, ++ 209, 7, 0, 223, 215, 7, 0, 171, 124, 7, 0, 0, 0, 0, 0, 201, 19, 13, ++ 0, 0, 0, 0, 0, 163, 19, 13, 0, 233, 126, 7, 0, 181, 125, 7, 0, 169, ++ 127, 7, 0, 29, 206, 7, 0, 93, 209, 7, 0, 223, 215, 7, 0, 231, 205, 7, ++ 0, 0, 0, 0, 0, 59, 20, 13, 0, 0, 0, 0, 0, 253, 19, 13, 0, 165, 209, ++ 7, 0, 171, 210, 7, 0, 103, 215, 7, 0, 29, 206, 7, 0, 255, 0, 0, 0, 56, ++ 10, 33, 0, 0, 0, 48, 16, 76, 252, 255, 17, 37, 33, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 123, 30, 13, 0, 129, 30, 13, 0, 29, ++ 31, 13, 0, 63, 32, 13, 0, 0, 12, 0, 0, 143, 251, 6, 0, 133, 56, 13, ++ 0, 119, 57, 13, 0, 31, 2, 7, 0, 193, 3, 7, 0, 0, 0, 0, 0, 125, 6, 7, ++ 0, 231, 10, 7, 0, 101, 57, 13, 0, 141, 254, 6, 0, 97, 4, 7, 0, 0, 0, ++ 0, 0, 219, 230, 2, 0, 189, 57, 13, 0, 13, 230, 2, 0, 253, 230, 2, 0, ++ 203, 236, 2, 0, 0, 0, 0, 0, 253, 232, 2, 0, 0, 0, 0, 0, 139, 233, 2, ++ 0, 103, 235, 2, 0, 249, 231, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, ++ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 100, 0, 0, 0, 0, 0, 194, 11, 163, ++ 18, 133, 23, 78, 27, 102, 30, 3, 33, 71, 35, 70, 37, 16, 39, 174, 40, ++ 40, 42, 131, 43, 197, 76, 252, 255, 12, 38, 33, 0, 44, 241, 45, 9, 47, ++ 16, 48, 9, 49, 244, 49, 210, 50, 166, 51, 112, 52, 49, 53, 234, 53, ++ 155, 54, 70, 55, 234, 55, 136, 56, 32, 57, 179, 57, 66, 58, 203, 58, ++ 81, 59, 211, 59, 81, 60, 203, 60, 66, 61, 182, 61, 39, 62, 149, 62, ++ 0, 63, 104, 63, 207, 63, 51, 64, 148, 64, 244, 64, 81, 65, 172, 65, ++ 6, 66, 94, 66, 180, 66, 8, 67, 91, 67, 172, 67, 252, 67, 74, 68, 151, ++ 68, 226, 68, 45, 69, 118, 69, 189, 69, 4, 70, 73, 70, 142, 70, 209, ++ 70, 19, 71, 85, 71, 149, 71, 212, 71, 19, 72, 81, 72, 141, 72, 201, ++ 72, 4, 73, 63, 73, 120, 73, 177, 73, 233, 73, 32, 74, 87, 74, 141, 74, ++ 194, 74, 247, 74, 43, 75, 94, 75, 145, 75, 195, 75, 245, 75, 38, 76, ++ 86, 76, 134, 76, 182, 76, 229, 76, 19, 77, 65, 77, 111, 77, 156, 77, ++ 200, 77, 244, 77, 32, 78, 75, 78, 118, 78, 160, 78, 202, 78, 244, 78, ++ 29, 79, 70, 79, 110, 79, 150, 79, 190, 79, 229, 79, 12, 80, 51, 80, ++ 89, 80, 127, 80, 165, 80, 202, 80, 239, 80, 19, 81, 56, 81, 92, 81, ++ 128, 81, 163, 81, 198, 81, 233, 81, 12, 82, 46, 82, 80, 82, 114, 82, ++ 147, 82, 181, 82, 214, 82, 247, 82, 23, 83, 55, 83, 87, 83, 119, 83, ++ 151, 83, 182, 83, 76, 252, 255, 7, 39, 33, 0, 213, 83, 244, 83, 19, ++ 84, 49, 84, 80, 84, 110, 84, 140, 84, 169, 84, 199, 84, 228, 84, 1, ++ 85, 30, 85, 58, 85, 87, 85, 115, 85, 143, 85, 171, 85, 199, 85, 227, ++ 85, 254, 85, 25, 86, 52, 86, 79, 86, 106, 86, 132, 86, 159, 86, 185, ++ 86, 211, 86, 237, 86, 7, 87, 32, 87, 58, 87, 83, 87, 108, 87, 133, 87, ++ 158, 87, 183, 87, 208, 87, 232, 87, 1, 88, 25, 88, 49, 88, 73, 88, 97, ++ 88, 120, 88, 144, 88, 167, 88, 190, 88, 214, 88, 237, 88, 4, 89, 26, ++ 89, 49, 89, 72, 89, 94, 89, 116, 89, 139, 89, 161, 89, 183, 89, 205, ++ 89, 226, 89, 248, 89, 14, 90, 35, 90, 56, 90, 78, 90, 99, 90, 120, 90, ++ 141, 90, 161, 90, 182, 90, 203, 90, 223, 90, 244, 90, 8, 91, 28, 91, ++ 49, 91, 69, 91, 89, 91, 108, 91, 128, 91, 148, 91, 168, 91, 187, 91, ++ 206, 91, 226, 91, 245, 91, 8, 92, 27, 92, 46, 92, 65, 92, 84, 92, 103, ++ 92, 122, 92, 140, 92, 159, 92, 177, 92, 195, 92, 214, 92, 232, 92, 250, ++ 92, 12, 93, 30, 93, 48, 93, 66, 93, 84, 93, 101, 93, 119, 93, 137, 93, ++ 154, 93, 171, 93, 189, 93, 206, 93, 223, 93, 240, 93, 1, 94, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 112, 1, 101, 0, 1, 0, 0, 0, 1, 76, 252, 255, 2, ++ 40, 33, 0, 0, 0, 0, 0, 0, 0, 0, 96, 1, 101, 0, 1, 0, 0, 0, 1, 0, 0, ++ 0, 0, 0, 0, 0, 192, 4, 65, 0, 0, 0, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, ++ 213, 78, 13, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 188, ++ 1, 96, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 33, 182, 2, 0, 188, 188, ++ 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 32, 0, 96, 0, 0, 0, 0, 0, 255, ++ 0, 0, 0, 0, 0, 0, 0, 28, 0, 96, 0, 64, 0, 0, 0, 255, 0, 0, 0, 0, 0, ++ 0, 0, 24, 0, 96, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 20, 0, 96, ++ 0, 240, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 192, 4, 65, 0, 1, 0, 0, 0, ++ 255, 255, 0, 0, 0, 0, 0, 0, 44, 0, 96, 0, 48, 0, 0, 0, 255, 0, 0, 0, ++ 0, 0, 0, 0, 36, 0, 96, 0, 255, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 65, ++ 79, 13, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 232, 2, 96, ++ 0, 64, 0, 0, 0, 240, 0, 0, 0, 0, 0, 0, 0, 100, 4, 65, 0, 186, 64, 0, ++ 0, 255, 255, 0, 0, 0, 0, 0, 0, 96, 4, 65, 0, 76, 252, 255, 253, 40, ++ 33, 0, 192, 80, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 105, 78, 13, 0, 188, ++ 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 52, 6, 65, 0, 128, 24, 0, ++ 0, 255, 255, 0, 0, 0, 0, 0, 0, 96, 1, 96, 0, 85, 0, 0, 0, 255, 0, 0, ++ 0, 0, 0, 0, 0, 48, 4, 65, 0, 233, 2, 0, 0, 255, 255, 0, 0, 0, 0, 0, ++ 0, 220, 6, 65, 0, 241, 130, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 192, 4, ++ 65, 0, 33, 0, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 136, 4, 65, 0, 0, 0, ++ 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 219, 79, 13, 0, 188, 188, 188, 188, ++ 67, 67, 67, 67, 0, 0, 0, 0, 7, 80, 13, 0, 188, 188, 188, 188, 67, 67, ++ 67, 67, 0, 0, 0, 0, 121, 79, 13, 0, 188, 188, 188, 188, 67, 67, 67, ++ 67, 0, 0, 0, 0, 156, 2, 96, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, ++ 160, 2, 96, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 164, 2, 96, 0, ++ 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 168, 2, 96, 0, 0, 0, 0, 0, 255, ++ 0, 0, 0, 0, 0, 0, 0, 172, 2, 96, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, ++ 0, 76, 252, 255, 248, 41, 33, 0, 0, 200, 2, 96, 0, 0, 0, 0, 0, 255, ++ 0, 0, 0, 0, 0, 0, 0, 204, 2, 96, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, ++ 0, 0, 208, 2, 96, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 212, 2, 96, ++ 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 216, 2, 96, 0, 0, 0, 0, 0, ++ 255, 0, 0, 0, 0, 0, 0, 0, 145, 78, 13, 0, 188, 188, 188, 188, 67, 67, ++ 67, 67, 0, 0, 0, 0, 129, 183, 2, 0, 188, 188, 188, 188, 67, 67, 67, ++ 67, 0, 0, 0, 0, 240, 0, 100, 0, 1, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, ++ 228, 0, 100, 0, 12, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 224, 0, 100, ++ 0, 48, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 252, 2, 96, 0, 1, 0, 0, 0, 255, 0, 0, 0, 0, 0, ++ 0, 0, 188, 1, 96, 0, 1, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 213, 78, ++ 13, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 12, 1, 96, 0, ++ 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 51, 80, 13, 0, 188, 188, 188, ++ 188, 67, 67, 76, 252, 255, 243, 42, 33, 0, 67, 67, 0, 0, 0, 0, 96, 1, ++ 101, 0, 1, 0, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 112, 1, 101, 0, 1, 0, ++ 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 248, 0, 100, 0, 223, 0, 0, 0, 255, ++ 255, 0, 0, 0, 0, 0, 0, 200, 0, 100, 0, 24, 0, 0, 0, 255, 255, 0, 0, ++ 0, 0, 0, 0, 32, 0, 96, 0, 190, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 28, ++ 0, 96, 0, 255, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 24, 0, 96, 0, 15, ++ 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 20, 0, 96, 0, 255, 0, 0, 0, 255, ++ 0, 0, 0, 0, 0, 0, 0, 36, 0, 96, 0, 255, 0, 0, 0, 255, 0, 0, 0, 0, 0, ++ 0, 0, 44, 0, 96, 0, 48, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 220, 4, 96, ++ 0, 8, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 232, 4, 65, 0, 2, 194, 0, 0, ++ 255, 0, 0, 0, 0, 0, 0, 0, 100, 4, 65, 0, 186, 64, 0, 0, 255, 255, 0, ++ 0, 0, 0, 0, 0, 52, 6, 65, 0, 0, 72, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, ++ 232, 2, 96, 0, 69, 0, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 219, 79, 13, ++ 0, 188, 76, 252, 255, 238, 43, 33, 0, 188, 188, 188, 67, 67, 67, 67, ++ 0, 0, 0, 0, 7, 80, 13, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, ++ 0, 0, 105, 78, 13, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, ++ 145, 78, 13, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 63, ++ 81, 13, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 83, 80, 13, ++ 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 192, 4, 65, 0, 33, ++ 0, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 231, 80, 13, 0, 188, 188, 188, ++ 188, 67, 67, 67, 67, 0, 0, 0, 0, 153, 79, 13, 0, 188, 188, 188, 188, ++ 67, 67, 67, 67, 0, 0, 0, 0, 240, 0, 100, 0, 1, 0, 0, 0, 255, 0, 0, 0, ++ 0, 0, 0, 0, 228, 0, 100, 0, 12, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 224, ++ 0, 100, 0, 48, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 160, 2, 0, 69, 78, 13, 0, 57, 160, ++ 2, 0, 87, 160, 2, 0, 211, 160, 2, 0, 123, 161, 2, 0, 181, 161, 2, 0, ++ 197, 162, 2, 0, 0, 0, 0, 0, 12, 0, 10, 5, 8, 6, 6, 10, 4, 11, 2, 13, ++ 76, 252, 255, 233, 44, 33, 0, 0, 15, 254, 17, 252, 19, 250, 21, 248, ++ 23, 246, 25, 244, 27, 242, 29, 240, 31, 238, 33, 236, 35, 234, 37, 232, ++ 39, 230, 41, 10, 1, 8, 5, 6, 7, 4, 11, 2, 12, 0, 14, 100, 1, 96, 0, ++ 104, 1, 96, 0, 108, 1, 96, 0, 112, 1, 96, 0, 116, 1, 96, 0, 120, 1, ++ 96, 0, 124, 1, 96, 0, 132, 1, 96, 0, 81, 40, 13, 0, 3, 0, 0, 0, 189, ++ 48, 13, 0, 6, 0, 9, 0, 83, 49, 13, 0, 4, 0, 8, 0, 83, 50, 13, 0, 4, ++ 0, 6, 0, 101, 50, 13, 0, 3, 0, 7, 0, 69, 41, 13, 0, 0, 0, 14, 0, 245, ++ 68, 13, 0, 10, 0, 6, 0, 85, 41, 13, 0, 35, 0, 0, 0, 73, 86, 13, 0, 4, ++ 0, 6, 0, 207, 40, 13, 0, 13, 0, 6, 0, 223, 47, 13, 0, 0, 0, 0, 0, 115, ++ 48, 13, 0, 3, 0, 14, 0, 143, 190, 1, 0, 0, 0, 6, 0, 143, 41, 13, 0, ++ 0, 0, 6, 0, 183, 41, 13, 0, 10, 0, 6, 0, 117, 50, 13, 0, 12, 0, 6, 0, ++ 85, 43, 13, 0, 10, 0, 0, 0, 187, 43, 13, 0, 7, 0, 0, 0, 219, 41, 13, ++ 0, 28, 0, 0, 0, 13, 43, 13, 0, 3, 0, 0, 0, 143, 50, 13, 0, 5, 0, 7, ++ 0, 0, 0, 0, 0, 37, 0, 0, 0, 177, 53, 13, 76, 252, 255, 228, 45, 33, ++ 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 3, 1, 5, 44, 12, 33, 0, 0, 3, 1, 5, 43, ++ 12, 33, 0, 3, 3, 1, 5, 42, 12, 33, 0, 0, 3, 1, 5, 40, 12, 33, 0, 1, ++ 3, 1, 5, 41, 12, 33, 0, 0, 3, 1, 8, 36, 12, 33, 0, 185, 185, 187, 185, ++ 3, 1, 8, 32, 12, 33, 0, 185, 185, 187, 185, 3, 1, 5, 28, 12, 33, 0, ++ 0, 3, 1, 6, 30, 12, 33, 0, 0, 0, 3, 1, 8, 20, 12, 33, 0, 16, 0, 0, 0, ++ 3, 1, 8, 24, 12, 33, 0, 15, 0, 0, 0, 3, 1, 40, 240, 11, 33, 0, 82, 102, ++ 252, 252, 62, 82, 253, 253, 42, 62, 254, 254, 22, 42, 255, 255, 2, 22, ++ 0, 0, 238, 2, 1, 1, 218, 238, 2, 2, 198, 218, 3, 3, 178, 198, 4, 4, ++ 3, 1, 5, 235, 11, 33, 0, 0, 3, 1, 5, 236, 11, 33, 0, 0, 3, 1, 5, 237, ++ 11, 33, 0, 0, 3, 1, 5, 233, 11, 33, 0, 0, 3, 1, 5, 232, 11, 33, 0, 0, ++ 3, 1, 5, 234, 11, 33, 0, 0, 3, 1, 6, 238, 11, 33, 0, 144, 1, 3, 1, 8, ++ 228, 11, 33, 0, 40, 0, 0, 0, 3, 1, 8, 224, 11, 33, 0, 15, 0, 0, 0, 3, ++ 1, 5, 222, 11, 33, 0, 182, 3, 1, 5, 223, 11, 33, 0, 170, 3, 1, 5, 76, ++ 252, 255, 223, 46, 33, 0, 221, 11, 33, 0, 1, 3, 1, 5, 220, 11, 33, 0, ++ 40, 3, 1, 5, 219, 11, 33, 0, 1, 3, 1, 5, 218, 11, 33, 0, 0, 3, 1, 5, ++ 216, 11, 33, 0, 0, 3, 1, 5, 217, 11, 33, 0, 0, 3, 1, 164, 3, 56, 10, ++ 33, 0, 156, 1, 96, 0, 140, 2, 96, 0, 136, 2, 96, 0, 152, 2, 96, 0, 148, ++ 4, 65, 0, 152, 4, 65, 0, 12, 0, 0, 0, 0, 0, 0, 0, 93, 0, 0, 0, 6, 0, ++ 0, 0, 93, 0, 0, 0, 108, 2, 0, 0, 3, 128, 0, 0, 6, 0, 0, 0, 9, 0, 0, ++ 0, 93, 0, 0, 0, 6, 0, 0, 0, 93, 0, 0, 0, 108, 2, 0, 0, 3, 128, 0, 0, ++ 0, 0, 0, 0, 15, 0, 0, 0, 93, 0, 0, 0, 6, 0, 0, 0, 93, 0, 0, 0, 108, ++ 2, 0, 0, 3, 128, 0, 0, 250, 0, 0, 0, 21, 0, 0, 0, 93, 0, 0, 0, 6, 0, ++ 0, 0, 93, 0, 0, 0, 108, 2, 0, 0, 3, 128, 0, 0, 244, 0, 0, 0, 27, 0, ++ 0, 0, 93, 0, 0, 0, 6, 0, 0, 0, 93, 0, 0, 0, 108, 2, 0, 0, 3, 128, 0, ++ 0, 238, 0, 0, 0, 33, 0, 0, 0, 93, 0, 0, 0, 6, 0, 0, 0, 93, 0, 0, 0, ++ 108, 2, 0, 0, 3, 128, 0, 0, 232, 0, 0, 0, 39, 0, 76, 252, 255, 218, ++ 47, 33, 0, 0, 0, 93, 0, 0, 0, 6, 0, 0, 0, 93, 0, 0, 0, 108, 2, 0, 0, ++ 3, 128, 0, 0, 226, 0, 0, 0, 45, 0, 0, 0, 93, 0, 0, 0, 6, 0, 0, 0, 93, ++ 0, 0, 0, 108, 2, 0, 0, 3, 128, 0, 0, 220, 0, 0, 0, 49, 0, 0, 0, 93, ++ 0, 0, 0, 6, 0, 0, 0, 93, 0, 0, 0, 108, 2, 0, 0, 3, 128, 0, 0, 214, 0, ++ 0, 0, 49, 0, 0, 0, 93, 0, 0, 0, 6, 0, 0, 0, 93, 0, 0, 0, 108, 2, 0, ++ 0, 1, 128, 0, 0, 208, 0, 0, 0, 49, 0, 0, 0, 93, 0, 0, 0, 6, 0, 0, 0, ++ 16, 0, 0, 0, 92, 2, 0, 0, 1, 128, 0, 0, 202, 0, 0, 0, 49, 0, 0, 0, 93, ++ 0, 0, 0, 6, 0, 0, 0, 93, 0, 0, 0, 74, 2, 0, 0, 1, 128, 0, 0, 196, 0, ++ 0, 0, 49, 0, 0, 0, 93, 0, 0, 0, 6, 0, 0, 0, 93, 0, 0, 0, 68, 2, 0, 0, ++ 1, 128, 0, 0, 190, 0, 0, 0, 49, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 68, 2, 0, 0, 1, 128, 0, 0, 3, 1, 5, 52, 10, 33, 0, 1, 3, 1, ++ 5, 49, 10, 33, 0, 6, 3, 1, 5, 50, 10, 33, 0, 4, 3, 1, 5, 51, 10, 33, ++ 0, 0, 3, 76, 252, 255, 213, 48, 33, 0, 1, 5, 48, 10, 33, 0, 0, 3, 1, ++ 24, 0, 2, 13, 0, 145, 248, 216, 33, 1, 104, 33, 244, 64, 1, 10, 177, ++ 1, 245, 128, 1, 92, 247, 55, 189, 3, 1, 20, 20, 2, 13, 0, 143, 176, ++ 0, 36, 1, 72, 196, 97, 109, 247, 134, 188, 0, 63, 32, 0, 3, 1, 20, 36, ++ 2, 13, 0, 48, 70, 161, 123, 106, 70, 11, 171, 0, 240, 58, 251, 109, ++ 247, 28, 189, 3, 1, 24, 52, 2, 13, 0, 168, 105, 112, 247, 102, 253, ++ 176, 241, 128, 111, 1, 210, 108, 247, 9, 189, 108, 247, 16, 189, 3, ++ 1, 20, 72, 2, 13, 0, 32, 70, 0, 125, 2, 40, 1, 209, 32, 70, 144, 71, ++ 109, 247, 68, 184, 3, 1, 28, 88, 2, 13, 0, 4, 72, 0, 120, 8, 177, 0, ++ 240, 65, 251, 3, 32, 51, 247, 32, 253, 108, 247, 99, 190, 48, 10, 33, ++ 0, 3, 1, 16, 112, 2, 13, 0, 33, 0, 0, 240, 67, 251, 160, 117, 112, 189, ++ 0, 0, 3, 1, 32, 124, 2, 13, 0, 2, 180, 8, 70, 5, 240, 233, 251, 2, 188, ++ 32, 177, 62, 32, 91, 247, 219, 252, 177, 247, 113, 188, 189, 232, 240, ++ 159, 0, 0, 3, 1, 14, 152, 2, 13, 0, 16, 34, 168, 247, 89, 253, 169, ++ 247, 15, 184, 3, 1, 16, 162, 2, 13, 0, 2, 213, 32, 70, 0, 240, 237, ++ 251, 168, 247, 139, 187, 76, 252, 255, 208, 49, 33, 0, 3, 1, 22, 174, ++ 2, 13, 0, 104, 70, 140, 247, 221, 249, 16, 185, 32, 70, 117, 247, 121, ++ 250, 124, 189, 0, 0, 3, 1, 22, 192, 2, 13, 0, 162, 247, 188, 255, 24, ++ 185, 96, 104, 8, 177, 117, 247, 112, 250, 163, 247, 81, 187, 3, 1, 26, ++ 210, 2, 13, 0, 177, 247, 16, 252, 33, 120, 155, 248, 4, 0, 129, 66, ++ 1, 211, 163, 247, 54, 191, 163, 247, 200, 190, 3, 1, 24, 232, 2, 13, ++ 0, 49, 185, 193, 143, 1, 41, 3, 209, 176, 248, 70, 16, 164, 247, 77, ++ 185, 164, 247, 93, 185, 3, 1, 12, 252, 2, 13, 0, 0, 240, 0, 253, 124, ++ 189, 0, 0, 3, 1, 16, 4, 3, 13, 0, 0, 181, 0, 240, 94, 255, 93, 248, ++ 4, 235, 112, 71, 3, 1, 12, 16, 3, 13, 0, 115, 247, 80, 252, 114, 247, ++ 54, 186, 3, 1, 18, 24, 3, 13, 0, 32, 70, 107, 247, 9, 255, 48, 70, 117, ++ 247, 159, 248, 112, 189, 3, 1, 22, 38, 3, 13, 0, 32, 70, 0, 240, 2, ++ 254, 24, 177, 212, 248, 152, 32, 100, 247, 151, 191, 16, 189, 3, 1, ++ 20, 56, 3, 13, 0, 32, 70, 0, 240, 7, 254, 255, 32, 132, 248, 29, 1, ++ 102, 247, 31, 189, 3, 1, 20, 72, 3, 13, 0, 32, 70, 0, 240, 255, 253, ++ 255, 32, 132, 248, 29, 1, 101, 247, 124, 188, 3, 1, 24, 88, 76, 252, ++ 255, 203, 50, 33, 0, 3, 13, 0, 212, 248, 212, 0, 174, 247, 120, 248, ++ 0, 33, 212, 248, 216, 0, 100, 247, 190, 190, 0, 0, 3, 1, 20, 108, 3, ++ 13, 0, 0, 240, 101, 255, 8, 177, 165, 247, 101, 189, 165, 247, 115, ++ 189, 0, 0, 3, 1, 20, 124, 3, 13, 0, 163, 66, 1, 211, 167, 247, 10, 188, ++ 68, 33, 167, 247, 8, 188, 0, 0, 3, 1, 20, 140, 3, 13, 0, 1, 240, 105, ++ 248, 32, 70, 189, 232, 16, 64, 106, 247, 196, 190, 0, 0, 3, 1, 20, 156, ++ 3, 13, 0, 132, 248, 48, 1, 32, 70, 0, 240, 211, 253, 161, 247, 151, ++ 185, 0, 0, 3, 1, 12, 172, 3, 13, 0, 1, 240, 106, 255, 32, 70, 112, 189, ++ 3, 1, 12, 180, 3, 13, 0, 189, 232, 248, 67, 2, 240, 84, 184, 3, 1, 16, ++ 188, 3, 13, 0, 32, 70, 2, 240, 157, 249, 1, 36, 140, 247, 207, 189, ++ 3, 1, 22, 200, 3, 13, 0, 32, 70, 41, 70, 2, 240, 38, 250, 8, 177, 79, ++ 247, 147, 190, 79, 247, 165, 190, 3, 1, 30, 218, 3, 13, 0, 97, 136, ++ 193, 243, 201, 1, 0, 41, 3, 208, 3, 40, 3, 208, 79, 247, 242, 185, 79, ++ 247, 117, 186, 79, 247, 240, 185, 3, 1, 28, 244, 3, 13, 0, 225, 121, ++ 1, 41, 3, 208, 32, 40, 3, 211, 132, 247, 235, 188, 132, 247, 240, 188, ++ 132, 247, 248, 188, 76, 252, 255, 198, 51, 33, 0, 0, 0, 3, 1, 20, 12, ++ 4, 13, 0, 32, 136, 2, 33, 6, 34, 227, 28, 189, 232, 16, 64, 51, 247, ++ 86, 185, 3, 1, 28, 28, 4, 13, 0, 79, 244, 250, 87, 74, 70, 65, 70, 32, ++ 70, 2, 240, 225, 251, 8, 185, 127, 247, 237, 190, 127, 247, 232, 190, ++ 3, 1, 28, 52, 4, 13, 0, 187, 70, 79, 244, 250, 44, 32, 70, 2, 240, 254, ++ 251, 8, 177, 127, 247, 108, 191, 127, 247, 132, 191, 0, 0, 3, 1, 28, ++ 76, 4, 13, 0, 4, 112, 125, 247, 170, 251, 94, 247, 91, 252, 91, 247, ++ 21, 252, 91, 247, 107, 252, 91, 247, 180, 187, 0, 0, 3, 1, 24, 100, ++ 4, 13, 0, 2, 180, 48, 247, 126, 250, 2, 188, 32, 70, 48, 247, 118, 254, ++ 48, 247, 88, 191, 0, 0, 3, 1, 48, 120, 4, 13, 0, 9, 75, 27, 120, 51, ++ 177, 148, 249, 26, 16, 70, 49, 90, 41, 8, 216, 83, 247, 248, 190, 148, ++ 249, 26, 16, 21, 49, 30, 41, 1, 216, 83, 247, 241, 190, 83, 247, 215, ++ 190, 0, 0, 52, 10, 33, 0, 3, 1, 28, 164, 4, 13, 0, 33, 122, 1, 41, 3, ++ 208, 32, 40, 3, 211, 83, 247, 217, 190, 83, 247, 221, 190, 83, 247, ++ 201, 190, 0, 0, 3, 1, 16, 188, 4, 13, 0, 40, 70, 2, 240, 253, 254, 72, ++ 247, 240, 187, 0, 0, 3, 1, 52, 200, 4, 76, 252, 255, 193, 52, 33, 0, ++ 13, 0, 71, 242, 20, 1, 136, 66, 3, 209, 8, 72, 0, 120, 0, 177, 16, 189, ++ 8, 32, 117, 247, 175, 248, 1, 0, 249, 208, 71, 242, 20, 2, 148, 66, ++ 2, 209, 1, 34, 1, 72, 2, 112, 140, 247, 17, 184, 76, 94, 13, 0, 3, 1, ++ 12, 248, 4, 13, 0, 2, 240, 46, 255, 16, 189, 0, 0, 3, 1, 20, 0, 5, 13, ++ 0, 21, 127, 6, 45, 1, 208, 194, 248, 26, 64, 134, 247, 139, 187, 0, ++ 0, 3, 1, 20, 16, 5, 13, 0, 32, 177, 8, 32, 132, 248, 162, 0, 150, 247, ++ 113, 185, 112, 189, 0, 0, 3, 1, 16, 32, 5, 13, 0, 32, 70, 3, 240, 7, ++ 248, 189, 232, 240, 129, 0, 0, 3, 1, 20, 44, 5, 13, 0, 232, 96, 1, 32, ++ 168, 118, 0, 32, 104, 118, 153, 247, 244, 189, 0, 0, 3, 1, 16, 60, 5, ++ 13, 0, 200, 248, 8, 16, 3, 240, 114, 248, 114, 247, 38, 191, 3, 1, 76, ++ 72, 5, 13, 0, 12, 73, 9, 120, 65, 177, 12, 73, 8, 120, 40, 177, 0, 32, ++ 8, 112, 10, 73, 79, 240, 1, 0, 8, 112, 9, 73, 12, 32, 8, 96, 9, 72, ++ 1, 105, 65, 240, 1, 1, 1, 97, 1, 104, 65, 240, 1, 1, 1, 96, 0, 32, 112, ++ 71, 218, 11, 33, 0, 151, 30, 32, 0, 78, 94, 13, 0, 52, 9, 100, 0, 96, ++ 1, 101, 0, 76, 252, 255, 188, 53, 33, 0, 3, 1, 24, 144, 5, 13, 0, 102, ++ 247, 109, 252, 24, 185, 224, 105, 192, 2, 115, 247, 123, 185, 115, 247, ++ 122, 185, 0, 0, 3, 1, 28, 164, 5, 13, 0, 5, 209, 4, 72, 0, 120, 16, ++ 185, 96, 125, 86, 247, 11, 184, 0, 0, 86, 247, 18, 184, 219, 11, 33, ++ 0, 3, 1, 32, 188, 5, 13, 0, 0, 40, 8, 208, 0, 41, 6, 208, 136, 66, 200, ++ 191, 64, 26, 184, 191, 9, 26, 249, 209, 112, 71, 0, 32, 112, 71, 0, ++ 0, 3, 1, 28, 216, 5, 13, 0, 148, 248, 157, 0, 32, 240, 1, 0, 132, 248, ++ 157, 0, 104, 3, 1, 213, 111, 247, 82, 185, 111, 247, 90, 185, 3, 1, ++ 36, 240, 5, 13, 0, 8, 208, 1, 6, 6, 213, 148, 248, 168, 0, 3, 240, 176, ++ 248, 192, 126, 192, 7, 3, 208, 148, 248, 148, 0, 111, 247, 131, 185, ++ 111, 247, 131, 185, 3, 1, 44, 16, 6, 13, 0, 128, 123, 112, 247, 240, ++ 251, 5, 70, 48, 104, 176, 248, 216, 16, 168, 178, 112, 247, 49, 252, ++ 249, 136, 136, 66, 4, 221, 48, 104, 144, 248, 168, 0, 110, 247, 238, ++ 189, 110, 247, 238, 189, 3, 1, 22, 56, 6, 13, 0, 5, 208, 0, 181, 106, ++ 247, 242, 253, 106, 247, 255, 254, 0, 189, 158, 247, 110, 191, 3, 1, ++ 22, 74, 6, 13, 0, 8, 185, 132, 248, 68, 96, 248, 178, 132, 76, 252, ++ 255, 183, 54, 33, 0, 248, 62, 0, 158, 247, 58, 190, 0, 0, 3, 1, 20, ++ 92, 6, 13, 0, 132, 248, 136, 0, 1, 32, 132, 248, 33, 0, 125, 247, 31, ++ 188, 0, 0, 3, 1, 20, 108, 6, 13, 0, 2, 45, 189, 232, 112, 64, 1, 208, ++ 107, 247, 244, 188, 107, 247, 90, 189, 3, 1, 16, 124, 6, 13, 0, 32, ++ 70, 3, 240, 137, 248, 132, 247, 192, 184, 0, 0, 3, 1, 10, 136, 6, 13, ++ 0, 3, 240, 138, 250, 112, 189, 3, 1, 10, 142, 6, 13, 0, 3, 240, 180, ++ 250, 16, 189, 3, 1, 8, 148, 6, 13, 0, 16, 181, 16, 189, 3, 1, 8, 152, ++ 6, 13, 0, 3, 240, 26, 187, 3, 1, 12, 156, 6, 13, 0, 3, 240, 25, 251, ++ 16, 189, 0, 0, 3, 1, 10, 164, 6, 13, 0, 3, 240, 181, 251, 112, 189, ++ 3, 1, 20, 170, 6, 13, 0, 15, 180, 3, 240, 222, 251, 15, 188, 189, 232, ++ 16, 64, 157, 247, 28, 187, 3, 1, 26, 186, 6, 13, 0, 0, 32, 15, 180, ++ 3, 240, 85, 252, 15, 188, 134, 247, 102, 250, 32, 104, 139, 247, 63, ++ 184, 0, 0, 3, 1, 12, 208, 6, 13, 0, 3, 240, 54, 255, 189, 232, 240, ++ 129, 3, 1, 12, 216, 6, 13, 0, 189, 232, 240, 79, 4, 240, 169, 184, 3, ++ 1, 16, 224, 6, 13, 0, 98, 247, 153, 251, 173, 248, 12, 0, 100, 247, ++ 70, 187, 76, 252, 255, 178, 55, 33, 0, 3, 1, 12, 236, 6, 13, 0, 4, 240, ++ 61, 249, 100, 247, 159, 184, 3, 1, 32, 244, 6, 13, 0, 41, 70, 50, 70, ++ 4, 240, 45, 250, 6, 70, 44, 177, 57, 70, 4, 240, 27, 250, 7, 70, 98, ++ 247, 38, 191, 98, 247, 44, 191, 3, 1, 20, 16, 7, 13, 0, 0, 45, 3, 208, ++ 5, 45, 1, 208, 99, 247, 66, 184, 189, 232, 240, 129, 3, 1, 10, 32, 7, ++ 13, 0, 4, 240, 42, 251, 112, 189, 3, 1, 18, 38, 7, 13, 0, 2, 209, 1, ++ 32, 75, 247, 237, 191, 4, 240, 108, 251, 16, 189, 3, 1, 32, 52, 7, 13, ++ 0, 1, 32, 96, 243, 15, 36, 4, 240, 254, 0, 92, 247, 136, 253, 65, 247, ++ 179, 248, 8, 177, 4, 240, 152, 253, 92, 247, 242, 189, 3, 1, 20, 80, ++ 7, 13, 0, 2, 240, 18, 254, 32, 70, 41, 70, 116, 247, 146, 252, 79, 247, ++ 216, 191, 3, 1, 10, 96, 7, 13, 0, 5, 240, 40, 249, 112, 189, 3, 1, 10, ++ 102, 7, 13, 0, 5, 240, 89, 249, 112, 189, 3, 1, 16, 108, 7, 13, 0, 25, ++ 177, 4, 70, 0, 32, 130, 247, 45, 187, 112, 189, 3, 1, 44, 120, 7, 13, ++ 0, 153, 248, 0, 48, 75, 185, 5, 180, 5, 240, 128, 249, 3, 0, 5, 188, ++ 27, 177, 70, 234, 3, 6, 98, 247, 193, 185, 2, 75, 2, 235, 66, 2, 98, ++ 247, 76, 252, 255, 173, 56, 33, 0, 117, 185, 142, 94, 8, 0, 3, 1, 12, ++ 160, 7, 13, 0, 0, 136, 192, 245, 88, 32, 16, 189, 3, 1, 12, 168, 7, ++ 13, 0, 5, 240, 126, 249, 112, 189, 0, 0, 3, 1, 20, 176, 7, 13, 0, 32, ++ 70, 2, 73, 50, 247, 143, 252, 166, 247, 153, 188, 77, 91, 13, 0, 3, ++ 1, 20, 192, 7, 13, 0, 5, 240, 142, 249, 1, 72, 2, 36, 165, 247, 222, ++ 191, 108, 159, 32, 0, 3, 1, 12, 208, 7, 13, 0, 5, 240, 230, 249, 50, ++ 247, 192, 187, 3, 1, 28, 216, 7, 13, 0, 4, 70, 13, 70, 5, 240, 234, ++ 249, 16, 177, 2, 74, 50, 247, 255, 188, 112, 189, 0, 0, 196, 24, 32, ++ 0, 3, 1, 16, 240, 7, 13, 0, 2, 40, 1, 217, 74, 247, 4, 191, 74, 247, ++ 5, 191, 3, 1, 14, 252, 7, 13, 0, 32, 70, 5, 240, 55, 250, 76, 247, 16, ++ 184, 3, 1, 18, 6, 8, 13, 0, 32, 70, 41, 70, 5, 240, 76, 250, 189, 232, ++ 240, 129, 0, 0, 3, 1, 20, 20, 8, 13, 0, 42, 32, 32, 98, 32, 70, 5, 240, ++ 107, 250, 2, 40, 74, 247, 45, 190, 3, 1, 132, 1, 36, 8, 13, 0, 112, ++ 181, 4, 70, 92, 247, 18, 248, 23, 77, 149, 248, 216, 1, 56, 179, 22, ++ 72, 23, 74, 65, 104, 65, 243, 128, 16, 64, 28, 16, 96, 196, 235, 4, ++ 16, 20, 76, 252, 255, 168, 57, 33, 0, 74, 0, 235, 132, 16, 2, 235, 128, ++ 0, 144, 248, 192, 32, 17, 72, 7, 42, 22, 208, 17, 74, 18, 104, 82, 30, ++ 2, 96, 32, 70, 197, 248, 12, 17, 91, 247, 169, 252, 116, 247, 245, 253, ++ 149, 248, 217, 17, 65, 240, 1, 1, 133, 248, 217, 17, 116, 247, 241, ++ 253, 0, 32, 112, 189, 3, 32, 112, 189, 1, 34, 233, 231, 128, 1, 33, ++ 0, 112, 29, 32, 0, 164, 53, 32, 0, 172, 117, 32, 0, 160, 49, 32, 0, ++ 168, 49, 32, 0, 3, 1, 68, 164, 8, 13, 0, 112, 181, 12, 70, 176, 249, ++ 32, 16, 64, 140, 21, 70, 30, 70, 8, 24, 11, 213, 64, 66, 25, 70, 112, ++ 247, 77, 250, 34, 70, 51, 70, 41, 70, 189, 232, 112, 64, 16, 70, 112, ++ 247, 71, 184, 25, 70, 112, 247, 66, 250, 34, 70, 51, 70, 41, 70, 189, ++ 232, 112, 64, 16, 70, 112, 247, 48, 185, 3, 1, 28, 228, 8, 13, 0, 16, ++ 181, 116, 247, 184, 253, 4, 70, 48, 247, 228, 252, 32, 70, 189, 232, ++ 16, 64, 116, 247, 180, 189, 0, 0, 3, 1, 40, 252, 8, 13, 0, 16, 181, ++ 7, 75, 0, 34, 83, 248, 34, 64, 140, 66, 2, 209, 64, 240, 3, 0, 16, 189, ++ 82, 28, 10, 42, 245, 219, 64, 240, 1, 0, 16, 189, 112, 93, 13, 0, 3, ++ 1, 32, 32, 9, 13, 0, 65, 124, 2, 41, 8, 208, 76, 252, 255, 163, 58, ++ 33, 0, 3, 41, 6, 208, 0, 124, 22, 40, 3, 208, 23, 40, 1, 208, 0, 32, ++ 112, 71, 1, 32, 112, 71, 3, 1, 132, 1, 60, 9, 13, 0, 45, 233, 254, 67, ++ 27, 76, 102, 120, 160, 120, 8, 177, 6, 70, 34, 224, 132, 247, 238, 249, ++ 8, 177, 38, 120, 29, 224, 23, 72, 0, 37, 160, 70, 208, 233, 0, 18, 128, ++ 104, 0, 145, 205, 233, 1, 32, 111, 70, 87, 248, 37, 0, 4, 104, 7, 224, ++ 32, 31, 255, 247, 212, 255, 16, 177, 152, 248, 0, 96, 4, 224, 36, 104, ++ 87, 248, 37, 0, 160, 66, 243, 209, 109, 28, 237, 178, 3, 45, 235, 211, ++ 9, 72, 1, 120, 142, 66, 7, 208, 6, 112, 3, 176, 49, 70, 189, 232, 240, ++ 67, 2, 32, 116, 247, 104, 188, 189, 232, 254, 131, 0, 0, 49, 10, 33, ++ 0, 96, 93, 13, 0, 152, 93, 13, 0, 3, 1, 18, 188, 9, 13, 0, 47, 72, 0, ++ 33, 1, 97, 65, 97, 129, 97, 193, 97, 112, 71, 3, 1, 26, 202, 9, 13, ++ 0, 0, 32, 43, 75, 1, 70, 16, 51, 83, 248, 33, 32, 73, 28, 16, 67, 4, ++ 41, 249, 211, 112, 71, 3, 1, 144, 1, 224, 9, 13, 0, 254, 181, 38, 78, ++ 4, 0, 31, 70, 79, 240, 0, 5, 6, 241, 16, 6, 4, 208, 1, 44, 2, 208, 2, ++ 40, 45, 208, 52, 224, 16, 104, 0, 144, 144, 136, 173, 76, 252, 255, ++ 158, 59, 33, 0, 248, 4, 0, 2, 170, 104, 70, 113, 247, 127, 255, 28, ++ 73, 9, 120, 136, 66, 39, 210, 128, 40, 37, 210, 65, 9, 0, 240, 31, 0, ++ 1, 34, 86, 248, 33, 48, 2, 250, 0, 242, 12, 177, 147, 67, 15, 224, 19, ++ 66, 1, 208, 23, 37, 23, 224, 223, 248, 64, 192, 7, 240, 1, 7, 135, 64, ++ 92, 248, 33, 64, 148, 67, 60, 67, 76, 248, 33, 64, 19, 67, 70, 248, ++ 33, 48, 8, 224, 0, 32, 1, 70, 70, 248, 32, 16, 64, 28, 4, 40, 250, 211, ++ 0, 224, 18, 37, 40, 70, 254, 189, 3, 1, 28, 108, 10, 13, 0, 0, 40, 4, ++ 208, 9, 56, 32, 240, 3, 0, 116, 247, 154, 190, 112, 71, 8, 103, 13, ++ 0, 75, 41, 32, 0, 3, 1, 200, 1, 132, 10, 13, 0, 45, 233, 240, 71, 4, ++ 70, 144, 248, 210, 0, 0, 240, 53, 250, 6, 70, 180, 248, 72, 0, 180, ++ 248, 74, 16, 136, 66, 3, 208, 148, 248, 32, 33, 167, 247, 2, 255, 69, ++ 0, 53, 128, 74, 208, 180, 248, 34, 17, 32, 70, 100, 247, 63, 250, 130, ++ 70, 32, 108, 0, 38, 32, 244, 128, 32, 79, 246, 255, 121, 32, 100, 4, ++ 235, 70, 7, 183, 248, 40, 1, 72, 69, 55, 208, 65, 0, 80, 70, 111, 247, ++ 142, 255, 176, 251, 245, 241, 128, 70, 5, 251, 17, 128, 167, 248, 40, ++ 1, 95, 234, 72, 16, 21, 76, 252, 255, 153, 60, 33, 0, 212, 148, 248, ++ 210, 0, 102, 247, 172, 249, 64, 1, 32, 213, 79, 240, 128, 96, 176, 251, ++ 245, 241, 105, 67, 64, 70, 112, 247, 253, 248, 176, 251, 245, 241, 5, ++ 251, 17, 1, 167, 248, 40, 17, 64, 1, 16, 213, 183, 248, 40, 1, 2, 35, ++ 42, 70, 0, 33, 99, 247, 145, 254, 167, 248, 40, 1, 1, 32, 176, 64, 33, ++ 108, 192, 243, 0, 0, 65, 234, 128, 64, 32, 100, 118, 28, 6, 46, 193, ++ 211, 189, 232, 240, 135, 3, 1, 150, 3, 72, 11, 13, 0, 45, 233, 252, ++ 95, 6, 70, 128, 120, 214, 248, 4, 160, 241, 120, 0, 240, 15, 4, 10, ++ 235, 1, 0, 79, 240, 0, 8, 199, 121, 180, 72, 223, 248, 212, 178, 1, ++ 37, 0, 120, 193, 70, 72, 185, 4, 44, 7, 208, 174, 247, 119, 250, 32, ++ 177, 219, 248, 0, 0, 0, 33, 128, 248, 252, 17, 167, 247, 255, 250, 1, ++ 40, 1, 209, 248, 7, 100, 209, 174, 247, 105, 250, 0, 40, 96, 208, 167, ++ 72, 0, 120, 48, 185, 4, 44, 4, 209, 219, 248, 0, 0, 144, 248, 252, 1, ++ 112, 187, 247, 120, 81, 70, 4, 44, 26, 209, 219, 248, 0, 16, 58, 70, ++ 1, 245, 129, 112, 205, 233, 0, 1, 81, 70, 116, 247, 45, 254, 219, 248, ++ 0, 16, 0, 152, 10, 122, 1, 153, 56, 68, 82, 28, 9, 49, 116, 247, 35, ++ 254, 219, 248, 0, 16, 76, 252, 255, 148, 61, 33, 0, 8, 122, 1, 245, ++ 129, 113, 56, 68, 199, 178, 146, 72, 0, 120, 0, 40, 176, 120, 64, 234, ++ 7, 32, 29, 208, 1, 240, 30, 251, 197, 178, 143, 72, 36, 177, 6, 44, ++ 2, 208, 4, 44, 5, 208, 38, 224, 5, 112, 48, 70, 162, 247, 250, 255, ++ 33, 224, 0, 120, 133, 66, 30, 208, 37, 234, 0, 1, 17, 240, 3, 8, 69, ++ 234, 0, 5, 23, 208, 128, 69, 21, 208, 79, 240, 1, 9, 18, 224, 174, 247, ++ 36, 249, 240, 177, 1, 32, 36, 177, 6, 44, 2, 208, 4, 44, 5, 208, 6, ++ 224, 219, 248, 0, 16, 129, 248, 252, 1, 1, 224, 79, 240, 1, 9, 122, ++ 73, 8, 112, 122, 79, 56, 104, 192, 5, 21, 213, 186, 241, 0, 15, 18, ++ 208, 120, 72, 128, 122, 192, 6, 14, 213, 48, 70, 162, 247, 178, 255, ++ 45, 224, 167, 247, 55, 251, 1, 40, 41, 209, 12, 177, 6, 44, 38, 209, ++ 48, 70, 162, 247, 190, 255, 34, 224, 1, 44, 3, 209, 48, 70, 162, 247, ++ 137, 255, 176, 177, 185, 241, 0, 15, 10, 208, 95, 234, 200, 112, 7, ++ 208, 105, 72, 0, 120, 16, 177, 104, 72, 176, 247, 33, 255, 162, 247, ++ 96, 255, 95, 72, 0, 120, 16, 177, 85, 177, 232, 7, 8, 208, 1, 32, 189, ++ 232, 252, 159, 56, 104, 64, 5, 2, 213, 48, 70, 161, 247, 243, 253, 0, ++ 32, 245, 231, 3, 1, 42, 76, 252, 255, 143, 62, 33, 0, 218, 12, 13, 0, ++ 16, 181, 10, 224, 93, 72, 137, 247, 62, 255, 4, 70, 64, 104, 8, 177, ++ 116, 247, 96, 253, 32, 70, 116, 247, 93, 253, 87, 72, 137, 247, 38, ++ 255, 0, 40, 239, 208, 16, 189, 3, 1, 28, 0, 13, 13, 0, 16, 181, 4, 70, ++ 139, 247, 179, 252, 0, 40, 4, 209, 96, 104, 189, 232, 16, 64, 116, 247, ++ 76, 189, 16, 189, 3, 1, 16, 24, 13, 13, 0, 1, 40, 1, 208, 0, 240, 221, ++ 184, 0, 240, 162, 184, 3, 1, 200, 2, 36, 13, 13, 0, 45, 233, 240, 95, ++ 0, 38, 128, 70, 15, 70, 52, 70, 172, 247, 48, 250, 88, 177, 0, 37, 95, ++ 234, 8, 0, 9, 208, 1, 40, 15, 208, 16, 40, 21, 208, 184, 241, 17, 15, ++ 64, 209, 24, 224, 1, 37, 242, 231, 167, 247, 195, 250, 129, 70, 21, ++ 32, 163, 247, 245, 251, 6, 70, 10, 224, 173, 247, 131, 252, 129, 70, ++ 20, 32, 163, 247, 237, 251, 6, 70, 3, 224, 167, 247, 179, 250, 129, ++ 70, 60, 70, 185, 241, 0, 15, 38, 208, 24, 240, 240, 15, 223, 248, 208, ++ 160, 223, 248, 208, 176, 223, 248, 208, 128, 223, 248, 208, 144, 29, ++ 208, 152, 248, 0, 0, 70, 70, 1, 40, 22, 209, 20, 177, 13, 177, 171, ++ 247, 234, 255, 79, 70, 185, 248, 0, 0, 167, 247, 219, 249, 186, 248, ++ 0, 0, 167, 247, 219, 249, 52, 76, 252, 255, 138, 63, 33, 0, 177, 56, ++ 136, 224, 131, 29, 177, 155, 248, 11, 0, 172, 247, 9, 248, 0, 32, 48, ++ 112, 189, 232, 240, 159, 0, 46, 251, 208, 173, 247, 147, 252, 6, 70, ++ 167, 247, 204, 249, 6, 251, 0, 247, 167, 247, 204, 249, 6, 70, 173, ++ 247, 145, 252, 70, 67, 183, 66, 236, 217, 167, 247, 196, 249, 170, 248, ++ 0, 0, 167, 247, 188, 249, 169, 248, 0, 0, 20, 177, 13, 177, 171, 247, ++ 184, 255, 173, 247, 128, 252, 167, 247, 170, 249, 173, 247, 116, 252, ++ 167, 247, 170, 249, 60, 177, 173, 247, 119, 252, 224, 131, 29, 177, ++ 155, 248, 11, 0, 171, 247, 215, 255, 1, 33, 136, 248, 0, 16, 203, 231, ++ 0, 0, 44, 94, 13, 0, 0, 51, 32, 0, 153, 93, 13, 0, 245, 50, 32, 0, 156, ++ 41, 32, 0, 88, 52, 32, 0, 144, 149, 32, 0, 252, 136, 32, 0, 58, 51, ++ 32, 0, 248, 91, 32, 0, 56, 51, 32, 0, 60, 51, 32, 0, 3, 1, 118, 104, ++ 14, 13, 0, 16, 181, 161, 247, 119, 253, 31, 72, 0, 104, 128, 5, 1, 213, ++ 160, 247, 177, 255, 167, 247, 133, 249, 1, 40, 1, 209, 169, 247, 19, ++ 249, 0, 33, 1, 32, 255, 247, 75, 255, 171, 247, 75, 255, 23, 72, 23, ++ 73, 0, 120, 0, 40, 8, 104, 2, 208, 64, 244, 0, 112, 1, 224, 32, 244, ++ 0, 112, 8, 96, 116, 247, 214, 250, 4, 76, 252, 255, 133, 64, 33, 0, ++ 70, 173, 247, 220, 251, 96, 177, 173, 247, 51, 252, 72, 185, 20, 32, ++ 163, 247, 67, 251, 40, 177, 6, 32, 173, 247, 213, 251, 11, 73, 1, 32, ++ 8, 112, 32, 70, 189, 232, 16, 64, 116, 247, 196, 186, 3, 1, 38, 218, ++ 14, 13, 0, 16, 181, 167, 247, 177, 249, 0, 33, 189, 232, 16, 64, 17, ++ 32, 255, 247, 28, 191, 156, 41, 32, 0, 241, 50, 32, 0, 252, 50, 32, ++ 0, 243, 50, 32, 0, 3, 1, 32, 252, 14, 13, 0, 4, 73, 9, 120, 136, 66, ++ 3, 210, 3, 73, 1, 235, 64, 0, 112, 71, 0, 32, 112, 71, 73, 41, 32, 0, ++ 40, 103, 13, 0, 3, 1, 12, 24, 15, 13, 0, 56, 73, 55, 72, 8, 96, 112, ++ 71, 3, 1, 20, 32, 15, 13, 0, 1, 41, 3, 209, 79, 244, 72, 19, 16, 34, ++ 218, 101, 101, 247, 5, 190, 3, 1, 32, 48, 15, 13, 0, 193, 123, 57, 185, ++ 144, 248, 139, 16, 138, 6, 5, 213, 33, 240, 32, 1, 128, 248, 139, 16, ++ 1, 32, 112, 71, 0, 32, 112, 71, 3, 1, 30, 76, 15, 13, 0, 193, 123, 0, ++ 41, 8, 209, 144, 248, 29, 17, 1, 41, 4, 209, 16, 248, 139, 31, 65, 240, ++ 32, 1, 1, 112, 112, 71, 3, 1, 86, 102, 15, 13, 0, 16, 181, 4, 70, 100, ++ 247, 134, 248, 212, 248, 212, 0, 1, 33, 173, 247, 108, 250, 212, 76, ++ 252, 255, 128, 65, 33, 0, 248, 216, 0, 1, 33, 173, 247, 103, 250, 32, ++ 109, 30, 74, 144, 248, 210, 16, 1, 32, 19, 104, 136, 64, 131, 67, 19, ++ 96, 27, 74, 19, 104, 131, 67, 19, 96, 26, 75, 26, 104, 130, 67, 8, 70, ++ 26, 96, 70, 247, 45, 255, 32, 70, 189, 232, 16, 64, 79, 244, 172, 113, ++ 116, 247, 28, 186, 3, 1, 36, 184, 15, 13, 0, 16, 181, 4, 70, 101, 247, ++ 36, 254, 224, 123, 0, 40, 7, 209, 17, 72, 1, 104, 17, 74, 33, 240, 255, ++ 1, 18, 120, 17, 67, 1, 96, 16, 189, 3, 1, 64, 216, 15, 13, 0, 16, 181, ++ 4, 70, 100, 247, 238, 255, 224, 123, 1, 40, 7, 209, 9, 72, 1, 104, 9, ++ 74, 33, 240, 255, 1, 18, 120, 17, 67, 1, 96, 16, 189, 156, 93, 13, 0, ++ 44, 41, 32, 0, 48, 41, 32, 0, 52, 41, 32, 0, 56, 41, 32, 0, 144, 139, ++ 49, 0, 40, 37, 32, 0, 3, 1, 116, 20, 16, 13, 0, 112, 181, 4, 70, 174, ++ 247, 164, 250, 8, 177, 64, 38, 0, 224, 0, 38, 106, 247, 37, 255, 16, ++ 185, 106, 247, 92, 255, 0, 179, 0, 37, 148, 248, 39, 0, 49, 70, 3, 40, ++ 30, 208, 12, 32, 110, 247, 103, 255, 148, 248, 39, 32, 196, 72, 1, 42, ++ 194, 73, 2, 104, 2, 234, 1, 2, 2, 96, 1, 104, 18, 208, 192, 74, 17, ++ 67, 1, 96, 29, 76, 252, 255, 123, 66, 33, 0, 177, 160, 123, 111, 247, ++ 200, 254, 160, 97, 32, 70, 189, 232, 112, 64, 164, 247, 162, 188, 106, ++ 247, 128, 249, 1, 37, 219, 231, 13, 32, 223, 231, 65, 240, 128, 113, ++ 235, 231, 3, 1, 16, 132, 16, 13, 0, 182, 73, 8, 112, 182, 73, 1, 32, ++ 8, 112, 112, 71, 3, 1, 160, 2, 144, 16, 13, 0, 45, 233, 240, 65, 180, ++ 77, 6, 70, 12, 70, 41, 120, 255, 32, 6, 241, 28, 7, 1, 41, 2, 209, 56, ++ 70, 105, 247, 210, 250, 175, 73, 10, 104, 66, 240, 0, 82, 10, 96, 174, ++ 73, 188, 177, 1, 44, 62, 208, 2, 44, 74, 208, 3, 44, 85, 208, 4, 44, ++ 94, 208, 5, 44, 108, 209, 150, 248, 39, 0, 1, 40, 104, 208, 48, 70, ++ 106, 247, 23, 253, 0, 40, 99, 208, 48, 70, 189, 232, 240, 65, 164, 247, ++ 40, 188, 42, 120, 1, 42, 14, 209, 255, 40, 12, 208, 9, 120, 193, 177, ++ 192, 243, 3, 17, 8, 41, 6, 209, 0, 240, 15, 0, 0, 240, 166, 250, 192, ++ 178, 255, 247, 187, 255, 107, 247, 175, 249, 120, 177, 111, 247, 77, ++ 250, 176, 66, 11, 209, 111, 247, 144, 251, 64, 177, 189, 232, 240, 65, ++ 111, 247, 142, 184, 146, 73, 1, 235, 128, 0, 0, 104, 233, 231, 48, 70, ++ 189, 232, 240, 65, 107, 231, 9, 120, 0, 41, 50, 208, 41, 120, 1, 41, ++ 47, 209, 192, 243, 3, 76, 252, 255, 118, 67, 33, 0, 17, 8, 41, 43, 209, ++ 0, 240, 15, 0, 1, 33, 35, 224, 56, 70, 105, 247, 171, 249, 16, 177, ++ 4, 32, 168, 247, 163, 255, 132, 72, 0, 120, 189, 232, 240, 65, 168, ++ 247, 44, 191, 41, 120, 1, 41, 23, 209, 255, 40, 21, 208, 127, 72, 0, ++ 104, 189, 232, 240, 65, 192, 178, 125, 231, 9, 120, 0, 41, 12, 208, ++ 41, 120, 1, 41, 9, 209, 192, 243, 3, 16, 8, 40, 5, 209, 0, 33, 8, 70, ++ 189, 232, 240, 65, 0, 240, 48, 186, 189, 232, 240, 129, 3, 1, 30, 172, ++ 17, 13, 0, 16, 181, 44, 34, 115, 73, 116, 72, 137, 247, 234, 252, 175, ++ 242, 43, 17, 113, 72, 1, 97, 113, 73, 8, 96, 16, 189, 3, 1, 114, 198, ++ 17, 13, 0, 45, 233, 240, 65, 3, 70, 8, 70, 255, 41, 234, 208, 0, 34, ++ 255, 38, 0, 241, 70, 1, 108, 77, 23, 70, 3, 235, 67, 4, 90, 41, 11, ++ 216, 98, 73, 9, 120, 65, 177, 0, 240, 234, 249, 41, 104, 64, 240, 128, ++ 0, 1, 235, 132, 1, 136, 113, 212, 231, 223, 248, 116, 225, 111, 240, ++ 24, 12, 14, 235, 130, 1, 9, 104, 12, 235, 65, 1, 73, 178, 67, 26, 0, ++ 213, 11, 26, 217, 178, 177, 66, 1, 216, 23, 70, 14, 70, 82, 28, 210, ++ 178, 5, 42, 237, 211, 40, 104, 0, 235, 132, 0, 135, 113, 185, 231, 3, ++ 1, 10, 52, 76, 252, 255, 113, 68, 33, 0, 18, 13, 0, 74, 72, 0, 120, ++ 112, 71, 3, 1, 226, 2, 58, 18, 13, 0, 45, 233, 240, 65, 5, 70, 64, 108, ++ 113, 247, 116, 249, 4, 0, 174, 208, 148, 248, 208, 0, 1, 33, 159, 247, ++ 124, 254, 148, 248, 208, 0, 164, 247, 233, 252, 5, 241, 28, 0, 1, 33, ++ 7, 70, 105, 247, 19, 250, 1, 33, 56, 70, 105, 247, 17, 250, 0, 33, 56, ++ 70, 105, 247, 68, 249, 69, 72, 0, 104, 32, 101, 68, 72, 0, 29, 0, 104, ++ 67, 73, 164, 248, 84, 0, 65, 72, 9, 104, 12, 48, 193, 243, 128, 17, ++ 132, 248, 86, 16, 149, 248, 40, 16, 132, 248, 87, 16, 0, 104, 59, 78, ++ 96, 99, 16, 54, 174, 247, 106, 249, 96, 177, 57, 72, 20, 48, 0, 104, ++ 192, 5, 7, 213, 48, 104, 160, 99, 54, 29, 104, 108, 113, 247, 53, 249, ++ 174, 247, 185, 249, 20, 34, 49, 70, 32, 70, 163, 247, 37, 252, 224, ++ 136, 0, 179, 97, 137, 241, 177, 64, 0, 164, 248, 198, 0, 148, 248, 208, ++ 0, 111, 247, 117, 253, 161, 136, 1, 37, 137, 0, 9, 29, 111, 247, 218, ++ 250, 79, 234, 80, 0, 196, 248, 204, 0, 65, 1, 25, 213, 180, 248, 198, ++ 16, 128, 240, 128, 96, 176, 251, 241, 242, 1, 251, 18, 0, 164, 248, ++ 196, 0, 2, 32, 22, 224, 0, 33, 56, 70, 105, 247, 183, 249, 0, 33, 56, ++ 70, 76, 252, 255, 108, 69, 33, 0, 105, 247, 181, 249, 1, 33, 56, 70, ++ 105, 247, 232, 248, 0, 32, 57, 231, 180, 248, 198, 16, 176, 251, 241, ++ 242, 1, 251, 18, 0, 164, 248, 196, 0, 0, 32, 132, 248, 212, 0, 224, ++ 120, 0, 185, 229, 112, 1, 32, 41, 231, 255, 255, 0, 254, 148, 131, 49, ++ 0, 0, 0, 1, 1, 165, 7, 32, 0, 16, 97, 13, 0, 36, 51, 32, 0, 0, 4, 32, ++ 0, 52, 10, 33, 0, 152, 50, 32, 0, 60, 29, 32, 0, 136, 50, 32, 0, 184, ++ 163, 8, 0, 40, 104, 13, 0, 140, 50, 32, 0, 132, 50, 32, 0, 0, 10, 55, ++ 0, 152, 139, 49, 0, 3, 1, 14, 152, 19, 13, 0, 20, 73, 19, 72, 8, 96, ++ 255, 247, 13, 187, 3, 1, 42, 162, 19, 13, 0, 16, 181, 4, 70, 166, 247, ++ 65, 253, 173, 247, 185, 249, 1, 40, 9, 209, 255, 247, 10, 251, 0, 40, ++ 5, 208, 161, 109, 32, 70, 189, 232, 16, 64, 0, 240, 121, 184, 16, 189, ++ 3, 1, 48, 200, 19, 13, 0, 16, 181, 12, 70, 166, 247, 0, 254, 0, 44, ++ 8, 209, 255, 247, 249, 250, 0, 40, 4, 208, 4, 72, 1, 104, 33, 244, 128, ++ 17, 1, 96, 16, 189, 200, 93, 13, 0, 184, 50, 32, 0, 108, 139, 49, 0, ++ 3, 1, 12, 244, 19, 13, 0, 43, 73, 42, 72, 8, 96, 112, 71, 3, 1, 66, ++ 252, 19, 13, 0, 76, 252, 255, 103, 70, 33, 0, 16, 181, 4, 70, 172, 247, ++ 195, 248, 176, 247, 178, 248, 104, 177, 173, 247, 137, 249, 1, 40, 9, ++ 209, 255, 247, 218, 250, 48, 177, 35, 72, 129, 109, 32, 70, 189, 232, ++ 16, 64, 0, 240, 73, 184, 148, 248, 74, 0, 4, 40, 4, 209, 31, 72, 1, ++ 104, 65, 244, 128, 17, 1, 96, 16, 189, 3, 1, 44, 58, 20, 13, 0, 16, ++ 181, 12, 70, 172, 247, 230, 249, 0, 44, 12, 209, 176, 247, 145, 248, ++ 0, 40, 8, 208, 255, 247, 188, 250, 0, 40, 4, 208, 21, 72, 1, 104, 33, ++ 244, 128, 17, 1, 96, 16, 189, 3, 1, 90, 98, 20, 13, 0, 16, 181, 4, 70, ++ 192, 140, 176, 245, 0, 111, 9, 209, 161, 247, 50, 248, 56, 177, 14, ++ 72, 225, 140, 0, 104, 176, 248, 112, 0, 7, 224, 224, 131, 16, 189, 158, ++ 247, 166, 249, 64, 177, 10, 72, 225, 140, 0, 143, 8, 26, 161, 140, 136, ++ 66, 243, 218, 8, 70, 241, 231, 224, 140, 239, 231, 244, 93, 13, 0, 204, ++ 50, 32, 0, 252, 238, 32, 0, 108, 139, 49, 0, 212, 48, 32, 0, 228, 87, ++ 32, 0, 3, 1, 212, 1, 184, 20, 13, 0, 16, 181, 11, 70, 134, 176, 4, 70, ++ 145, 248, 86, 16, 4, 170, 3, 241, 80, 0, 113, 247, 31, 250, 41, 73, ++ 9, 120, 136, 66, 36, 210, 128, 40, 34, 210, 39, 74, 65, 9, 0, 240, 31, ++ 76, 252, 255, 98, 71, 33, 0, 0, 82, 248, 33, 32, 1, 35, 131, 64, 26, ++ 66, 24, 208, 35, 74, 82, 248, 33, 16, 34, 124, 193, 64, 1, 240, 1, 0, ++ 32, 73, 1, 40, 38, 208, 21, 42, 10, 104, 44, 208, 34, 244, 128, 2, 10, ++ 96, 113, 247, 95, 249, 27, 74, 1, 104, 72, 50, 17, 96, 17, 29, 128, ++ 136, 8, 96, 24, 72, 1, 104, 0, 145, 64, 104, 1, 144, 160, 123, 2, 169, ++ 111, 247, 87, 252, 105, 70, 2, 168, 111, 247, 46, 252, 8, 48, 140, 40, ++ 19, 210, 15, 72, 0, 29, 1, 104, 65, 244, 128, 17, 1, 96, 6, 176, 16, ++ 189, 21, 42, 10, 104, 2, 208, 66, 244, 128, 2, 215, 231, 66, 240, 64, ++ 2, 212, 231, 34, 240, 64, 2, 209, 231, 110, 247, 165, 254, 0, 32, 173, ++ 247, 219, 248, 235, 231, 75, 41, 32, 0, 24, 103, 13, 0, 8, 103, 13, ++ 0, 104, 139, 49, 0, 112, 130, 49, 0, 3, 1, 64, 136, 21, 13, 0, 112, ++ 181, 5, 70, 12, 70, 8, 10, 0, 33, 159, 247, 239, 251, 0, 33, 4, 40, ++ 4, 217, 149, 248, 208, 32, 146, 7, 0, 213, 0, 31, 162, 7, 7, 208, 226, ++ 67, 146, 7, 5, 209, 3, 74, 18, 120, 144, 66, 0, 210, 0, 185, 1, 33, ++ 8, 70, 112, 189, 44, 52, 32, 0, 3, 1, 72, 196, 21, 13, 0, 43, 74, 0, ++ 33, 82, 104, 193, 235, 193, 3, 76, 252, 255, 93, 72, 33, 0, 2, 235, ++ 131, 3, 147, 249, 24, 48, 131, 66, 14, 220, 153, 177, 193, 235, 193, ++ 3, 2, 235, 131, 2, 146, 249, 24, 48, 18, 249, 4, 44, 195, 26, 16, 26, ++ 131, 66, 4, 221, 73, 30, 2, 224, 73, 28, 14, 41, 229, 219, 14, 41, 0, ++ 209, 13, 33, 72, 178, 112, 71, 3, 1, 80, 8, 22, 13, 0, 240, 181, 26, ++ 79, 58, 120, 138, 66, 31, 208, 255, 42, 1, 209, 0, 41, 27, 208, 23, ++ 76, 57, 112, 0, 34, 192, 235, 192, 6, 120, 104, 0, 235, 130, 3, 29, ++ 104, 117, 177, 81, 177, 45, 104, 68, 248, 34, 80, 0, 235, 134, 0, 0, ++ 235, 130, 0, 27, 104, 192, 105, 24, 96, 2, 224, 84, 248, 34, 0, 40, ++ 96, 82, 28, 6, 42, 232, 219, 240, 189, 3, 1, 48, 84, 22, 13, 0, 7, 73, ++ 0, 240, 15, 0, 192, 235, 192, 0, 73, 104, 1, 235, 128, 0, 5, 73, 192, ++ 105, 0, 235, 64, 0, 8, 68, 208, 248, 2, 0, 112, 71, 32, 94, 13, 0, 84, ++ 104, 13, 0, 112, 9, 32, 0, 3, 1, 254, 2, 128, 22, 13, 0, 45, 233, 255, ++ 79, 131, 176, 255, 33, 0, 145, 6, 153, 73, 177, 249, 73, 75, 120, 202, ++ 104, 2, 235, 3, 18, 18, 104, 146, 7, 31, 213, 12, 105, 18, 224, 245, ++ 73, 12, 104, 33, 104, 137, 7, 11, 212, 8, 42, 22, 210, 194, 235, 194, ++ 76, 252, 255, 88, 73, 33, 0, 1, 1, 235, 129, 1, 4, 235, 193, 1, 209, ++ 248, 108, 19, 137, 7, 12, 213, 4, 242, 45, 20, 111, 240, 5, 1, 1, 235, ++ 16, 40, 4, 158, 192, 243, 128, 16, 0, 39, 1, 144, 182, 29, 117, 224, ++ 254, 32, 7, 176, 189, 232, 240, 143, 49, 120, 0, 41, 113, 208, 72, 28, ++ 64, 69, 110, 220, 112, 120, 22, 40, 97, 209, 182, 248, 2, 176, 0, 34, ++ 112, 28, 75, 247, 42, 255, 129, 70, 1, 152, 148, 248, 44, 81, 64, 240, ++ 128, 10, 33, 224, 0, 45, 0, 218, 29, 37, 5, 235, 133, 0, 20, 248, 16, ++ 32, 82, 69, 24, 209, 6, 153, 41, 177, 210, 73, 9, 105, 1, 235, 64, 1, ++ 73, 28, 5, 224, 208, 73, 9, 104, 1, 235, 64, 1, 1, 245, 151, 113, 4, ++ 235, 64, 0, 176, 248, 7, 32, 90, 69, 4, 209, 6, 34, 4, 152, 112, 247, ++ 162, 253, 240, 179, 148, 248, 44, 1, 109, 30, 133, 66, 216, 209, 192, ++ 178, 0, 235, 128, 0, 4, 235, 64, 1, 4, 152, 127, 28, 2, 104, 193, 248, ++ 1, 32, 128, 136, 161, 248, 5, 0, 148, 248, 44, 1, 0, 235, 128, 0, 4, ++ 248, 16, 160, 148, 248, 44, 1, 0, 235, 128, 0, 4, 235, 64, 0, 160, 248, ++ 7, 176, 148, 248, 44, 1, 0, 235, 128, 0, 4, 235, 64, 0, 128, 248, 9, ++ 144, 148, 248, 44, 1, 64, 28, 192, 178, 76, 252, 255, 83, 74, 33, 0, ++ 132, 248, 44, 1, 30, 40, 2, 211, 0, 32, 132, 248, 44, 1, 22, 248, 1, ++ 11, 168, 235, 0, 1, 161, 241, 1, 8, 6, 68, 184, 241, 1, 15, 138, 220, ++ 143, 177, 0, 224, 1, 224, 255, 32, 130, 231, 5, 235, 133, 0, 4, 235, ++ 64, 0, 66, 122, 74, 69, 2, 209, 232, 178, 0, 144, 230, 231, 128, 248, ++ 9, 144, 127, 28, 226, 231, 0, 152, 114, 231, 3, 1, 68, 250, 23, 13, ++ 0, 45, 233, 240, 65, 157, 76, 160, 104, 184, 185, 167, 120, 230, 120, ++ 184, 1, 156, 77, 0, 235, 6, 17, 1, 242, 49, 17, 40, 70, 115, 247, 235, ++ 253, 5, 235, 135, 16, 1, 29, 196, 233, 2, 81, 0, 235, 6, 16, 1, 29, ++ 33, 97, 148, 73, 0, 242, 49, 16, 8, 96, 1, 32, 189, 232, 240, 129, 3, ++ 1, 90, 58, 24, 13, 0, 48, 181, 141, 75, 66, 121, 197, 136, 220, 104, ++ 209, 178, 4, 235, 1, 17, 37, 177, 13, 96, 5, 137, 13, 129, 133, 122, ++ 4, 224, 79, 244, 0, 69, 13, 96, 0, 37, 13, 129, 141, 114, 4, 235, 2, ++ 17, 197, 122, 205, 114, 2, 123, 10, 115, 2, 123, 1, 42, 9, 209, 176, ++ 248, 13, 32, 138, 128, 194, 123, 74, 115, 2, 124, 138, 115, 176, 248, ++ 17, 0, 200, 128, 24, 120, 64, 28, 24, 112, 48, 189, 3, 1, 90, 144, 24, ++ 13, 0, 240, 181, 223, 248, 76, 252, 255, 78, 75, 33, 0, 224, 225, 68, ++ 121, 0, 38, 222, 248, 12, 0, 0, 235, 4, 16, 1, 104, 41, 177, 158, 248, ++ 0, 16, 73, 30, 142, 248, 0, 16, 6, 96, 0, 32, 1, 37, 17, 224, 222, 248, ++ 8, 16, 5, 250, 4, 247, 1, 235, 128, 18, 19, 108, 59, 66, 6, 208, 187, ++ 67, 19, 100, 3, 209, 22, 113, 10, 120, 82, 30, 10, 112, 64, 28, 192, ++ 178, 158, 248, 2, 16, 136, 66, 233, 211, 240, 189, 3, 1, 240, 1, 230, ++ 24, 13, 0, 45, 233, 255, 79, 128, 70, 0, 36, 129, 176, 145, 70, 16, ++ 6, 2, 213, 6, 32, 0, 144, 1, 224, 205, 248, 0, 144, 92, 73, 254, 39, ++ 0, 38, 141, 104, 186, 70, 45, 29, 1, 32, 0, 250, 3, 251, 34, 224, 40, ++ 120, 208, 177, 186, 241, 253, 15, 11, 208, 72, 69, 9, 209, 149, 248, ++ 59, 16, 65, 69, 5, 209, 104, 28, 0, 154, 2, 153, 112, 247, 178, 252, ++ 8, 177, 64, 53, 13, 224, 232, 107, 16, 234, 11, 15, 2, 208, 79, 240, ++ 253, 10, 65, 224, 55, 70, 44, 70, 12, 224, 143, 66, 1, 211, 55, 70, ++ 44, 70, 118, 28, 246, 178, 70, 72, 129, 120, 142, 66, 216, 211, 186, ++ 241, 253, 15, 49, 208, 66, 72, 129, 120, 143, 66, 45, 210, 100, 179, ++ 132, 248, 0, 144, 132, 248, 59, 128, 225, 107, 25, 185, 128, 104, 1, ++ 120, 73, 28, 1, 112, 225, 76, 252, 255, 73, 76, 33, 0, 107, 96, 28, ++ 65, 234, 11, 1, 225, 99, 0, 154, 2, 153, 115, 247, 70, 255, 2, 154, ++ 184, 241, 2, 15, 2, 235, 9, 1, 9, 208, 184, 241, 3, 15, 6, 208, 184, ++ 241, 5, 15, 7, 208, 184, 241, 6, 15, 4, 208, 8, 224, 4, 241, 17, 0, ++ 0, 154, 2, 224, 4, 241, 30, 0, 0, 154, 115, 247, 45, 255, 186, 70, 80, ++ 70, 5, 176, 135, 230, 3, 1, 146, 1, 210, 25, 13, 0, 45, 233, 255, 95, ++ 0, 38, 144, 70, 16, 6, 2, 213, 79, 240, 6, 11, 0, 224, 195, 70, 35, ++ 73, 255, 39, 0, 37, 140, 104, 138, 70, 36, 29, 1, 32, 0, 250, 3, 249, ++ 26, 224, 32, 120, 168, 177, 255, 47, 19, 209, 64, 69, 17, 209, 148, ++ 248, 59, 16, 0, 152, 129, 66, 12, 209, 90, 70, 96, 28, 1, 153, 112, ++ 247, 63, 252, 48, 185, 224, 107, 16, 234, 9, 15, 2, 208, 47, 70, 38, ++ 70, 6, 224, 64, 52, 109, 28, 237, 178, 154, 248, 2, 0, 133, 66, 224, ++ 211, 154, 248, 2, 0, 81, 70, 135, 66, 10, 210, 78, 177, 240, 107, 48, ++ 234, 9, 0, 240, 99, 4, 209, 48, 112, 136, 104, 1, 120, 73, 30, 1, 112, ++ 4, 176, 56, 70, 189, 232, 240, 159, 3, 1, 88, 96, 26, 13, 0, 240, 181, ++ 4, 77, 0, 35, 1, 36, 170, 104, 31, 70, 18, 29, 140, 64, 28, 224, 0, ++ 76, 252, 255, 68, 77, 33, 0, 0, 40, 94, 13, 0, 28, 52, 32, 0, 137, 104, ++ 13, 0, 0, 51, 32, 0, 146, 248, 59, 16, 129, 66, 12, 209, 17, 120, 81, ++ 177, 209, 107, 33, 66, 7, 208, 161, 67, 209, 99, 4, 209, 23, 112, 169, ++ 104, 14, 120, 118, 30, 14, 112, 64, 50, 91, 28, 219, 178, 169, 120, ++ 139, 66, 232, 211, 240, 189, 3, 1, 88, 180, 26, 13, 0, 45, 233, 240, ++ 71, 250, 79, 129, 70, 65, 240, 128, 6, 188, 104, 79, 240, 1, 8, 36, ++ 29, 0, 37, 21, 224, 148, 248, 59, 0, 128, 185, 32, 120, 176, 66, 1, ++ 208, 130, 40, 11, 209, 122, 120, 225, 107, 8, 250, 2, 240, 1, 66, 5, ++ 208, 6, 34, 97, 28, 72, 70, 112, 247, 211, 251, 56, 177, 64, 52, 109, ++ 28, 184, 120, 133, 66, 230, 211, 255, 32, 189, 232, 240, 135, 232, 178, ++ 251, 231, 3, 1, 206, 1, 8, 27, 13, 0, 45, 233, 240, 67, 146, 248, 0, ++ 128, 137, 176, 84, 28, 7, 70, 21, 70, 14, 70, 233, 70, 65, 69, 25, 209, ++ 79, 240, 0, 0, 74, 70, 15, 224, 5, 235, 0, 1, 59, 92, 145, 248, 17, ++ 192, 3, 234, 12, 3, 19, 84, 35, 92, 73, 124, 3, 234, 1, 3, 35, 84, 0, ++ 241, 1, 0, 192, 178, 176, 66, 237, 211, 50, 70, 33, 70, 72, 70, 57, ++ 224, 24, 210, 67, 70, 74, 70, 56, 70, 173, 247, 150, 76, 252, 255, 63, ++ 78, 33, 0, 252, 0, 32, 74, 70, 10, 224, 41, 24, 19, 92, 78, 124, 51, ++ 64, 19, 84, 35, 92, 73, 124, 11, 64, 35, 84, 64, 28, 192, 178, 65, 70, ++ 64, 69, 241, 211, 10, 70, 33, 70, 30, 224, 11, 70, 74, 70, 65, 70, 32, ++ 70, 173, 247, 124, 252, 51, 70, 4, 170, 65, 70, 5, 241, 17, 0, 0, 240, ++ 165, 251, 0, 32, 76, 70, 4, 173, 191, 75, 8, 224, 58, 92, 41, 92, 10, ++ 64, 26, 84, 34, 92, 10, 64, 34, 84, 64, 28, 192, 178, 176, 66, 244, ++ 211, 185, 73, 50, 70, 104, 70, 112, 247, 102, 251, 9, 176, 189, 232, ++ 240, 131, 3, 1, 154, 2, 210, 27, 13, 0, 45, 233, 243, 95, 129, 70, 178, ++ 72, 0, 38, 55, 70, 132, 104, 153, 248, 0, 0, 36, 29, 3, 40, 3, 210, ++ 0, 32, 1, 70, 189, 232, 252, 159, 153, 248, 1, 0, 79, 240, 1, 11, 7, ++ 40, 22, 208, 8, 220, 160, 241, 2, 0, 5, 40, 102, 210, 223, 232, 0, 240, ++ 12, 12, 14, 14, 16, 0, 20, 40, 6, 208, 21, 40, 8, 208, 22, 40, 59, 208, ++ 31, 40, 89, 209, 1, 224, 2, 32, 2, 224, 4, 32, 0, 224, 16, 32, 130, ++ 70, 0, 32, 40, 224, 155, 72, 132, 104, 36, 29, 0, 37, 28, 224, 33, 120, ++ 185, 177, 148, 248, 59, 32, 1, 153, 138, 66, 18, 209, 66, 120, 225, ++ 107, 11, 250, 76, 252, 255, 58, 79, 33, 0, 2, 240, 1, 66, 12, 208, 9, ++ 235, 8, 0, 128, 28, 34, 70, 81, 70, 255, 247, 81, 255, 32, 185, 11, ++ 250, 5, 240, 6, 67, 71, 234, 224, 119, 64, 52, 109, 28, 237, 178, 138, ++ 72, 129, 120, 141, 66, 222, 211, 8, 235, 10, 0, 192, 178, 153, 248, ++ 0, 16, 128, 70, 161, 235, 10, 1, 65, 69, 207, 220, 31, 224, 0, 37, 223, ++ 248, 8, 130, 23, 224, 33, 120, 145, 177, 148, 248, 59, 32, 1, 153, 138, ++ 66, 13, 209, 152, 248, 1, 32, 225, 107, 11, 250, 2, 240, 1, 66, 6, 208, ++ 34, 70, 2, 33, 9, 241, 2, 0, 255, 247, 33, 255, 72, 177, 64, 52, 109, ++ 28, 237, 178, 152, 248, 2, 16, 141, 66, 227, 211, 48, 70, 57, 70, 136, ++ 231, 11, 250, 5, 240, 193, 23, 6, 67, 15, 67, 246, 231, 3, 1, 34, 232, ++ 28, 13, 0, 11, 70, 192, 243, 128, 17, 109, 72, 194, 104, 64, 120, 2, ++ 235, 0, 16, 0, 104, 192, 7, 1, 208, 24, 70, 216, 230, 254, 32, 112, ++ 71, 3, 1, 74, 6, 29, 13, 0, 240, 181, 102, 77, 132, 70, 0, 32, 170, ++ 104, 108, 120, 18, 29, 79, 240, 1, 14, 1, 70, 3, 70, 14, 250, 4, 246, ++ 175, 120, 16, 224, 20, 120, 92, 177, 146, 248, 59, 64, 100, 69, 7, 209, ++ 213, 107, 53, 66, 4, 208, 14, 250, 3, 244, 32, 67, 65, 234, 228, 76, ++ 252, 255, 53, 80, 33, 0, 113, 64, 50, 91, 28, 219, 178, 187, 66, 236, ++ 211, 240, 189, 3, 1, 172, 2, 76, 29, 13, 0, 45, 233, 248, 79, 15, 70, ++ 250, 33, 1, 235, 16, 32, 69, 178, 0, 32, 128, 70, 130, 70, 6, 70, 129, ++ 70, 79, 72, 79, 73, 28, 70, 192, 104, 73, 120, 2, 43, 0, 235, 1, 16, ++ 2, 208, 254, 42, 5, 208, 8, 224, 254, 42, 6, 209, 0, 104, 64, 7, 1, ++ 224, 0, 104, 0, 7, 0, 40, 2, 219, 254, 32, 189, 232, 248, 143, 24, 70, ++ 255, 247, 182, 255, 0, 144, 139, 70, 8, 67, 102, 208, 191, 29, 48, 224, ++ 56, 120, 128, 179, 64, 28, 168, 66, 45, 220, 2, 44, 4, 208, 3, 44, 7, ++ 208, 2, 44, 21, 208, 30, 224, 120, 120, 128, 30, 5, 40, 7, 217, 15, ++ 224, 120, 120, 20, 40, 3, 208, 31, 40, 1, 208, 21, 40, 18, 209, 33, ++ 70, 56, 70, 255, 247, 250, 254, 64, 234, 8, 8, 65, 234, 10, 10, 9, 224, ++ 120, 120, 22, 40, 6, 209, 33, 70, 56, 70, 255, 247, 238, 254, 6, 67, ++ 65, 234, 9, 9, 23, 248, 1, 11, 41, 26, 73, 30, 77, 178, 7, 68, 1, 45, ++ 204, 220, 2, 44, 2, 208, 3, 44, 8, 208, 30, 224, 35, 72, 193, 104, 64, ++ 120, 1, 235, 0, 16, 0, 137, 64, 7, 6, 224, 31, 72, 193, 104, 64, 120, ++ 1, 235, 0, 16, 0, 137, 76, 252, 255, 48, 81, 33, 0, 0, 7, 0, 40, 13, ++ 218, 0, 154, 43, 234, 10, 0, 34, 234, 8, 1, 1, 67, 18, 208, 34, 234, ++ 6, 0, 43, 234, 9, 1, 8, 67, 12, 208, 13, 224, 0, 154, 10, 234, 11, 0, ++ 8, 234, 2, 1, 1, 67, 4, 209, 22, 64, 9, 234, 11, 0, 6, 67, 1, 208, 0, ++ 32, 143, 231, 255, 32, 141, 231, 3, 1, 10, 116, 30, 13, 0, 2, 35, 254, ++ 34, 104, 231, 3, 1, 10, 122, 30, 13, 0, 3, 35, 254, 34, 101, 231, 3, ++ 1, 160, 1, 128, 30, 13, 0, 45, 233, 240, 65, 7, 78, 250, 34, 2, 235, ++ 16, 32, 214, 233, 2, 82, 115, 120, 64, 178, 2, 235, 3, 18, 18, 104, ++ 210, 6, 6, 212, 254, 32, 201, 228, 0, 0, 40, 94, 13, 0, 108, 104, 13, ++ 0, 140, 29, 14, 224, 33, 120, 113, 177, 74, 28, 130, 66, 11, 220, 98, ++ 120, 8, 42, 10, 208, 9, 42, 8, 208, 64, 26, 64, 30, 100, 28, 64, 178, ++ 12, 68, 1, 40, 238, 220, 255, 32, 175, 228, 45, 29, 0, 39, 79, 240, ++ 1, 8, 23, 224, 42, 120, 146, 177, 149, 248, 59, 0, 4, 40, 14, 209, 32, ++ 120, 64, 30, 130, 66, 10, 220, 115, 120, 233, 107, 8, 250, 3, 240, 1, ++ 66, 4, 208, 161, 28, 104, 28, 112, 247, 200, 249, 48, 177, 64, 53, 127, ++ 28, 255, 178, 176, 120, 135, 66, 228, 211, 220, 76, 252, 255, 43, 82, ++ 33, 0, 231, 56, 70, 140, 228, 3, 1, 166, 2, 28, 31, 13, 0, 45, 233, ++ 248, 79, 13, 70, 250, 33, 1, 235, 16, 32, 79, 250, 128, 250, 234, 72, ++ 79, 240, 0, 7, 185, 70, 193, 104, 64, 120, 1, 235, 0, 16, 0, 104, 128, ++ 6, 1, 212, 254, 32, 36, 231, 5, 32, 255, 247, 221, 254, 131, 70, 0, ++ 145, 8, 67, 114, 208, 173, 29, 84, 224, 40, 120, 232, 179, 64, 28, 80, ++ 69, 82, 220, 104, 120, 255, 40, 68, 209, 219, 72, 132, 104, 36, 29, ++ 0, 38, 57, 224, 32, 120, 136, 179, 148, 248, 59, 16, 5, 41, 48, 209, ++ 41, 120, 73, 30, 136, 66, 44, 220, 156, 248, 4, 0, 144, 177, 0, 32, ++ 223, 248, 76, 131, 11, 224, 33, 24, 75, 120, 138, 127, 19, 64, 75, 112, ++ 41, 24, 137, 120, 17, 64, 8, 248, 0, 16, 64, 28, 192, 178, 33, 120, ++ 129, 66, 240, 216, 156, 248, 1, 32, 225, 107, 79, 240, 1, 8, 8, 250, ++ 2, 240, 1, 66, 13, 208, 34, 120, 197, 73, 96, 28, 112, 247, 101, 249, ++ 32, 185, 8, 250, 6, 240, 7, 67, 1, 224, 22, 224, 1, 224, 73, 234, 224, ++ 121, 64, 52, 118, 28, 246, 178, 223, 248, 240, 194, 156, 248, 2, 0, ++ 134, 66, 191, 211, 21, 248, 1, 11, 170, 235, 0, 1, 73, 30, 79, 250, ++ 129, 250, 5, 68, 186, 241, 1, 15, 167, 220, 179, 72, 76, 252, 255, 38, ++ 83, 33, 0, 193, 104, 64, 120, 1, 235, 0, 16, 0, 137, 128, 6, 7, 213, ++ 0, 155, 43, 234, 7, 1, 35, 234, 9, 0, 1, 67, 7, 208, 8, 224, 0, 154, ++ 7, 234, 11, 7, 9, 234, 2, 0, 7, 67, 1, 208, 0, 32, 170, 230, 255, 32, ++ 168, 230, 3, 1, 158, 2, 62, 32, 13, 0, 45, 233, 248, 79, 13, 70, 250, ++ 33, 1, 235, 16, 32, 71, 178, 79, 240, 0, 1, 161, 72, 137, 70, 138, 70, ++ 193, 104, 64, 120, 1, 235, 0, 16, 0, 104, 64, 6, 1, 212, 254, 32, 147, ++ 230, 6, 32, 255, 247, 76, 254, 131, 70, 0, 145, 8, 67, 110, 208, 173, ++ 29, 74, 224, 40, 120, 232, 179, 64, 28, 184, 66, 71, 220, 104, 120, ++ 22, 40, 60, 209, 147, 72, 132, 104, 36, 29, 0, 38, 47, 224, 32, 120, ++ 80, 179, 148, 248, 59, 16, 6, 41, 38, 209, 41, 120, 73, 30, 136, 66, ++ 34, 220, 156, 248, 4, 0, 144, 177, 0, 32, 223, 248, 40, 130, 11, 224, ++ 33, 24, 75, 120, 138, 127, 19, 64, 75, 112, 41, 24, 137, 120, 17, 64, ++ 8, 248, 0, 16, 64, 28, 192, 178, 33, 120, 129, 66, 240, 216, 156, 248, ++ 1, 32, 225, 107, 1, 32, 144, 64, 1, 66, 5, 208, 34, 120, 125, 73, 96, ++ 28, 112, 247, 214, 248, 16, 179, 64, 52, 118, 28, 246, 178, 223, 248, ++ 224, 193, 0, 224, 11, 224, 156, 76, 252, 255, 33, 84, 33, 0, 248, 2, ++ 0, 134, 66, 199, 211, 21, 248, 1, 11, 57, 26, 73, 30, 79, 178, 5, 68, ++ 1, 47, 178, 220, 112, 72, 193, 104, 64, 120, 1, 235, 0, 16, 0, 137, ++ 64, 6, 14, 213, 0, 155, 43, 234, 9, 0, 35, 234, 10, 1, 8, 67, 14, 208, ++ 15, 224, 1, 32, 176, 64, 64, 234, 9, 9, 74, 234, 224, 122, 224, 231, ++ 0, 155, 9, 234, 11, 1, 10, 234, 3, 0, 1, 67, 1, 208, 0, 32, 29, 230, ++ 255, 32, 27, 230, 3, 1, 230, 1, 88, 33, 13, 0, 45, 233, 240, 95, 147, ++ 70, 94, 74, 192, 178, 138, 70, 1, 240, 15, 4, 80, 112, 209, 104, 0, ++ 37, 1, 235, 0, 16, 46, 70, 144, 249, 11, 48, 1, 104, 233, 179, 0, 123, ++ 48, 177, 2, 40, 2, 208, 1, 40, 2, 208, 2, 224, 2, 38, 0, 224, 1, 38, ++ 83, 72, 208, 248, 3, 0, 144, 249, 1, 1, 152, 66, 61, 221, 145, 70, 8, ++ 4, 62, 212, 89, 70, 80, 70, 255, 247, 158, 253, 7, 70, 255, 40, 51, ++ 208, 1, 44, 51, 208, 89, 70, 80, 70, 255, 247, 91, 254, 255, 40, 43, ++ 208, 1, 35, 58, 70, 89, 70, 80, 70, 255, 247, 89, 250, 255, 40, 35, ++ 208, 223, 248, 4, 129, 0, 36, 8, 241, 20, 8, 79, 70, 88, 248, 36, 32, ++ 89, 70, 80, 70, 144, 71, 255, 40, 28, 208, 185, 120, 136, 66, 76, 252, ++ 255, 28, 85, 33, 0, 7, 210, 121, 120, 248, 104, 0, 224, 15, 224, 0, ++ 235, 1, 16, 128, 122, 120, 177, 100, 28, 228, 178, 4, 44, 233, 211, ++ 121, 120, 248, 104, 0, 235, 1, 16, 128, 122, 1, 40, 4, 208, 29, 177, ++ 0, 32, 30, 228, 254, 40, 251, 208, 48, 70, 26, 228, 121, 120, 248, 104, ++ 0, 235, 1, 16, 128, 122, 1, 40, 242, 208, 109, 28, 237, 178, 227, 231, ++ 3, 1, 46, 58, 34, 13, 0, 45, 233, 240, 65, 0, 37, 7, 70, 136, 70, 44, ++ 70, 36, 78, 7, 224, 66, 70, 57, 70, 32, 70, 255, 247, 130, 255, 5, 67, ++ 100, 28, 228, 178, 240, 120, 132, 66, 244, 211, 40, 70, 29, 230, 3, ++ 1, 36, 100, 34, 13, 0, 31, 72, 16, 181, 0, 104, 128, 7, 1, 213, 172, ++ 247, 111, 250, 25, 72, 0, 121, 0, 40, 3, 208, 189, 232, 16, 64, 255, ++ 247, 188, 186, 16, 189, 3, 1, 58, 132, 34, 13, 0, 16, 181, 20, 76, 160, ++ 104, 40, 177, 161, 120, 4, 34, 2, 235, 129, 17, 115, 247, 172, 248, ++ 224, 104, 24, 177, 225, 120, 9, 1, 115, 247, 166, 248, 32, 105, 24, ++ 177, 64, 242, 45, 17, 115, 247, 160, 248, 0, 32, 32, 112, 96, 112, 32, ++ 113, 16, 189, 3, 1, 54, 186, 34, 13, 0, 7, 72, 0, 121, 56, 185, 8, 72, ++ 0, 104, 128, 7, 5, 213, 7, 72, 0, 104, 0, 104, 8, 76, 252, 255, 23, ++ 86, 33, 0, 177, 1, 32, 112, 71, 0, 32, 112, 71, 40, 94, 13, 0, 108, ++ 104, 13, 0, 144, 149, 32, 0, 156, 41, 32, 0, 28, 52, 32, 0, 3, 1, 62, ++ 236, 34, 13, 0, 112, 181, 14, 70, 5, 70, 20, 70, 179, 66, 21, 217, 4, ++ 43, 12, 208, 255, 34, 16, 33, 32, 70, 162, 247, 217, 251, 50, 70, 41, ++ 70, 4, 241, 12, 0, 189, 232, 112, 64, 115, 247, 135, 186, 40, 120, 32, ++ 112, 104, 120, 96, 112, 255, 32, 224, 112, 144, 112, 112, 189, 3, 1, ++ 194, 2, 38, 35, 13, 0, 45, 233, 247, 79, 130, 176, 4, 0, 24, 208, 180, ++ 248, 80, 16, 180, 248, 78, 0, 13, 26, 149, 66, 0, 217, 21, 70, 40, 68, ++ 164, 248, 78, 0, 32, 108, 169, 70, 40, 68, 32, 100, 97, 106, 4, 241, ++ 16, 0, 79, 240, 0, 10, 0, 144, 81, 185, 129, 247, 236, 249, 24, 177, ++ 0, 32, 5, 176, 189, 232, 240, 143, 32, 105, 96, 98, 196, 248, 44, 160, ++ 212, 248, 36, 128, 4, 241, 85, 11, 87, 224, 180, 248, 76, 16, 224, 106, ++ 14, 26, 174, 66, 0, 217, 46, 70, 161, 105, 8, 241, 12, 7, 56, 68, 11, ++ 104, 50, 70, 3, 153, 152, 71, 3, 144, 148, 248, 84, 0, 48, 177, 224, ++ 106, 50, 70, 193, 25, 88, 70, 148, 247, 66, 254, 8, 224, 148, 248, 85, ++ 0, 40, 177, 224, 106, 50, 70, 193, 76, 252, 255, 18, 87, 33, 0, 25, ++ 88, 70, 148, 247, 32, 254, 224, 106, 173, 27, 48, 68, 224, 98, 180, ++ 248, 76, 16, 136, 66, 44, 209, 64, 70, 129, 247, 171, 249, 4, 241, 8, ++ 1, 64, 70, 129, 247, 162, 249, 196, 248, 44, 160, 0, 152, 129, 247, ++ 166, 249, 216, 177, 196, 248, 36, 160, 93, 177, 180, 248, 78, 0, 169, ++ 235, 5, 9, 160, 235, 5, 0, 164, 248, 78, 0, 32, 108, 160, 235, 5, 0, ++ 32, 100, 224, 105, 180, 248, 78, 32, 129, 104, 217, 177, 193, 139, 203, ++ 6, 24, 213, 193, 243, 1, 3, 1, 43, 6, 208, 8, 224, 32, 105, 96, 98, ++ 128, 70, 0, 45, 165, 209, 236, 231, 131, 139, 147, 66, 4, 217, 139, ++ 7, 8, 209, 131, 139, 147, 66, 5, 211, 33, 240, 16, 1, 193, 131, 130, ++ 104, 129, 105, 144, 71, 160, 105, 193, 139, 65, 240, 16, 1, 193, 131, ++ 32, 70, 148, 247, 171, 252, 72, 70, 128, 231, 0, 0, 3, 1, 148, 1, 100, ++ 36, 13, 0, 45, 233, 248, 67, 4, 0, 136, 70, 23, 70, 29, 70, 13, 208, ++ 96, 105, 0, 40, 11, 208, 114, 247, 239, 255, 6, 70, 224, 139, 128, 6, ++ 7, 213, 96, 105, 41, 70, 148, 247, 136, 255, 3, 224, 0, 32, 189, 232, ++ 248, 131, 0, 32, 56, 67, 173, 248, 0, 0, 141, 248, 2, 80, 35, 104, 3, ++ 34, 105, 70, 64, 70, 152, 71, 1, 70, 96, 105, 76, 252, 255, 13, 88, ++ 33, 0, 42, 70, 148, 247, 68, 253, 97, 105, 200, 105, 177, 248, 78, 32, ++ 129, 104, 161, 177, 193, 139, 203, 6, 17, 213, 193, 243, 1, 3, 1, 43, ++ 2, 209, 131, 139, 147, 66, 4, 217, 139, 7, 8, 209, 131, 139, 147, 66, ++ 5, 211, 33, 240, 16, 1, 193, 131, 130, 104, 129, 105, 144, 71, 48, 70, ++ 114, 247, 185, 255, 40, 70, 205, 231, 3, 1, 94, 244, 36, 13, 0, 45, ++ 233, 240, 65, 4, 0, 14, 70, 21, 70, 32, 208, 224, 139, 122, 73, 192, ++ 243, 129, 0, 49, 248, 16, 0, 160, 245, 112, 97, 255, 57, 22, 208, 148, ++ 248, 36, 0, 1, 40, 18, 209, 96, 105, 128, 177, 114, 247, 155, 255, 7, ++ 70, 96, 105, 41, 70, 148, 247, 66, 255, 96, 105, 42, 70, 49, 70, 148, ++ 247, 150, 253, 56, 70, 189, 232, 240, 65, 114, 247, 144, 191, 48, 70, ++ 189, 232, 240, 65, 17, 70, 148, 247, 183, 187, 3, 1, 186, 1, 78, 37, ++ 13, 0, 45, 233, 240, 65, 4, 0, 192, 139, 192, 243, 129, 6, 81, 208, ++ 96, 105, 0, 40, 78, 208, 48, 70, 121, 247, 94, 251, 5, 0, 2, 209, 90, ++ 247, 139, 251, 136, 177, 95, 72, 0, 235, 198, 7, 90, 247, 133, 251, ++ 56, 179, 93, 72, 0, 104, 16, 244, 64, 15, 96, 105, 176, 248, 76, 96, ++ 10, 208, 240, 46, 19, 217, 48, 70, 18, 224, 96, 105, 176, 248, 76, 252, ++ 255, 8, 89, 33, 0, 78, 16, 189, 232, 240, 65, 148, 247, 140, 188, 120, ++ 46, 1, 217, 48, 70, 0, 224, 120, 32, 168, 66, 11, 210, 120, 46, 6, 216, ++ 120, 37, 7, 224, 240, 32, 168, 66, 4, 210, 240, 46, 1, 217, 53, 70, ++ 0, 224, 240, 37, 96, 105, 14, 224, 96, 105, 176, 248, 76, 96, 60, 46, ++ 1, 217, 49, 70, 0, 224, 60, 33, 169, 66, 4, 210, 60, 46, 1, 217, 53, ++ 70, 0, 224, 60, 37, 41, 70, 148, 247, 234, 254, 96, 105, 42, 70, 57, ++ 70, 189, 232, 240, 65, 148, 247, 158, 188, 189, 232, 240, 129, 3, 1, ++ 252, 1, 4, 38, 13, 0, 45, 233, 240, 65, 5, 0, 192, 139, 58, 73, 192, ++ 243, 129, 6, 198, 235, 6, 16, 0, 235, 134, 16, 1, 235, 128, 7, 239, ++ 208, 104, 105, 0, 40, 236, 208, 48, 70, 121, 247, 221, 250, 4, 0, 231, ++ 208, 47, 72, 0, 31, 0, 235, 198, 6, 90, 247, 37, 251, 96, 179, 45, 72, ++ 0, 104, 16, 244, 64, 15, 104, 105, 176, 248, 76, 112, 3, 208, 240, 47, ++ 12, 217, 56, 70, 11, 224, 120, 47, 1, 217, 56, 70, 0, 224, 120, 32, ++ 160, 66, 11, 210, 120, 47, 6, 216, 120, 36, 7, 224, 240, 32, 160, 66, ++ 4, 210, 240, 47, 1, 217, 60, 70, 0, 224, 240, 36, 104, 105, 33, 70, ++ 148, 247, 151, 254, 104, 105, 34, 70, 49, 70, 148, 247, 235, 76, 252, ++ 255, 3, 90, 33, 0, 252, 40, 70, 189, 232, 240, 65, 89, 247, 171, 191, ++ 215, 248, 228, 16, 136, 2, 11, 213, 0, 32, 1, 224, 50, 104, 64, 28, ++ 176, 235, 84, 15, 250, 211, 33, 244, 0, 16, 199, 248, 228, 0, 163, 231, ++ 104, 105, 176, 248, 76, 112, 60, 47, 1, 217, 57, 70, 0, 224, 60, 33, ++ 161, 66, 4, 210, 60, 47, 1, 217, 60, 70, 0, 224, 60, 36, 33, 70, 148, ++ 247, 107, 254, 104, 105, 34, 70, 49, 70, 189, 232, 240, 65, 148, 247, ++ 189, 188, 0, 0, 180, 49, 32, 0, 8, 16, 53, 0, 88, 30, 32, 0, 172, 117, ++ 32, 0, 3, 1, 32, 252, 38, 13, 0, 16, 181, 107, 247, 45, 255, 0, 40, ++ 6, 208, 1, 33, 128, 248, 237, 16, 189, 232, 16, 64, 107, 247, 48, 190, ++ 16, 189, 0, 0, 3, 1, 136, 2, 24, 39, 13, 0, 45, 233, 240, 95, 69, 105, ++ 176, 248, 30, 192, 4, 70, 135, 140, 181, 248, 76, 32, 0, 106, 139, 70, ++ 204, 243, 129, 8, 22, 70, 0, 40, 28, 208, 50, 73, 223, 248, 204, 160, ++ 9, 136, 139, 6, 79, 240, 210, 1, 9, 212, 218, 248, 0, 48, 51, 185, 187, ++ 7, 91, 15, 33, 250, 3, 243, 219, 67, 155, 7, 9, 208, 187, 7, 91, 15, ++ 217, 64, 1, 240, 3, 1, 79, 240, 1, 9, 2, 41, 3, 208, 69, 224, 0, 32, ++ 189, 232, 240, 159, 95, 234, 140, 76, 252, 255, 254, 90, 33, 0, 97, ++ 63, 212, 120, 247, 93, 250, 16, 177, 187, 241, 0, 15, 29, 208, 184, ++ 6, 0, 213, 118, 16, 31, 73, 193, 248, 176, 146, 225, 139, 30, 74, 193, ++ 243, 129, 1, 81, 92, 142, 64, 28, 73, 14, 96, 27, 73, 9, 250, 8, 240, ++ 8, 57, 8, 96, 10, 104, 2, 66, 252, 209, 32, 106, 181, 248, 76, 32, 12, ++ 48, 22, 73, 162, 247, 173, 249, 7, 224, 96, 105, 0, 33, 176, 248, 76, ++ 32, 32, 106, 12, 48, 162, 247, 198, 249, 33, 106, 79, 244, 0, 80, 136, ++ 96, 218, 248, 0, 0, 24, 177, 32, 106, 79, 244, 192, 65, 129, 96, 132, ++ 248, 39, 144, 105, 108, 181, 248, 76, 32, 72, 70, 17, 68, 105, 100, ++ 186, 231, 41, 107, 12, 48, 230, 231, 0, 0, 8, 30, 32, 0, 164, 53, 32, ++ 0, 0, 144, 49, 0, 108, 93, 13, 0, 8, 141, 49, 0, 120, 142, 49, 0, 3, ++ 1, 56, 28, 40, 13, 0, 112, 181, 5, 70, 8, 70, 1, 38, 144, 248, 163, ++ 0, 181, 248, 11, 64, 169, 122, 64, 9, 0, 34, 70, 247, 225, 252, 0, 40, ++ 9, 208, 64, 136, 160, 66, 0, 210, 4, 70, 42, 122, 33, 70, 48, 70, 77, ++ 247, 76, 248, 1, 32, 112, 189, 3, 1, 86, 80, 40, 13, 0, 16, 181, 4, ++ 70, 0, 33, 19, 32, 127, 247, 223, 251, 254, 247, 174, 248, 52, 72, 0, ++ 120, 1, 40, 76, 252, 255, 249, 91, 33, 0, 1, 209, 51, 73, 8, 112, 51, ++ 73, 0, 32, 8, 112, 51, 73, 193, 233, 10, 0, 140, 247, 200, 249, 113, ++ 247, 75, 249, 24, 177, 189, 232, 16, 64, 137, 247, 121, 191, 1, 32, ++ 89, 247, 121, 249, 180, 248, 9, 0, 0, 33, 48, 247, 215, 254, 189, 232, ++ 16, 64, 1, 240, 63, 190, 3, 1, 48, 162, 40, 13, 0, 16, 181, 4, 70, 10, ++ 34, 85, 33, 12, 32, 48, 247, 224, 254, 1, 70, 8, 48, 34, 104, 192, 248, ++ 2, 32, 98, 104, 192, 248, 6, 32, 34, 137, 66, 129, 189, 232, 16, 64, ++ 8, 70, 48, 247, 96, 190, 3, 1, 122, 206, 40, 13, 0, 62, 181, 0, 241, ++ 9, 4, 0, 32, 0, 144, 1, 144, 2, 144, 212, 248, 3, 0, 0, 144, 212, 248, ++ 7, 0, 1, 144, 180, 248, 11, 0, 173, 248, 8, 0, 21, 70, 104, 70, 136, ++ 247, 145, 254, 33, 123, 9, 6, 23, 212, 20, 40, 21, 211, 15, 73, 10, ++ 34, 9, 29, 224, 28, 111, 247, 197, 252, 0, 40, 12, 208, 224, 28, 112, ++ 247, 20, 252, 144, 247, 245, 250, 32, 177, 144, 247, 27, 251, 224, 28, ++ 255, 247, 189, 255, 137, 247, 79, 249, 62, 189, 18, 32, 104, 113, 62, ++ 189, 78, 94, 13, 0, 151, 30, 32, 0, 76, 94, 13, 0, 24, 65, 32, 0, 3, ++ 1, 20, 68, 41, 13, 0, 124, 72, 129, 104, 194, 248, 6, 16, 76, 252, 255, ++ 244, 92, 33, 0, 192, 104, 194, 248, 10, 0, 112, 71, 3, 1, 62, 84, 41, ++ 13, 0, 112, 181, 121, 76, 14, 70, 0, 241, 9, 5, 161, 105, 49, 177, 176, ++ 248, 9, 0, 189, 232, 112, 64, 12, 33, 48, 247, 108, 190, 115, 72, 113, ++ 247, 217, 250, 169, 247, 66, 250, 114, 72, 165, 97, 196, 233, 2, 4, ++ 111, 72, 113, 247, 214, 250, 0, 32, 48, 112, 112, 189, 3, 1, 44, 142, ++ 41, 13, 0, 112, 181, 4, 70, 13, 70, 22, 70, 160, 247, 192, 254, 40, ++ 185, 0, 35, 26, 70, 25, 70, 2, 32, 254, 247, 28, 248, 50, 70, 41, 70, ++ 32, 70, 189, 232, 112, 64, 130, 247, 5, 189, 3, 1, 40, 182, 41, 13, ++ 0, 112, 181, 0, 241, 9, 4, 21, 70, 130, 247, 54, 253, 104, 121, 0, 40, ++ 7, 209, 34, 29, 225, 120, 189, 232, 112, 64, 0, 35, 1, 32, 254, 247, ++ 4, 184, 112, 189, 3, 1, 182, 2, 218, 41, 13, 0, 45, 233, 252, 65, 0, ++ 241, 9, 4, 0, 38, 171, 247, 66, 254, 64, 185, 87, 72, 68, 242, 16, 1, ++ 0, 104, 8, 66, 4, 208, 171, 247, 119, 254, 8, 177, 12, 38, 125, 224, ++ 180, 248, 5, 16, 180, 248, 3, 0, 69, 247, 80, 253, 32, 179, 97, 139, ++ 32, 139, 205, 233, 0, 1, 227, 138, 162, 138, 97, 138, 32, 138, 69, 247, ++ 86, 253, 200, 177, 97, 247, 143, 255, 192, 177, 76, 252, 255, 239, 93, ++ 33, 0, 0, 32, 111, 247, 245, 253, 7, 70, 255, 40, 20, 208, 165, 247, ++ 16, 249, 56, 70, 111, 247, 119, 253, 5, 70, 63, 72, 113, 247, 112, 250, ++ 98, 139, 33, 139, 40, 70, 69, 247, 91, 253, 224, 121, 48, 177, 15, 224, ++ 18, 38, 79, 224, 13, 38, 77, 224, 9, 38, 75, 224, 32, 122, 133, 248, ++ 86, 0, 212, 248, 9, 0, 40, 101, 180, 248, 13, 0, 165, 248, 84, 0, 224, ++ 123, 133, 248, 87, 0, 32, 138, 165, 248, 72, 0, 96, 138, 165, 248, 74, ++ 0, 149, 248, 210, 0, 165, 247, 139, 252, 33, 138, 1, 128, 97, 138, 65, ++ 128, 160, 138, 40, 129, 224, 138, 104, 129, 40, 70, 168, 247, 241, 254, ++ 37, 72, 113, 247, 67, 250, 41, 70, 32, 70, 130, 247, 232, 250, 0, 40, ++ 38, 209, 1, 32, 171, 247, 197, 253, 56, 70, 171, 247, 190, 253, 180, ++ 248, 5, 0, 32, 240, 1, 0, 171, 247, 27, 254, 180, 248, 3, 0, 32, 240, ++ 1, 0, 171, 247, 29, 254, 224, 121, 171, 247, 10, 254, 25, 73, 0, 32, ++ 254, 247, 28, 249, 0, 33, 8, 70, 171, 247, 89, 253, 110, 247, 104, 249, ++ 21, 73, 8, 96, 32, 136, 49, 70, 189, 232, 252, 65, 48, 247, 203, 189, ++ 189, 232, 252, 129, 3, 1, 76, 12, 43, 13, 0, 16, 181, 4, 70, 171, 247, ++ 172, 253, 64, 177, 0, 32, 171, 247, 151, 253, 189, 232, 76, 252, 255, ++ 234, 94, 33, 0, 16, 64, 10, 73, 16, 32, 254, 247, 254, 184, 180, 248, ++ 9, 0, 189, 232, 16, 64, 12, 33, 48, 247, 137, 189, 0, 0, 16, 130, 32, ++ 0, 244, 239, 32, 0, 136, 41, 32, 0, 99, 133, 1, 0, 156, 41, 32, 0, 92, ++ 239, 32, 0, 20, 52, 32, 0, 3, 1, 106, 84, 43, 13, 0, 45, 233, 240, 65, ++ 5, 70, 0, 241, 9, 4, 14, 70, 144, 70, 224, 28, 112, 247, 5, 253, 208, ++ 177, 193, 105, 193, 243, 196, 1, 4, 41, 21, 208, 8, 41, 19, 210, 7, ++ 70, 0, 241, 40, 1, 112, 247, 69, 253, 160, 177, 248, 105, 128, 2, 10, ++ 212, 56, 104, 140, 247, 203, 249, 48, 177, 57, 104, 11, 32, 48, 247, ++ 112, 254, 56, 104, 113, 247, 10, 248, 66, 70, 49, 70, 40, 70, 189, 232, ++ 240, 65, 124, 247, 110, 187, 32, 136, 189, 232, 240, 65, 18, 33, 48, ++ 247, 114, 189, 3, 1, 54, 186, 43, 13, 0, 45, 233, 240, 65, 5, 70, 14, ++ 70, 0, 241, 9, 4, 23, 70, 128, 137, 3, 33, 112, 247, 67, 253, 48, 177, ++ 58, 70, 49, 70, 40, 70, 189, 232, 240, 65, 124, 247, 142, 188, 32, 136, ++ 189, 232, 240, 65, 2, 33, 48, 247, 89, 189, 3, 1, 84, 236, 43, 13, 0, ++ 0, 35, 210, 30, 252, 42, 32, 211, 4, 41, 30, 211, 2, 104, 65, 104, 138, ++ 66, 3, 208, 10, 177, 193, 185, 76, 252, 255, 229, 95, 33, 0, 0, 224, ++ 177, 177, 1, 122, 66, 123, 145, 66, 18, 209, 65, 138, 129, 177, 129, ++ 138, 113, 177, 208, 248, 22, 32, 208, 248, 26, 16, 138, 66, 3, 208, ++ 10, 177, 49, 185, 0, 224, 33, 177, 129, 127, 144, 248, 35, 0, 129, 66, ++ 0, 208, 18, 35, 24, 70, 112, 71, 3, 1, 100, 60, 44, 13, 0, 1, 70, 22, ++ 75, 209, 248, 22, 32, 9, 141, 0, 32, 201, 8, 178, 251, 241, 242, 25, ++ 104, 178, 245, 250, 95, 33, 244, 64, 1, 13, 208, 178, 245, 122, 95, ++ 17, 208, 178, 245, 122, 111, 6, 209, 1, 245, 0, 1, 33, 240, 56, 0, 24, ++ 96, 79, 244, 250, 48, 112, 71, 33, 240, 56, 0, 8, 48, 24, 96, 79, 244, ++ 122, 48, 112, 71, 1, 245, 128, 1, 33, 240, 56, 0, 16, 48, 24, 96, 79, ++ 244, 250, 32, 112, 71, 0, 0, 88, 30, 32, 0, 3, 1, 172, 1, 156, 44, 13, ++ 0, 45, 233, 240, 71, 4, 70, 13, 70, 254, 247, 169, 253, 79, 240, 7, ++ 9, 1, 40, 4, 208, 41, 104, 129, 248, 5, 144, 189, 232, 240, 135, 32, ++ 121, 18, 33, 247, 79, 2, 40, 8, 216, 3, 210, 98, 121, 59, 120, 154, ++ 66, 3, 210, 40, 185, 162, 122, 1, 42, 2, 217, 40, 104, 65, 113, 236, ++ 231, 46, 104, 223, 248, 192, 131, 240, 113, 32, 121, 56, 177, 1, 40, ++ 25, 208, 2, 33, 0, 32, 76, 252, 255, 224, 96, 33, 0, 171, 247, 111, ++ 253, 56, 120, 26, 224, 234, 74, 96, 121, 18, 104, 2, 235, 0, 16, 0, ++ 104, 24, 177, 41, 104, 23, 32, 72, 113, 211, 231, 152, 248, 0, 0, 58, ++ 120, 144, 66, 222, 210, 32, 70, 254, 247, 142, 253, 2, 224, 32, 70, ++ 254, 247, 181, 253, 57, 120, 152, 248, 0, 0, 8, 26, 48, 114, 40, 104, ++ 64, 121, 0, 40, 190, 209, 32, 121, 240, 113, 41, 104, 129, 248, 1, 144, ++ 184, 231, 3, 1, 176, 1, 68, 45, 13, 0, 45, 233, 240, 65, 4, 70, 13, ++ 70, 254, 247, 85, 253, 79, 240, 7, 8, 1, 40, 71, 209, 32, 121, 18, 39, ++ 2, 40, 8, 216, 2, 210, 33, 123, 2, 41, 4, 216, 204, 74, 97, 121, 18, ++ 120, 145, 66, 3, 211, 40, 104, 71, 113, 189, 232, 240, 129, 46, 104, ++ 40, 177, 1, 40, 19, 208, 2, 40, 28, 208, 119, 113, 245, 231, 32, 123, ++ 11, 70, 64, 240, 128, 2, 161, 29, 0, 32, 254, 247, 166, 253, 254, 40, ++ 36, 208, 253, 40, 17, 209, 41, 104, 23, 32, 72, 113, 229, 231, 32, 123, ++ 11, 70, 64, 240, 128, 2, 161, 29, 0, 32, 254, 247, 12, 254, 255, 40, ++ 217, 208, 2, 224, 0, 32, 254, 247, 77, 254, 40, 104, 64, 121, 0, 40, ++ 211, 209, 32, 121, 240, 113, 41, 104, 180, 72, 129, 248, 1, 128, 0, ++ 104, 179, 73, 0, 120, 9, 120, 8, 76, 252, 255, 219, 97, 33, 0, 26, 48, ++ 114, 198, 231, 41, 104, 129, 248, 5, 128, 194, 231, 3, 1, 254, 1, 240, ++ 45, 13, 0, 45, 233, 240, 71, 4, 70, 13, 70, 0, 38, 254, 247, 254, 252, ++ 79, 240, 7, 9, 1, 40, 109, 209, 32, 121, 2, 40, 2, 210, 161, 120, 201, ++ 30, 206, 178, 79, 240, 18, 8, 200, 177, 2, 40, 19, 216, 161, 120, 2, ++ 41, 16, 211, 2, 40, 22, 216, 157, 74, 97, 121, 18, 120, 145, 66, 9, ++ 210, 2, 40, 15, 210, 16, 46, 5, 216, 2, 46, 11, 208, 4, 46, 9, 208, ++ 16, 46, 7, 208, 41, 104, 129, 248, 5, 128, 52, 231, 241, 7, 249, 209, ++ 118, 8, 227, 231, 47, 104, 48, 177, 1, 40, 25, 208, 2, 40, 38, 208, ++ 135, 248, 5, 128, 39, 231, 224, 120, 99, 121, 3, 40, 50, 70, 4, 241, ++ 6, 1, 7, 208, 3, 32, 254, 247, 54, 253, 254, 40, 49, 208, 253, 40, 2, ++ 208, 27, 224, 2, 32, 246, 231, 41, 104, 23, 32, 72, 113, 18, 231, 224, ++ 120, 99, 121, 3, 40, 50, 70, 4, 241, 6, 1, 5, 208, 3, 32, 254, 247, ++ 151, 253, 255, 40, 205, 208, 8, 224, 2, 32, 248, 231, 224, 120, 97, ++ 121, 3, 40, 19, 208, 3, 32, 254, 247, 210, 253, 40, 104, 64, 121, 0, ++ 40, 194, 209, 32, 121, 248, 113, 41, 104, 119, 72, 129, 248, 1, 144, ++ 0, 104, 118, 73, 0, 120, 76, 252, 255, 214, 98, 33, 0, 9, 120, 8, 26, ++ 56, 114, 235, 230, 2, 32, 234, 231, 41, 104, 129, 248, 5, 144, 229, ++ 230, 3, 1, 248, 1, 234, 46, 13, 0, 45, 233, 240, 65, 4, 70, 13, 70, ++ 254, 247, 130, 252, 7, 39, 1, 40, 109, 209, 35, 121, 79, 240, 18, 8, ++ 2, 43, 7, 216, 160, 120, 3, 40, 4, 211, 99, 74, 97, 121, 18, 120, 145, ++ 66, 3, 211, 41, 104, 129, 248, 5, 128, 43, 231, 192, 30, 194, 178, 224, ++ 120, 46, 104, 6, 40, 3, 208, 7, 40, 1, 208, 99, 177, 0, 224, 35, 177, ++ 1, 43, 33, 208, 2, 43, 50, 208, 60, 224, 211, 7, 2, 208, 134, 248, 5, ++ 128, 22, 231, 82, 8, 5, 40, 12, 208, 11, 70, 6, 40, 4, 241, 6, 1, 11, ++ 208, 6, 32, 254, 247, 196, 252, 254, 40, 58, 208, 253, 40, 6, 208, 39, ++ 224, 11, 70, 161, 29, 4, 32, 244, 231, 5, 32, 242, 231, 41, 104, 23, ++ 32, 72, 113, 252, 230, 5, 40, 10, 208, 11, 70, 6, 40, 4, 241, 6, 1, ++ 9, 208, 6, 32, 254, 247, 33, 253, 255, 40, 192, 208, 16, 224, 11, 70, ++ 161, 29, 4, 32, 246, 231, 5, 32, 244, 231, 5, 40, 3, 208, 6, 40, 3, ++ 208, 6, 32, 2, 224, 4, 32, 0, 224, 5, 32, 254, 247, 84, 253, 40, 104, ++ 64, 121, 0, 40, 173, 209, 32, 121, 240, 113, 40, 104, 57, 73, 71, 76, ++ 252, 255, 209, 99, 33, 0, 112, 55, 72, 9, 120, 0, 104, 0, 120, 8, 26, ++ 48, 114, 206, 230, 40, 104, 71, 113, 203, 230, 3, 1, 152, 1, 222, 47, ++ 13, 0, 112, 181, 140, 176, 0, 241, 9, 4, 205, 248, 40, 208, 0, 32, 5, ++ 38, 141, 248, 5, 0, 141, 248, 1, 96, 224, 120, 109, 70, 8, 40, 34, 210, ++ 223, 232, 0, 240, 4, 13, 18, 23, 23, 28, 28, 28, 41, 73, 32, 121, 8, ++ 112, 141, 248, 7, 0, 6, 32, 141, 248, 1, 0, 22, 224, 10, 169, 32, 70, ++ 255, 247, 60, 254, 17, 224, 10, 169, 32, 70, 255, 247, 139, 254, 12, ++ 224, 10, 169, 32, 70, 255, 247, 220, 254, 7, 224, 10, 169, 32, 70, 255, ++ 247, 84, 255, 2, 224, 18, 32, 141, 248, 5, 0, 10, 153, 0, 41, 10, 208, ++ 32, 70, 145, 247, 56, 253, 10, 152, 65, 121, 1, 177, 70, 112, 168, 66, ++ 3, 209, 48, 247, 220, 250, 12, 176, 112, 189, 8, 56, 48, 247, 143, 250, ++ 249, 231, 3, 1, 78, 114, 48, 13, 0, 16, 181, 20, 70, 80, 247, 173, 255, ++ 14, 73, 8, 120, 8, 177, 13, 72, 0, 136, 32, 129, 72, 120, 1, 40, 3, ++ 209, 224, 114, 3, 72, 0, 120, 32, 115, 0, 32, 96, 115, 16, 189, 0, 0, ++ 43, 94, 13, 0, 40, 94, 13, 0, 52, 94, 13, 0, 48, 94, 13, 0, 42, 94, ++ 13, 0, 44, 94, 13, 0, 216, 76, 252, 255, 204, 100, 33, 0, 11, 33, 0, ++ 84, 41, 32, 0, 3, 1, 154, 1, 188, 48, 13, 0, 45, 233, 240, 65, 0, 241, ++ 9, 1, 5, 123, 64, 123, 78, 121, 16, 114, 149, 113, 192, 243, 65, 1, ++ 20, 70, 0, 240, 1, 7, 214, 113, 3, 41, 5, 208, 41, 6, 5, 213, 17, 32, ++ 80, 113, 189, 232, 240, 129, 18, 32, 250, 231, 4, 45, 1, 210, 108, 73, ++ 1, 224, 107, 73, 9, 29, 171, 7, 79, 234, 211, 108, 10, 104, 255, 35, ++ 3, 250, 12, 243, 154, 67, 0, 250, 12, 240, 16, 67, 101, 74, 8, 96, 16, ++ 104, 79, 234, 133, 3, 79, 240, 15, 1, 1, 250, 3, 241, 32, 234, 1, 0, ++ 16, 96, 135, 240, 1, 2, 79, 240, 0, 1, 40, 70, 143, 247, 217, 249, 39, ++ 177, 40, 70, 143, 247, 198, 249, 198, 178, 3, 224, 49, 70, 40, 70, 143, ++ 247, 178, 249, 230, 113, 0, 32, 96, 113, 201, 231, 3, 1, 44, 82, 49, ++ 13, 0, 112, 181, 0, 241, 9, 5, 0, 123, 2, 33, 20, 70, 177, 235, 208, ++ 15, 2, 216, 48, 32, 80, 113, 112, 189, 143, 247, 174, 249, 224, 113, ++ 232, 120, 160, 113, 0, 32, 96, 113, 112, 189, 3, 1, 42, 122, 49, 13, ++ 0, 16, 181, 4, 70, 114, 247, 108, 249, 74, 74, 210, 248, 0, 17, 20, ++ 177, 65, 244, 0, 1, 1, 224, 33, 244, 0, 1, 194, 248, 0, 17, 189, 232, ++ 76, 252, 255, 199, 101, 33, 0, 16, 64, 114, 247, 97, 185, 3, 1, 78, ++ 160, 49, 13, 0, 112, 181, 4, 70, 13, 70, 114, 247, 88, 249, 65, 75, ++ 1, 70, 211, 248, 148, 32, 36, 177, 1, 44, 5, 208, 2, 44, 6, 208, 9, ++ 224, 34, 240, 1, 2, 6, 224, 66, 240, 3, 2, 3, 224, 34, 240, 2, 0, 64, ++ 240, 128, 2, 34, 244, 112, 16, 13, 177, 0, 245, 128, 32, 195, 248, 148, ++ 0, 189, 232, 112, 64, 8, 70, 114, 247, 60, 185, 3, 1, 44, 234, 49, 13, ++ 0, 16, 181, 48, 76, 56, 177, 0, 32, 95, 247, 42, 252, 32, 104, 64, 240, ++ 4, 0, 32, 96, 16, 189, 32, 104, 32, 240, 4, 0, 32, 96, 189, 232, 16, ++ 64, 0, 32, 95, 247, 183, 188, 3, 1, 68, 18, 50, 13, 0, 16, 181, 4, 70, ++ 39, 72, 2, 120, 90, 177, 1, 42, 23, 209, 33, 70, 1, 32, 255, 247, 188, ++ 255, 79, 240, 0, 0, 84, 177, 93, 247, 75, 250, 9, 224, 33, 70, 0, 32, ++ 255, 247, 178, 255, 32, 70, 189, 232, 16, 64, 210, 231, 93, 247, 107, ++ 250, 32, 70, 189, 232, 16, 64, 148, 231, 16, 189, 3, 1, 22, 82, 50, ++ 13, 0, 25, 73, 2, 123, 200, 124, 98, 243, 134, 16, 200, 116, 192, 243, ++ 128, 16, 214, 231, 3, 1, 20, 100, 50, 13, 0, 20, 72, 192, 124, 192, ++ 243, 128, 16, 144, 113, 0, 32, 80, 113, 76, 252, 255, 194, 102, 33, ++ 0, 112, 71, 3, 1, 30, 116, 50, 13, 0, 112, 181, 9, 48, 20, 70, 197, ++ 120, 195, 122, 1, 121, 66, 29, 40, 70, 253, 247, 172, 251, 0, 32, 96, ++ 113, 112, 189, 3, 1, 50, 142, 50, 13, 0, 16, 181, 144, 249, 13, 16, ++ 20, 70, 0, 123, 2, 240, 44, 248, 160, 113, 0, 32, 96, 113, 16, 189, ++ 104, 0, 50, 0, 136, 0, 50, 0, 0, 32, 53, 0, 0, 16, 53, 0, 96, 44, 32, ++ 0, 24, 65, 32, 0, 3, 1, 160, 1, 188, 50, 13, 0, 112, 181, 35, 76, 71, ++ 242, 68, 3, 5, 70, 1, 70, 194, 26, 32, 104, 153, 66, 48, 208, 6, 220, ++ 161, 245, 224, 65, 63, 57, 24, 208, 1, 41, 4, 209, 21, 224, 62, 42, ++ 31, 208, 188, 42, 23, 208, 45, 247, 61, 251, 8, 33, 3, 32, 113, 247, ++ 195, 255, 32, 104, 114, 247, 90, 250, 40, 70, 137, 247, 107, 248, 189, ++ 232, 112, 64, 8, 33, 4, 32, 113, 247, 183, 191, 72, 247, 9, 254, 189, ++ 232, 112, 64, 139, 247, 74, 189, 114, 247, 73, 250, 189, 232, 112, 64, ++ 65, 247, 84, 191, 10, 73, 9, 105, 0, 41, 13, 208, 189, 232, 112, 64, ++ 8, 71, 8, 73, 2, 122, 11, 120, 154, 26, 10, 112, 114, 247, 55, 250, ++ 189, 232, 112, 64, 48, 247, 248, 184, 112, 189, 0, 0, 240, 39, 32, 0, ++ 200, 158, 32, 0, 164, 40, 32, 76, 252, 255, 189, 103, 33, 0, 0, 3, 1, ++ 36, 88, 51, 13, 0, 16, 181, 1, 70, 0, 36, 5, 72, 131, 247, 215, 250, ++ 32, 177, 1, 36, 71, 242, 10, 0, 137, 247, 204, 248, 32, 70, 16, 189, ++ 12, 96, 32, 0, 3, 1, 168, 1, 120, 51, 13, 0, 240, 181, 33, 76, 33, 75, ++ 33, 104, 66, 24, 154, 66, 2, 210, 8, 68, 32, 96, 240, 189, 178, 251, ++ 243, 241, 3, 251, 17, 32, 32, 96, 5, 32, 177, 251, 240, 247, 26, 74, ++ 80, 104, 8, 68, 80, 96, 1, 32, 6, 70, 19, 104, 6, 250, 0, 244, 35, 66, ++ 3, 208, 19, 24, 28, 122, 229, 25, 29, 114, 64, 28, 17, 40, 243, 211, ++ 0, 32, 2, 235, 128, 3, 28, 127, 52, 177, 92, 139, 140, 66, 1, 216, 94, ++ 131, 1, 224, 100, 26, 92, 131, 64, 28, 8, 40, 241, 211, 11, 72, 192, ++ 124, 64, 7, 209, 212, 10, 72, 0, 120, 24, 177, 9, 72, 2, 136, 10, 68, ++ 2, 128, 8, 72, 2, 120, 17, 68, 1, 112, 240, 189, 0, 0, 212, 35, 32, ++ 0, 72, 232, 1, 0, 212, 96, 32, 0, 24, 65, 32, 0, 146, 38, 32, 0, 144, ++ 38, 32, 0, 76, 35, 32, 0, 3, 1, 42, 28, 52, 13, 0, 16, 181, 4, 70, 0, ++ 109, 72, 177, 62, 74, 180, 248, 156, 16, 64, 242, 113, 35, 18, 120, ++ 90, 67, 81, 67, 113, 247, 169, 254, 32, 70, 189, 232, 76, 252, 255, ++ 184, 104, 33, 0, 16, 64, 76, 247, 117, 186, 3, 1, 162, 1, 66, 52, 13, ++ 0, 112, 181, 4, 70, 103, 247, 216, 250, 5, 70, 32, 70, 146, 247, 195, ++ 255, 32, 70, 112, 247, 246, 251, 112, 177, 148, 248, 163, 0, 192, 6, ++ 10, 213, 224, 105, 192, 243, 196, 0, 10, 40, 5, 209, 32, 70, 128, 247, ++ 110, 254, 32, 104, 96, 247, 72, 249, 224, 105, 192, 243, 196, 1, 8, ++ 41, 3, 211, 32, 240, 248, 0, 104, 48, 224, 97, 32, 70, 75, 247, 179, ++ 255, 225, 105, 36, 72, 193, 243, 192, 49, 65, 240, 14, 1, 41, 115, 148, ++ 248, 161, 16, 105, 115, 104, 96, 32, 72, 168, 96, 41, 70, 32, 70, 75, ++ 247, 211, 255, 32, 32, 114, 247, 194, 248, 5, 0, 15, 208, 34, 70, 27, ++ 73, 113, 247, 24, 253, 26, 72, 180, 248, 156, 16, 64, 242, 113, 34, ++ 0, 120, 80, 67, 65, 67, 40, 70, 113, 247, 88, 254, 37, 101, 1, 32, 112, ++ 189, 3, 1, 88, 224, 52, 13, 0, 112, 181, 5, 70, 12, 70, 177, 248, 3, ++ 0, 2, 33, 112, 247, 179, 248, 120, 177, 208, 248, 228, 16, 193, 243, ++ 4, 33, 9, 41, 9, 208, 97, 121, 5, 248, 161, 31, 22, 33, 105, 112, 189, ++ 232, 112, 64, 5, 33, 115, 247, 8, 189, 40, 70, 189, 232, 112, 64, 7, ++ 34, 1, 33, 120, 247, 209, 188, 55, 49, 32, 0, 171, 100, 6, 0, 76, 252, ++ 255, 179, 105, 33, 0, 167, 100, 6, 0, 209, 99, 6, 0, 77, 94, 13, 0, ++ 3, 1, 72, 52, 53, 13, 0, 16, 181, 193, 105, 193, 243, 192, 49, 177, ++ 177, 12, 73, 2, 142, 9, 136, 15, 42, 1, 208, 11, 4, 15, 213, 9, 75, ++ 17, 36, 91, 104, 27, 123, 180, 235, 83, 15, 3, 208, 15, 42, 6, 209, ++ 137, 4, 4, 213, 0, 104, 131, 247, 14, 251, 0, 32, 16, 189, 35, 32, 16, ++ 189, 8, 30, 32, 0, 164, 35, 32, 0, 3, 1, 60, 120, 53, 13, 0, 16, 181, ++ 9, 76, 32, 33, 9, 72, 151, 247, 253, 253, 8, 72, 113, 247, 39, 254, ++ 32, 70, 103, 247, 43, 255, 8, 177, 140, 247, 93, 248, 5, 73, 139, 32, ++ 8, 96, 16, 189, 0, 0, 200, 217, 32, 0, 136, 96, 32, 0, 168, 96, 32, ++ 0, 236, 138, 49, 0, 3, 1, 124, 176, 53, 13, 0, 112, 181, 4, 70, 6, 41, ++ 3, 209, 148, 248, 181, 0, 192, 8, 1, 208, 0, 32, 112, 189, 4, 34, 128, ++ 33, 32, 70, 137, 247, 250, 248, 20, 77, 3, 0, 4, 208, 104, 104, 0, 123, ++ 192, 243, 0, 2, 21, 224, 224, 105, 192, 243, 196, 1, 8, 41, 11, 209, ++ 14, 73, 9, 136, 9, 5, 17, 213, 0, 4, 15, 212, 32, 104, 112, 247, 113, ++ 251, 94, 247, 176, 252, 72, 177, 104, 104, 12, 35, 0, 123, 192, 243, ++ 0, 2, 23, 33, 32, 70, 76, 252, 255, 174, 106, 33, 0, 103, 247, 65, 250, ++ 2, 224, 32, 70, 138, 247, 53, 249, 1, 32, 112, 189, 0, 0, 164, 35, 32, ++ 0, 8, 30, 32, 0, 3, 1, 14, 40, 54, 13, 0, 17, 72, 0, 33, 192, 233, 12, ++ 17, 112, 71, 3, 1, 74, 50, 54, 13, 0, 112, 181, 0, 34, 15, 77, 16, 70, ++ 17, 70, 83, 35, 75, 67, 5, 235, 131, 3, 220, 105, 230, 2, 10, 213, 147, ++ 248, 155, 96, 4, 46, 6, 208, 196, 243, 196, 4, 8, 44, 2, 209, 179, 248, ++ 100, 0, 82, 28, 73, 28, 11, 41, 234, 219, 1, 42, 0, 208, 0, 32, 112, ++ 189, 0, 0, 24, 65, 32, 0, 104, 66, 32, 0, 3, 1, 32, 120, 54, 13, 0, ++ 5, 72, 16, 181, 128, 123, 32, 185, 139, 247, 171, 250, 8, 177, 2, 32, ++ 16, 189, 0, 32, 16, 189, 0, 0, 248, 91, 32, 0, 3, 1, 206, 1, 148, 54, ++ 13, 0, 112, 181, 53, 77, 40, 104, 128, 123, 109, 247, 171, 251, 41, ++ 104, 201, 110, 109, 247, 47, 251, 41, 104, 49, 78, 49, 75, 145, 248, ++ 237, 32, 194, 177, 145, 248, 229, 32, 154, 185, 47, 76, 209, 248, 200, ++ 32, 36, 104, 34, 66, 6, 208, 145, 248, 148, 64, 36, 6, 9, 212, 52, 120, ++ 160, 66, 6, 216, 41, 72, 42, 76, 0, 104, 36, 104, 32, 67, 2, 66, 1, ++ 208, 156, 120, 0, 224, 92, 120, 145, 248, 229, 0, 76, 252, 255, 169, ++ 107, 33, 0, 24, 177, 24, 92, 160, 66, 0, 217, 4, 70, 35, 72, 0, 104, ++ 0, 7, 0, 213, 220, 120, 209, 248, 192, 0, 64, 28, 22, 208, 136, 123, ++ 109, 247, 116, 251, 41, 104, 209, 248, 192, 16, 109, 247, 255, 250, ++ 27, 73, 0, 40, 7, 219, 42, 104, 79, 240, 255, 48, 194, 248, 192, 0, ++ 63, 32, 8, 112, 3, 224, 8, 120, 132, 66, 0, 210, 4, 70, 112, 120, 64, ++ 177, 69, 44, 6, 209, 40, 104, 144, 248, 168, 0, 76, 247, 229, 251, 0, ++ 177, 15, 36, 33, 70, 40, 104, 104, 247, 14, 254, 13, 72, 0, 120, 133, ++ 248, 52, 0, 112, 189, 3, 1, 58, 94, 55, 13, 0, 12, 73, 0, 235, 192, ++ 0, 1, 235, 128, 0, 112, 71, 0, 0, 240, 110, 32, 0, 220, 11, 33, 0, 48, ++ 36, 32, 0, 0, 38, 32, 0, 180, 48, 32, 0, 44, 36, 32, 0, 56, 30, 32, ++ 0, 24, 36, 32, 0, 32, 36, 32, 0, 120, 112, 32, 0, 3, 1, 72, 148, 55, ++ 13, 0, 112, 181, 4, 70, 13, 77, 109, 247, 21, 251, 128, 178, 41, 140, ++ 109, 247, 112, 251, 225, 139, 176, 235, 65, 15, 4, 217, 160, 123, 16, ++ 185, 168, 124, 46, 40, 6, 208, 113, 32, 160, 116, 5, 72, 0, 120, 132, ++ 248, 67, 0, 112, 189, 148, 248, 71, 0, 160, 116, 112, 189, 0, 0, 156, ++ 91, 32, 0, 248, 48, 32, 0, 3, 76, 252, 255, 164, 108, 33, 0, 1, 82, ++ 216, 55, 13, 0, 112, 181, 39, 73, 37, 76, 9, 120, 0, 41, 29, 208, 8, ++ 48, 1, 34, 225, 139, 130, 64, 35, 72, 17, 67, 225, 131, 144, 248, 48, ++ 0, 46, 37, 152, 177, 33, 73, 180, 249, 28, 0, 9, 120, 136, 66, 6, 220, ++ 64, 66, 136, 66, 3, 220, 148, 248, 54, 0, 0, 40, 5, 208, 32, 70, 94, ++ 247, 242, 251, 0, 40, 0, 208, 165, 116, 112, 189, 160, 139, 244, 231, ++ 3, 1, 98, 38, 56, 13, 0, 112, 181, 18, 76, 1, 34, 130, 64, 225, 139, ++ 4, 235, 64, 0, 17, 67, 225, 131, 0, 33, 65, 132, 15, 72, 46, 37, 144, ++ 248, 48, 0, 152, 177, 14, 73, 180, 249, 28, 0, 9, 120, 136, 66, 6, 220, ++ 64, 66, 136, 66, 3, 220, 148, 248, 54, 0, 0, 40, 5, 208, 32, 70, 94, ++ 247, 204, 251, 0, 40, 0, 208, 165, 116, 112, 189, 160, 139, 244, 231, ++ 0, 0, 156, 91, 32, 0, 31, 35, 32, 0, 248, 91, 32, 0, 32, 35, 32, 0, ++ 3, 1, 228, 1, 132, 56, 13, 0, 112, 181, 4, 70, 104, 247, 54, 249, 0, ++ 38, 1, 37, 88, 177, 63, 72, 0, 33, 6, 112, 32, 70, 156, 247, 211, 251, ++ 32, 70, 156, 247, 19, 252, 132, 248, 91, 80, 112, 189, 32, 70, 104, ++ 247, 1, 251, 0, 40, 249, 208, 32, 70, 225, 139, 156, 247, 196, 251, ++ 160, 123, 76, 252, 255, 159, 109, 33, 0, 109, 247, 154, 250, 161, 105, ++ 109, 247, 31, 250, 225, 139, 137, 30, 136, 66, 12, 216, 32, 70, 156, ++ 247, 31, 250, 47, 73, 8, 96, 47, 73, 8, 96, 47, 72, 5, 96, 109, 247, ++ 113, 250, 46, 73, 8, 96, 148, 248, 91, 0, 152, 177, 91, 247, 176, 249, ++ 73, 247, 219, 253, 1, 40, 11, 209, 32, 70, 90, 247, 80, 254, 56, 177, ++ 148, 248, 111, 0, 32, 177, 132, 248, 110, 80, 32, 70, 155, 247, 154, ++ 249, 132, 248, 91, 96, 148, 248, 107, 0, 232, 185, 148, 248, 40, 0, ++ 1, 40, 13, 208, 148, 248, 36, 0, 148, 248, 44, 16, 192, 243, 2, 0, 193, ++ 243, 2, 1, 136, 66, 3, 209, 148, 248, 41, 0, 2, 40, 11, 208, 32, 70, ++ 90, 247, 45, 254, 56, 177, 148, 248, 111, 0, 32, 177, 132, 248, 110, ++ 80, 32, 70, 155, 247, 119, 249, 32, 70, 189, 232, 112, 64, 156, 247, ++ 51, 187, 3, 1, 22, 100, 57, 13, 0, 16, 181, 4, 70, 156, 247, 147, 255, ++ 32, 70, 189, 232, 16, 64, 0, 240, 191, 184, 3, 1, 22, 118, 57, 13, 0, ++ 16, 181, 156, 247, 148, 248, 9, 73, 0, 32, 8, 112, 9, 73, 8, 128, 16, ++ 189, 3, 1, 48, 136, 57, 13, 0, 9, 73, 8, 72, 8, 96, 112, 71, 252, 38, ++ 32, 0, 8, 39, 32, 0, 160, 28, 32, 0, 156, 28, 32, 0, 164, 28, 32, 0, ++ 76, 252, 255, 154, 110, 33, 0, 172, 94, 13, 0, 176, 94, 13, 0, 80, 94, ++ 13, 0, 4, 39, 32, 0, 3, 1, 12, 180, 57, 13, 0, 49, 73, 48, 72, 8, 96, ++ 112, 71, 3, 1, 200, 1, 188, 57, 13, 0, 45, 233, 240, 65, 4, 70, 45, ++ 73, 144, 248, 86, 0, 9, 31, 69, 24, 32, 70, 104, 247, 147, 248, 0, 38, ++ 0, 40, 32, 70, 16, 208, 104, 247, 3, 250, 1, 39, 8, 177, 47, 112, 0, ++ 224, 46, 112, 160, 108, 158, 247, 212, 253, 224, 108, 158, 247, 178, ++ 253, 132, 248, 91, 112, 189, 232, 240, 129, 104, 247, 89, 250, 176, ++ 177, 148, 248, 91, 0, 24, 185, 160, 108, 144, 248, 39, 0, 80, 185, 91, ++ 247, 32, 249, 73, 247, 75, 253, 1, 40, 2, 209, 32, 70, 90, 247, 192, ++ 253, 132, 248, 91, 96, 32, 70, 189, 232, 240, 65, 90, 247, 240, 190, ++ 32, 70, 104, 247, 55, 250, 0, 40, 222, 208, 40, 120, 128, 177, 148, ++ 248, 91, 0, 24, 185, 160, 108, 144, 248, 39, 0, 72, 185, 91, 247, 2, ++ 249, 73, 247, 45, 253, 1, 40, 2, 209, 32, 70, 90, 247, 162, 253, 46, ++ 112, 32, 70, 90, 247, 213, 254, 160, 108, 158, 247, 149, 253, 224, 108, ++ 189, 232, 240, 65, 158, 247, 113, 189, 0, 0, 128, 94, 13, 0, 12, 39, ++ 32, 0, 3, 1, 44, 128, 58, 13, 0, 16, 181, 130, 247, 80, 251, 60, 72, ++ 0, 76, 252, 255, 149, 111, 33, 0, 33, 1, 112, 129, 128, 59, 73, 74, ++ 104, 9, 104, 162, 235, 1, 1, 57, 74, 193, 241, 255, 1, 210, 121, 161, ++ 235, 2, 1, 129, 112, 16, 189, 3, 1, 58, 168, 58, 13, 0, 2, 42, 22, 209, ++ 53, 72, 22, 41, 6, 208, 19, 41, 10, 208, 20, 41, 8, 208, 21, 41, 6, ++ 208, 12, 224, 1, 104, 45, 74, 33, 240, 255, 1, 146, 120, 4, 224, 1, ++ 104, 46, 74, 33, 240, 255, 1, 18, 120, 17, 67, 1, 96, 0, 32, 112, 71, ++ 3, 1, 26, 222, 58, 13, 0, 43, 72, 0, 104, 16, 177, 175, 242, 103, 1, ++ 1, 96, 175, 242, 67, 0, 40, 73, 200, 100, 112, 71, 3, 1, 176, 1, 244, ++ 58, 13, 0, 112, 181, 64, 108, 0, 40, 59, 208, 144, 249, 223, 0, 127, ++ 40, 55, 208, 28, 76, 35, 75, 1, 37, 97, 120, 73, 28, 1, 240, 15, 2, ++ 98, 112, 33, 70, 147, 249, 0, 96, 137, 136, 176, 66, 3, 218, 147, 249, ++ 1, 48, 152, 66, 4, 218, 5, 250, 2, 240, 129, 67, 161, 128, 3, 224, 5, ++ 250, 2, 240, 8, 67, 160, 128, 160, 136, 73, 247, 192, 252, 33, 120, ++ 33, 177, 4, 40, 5, 216, 0, 32, 32, 112, 2, 224, 8, 40, 0, 211, 37, 112, ++ 16, 74, 16, 104, 192, 243, 5, 65, 32, 41, 9, 209, 33, 120, 1, 41, 6, ++ 209, 13, 73, 64, 244, 128, 0, 16, 96, 76, 252, 255, 144, 112, 33, 0, ++ 8, 96, 80, 104, 72, 96, 112, 189, 0, 0, 172, 94, 13, 0, 144, 128, 49, ++ 0, 16, 30, 32, 0, 144, 139, 49, 0, 40, 37, 32, 0, 4, 29, 32, 0, 24, ++ 82, 32, 0, 222, 11, 33, 0, 188, 28, 32, 0, 96, 1, 101, 0, 3, 1, 94, ++ 160, 59, 13, 0, 91, 72, 79, 244, 128, 113, 0, 104, 1, 96, 1, 96, 89, ++ 72, 90, 73, 130, 104, 10, 99, 130, 106, 138, 99, 88, 75, 194, 104, 26, ++ 96, 88, 75, 2, 105, 26, 96, 87, 75, 66, 105, 26, 96, 87, 75, 130, 105, ++ 26, 96, 86, 75, 194, 105, 26, 96, 86, 75, 2, 106, 26, 96, 66, 106, 10, ++ 96, 84, 73, 64, 104, 8, 96, 84, 72, 1, 105, 33, 240, 1, 1, 1, 97, 1, ++ 104, 33, 240, 1, 1, 1, 96, 112, 71, 3, 1, 218, 1, 250, 59, 13, 0, 112, ++ 181, 5, 70, 174, 247, 7, 249, 76, 72, 0, 104, 67, 76, 0, 240, 63, 0, ++ 32, 99, 73, 72, 56, 56, 0, 104, 192, 243, 133, 1, 74, 17, 33, 240, 32, ++ 0, 224, 98, 1, 42, 4, 209, 128, 240, 31, 0, 64, 28, 64, 66, 224, 98, ++ 62, 72, 80, 48, 0, 104, 192, 243, 3, 48, 194, 16, 32, 240, 8, 1, 97, ++ 99, 1, 42, 4, 209, 129, 240, 7, 0, 64, 28, 64, 66, 96, 99, 173, 28, ++ 232, 178, 64, 240, 128, 1, 49, 72, 184, 56, 76, 252, 255, 139, 113, ++ 33, 0, 149, 247, 167, 255, 47, 73, 1, 32, 8, 96, 44, 72, 1, 107, 65, ++ 240, 207, 1, 1, 99, 79, 240, 15, 1, 129, 99, 79, 240, 28, 1, 1, 96, ++ 47, 72, 1, 105, 65, 240, 1, 1, 1, 97, 1, 104, 65, 240, 1, 1, 1, 96, ++ 36, 73, 71, 242, 193, 0, 8, 96, 35, 73, 79, 244, 192, 64, 8, 96, 34, ++ 72, 1, 104, 75, 246, 255, 114, 1, 234, 2, 1, 34, 104, 65, 234, 130, ++ 49, 1, 96, 31, 72, 1, 104, 33, 74, 33, 240, 127, 1, 18, 104, 65, 234, ++ 2, 1, 65, 240, 64, 1, 1, 96, 25, 73, 79, 244, 197, 64, 8, 96, 112, 189, ++ 3, 1, 6, 208, 60, 13, 0, 112, 71, 3, 1, 114, 210, 60, 13, 0, 17, 73, ++ 10, 107, 15, 72, 130, 96, 16, 74, 18, 104, 194, 96, 138, 107, 130, 98, ++ 14, 74, 18, 104, 2, 97, 14, 74, 18, 104, 66, 97, 13, 74, 18, 104, 130, ++ 97, 13, 74, 18, 104, 194, 97, 12, 74, 18, 104, 2, 98, 9, 104, 65, 98, ++ 11, 73, 9, 104, 65, 96, 112, 71, 0, 0, 208, 27, 32, 0, 184, 94, 13, ++ 0, 200, 0, 100, 0, 188, 1, 96, 0, 96, 4, 65, 0, 252, 4, 65, 0, 232, ++ 6, 65, 0, 88, 4, 65, 0, 40, 4, 65, 0, 228, 6, 65, 0, 96, 1, 101, 0, ++ 224, 11, 33, 0, 3, 1, 58, 64, 61, 13, 0, 76, 252, 255, 134, 114, 33, ++ 0, 248, 74, 255, 40, 2, 220, 50, 248, 16, 0, 112, 71, 255, 33, 144, ++ 251, 241, 241, 100, 35, 88, 67, 193, 235, 1, 35, 144, 251, 243, 240, ++ 178, 248, 200, 48, 50, 248, 16, 0, 50, 248, 17, 16, 192, 26, 178, 248, ++ 254, 49, 25, 68, 8, 68, 112, 71, 3, 1, 160, 1, 118, 61, 13, 0, 45, 233, ++ 240, 65, 0, 33, 234, 75, 10, 70, 8, 70, 14, 70, 79, 244, 0, 71, 232, ++ 77, 28, 104, 8, 224, 47, 96, 43, 104, 46, 96, 155, 4, 155, 12, 26, 68, ++ 0, 209, 64, 28, 73, 28, 161, 66, 244, 211, 160, 66, 3, 210, 32, 26, ++ 178, 251, 240, 240, 0, 224, 0, 32, 79, 244, 122, 113, 72, 67, 27, 33, ++ 176, 251, 241, 240, 64, 29, 10, 33, 144, 251, 241, 240, 255, 247, 187, ++ 255, 160, 245, 0, 64, 160, 245, 226, 80, 0, 235, 128, 0, 79, 234, 128, ++ 0, 66, 242, 16, 113, 144, 251, 241, 240, 211, 73, 9, 104, 160, 235, ++ 1, 1, 210, 72, 0, 104, 192, 241, 11, 0, 0, 235, 64, 0, 8, 68, 207, 73, ++ 9, 104, 160, 235, 1, 0, 206, 73, 9, 104, 64, 24, 1, 213, 64, 66, 64, ++ 66, 64, 178, 189, 232, 240, 129, 3, 1, 56, 18, 62, 13, 0, 112, 181, ++ 4, 70, 4, 241, 40, 1, 144, 248, 52, 0, 13, 70, 153, 247, 155, 255, 6, ++ 70, 255, 247, 166, 255, 1, 0, 76, 252, 255, 129, 115, 33, 0, 9, 208, ++ 48, 70, 153, 247, 219, 255, 118, 28, 41, 70, 240, 178, 153, 247, 142, ++ 255, 132, 248, 52, 0, 0, 32, 112, 189, 3, 1, 42, 70, 62, 13, 0, 16, ++ 181, 4, 70, 189, 72, 0, 104, 16, 240, 254, 15, 9, 208, 187, 72, 135, ++ 247, 224, 251, 24, 177, 68, 67, 79, 32, 180, 251, 240, 244, 4, 185, ++ 1, 36, 32, 70, 16, 189, 3, 1, 26, 108, 62, 13, 0, 182, 72, 16, 181, ++ 64, 136, 255, 247, 232, 255, 179, 73, 128, 0, 80, 57, 161, 248, 192, ++ 2, 16, 189, 3, 1, 120, 130, 62, 13, 0, 16, 181, 107, 247, 88, 255, 56, ++ 185, 98, 247, 240, 255, 32, 185, 132, 247, 11, 248, 8, 185, 135, 247, ++ 237, 250, 170, 76, 80, 60, 180, 248, 194, 2, 48, 177, 160, 241, 1, 0, ++ 0, 4, 0, 12, 164, 248, 194, 2, 9, 208, 166, 72, 144, 248, 59, 0, 64, ++ 7, 27, 213, 160, 76, 32, 104, 64, 8, 14, 209, 9, 224, 160, 72, 0, 120, ++ 255, 247, 188, 255, 164, 248, 194, 2, 189, 232, 16, 64, 135, 247, 137, ++ 190, 157, 72, 0, 136, 64, 7, 8, 213, 1, 34, 4, 33, 0, 32, 130, 247, ++ 84, 254, 32, 104, 64, 240, 1, 0, 32, 96, 16, 189, 3, 1, 122, 246, 62, ++ 13, 0, 112, 181, 0, 37, 107, 247, 29, 255, 145, 76, 80, 60, 104, 177, ++ 20, 32, 153, 247, 128, 251, 135, 76, 252, 255, 124, 116, 33, 0, 247, ++ 153, 251, 145, 72, 33, 109, 1, 37, 1, 96, 97, 109, 65, 96, 180, 248, ++ 88, 16, 1, 129, 98, 247, 165, 255, 16, 177, 153, 247, 80, 253, 0, 224, ++ 61, 177, 2, 32, 153, 247, 123, 255, 148, 248, 239, 0, 8, 177, 135, 247, ++ 115, 250, 131, 72, 144, 248, 59, 0, 64, 7, 16, 213, 125, 76, 32, 104, ++ 64, 8, 3, 209, 127, 72, 0, 136, 64, 7, 8, 213, 1, 34, 4, 33, 0, 32, ++ 130, 247, 25, 254, 32, 104, 64, 240, 1, 0, 32, 96, 112, 189, 3, 1, 58, ++ 108, 63, 13, 0, 112, 181, 120, 72, 116, 76, 117, 77, 0, 136, 164, 241, ++ 80, 4, 64, 7, 1, 213, 1, 32, 3, 224, 104, 136, 255, 247, 95, 255, 128, ++ 0, 164, 248, 192, 2, 108, 72, 0, 104, 64, 8, 2, 208, 40, 120, 255, 247, ++ 85, 255, 164, 248, 194, 2, 112, 189, 3, 1, 6, 162, 63, 13, 0, 112, 71, ++ 3, 1, 196, 3, 164, 63, 13, 0, 45, 233, 255, 71, 0, 39, 4, 70, 62, 70, ++ 103, 247, 113, 255, 0, 40, 116, 208, 108, 247, 67, 252, 0, 40, 112, ++ 209, 148, 248, 50, 0, 2, 40, 108, 208, 100, 72, 144, 248, 48, 0, 32, ++ 177, 151, 247, 235, 252, 176, 245, 28, 127, 99, 217, 160, 123, 2, 169, ++ 108, 247, 0, 255, 2, 152, 94, 77, 16, 240, 3, 0, 6, 208, 1, 40, 7, 208, ++ 2, 40, 76, 252, 255, 119, 117, 33, 0, 14, 208, 3, 40, 23, 209, 2, 224, ++ 1, 33, 2, 152, 13, 224, 40, 104, 3, 153, 64, 29, 129, 66, 6, 210, 2, ++ 153, 205, 233, 0, 16, 10, 224, 2, 152, 64, 28, 3, 224, 2, 33, 2, 152, ++ 108, 247, 69, 252, 0, 144, 40, 104, 64, 29, 1, 144, 160, 123, 2, 171, ++ 2, 70, 105, 70, 108, 247, 137, 253, 104, 70, 108, 247, 136, 254, 5, ++ 70, 223, 248, 232, 144, 148, 248, 50, 0, 223, 248, 12, 129, 169, 241, ++ 2, 9, 104, 177, 152, 248, 2, 16, 153, 248, 0, 0, 8, 68, 168, 66, 2, ++ 216, 181, 251, 240, 240, 199, 178, 0, 37, 79, 240, 2, 9, 70, 224, 1, ++ 32, 132, 248, 50, 0, 148, 248, 52, 0, 173, 247, 3, 255, 173, 247, 54, ++ 255, 152, 248, 2, 0, 152, 248, 3, 32, 153, 248, 0, 16, 131, 24, 1, 38, ++ 11, 68, 171, 66, 231, 210, 43, 26, 11, 68, 26, 68, 8, 68, 178, 251, ++ 240, 240, 64, 28, 222, 231, 62, 224, 148, 248, 52, 0, 4, 241, 40, 1, ++ 153, 247, 86, 254, 128, 28, 192, 178, 64, 240, 128, 1, 42, 72, 149, ++ 247, 120, 253, 70, 177, 152, 248, 2, 16, 152, 248, 3, 0, 8, 68, 73, ++ 247, 33, 250, 0, 38, 3, 224, 152, 248, 2, 0, 73, 247, 27, 250, 32, 70, ++ 153, 247, 140, 254, 148, 248, 52, 0, 78, 40, 5, 217, 132, 248, 50, 144, ++ 32, 76, 252, 255, 114, 118, 33, 0, 70, 127, 247, 110, 253, 3, 224, 109, ++ 28, 237, 178, 189, 66, 211, 211, 148, 248, 60, 0, 64, 28, 192, 178, ++ 132, 248, 60, 0, 78, 40, 10, 217, 148, 248, 50, 0, 1, 40, 6, 209, 132, ++ 248, 50, 144, 32, 70, 127, 247, 88, 253, 153, 247, 82, 255, 189, 232, ++ 255, 135, 10, 95, 13, 0, 228, 11, 33, 0, 232, 6, 65, 0, 228, 94, 13, ++ 0, 224, 11, 33, 0, 232, 94, 13, 0, 236, 94, 13, 0, 144, 86, 32, 0, 124, ++ 212, 32, 0, 168, 29, 32, 0, 24, 65, 32, 0, 180, 29, 32, 0, 221, 126, ++ 32, 0, 248, 91, 32, 0, 68, 43, 32, 0, 4, 1, 96, 0, 3, 1, 80, 100, 65, ++ 13, 0, 124, 181, 0, 37, 4, 70, 2, 41, 15, 208, 4, 41, 29, 209, 148, ++ 248, 50, 0, 0, 40, 25, 208, 89, 78, 160, 123, 105, 70, 108, 247, 46, ++ 254, 0, 152, 192, 67, 128, 7, 6, 208, 9, 224, 85, 72, 0, 104, 192, 243, ++ 2, 16, 160, 115, 7, 224, 1, 152, 49, 104, 136, 66, 236, 216, 173, 247, ++ 206, 254, 173, 247, 1, 255, 132, 248, 50, 80, 124, 189, 3, 1, 152, 1, ++ 176, 65, 13, 0, 16, 181, 77, 76, 0, 32, 132, 248, 60, 0, 148, 248, 64, ++ 0, 8, 185, 105, 247, 62, 251, 224, 142, 8, 177, 64, 30, 224, 134, 105, ++ 247, 71, 255, 106, 247, 125, 248, 69, 72, 127, 76, 252, 255, 109, 119, ++ 33, 0, 247, 175, 250, 32, 185, 67, 72, 0, 104, 0, 31, 106, 247, 7, 248, ++ 66, 72, 127, 247, 166, 250, 56, 185, 148, 248, 59, 0, 1, 40, 3, 216, ++ 105, 247, 228, 253, 105, 247, 86, 255, 130, 247, 6, 251, 0, 32, 142, ++ 247, 189, 251, 32, 104, 80, 177, 1, 124, 4, 41, 7, 209, 56, 73, 73, ++ 120, 33, 185, 148, 248, 59, 16, 9, 185, 255, 247, 193, 254, 148, 248, ++ 59, 0, 1, 40, 5, 208, 104, 247, 249, 253, 73, 247, 208, 248, 1, 32, ++ 16, 189, 105, 247, 128, 255, 0, 40, 247, 209, 73, 247, 240, 251, 244, ++ 231, 3, 1, 192, 1, 68, 66, 13, 0, 112, 181, 40, 76, 1, 32, 132, 248, ++ 60, 0, 105, 247, 247, 250, 0, 37, 79, 246, 255, 112, 37, 97, 224, 134, ++ 165, 97, 105, 247, 254, 254, 106, 247, 52, 248, 33, 72, 127, 247, 102, ++ 250, 32, 185, 31, 72, 0, 104, 0, 31, 105, 247, 190, 255, 105, 247, 137, ++ 255, 30, 72, 229, 96, 127, 247, 90, 250, 8, 185, 105, 247, 58, 254, ++ 104, 247, 131, 254, 1, 32, 142, 247, 119, 251, 32, 104, 56, 177, 1, ++ 124, 4, 41, 4, 209, 21, 73, 73, 120, 9, 185, 255, 247, 126, 254, 20, ++ 72, 0, 120, 8, 177, 252, 247, 69, 251, 1, 32, 104, 247, 158, 250, 24, ++ 185, 13, 72, 127, 247, 60, 250, 40, 177, 104, 247, 173, 253, 73, 247, ++ 132, 248, 76, 252, 255, 104, 120, 33, 0, 1, 32, 112, 189, 4, 72, 1, ++ 34, 17, 70, 3, 104, 16, 70, 91, 29, 104, 247, 145, 250, 242, 231, 68, ++ 43, 32, 0, 36, 134, 49, 0, 0, 63, 32, 0, 68, 28, 32, 0, 60, 28, 32, ++ 0, 168, 29, 32, 0, 52, 28, 32, 0, 201, 34, 32, 0, 3, 1, 248, 3, 0, 67, ++ 13, 0, 45, 233, 248, 79, 128, 79, 5, 70, 79, 240, 0, 8, 56, 104, 32, ++ 185, 40, 120, 0, 40, 126, 209, 112, 247, 201, 249, 113, 247, 158, 248, ++ 0, 144, 122, 72, 34, 33, 1, 96, 79, 244, 70, 25, 0, 38, 201, 248, 0, ++ 98, 4, 33, 201, 248, 4, 18, 79, 244, 72, 20, 38, 102, 201, 248, 0, 96, ++ 50, 32, 73, 247, 228, 248, 114, 72, 224, 101, 79, 244, 69, 17, 79, 240, ++ 128, 11, 193, 248, 12, 176, 200, 32, 73, 247, 217, 248, 40, 120, 79, ++ 244, 202, 10, 79, 244, 192, 4, 224, 177, 196, 248, 188, 97, 105, 72, ++ 6, 96, 212, 248, 252, 2, 32, 240, 12, 0, 196, 248, 252, 2, 56, 104, ++ 72, 177, 10, 245, 176, 112, 1, 105, 33, 240, 1, 1, 1, 97, 1, 104, 33, ++ 240, 1, 1, 1, 96, 0, 152, 113, 247, 100, 248, 40, 120, 52, 70, 208, ++ 179, 156, 224, 0, 32, 133, 247, 246, 253, 1, 33, 10, 245, 176, 112, ++ 57, 96, 2, 105, 66, 240, 1, 2, 2, 97, 2, 104, 66, 240, 1, 76, 252, 255, ++ 99, 121, 33, 0, 2, 2, 96, 72, 70, 201, 248, 0, 98, 201, 248, 4, 178, ++ 234, 120, 0, 42, 212, 248, 252, 34, 2, 208, 66, 240, 12, 2, 3, 224, ++ 34, 240, 12, 2, 66, 240, 8, 2, 196, 248, 252, 34, 75, 74, 137, 70, 17, ++ 96, 105, 120, 73, 74, 137, 30, 8, 50, 17, 96, 105, 120, 137, 30, 18, ++ 31, 17, 96, 70, 73, 1, 96, 0, 32, 79, 244, 122, 115, 79, 244, 69, 18, ++ 1, 70, 64, 28, 153, 66, 1, 224, 107, 224, 14, 224, 2, 216, 209, 104, ++ 9, 6, 245, 213, 79, 244, 72, 16, 79, 244, 0, 49, 1, 102, 200, 32, 73, ++ 247, 111, 248, 196, 248, 188, 145, 174, 231, 224, 178, 169, 120, 64, ++ 240, 1, 0, 96, 243, 7, 4, 6, 41, 25, 210, 223, 232, 1, 240, 3, 7, 14, ++ 39, 42, 46, 32, 240, 28, 0, 24, 48, 14, 224, 196, 243, 7, 32, 64, 240, ++ 1, 0, 96, 243, 15, 36, 9, 224, 196, 243, 7, 33, 65, 240, 1, 1, 97, 243, ++ 15, 36, 64, 240, 2, 0, 96, 243, 7, 4, 233, 120, 196, 243, 7, 32, 97, ++ 243, 131, 0, 96, 243, 15, 36, 40, 121, 7, 40, 15, 216, 0, 6, 128, 13, ++ 64, 66, 64, 178, 17, 224, 32, 240, 224, 0, 235, 231, 32, 240, 224, 0, ++ 32, 48, 231, 231, 32, 240, 224, 0, 160, 48, 227, 231, 8, 40, 2, 208, ++ 9, 40, 5, 208, 8, 224, 76, 252, 255, 94, 122, 33, 0, 149, 249, 5, 0, ++ 126, 247, 10, 250, 2, 224, 168, 121, 125, 247, 158, 254, 128, 70, 2, ++ 33, 64, 70, 165, 247, 69, 253, 8, 240, 255, 1, 17, 72, 149, 247, 104, ++ 251, 11, 72, 4, 96, 40, 120, 32, 177, 56, 104, 16, 177, 111, 247, 91, ++ 255, 62, 96, 1, 32, 189, 232, 248, 143, 3, 1, 48, 244, 68, 13, 0, 16, ++ 181, 20, 70, 12, 48, 255, 247, 1, 255, 0, 40, 1, 209, 18, 32, 96, 113, ++ 16, 189, 12, 97, 13, 0, 192, 4, 65, 0, 0, 2, 12, 0, 16, 132, 49, 0, ++ 1, 0, 128, 0, 12, 1, 96, 0, 3, 1, 36, 32, 69, 13, 0, 16, 181, 133, 247, ++ 110, 253, 133, 247, 95, 253, 4, 72, 1, 104, 65, 240, 1, 1, 1, 96, 189, ++ 232, 16, 64, 133, 247, 17, 189, 4, 44, 32, 0, 3, 1, 184, 1, 64, 69, ++ 13, 0, 45, 233, 240, 65, 13, 70, 38, 73, 223, 248, 152, 192, 0, 35, ++ 137, 120, 28, 248, 3, 64, 161, 66, 3, 216, 92, 30, 6, 43, 4, 210, 6, ++ 224, 91, 28, 219, 178, 6, 43, 243, 211, 5, 35, 4, 36, 2, 224, 11, 185, ++ 1, 35, 0, 36, 28, 78, 5, 235, 133, 5, 128, 177, 27, 72, 195, 235, 3, ++ 23, 7, 68, 47, 68, 23, 68, 151, 248, 162, 112, 247, 96, 196, 235, 4, ++ 23, 56, 68, 40, 68, 16, 68, 144, 248, 162, 0, 17, 76, 252, 255, 89, ++ 123, 33, 0, 224, 20, 72, 3, 235, 131, 7, 0, 235, 199, 7, 47, 68, 23, ++ 68, 151, 248, 109, 113, 247, 96, 4, 235, 132, 7, 0, 235, 199, 0, 40, ++ 68, 16, 68, 144, 248, 109, 1, 176, 96, 28, 248, 3, 0, 112, 96, 28, 248, ++ 4, 0, 48, 96, 5, 72, 81, 247, 54, 253, 255, 40, 0, 217, 255, 32, 189, ++ 232, 240, 129, 189, 30, 32, 0, 16, 19, 32, 0, 44, 81, 32, 0, 235, 21, ++ 32, 0, 22, 19, 32, 0, 3, 1, 194, 4, 244, 69, 13, 0, 45, 233, 240, 79, ++ 135, 176, 0, 38, 4, 70, 5, 150, 144, 248, 210, 0, 252, 247, 122, 252, ++ 128, 70, 138, 247, 255, 250, 148, 248, 210, 112, 4, 169, 30, 55, 56, ++ 70, 95, 247, 252, 249, 223, 248, 188, 180, 5, 0, 10, 208, 4, 152, 0, ++ 235, 64, 1, 219, 248, 0, 0, 0, 235, 129, 0, 6, 96, 70, 96, 134, 96, ++ 3, 224, 4, 168, 95, 247, 214, 249, 240, 179, 8, 32, 141, 248, 10, 0, ++ 79, 240, 1, 10, 141, 248, 11, 160, 141, 248, 7, 112, 148, 248, 208, ++ 0, 173, 248, 0, 96, 141, 248, 8, 0, 173, 248, 2, 96, 95, 247, 209, 250, ++ 141, 248, 9, 0, 180, 248, 76, 0, 79, 240, 2, 9, 64, 28, 32, 240, 1, ++ 0, 128, 178, 173, 248, 4, 0, 2, 40, 1, 210, 173, 248, 4, 144, 180, 248, ++ 78, 0, 189, 248, 4, 16, 76, 252, 255, 84, 124, 33, 0, 64, 28, 32, 240, ++ 1, 0, 136, 66, 1, 217, 64, 26, 5, 144, 148, 248, 210, 0, 165, 247, 254, ++ 250, 5, 153, 111, 240, 1, 2, 8, 68, 5, 144, 180, 248, 72, 16, 2, 235, ++ 65, 2, 130, 66, 3, 216, 72, 0, 0, 224, 18, 224, 128, 30, 141, 248, 6, ++ 0, 148, 248, 209, 0, 176, 177, 0, 45, 126, 208, 180, 248, 200, 0, 173, ++ 248, 0, 0, 180, 248, 202, 0, 173, 248, 2, 0, 148, 248, 213, 0, 137, ++ 224, 0, 35, 107, 34, 64, 242, 161, 49, 251, 72, 112, 247, 244, 248, ++ 7, 176, 189, 232, 240, 143, 1, 39, 89, 247, 99, 255, 24, 177, 94, 247, ++ 60, 248, 0, 185, 0, 39, 180, 248, 68, 0, 64, 5, 5, 213, 184, 248, 0, ++ 0, 16, 177, 173, 248, 2, 0, 9, 224, 180, 248, 74, 0, 59, 70, 66, 0, ++ 180, 248, 72, 0, 65, 0, 104, 70, 95, 247, 66, 251, 189, 248, 2, 0, 1, ++ 40, 10, 217, 233, 73, 73, 104, 64, 30, 177, 251, 240, 242, 0, 251, 18, ++ 16, 32, 240, 1, 0, 173, 248, 0, 0, 148, 248, 210, 0, 5, 170, 105, 70, ++ 165, 247, 199, 250, 72, 187, 180, 248, 68, 0, 64, 5, 25, 213, 184, 248, ++ 0, 0, 176, 177, 74, 70, 33, 70, 104, 70, 205, 248, 12, 144, 95, 247, ++ 51, 252, 208, 185, 82, 70, 33, 70, 104, 70, 205, 248, 12, 160, 95, 247, ++ 43, 76, 252, 255, 79, 125, 33, 0, 252, 144, 185, 50, 70, 33, 70, 104, ++ 70, 3, 150, 95, 247, 36, 252, 88, 185, 3, 169, 104, 70, 95, 247, 234, ++ 250, 48, 185, 173, 248, 0, 96, 180, 248, 74, 0, 64, 0, 173, 248, 2, ++ 0, 189, 248, 0, 0, 93, 177, 164, 248, 200, 0, 189, 248, 2, 0, 164, 248, ++ 202, 0, 157, 248, 9, 0, 132, 248, 213, 0, 23, 224, 10, 224, 164, 248, ++ 196, 0, 189, 248, 2, 0, 164, 248, 198, 0, 157, 248, 9, 0, 132, 248, ++ 212, 0, 11, 224, 180, 248, 196, 0, 173, 248, 0, 0, 180, 248, 198, 0, ++ 173, 248, 2, 0, 148, 248, 212, 0, 141, 248, 9, 0, 4, 152, 219, 248, ++ 0, 16, 0, 235, 64, 2, 1, 235, 130, 0, 0, 154, 2, 96, 1, 154, 66, 96, ++ 2, 154, 130, 96, 0, 45, 127, 244, 107, 175, 4, 152, 0, 235, 64, 0, 1, ++ 235, 128, 0, 128, 121, 132, 248, 214, 0, 97, 231, 3, 1, 188, 2, 50, ++ 72, 13, 0, 45, 233, 240, 79, 5, 70, 144, 248, 210, 0, 139, 176, 138, ++ 70, 144, 70, 155, 70, 30, 48, 4, 169, 95, 247, 228, 248, 0, 40, 120, ++ 208, 138, 247, 220, 249, 4, 152, 0, 235, 64, 1, 160, 72, 0, 104, 0, ++ 235, 129, 1, 8, 104, 0, 144, 72, 104, 1, 144, 136, 104, 2, 144, 12, ++ 104, 6, 148, 72, 104, 7, 144, 136, 104, 8, 144, 0, 32, 8, 96, 76, 252, ++ 255, 74, 126, 33, 0, 72, 96, 136, 96, 5, 169, 104, 70, 95, 247, 94, ++ 254, 181, 248, 78, 32, 181, 248, 76, 16, 104, 70, 96, 247, 127, 249, ++ 2, 37, 79, 240, 0, 9, 32, 12, 79, 70, 9, 144, 186, 248, 2, 0, 9, 153, ++ 64, 4, 0, 12, 173, 248, 2, 0, 129, 66, 5, 209, 5, 152, 133, 66, 2, 210, ++ 79, 240, 0, 9, 64, 224, 0, 38, 184, 241, 0, 15, 1, 208, 0, 36, 30, 224, ++ 3, 169, 104, 70, 95, 247, 81, 250, 1, 40, 26, 209, 3, 152, 168, 66, ++ 23, 209, 79, 240, 1, 9, 41, 224, 11, 235, 132, 0, 189, 248, 2, 16, 0, ++ 104, 176, 251, 241, 242, 1, 251, 18, 0, 173, 248, 0, 0, 3, 169, 104, ++ 70, 95, 247, 33, 254, 3, 152, 168, 66, 234, 208, 100, 28, 68, 69, 234, ++ 211, 189, 248, 2, 0, 128, 30, 128, 178, 173, 248, 2, 0, 186, 248, 0, ++ 16, 176, 235, 65, 15, 2, 211, 118, 28, 12, 46, 203, 211, 127, 28, 109, ++ 30, 3, 47, 183, 211, 185, 241, 0, 15, 4, 208, 20, 152, 3, 153, 1, 96, ++ 3, 224, 16, 224, 20, 153, 0, 32, 8, 96, 4, 152, 0, 235, 64, 1, 98, 72, ++ 0, 104, 0, 235, 129, 0, 6, 153, 1, 96, 7, 153, 65, 96, 8, 153, 129, ++ 96, 72, 70, 11, 176, 198, 230, 3, 1, 214, 3, 106, 73, 13, 0, 112, 181, ++ 134, 176, 4, 70, 138, 76, 252, 255, 69, 127, 33, 0, 247, 76, 249, 0, ++ 37, 32, 104, 3, 169, 95, 247, 75, 248, 32, 177, 224, 105, 0, 4, 6, 213, ++ 1, 37, 4, 224, 3, 168, 95, 247, 46, 248, 0, 40, 122, 208, 84, 72, 0, ++ 120, 24, 177, 224, 105, 0, 4, 0, 213, 1, 37, 4, 32, 141, 248, 10, 0, ++ 1, 32, 141, 248, 11, 0, 32, 104, 141, 248, 7, 0, 32, 104, 111, 247, ++ 145, 249, 141, 248, 8, 0, 180, 248, 176, 0, 173, 248, 0, 0, 180, 248, ++ 178, 0, 173, 248, 2, 0, 148, 248, 180, 0, 141, 248, 9, 0, 33, 70, 104, ++ 70, 94, 247, 155, 253, 189, 248, 0, 16, 66, 78, 200, 7, 5, 209, 189, ++ 248, 2, 0, 128, 177, 128, 30, 129, 66, 8, 221, 79, 240, 0, 0, 0, 45, ++ 70, 209, 173, 248, 0, 0, 189, 248, 2, 0, 32, 177, 13, 185, 240, 120, ++ 232, 179, 1, 37, 128, 224, 55, 72, 0, 120, 40, 185, 180, 248, 170, 0, ++ 180, 248, 168, 80, 168, 66, 4, 209, 180, 248, 168, 0, 173, 248, 2, 0, ++ 44, 224, 48, 120, 56, 177, 224, 105, 0, 4, 4, 212, 173, 248, 2, 80, ++ 164, 248, 178, 80, 39, 224, 180, 248, 188, 0, 16, 177, 133, 66, 0, 217, ++ 5, 70, 112, 120, 136, 177, 224, 105, 0, 4, 14, 213, 240, 136, 133, 66, ++ 11, 217, 94, 247, 223, 253, 64, 66, 0, 235, 128, 0, 180, 248, 170, 16, ++ 5, 235, 76, 252, 255, 64, 128, 33, 0, 64, 0, 129, 66, 0, 210, 5, 70, ++ 180, 248, 170, 16, 1, 35, 42, 70, 104, 70, 95, 247, 155, 249, 189, 248, ++ 2, 0, 1, 224, 2, 224, 85, 224, 164, 248, 178, 0, 4, 169, 104, 70, 95, ++ 247, 112, 249, 5, 0, 77, 208, 176, 120, 2, 45, 3, 208, 208, 177, 1, ++ 45, 37, 208, 51, 224, 104, 177, 225, 105, 9, 4, 10, 212, 180, 248, 172, ++ 16, 129, 66, 6, 210, 180, 248, 178, 16, 242, 136, 145, 66, 1, 217, 164, ++ 248, 172, 0, 189, 248, 0, 0, 164, 248, 176, 0, 157, 248, 9, 0, 132, ++ 248, 180, 0, 27, 224, 26, 224, 80, 49, 32, 0, 7, 0, 2, 0, 0, 160, 50, ++ 0, 71, 49, 32, 0, 232, 11, 33, 0, 73, 49, 32, 0, 225, 105, 9, 4, 11, ++ 212, 180, 248, 172, 16, 129, 66, 7, 210, 180, 248, 178, 16, 242, 136, ++ 145, 66, 2, 217, 164, 248, 172, 0, 2, 37, 39, 73, 3, 152, 0, 34, 9, ++ 104, 0, 235, 64, 0, 1, 235, 128, 0, 0, 153, 1, 96, 1, 153, 65, 96, 2, ++ 153, 129, 96, 4, 33, 32, 70, 150, 247, 215, 248, 40, 70, 6, 176, 112, ++ 189, 3, 1, 30, 60, 75, 13, 0, 29, 74, 3, 70, 8, 70, 17, 121, 0, 41, ++ 5, 208, 129, 66, 3, 217, 210, 136, 154, 66, 0, 210, 8, 70, 112, 71, ++ 3, 1, 106, 86, 75, 13, 0, 16, 181, 4, 76, 252, 255, 59, 129, 33, 0, ++ 70, 16, 0, 1, 209, 180, 248, 170, 0, 21, 74, 18, 121, 0, 42, 33, 208, ++ 18, 74, 82, 121, 144, 66, 29, 211, 98, 107, 147, 7, 1, 213, 5, 35, 4, ++ 224, 210, 7, 1, 208, 3, 35, 0, 224, 1, 35, 180, 248, 102, 32, 20, 11, ++ 1, 208, 91, 29, 5, 224, 18, 244, 112, 111, 1, 208, 219, 28, 0, 224, ++ 91, 28, 131, 66, 0, 211, 131, 30, 138, 136, 154, 66, 0, 217, 19, 70, ++ 139, 128, 16, 189, 80, 49, 32, 0, 232, 11, 33, 0, 212, 29, 32, 0, 3, ++ 1, 148, 3, 188, 75, 13, 0, 45, 233, 248, 79, 0, 36, 38, 70, 79, 240, ++ 1, 9, 129, 247, 84, 254, 5, 70, 76, 247, 123, 253, 90, 79, 56, 104, ++ 0, 240, 224, 1, 89, 72, 2, 120, 2, 240, 31, 2, 17, 67, 57, 96, 57, 31, ++ 10, 104, 67, 120, 2, 240, 224, 2, 3, 240, 31, 3, 26, 67, 10, 96, 58, ++ 29, 19, 104, 144, 248, 2, 192, 3, 240, 224, 3, 12, 240, 31, 12, 67, ++ 234, 12, 3, 19, 96, 77, 74, 19, 104, 144, 248, 3, 192, 3, 240, 224, ++ 3, 12, 240, 31, 12, 67, 234, 12, 3, 19, 96, 223, 248, 28, 161, 10, 241, ++ 8, 10, 218, 248, 0, 192, 0, 121, 12, 240, 224, 12, 0, 240, 31, 0, 76, ++ 234, 0, 12, 202, 248, 0, 192, 56, 104, 223, 248, 244, 192, 0, 240, 31, ++ 0, 76, 252, 255, 54, 130, 33, 0, 12, 241, 84, 12, 12, 241, 4, 8, 3, ++ 40, 3, 211, 128, 30, 204, 248, 0, 0, 4, 224, 0, 35, 204, 248, 0, 48, ++ 24, 177, 64, 30, 200, 248, 0, 0, 1, 224, 200, 248, 0, 48, 237, 179, ++ 4, 45, 73, 208, 16, 104, 0, 240, 31, 0, 8, 48, 218, 248, 0, 32, 96, ++ 243, 4, 2, 202, 248, 0, 32, 45, 75, 64, 51, 26, 104, 0, 240, 16, 0, ++ 34, 240, 16, 2, 2, 67, 26, 96, 69, 179, 3, 45, 55, 208, 8, 104, 4, 45, ++ 0, 208, 128, 30, 56, 96, 48, 247, 208, 251, 0, 40, 62, 208, 106, 70, ++ 2, 33, 110, 32, 48, 247, 155, 251, 189, 248, 0, 0, 193, 178, 65, 234, ++ 16, 32, 1, 6, 1, 213, 79, 240, 255, 57, 0, 240, 127, 0, 0, 251, 9, 240, ++ 64, 178, 0, 40, 41, 208, 25, 74, 2, 235, 132, 1, 145, 249, 0, 48, 131, ++ 66, 26, 220, 1, 224, 12, 224, 15, 224, 145, 249, 1, 16, 129, 66, 19, ++ 221, 109, 177, 4, 45, 11, 208, 2, 235, 132, 0, 144, 249, 2, 96, 15, ++ 224, 16, 104, 0, 240, 31, 0, 181, 231, 8, 104, 64, 30, 200, 231, 2, ++ 235, 132, 0, 144, 249, 3, 96, 3, 224, 100, 28, 228, 178, 9, 44, 218, ++ 211, 56, 104, 48, 68, 192, 178, 56, 96, 189, 232, 248, 143, 0, 0, 16, ++ 4, 96, 0, 156, 7, 32, 0, 0, 7, 96, 76, 252, 255, 49, 131, 33, 0, 0, ++ 240, 11, 33, 0, 3, 1, 26, 76, 77, 13, 0, 52, 72, 1, 104, 52, 72, 1, ++ 96, 52, 73, 9, 104, 65, 96, 52, 73, 73, 104, 129, 96, 112, 71, 3, 1, ++ 26, 98, 77, 13, 0, 51, 72, 1, 104, 47, 72, 1, 96, 50, 73, 9, 104, 65, ++ 96, 46, 73, 9, 104, 129, 96, 112, 71, 3, 1, 132, 1, 120, 77, 13, 0, ++ 112, 181, 47, 72, 6, 38, 0, 37, 128, 104, 46, 76, 1, 124, 34, 41, 46, ++ 208, 8, 220, 1, 41, 16, 208, 6, 41, 25, 208, 16, 41, 37, 208, 33, 41, ++ 6, 209, 39, 224, 40, 41, 23, 208, 42, 41, 27, 208, 43, 41, 28, 208, ++ 37, 96, 189, 232, 112, 64, 215, 231, 144, 248, 169, 0, 28, 224, 255, ++ 247, 200, 255, 38, 96, 112, 189, 255, 247, 207, 255, 37, 96, 112, 189, ++ 144, 248, 57, 0, 3, 40, 247, 209, 242, 231, 64, 143, 67, 242, 6, 49, ++ 8, 66, 241, 208, 236, 231, 144, 248, 96, 0, 6, 224, 64, 106, 228, 231, ++ 144, 248, 101, 0, 1, 224, 144, 248, 89, 0, 1, 40, 228, 209, 223, 231, ++ 3, 1, 22, 248, 77, 13, 0, 16, 181, 133, 247, 113, 249, 81, 247, 175, ++ 248, 189, 232, 16, 64, 71, 247, 171, 186, 3, 1, 62, 10, 78, 13, 0, 16, ++ 181, 12, 76, 32, 120, 16, 177, 1, 32, 71, 247, 77, 252, 0, 32, 32, 112, ++ 16, 189, 76, 252, 255, 44, 132, 33, 0, 0, 0, 12, 8, 32, 0, 104, 1, 96, ++ 0, 20, 8, 32, 0, 20, 12, 33, 0, 8, 8, 32, 0, 16, 8, 32, 0, 0, 63, 32, ++ 0, 100, 8, 100, 0, 16, 97, 13, 0, 3, 1, 22, 68, 78, 13, 0, 16, 181, ++ 200, 74, 200, 73, 201, 72, 80, 247, 110, 255, 200, 73, 8, 112, 16, 189, ++ 3, 1, 22, 86, 78, 13, 0, 197, 73, 199, 72, 220, 57, 200, 96, 199, 73, ++ 0, 245, 152, 96, 8, 96, 112, 71, 3, 1, 44, 104, 78, 13, 0, 197, 74, ++ 198, 75, 1, 40, 3, 208, 2, 40, 9, 209, 24, 136, 6, 224, 16, 104, 24, ++ 128, 72, 120, 1, 40, 3, 208, 67, 246, 2, 16, 16, 96, 112, 71, 67, 246, ++ 14, 16, 250, 231, 3, 1, 72, 144, 78, 13, 0, 16, 181, 187, 74, 188, 76, ++ 8, 50, 64, 246, 162, 99, 1, 40, 3, 208, 2, 40, 18, 209, 32, 136, 15, ++ 224, 16, 104, 128, 178, 32, 128, 73, 120, 1, 41, 11, 208, 173, 73, 220, ++ 57, 201, 136, 193, 245, 128, 81, 137, 178, 97, 243, 31, 16, 64, 240, ++ 8, 0, 16, 96, 16, 189, 16, 104, 99, 243, 31, 16, 247, 231, 3, 1, 112, ++ 212, 78, 13, 0, 112, 181, 164, 74, 164, 75, 169, 76, 18, 120, 220, 59, ++ 2, 235, 130, 2, 3, 235, 194, 2, 168, 77, 82, 125, 148, 60, 168, 78, ++ 79, 244, 192, 3, 1, 40, 76, 252, 255, 39, 133, 33, 0, 9, 208, 2, 40, ++ 6, 209, 72, 120, 1, 40, 26, 208, 48, 136, 32, 96, 1, 32, 88, 96, 112, ++ 189, 32, 104, 128, 178, 48, 128, 211, 248, 4, 97, 46, 96, 73, 120, 1, ++ 41, 9, 208, 72, 242, 255, 1, 8, 64, 2, 240, 127, 1, 64, 234, 1, 32, ++ 32, 96, 0, 32, 88, 96, 195, 248, 4, 33, 112, 189, 40, 104, 195, 248, ++ 4, 1, 112, 189, 3, 1, 60, 64, 79, 13, 0, 16, 181, 148, 73, 148, 75, ++ 149, 74, 149, 76, 1, 40, 6, 208, 2, 40, 3, 209, 24, 104, 8, 96, 32, ++ 104, 16, 96, 16, 189, 8, 104, 24, 96, 16, 104, 32, 96, 8, 104, 32, 240, ++ 63, 0, 64, 240, 72, 0, 8, 96, 16, 104, 32, 240, 2, 0, 239, 231, 3, 1, ++ 36, 120, 79, 13, 0, 138, 74, 79, 244, 192, 1, 1, 40, 4, 208, 2, 40, ++ 1, 209, 16, 104, 136, 97, 112, 71, 136, 105, 16, 96, 136, 105, 32, 240, ++ 2, 0, 247, 231, 3, 1, 70, 152, 79, 13, 0, 79, 244, 192, 2, 1, 40, 6, ++ 208, 2, 40, 20, 209, 210, 248, 252, 2, 32, 240, 12, 0, 13, 224, 72, ++ 120, 1, 40, 13, 208, 0, 40, 10, 209, 136, 120, 1, 40, 8, 208, 210, 248, ++ 252, 2, 32, 240, 12, 0, 64, 240, 8, 0, 194, 248, 252, 2, 112, 71, 210, ++ 248, 252, 2, 64, 240, 12, 0, 247, 231, 3, 1, 76, 252, 255, 34, 134, ++ 33, 0, 48, 218, 79, 13, 0, 105, 74, 114, 75, 24, 50, 1, 40, 3, 208, ++ 2, 40, 10, 209, 24, 104, 7, 224, 16, 104, 24, 96, 72, 120, 1, 40, 16, ++ 104, 3, 208, 64, 244, 128, 64, 16, 96, 112, 71, 32, 244, 128, 64, 250, ++ 231, 3, 1, 48, 6, 80, 13, 0, 105, 75, 105, 74, 1, 40, 3, 208, 2, 40, ++ 10, 209, 24, 104, 7, 224, 16, 104, 24, 96, 72, 120, 1, 40, 16, 104, ++ 3, 208, 64, 244, 128, 96, 16, 96, 112, 71, 79, 246, 255, 49, 8, 64, ++ 249, 231, 3, 1, 36, 50, 80, 13, 0, 90, 73, 95, 74, 28, 57, 1, 40, 4, ++ 208, 2, 40, 1, 209, 16, 104, 8, 96, 112, 71, 8, 104, 16, 96, 8, 104, ++ 0, 240, 3, 0, 247, 231, 3, 1, 152, 1, 82, 80, 13, 0, 45, 233, 240, 65, ++ 88, 79, 85, 78, 1, 40, 24, 208, 2, 40, 20, 209, 48, 104, 57, 104, 32, ++ 244, 0, 112, 33, 244, 0, 81, 64, 244, 128, 116, 65, 244, 128, 69, 52, ++ 96, 61, 96, 50, 32, 111, 247, 187, 255, 36, 244, 128, 112, 37, 244, ++ 128, 65, 48, 96, 57, 96, 189, 232, 240, 129, 72, 120, 1, 40, 22, 208, ++ 48, 104, 57, 104, 32, 244, 0, 112, 64, 244, 128, 112, 33, 244, 0, 81, ++ 65, 244, 128, 65, 48, 96, 57, 96, 64, 244, 0, 112, 65, 244, 0, 81, 48, ++ 96, 57, 96, 76, 252, 255, 29, 135, 33, 0, 189, 232, 240, 65, 200, 32, ++ 111, 247, 153, 191, 79, 244, 128, 64, 56, 96, 48, 104, 79, 246, 255, ++ 65, 8, 64, 48, 96, 79, 244, 192, 64, 56, 96, 48, 104, 128, 178, 64, ++ 244, 64, 112, 48, 96, 210, 231, 3, 1, 92, 230, 80, 13, 0, 48, 181, 37, ++ 74, 37, 75, 51, 77, 52, 76, 124, 58, 96, 51, 1, 40, 9, 208, 2, 40, 6, ++ 209, 72, 120, 1, 40, 3, 209, 40, 104, 16, 96, 32, 104, 24, 96, 48, 189, ++ 16, 104, 40, 96, 24, 104, 32, 96, 72, 120, 1, 40, 247, 209, 19, 72, ++ 19, 76, 201, 120, 0, 120, 220, 60, 0, 235, 128, 0, 4, 235, 192, 0, 41, ++ 177, 1, 41, 3, 208, 128, 140, 16, 96, 0, 32, 230, 231, 192, 138, 250, ++ 231, 3, 1, 142, 1, 62, 81, 13, 0, 30, 74, 32, 75, 116, 58, 1, 40, 3, ++ 208, 2, 40, 9, 209, 24, 136, 6, 224, 16, 104, 24, 128, 72, 120, 1, 40, ++ 3, 208, 79, 244, 0, 96, 16, 96, 112, 71, 37, 32, 251, 231, 0, 0, 160, ++ 30, 32, 0, 44, 17, 32, 0, 196, 99, 13, 0, 180, 43, 32, 0, 20, 97, 13, ++ 0, 188, 43, 32, 0, 172, 6, 65, 0, 40, 16, 32, 0, 38, 16, 32, 0, 44, ++ 16, 32, 0, 36, 16, 32, 0, 220, 4, 96, 0, 68, 16, 32, 0, 100, 6, 96, ++ 0, 72, 16, 32, 0, 48, 16, 76, 252, 255, 24, 136, 33, 0, 32, 0, 52, 16, ++ 32, 0, 56, 16, 32, 0, 232, 7, 65, 0, 76, 16, 32, 0, 252, 4, 65, 0, 60, ++ 16, 32, 0, 64, 16, 32, 0, 42, 16, 32, 0, 3, 1, 184, 1, 200, 81, 13, ++ 0, 2, 70, 48, 180, 0, 32, 17, 42, 82, 210, 223, 232, 2, 240, 9, 74, ++ 71, 62, 59, 41, 12, 69, 15, 69, 71, 59, 74, 74, 41, 41, 78, 0, 48, 188, ++ 88, 247, 118, 184, 48, 188, 87, 247, 169, 191, 59, 74, 19, 104, 111, ++ 243, 15, 3, 66, 248, 144, 57, 57, 76, 58, 75, 5, 41, 15, 210, 223, 232, ++ 1, 240, 16, 3, 16, 22, 16, 0, 2, 241, 124, 2, 81, 105, 72, 246, 136, ++ 3, 65, 234, 3, 1, 81, 97, 79, 240, 187, 49, 17, 96, 48, 188, 112, 71, ++ 25, 104, 9, 177, 209, 103, 249, 231, 97, 104, 251, 231, 82, 248, 124, ++ 31, 25, 96, 161, 104, 17, 96, 81, 105, 99, 136, 25, 67, 81, 97, 237, ++ 231, 48, 188, 87, 247, 140, 191, 17, 177, 48, 188, 87, 247, 188, 191, ++ 48, 188, 87, 247, 217, 191, 2, 32, 225, 231, 48, 188, 87, 247, 141, ++ 191, 48, 188, 8, 70, 87, 247, 240, 191, 48, 188, 87, 247, 159, 191, ++ 1, 32, 213, 231, 3, 1, 124, 124, 82, 13, 0, 28, 73, 69, 32, 8, 96, 25, ++ 72, 1, 120, 79, 244, 72, 16, 169, 177, 0, 241, 144, 0, 208, 248, 76, ++ 252, 255, 19, 137, 33, 0, 164, 16, 33, 244, 124, 81, 65, 244, 248, 81, ++ 192, 248, 164, 16, 1, 104, 33, 244, 112, 33, 65, 244, 0, 33, 1, 96, ++ 65, 109, 33, 240, 1, 1, 65, 101, 160, 241, 144, 0, 0, 241, 144, 0, 208, ++ 248, 164, 16, 33, 240, 63, 1, 65, 240, 31, 1, 192, 248, 164, 16, 1, ++ 104, 33, 240, 112, 97, 65, 240, 0, 97, 1, 96, 65, 109, 33, 244, 128, ++ 49, 65, 101, 112, 71, 0, 0, 144, 0, 50, 0, 28, 12, 33, 0, 244, 101, ++ 13, 0, 0, 132, 49, 0, 3, 1, 168, 2, 244, 82, 13, 0, 45, 233, 240, 65, ++ 3, 0, 2, 208, 60, 76, 6, 34, 2, 224, 59, 76, 40, 60, 20, 34, 148, 249, ++ 0, 0, 0, 37, 136, 66, 29, 221, 43, 185, 148, 249, 10, 0, 136, 66, 1, ++ 219, 5, 37, 22, 224, 4, 235, 66, 0, 16, 249, 2, 12, 136, 66, 2, 219, ++ 82, 30, 213, 178, 13, 224, 1, 32, 9, 224, 4, 235, 64, 6, 150, 249, 0, ++ 96, 142, 66, 1, 220, 5, 70, 3, 224, 64, 28, 192, 178, 144, 66, 243, ++ 211, 4, 235, 69, 0, 144, 249, 0, 112, 27, 177, 38, 73, 64, 120, 8, 96, ++ 60, 224, 37, 73, 38, 78, 137, 121, 143, 66, 1, 221, 1, 32, 0, 224, 0, ++ 32, 112, 112, 129, 247, 127, 250, 48, 112, 8, 32, 240, 112, 223, 248, ++ 112, 192, 176, 112, 0, 32, 12, 76, 252, 255, 14, 138, 33, 0, 241, 12, ++ 12, 5, 235, 64, 1, 4, 235, 65, 3, 6, 235, 64, 1, 26, 120, 10, 117, 10, ++ 113, 72, 117, 72, 113, 92, 248, 32, 32, 89, 120, 17, 96, 1, 40, 4, 208, ++ 2, 40, 9, 208, 3, 40, 14, 209, 21, 224, 220, 248, 4, 16, 9, 104, 17, ++ 74, 17, 96, 17, 74, 5, 224, 220, 248, 8, 16, 9, 104, 15, 74, 17, 96, ++ 15, 74, 17, 96, 64, 28, 177, 120, 192, 178, 129, 66, 214, 216, 56, 70, ++ 189, 232, 240, 129, 220, 248, 12, 16, 9, 104, 10, 74, 17, 96, 10, 74, ++ 239, 231, 0, 0, 32, 102, 13, 0, 156, 1, 96, 0, 75, 30, 32, 0, 148, 23, ++ 32, 0, 12, 8, 32, 0, 8, 8, 32, 0, 20, 8, 32, 0, 16, 8, 32, 0, 24, 12, ++ 33, 0, 20, 12, 33, 0, 3, 1, 48, 24, 84, 13, 0, 112, 181, 193, 23, 0, ++ 235, 209, 97, 76, 17, 33, 240, 31, 1, 69, 26, 112, 247, 23, 248, 79, ++ 240, 224, 34, 1, 33, 2, 235, 132, 2, 169, 64, 194, 248, 128, 17, 189, ++ 232, 112, 64, 112, 247, 15, 184, 3, 1, 94, 68, 84, 13, 0, 100, 75, 48, ++ 181, 24, 68, 131, 7, 10, 213, 80, 248, 2, 60, 137, 30, 27, 12, 128, ++ 28, 19, 112, 27, 10, 83, 112, 137, 178, 2, 241, 2, 2, 79, 234, 145, ++ 4, 13, 224, 80, 248, 4, 59, 19, 112, 79, 234, 76, 252, 255, 9, 139, ++ 33, 0, 19, 37, 85, 112, 79, 234, 19, 69, 149, 112, 79, 234, 19, 99, ++ 211, 112, 2, 241, 4, 2, 35, 0, 164, 241, 1, 4, 164, 178, 236, 209, 137, ++ 7, 3, 213, 0, 104, 16, 112, 0, 10, 80, 112, 48, 189, 3, 1, 126, 158, ++ 84, 13, 0, 14, 181, 78, 72, 0, 120, 1, 40, 54, 209, 77, 72, 0, 104, ++ 77, 73, 0, 240, 4, 0, 9, 120, 8, 67, 46, 209, 47, 247, 204, 255, 0, ++ 40, 42, 208, 106, 70, 10, 33, 0, 32, 255, 247, 189, 255, 157, 248, 0, ++ 0, 80, 40, 33, 209, 157, 248, 1, 0, 79, 40, 29, 209, 157, 248, 2, 0, ++ 0, 40, 25, 208, 157, 248, 3, 0, 0, 40, 21, 208, 157, 248, 4, 0, 120, ++ 185, 157, 248, 5, 0, 96, 185, 157, 248, 6, 0, 72, 185, 157, 248, 7, ++ 0, 48, 185, 157, 248, 8, 0, 24, 185, 157, 248, 9, 0, 0, 40, 2, 208, ++ 1, 168, 109, 247, 139, 255, 14, 189, 3, 1, 88, 24, 85, 13, 0, 16, 181, ++ 4, 40, 36, 209, 51, 73, 49, 72, 8, 96, 51, 73, 50, 72, 8, 96, 52, 73, ++ 50, 72, 8, 96, 15, 32, 255, 247, 113, 255, 51, 73, 49, 72, 8, 96, 50, ++ 73, 79, 240, 255, 48, 136, 96, 50, 73, 49, 72, 72, 96, 255, 247, 168, ++ 255, 251, 247, 113, 254, 48, 73, 8, 96, 33, 72, 64, 120, 40, 177, 46, ++ 73, 1, 76, 252, 255, 4, 140, 33, 0, 32, 136, 96, 21, 32, 166, 247, 247, ++ 255, 0, 32, 16, 189, 3, 1, 12, 108, 85, 13, 0, 4, 33, 8, 32, 87, 247, ++ 8, 191, 3, 1, 12, 116, 85, 13, 0, 3, 33, 8, 32, 87, 247, 4, 191, 3, ++ 1, 208, 1, 124, 85, 13, 0, 16, 181, 175, 242, 103, 0, 38, 73, 8, 96, ++ 255, 247, 102, 252, 37, 73, 29, 32, 72, 112, 175, 242, 31, 1, 35, 72, ++ 65, 96, 175, 242, 47, 1, 129, 96, 70, 247, 3, 250, 34, 73, 32, 72, 80, ++ 34, 8, 96, 34, 73, 32, 72, 48, 35, 8, 96, 34, 72, 32, 73, 193, 103, ++ 33, 73, 129, 103, 33, 72, 12, 33, 65, 128, 2, 113, 5, 33, 65, 113, 195, ++ 128, 2, 114, 65, 114, 37, 33, 1, 115, 3, 33, 65, 115, 16, 189, 126, ++ 17, 101, 0, 40, 12, 33, 0, 128, 1, 50, 0, 78, 5, 32, 0, 197, 87, 13, ++ 0, 136, 35, 32, 0, 77, 88, 13, 0, 196, 35, 32, 0, 81, 88, 13, 0, 252, ++ 37, 32, 0, 81, 86, 13, 0, 84, 50, 32, 0, 16, 130, 32, 0, 121, 54, 13, ++ 0, 228, 92, 32, 0, 136, 50, 32, 0, 0, 144, 50, 0, 180, 57, 32, 0, 179, ++ 50, 32, 0, 188, 120, 13, 0, 101, 65, 13, 0, 188, 48, 32, 0, 163, 63, ++ 13, 0, 192, 48, 32, 0, 69, 66, 13, 0, 24, 82, 32, 0, 177, 65, 13, 0, ++ 76, 252, 255, 255, 140, 33, 0, 156, 24, 32, 0, 3, 1, 12, 72, 86, 13, ++ 0, 91, 73, 0, 123, 8, 112, 112, 71, 3, 1, 248, 2, 80, 86, 13, 0, 240, ++ 180, 0, 36, 89, 78, 12, 96, 166, 241, 128, 4, 5, 43, 113, 208, 6, 220, ++ 1, 43, 11, 208, 2, 43, 108, 208, 3, 43, 106, 209, 19, 224, 6, 43, 103, ++ 208, 8, 43, 28, 208, 63, 43, 99, 209, 63, 224, 9, 42, 2, 208, 15, 42, ++ 94, 209, 3, 224, 52, 104, 12, 96, 116, 104, 137, 224, 180, 104, 12, ++ 96, 244, 104, 133, 224, 3, 42, 2, 208, 63, 42, 81, 209, 3, 224, 37, ++ 104, 13, 96, 100, 104, 124, 224, 165, 108, 13, 96, 228, 108, 120, 224, ++ 18, 42, 23, 208, 6, 220, 13, 42, 24, 208, 14, 42, 26, 208, 16, 42, 115, ++ 209, 11, 224, 23, 42, 5, 208, 28, 42, 110, 209, 165, 106, 13, 96, 228, ++ 106, 102, 224, 165, 107, 13, 96, 228, 107, 98, 224, 165, 110, 13, 96, ++ 228, 110, 94, 224, 37, 111, 13, 96, 100, 111, 90, 224, 52, 105, 12, ++ 96, 116, 105, 86, 224, 180, 105, 12, 96, 244, 105, 82, 224, 64, 242, ++ 63, 23, 162, 242, 63, 21, 186, 66, 65, 208, 14, 220, 36, 42, 34, 208, ++ 6, 220, 20, 42, 39, 208, 25, 42, 21, 208, 26, 42, 70, 209, 22, 224, ++ 37, 42, 28, 208, 133, 42, 65, 209, 33, 224, 20, 45, 35, 208, 4, 220, ++ 76, 252, 255, 250, 141, 33, 0, 1, 45, 48, 208, 2, 45, 57, 209, 45, 224, ++ 24, 45, 31, 208, 138, 45, 52, 209, 44, 224, 50, 224, 165, 104, 13, 96, ++ 228, 104, 42, 224, 37, 105, 13, 96, 100, 105, 38, 224, 165, 105, 13, ++ 96, 228, 105, 34, 224, 37, 106, 13, 96, 100, 106, 30, 224, 37, 107, ++ 13, 96, 100, 107, 26, 224, 37, 108, 13, 96, 100, 108, 22, 224, 165, ++ 109, 13, 96, 228, 109, 18, 224, 16, 77, 45, 120, 1, 45, 18, 209, 37, ++ 109, 13, 96, 100, 109, 10, 224, 165, 111, 13, 96, 228, 111, 6, 224, ++ 37, 110, 13, 96, 100, 110, 2, 224, 52, 106, 12, 96, 116, 106, 76, 96, ++ 12, 104, 0, 44, 2, 209, 240, 188, 70, 247, 57, 188, 240, 188, 112, 71, ++ 0, 0, 44, 12, 33, 0, 204, 102, 13, 0, 217, 11, 33, 0, 3, 1, 140, 1, ++ 196, 87, 13, 0, 112, 181, 4, 70, 1, 41, 2, 208, 2, 41, 47, 208, 48, ++ 224, 164, 245, 224, 64, 10, 56, 33, 209, 23, 72, 129, 247, 167, 249, ++ 4, 70, 22, 77, 22, 78, 14, 224, 20, 73, 19, 72, 129, 247, 234, 248, ++ 41, 136, 11, 41, 2, 209, 40, 121, 2, 40, 8, 208, 6, 235, 129, 0, 1, ++ 104, 14, 72, 136, 71, 100, 30, 238, 210, 0, 36, 18, 224, 11, 72, 157, ++ 247, 70, 250, 11, 73, 16, 32, 251, 247, 132, 250, 243, 231, 164, 245, ++ 224, 64, 6, 76, 252, 255, 245, 142, 33, 0, 56, 6, 208, 14, 56, 4, 209, ++ 7, 73, 8, 112, 236, 231, 137, 247, 188, 250, 32, 70, 112, 189, 12, 96, ++ 32, 0, 164, 35, 32, 0, 60, 146, 8, 0, 92, 239, 32, 0, 76, 94, 13, 0, ++ 3, 1, 8, 76, 88, 13, 0, 0, 32, 112, 71, 3, 1, 28, 80, 88, 13, 0, 8, ++ 123, 66, 8, 0, 32, 127, 42, 3, 208, 7, 42, 1, 209, 1, 74, 138, 96, 112, ++ 71, 29, 52, 13, 0, 3, 1, 80, 104, 88, 13, 0, 240, 181, 17, 73, 15, 72, ++ 15, 78, 72, 97, 0, 32, 54, 29, 1, 39, 86, 248, 48, 48, 90, 9, 3, 240, ++ 31, 5, 81, 248, 34, 64, 7, 250, 5, 243, 28, 67, 65, 248, 34, 64, 6, ++ 235, 192, 2, 75, 105, 82, 104, 3, 235, 64, 3, 66, 240, 1, 2, 194, 245, ++ 88, 34, 26, 128, 64, 28, 230, 208, 240, 189, 244, 102, 13, 0, 108, 159, ++ 32, 0, 3, 1, 128, 1, 180, 88, 13, 0, 45, 233, 240, 65, 26, 72, 0, 104, ++ 192, 7, 46, 208, 25, 72, 1, 104, 65, 240, 1, 1, 1, 96, 23, 79, 124, ++ 63, 56, 104, 64, 240, 128, 0, 56, 96, 21, 78, 1, 32, 48, 96, 69, 247, ++ 78, 251, 61, 104, 37, 240, 128, 0, 56, 96, 15, 72, 116, 56, 1, 104, ++ 65, 240, 32, 1, 1, 96, 1, 104, 33, 240, 32, 1, 1, 96, 0, 36, 4, 224, ++ 48, 76, 252, 255, 240, 143, 33, 0, 32, 69, 247, 167, 250, 4, 241, 1, ++ 4, 48, 104, 128, 7, 1, 212, 50, 44, 245, 211, 69, 240, 128, 0, 56, 96, ++ 0, 32, 48, 96, 189, 232, 240, 129, 0, 0, 96, 24, 32, 0, 124, 8, 100, ++ 0, 180, 4, 50, 0, 3, 1, 136, 1, 48, 89, 13, 0, 48, 181, 27, 76, 36, ++ 120, 1, 44, 7, 209, 176, 245, 225, 63, 7, 208, 24, 76, 37, 104, 69, ++ 240, 1, 5, 37, 96, 23, 76, 160, 66, 1, 216, 22, 76, 0, 224, 22, 76, ++ 180, 251, 240, 240, 16, 40, 12, 219, 196, 23, 0, 235, 20, 116, 37, 17, ++ 36, 240, 15, 4, 4, 27, 24, 104, 32, 240, 8, 0, 64, 240, 128, 0, 6, 224, ++ 5, 70, 24, 104, 0, 36, 32, 240, 128, 0, 64, 240, 8, 0, 24, 96, 197, ++ 245, 128, 112, 16, 96, 4, 235, 212, 112, 64, 16, 34, 26, 66, 234, 0, ++ 16, 8, 96, 48, 189, 0, 0, 42, 12, 33, 0, 28, 4, 54, 0, 96, 227, 22, ++ 0, 0, 54, 110, 1, 0, 108, 220, 2, 3, 1, 50, 180, 89, 13, 0, 112, 181, ++ 4, 70, 0, 37, 111, 247, 78, 253, 6, 70, 32, 70, 111, 247, 34, 254, 4, ++ 0, 6, 208, 1, 33, 111, 247, 5, 254, 5, 70, 32, 70, 111, 247, 251, 253, ++ 48, 70, 111, 247, 66, 253, 40, 70, 112, 189, 3, 1, 62, 226, 89, 13, ++ 0, 112, 181, 4, 70, 76, 252, 255, 235, 144, 33, 0, 0, 37, 111, 247, ++ 55, 253, 6, 70, 32, 70, 111, 247, 11, 254, 4, 0, 7, 208, 0, 33, 111, ++ 247, 238, 253, 5, 70, 32, 70, 111, 247, 228, 253, 4, 224, 203, 33, 79, ++ 244, 0, 112, 111, 247, 204, 248, 48, 70, 111, 247, 37, 253, 40, 70, ++ 112, 189, 3, 1, 62, 28, 90, 13, 0, 112, 181, 5, 0, 22, 72, 4, 104, 22, ++ 208, 12, 224, 41, 70, 32, 70, 111, 247, 178, 254, 48, 177, 68, 177, ++ 41, 70, 32, 70, 189, 232, 112, 64, 111, 247, 135, 190, 36, 104, 0, 44, ++ 240, 209, 189, 232, 112, 64, 254, 33, 79, 244, 0, 112, 111, 247, 171, ++ 184, 112, 189, 3, 1, 50, 86, 90, 13, 0, 112, 181, 9, 77, 1, 70, 1, 36, ++ 40, 120, 80, 177, 8, 70, 111, 247, 209, 253, 40, 177, 1, 124, 64, 124, ++ 42, 120, 80, 67, 129, 66, 0, 210, 0, 36, 32, 70, 112, 189, 132, 5, 32, ++ 0, 43, 12, 33, 0, 3, 1, 40, 132, 90, 13, 0, 6, 73, 0, 32, 9, 104, 201, ++ 6, 6, 213, 5, 72, 1, 104, 33, 244, 112, 49, 1, 96, 79, 244, 112, 32, ++ 112, 71, 0, 0, 0, 103, 13, 0, 88, 30, 32, 0, 3, 1, 60, 168, 90, 13, ++ 0, 112, 181, 5, 70, 12, 70, 128, 106, 8, 33, 1, 235, 128, 0, 111, 247, ++ 193, 253, 0, 40, 15, 208, 170, 106, 0, 241, 8, 1, 2, 76, 252, 255, 230, ++ 145, 33, 0, 42, 3, 209, 84, 248, 4, 43, 65, 248, 4, 43, 34, 104, 10, ++ 96, 1, 70, 40, 70, 125, 247, 119, 249, 1, 32, 112, 189, 3, 1, 112, 224, ++ 90, 13, 0, 112, 181, 22, 76, 160, 120, 0, 40, 38, 208, 111, 247, 161, ++ 250, 1, 70, 19, 72, 0, 104, 45, 247, 180, 249, 161, 120, 64, 246, 53, ++ 66, 81, 67, 192, 235, 129, 4, 111, 247, 169, 252, 14, 77, 6, 70, 40, ++ 120, 192, 6, 13, 213, 0, 44, 11, 220, 45, 247, 232, 249, 32, 185, 10, ++ 72, 1, 104, 33, 240, 32, 1, 1, 96, 40, 120, 32, 240, 16, 0, 40, 112, ++ 48, 70, 189, 232, 112, 64, 111, 247, 149, 188, 112, 189, 0, 0, 196, ++ 24, 32, 0, 4, 103, 13, 0, 22, 29, 32, 0, 32, 4, 54, 0, 3, 1, 88, 76, ++ 91, 13, 0, 208, 248, 216, 32, 4, 70, 0, 33, 144, 71, 66, 78, 223, 248, ++ 8, 129, 223, 248, 8, 145, 4, 241, 176, 10, 80, 70, 125, 247, 146, 249, ++ 5, 70, 112, 121, 136, 177, 176, 120, 120, 177, 111, 247, 113, 252, 152, ++ 248, 0, 16, 7, 70, 65, 240, 16, 1, 136, 248, 0, 16, 111, 247, 83, 250, ++ 201, 248, 0, 0, 56, 70, 111, 247, 103, 252, 212, 248, 216, 32, 41, 70, ++ 32, 70, 144, 71, 225, 231, 3, 1, 24, 160, 91, 13, 0, 47, 72, 16, 181, ++ 64, 121, 24, 177, 45, 247, 159, 76, 252, 255, 225, 146, 33, 0, 249, ++ 0, 40, 0, 208, 1, 32, 16, 189, 3, 1, 192, 1, 180, 91, 13, 0, 45, 233, ++ 240, 65, 223, 248, 176, 128, 14, 70, 152, 248, 0, 0, 224, 179, 230, ++ 179, 192, 7, 61, 208, 113, 104, 6, 241, 8, 0, 161, 245, 224, 66, 132, ++ 58, 15, 209, 69, 136, 4, 70, 5, 241, 9, 0, 111, 247, 44, 253, 7, 70, ++ 42, 70, 33, 29, 9, 48, 111, 247, 26, 254, 60, 70, 71, 242, 63, 0, 29, ++ 224, 161, 245, 224, 66, 65, 58, 34, 209, 5, 70, 253, 247, 22, 253, 7, ++ 0, 29, 208, 40, 120, 19, 40, 26, 208, 104, 120, 0, 29, 63, 247, 175, ++ 250, 105, 120, 160, 241, 8, 4, 137, 28, 65, 128, 32, 248, 4, 123, 106, ++ 120, 41, 70, 146, 28, 111, 247, 250, 253, 71, 242, 130, 0, 96, 96, 85, ++ 247, 13, 254, 33, 70, 1, 224, 12, 224, 1, 224, 45, 247, 140, 250, 152, ++ 248, 0, 0, 64, 7, 5, 213, 48, 70, 111, 247, 173, 253, 0, 32, 189, 232, ++ 240, 129, 1, 32, 251, 231, 0, 0, 196, 24, 32, 0, 22, 29, 32, 0, 4, 103, ++ 13, 0, 44, 12, 33, 0, 3, 1, 58, 112, 92, 13, 0, 29, 73, 48, 180, 10, ++ 104, 106, 177, 1, 70, 161, 251, 2, 5, 0, 35, 3, 251, 2, 82, 1, 251, ++ 3, 33, 24, 74, 25, 75, 18, 104, 27, 120, 90, 67, 4, 224, 64, 246, 235, ++ 76, 252, 255, 220, 147, 33, 0, 49, 160, 251, 1, 1, 100, 34, 48, 188, ++ 0, 35, 85, 247, 237, 187, 3, 1, 82, 166, 92, 13, 0, 240, 180, 15, 74, ++ 18, 104, 106, 177, 15, 75, 28, 104, 15, 75, 27, 120, 92, 67, 3, 70, ++ 164, 251, 3, 6, 0, 37, 5, 251, 3, 99, 4, 251, 1, 49, 10, 224, 100, 34, ++ 3, 70, 163, 251, 2, 5, 1, 251, 2, 81, 0, 36, 3, 251, 4, 17, 64, 246, ++ 235, 50, 240, 188, 0, 35, 85, 247, 204, 187, 228, 24, 32, 0, 224, 24, ++ 32, 0, 217, 24, 32, 0, 3, 1, 80, 244, 92, 13, 0, 16, 181, 4, 70, 69, ++ 247, 188, 250, 12, 73, 2, 40, 8, 112, 34, 106, 17, 208, 79, 244, 128, ++ 113, 10, 67, 34, 98, 9, 73, 9, 74, 9, 104, 18, 120, 81, 67, 64, 246, ++ 235, 50, 81, 67, 100, 34, 177, 251, 242, 241, 5, 74, 17, 96, 16, 189, ++ 128, 33, 237, 231, 0, 0, 136, 25, 32, 0, 224, 24, 32, 0, 217, 24, 32, ++ 0, 228, 24, 32, 0, 16, 1, 15, 0, 36, 198, 2, 0, 164, 240, 254, 184, ++ 0, 0, 36, 8, 13, 0, 16, 1, 15, 1, 120, 204, 2, 0, 163, 240, 194, 186, ++ 0, 0, 0, 2, 13, 0, 16, 1, 15, 2, 40, 219, 3, 0, 146, 240, 116, 187, ++ 0, 0, 20, 2, 13, 0, 16, 1, 15, 3, 84, 220, 3, 0, 146, 240, 230, 186, ++ 0, 0, 76, 252, 255, 215, 148, 33, 0, 36, 2, 13, 0, 16, 1, 15, 4, 80, ++ 204, 3, 0, 147, 240, 240, 186, 0, 0, 52, 2, 13, 0, 16, 1, 15, 5, 220, ++ 210, 3, 0, 146, 240, 180, 191, 0, 0, 72, 2, 13, 0, 16, 1, 15, 6, 44, ++ 207, 3, 0, 147, 240, 148, 185, 0, 0, 88, 2, 13, 0, 16, 1, 15, 7, 36, ++ 182, 3, 0, 148, 240, 36, 190, 0, 0, 112, 2, 13, 0, 16, 1, 15, 8, 112, ++ 27, 8, 0, 78, 240, 132, 187, 0, 0, 124, 2, 13, 0, 16, 1, 15, 9, 84, ++ 133, 1, 0, 184, 240, 138, 186, 0, 0, 108, 10, 13, 0, 16, 1, 15, 10, ++ 188, 146, 7, 0, 86, 240, 236, 191, 0, 0, 152, 2, 13, 0, 16, 1, 15, 11, ++ 4, 137, 7, 0, 87, 240, 205, 188, 0, 0, 162, 2, 13, 0, 16, 1, 15, 12, ++ 188, 132, 7, 0, 87, 240, 247, 190, 0, 0, 174, 2, 13, 0, 16, 1, 15, 13, ++ 192, 55, 8, 0, 112, 189, 0, 0, 0, 0, 0, 0, 0, 0, 16, 1, 15, 14, 176, ++ 55, 8, 0, 3, 41, 248, 210, 0, 0, 0, 0, 0, 0, 16, 1, 15, 15, 104, 60, ++ 7, 0, 92, 240, 110, 191, 0, 0, 72, 11, 13, 0, 16, 1, 15, 16, 148, 41, ++ 7, 0, 94, 240, 161, 185, 0, 0, 218, 12, 13, 0, 16, 1, 15, 17, 112, 57, ++ 7, 0, 92, 240, 166, 188, 0, 76, 252, 255, 210, 149, 33, 0, 0, 192, 2, ++ 13, 0, 16, 1, 15, 18, 116, 64, 7, 0, 92, 240, 45, 185, 0, 0, 210, 2, ++ 13, 0, 16, 1, 15, 19, 140, 69, 7, 0, 91, 240, 172, 190, 0, 0, 232, 2, ++ 13, 0, 16, 1, 15, 20, 192, 51, 7, 0, 92, 240, 156, 191, 0, 0, 252, 2, ++ 13, 0, 16, 1, 15, 21, 64, 52, 7, 0, 93, 240, 106, 188, 0, 0, 24, 13, ++ 13, 0, 16, 1, 15, 22, 172, 166, 3, 0, 149, 240, 42, 190, 0, 0, 4, 3, ++ 13, 0, 16, 1, 15, 23, 112, 39, 4, 0, 141, 240, 206, 189, 0, 0, 16, 3, ++ 13, 0, 6, 1, 4, 24, 15, 13, 0, 16, 1, 15, 24, 204, 84, 3, 0, 2, 33, ++ 0, 224, 0, 0, 0, 0, 0, 0, 16, 1, 15, 25, 200, 85, 3, 0, 154, 240, 166, ++ 190, 0, 0, 24, 3, 13, 0, 16, 1, 15, 26, 96, 82, 3, 0, 155, 240, 97, ++ 184, 0, 0, 38, 3, 13, 0, 16, 1, 15, 27, 128, 109, 3, 0, 153, 240, 218, ++ 186, 0, 0, 56, 3, 13, 0, 16, 1, 15, 28, 76, 92, 3, 0, 154, 240, 124, ++ 187, 0, 0, 72, 3, 13, 0, 16, 1, 15, 29, 216, 80, 3, 0, 155, 240, 62, ++ 185, 0, 0, 88, 3, 13, 0, 6, 1, 4, 172, 17, 13, 0, 16, 1, 15, 30, 60, ++ 94, 7, 0, 90, 240, 150, 186, 0, 0, 108, 3, 76, 252, 255, 205, 150, 33, ++ 0, 13, 0, 6, 1, 4, 152, 19, 13, 0, 16, 1, 15, 31, 148, 123, 7, 0, 88, ++ 240, 242, 187, 0, 0, 124, 3, 13, 0, 6, 1, 4, 244, 19, 13, 0, 16, 1, ++ 15, 32, 212, 205, 7, 0, 83, 240, 218, 186, 0, 0, 140, 3, 13, 0, 16, ++ 1, 15, 33, 184, 13, 7, 0, 0, 0, 139, 73, 0, 0, 0, 0, 0, 0, 16, 1, 15, ++ 34, 212, 22, 7, 0, 94, 240, 98, 190, 0, 0, 156, 3, 13, 0, 16, 1, 15, ++ 35, 44, 154, 7, 0, 87, 240, 172, 189, 0, 0, 136, 21, 13, 0, 16, 1, 15, ++ 36, 144, 231, 7, 0, 83, 240, 104, 189, 0, 0, 100, 34, 13, 0, 16, 1, ++ 15, 37, 36, 232, 7, 0, 81, 240, 194, 189, 0, 0, 172, 3, 13, 0, 16, 1, ++ 15, 38, 104, 240, 7, 0, 83, 240, 39, 185, 0, 0, 186, 34, 13, 0, 16, ++ 1, 15, 39, 100, 112, 6, 0, 107, 240, 95, 185, 0, 0, 38, 35, 13, 0, 16, ++ 1, 15, 40, 252, 107, 6, 0, 105, 240, 218, 187, 0, 0, 180, 3, 13, 0, ++ 16, 1, 15, 41, 204, 108, 6, 0, 107, 240, 18, 188, 0, 0, 244, 36, 13, ++ 0, 16, 1, 15, 42, 212, 105, 6, 0, 107, 240, 187, 189, 0, 0, 78, 37, ++ 13, 0, 16, 1, 15, 43, 220, 104, 6, 0, 107, 240, 146, 190, 0, 0, 4, 38, ++ 13, 0, 16, 76, 252, 255, 200, 151, 33, 0, 1, 15, 44, 96, 207, 5, 0, ++ 115, 240, 44, 186, 0, 0, 188, 3, 13, 0, 16, 1, 15, 45, 68, 38, 7, 0, ++ 96, 240, 104, 184, 0, 0, 24, 39, 13, 0, 16, 1, 15, 46, 224, 0, 2, 0, ++ 176, 240, 114, 185, 0, 0, 200, 3, 13, 0, 16, 1, 15, 47, 204, 247, 1, ++ 0, 176, 240, 5, 190, 0, 0, 218, 3, 13, 0, 16, 1, 15, 48, 212, 77, 5, ++ 0, 123, 240, 14, 187, 0, 0, 244, 3, 13, 0, 16, 1, 15, 49, 124, 241, ++ 4, 0, 129, 240, 70, 185, 0, 0, 12, 4, 13, 0, 16, 1, 15, 50, 164, 1, ++ 5, 0, 128, 240, 58, 185, 0, 0, 28, 4, 13, 0, 16, 1, 15, 51, 200, 2, ++ 5, 0, 128, 240, 180, 184, 0, 0, 52, 4, 13, 0, 16, 1, 15, 52, 184, 187, ++ 2, 0, 164, 240, 72, 188, 0, 0, 76, 4, 13, 0, 16, 1, 15, 53, 120, 58, ++ 0, 0, 1, 32, 32, 185, 0, 0, 0, 0, 0, 0, 16, 1, 15, 54, 32, 19, 0, 0, ++ 207, 240, 160, 184, 0, 0, 100, 4, 13, 0, 16, 1, 15, 55, 120, 66, 2, ++ 0, 172, 240, 254, 184, 0, 0, 120, 4, 13, 0, 16, 1, 15, 56, 96, 66, 2, ++ 0, 172, 240, 32, 185, 0, 0, 164, 4, 13, 0, 16, 1, 15, 57, 120, 140, ++ 1, 0, 183, 240, 32, 188, 0, 0, 188, 4, 13, 0, 76, 252, 255, 195, 152, ++ 33, 0, 16, 1, 15, 58, 12, 197, 5, 0, 115, 240, 220, 191, 0, 0, 200, ++ 4, 13, 0, 16, 1, 15, 59, 112, 198, 5, 0, 115, 240, 66, 191, 0, 0, 248, ++ 4, 13, 0, 16, 1, 15, 60, 32, 108, 5, 0, 121, 240, 110, 188, 0, 0, 0, ++ 5, 13, 0, 16, 1, 15, 61, 16, 190, 4, 0, 152, 70, 11, 48, 0, 0, 0, 0, ++ 0, 0, 16, 1, 15, 62, 176, 100, 6, 0, 108, 240, 199, 191, 0, 0, 66, 52, ++ 13, 0, 16, 1, 15, 63, 248, 103, 6, 0, 105, 240, 138, 190, 0, 0, 16, ++ 5, 13, 0, 16, 1, 15, 64, 252, 97, 6, 0, 109, 240, 112, 185, 0, 0, 224, ++ 52, 13, 0, 16, 1, 15, 65, 20, 172, 3, 0, 149, 240, 132, 188, 0, 0, 32, ++ 5, 13, 0, 16, 1, 15, 66, 224, 155, 6, 0, 105, 240, 202, 188, 0, 0, 120, ++ 53, 13, 0, 16, 1, 15, 67, 28, 161, 6, 0, 102, 240, 6, 186, 0, 0, 44, ++ 5, 13, 0, 16, 1, 15, 68, 144, 51, 4, 0, 141, 240, 212, 184, 0, 0, 60, ++ 5, 13, 0, 16, 1, 15, 69, 4, 62, 4, 0, 140, 240, 160, 187, 0, 0, 72, ++ 5, 13, 0, 16, 1, 15, 70, 144, 56, 4, 0, 140, 240, 126, 190, 0, 0, 144, ++ 5, 13, 0, 16, 1, 15, 71, 196, 101, 2, 0, 169, 240, 238, 191, 0, 0, 164, ++ 5, 13, 76, 252, 255, 190, 153, 33, 0, 0, 16, 1, 15, 72, 32, 76, 7, 0, ++ 91, 240, 204, 188, 0, 0, 188, 5, 13, 0, 16, 1, 15, 73, 204, 239, 3, ++ 0, 148, 240, 98, 187, 0, 0, 148, 54, 13, 0, 16, 1, 15, 74, 140, 248, ++ 3, 0, 144, 240, 164, 190, 0, 0, 216, 5, 13, 0, 16, 1, 15, 75, 12, 249, ++ 3, 0, 144, 240, 112, 190, 0, 0, 240, 5, 13, 0, 16, 1, 15, 76, 12, 242, ++ 3, 0, 145, 240, 0, 186, 0, 0, 16, 6, 13, 0, 16, 1, 15, 77, 32, 245, ++ 6, 0, 97, 240, 138, 184, 0, 0, 56, 6, 13, 0, 16, 1, 15, 78, 200, 242, ++ 6, 0, 97, 240, 191, 185, 0, 0, 74, 6, 13, 0, 16, 1, 15, 79, 164, 222, ++ 4, 0, 130, 240, 218, 187, 0, 0, 92, 6, 13, 0, 16, 1, 15, 80, 44, 66, ++ 5, 0, 124, 240, 30, 186, 0, 0, 108, 6, 13, 0, 16, 1, 15, 81, 252, 71, ++ 5, 0, 123, 240, 62, 191, 0, 0, 124, 6, 13, 0, 16, 1, 15, 82, 36, 32, ++ 3, 0, 161, 240, 216, 187, 0, 0, 216, 55, 13, 0, 16, 1, 15, 83, 108, ++ 32, 3, 0, 161, 240, 219, 187, 0, 0, 38, 56, 13, 0, 6, 1, 4, 136, 57, ++ 13, 0, 16, 1, 15, 84, 144, 200, 7, 0, 64, 26, 128, 178, 0, 0, 0, 0, ++ 0, 0, 6, 1, 4, 180, 57, 13, 0, 6, 1, 76, 252, 255, 185, 154, 33, 0, ++ 4, 222, 58, 13, 0, 16, 1, 15, 85, 68, 31, 8, 0, 78, 240, 160, 187, 0, ++ 0, 136, 6, 13, 0, 16, 1, 15, 86, 128, 30, 8, 0, 78, 240, 5, 188, 0, ++ 0, 142, 6, 13, 0, 16, 1, 15, 87, 232, 30, 8, 0, 78, 240, 212, 187, 0, ++ 0, 148, 6, 13, 0, 16, 1, 15, 88, 176, 31, 8, 0, 78, 240, 114, 187, 0, ++ 0, 152, 6, 13, 0, 16, 1, 15, 89, 20, 30, 8, 0, 78, 240, 66, 188, 0, ++ 0, 156, 6, 13, 0, 16, 1, 15, 90, 248, 221, 6, 0, 98, 240, 84, 188, 0, ++ 0, 164, 6, 13, 0, 16, 1, 15, 91, 52, 189, 5, 0, 116, 240, 185, 188, ++ 0, 0, 170, 6, 13, 0, 16, 1, 15, 92, 156, 188, 5, 0, 120, 240, 241, 184, ++ 0, 0, 130, 62, 13, 0, 16, 1, 15, 93, 236, 187, 5, 0, 120, 240, 131, ++ 185, 0, 0, 246, 62, 13, 0, 16, 1, 15, 94, 68, 183, 5, 0, 116, 240, 185, ++ 191, 0, 0, 186, 6, 13, 0, 16, 1, 15, 95, 132, 27, 2, 0, 174, 240, 164, ++ 189, 0, 0, 208, 6, 13, 0, 16, 1, 15, 96, 76, 64, 3, 0, 160, 240, 210, ++ 186, 0, 0, 244, 69, 13, 0, 16, 1, 15, 97, 208, 75, 3, 0, 155, 240, 130, ++ 189, 0, 0, 216, 6, 13, 0, 16, 1, 15, 98, 116, 77, 3, 0, 155, 240, 180, ++ 188, 76, 252, 255, 180, 155, 33, 0, 0, 0, 224, 6, 13, 0, 16, 1, 15, ++ 99, 28, 71, 3, 0, 155, 240, 230, 191, 0, 0, 236, 6, 13, 0, 16, 1, 15, ++ 100, 52, 53, 3, 0, 157, 240, 222, 184, 0, 0, 244, 6, 13, 0, 16, 1, 15, ++ 101, 156, 55, 3, 0, 156, 240, 184, 191, 0, 0, 16, 7, 13, 0, 16, 1, 15, ++ 102, 236, 23, 2, 0, 179, 240, 230, 185, 0, 0, 188, 75, 13, 0, 16, 1, ++ 15, 103, 56, 199, 1, 0, 179, 240, 242, 191, 0, 0, 32, 7, 13, 0, 16, ++ 1, 15, 104, 16, 68, 0, 0, 208, 240, 242, 188, 0, 0, 248, 77, 13, 0, ++ 16, 1, 15, 105, 4, 199, 1, 0, 180, 240, 15, 184, 0, 0, 38, 7, 13, 0, ++ 16, 1, 15, 106, 132, 211, 2, 0, 167, 240, 32, 191, 0, 0, 200, 81, 13, ++ 0, 16, 1, 15, 107, 240, 210, 2, 0, 163, 240, 32, 186, 0, 0, 52, 7, 13, ++ 0, 6, 1, 4, 124, 85, 13, 0, 6, 1, 4, 104, 88, 13, 0, 16, 1, 15, 108, ++ 240, 175, 1, 0, 186, 240, 96, 188, 0, 0, 180, 88, 13, 0, 16, 1, 15, ++ 109, 12, 7, 2, 0, 176, 240, 32, 184, 0, 0, 80, 7, 13, 0, 16, 1, 15, ++ 110, 100, 57, 8, 0, 81, 240, 228, 191, 0, 0, 48, 89, 13, 0, 16, 1, 15, ++ 111, 100, 86, 4, 0, 139, 240, 124, 184, 0, 0, 96, 76, 252, 255, 175, ++ 156, 33, 0, 7, 13, 0, 16, 1, 15, 112, 60, 86, 4, 0, 144, 240, 209, 185, ++ 0, 0, 226, 89, 13, 0, 16, 1, 15, 113, 176, 87, 4, 0, 138, 240, 217, ++ 191, 0, 0, 102, 7, 13, 0, 16, 1, 15, 114, 204, 45, 5, 0, 125, 240, 206, ++ 188, 0, 0, 108, 7, 13, 0, 16, 1, 15, 115, 128, 42, 3, 0, 157, 240, 122, ++ 190, 0, 0, 120, 7, 13, 0, 16, 1, 15, 116, 84, 164, 6, 0, 102, 240, 164, ++ 185, 0, 0, 160, 7, 13, 0, 16, 1, 15, 117, 20, 105, 5, 0, 121, 240, 72, ++ 191, 0, 0, 168, 7, 13, 0, 16, 1, 15, 118, 232, 112, 7, 0, 89, 240, 98, ++ 187, 0, 0, 176, 7, 13, 0, 16, 1, 15, 119, 132, 103, 7, 0, 90, 240, 28, ++ 184, 0, 0, 192, 7, 13, 0, 16, 1, 15, 120, 84, 47, 0, 0, 205, 240, 60, ++ 188, 0, 0, 208, 7, 13, 0, 16, 1, 15, 121, 224, 49, 0, 0, 205, 240, 250, ++ 186, 0, 0, 216, 7, 13, 0, 16, 1, 15, 122, 252, 181, 1, 0, 181, 240, ++ 248, 184, 0, 0, 240, 7, 13, 0, 16, 1, 15, 123, 252, 199, 1, 0, 179, ++ 240, 254, 191, 0, 0, 252, 7, 13, 0, 16, 1, 15, 124, 100, 200, 1, 0, ++ 179, 240, 207, 191, 0, 0, 6, 8, 13, 0, 16, 1, 15, 125, 80, 180, 1, 0, ++ 181, 240, 224, 185, 0, 0, 76, 252, 11, 170, 157, 33, 0, 20, 8, 13, 0, ++ 254, 0, 0, 78, 252, 4, 255, 255, 255, 255 ++}; ++ ++const int brcm_patch_ram_length = sizeof(brcm_patchram_buf); +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/CMakeLists.txt +new file mode 100644 +index 0000000000..55b7e63ecf +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/CMakeLists.txt +@@ -0,0 +1,34 @@ ++# Copyright (c) 2020-2021 ARM Limited. All rights reserved. ++# SPDX-License-Identifier: Apache-2.0 ++ ++add_library(mbed-portenta-whd-4343w-fw INTERFACE) ++target_include_directories(mbed-portenta-whd-4343w-fw ++ INTERFACE ++ resources/firmware/COMPONENT_4343W_FS ++) ++target_sources(mbed-portenta-whd-4343w-fw ++ INTERFACE ++ resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c ++ resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c ++) ++ ++add_library(mbed-portenta-whd-4343w-nvram INTERFACE) ++target_include_directories(mbed-portenta-whd-4343w-nvram INTERFACE resources/nvram) ++ ++add_library(mbed-portenta-whd INTERFACE) ++target_include_directories(mbed-portenta-whd ++ INTERFACE ++ . ++ port ++ interface ++) ++ ++target_sources(mbed-portenta-whd ++ INTERFACE ++ port/cyhal.c ++ port/cyhalgpio.cpp ++ port/cyhalsdio.c ++ port/wiced_filesystem.cpp ++ interface/cyabs_rtos_rtxv5.c ++) ++ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/generated_mac_address.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/generated_mac_address.txt +new file mode 100644 +index 0000000000..eb735ba173 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/generated_mac_address.txt +@@ -0,0 +1,9 @@ ++/* ++ * This file is used to set the MAC address in NVRAM. ++ * The MAC address of the Wi-Fi device may be configured in OTP and/or in NVRAM. ++ * If both OTP and NVRAM contains the MAC address then OTP programmed MAC address will be used. ++ * PSOC boards are usually programmed with OTP MAC address. ++ * MAC address is printed during WHD power up ++ */ ++ ++#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=00:A0:50:6f:b2:ea" +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cy_result.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cy_result.h +new file mode 100644 +index 0000000000..8277169ab9 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cy_result.h +@@ -0,0 +1,228 @@ ++/***************************************************************************//** ++* \file cy_result.h ++* ++* \brief ++* Basic function result handling. Defines a simple type for conveying ++* information about whether something succeeded or details about any issues ++* that were detected. ++* ++******************************************************************************** ++* \copyright ++* Copyright 2018-2020 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++/** ++* \addtogroup group_result Result Type ++* \ingroup group_abstraction ++* \{ ++* \anchor anchor_general_description ++* \brief Defines a type and related utilities for function result handling. ++* ++* The @ref cy_rslt_t type is a structured bitfield which encodes information ++* about result type, the originating module, and a code for the specific ++* error (or warning etc). In order to extract these individual fields from ++* a @ref cy_rslt_t value, the utility macros @ref CY_RSLT_GET_TYPE, @ref CY_RSLT_GET_MODULE, ++* and @ref CY_RSLT_GET_CODE are provided. For example: ++* \code ++* cy_rslt_t result = cy_hal_do_operation(arg); ++* // Will be CY_RSLT_TYPE_INFO, CY_RSLT_TYPE_WARNING, CY_RSLT_TYPE_ERROR, or CY_RSLT_TYPE_FATAL ++* uint8_t type = CY_RSLT_GET_TYPE(result) ++* // See the "Modules" section for possible values ++* uint16_t module_id = CY_RSLT_GET_MODULE(result); ++* // Specific error codes are defined by each module ++* uint16_t error_code = CY_RSLT_GET_CODE(result); ++* \endcode ++*/ ++ ++#if !defined(CY_RESULT_H) ++#define CY_RESULT_H ++ ++#include ++ ++#if defined(__cplusplus) ++extern "C" { ++#endif ++ ++/** ++ * @brief Provides the result of an operation as a structured bitfield. ++ * ++ * See the \ref anchor_general_description "General Description" ++ * for more details on structure and usage. ++ */ ++typedef uint32_t cy_rslt_t; ++ ++/** @ref cy_rslt_t return value indicating success */ ++#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) ++ ++/** \cond INTERNAL */ ++/** Mask for the bit at position "x" */ ++#define CY_BIT_MASK(x) ((1UL << (x)) - 1U) ++ ++/** Bit position of the result type */ ++#define CY_RSLT_TYPE_POSITION (16U) ++/** Bit width of the result type */ ++#define CY_RSLT_TYPE_WIDTH (2U) ++/** Bit position of the module identifier */ ++#define CY_RSLT_MODULE_POSITION (18U) ++/** Bit width of the module identifier */ ++#define CY_RSLT_MODULE_WIDTH (14U) ++/** Bit position of the result code */ ++#define CY_RSLT_CODE_POSITION (0U) ++/** Bit width of the result code */ ++#define CY_RSLT_CODE_WIDTH (16U) ++ ++/** Mask for the result type */ ++#define CY_RSLT_TYPE_MASK CY_BIT_MASK(CY_RSLT_TYPE_WIDTH) ++/** Mask for the module identifier */ ++#define CY_RSLT_MODULE_MASK CY_BIT_MASK(CY_RSLT_MODULE_WIDTH) ++/** Mask for the result code */ ++#define CY_RSLT_CODE_MASK CY_BIT_MASK(CY_RSLT_CODE_WIDTH) ++ ++/** \endcond */ ++ ++/** ++* \{ ++* @name Fields ++* Utility macros for constructing result values and extracting individual fields from existing results. ++*/ ++ ++/** ++ * @brief Get the value of the result type field ++ * @param x the @ref cy_rslt_t value from which to extract the result type ++ */ ++#define CY_RSLT_GET_TYPE(x) (((x) >> CY_RSLT_TYPE_POSITION) & CY_RSLT_TYPE_MASK) ++/** ++ * @brief Get the value of the module identifier field ++ * @param x the @ref cy_rslt_t value from which to extract the module id ++ */ ++#define CY_RSLT_GET_MODULE(x) (((x) >> CY_RSLT_MODULE_POSITION) & CY_RSLT_MODULE_MASK) ++/** ++ * @brief Get the value of the result code field ++ * @param x the @ref cy_rslt_t value from which to extract the result code ++ */ ++#define CY_RSLT_GET_CODE(x) (((x) >> CY_RSLT_CODE_POSITION) & CY_RSLT_CODE_MASK) ++ ++/** ++ * @brief Create a new @ref cy_rslt_t value that encodes the specified type, module, and result code. ++ * @param type one of @ref CY_RSLT_TYPE_INFO, @ref CY_RSLT_TYPE_WARNING, ++ * @ref CY_RSLT_TYPE_ERROR, @ref CY_RSLT_TYPE_FATAL ++ * @param module Identifies the module where this result originated; see @ref anchor_modules "Modules". ++ * @param code a module-defined identifier to identify the specific situation that ++ * this result describes. ++ */ ++#define CY_RSLT_CREATE(type, module, code) \ ++ ((((module) & CY_RSLT_MODULE_MASK) << CY_RSLT_MODULE_POSITION) | \ ++ (((code) & CY_RSLT_CODE_MASK) << CY_RSLT_CODE_POSITION) | \ ++ (((type) & CY_RSLT_TYPE_MASK) << CY_RSLT_TYPE_POSITION)) ++ ++/** \} fields */ ++ ++/** ++* \{ ++* @name Result Types ++* Defines codes to identify the type of result. ++*/ ++ ++/** @brief The result code is informational-only */ ++#define CY_RSLT_TYPE_INFO (0U) ++/** @brief The result code is warning of a problem but will proceed */ ++#define CY_RSLT_TYPE_WARNING (1U) ++/** @brief The result code is an error */ ++#define CY_RSLT_TYPE_ERROR (2U) ++/** @brief The result code is a fatal error */ ++#define CY_RSLT_TYPE_FATAL (3U) ++ ++/** \} severity */ ++ ++/** ++* \{ ++* @name Modules ++* @anchor anchor_modules ++* Defines codes to identify the module from which an error originated. ++* For some large libraries, a range of module codes is defined here; ++* see the library documentation for values corresponding to individual modules. ++* Valid range is 0x0000-0x4000. ++*/ ++/**** DRIVER Module codes: 0x0000 - 0x00FF ****/ ++/** Base module identifier for peripheral driver library drivers (0x0000 - 0x007F) */ ++#define CY_RSLT_MODULE_DRIVERS_PDL_BASE (0x0000U) ++/** Base module identifier for wireless host driver library modules (0x0080 - 0x00FF) */ ++#define CY_RSLT_MODULE_DRIVERS_WHD_BASE (0x0080U) ++ ++/** Deprecated. Use \ref CY_RSLT_MODULE_ABSTRACTION_HAL */ ++#define CY_RSLT_MODULE_ABSTRACTION_HAL_BASE (0x0100U) ++/** Module identifier for the Hardware Abstraction Layer */ ++#define CY_RSLT_MODULE_ABSTRACTION_HAL (0x0100U) ++/** Module identifier for board support package */ ++#define CY_RSLT_MODULE_ABSTRACTION_BSP (0x0180U) ++/** Module identifier for file system abstraction */ ++#define CY_RSLT_MODULE_ABSTRACTION_FS (0x0181U) ++/** Module identifier for resource abstraction */ ++#define CY_RSLT_MODULE_ABSTRACTION_RESOURCE (0x0182U) ++/** Module identifier for rtos abstraction */ ++#define CY_RSLT_MODULE_ABSTRACTION_OS (0x0183U) ++/** Base identifier for environment abstraction modules (0x0184 - 0x01FF) */ ++#define CY_RSLT_MODULE_ABSTRACTION_ENV (0x0184U) ++ ++/** Base module identifier for Board Libraries (0x01A0 - 0x01BF) */ ++#define CY_RSLT_MODULE_BOARD_LIB_BASE (0x01A0U) ++/** Module identifier for the Retarget IO Board Library */ ++#define CY_RSLT_MODULE_BOARD_LIB_RETARGET_IO (0x1A0U) ++/** Module identifier for the RGB LED Board Library */ ++#define CY_RSLT_MODULE_BOARD_LIB_RGB_LED (0x01A1U) ++/** Module identifier for the Serial Flash Board Library */ ++#define CY_RSLT_MODULE_BOARD_LIB_SERIAL_FLASH (0x01A2U) ++/** Module identifier for the WiFi Host Driver + Board Support Integration Library */ ++#define CY_RSLT_MODULE_BOARD_LIB_WHD_INTEGRATION (0x01A3U) ++ ++/** Base module identifier for Shield Board Libraries (0x01B8 - 0x01BF) */ ++#define CY_RSLT_MODULE_BOARD_SHIELD_BASE (0x01B8U) ++/** Module identifier for Shield Board CY8CKIT-028-EPD */ ++#define CY_RSLT_MODULE_BOARD_SHIELD_028_EPD (0x01B8U) ++/** Module identifier for Shield Board CY8CKIT-028-TFT */ ++#define CY_RSLT_MODULE_BOARD_SHIELD_028_TFT (0x01B9U) ++/** Module identifier for Shield Board CY8CKIT-032 */ ++#define CY_RSLT_MODULE_BOARD_SHIELD_032 (0x01BAU) ++ ++/** Base module identifier for Board Hardware Libraries (0x01C0 - 0x01FF) */ ++#define CY_RSLT_MODULE_BOARD_HARDWARE_BASE (0x01C0U) ++/** Module identifier for the BMI160 Motion Sensor Library */ ++#define CY_RSLT_MODULE_BOARD_HARDWARE_BMI160 (0x01C0U) ++/** Module identifier for the E2271CS021 E-Ink Controller Library */ ++#define CY_RSLT_MODULE_BOARD_HARDWARE_E2271CS021 (0x01C1U) ++/** Module identifier for the NTC GPIO Thermistor Library */ ++#define CY_RSLT_MODULE_BOARD_HARDWARE_THERMISTOR (0x01C2U) ++/** Module identifier for the SSD1306 OLED Controller Library */ ++#define CY_RSLT_MODULE_BOARD_HARDWARE_SSD1306 (0x01C3U) ++/** Module identifier for the ST7789V TFT Controller Library */ ++#define CY_RSLT_MODULE_BOARD_HARDWARE_ST7789V (0x01C4U) ++/** Module identifier for the Light Sensor Library */ ++#define CY_RSLT_MODULE_BOARD_HARDWARE_LIGHT_SENSOR (0x01C5U) ++/** Module identifier for the AK4954A Audio Codec Library */ ++#define CY_RSLT_MODULE_BOARD_HARDWARE_AK4954A (0x01C6U) ++ ++/** Base module identifier for Middleware Libraries (0x0200 - 0x02FF) */ ++#define CY_RSLT_MODULE_MIDDLEWARE_BASE (0x0200U) ++ ++/** \} modules */ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* CY_RESULT_H */ ++ ++/** \} group_result */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos.h +new file mode 100644 +index 0000000000..e19ffc49f7 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos.h +@@ -0,0 +1,711 @@ ++/***************************************************************************//** ++* \file cyabs_rtos.h ++* ++* \brief ++* Defines the Cypress RTOS Interface. Provides prototypes for functions that ++* allow Cypress libraries to use RTOS resources such as threads, mutexes & ++* timing functions in an abstract way. The APIs are implemented in the Port ++* Layer RTOS interface which is specific to the RTOS in use. ++* ++******************************************************************************** ++* \copyright ++* Copyright 2018-2020 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++#ifndef INCLUDED_CY_RTOS_INTERFACE_H_ ++#define INCLUDED_CY_RTOS_INTERFACE_H_ ++ ++#include "cyabs_rtos_impl.h" ++#include "cy_result.h" ++#include ++#include ++#include ++ ++/** ++* \defgroup group_abstraction_rtos_common Common ++ * General types and defines for working with the RTOS abstraction layer. ++* \defgroup group_abstraction_rtos_mutex Mutex ++ * APIs for acquiring and working with Mutexes. ++* \defgroup group_abstraction_rtos_queue Queue ++ * APIs for creating and working with Queues. ++* \defgroup group_abstraction_rtos_semaphore Semaphore ++ * APIs for acquiring and working with Semaphores. ++* \defgroup group_abstraction_rtos_threads Threads ++ * APIs for creating and working with Threads. ++* \defgroup group_abstraction_rtos_time Time ++ * APIs for getting the current time and waiting. ++* \defgroup group_abstraction_rtos_timer Timer ++ * APIs for creating and working with Timers. ++*/ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++/*********************************************** CONSTANTS **********************************************/ ++ ++/** ++ * \ingroup group_abstraction_rtos_common ++ * \{ ++ */ ++ ++#if defined(DOXYGEN) ++//#include "Template/cyabs_rtos_impl.h" ++ ++/** Return value indicating success */ ++#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) ++#endif ++ ++/** Used with RTOS calls that require a timeout. This implies the call will never timeout. */ ++#define CY_RTOS_NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) ++ ++// ++// Note on error strategy. If the error is a normal part of operation (timeouts, full queues, empty ++// queues), the these errors are listed here and the abstraction layer implementation must map from the ++// underlying errors to these. If the errors are special cases, the the error \ref CY_RTOS_GENERAL_ERROR ++// will be returned and \ref cy_rtos_last_error() can be used to retrieve the RTOS specific error message. ++// ++/** Requested operation did not complete in the specified time */ ++#define CY_RTOS_TIMEOUT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 0) ++/** The RTOS could not allocate memory for the specified operation */ ++#define CY_RTOS_NO_MEMORY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 1) ++/** An error occured in the RTOS */ ++#define CY_RTOS_GENERAL_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 2) ++/** A bad argument was passed into the APIs */ ++#define CY_RTOS_BAD_PARAM CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 5) ++/** A memory alignment issue was detected. Ensure memory provided is aligned per \ref CY_RTOS_ALIGNMENT_MASK */ ++#define CY_RTOS_ALIGNMENT_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 6) ++ ++/** \} group_abstraction_rtos_common */ ++ ++/** ++ * \ingroup group_abstraction_rtos_queue ++ * \{ ++ */ ++ ++/** The Queue is already full and can't accept any more items at this time */ ++#define CY_RTOS_QUEUE_FULL CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 3) ++/** The Queue is empty and has nothing to remove */ ++#define CY_RTOS_QUEUE_EMPTY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 4) ++ ++/** \} group_abstraction_rtos_queue */ ++ ++/*********************************************** TYPES **********************************************/ ++ ++/** ++ * The state a thread can be in ++ * ++ * \ingroup group_abstraction_rtos_threads ++ */ ++typedef enum cy_thread_state ++{ ++ CY_THREAD_STATE_INACTIVE, /**< thread has not started or was terminated but not yet joined */ ++ CY_THREAD_STATE_READY, /**< thread can run, but is not currently */ ++ CY_THREAD_STATE_RUNNING, /**< thread is currently running */ ++ CY_THREAD_STATE_BLOCKED, /**< thread is blocked waiting for something */ ++ CY_THREAD_STATE_TERMINATED, /**< thread has terminated but not freed */ ++ CY_THREAD_STATE_UNKNOWN, /**< thread is in an unknown state */ ++} cy_thread_state_t; ++ ++/** ++ * The type of timer ++ * ++ * \ingroup group_abstraction_rtos_timer ++ */ ++typedef enum cy_timer_trigger_type ++{ ++ CY_TIMER_TYPE_PERIODIC, /**< called periodically until stopped */ ++ CY_TIMER_TYPE_ONCE, /**< called once only */ ++ cy_timer_type_periodic = CY_TIMER_TYPE_PERIODIC, /**< \deprecated replaced by \ref CY_TIMER_TYPE_PERIODIC */ ++ cy_timer_type_once = CY_TIMER_TYPE_ONCE, /**< \deprecated replaced by \ref CY_TIMER_TYPE_ONCE */ ++} cy_timer_trigger_type_t; ++ ++/** ++ * The type of a function that is the entry point for a thread ++ * ++ * @param[in] arg the argument passed from the thread create call to the entry function ++ * ++ * \ingroup group_abstraction_rtos_threads ++ */ ++typedef void (*cy_thread_entry_fn_t)(cy_thread_arg_t arg); ++ ++/** ++ * The callback function to be called by a timer ++ * ++ * \ingroup group_abstraction_rtos_timer ++ */ ++typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg); ++ ++/** ++ * Return the last error from the RTOS. ++ * ++ * The functions in the RTOS abstraction layer adhere to the Cypress return ++ * results calling convention. The underlying RTOS implementations will not but rather ++ * will have their own error code conventions. This function is provided as a service ++ * to the developer, mostly for debugging, and returns the underlying RTOS error code ++ * from the last RTOS abstraction layer that returned \ref CY_RTOS_GENERAL_ERROR. ++ * ++ * @return RTOS specific error code. ++ * ++ * \ingroup group_abstraction_rtos_common ++ */ ++cy_rtos_error_t cy_rtos_last_error(); ++ ++/*********************************************** Threads **********************************************/ ++ ++/** ++ * \ingroup group_abstraction_rtos_threads ++ * \{ ++ */ ++ ++/** Create a thread with specific thread argument. ++ * ++ * This function is called to startup a new thread. If the thread can exit, it must call ++ * \ref cy_rtos_exit_thread() just before doing so. All created threads that can terminate, either ++ * by themselves or forcefully by another thread MUST have \ref cy_rtos_join_thread() called on them ++ * by another thread in order to cleanup any resources that might have been allocated for them. ++ * ++ * @param[out] thread Pointer to a variable which will receive the new thread handle ++ * @param[in] entry_function Function pointer which points to the main function for the new thread ++ * @param[in] name String thread name used for a debugger ++ * @param[in] stack The buffer to use for the thread stack. This must be aligned to ++ * \ref CY_RTOS_ALIGNMENT_MASK with a size of at least \ref CY_RTOS_MIN_STACK_SIZE. ++ * If stack is null, cy_rtos_create_thread will allocate a stack from the heap. ++ * @param[in] stack_size The size of the thread stack in bytes ++ * @param[in] priority The priority of the thread. Values are operating system specific, but some ++ * common priority levels are defined: ++ * CY_THREAD_PRIORITY_LOW ++ * CY_THREAD_PRIORITY_NORMAL ++ * CY_THREAD_PRIORITY_HIGH ++ * @param[in] arg The argument to pass to the new thread ++ * ++ * @return The status of thread create request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, ++ const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg); ++ ++/** Exit the current thread. ++ * ++ * This function is called just before a thread exits. In some cases it is sufficient ++ * for a thread to just return to exit, but in other cases, the RTOS must be explicitly ++ * signaled. In cases where a return is sufficient, this should be a null funcition. ++ * where the RTOS must be signaled, this function should perform that In cases operation. ++ * In code using RTOS services, this function should be placed at any at any location ++ * where the main thread function will return, exiting the thread. Threads that can ++ * exit must still be joined (\ref cy_rtos_join_thread) to ensure their resources are ++ * fully cleaned up. ++ * ++ * @return The status of thread exit request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_exit_thread(); ++ ++/** Terminates another thread. ++ * ++ * This function is called to terminate another thread and reap the resources claimed ++ * by the thread. This should be called both when forcibly terminating another thread ++ * as well as any time a thread can exit on its own. For some RTOS implementations ++ * this is not required as the thread resources are claimed as soon as it exits. In ++ * other cases, this must be called to reclaim resources. Threads that are terminated ++ * must still be joined (\ref cy_rtos_join_thread) to ensure their resources are fully ++ * cleaned up. ++ * ++ * @param[in] thread Handle of the thread to terminate ++ * ++ * @returns The status of the thread terminate. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread); ++ ++/** Waits for a thread to complete. ++ * ++ * This must be called on any thread that can complete to ensure that any resources that ++ * were allocated for it are cleaned up. ++ * ++ * @param[in] thread Handle of the thread to wait for ++ * ++ * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread); ++ ++/** Checks if the thread is running ++ * ++ * This function is called to determine if a thread is actively running or not. For information on ++ * the thread state, use the \ref cy_rtos_get_thread_state() function. ++ * ++ * @param[in] thread Handle of the terminated thread to delete ++ * @param[out] running Returns true if the thread is running, otherwise false ++ * ++ * @returns The status of the thread running check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running); ++ ++/** Gets the state the thread is currently in ++ * ++ * This function is called to determine if a thread is running/blocked/inactive/ready etc. ++ * ++ * @param[in] thread Handle of the terminated thread to delete ++ * @param[out] state Returns the state the thread is currently in ++ * ++ * @returns The status of the thread state check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state); ++ ++/** Get current thread handle ++ * ++ * Returns the unique thread handle of the current running thread. ++ * ++ * @param[out] thread Handle of the current running thread ++ * ++ * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread); ++ ++/** \} group_abstraction_rtos_threads */ ++ ++/*********************************************** Mutexes **********************************************/ ++ ++/** ++ * \ingroup group_abstraction_rtos_mutex ++ * \{ ++ */ ++ ++/** Create a recursive mutex. ++ * ++ * Creates a binary mutex which can be used to synchronize between threads ++ * and between threads and ISRs. Created mutexes are recursive and support priority inheritance. ++ * ++ * This function has been replaced by \ref cy_rtos_init_mutex2 which allow for specifying ++ * whether or not the mutex supports recursion or not. ++ * ++ * @param[out] mutex Pointer to the mutex handle to be initialized ++ * ++ * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++#define cy_rtos_init_mutex(mutex) cy_rtos_init_mutex2(mutex, true) ++ ++/** Create a mutex which can support recursion or not. ++ * ++ * Creates a binary mutex which can be used to synchronize between threads and between threads and ++ * ISRs. Created mutexes can support priority inheritance if recursive. ++ * ++ * \note Not all RTOS implementations support non-recursive mutexes. In this case a recursive ++ * mutex will be created. ++ * ++ * @param[out] mutex Pointer to the mutex handle to be initialized ++ * @param[in] recursive Should the created mutex support recursion or not ++ * ++ * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive); ++ ++/** Get a mutex. ++ * ++ * If the mutex is available, it is acquired and this function returned. ++ * If the mutex is not available, the thread waits until the mutex is available ++ * or until the timeout occurs. ++ * ++ * @note This function must not be called from an interrupt context as it may block. ++ * ++ * @param[in] mutex Pointer to the mutex handle ++ * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get ++ * the mutex. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. ++ * Must be zero if in_isr is true. ++ * ++ * @return The status of the get mutex. Returns timeout if mutex was not acquired ++ * before timeout_ms period. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms); ++ ++/** Set a mutex. ++ * ++ * The mutex is released allowing any other threads waiting on the mutex to ++ * obtain the semaphore. ++ * ++ * @param[in] mutex Pointer to the mutex handle ++ * ++ * @return The status of the set mutex request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ * ++ */ ++cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex); ++ ++/** Deletes a mutex. ++ * ++ * This function frees the resources associated with a sempahore. ++ * ++ * @param[in] mutex Pointer to the mutex handle ++ * ++ * @return The status to the delete request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex); ++ ++/** \} group_abstraction_rtos_mutex */ ++ ++/*********************************************** Semaphores **********************************************/ ++ ++/** ++ * \ingroup group_abstraction_rtos_semaphore ++ * \{ ++ */ ++ ++/** ++ * Create a semaphore ++ * ++ * This is basically a counting semaphore. ++ * ++ * @param[in,out] semaphore Pointer to the semaphore handle to be initialized ++ * @param[in] maxcount The maximum count for this semaphore ++ * @param[in] initcount The initial count for this semaphore ++ * ++ * @return The status of the semaphore creation. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount); ++ ++/** ++ * Get/Acquire a semaphore ++ * ++ * If the semaphore count is zero, waits until the semaphore count is greater than zero. ++ * Once the semaphore count is greater than zero, this function decrements ++ * the count and return. It may also return if the timeout is exceeded. ++ * ++ * @param[in] semaphore Pointer to the semaphore handle ++ * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get ++ * the semaphore. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. Must ++ * be zero is in_isr is true ++ * @param[in] in_isr true if we are trying to get the semaphore from with an ISR ++ * @return The status of get semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr); ++ ++/** ++ * Set/Release a semaphore ++ * ++ * Increments the semaphore count, up to the maximum count for this semaphore. ++ * ++ * @param[in] semaphore Pointer to the semaphore handle ++ * @param[in] in_isr Value of true indicates calling from interrupt context ++ * Value of false indicates calling from normal thread context ++ * @return The status of set semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr); ++ ++/** ++ * Get the count of a semaphore. ++ * ++ * Gets the number of available tokens on the semaphore. ++ * ++ * @param[in] semaphore Pointer to the semaphore handle ++ * @param[out] count Pointer to the return count ++ * @return The status of get semaphore count operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count); ++ ++/** ++ * Deletes a semaphore ++ * ++ * This function frees the resources associated with a semaphore. ++ * ++ * @param[in] semaphore Pointer to the semaphore handle ++ * ++ * @return The status of semaphore deletion [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore); ++ ++/** \} group_abstraction_rtos_semaphore */ ++ ++/*********************************************** Events **********************************************/ ++ ++/** ++ * \ingroup group_abstraction_rtos_event ++ * \{ ++ */ ++ ++/** Create an event. ++ * ++ * This is an event which can be used to signal a set of threads ++ * with a 32 bit data element. ++ * ++ * @param[in,out] event Pointer to the event handle to be initialized ++ * ++ * @return The status of the event initialization request. ++ * [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_init_event(cy_event_t *event); ++ ++/** Set the event flag bits. ++ * ++ * This is an event which can be used to signal a set of threads ++ * with a 32 bit data element. Any threads waiting on this event are released ++ * ++ * @param[in] event Pointer to the event handle ++ * @param[in] bits The value of the 32 bit flags ++ * @param[in] in_isr If true, this is called from an ISR, otherwise from a thread ++ * ++ * @return The status of the set request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; ++ ++/** ++ * Clear the event flag bits ++ * ++ * This function clears bits in the event. ++ * ++ * @param[in] event Pointer to the event handle ++ * @param[in] bits Any bits set in this value, will be cleared in the event. ++ * @param[in] in_isr if true, this is called from an ISR, otherwise from a thread ++ * ++ * @return The status of the clear flags request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; ++ ++/** Get the event bits. ++ * ++ * Returns the current bits for the event. ++ * ++ * @param[in] event Pointer to the event handle ++ * @param[out] bits pointer to receive the value of the event flags ++ * ++ * @return The status of the get request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits); ++ ++/** Wait for the event and return bits. ++ * ++ * Waits for the event to be set and then returns the bits associated ++ * with the event, or waits for the given timeout period. ++ * @note This function returns if any bit in the set is set. ++ * ++ * @param[in] event Pointer to the event handle ++ * @param[in,out] bits pointer to receive the value of the event flags ++ * @param[in] clear if true, clear any bits set that cause the wait to return ++ * if false, do not clear bits ++ * @param[in] all if true, all bits in the initial bits value must be set to return ++ * if false, any one bit in the initial bits value must be set to return ++ * @param[in] timeout The amount of time to wait in milliseconds ++ * ++ * @return The status of the wait for event request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout); ++ ++/** Deinitialize a event. ++ * ++ * This function frees the resources associated with an event. ++ * ++ * @param[in] event Pointer to the event handle ++ * ++ * @return The status of the deletion request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_deinit_event(cy_event_t *event); ++ ++/** \} group_abstraction_rtos_event */ ++ ++/*********************************************** Queues **********************************************/ ++ ++/** ++ * \ingroup group_abstraction_rtos_queue ++ * \{ ++ */ ++ ++/** Create a queue. ++ * ++ * This is a queue of data where entries are placed on the back of the queue ++ * and removed from the front of the queue. ++ * ++ * @param[out] queue Pointer to the queue handle ++ * @param[in] length The maximum length of the queue in items ++ * @param[in] itemsize The size of each item in the queue. ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize); ++ ++/** Put an item in a queue. ++ * ++ * This function puts an item in the queue. The item is copied ++ * into the queue using a memory copy and the data pointed to by item_ptr ++ * is no longer referenced once the call returns. ++ * ++ * @note If in_isr is true, timeout_ms must be zero. ++ * ++ * @param[in] queue Pointer to the queue handle ++ * @param[in] item_ptr Pointer to the item to place in the queue ++ * @param[in] timeout_ms The time to wait to place the item in the queue ++ * @param[in] in_isr If true this is being called from within and ISR ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_FULL] ++ */ ++cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr); ++ ++/** Gets an item in a queue. ++ * ++ * This function gets an item from the queue. The item is copied ++ * out of the queue into the memory provide by item_ptr. This space must be ++ * large enough to hold a queue entry as defined when the queue was initialized. ++ * ++ * @note If in_isr is true, timeout_ms must be zero. ++ * ++ * @param[in] queue Pointer to the queue handle ++ * @param[in] item_ptr Pointer to the memory for the item from the queue ++ * @param[in] timeout_ms The time to wait to get an item from the queue ++ * @param[in] in_isr If true this is being called from within an ISR ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_EMPTY] ++ */ ++cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr); ++ ++/** Return the number of items in the queue. ++ * ++ * This function returns the number of items currently in the queue. ++ * ++ * @param[in] queue Pointer to the queue handle ++ * @param[out] num_waiting Pointer to the return count ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting); ++ ++/** Return the amount of empty space in the queue. ++ * ++ * This function returns the amount of empty space in the ++ * queue. For instance, if the queue was created with 10 entries max and there ++ * are currently 2 entries in the queue, this will return 8. ++ * ++ * @param[in] queue Pointer to the queue handle ++ * @param[out] num_spaces Pointer to the return count. ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces); ++ ++/** Reset the queue. ++ * ++ * This function sets the queue to empty. ++ * ++ * @param[in] queue pointer to the queue handle ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue); ++ ++/** Deinitialize the queue handle. ++ * ++ * This function de-initializes the queue and returns all ++ * resources used by the queue. ++ * ++ * @param[in] queue Pointer to the queue handle ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue); ++ ++/** \} group_abstraction_rtos_queue */ ++ ++/*********************************************** Timers **********************************************/ ++ ++/** ++ * \ingroup group_abstraction_rtos_timer ++ * \{ ++ */ ++ ++/** Create a new timer. ++ * ++ * This function initializes a timer object. ++ * @note The timer is not active until start is called. ++ * @note The callback may be (likely will be) called from a different thread. ++ * ++ * @param[out] timer Pointer to the timer handle to initialize ++ * @param[in] type Type of timer (periodic or once) ++ * @param[in] fun The function ++ * @param[in] arg Argument to pass along to the callback function ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, ++ cy_timer_callback_t fun, cy_timer_callback_arg_t arg); ++ ++/** Start a timer. ++ * ++ * @param[in] timer Pointer to the timer handle ++ * @param[in] num_ms The number of milliseconds to wait before the timer fires ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms); ++ ++/** Stop a timer. ++ * ++ * @param[in] timer Pointer to the timer handle ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer); ++ ++/** Returns state of a timer. ++ * ++ * @param[in] timer Pointer to the timer handle ++ * @param[out] state Return value for state, true if running, false otherwise ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state); ++ ++/** Deinit the timer. ++ * ++ * This function deinitializes the timer and frees all consumed resources. ++ * ++ * @param[in] timer Pointer to the timer handle ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer); ++ ++/** \} group_abstraction_rtos_timer */ ++ ++/*********************************************** Time **********************************************/ ++ ++/** ++ * \ingroup group_abstraction_rtos_time ++ * \{ ++ */ ++ ++/** Gets time in milliseconds since RTOS start. ++ * ++ * @note Since this is only 32 bits, it will roll over every 49 days, 17 hours, 2 mins, 47.296 seconds ++ * ++ * @param[out] tval Pointer to the struct to populate with the RTOS time ++ * ++ * @returns Time in milliseconds since the RTOS started. ++ */ ++cy_rslt_t cy_rtos_get_time(cy_time_t *tval); ++ ++/** Delay for a number of milliseconds. ++ * ++ * Processing of this function depends on the minimum sleep ++ * time resolution of the RTOS. The current thread should sleep for ++ * the longest period possible which is less than the delay required, ++ * then makes up the difference with a tight loop. ++ * ++ * @param[in] num_ms The number of milliseconds to delay for ++ * ++ * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] ++ */ ++cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms); ++ ++/** \} group_abstraction_rtos_time */ ++ ++#ifdef __cplusplus ++} /* extern "C" */ ++#endif ++#endif /* ifndef INCLUDED_CY_RTOS_INTERFACE_H_ */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_impl.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_impl.h +new file mode 100644 +index 0000000000..8b36a68844 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_impl.h +@@ -0,0 +1,77 @@ ++/***************************************************************************//** ++* \file cyabs_rtos_impl.h ++* ++* \brief ++* Internal definitions for RTOS abstraction layer ++* ++******************************************************************************** ++* \copyright ++* Copyright 2019-2020 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*/ ++ ++ ++#ifndef INCLUDED_CYABS_RTOS_IMPL_H_ ++#define INCLUDED_CYABS_RTOS_IMPL_H_ ++ ++#include "cmsis_os2.h" ++#include "rtx_os.h" ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++/****************************************************** ++* Constants ++******************************************************/ ++#define CY_RTOS_MIN_STACK_SIZE 300 /** Minimum stack size in bytes */ ++#define CY_RTOS_ALIGNMENT 0x00000008UL /** Minimum alignment for RTOS objects */ ++#define CY_RTOS_ALIGNMENT_MASK 0x00000007UL /** Mask for checking the alignment of created RTOS objects */ ++ ++ ++/****************************************************** ++* Type Definitions ++******************************************************/ ++ ++/* RTOS thread priority */ ++typedef enum ++{ ++ CY_RTOS_PRIORITY_MIN = osPriorityNone, ++ CY_RTOS_PRIORITY_LOW = osPriorityLow, ++ CY_RTOS_PRIORITY_BELOWNORMAL = osPriorityBelowNormal, ++ CY_RTOS_PRIORITY_NORMAL = osPriorityNormal, ++ CY_RTOS_PRIORITY_ABOVENORMAL = osPriorityAboveNormal, ++ CY_RTOS_PRIORITY_HIGH = osPriorityHigh, ++ CY_RTOS_PRIORITY_REALTIME = osPriorityRealtime, ++ CY_RTOS_PRIORITY_MAX = osPriorityRealtime7 ++} cy_thread_priority_t ; ++ ++typedef osThreadId_t cy_thread_t; /** CMSIS definition of a thread handle */ ++typedef void * cy_thread_arg_t; /** Argument passed to the entry function of a thread */ ++typedef osMutexId_t cy_mutex_t; /** CMSIS definition of a mutex */ ++typedef osSemaphoreId_t cy_semaphore_t; /** CMSIS definition of a semaphore */ ++typedef osEventFlagsId_t cy_event_t; /** CMSIS definition of an event */ ++typedef osMessageQueueId_t cy_queue_t; /** CMSIS definition of a message queue */ ++typedef osTimerId_t cy_timer_t; /** CMSIS definition of a timer */ ++typedef void * cy_timer_callback_arg_t; /** Argument passed to the timer callback function */ ++typedef uint32_t cy_time_t; /** Time in milliseconds */ ++typedef osStatus_t cy_rtos_error_t; /** CMSIS definition of a error status */ ++ ++#ifdef __cplusplus ++} /* extern "C" */ ++#endif ++#endif /* ifndef INCLUDED_CYABS_RTOS_IMPL_H_ */ ++ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c +new file mode 100644 +index 0000000000..37c70fe5c7 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c +@@ -0,0 +1,863 @@ ++/***************************************************************************//** ++* \file cyabs_rtos.c ++* ++* \brief ++* Implementation for CMSIS RTOS v2 abstraction ++* ++******************************************************************************** ++* \copyright ++* Copyright 2018-2020 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++#include ++#include ++#include ++ ++#if defined(__cplusplus) ++extern "C" { ++#endif ++ ++ ++/****************************************************** ++* Error Converter ++******************************************************/ ++ ++/* Last received error status */ ++static cy_rtos_error_t dbgErr; ++cy_rtos_error_t cy_rtos_last_error() { return dbgErr; } ++ ++/* Converts internal error type to external error type */ ++static cy_rslt_t error_converter(cy_rtos_error_t internalError) ++{ ++ cy_rslt_t value; ++ ++ switch (internalError) ++ { ++ case osOK: ++ value = CY_RSLT_SUCCESS; ++ break; ++ case osErrorTimeout: ++ value = CY_RTOS_TIMEOUT; ++ break; ++ case osErrorParameter: ++ value = CY_RTOS_BAD_PARAM; ++ break; ++ case osErrorNoMemory: ++ value = CY_RTOS_NO_MEMORY; ++ break; ++ case osError: ++ case osErrorResource: ++ case osErrorISR: ++ default: ++ value = CY_RTOS_GENERAL_ERROR; ++ break; ++ } ++ ++ /* Update the last known error status */ ++ dbgErr = internalError; ++ return value; ++} ++ ++ ++/****************************************************** ++* Threads ++******************************************************/ ++ ++cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, ++ const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ osThreadAttr_t attr; ++ ++ if (thread == NULL || stack_size < CY_RTOS_MIN_STACK_SIZE) ++ status = CY_RTOS_BAD_PARAM; ++ else if (stack != NULL && (0 != (((uint32_t)stack) & CY_RTOS_ALIGNMENT_MASK))) ++ status = CY_RTOS_ALIGNMENT_ERROR; ++ else ++ { ++ attr.name = name; ++ attr.attr_bits = osThreadJoinable; ++ attr.cb_size = osRtxThreadCbSize; ++ attr.stack_size = stack_size; ++ attr.priority = (osPriority_t)priority; ++ attr.tz_module = 0; ++ attr.reserved = 0; ++ ++ /* Allocate stack if NULL was passed */ ++ if ((uint32_t *)stack == NULL) ++ { ++ /* Note: 1 malloc so that it can be freed with 1 call when terminating */ ++ uint32_t cb_mem_pad = (~osRtxThreadCbSize + 1) & CY_RTOS_ALIGNMENT_MASK; ++ attr.cb_mem = malloc(osRtxThreadCbSize + cb_mem_pad + stack_size); ++ if (attr.cb_mem != NULL) ++ attr.stack_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxThreadCbSize + cb_mem_pad); ++ } ++ else ++ { ++ attr.cb_mem = malloc(osRtxThreadCbSize); ++ attr.stack_mem = stack; ++ } ++ ++ if (attr.cb_mem == NULL) ++ status = CY_RTOS_NO_MEMORY; ++ else ++ { ++ CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); ++ CY_ASSERT(((uint32_t)attr.stack_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); ++ *thread = osThreadNew((osThreadFunc_t)entry_function, arg, &attr); ++ CY_ASSERT((*thread == attr.cb_mem) || (*thread == NULL)); ++ status = (*thread == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; ++ } ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_exit_thread() ++{ ++ /* This does not have a return statement because the osThreadExit() function ++ * does not return so the return statement would be unreachable and causes a ++ * warning for IAR compiler. ++ */ ++ osThreadExit(); ++} ++ ++cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (thread == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osThreadTerminate(*thread); ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ ++ if ((thread == NULL) || (running == NULL)) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ *running = (osThreadGetState(*thread) == osThreadRunning) ? true : false; ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ ++ if ((thread == NULL) || (state == NULL)) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ switch (osThreadGetState(*thread)) ++ { ++ case osThreadInactive: ++ *state = CY_THREAD_STATE_INACTIVE; ++ break; ++ case osThreadReady: ++ *state = CY_THREAD_STATE_READY; ++ break; ++ case osThreadRunning: ++ *state = CY_THREAD_STATE_RUNNING; ++ break; ++ case osThreadBlocked: ++ *state = CY_THREAD_STATE_BLOCKED; ++ break; ++ case osThreadTerminated: ++ *state = CY_THREAD_STATE_TERMINATED; ++ break; ++ case osThreadError: ++ case osThreadReserved: ++ default: ++ *state = CY_THREAD_STATE_UNKNOWN; ++ break; ++ } ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (thread == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osThreadJoin(*thread); ++ status = error_converter(statusInternal); ++ ++ if (status == CY_RSLT_SUCCESS) ++ { ++ free(*thread); ++ *thread = NULL; ++ } ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ ++ if (thread == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ *thread = osThreadGetId(); ++ ++ return status; ++} ++ ++ ++/****************************************************** ++* Mutexes ++******************************************************/ ++ ++cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive) ++{ ++ cy_rslt_t status; ++ osMutexAttr_t attr; ++ ++ if (mutex == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ attr.name = NULL; ++ attr.attr_bits = osMutexPrioInherit; ++ if (recursive) ++ { ++ attr.attr_bits |= osMutexRecursive; ++ } ++ attr.cb_mem = malloc(osRtxMutexCbSize); ++ attr.cb_size = osRtxMutexCbSize; ++ ++ if (attr.cb_mem == NULL) ++ status = CY_RTOS_NO_MEMORY; ++ else ++ { ++ CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); ++ *mutex = osMutexNew(&attr); ++ CY_ASSERT((*mutex == attr.cb_mem) || (*mutex == NULL)); ++ status = (*mutex == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; ++ } ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (mutex == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osMutexAcquire(*mutex, timeout_ms); ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (mutex == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osMutexRelease(*mutex); ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (mutex == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osMutexDelete(*mutex); ++ status = error_converter(statusInternal); ++ ++ if (status == CY_RSLT_SUCCESS) ++ { ++ free(*mutex); ++ *mutex = NULL; ++ } ++ } ++ ++ return status; ++} ++ ++ ++/****************************************************** ++* Semaphores ++******************************************************/ ++ ++cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount) ++{ ++ cy_rslt_t status; ++ osSemaphoreAttr_t attr; ++ ++ if (semaphore == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ attr.name = NULL; ++ attr.attr_bits = 0U; ++ attr.cb_mem = malloc(osRtxSemaphoreCbSize); ++ attr.cb_size = osRtxSemaphoreCbSize; ++ ++ if (attr.cb_mem == NULL) ++ status = CY_RTOS_NO_MEMORY; ++ else ++ { ++ CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); ++ *semaphore = osSemaphoreNew(maxcount, initcount, &attr); ++ CY_ASSERT((*semaphore == attr.cb_mem) || (*semaphore == NULL)); ++ status = (*semaphore == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; ++ } ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ cy_rtos_error_t statusInternal; ++ ++ if (semaphore == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ /* Not allowed to be called in ISR if timeout != 0 */ ++ if ((!in_isr) || (in_isr && (timeout_ms == 0U))) ++ statusInternal = osSemaphoreAcquire(*semaphore, timeout_ms); ++ else ++ statusInternal = osErrorISR; ++ ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ cy_rtos_error_t statusInternal; ++ (void)in_isr; // Unused parameter in this implementation ++ ++ if (semaphore == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osSemaphoreRelease(*semaphore); ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count) ++{ ++ cy_rslt_t status; ++ if (semaphore == NULL || count == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ *count = osSemaphoreGetCount(*semaphore); ++ status = CY_RSLT_SUCCESS; ++ } ++ return status; ++} ++ ++cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (semaphore == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osSemaphoreDelete(*semaphore); ++ status = error_converter(statusInternal); ++ if (status == CY_RSLT_SUCCESS) ++ { ++ free(*semaphore); ++ *semaphore = NULL; ++ } ++ } ++ ++ return status; ++} ++ ++ ++/****************************************************** ++* Events ++******************************************************/ ++ ++#define CY_RTOS_EVENT_ERRORFLAG 0x80000000UL ++#define CY_RTOS_EVENT_FLAGS 0x7FFFFFFFUL ++ ++cy_rslt_t cy_rtos_init_event(cy_event_t *event) ++{ ++ cy_rslt_t status; ++ osEventFlagsAttr_t attr; ++ ++ if (event == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ attr.name = NULL; ++ attr.attr_bits = 0U; ++ attr.cb_mem = malloc(osRtxEventFlagsCbSize); ++ attr.cb_size = osRtxEventFlagsCbSize; ++ ++ if (attr.cb_mem == NULL) ++ status = CY_RTOS_NO_MEMORY; ++ else ++ { ++ CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); ++ *event = osEventFlagsNew(&attr); ++ CY_ASSERT((*event == attr.cb_mem) || (*event == NULL)); ++ status = (*event == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; ++ } ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ cy_rtos_error_t statusInternal; ++ (void)in_isr; // Unused parameter in this implementation ++ ++ if (event == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = (osStatus_t)osEventFlagsSet(*event, bits); ++ if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ cy_rtos_error_t statusInternal; ++ (void)in_isr; // Unused parameter in this implementation ++ ++ if (event == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = (osStatus_t)osEventFlagsClear(*event, bits); ++ if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ ++ if ((event == NULL) || (bits == NULL)) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ *bits = osEventFlagsGet(*event); ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ cy_rtos_error_t statusInternal; ++ uint32_t flagOption; ++ ++ if ((event == NULL) || (bits == NULL)) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ flagOption = (all) ? osFlagsWaitAll : osFlagsWaitAny; ++ if (!clear) ++ flagOption |= osFlagsNoClear; ++ ++ statusInternal = (osStatus_t)osEventFlagsWait(*event, *bits, flagOption, timeout); ++ if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) == 0UL) ++ *bits = statusInternal; ++ else ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_deinit_event(cy_event_t *event) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (event == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osEventFlagsDelete(*event); ++ status = error_converter(statusInternal); ++ if (status == CY_RSLT_SUCCESS) ++ { ++ free(*event); ++ *event = NULL; ++ } ++ } ++ ++ return status; ++} ++ ++ ++/****************************************************** ++* Queues ++******************************************************/ ++ ++cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize) ++{ ++ cy_rslt_t status; ++ osMessageQueueAttr_t attr; ++ ++ if (queue == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ attr.name = NULL; ++ attr.attr_bits = 0U; ++ attr.cb_size = osRtxMessageQueueCbSize; ++ uint32_t blockSize = ((itemsize + 3U) & ~3UL) + sizeof(osRtxMessage_t); ++ attr.mq_size = blockSize * length; ++ ++ /* Note: 1 malloc for both so that they can be freed with 1 call */ ++ uint32_t cb_mem_pad = (8 - (osRtxMessageQueueCbSize & 0x07)) & 0x07; ++ attr.cb_mem = malloc(osRtxMessageQueueCbSize + cb_mem_pad + attr.mq_size); ++ if (attr.cb_mem != NULL) ++ attr.mq_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxMessageQueueCbSize + cb_mem_pad); ++ ++ if (attr.cb_mem == NULL) ++ status = CY_RTOS_NO_MEMORY; ++ else ++ { ++ CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); ++ CY_ASSERT(((uint32_t)attr.mq_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); ++ *queue = osMessageQueueNew(length, itemsize, &attr); ++ CY_ASSERT((*queue == attr.cb_mem) || (*queue == NULL)); ++ status = (*queue == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; ++ } ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if ((queue == NULL) || (item_ptr == NULL)) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ /* Not allowed to be called in ISR if timeout != 0 */ ++ if ((!in_isr) || (in_isr && (timeout_ms == 0U))) ++ statusInternal = osMessageQueuePut(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); ++ else ++ statusInternal = osErrorISR; ++ ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if ((queue == NULL) || (item_ptr == NULL)) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ /* Not allowed to be called in ISR if timeout != 0 */ ++ if ((!in_isr) || (in_isr && (timeout_ms == 0U))) ++ statusInternal = osMessageQueueGet(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); ++ else ++ statusInternal = osErrorISR; ++ ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ ++ if ((queue == NULL) || (num_waiting == NULL)) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ *num_waiting = osMessageQueueGetCount(*queue); ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ ++ if ((queue == NULL) || (num_spaces == NULL)) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ *num_spaces = osMessageQueueGetSpace(*queue); ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (queue == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osMessageQueueReset(*queue); ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (queue == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osMessageQueueDelete(*queue); ++ status = error_converter(statusInternal); ++ ++ if (status == CY_RSLT_SUCCESS) ++ { ++ free(*queue); ++ *queue = NULL; ++ } ++ } ++ ++ return status; ++} ++ ++ ++/****************************************************** ++* Timers ++******************************************************/ ++ ++cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, ++ cy_timer_callback_t fun, cy_timer_callback_arg_t arg) ++{ ++ cy_rslt_t status; ++ osTimerAttr_t attr; ++ ++ if (timer == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ attr.name = NULL; ++ attr.attr_bits = 0U; ++ attr.cb_mem = malloc(osRtxTimerCbSize); ++ attr.cb_size = osRtxTimerCbSize; ++ ++ if (attr.cb_mem == NULL) ++ status = CY_RTOS_NO_MEMORY; ++ else ++ { ++ osTimerType_t osTriggerType = (CY_TIMER_TYPE_PERIODIC == type) ++ ? osTimerPeriodic ++ : osTimerOnce; ++ ++ CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); ++ *timer = osTimerNew( (osTimerFunc_t)fun, osTriggerType, (void *)arg, &attr ); ++ CY_ASSERT((*timer == attr.cb_mem) || (*timer == NULL)); ++ status = (*timer == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; ++ } ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (timer == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ /* Get Number of ticks per second */ ++ uint32_t tick_freq = osKernelGetTickFreq(); ++ ++ /* Convert ticks count to time in milliseconds */ ++ if (tick_freq != 0) ++ { ++ uint32_t ticks = ((num_ms * tick_freq) / 1000); ++ statusInternal = osTimerStart(*timer, ticks); ++ status = error_converter(statusInternal); ++ } ++ else ++ status = CY_RTOS_GENERAL_ERROR; ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (timer == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osTimerStop(*timer); ++ status = error_converter(statusInternal); ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ ++ if ((timer == NULL) || (state == NULL)) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ *state = osTimerIsRunning(*timer); ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ if (timer == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ statusInternal = osTimerDelete(*timer); ++ status = error_converter(statusInternal); ++ ++ if (status == CY_RSLT_SUCCESS) ++ { ++ free(*timer); ++ *timer = NULL; ++ } ++ } ++ ++ return status; ++} ++ ++ ++/****************************************************** ++* Time ++******************************************************/ ++ ++cy_rslt_t cy_rtos_get_time(cy_time_t *tval) ++{ ++ cy_rslt_t status = CY_RSLT_SUCCESS; ++ uint32_t tick_freq; ++ ++ if (tval == NULL) ++ status = CY_RTOS_BAD_PARAM; ++ else ++ { ++ /* Get Number of ticks per second */ ++ tick_freq = osKernelGetTickFreq(); ++ ++ /* Convert ticks count to time in milliseconds */ ++ if (tick_freq != 0) ++ *tval = (cy_time_t)((osKernelGetTickCount() * 1000LL) / tick_freq); ++ else ++ status = CY_RTOS_GENERAL_ERROR; ++ } ++ ++ return status; ++} ++ ++cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms) ++{ ++ cy_rslt_t status; ++ cy_rtos_error_t statusInternal; ++ ++ statusInternal = osDelay(num_ms); ++ status = error_converter(statusInternal); ++ ++ return status; ++} ++ ++ ++#if defined(__cplusplus) ++} ++#endif +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_gpio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_gpio.h +new file mode 100644 +index 0000000000..08d4e5bfb1 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_gpio.h +@@ -0,0 +1,247 @@ ++/***************************************************************************//** ++* \file cyhal_gpio.h ++* ++* \brief ++* Provides a high level interface for interacting with the GPIO on Cypress devices. ++* This interface abstracts out the chip specific details. If any chip specific ++* functionality is necessary, or performance is critical the low level functions ++* can be used directly. ++* ++******************************************************************************** ++* \copyright ++* Copyright 2018-2020 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++/** ++* \addtogroup group_hal_gpio GPIO (General Purpose Input Output) ++* \ingroup group_hal ++* \{ ++* High level interface for configuring and interacting with general purpose input/outputs (GPIO). ++* ++* The GPIO driver provides functions to configure and initialize GPIO, and to read and write data to the pin. ++* The driver also supports interrupt generation on GPIO signals with rising, falling or both edges. ++* ++* \note The APIs in this driver need not be used if a GPIO is to be used as an input or output of peripherals like I2C or PWM. ++* The respective peripheral's driver will utilize the GPIO interface to configure and initialize its GPIO pins. ++* ++* \section subsection_gpio_features Features ++* * Configurable GPIO pin direction - \ref cyhal_gpio_direction_t ++* * Configurable GPIO pin drive modes - \ref cyhal_gpio_drive_mode_t ++* * Configurable analog and digital characteristics ++* * Configurable edge-triggered interrupts and callback assignment on GPIO events - \ref cyhal_gpio_event_t ++* ++* \section subsection_gpio_quickstart Quick Start ++* \ref cyhal_gpio_init can be used for a simple GPIO initialization by providing the pin number (pin), pin direction (direction), ++* pin drive mode (drive_mode) and the initial value on the pin (init_val). ++* ++* \section subsection_gpio_sample_snippets Code Snippets ++* ++* \subsection subsection_gpio_snippet_1 Snippet 1: Reading value from GPIO ++* The following snippet initializes GPIO pin \ref P0_0 as an input with high impedance digital drive mode and initial value = false (low). A value is read ++* from the pin and stored to a uint8_t variable (read_val). ++ ++* \snippet gpio.c snippet_cyhal_gpio_read ++ ++* \subsection subsection_gpio_snippet_2 Snippet 2: Writing value to a GPIO ++* The following snippet initializes GPIO pin \ref P0_0 as an output pin with strong drive mode and initial value = false (low). ++* A value = true (high) is written to the output driver. ++ ++* \snippet gpio.c snippet_cyhal_gpio_write ++ ++* \subsection subsection_gpio_snippet_3 Snippet 3: Reconfiguring a GPIO ++* The following snippet shows how to reconfigure a GPIO pin during run-time using the firmware. The GPIO pin \ref P0_0 ++* is first initialized as an output pin with strong drive mode. The pin is then reconfigured as an input with high impedance digital drive mode. ++* \note \ref cyhal_gpio_configure only changes the direction and the drive_mode ++* of the pin. Previously set pin value is retained. ++* ++* \snippet gpio.c snippet_cyhal_gpio_reconfigure ++ ++* \subsection subsection_gpio_snippet_4 Snippet 4: Interrupts on GPIO events ++* GPIO events can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and ++* then the event needs to be enabled. ++** The following snippet initializes GPIO pin \ref P0_0 as an input pin. It registers a callback function and enables detection ++* of a falling edge event to trigger the callback. ++* \note If no argument needs to be passed to the callback function then a NULL can be passed during registering.
++* ++* \snippet gpio.c snippet_cyhal_gpio_interrupt ++*/ ++ ++#pragma once ++ ++#include ++#include ++#include "cy_result.h" ++#include "cyhal_hw_types.h" ++ ++#if defined(__cplusplus) ++extern "C" { ++#endif /* __cplusplus */ ++ ++ ++/******************************************************************************* ++* Defines ++*******************************************************************************/ ++ ++/** Integer representation of no connect pin (required to exist in all BSPs) */ ++#define CYHAL_NC_PIN_VALUE (NC) ++ ++/******************************************************************************* ++* Enumerations ++*******************************************************************************/ ++ ++/** Pin events */ ++typedef enum { ++ CYHAL_GPIO_IRQ_NONE = 0, /**< No interrupt */ ++ CYHAL_GPIO_IRQ_RISE = 1 << 0, /**< Interrupt on rising edge */ ++ CYHAL_GPIO_IRQ_FALL = 1 << 1, /**< Interrupt on falling edge */ ++ CYHAL_GPIO_IRQ_BOTH = (CYHAL_GPIO_IRQ_RISE | CYHAL_GPIO_IRQ_FALL), /**< Interrupt on both rising and falling edges */ ++} cyhal_gpio_event_t; ++ ++/** Pin direction */ ++typedef enum { ++ CYHAL_GPIO_DIR_INPUT, /**< Input pin */ ++ CYHAL_GPIO_DIR_OUTPUT, /**< Output pin */ ++ CYHAL_GPIO_DIR_BIDIRECTIONAL, /**< Input and output pin */ ++} cyhal_gpio_direction_t; ++ ++/** Pin drive mode */ ++ ++/** \note When the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_PULL_NONE , ++ * it is set to CYHAL_GPIO_DRIVE_STRONG if the direction ++ * of the pin is CYHAL_GPIO_DIR_OUTPUT or CYHAL_GPIO_DIR_BIDIRECTIONAL. ++ * If not, the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_NONE. ++ */ ++typedef enum { ++ CYHAL_GPIO_DRIVE_NONE, /**< Digital Hi-Z. Input only. Input init value(s): 0 or 1 */ ++ CYHAL_GPIO_DRIVE_ANALOG, /**< Analog Hi-Z. Use only for analog purpose */ ++ CYHAL_GPIO_DRIVE_PULLUP, /**< Pull-up resistor. Input and output. Input init value(s): 1, output value(s): 0 */ ++ CYHAL_GPIO_DRIVE_PULLDOWN, /**< Pull-down resistor. Input and output. Input init value(s): 0, output value(s): 1 */ ++ CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW, /**< Open-drain, Drives Low. Input and output. Input init value(s): 1, output value(s): 0 */ ++ CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH, /**< Open-drain, Drives High. Input and output. Input init value(s): 0, output value(s): 1 */ ++ CYHAL_GPIO_DRIVE_STRONG, /**< Strong output. Output only. Output init value(s): 0 or 1 */ ++ CYHAL_GPIO_DRIVE_PULLUPDOWN, /**< Pull-up and pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ ++ CYHAL_GPIO_DRIVE_PULL_NONE, /**< No Pull-up or pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ ++} cyhal_gpio_drive_mode_t; ++ ++/** GPIO callback function type */ ++typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event_t event); ++ ++/******************************************************************************* ++* Functions ++*******************************************************************************/ ++ ++/** Initialize the GPIO pin
++ * See \ref subsection_gpio_snippet_1. ++ * ++ * @param[in] pin The GPIO pin to initialize ++ * @param[in] direction The pin direction ++ * @param[in] drive_mode The pin drive mode ++ * @param[in] init_val Initial value on the pin ++ * ++ * @return The status of the init request ++ * ++ * Guidance for using gpio drive modes ( \ref cyhal_gpio_drive_mode_t for details). ++ * For default use drive modes: ++ * Input GPIO direction - \ref CYHAL_GPIO_DRIVE_NONE ++ * Output GPIO direction - \ref CYHAL_GPIO_DRIVE_STRONG ++ * Bidirectional GPIO - \ref CYHAL_GPIO_DRIVE_PULLUPDOWN ++ * \warning Don't use \ref CYHAL_GPIO_DRIVE_STRONG for input GPIO direction. It may cause an overcurrent issue. ++ */ ++cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode, bool init_val); ++ ++/** Uninitialize the gpio peripheral and the cyhal_gpio_t object ++ * ++ * @param[in] pin Pin number ++ */ ++void cyhal_gpio_free(cyhal_gpio_t pin); ++ ++/** Configure the GPIO pin
++ * See \ref subsection_gpio_snippet_3. ++ * ++ * @param[in] pin The GPIO pin ++ * @param[in] direction The pin direction ++ * @param[in] drive_mode The pin drive mode ++ * ++ * @return The status of the configure request ++ */ ++cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode); ++ ++/** Set the output value for the pin. This only works for output & in_out pins.
++ * See \ref subsection_gpio_snippet_2. ++ * ++ * @param[in] pin The GPIO object ++ * @param[in] value The value to be set (high = true, low = false) ++ */ ++void cyhal_gpio_write(cyhal_gpio_t pin, bool value); ++ ++/** Read the input value. This only works for \ref CYHAL_GPIO_DIR_INPUT & \ref CYHAL_GPIO_DIR_BIDIRECTIONAL pins.
++ * See \ref subsection_gpio_snippet_1. ++ * ++ * @param[in] pin The GPIO object ++ * @return The value of the IO (true = high, false = low) ++ */ ++bool cyhal_gpio_read(cyhal_gpio_t pin); ++ ++/** Toggle the output value
++ * See \ref subsection_gpio_snippet_4. ++ * @param[in] pin The GPIO object ++ */ ++void cyhal_gpio_toggle(cyhal_gpio_t pin); ++ ++/** Register/clear a callback handler for pin events
++ * ++ * This function will be called when one of the events enabled by \ref cyhal_gpio_enable_event occurs. ++ * ++ * See \ref subsection_gpio_snippet_4. ++ * ++ * @param[in] pin The pin number ++ * @param[in] callback The function to call when the specified event happens. Pass NULL to unregister the handler. ++ * @param[in] callback_arg Generic argument that will be provided to the callback when called, can be NULL ++ */ ++void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg); ++ ++/** Enable or Disable the specified GPIO event
++ * ++ * When an enabled event occurs, the function specified by \ref cyhal_gpio_register_callback will be called. ++ * ++ * See \ref subsection_gpio_snippet_4. ++ * ++ * @param[in] pin The GPIO object ++ * @param[in] event The GPIO event ++ * @param[in] intr_priority The priority for NVIC interrupt events ++ * @param[in] enable True to turn on interrupts, False to turn off ++ */ ++void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable); ++ ++/******************************************************************************* ++* Backward compatibility macro. The following code is DEPRECATED and must ++* not be used in new projects ++*******************************************************************************/ ++/** \cond INTERNAL */ ++#define cyhal_gpio_register_irq(pin, priority, handler, handler_arg) cyhal_gpio_register_callback(pin, handler, handler_arg) ++#define cyhal_gpio_irq_enable(pin, event, enable) cyhal_gpio_enable_event(pin, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) ++typedef cyhal_gpio_event_t cyhal_gpio_irq_event_t; ++/** \endcond */ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#ifdef CYHAL_GPIO_IMPL_HEADER ++#include CYHAL_GPIO_IMPL_HEADER ++#endif /* CYHAL_GPIO_IMPL_HEADER */ ++ ++/** \} group_hal_gpio */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_sdio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_sdio.h +new file mode 100644 +index 0000000000..d5600efd99 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_sdio.h +@@ -0,0 +1,366 @@ ++/***************************************************************************//** ++* \file cyhal_sdio.h ++* ++* \brief ++* Provides a high level interface for interacting with the Cypress SDIO interface. ++* This interface abstracts out the chip specific details. If any chip specific ++* functionality is necessary, or performance is critical the low level functions ++* can be used directly. ++* ++******************************************************************************** ++* \copyright ++* Copyright 2018-2020 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++/** ++* \addtogroup group_hal_sdio SDIO (Secure Digital Input Output) ++* \ingroup group_hal ++* \{ ++* High level interface to the Secure Digital Input Output (SDIO). ++* ++* This driver allows commands to be sent over the SDIO bus; the supported commands ++* can be found in \ref cyhal_sdio_command_t. Bulk data transfer is also supported ++* via cyhal_sdio_bulk_transfer(). ++* ++* The SDIO protocol is an extension of the SD ++* interface for general I/O functions. Refer to the SD Specifications Part 1 SDIO ++* Specifications Version 4.10 for more information on the SDIO protocol and specifications. ++* ++* ++* \section subsection_sdio_features Features ++* * Supports 4-bit interface ++* * Supports Ultra High Speed (UHS-I) mode ++* * Supports Default Speed (DS), High Speed (HS), SDR12, SDR25 and SDR50 speed modes ++* * Supports SDIO card interrupts in both 1-bit and 4-bit modes ++* * Supports Standard capacity (SDSC), High capacity (SDHC) and Extended capacity (SDXC) memory ++* ++* \section subsection_sdio_quickstart Quick Start ++* ++* \ref cyhal_sdio_init initializes the SDIO peripheral and passes a pointer to the SDIO block through the **obj** object of type \ref cyhal_sdio_t. ++* ++* \section subsection_sdio_code_snippets Code Snippets ++* ++* \subsection subsection_sdio_use_case_1 Snippet1: Simple SDIO Initialization example ++* The following snippet shows how to initialize the SDIO interface with a pre-defined configuration ++* ++* \snippet sdio.c snippet_cyhal_sdio_simple_init ++* ++* \subsection subsection_sdio_use_case_2 Snippet2: Configure Interrupt ++* The following snippet shows how to configure an interrupt and handle specific events. Refer \ref cyhal_sdio_event_t for different types of events. ++* ++* \snippet sdio.c snippet_cyhal_sdio_interrupt_callback ++* ++* \subsection subsection_sdio_use_case_3 Snippet3: Sending Commands ++* The following snippet shows how to send a particular command. Some steps of the card initialization have been provided for reference. Refer \ref cyhal_sdio_command_t for different commands. ++* ++* \snippet sdio.c snippet_cyhal_sdio_send_command ++* ++* \subsection subsection_sdio_use_case_4 Snippet4: Bulk Data Transfer ++* The following snippet shows how to start a bulk data transfer. ++* ++* \snippet sdio.c snippet_cyhal_sdio_bulk_transfer ++* ++* \subsection subsection_sdio_use_case_5 Snippet5: Async Data Transfer ++* ++* The following snippet shows how to start an async data transfer. ++* \snippet sdio.c snippet_cyhal_sdio_async_transfer ++*/ ++ ++#pragma once ++ ++#include ++#include ++#include "cy_result.h" ++#include "cyhal_hw_types.h" ++ ++#if defined(__cplusplus) ++extern "C" { ++#endif ++ ++/******************************************************************************* ++* Defines ++*******************************************************************************/ ++ ++#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ ++#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ ++#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/ ++#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/ ++#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/ ++#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/ ++#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/ ++#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/ ++#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/ ++ ++#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */ ++#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */ ++#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */ ++#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */ ++#define CYHAL_SDIO_CANCELED (0x1000) /**< Operation canceled */ ++#define CYHAL_SDIO_PM_PENDING_ERROR (0x2000) /**< Transfer cannot be initiated after power mode transition allowed.*/ ++ ++/* HAL return value defines */ ++ ++/** \addtogroup group_hal_results_sdio SDIO HAL Results ++ * SDIO specific return codes ++ * \ingroup group_hal_results ++ * \{ *//** ++ */ ++ ++/** Incorrect parameter value define */ ++#define CYHAL_SDIO_RSLT_ERR_BAD_PARAM \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_BAD_ARGUMENT)) ++/** Clock initialization error define */ ++#define CYHAL_SDIO_RSLT_ERR_CLOCK \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CLOCK_ERROR)) ++/** Semaphore not initiated error define */ ++#define CYHAL_SDIO_RSLT_ERR_SEMA_NOT_INITED \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_SEMA_NOT_INITED)) ++/** Error define based on SDIO lower function return value */ ++#define CYHAL_SDIO_RSLT_ERR_FUNC_RET(retVal) \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, ((uint16_t)retVal))) ++/** Define to indicate canceled operation */ ++#define CYHAL_SDIO_RSLT_CANCELED \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CANCELED)) ++/** Transfers are not allowed after the SDIO block has allowed power mode transition. */ ++#define CYHAL_SDIO_RSLT_ERR_PM_PENDING \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_PM_PENDING_ERROR)) ++ ++/** ++ * \} ++ */ ++ ++ ++/******************************************************************************* ++* Enumerations ++*******************************************************************************/ ++ ++/** Commands that can be issued */ ++typedef enum ++{ ++ CYHAL_SDIO_CMD_GO_IDLE_STATE = 0, //!< Go to idle state ++ CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR = 3, //!< Send a relative address ++ CYHAL_SDIO_CMD_IO_SEND_OP_COND = 5, //!< Send an OP IO ++ CYHAL_SDIO_CMD_SELECT_CARD = 7, //!< Send a card select ++ CYHAL_SDIO_CMD_GO_INACTIVE_STATE = 15, //!< Go to inactive state ++ CYHAL_SDIO_CMD_IO_RW_DIRECT = 52, //!< Perform a direct read/write ++ CYHAL_SDIO_CMD_IO_RW_EXTENDED = 53, //!< Perform an extended read/write ++} cyhal_sdio_command_t; ++ ++/** Types of transfer that can be performed */ ++typedef enum ++{ ++ CYHAL_READ, //!< Read from the card ++ CYHAL_WRITE //!< Write to the card ++} cyhal_transfer_t; ++ ++/** Types of events that could be asserted by SDIO */ ++typedef enum { ++ /* Interrupt-based thread events */ ++ CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!< Command Complete ++ CYHAL_SDIO_XFER_COMPLETE = 0x00002, //!< Host read/write transfer is complete ++ CYHAL_SDIO_BGAP_EVENT = 0x00004, //!< This bit is set when both read/write transaction is stopped ++ CYHAL_SDIO_DMA_INTERRUPT = 0x00008, //!< Host controller detects an SDMA Buffer Boundary during transfer ++ CYHAL_SDIO_BUF_WR_READY = 0x00010, //!< This bit is set if the Buffer Write Enable changes from 0 to 1 ++ CYHAL_SDIO_BUF_RD_READY = 0x00020, //!< This bit is set if the Buffer Read Enable changes from 0 to 1 ++ CYHAL_SDIO_CARD_INSERTION = 0x00040, //!< This bit is set if the Card Inserted in the Present State ++ CYHAL_SDIO_CARD_REMOVAL = 0x00080, //!< This bit is set if the Card Inserted in the Present State ++ CYHAL_SDIO_CARD_INTERRUPT = 0x00100, //!< The synchronized value of the DAT[1] interrupt input for SD mode ++ CYHAL_SDIO_INT_A = 0x00200, //!< Reserved: set to 0 ++ CYHAL_SDIO_INT_B = 0x00400, //!< Reserved: set to 0 ++ CYHAL_SDIO_INT_C = 0x00800, //!< Reserved: set to 0 ++ CYHAL_SDIO_RE_TUNE_EVENT = 0x01000, //!< Reserved: set to 0 ++ CYHAL_SDIO_FX_EVENT = 0x02000, //!< This status is set when R[14] of response register is set to 1 ++ CYHAL_SDIO_CQE_EVENT = 0x04000, //!< This status is set if Command Queuing/Crypto event has occurred ++ CYHAL_SDIO_ERR_INTERRUPT = 0x08000, //!< If any of the bits in the Error Interrupt Status register are set ++ ++ /* Non-interrupt-based thread events */ ++ CYHAL_SDIO_GOING_DOWN = 0x10000, //!< The interface is going away (eg: powering down for some period of time) ++ CYHAL_SDIO_COMING_UP = 0x20000, //!< The interface is back up (eg: came back from a low power state) ++ ++ CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF, //!< Is used to enable/disable all interrupts events ++} cyhal_sdio_event_t; ++ ++ ++/******************************************************************************* ++* Data Structures ++*******************************************************************************/ ++ ++/** @brief SDIO controller initial configuration */ ++typedef struct ++{ ++ uint32_t frequencyhal_hz; //!< Clock frequency, in hertz ++ uint16_t block_size; //!< Block size ++} cyhal_sdio_cfg_t; ++ ++/** Callback for SDIO events */ ++typedef void (*cyhal_sdio_event_callback_t)(void *callback_arg, cyhal_sdio_event_t event); ++ ++ ++/******************************************************************************* ++* Data Structures ++*******************************************************************************/ ++/** Initialize the SDIO peripheral ++ * ++ * @param[out] obj Pointer to an SDIO object. ++ * The caller must allocate the memory for this object but the init ++ * function will initialize its contents. ++ * @param[out] clk The pin connected to the clk signal ++ * @param[in] cmd The pin connected to the command signal ++ * @param[in] data0 The pin connected to the data0 signal ++ * @param[in] data1 The pin connected to the data1 signal ++ * @param[in] data2 The pin connected to the data2 signal ++ * @param[in] data3 The pin connected to the data3 signal ++ * @return The status of the init request ++ * ++ * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_1 for more information. ++ */ ++cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3); ++ ++/** Release the SDIO block. ++ * ++ * @param[in,out] obj The SDIO object ++ */ ++void cyhal_sdio_free(cyhal_sdio_t *obj); ++ ++/** Configure the SDIO block with required parameters. Refer \ref cyhal_sdio_cfg_t for more information. ++ * ++ * @param[in,out] obj The SDIO object ++ * @param[in] config The SDIO configuration to apply ++ * @return The status of the configure request. ++ * ++ * Returns \ref CY_RSLT_SUCCESS on successful operation. ++ */ ++cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config); ++ ++/** Sends command to the SDIO device. See \ref cyhal_sdio_command_t for list of available commands. ++ * ++ * This will block until the command is completed. ++ * ++ * @param[in,out] obj The SDIO object ++ * @param[in] direction The direction of transfer (read/write) ++ * @param[in] command The command to send to the SDIO device ++ * @param[in] argument The argument to the command ++ * @param[out] response The response from the SDIO device ++ * @return The status of the command transfer. ++ * ++ * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_3 for more information. ++ */ ++cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t* response); ++ ++/** Performs a bulk data transfer. Sends \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command (CMD=53) which allows writing and reading of a large number of I/O registers with a single command. ++ * ++ * This will block until the transfer is completed. ++ * ++ * @param[in,out] obj The SDIO object ++ * @param[in] direction The direction of transfer (read/write) ++ * @param[in] argument The argument to the command ++ * @param[in] data The data to send to the SDIO device. A bulk transfer is done in block ++ * size (default: 64 bytes) chunks for better performance. Therefore, ++ * the size of the data buffer passed into this function must be at least ++ * `length` bytes and a multiple of the block size. For example, when ++ * requesting to read 100 bytes of data with a block size 64 bytes, the ++ * data buffer needs to be at least 128 bytes. The first 100 bytes of data ++ * in the buffer will be the requested data. ++ * @param[in] length The number of bytes to send ++ * @param[out] response The response from the SDIO device ++ * @return The status of the bulk transfer operation. ++ * ++ * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_4 for more information. ++ */ ++cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response); ++ ++/** Performs a bulk asynchronous data transfer by issuing the \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command(CMD=53) to the SDIO block. ++ * After exiting this function the \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are not asserted. ++ * ++ * To complete the asynchronous transfer, call \ref cyhal_sdio_is_busy() ++ * until it returns false. ++ * The \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are enabled ++ * after the asynchronous transfer is complete and in the condition they were ++ * enabled in before the transfer operation started. Handle these events in the interrupt callback. ++ * ++ * When the transfer is complete, the \ref CYHAL_SDIO_XFER_COMPLETE event will be raised. ++ * See \ref cyhal_sdio_register_callback and \ref cyhal_sdio_enable_event. ++ * ++ * @param[in,out] obj The SDIO object ++ * @param[in] direction The direction of transfer (read/write) ++ * @param[in] argument The argument to the command ++ * @param[in] data The data to send to the SDIO device ++ * @param[in] length The number of bytes to send ++ * @return The status of the async tranfer operation. ++ * ++ * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_5 for more information. ++ */ ++cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length); ++ ++/** Checks if the specified SDIO is in use ++ * ++ * @param[in] obj The SDIO peripheral to check ++ * @return true if SDIO is in use. false, otherwise. ++ */ ++bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj); ++ ++/** Abort an SDIO transfer ++ * ++ * @param[in] obj The SDIO peripheral to stop ++ * @return The status of the abort_async request. ++ * ++ * Returns \ref CY_RSLT_SUCCESS on successful operation. ++ */ ++cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj); ++ ++/** Register an SDIO event callback to be invoked when the event is triggered. ++ * ++ * This function will be called when one of the events enabled by \ref cyhal_sdio_enable_event occurs. ++ * ++ * @param[in] obj The SDIO object ++ * @param[in] callback The callback function which will be invoked when the event triggers ++ * @param[in] callback_arg Generic argument that will be provided to the callback when executed ++ * ++ * Refer \ref subsection_sdio_use_case_2 for more implementation. ++ */ ++void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t callback, void *callback_arg); ++ ++/** Enables callbacks to be triggered for specified SDIO events. Refer \ref cyhal_sdio_event_t for all events. ++ * ++ * @param[in] obj The SDIO object ++ * @param[in] event The SDIO event type ++ * @param[in] intr_priority The priority for NVIC interrupt events ++ * @param[in] enable Set to true to enable events, or false to disable them ++ * ++ * Refer \ref subsection_sdio_use_case_2 for more information. ++ */ ++void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intr_priority, bool enable); ++ ++/******************************************************************************* ++* Backward compatibility macro. The following code is DEPRECATED and must ++* not be used in new projects ++*******************************************************************************/ ++/** \cond INTERNAL */ ++#define cyhal_sdio_register_irq cyhal_sdio_register_callback ++#define cyhal_sdio_irq_enable(obj, event, enable) cyhal_sdio_enable_event(obj, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) ++typedef cyhal_sdio_event_t cyhal_sdio_irq_event_t; ++typedef cyhal_sdio_event_callback_t cyhal_sdio_irq_handler_t; ++/** \endcond */ ++ ++#if defined(__cplusplus) ++} ++#endif ++ ++#ifdef CYHAL_SDIO_IMPL_HEADER ++#include CYHAL_SDIO_IMPL_HEADER ++#endif /* CYHAL_SDIO_IMPL_HEADER */ ++ ++/** \} group_hal_sdio */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_spi.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_spi.h +new file mode 100644 +index 0000000000..f5ba47669f +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_spi.h +@@ -0,0 +1,383 @@ ++/***************************************************************************//** ++* \file cyhal_spi.h ++* ++* \brief ++* Provides a high level interface for interacting with the Cypress SPI. ++* This interface abstracts out the chip specific details. If any chip specific ++* functionality is necessary, or performance is critical the low level functions ++* can be used directly. ++* ++******************************************************************************** ++* \copyright ++* Copyright 2018-2020 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++/** ++* \addtogroup group_hal_spi SPI (Serial Peripheral Interface) ++* \ingroup group_hal ++* \{ ++* High level interface for interacting with the Serial Peripheral Interface (SPI). ++* ++* The SPI protocol is a synchronous serial interface protocol. Devices operate ++* in either master or slave mode. The master initiates the data transfer. ++* ++* Motorola SPI modes 0, 1, 2, and 3 are supported, with either MSB or LSB first. ++* The operating mode and data frame size can be configured via \ref cyhal_spi_cfg_t. ++* ++* \section section_spi_features Features ++* * Supports master and slave functionality. ++* * Supports Motorola modes - 0, 1, 2 and 3 - \ref cyhal_spi_mode_t ++* * MSb or LSb first shift direction - \ref cyhal_spi_mode_t ++* * Master supports up to four slave select lines ++* * Supports data frame size of 8 or 16 bits ++* * Configurable interrupt and callback assignment on SPI events: ++* Data transfer to FIFO complete, Transfer complete and Transmission error - \ref cyhal_spi_event_t ++* * Supports changing baud rate of the transaction in run time. ++* * Provides functions to send/receive a single byte or block of data. ++* ++* \section section_spi_quickstart Quick Start ++* ++* Initialise a SPI master or slave interface using \ref cyhal_spi_init() and provide the SPI pins (mosi, miso, sclk, ssel), ++* number of bits per frame (data_bits) and SPI Motorola mode. The data rate can be set using \ref cyhal_spi_set_frequency().
++* See \ref section_spi_snippets for code snippets to send or receive the data. ++* ++* \section section_spi_snippets Code snippets ++* ++* \subsection subsection_spi_snippet_1 Snippet 1: SPI Master - Single byte transfer operation (Read and Write) ++* The following code snippet initializes an SPI Master interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency(). ++* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv(). ++* \snippet spi.c snippet_cyhal_spi_master_byte_operation ++* ++* \subsection subsection_spi_snippet_2 Snippet 2: SPI Slave - Single byte transfer operation (Read and Write) ++* The following code snippet initializes an SPI Slave interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency. ++* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv. ++* \snippet spi.c snippet_cyhal_spi_slave_byte_operation ++* ++* \subsection subsection_spi_snippet_3 Snippet 3: SPI Block Data transfer ++* The following snippet sends and receives an array of data in a single SPI transaction using \ref cyhal_spi_transfer(). The example ++* uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction. ++* \snippet spi.c snippet_cyhal_spi_block_data_transfer ++* ++* \subsection subsection_spi_snippet_4 Snippet 4: Interrupts on SPI events ++* SPI interrupt events ( \ref cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function. ++* The callback function needs to be first registered and then the event needs to be enabled. ++* The following snippet initialises a SPI master to perform a block transfer using \ref cyhal_spi_transfer_async(). This is a non-blocking function. ++* A callback function is registered using \ref cyhal_spi_register_callback to notify whenever the SPI transfer is complete. ++* \snippet spi.c snippet_cyhal_spi_interrupt_callback_events ++ ++* \section subsection_spi_moreinfor More Information ++* ++* * mtb-example-psoc6-spi-master: This example project demonstrates ++* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave. ++* ++*/ ++ ++#pragma once ++ ++#include ++#include ++#include "cy_result.h" ++#include "cyhal_hw_types.h" ++ ++#if defined(__cplusplus) ++extern "C" { ++#endif ++ ++/** \addtogroup group_hal_results_spi SPI HAL Results ++ * SPI specific return codes ++ * \ingroup group_hal_results ++ * \{ *//** ++ */ ++ ++/** Bad argument */ ++#define CYHAL_SPI_RSLT_BAD_ARGUMENT \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0)) ++/** Failed to initialize SPI clock */ ++#define CYHAL_SPI_RSLT_CLOCK_ERROR \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 1)) ++/** Failed to Transfer SPI data */ ++#define CYHAL_SPI_RSLT_TRANSFER_ERROR \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 2)) ++/** Provided clock is not supported by SPI */ ++#define CYHAL_SPI_RSLT_CLOCK_NOT_SUPPORTED \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 3)) ++/** Provided PIN configuration is not supported by SPI */ ++#define CYHAL_SPI_RSLT_PIN_CONFIG_NOT_SUPPORTED \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 5)) ++/** Provided PIN configuration is not supported by SPI */ ++#define CYHAL_SPI_RSLT_INVALID_PIN_API_NOT_SUPPORTED \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 6)) ++/** The requested resource type is invalid */ ++#define CYHAL_SPI_RSLT_ERR_INVALID_PIN \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 7)) ++/** Cannot configure SSEL signal */ ++#define CYHAL_SPI_RSLT_ERR_CANNOT_CONFIG_SSEL \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 8)) ++/** Cannot switch SSEL - device is busy or incorrect pin provided */ ++#define CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL \ ++ (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 9)) ++ ++/** ++ * \} ++ */ ++ ++/** Compatibility define for cyhal_spi_set_frequency. */ ++#define cyhal_spi_frequency cyhal_spi_set_frequency ++ ++/** SPI interrupt triggers */ ++typedef enum { ++ /** All transfer data has been moved into data FIFO */ ++ CYHAL_SPI_IRQ_DATA_IN_FIFO = 1 << 1, ++ /** Transfer complete. */ ++ CYHAL_SPI_IRQ_DONE = 1 << 2, ++ /** An error occurred while transferring data */ ++ CYHAL_SPI_IRQ_ERROR = 1 << 3, ++} cyhal_spi_event_t; ++ ++/** SPI Slave Select polarity */ ++typedef enum { ++ /** SSEL signal is active low */ ++ CYHAL_SPI_SSEL_ACTIVE_LOW = 0, ++ /** SSEL signal is active high */ ++ CYHAL_SPI_SSEL_ACTIVE_HIGH = 1, ++} cyhal_spi_ssel_polarity_t; ++ ++/** Handler for SPI interrupts */ ++typedef void (*cyhal_spi_event_callback_t)(void *callback_arg, cyhal_spi_event_t event); ++ ++/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the LSB is sent first. */ ++#define CYHAL_SPI_MODE_FLAG_LSB (0x01u) ++/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPHA=1. */ ++#define CYHAL_SPI_MODE_FLAG_CPHA (0x02u) ++/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPOL=1. */ ++#define CYHAL_SPI_MODE_FLAG_CPOL (0x04u) ++/** Creates a \ref cyhal_spi_mode_t value given the cpol, cpha, lsb values. */ ++#define CYHAL_SPI_MODE(cpol, cpha, lsb) (((cpol > 0) ? CYHAL_SPI_MODE_FLAG_CPOL : 0) | \ ++ ((cpha > 0) ? CYHAL_SPI_MODE_FLAG_CPHA : 0) | \ ++ (( lsb > 0) ? CYHAL_SPI_MODE_FLAG_LSB : 0)) ++ ++/** SPI operating modes */ ++typedef enum ++{ ++ /** Standard motorola SPI CPOL=0, CPHA=0 with MSB first operation */ ++ CYHAL_SPI_MODE_00_MSB = CYHAL_SPI_MODE(0, 0, 0), ++ /** Standard motorola SPI CPOL=0, CPHA=0 with LSB first operation */ ++ CYHAL_SPI_MODE_00_LSB = CYHAL_SPI_MODE(0, 0, 1), ++ /** Standard motorola SPI CPOL=0, CPHA=1 with MSB first operation */ ++ CYHAL_SPI_MODE_01_MSB = CYHAL_SPI_MODE(0, 1, 0), ++ /** Standard motorola SPI CPOL=0, CPHA=1 with LSB first operation */ ++ CYHAL_SPI_MODE_01_LSB = CYHAL_SPI_MODE(0, 1, 1), ++ /** Standard motorola SPI CPOL=1, CPHA=0 with MSB first operation */ ++ CYHAL_SPI_MODE_10_MSB = CYHAL_SPI_MODE(1, 0, 0), ++ /** Standard motorola SPI CPOL=1, CPHA=0 with LSB first operation */ ++ CYHAL_SPI_MODE_10_LSB = CYHAL_SPI_MODE(1, 0, 1), ++ /** Standard motorola SPI CPOL=1, CPHA=1 with MSB first operation */ ++ CYHAL_SPI_MODE_11_MSB = CYHAL_SPI_MODE(1, 1, 0), ++ /** Standard motorola SPI CPOL=1, CPHA=1 with LSB first operation */ ++ CYHAL_SPI_MODE_11_LSB = CYHAL_SPI_MODE(1, 1, 1), ++} cyhal_spi_mode_t; ++ ++/** @brief Initial SPI configuration. */ ++typedef struct ++{ ++ cyhal_spi_mode_t mode; //!< The operating mode ++ uint8_t data_bits; //!< The number of bits per transfer ++ bool is_slave; //!< Whether the peripheral is operating as slave or master ++} cyhal_spi_cfg_t; ++ ++/** Initialize the SPI peripheral ++ * ++ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral ++ * @param[out] obj Pointer to a SPI object. The caller must allocate the memory ++ * for this object but the init function will initialize its contents. ++ * @param[in] mosi The pin to use for MOSI ++ * @note At least MOSI or MISO pin should be non-NC ++ * @param[in] miso The pin to use for MISO ++ * @note At least MOSI or MISO pin should be non-NC ++ * @param[in] sclk The pin to use for SCLK ++ * @note This pin cannot be NC ++ * @param[in] ssel The pin to use for SSEL ++ * @note Provided pin will be configured for \ref CYHAL_SPI_SSEL_ACTIVE_LOW polarity and set as active. This can be changed ++ * (as well as additional ssel pins can be added) by \ref cyhal_spi_slave_select_config and \ref cyhal_spi_select_active_ssel ++ * functions. This pin can be NC. ++ * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated ++ * @param[in] bits The number of bits per frame ++ * @note bits should be 8 or 16 ++ * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) ++ * @param[in] is_slave false for master mode or true for slave mode operation ++ * @return The status of the init request ++ */ ++cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, cyhal_gpio_t sclk, cyhal_gpio_t ssel, ++ const cyhal_clock_t *clk, uint8_t bits, cyhal_spi_mode_t mode, bool is_slave); ++ ++/** Release a SPI object ++ * ++ * Return the peripheral, pins and clock owned by the SPI object to their reset state ++ * @param[in,out] obj The SPI object to deinitialize ++ */ ++void cyhal_spi_free(cyhal_spi_t *obj); ++ ++/** Set the SPI baud rate ++ * ++ * Actual frequency may differ from the desired frequency due to available dividers and bus clock ++ * Configures the SPI peripheral's baud rate ++ * @param[in,out] obj The SPI object to configure ++ * @param[in] hz The baud rate in Hz ++ * @return The status of the set_frequency request ++ */ ++cy_rslt_t cyhal_spi_set_frequency(cyhal_spi_t *obj, uint32_t hz); ++ ++/** Configures provided ssel pin to work as SPI slave select with specified polarity. ++ * ++ * Multiple pins can be configured as SPI slave select pins. Please refer to device datasheet for details. Switching ++ * between configured slave select pins is done by \ref cyhal_spi_select_active_ssel function. ++ * Unless modified with this function, the SSEL pin provided as part of \ref cyhal_spi_init is the default. ++ * @param[in] obj The SPI object to add slave select for ++ * @param[in] ssel Slave select pin to be added ++ * @param[in] polarity Polarity of slave select ++ * @return The status of ssel pin configuration ++ */ ++cy_rslt_t cyhal_spi_slave_select_config(cyhal_spi_t *obj, cyhal_gpio_t ssel, cyhal_spi_ssel_polarity_t polarity); ++ ++/** Selects an active slave select line from one of available. ++ * ++ * This function is applicable for the master and slave. ++ * SSEL pin should be configured by \ref cyhal_spi_slave_select_config or \ref cyhal_spi_init functions prior ++ * to selecting it as active. The active slave select line will automatically be toggled as part of any transfer. ++ * @param[in] obj The SPI object for switching ++ * @param[in] ssel Slave select pin to be set as active ++ * @return CY_RSLT_SUCCESS if slave select was switched successfully, otherwise - CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL ++ */ ++cy_rslt_t cyhal_spi_select_active_ssel(cyhal_spi_t *obj, cyhal_gpio_t ssel); ++ ++/** Synchronously get a received value out of the SPI receive buffer ++ * ++ * In Master mode - transmits fill-in value and read the data from RxFifo ++ * In Slave mode - Blocks until a value is available ++ * ++ * @param[in] obj The SPI peripheral to read ++ * @param[in] value The value received ++ * @return The status of the read request ++ * @note ++ * - In Master mode, MISO pin required to be non-NC for this API to operate ++ * - In Slave mode, MOSI pin required to be non-NC for this API to operate ++ */ ++cy_rslt_t cyhal_spi_recv(cyhal_spi_t *obj, uint32_t* value); ++ ++/** Synchronously send a byte out ++ * ++ * In Master mode transmits value to slave and read/drop a value from the RxFifo. ++ * In Slave mode writes a value to TxFifo ++ * ++ * @param[in] obj The SPI peripheral to use for sending ++ * @param[in] value The value to send ++ * @return The status of the write request ++ * @note ++ * - In Master mode, MOSI pin required to be non-NC for this API to operate ++ * - In Slave mode, MISO pin required to be non-NC for this API to operate ++ */ ++cy_rslt_t cyhal_spi_send(cyhal_spi_t *obj, uint32_t value); ++ ++/** Synchronously Write a block out and receive a value ++ * ++ * The total number of bytes sent and received will be the maximum of tx_length ++ * and rx_length. The bytes written will be padded (at the end) with the value ++ * given by write_fill. ++ * ++ * This function will block for the duration of the transfer. \ref cyhal_spi_transfer_async ++ * can be used for non-blocking transfers. ++ * ++ * @param[in] obj The SPI peripheral to use for sending ++ * @param[in] tx Pointer to the byte-array of data to write to the device ++ * @param[in,out] tx_length Number of bytes to write, updated with the number actually written ++ * @param[out] rx Pointer to the byte-array of data to read from the device ++ * @param[in,out] rx_length Number of bytes to read, updated with the number actually read ++ * @param[in] write_fill Default data transmitted while performing a read ++ * @return The status of the transfer request ++ * @note Both MOSI and MISO pins required to be non-NC for this API to operate ++ */ ++cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill); ++ ++/** Start an asynchronous SPI transfer. ++ * ++ * This will transfer `rx_length` bytes into the buffer pointed to by `rx`, while simultaneously transfering ++ * `tx_length` bytes of data from the buffer pointed to by `tx`, both in the background. ++ * When the transfer is complete, the @ref CYHAL_SPI_IRQ_DONE event will be raised. ++ * See @ref cyhal_spi_register_callback and @ref cyhal_spi_enable_event. ++ * \note For blocking transfers cyhal_spi_transfer can be used. ++ * ++ * @param[in] obj The SPI object that holds the transfer information ++ * @param[in] tx The transmit buffer ++ * @param[in,out] tx_length The number of bytes to transmit ++ * @param[out] rx The receive buffer ++ * @param[in,out] rx_length The number of bytes to receive ++ * @return The status of the transfer_async request ++ * @note Both MOSI and MISO pins required to be non-NC for this API to operate ++ */ ++cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length); ++ ++/** Checks if the specified SPI peripheral is in use ++ * ++ * @param[in] obj The SPI peripheral to check ++ * @return Indication of whether the SPI is still transmitting ++ */ ++bool cyhal_spi_is_busy(cyhal_spi_t *obj); ++ ++/** Abort an SPI transfer ++ * ++ * @param[in] obj The SPI peripheral to stop ++ * @return The status of the abort_async request ++ */ ++cy_rslt_t cyhal_spi_abort_async(cyhal_spi_t *obj); ++ ++/** Register a SPI callback handler ++ * ++ * This function will be called when one of the events enabled by \ref cyhal_spi_enable_event occurs. ++ * ++ * @param[in] obj The SPI object ++ * @param[in] callback The callback handler which will be invoked when the interrupt fires ++ * @param[in] callback_arg Generic argument that will be provided to the callback when called ++ */ ++void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t callback, void *callback_arg); ++ ++/** Configure SPI interrupt. This function is used for word-approach ++ * ++ * When an enabled event occurs, the function specified by \ref cyhal_spi_register_callback will be called. ++ * ++ * @param[in] obj The SPI object ++ * @param[in] event The SPI event type ++ * @param[in] intr_priority The priority for NVIC interrupt events ++ * @param[in] enable True to turn on interrupts, False to turn off ++ */ ++void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intr_priority, bool enable); ++ ++/******************************************************************************* ++* Backward compatibility macro. The following code is DEPRECATED and must ++* not be used in new projects ++*******************************************************************************/ ++/** \cond INTERNAL */ ++typedef cyhal_spi_event_t cyhal_spi_irq_event_t; ++/** \endcond */ ++ ++#if defined(__cplusplus) ++} ++#endif ++ ++#ifdef CYHAL_SPI_IMPL_HEADER ++#include CYHAL_SPI_IMPL_HEADER ++#endif /* CYHAL_SPI_IMPL_HEADER */ ++ ++/** \} group_hal_spi */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_hal.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_hal.c +new file mode 100644 +index 0000000000..f5a0716697 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_hal.c +@@ -0,0 +1,63 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Provides cyhal porting to generic mbed APIs ++ */ ++#include "cyhal.h" ++#include "mbed_thread.h" ++#include "mbed_wait_api.h" ++ ++static cyhal_sdio_t sdio_obj; ++ ++/* Edit Pin configuration */ ++const pinconfig_t PinConfig[] = { ++ ++ [CYBSP_WIFI_WL_REG_ON] = WIFI_WL_REG_ON, ++#ifdef CYBSP_WIFI_32K_CLK ++ [CYBSP_WIFI_32K_CLK] = WIFI_32K_CLK, ++#endif /* CYBSP_WIFI_32K_CLK */ ++ [CYBSP_LED1 ] = BSP_LED1, ++ [CYBSP_LED2 ] = BSP_LED2, ++ [CYBSP_WIFI_SDIO_CMD] = WIFI_SDIO_CMD, ++ [CYBSP_WIFI_SDIO_CLK] = WIFI_SDIO_CLK, ++ [CYBSP_WIFI_SDIO_D0 ] = WIFI_SDIO_D0, ++ [CYBSP_WIFI_SDIO_D1 ] = WIFI_SDIO_D1, ++ [CYBSP_WIFI_SDIO_D2 ] = WIFI_SDIO_D2, ++ [CYBSP_WIFI_SDIO_D3 ] = WIFI_SDIO_D3, ++ [CYBSP_SDIO_OOB_IRQ ] = WIFI_SDIO_OOB_IRQ //VIKR ++}; ++ ++void Cy_SysLib_Delay(uint32_t milliseconds) ++{ ++ thread_sleep_for(milliseconds); ++} ++ ++void Cy_SysLib_DelayUs(uint16_t microseconds) ++{ ++ wait_us(microseconds); ++} ++ ++void cyhal_system_delay_ms(uint32_t milliseconds) ++{ ++ Cy_SysLib_Delay(milliseconds); ++} ++ ++cyhal_sdio_t *cybsp_get_wifi_sdio_obj(void) ++{ ++ return &sdio_obj; ++} +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_syslib.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_syslib.h +new file mode 100644 +index 0000000000..7671d853cf +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_syslib.h +@@ -0,0 +1,592 @@ ++/***************************************************************************//** ++* \file cy_syslib.h ++* \version 2.40.1 ++* ++* Provides an API declaration of the SysLib driver. ++* ++******************************************************************************** ++* \copyright ++* Copyright 2016-2019 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++/** ++* \addtogroup group_syslib ++* \{ ++* The system libraries provide APIs that can be called in the user application ++* to handle the timing, logical checking or register. ++* ++* The functions and other declarations used in this driver are in cy_syslib.h. ++* You can include cy_pdl.h (ModusToolbox only) to get access to all functions ++* and declarations in the PDL. ++* ++* The SysLib driver contains a set of different system functions. These functions ++* can be called in the application routine. Major features of the system library: ++* * Delay functions ++* * The register Read/Write macro ++* * Assert and Halt ++* * Assert Classes and Levels ++* * A software reset ++* * Reading the reset cause ++* * An API to invalidate the flash cache and buffer ++* * Data manipulation macro ++* * A variable type definition from MISRA-C which specifies signedness ++* * Cross compiler compatible attributes ++* * Getting a silicon-unique ID API ++* * Setting wait states API ++* * Resetting the backup domain API ++* * APIs to serve Fault handler ++* ++* \section group_syslib_configuration Configuration Considerations ++* Assertion Usage
++* Use the CY_ASSERT() macro to check expressions that must be true as long as the ++* program is running correctly. It is a convenient way to insert sanity checks. ++* The CY_ASSERT() macro is defined in the cy_syslib.h file which is part of ++* the PDL library. The behavior of the macro is as follows: if the expression ++* passed to the macro is false, output an error message that includes the file ++* name and line number, and then halts the CPU. \n ++* In case of fault, the CY_ASSERT() macro calls the Cy_SysLib_AssertFailed() function. ++* This is a weakly linked function. The default implementation stores the file ++* name and line number of the ASSERT into global variables, cy_assertFileName ++* and cy_assertLine . It then calls the Cy_SysLib_Halt() function. ++* \note Firmware can redefine the Cy_SysLib_AssertFailed() function for custom processing. ++* ++* The PDL source code uses this assert mechanism extensively. It is recommended ++* that you enable asserts when debugging firmware. \n ++* Assertion Classes and Levels
++* The PDL defines three assert classes, which correspond to different kinds ++* of parameters. There is a corresponding assert "level" for each class. ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++*
Class MacroLevel MacroType of check
CY_ASSERT_CLASS_1CY_ASSERT_L1A parameter that could change between different PSoC devices ++* (e.g. the number of clock paths)
CY_ASSERT_CLASS_2CY_ASSERT_L2A parameter that has fixed limits such as a counter period
CY_ASSERT_CLASS_3CY_ASSERT_L3A parameter that is an enum constant
++* Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL. ++* This is a compiler command line argument, similar to how the DEBUG / NDEBUG ++* macro is passed. \n ++* Enabling any class also enables any lower-numbered class. ++* CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three ++* classes. The following example shows the command-line option to enable all ++* the assert levels: ++* \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode ++* \note The use of special characters, such as spaces, parenthesis, etc. must ++* be protected with quotes. ++* ++* After CY_ASSERT_LEVEL is defined, firmware can use ++* one of the three level macros to make an assertion. For example, if the ++* parameter can vary between devices, firmware uses the L1 macro. ++* \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode ++* If the parameter has bounds, firmware uses L2. ++* \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode ++* If the parameter is an enum, firmware uses L3. ++* \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode ++* Each check uses the appropriate level macro for the kind of parameter being checked. ++* If a particular assert class/level is not enabled, then the assert does nothing. ++* ++* \section group_syslib_more_information More Information ++* Refer to the technical reference manual (TRM). ++* ++* \section group_syslib_MISRA MISRA-C Compliance ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
1.2RNo reliance shall be placed on undefined or unspecified behaviour.This specific behavior is explicitly covered in rule 20.1.
2.1RThis function contains a mixture of in-line assembler statements and C statements.This si required by design of the Cy_SysLib_Halt function.
18.4RUnions shall not be used.The unions are used for CFSR, HFSR and SHCSR Fault Status Registers ++* content access as a word in code and as a structure during debug.
19.13AThe # and ## operators should not be used.The ## preprocessor operator is used in macros to form the field mask.
20.1RReserved identifiers, macros and functions in the standard library, shall not be ++* defined, redefined or undefined.The driver defines the macros with leading underscores ++* (_CLR_SET_FLD/_BOOL2FLD/_FLD2BOOL) and therefore generates this MISRA violation.
++* ++* \section group_syslib_changelog Changelog ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++* ++*
VersionChangesReason for Change
2.40.1Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.Removed the IAR compiler warning.
2.40Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.Improve PDL code base.
2.30Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.Provided support for the ARM Compiler 6.
Minor documentation edits.Documentation update and clarification.
Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.Improve user experience.
2.20Updated implementation of the \ref Cy_SysLib_AssertFailed() function to be available in Release and Debug modes.Provided support for the PDL static library in Release mode.
Minor documentation edits.Documentation update and clarification.
2.10Flattened the organization of the driver source code into the single source directory and the single include directory.Driver library directory-structure simplification.
Added the following macros: \ref CY_REG32_CLR_SET, \ref _CLR_SET_FLD16U, \ref CY_REG16_CLR_SET, \ref _CLR_SET_FLD8U, \ref CY_REG8_CLR_SETRegister access simplification.
Removed the Cy_SysLib_GetNumHfclkResetCause API function.This feature is not supported by SRSS_ver1.
Added register access layer. Use register access macros instead ++* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does ++* not need to be recompiled for each supported part number.
2.0.1Minor documentation editsDocumentation update and clarification
2.0 ++* Added Cy_SysLib_ResetBackupDomain() API implementation. \n ++* Added CY_NOINLINE attribute implementation. \n ++* Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n ++* Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n ++* Optimized Cy_SysLib_SetWaitStates() API implementation. ++* Improvements made based on usability feedback.
Added Assertion Classes and Levels.For error checking, parameter validation and status returns in the PDL API.
Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.To store debug information into a non-zero init area for future analysis.
Removed CY_WEAK attribute implementation.CMSIS __WEAK attribute should be used instead.
1.0Initial version
++* ++* \defgroup group_syslib_macros Macros ++* \defgroup group_syslib_functions Functions ++* \defgroup group_syslib_data_structures Data Structures ++* \defgroup group_syslib_enumerated_types Enumerated Types ++* ++*/ ++ ++#if !defined(CY_SYSLIB_H) ++#define CY_SYSLIB_H ++ ++#include ++#include ++ ++/******************************************************************************* ++* Data manipulation defines ++*******************************************************************************/ ++ ++/** Get the lower 8 bits of a 16-bit value. */ ++#define CY_LO8(x) ((uint8_t) ((x) & 0xFFU)) ++/** Get the upper 8 bits of a 16-bit value. */ ++#define CY_HI8(x) ((uint8_t) ((uint16_t)(x) >> 8U)) ++ ++/** Get the lower 16 bits of a 32-bit value. */ ++#define CY_LO16(x) ((uint16_t) ((x) & 0xFFFFU)) ++/** Get the upper 16 bits of a 32-bit value. */ ++#define CY_HI16(x) ((uint16_t) ((uint32_t)(x) >> 16U)) ++ ++/** Swap the byte ordering of a 16-bit value */ ++#define CY_SWAP_ENDIAN16(x) ((uint16_t)(((x) << 8U) | (((x) >> 8U) & 0x00FFU))) ++ ++/** Swap the byte ordering of a 32-bit value */ ++#define CY_SWAP_ENDIAN32(x) ((uint32_t)((((x) >> 24U) & 0x000000FFU) | (((x) & 0x00FF0000U) >> 8U) | \ ++ (((x) & 0x0000FF00U) << 8U) | ((x) << 24U))) ++ ++/** Swap the byte ordering of a 64-bit value */ ++#define CY_SWAP_ENDIAN64(x) ((uint64_t) (((uint64_t) CY_SWAP_ENDIAN32((uint32_t)(x)) << 32U) | \ ++ CY_SWAP_ENDIAN32((uint32_t)((x) >> 32U)))) ++ ++/* MISRA rule 6.3 recommends using specific-length typedef for the basic ++ * numerical types of signed and unsigned variants of char, float, and double. ++ */ ++typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */ ++typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */ ++typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */ ++ ++ ++/******************************************************************************* ++* Macro Name: CY_GET_REG8(addr) ++****************************************************************************//** ++* ++* Reads the 8-bit value from the specified address. This function can't be ++* used to access the Core register, otherwise a fault occurs. ++* ++* \param addr The register address. ++* ++* \return The read value. ++* ++*******************************************************************************/ ++#define CY_GET_REG8(addr) (*((const volatile uint8_t *)(addr))) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_SET_REG8(addr, value) ++****************************************************************************//** ++* ++* Writes an 8-bit value to the specified address. This function can't be ++* used to access the Core register, otherwise a fault occurs. ++* ++* \param addr The register address. ++* ++* \param value The value to write. ++* ++*******************************************************************************/ ++#define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value)) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_GET_REG16(addr) ++****************************************************************************//** ++* ++* Reads the 16-bit value from the specified address. ++* ++* \param addr The register address. ++* ++* \return The read value. ++* ++*******************************************************************************/ ++#define CY_GET_REG16(addr) (*((const volatile uint16_t *)(addr))) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_SET_REG16(addr, value) ++****************************************************************************//** ++* ++* Writes the 16-bit value to the specified address. ++* ++* \param addr The register address. ++* ++* \param value The value to write. ++* ++*******************************************************************************/ ++#define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value)) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_GET_REG24(addr) ++****************************************************************************//** ++* ++* Reads the 24-bit value from the specified address. ++* ++* \param addr The register address. ++* ++* \return The read value. ++* ++*******************************************************************************/ ++#define CY_GET_REG24(addr) (((uint32_t) (*((const volatile uint8_t *)(addr)))) | \ ++ (((uint32_t) (*((const volatile uint8_t *)(addr) + 1))) << 8U) | \ ++ (((uint32_t) (*((const volatile uint8_t *)(addr) + 2))) << 16U)) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_SET_REG24(addr, value) ++****************************************************************************//** ++* ++* Writes the 24-bit value to the specified address. ++* ++* \param addr The register address. ++* ++* \param value The value to write. ++* ++*******************************************************************************/ ++#define CY_SET_REG24(addr, value) do \ ++ { \ ++ (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \ ++ (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8U); \ ++ (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16U); \ ++ } \ ++ while(0) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_GET_REG32(addr) ++****************************************************************************//** ++* ++* Reads the 32-bit value from the specified register. The address is the little ++* endian order (LSB in lowest address). ++* ++* \param addr The register address. ++* ++* \return The read value. ++* ++*******************************************************************************/ ++#define CY_GET_REG32(addr) (*((const volatile uint32_t *)(addr))) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_SET_REG32(addr, value) ++****************************************************************************//** ++* ++* Writes the 32-bit value to the specified register. The address is the little ++* endian order (LSB in lowest address). ++* ++* \param addr The register address. ++* ++* \param value The value to write. ++* ++*******************************************************************************/ ++#define CY_SET_REG32(addr, value) (*((volatile uint32_t *)(addr)) = (uint32_t)(value)) ++ ++/******************************************************************************* ++* Macro Name: _CLR_SET_FLD32U ++****************************************************************************//** ++* ++* The macro for setting a register with a name field and value for providing ++* get-clear-modify-write operations. ++* Returns a resulting value to be assigned to the register. ++* ++*******************************************************************************/ ++#define _CLR_SET_FLD32U(reg, field, value) (((reg) & ((uint32_t)(~(field ## _Msk)))) | (_VAL2FLD(field, value))) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_REG32_CLR_SET ++****************************************************************************//** ++* ++* Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write ++* operations with a name field and value and writes a resulting value ++* to the 32-bit register. ++* ++*******************************************************************************/ ++#define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value))) ++ ++ ++/******************************************************************************* ++* Macro Name: _CLR_SET_FLD16U ++****************************************************************************//** ++* ++* The macro for setting a 16-bit register with a name field and value for providing ++* get-clear-modify-write operations. ++* Returns a resulting value to be assigned to the 16-bit register. ++* ++*******************************************************************************/ ++#define _CLR_SET_FLD16U(reg, field, value) ((uint16_t)(((reg) & ((uint16_t)(~(field ## _Msk)))) | \ ++ ((uint16_t)_VAL2FLD(field, value)))) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_REG16_CLR_SET ++****************************************************************************//** ++* ++* Uses _CLR_SET_FLD16U macro for providing get-clear-modify-write ++* operations with a name field and value and writes a resulting value ++* to the 16-bit register. ++* ++*******************************************************************************/ ++#define CY_REG16_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD16U((reg), field, (value))) ++ ++ ++/******************************************************************************* ++* Macro Name: _CLR_SET_FLD8U ++****************************************************************************//** ++* ++* The macro for setting a 8-bit register with a name field and value for providing ++* get-clear-modify-write operations. ++* Returns a resulting value to be assigned to the 8-bit register. ++* ++*******************************************************************************/ ++#define _CLR_SET_FLD8U(reg, field, value) ((uint8_t)(((reg) & ((uint8_t)(~(field ## _Msk)))) | \ ++ ((uint8_t)_VAL2FLD(field, value)))) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_REG8_CLR_SET ++****************************************************************************//** ++* ++* Uses _CLR_SET_FLD8U macro for providing get-clear-modify-write ++* operations with a name field and value and writes a resulting value ++* to the 8-bit register. ++* ++*******************************************************************************/ ++#define CY_REG8_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD8U((reg), field, (value))) ++ ++ ++/******************************************************************************* ++* Macro Name: _BOOL2FLD ++****************************************************************************//** ++* ++* Returns a field mask if the value is not false. ++* Returns 0, if the value is false. ++* ++*******************************************************************************/ ++#define _BOOL2FLD(field, value) (((value) != false) ? (field ## _Msk) : 0UL) ++ ++ ++/******************************************************************************* ++* Macro Name: _FLD2BOOL ++****************************************************************************//** ++* ++* Returns true, if the value includes the field mask. ++* Returns false, if the value doesn't include the field mask. ++* ++*******************************************************************************/ ++#define _FLD2BOOL(field, value) (((value) & (field ## _Msk)) != 0UL) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_SYSLIB_DIV_ROUND ++****************************************************************************//** ++* ++* Calculates a / b with rounding to the nearest integer, ++* a and b must have the same sign. ++* ++*******************************************************************************/ ++#define CY_SYSLIB_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b)) ++ ++ ++/******************************************************************************* ++* Macro Name: CY_SYSLIB_DIV_ROUNDUP ++****************************************************************************//** ++* ++* Calculates a / b with rounding up if remainder != 0, ++* both a and b must be positive. ++* ++*******************************************************************************/ ++#define CY_SYSLIB_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) ++ ++typedef uint32_t cy_status; ++/** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */ ++typedef uint32_t cystatus; ++typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */ ++typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */ ++typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */ ++typedef int8_t int8; /**< Alias to int8_t for backward compatibility */ ++typedef int16_t int16; /**< Alias to int16_t for backward compatibility */ ++typedef int32_t int32; /**< Alias to int32_t for backward compatibility */ ++typedef float float32; /**< Alias to float for backward compatibility */ ++typedef double float64; /**< Alias to double for backward compatibility */ ++typedef int64_t int64; /**< Alias to int64_t for backward compatibility */ ++typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */ ++/* Signed or unsigned depending on the compiler selection */ ++typedef char char8; /**< Alias to char for backward compatibility */ ++typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */ ++typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */ ++typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */ ++ ++/** The ARM 32-bit Return error / status code for backward compatibility. ++* Do not use them in your code. ++*/ ++#define CY_RET_SUCCESS (0x00U) /* Successful */ ++#define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */ ++#define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */ ++#define CY_RET_MEMORY (0x03U) /* A memory-related failure */ ++#define CY_RET_LOCKED (0x04U) /* A resource lock failure */ ++#define CY_RET_EMPTY (0x05U) /* No more objects available */ ++#define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ ++#define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ ++#define CY_RET_FINISHED (0x08U) /* Operation is completed */ ++#define CY_RET_CANCELED (0x09U) /* Operation is canceled */ ++#define CY_RET_TIMEOUT (0x10U) /* Operation timed out */ ++#define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ ++#define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */ ++ ++/** ARM 32-bit Return error / status codes for backward compatibility with the UDB components. ++* Do not use them in your code. ++*/ ++#define CYRET_SUCCESS (0x00U) /* Successful */ ++#define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */ ++#define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */ ++#define CYRET_MEMORY (0x03U) /* A memory-related failure */ ++#define CYRET_LOCKED (0x04U) /* A resource lock failure */ ++#define CYRET_EMPTY (0x05U) /* No more objects available */ ++#define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ ++#define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ ++#define CYRET_FINISHED (0x08U) /* Operation is completed */ ++#define CYRET_CANCELED (0x09U) /* Operation is canceled */ ++#define CYRET_TIMEOUT (0x10U) /* Operation timed out */ ++#define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ ++#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */ ++ ++/** \} group_syslib_functions */ ++ ++#endif /* CY_SYSLIB_H */ ++ ++/** \} group_syslib */ ++ ++/* [] END OF FILE */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_utils.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_utils.h +new file mode 100644 +index 0000000000..db8c143f36 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_utils.h +@@ -0,0 +1,81 @@ ++/***************************************************************************//** ++* \file cy_utils.h ++* ++* \brief ++* Basic utility macros and functions. ++* ++******************************************************************************** ++* \copyright ++* Copyright 2018-2019 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++/** ++* \addtogroup group_utils Utilities ++* \ingroup group_abstraction ++* \{ ++* Basic utility macros and functions. ++* ++* \defgroup group_utils_macros Macros ++*/ ++ ++#pragma once ++ ++#include "stdint.h" ++ ++#if defined(__cplusplus) ++extern "C" { ++#endif ++ ++/** ++* \addtogroup group_utils_macros ++* \{ ++*/ ++ ++/** Simple macro to supress the unused parameter warning by casting to void. */ ++#define CY_UNUSED_PARAMETER(x) ( (void)(x) ) ++ ++/** Halt the processor in the debug state ++ * @return ++ */ ++static inline uint32_t CY_HALT() ++{ ++ __asm(" bkpt 1"); ++ return 0; ++} ++ ++#ifdef CY_ASSERT ++#undef CY_ASSERT ++#endif /* ifdef(CY_ASSERT) */ ++ ++/** Utility macro when neither NDEBUG or CY_NO_ASSERT is not declared to check a condition and, if false, trigger a breakpoint */ ++#if defined(NDEBUG) || defined(CY_NO_ASSERT) ++ #define CY_ASSERT(x) CY_UNUSED_PARAMETER(x) ++#else ++ #define CY_ASSERT(x) do { \ ++ if(!(x)) \ ++ { \ ++ CY_HALT(); \ ++ } \ ++ } while(0) ++#endif /* defined(NDEBUG) */ ++ ++/** \} group_utils_macros */ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/** \} group_utils */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cybsp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cybsp.h +new file mode 100644 +index 0000000000..06226f327b +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cybsp.h +@@ -0,0 +1,50 @@ ++/***************************************************************************//** ++* \file cybsp.h ++* ++* \brief ++* Basic API for setting up boards containing a Cypress MCU. ++* ++******************************************************************************** ++* \copyright ++* Copyright 2018-2020 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++#pragma once ++ ++#include "cy_result.h" ++#include "cyhal_sdio.h" ++ ++#if defined(__cplusplus) ++extern "C" { ++#endif ++ ++/** ++* \addtogroup group_bsp_functions Functions ++* \{ ++*/ ++ ++/** ++ * \brief Get the initialized sdio object used for communicating with the WiFi Chip. ++ * \note This function should only be called after cybsp_init(); ++ * \returns The initialized sdio object. ++ */ ++cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); ++ ++/** \} group_bsp_functions */ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cycfg.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cycfg.h +new file mode 100644 +index 0000000000..7a3dee0ca9 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cycfg.h +@@ -0,0 +1,20 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Empty file to be compliant with Cypress COMPONENT_WHD ++ */ +\ No newline at end of file +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal.h +new file mode 100644 +index 0000000000..e56be0e013 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal.h +@@ -0,0 +1,52 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Provides cyhal porting to generic mbed APIs ++ */ ++#include "whd_config.h" ++#include "cyhal_hw_types.h" ++#include "cyhal_gpio.h" ++#include "cyhal_sdio.h" ++ ++#if defined(__cplusplus) ++extern "C" { ++#endif ++ ++typedef enum ++{ ++ CYBSP_WIFI_WL_REG_ON, ++ CYBSP_WIFI_32K_CLK, ++ CYBSP_LED1, ++ CYBSP_LED2, ++ CYBSP_WIFI_SDIO_CMD, ++ CYBSP_WIFI_SDIO_CLK, ++ CYBSP_WIFI_SDIO_D0, ++ CYBSP_WIFI_SDIO_D1, ++ CYBSP_WIFI_SDIO_D2, ++ CYBSP_WIFI_SDIO_D3, ++ CYBSP_SDIO_OOB_IRQ, ++ CYBSP_WIFI_MAX, ++} wwd_sdio_pin_t; ++ ++void cyhal_system_delay_ms(uint32_t milliseconds); ++cy_rslt_t sdio_enable_high_speed(void); ++ ++#if defined(__cplusplus) ++} ++#endif ++ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_gpio.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_gpio.cpp +new file mode 100644 +index 0000000000..3b7d33d0fe +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_gpio.cpp +@@ -0,0 +1,104 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Provides the porting layer for STM32 GPIOs on WHD driver ++ */ ++ ++#include ++#include "cyhal.h" ++#include "cybsp.h" ++#include "mbed.h" ++#include "wiced_filesystem.h" ++ ++extern pinconfig_t PinConfig[]; ++ ++/******************************************************************************* ++* Internal ++*******************************************************************************/ ++static mbed::InterruptIn *oob_irq; ++static cyhal_gpio_event_t oob_event = CYHAL_GPIO_IRQ_FALL; ++static cyhal_gpio_event_callback_t oob_handler; ++static void *oob_handler_arg; ++ ++/******************************************************************************* ++* Internal Interrrupt Service Routine ++*******************************************************************************/ ++static void cb() ++{ ++ oob_handler(oob_handler_arg, oob_event); ++} ++ ++/******************************************************************************* ++* HAL Implementation ++*******************************************************************************/ ++cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal) ++{ ++ cy_rslt_t ret = CY_RSLT_SUCCESS; ++ ++ // Workaround to enable GPIOJ clock ++ if (pin == CYBSP_WIFI_WL_REG_ON) { ++ __HAL_RCC_GPIOB_CLK_ENABLE(); ++ // Ensure FS and BlockDevice are initialized on time if needed ++ wiced_filesystem_init(); ++ } ++ // Ignore the parameter and take the pin config directly from a static array defintions ++ HAL_GPIO_Init(PinConfig[pin].port, &PinConfig[pin].config); ++ if (direction == CYHAL_GPIO_DIR_OUTPUT) { ++ HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (initVal) ? GPIO_PIN_SET : GPIO_PIN_RESET); ++ } ++ // Workaround to initialize sdio interface without cypress bsp init ++ if (pin == CYBSP_WIFI_WL_REG_ON) { ++ cyhal_sdio_t *sdio_p = cybsp_get_wifi_sdio_obj(); ++ ret = cyhal_sdio_init(sdio_p, CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3); ++ } ++ return ret; ++} ++ ++void cyhal_gpio_write(cyhal_gpio_t pin, bool value) ++{ ++ HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (value) ? GPIO_PIN_SET : GPIO_PIN_RESET); ++} ++ ++void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t handler, void *handler_arg) ++{ ++ if (handler && handler_arg && (oob_irq == NULL)) { ++ oob_irq = new mbed::InterruptIn(WL_HOST_WAKE); ++ oob_handler = handler; ++ oob_handler_arg = handler_arg; ++ } ++} ++ ++void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable) ++{ ++ oob_event = event; ++ if (enable) { ++ if (event == CYHAL_GPIO_IRQ_RISE) { ++ oob_irq->rise(cb); ++ } ++ if (event == CYHAL_GPIO_IRQ_FALL) { ++ oob_irq->fall(cb); ++ } ++ } else if (oob_irq != NULL) { ++ delete oob_irq; ++ } ++} ++ ++void cyhal_gpio_free(cyhal_gpio_t pin) ++{ ++ // Do nothing ++} +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_hw_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_hw_types.h +new file mode 100644 +index 0000000000..1f872abb37 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_hw_types.h +@@ -0,0 +1,112 @@ ++/***************************************************************************//** ++* \file cyhal_hw_types_template.h ++* ++* \brief ++* Provides a template for configuration resources used by the HAL. Items ++* here need to be implemented for each HAL port. It is up to the environment ++* being ported into what the actual types are. There are some suggestions below ++* but these are not required. All that is required is that the type is defined; ++* it does not matter to the HAL what type is actually chosen for the ++* implementation ++* All TODOs and references to 'PORT' need to be replaced by with meaningful ++* values for the device being supported. ++* ++******************************************************************************** ++* \copyright ++* Copyright 2018-2019 Cypress Semiconductor Corporation ++* SPDX-License-Identifier: Apache-2.0 ++* ++* Licensed under the Apache License, Version 2.0 (the "License"); ++* you may not use this file except in compliance with the License. ++* You may obtain a copy of the License at ++* ++* http://www.apache.org/licenses/LICENSE-2.0 ++* ++* Unless required by applicable law or agreed to in writing, software ++* distributed under the License is distributed on an "AS IS" BASIS, ++* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++* See the License for the specific language governing permissions and ++* limitations under the License. ++*******************************************************************************/ ++ ++/** ++ * \addtogroup group_hal_hw_types PORT Hardware Types ++ * \ingroup group_hal_PORT ++ * \{ ++ * Struct definitions for configuration resources in the PORT. ++ * ++ * \defgroup group_hal_hw_types_data_structures Data Structures ++ */ ++ ++#pragma once ++#include ++#include "stm32h7xx_hal.h" ++#include "PinNames.h" ++ ++/* ++ #include "TODO: Port specific header file" ++ */ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ ++#ifndef CYHAL_ISR_PRIORITY_DEFAULT ++/** Priority that is applied by default to all drivers when initalized. Priorities can be ++ * overridden on each driver as part of enabling events. ++ */ ++#define CYHAL_ISR_PRIORITY_DEFAULT (7) ++#endif ++ ++/** ++ * \addtogroup group_hal_hw_types_data_structures ++ * \{ ++ */ ++ ++typedef int32_t cyhal_gpio_t; ++ ++/** GPIO object */ ++typedef struct ++{ ++ GPIO_TypeDef *port; ++ GPIO_InitTypeDef config; ++} pinconfig_t; ++ ++/** Clock divider object */ ++typedef struct ++{ ++ /* TODO: replace with port specific items */ ++ void *div_type; ++} cyhal_clock_divider_t; ++ ++/** Clock object */ ++typedef struct ++{ ++ //For backwards compatibility with cyhal_clock_divider_t only. Do not use going forward. ++ int div_type; /*!< Deprecated */ ++ uint8_t div_num; /*!< Deprecated */ ++ //End BWC items ++ int block; ++ uint8_t channel; ++ bool reserved; ++} cyhal_clock_t; ++ ++/** SDIO object */ ++typedef void* *cyhal_sdio_t; ++ ++/** SPI object */ ++typedef struct ++{ ++ /* TODO: replace with port specific items */ ++ void *empty; ++} cyhal_spi_t; ++ ++#include "whd_config.h" ++#include "whd_debug.h" ++ ++#if defined(__cplusplus) ++} ++#endif /* __cplusplus */ ++ ++/** \} group_hal_hw_types */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_sdio.c +new file mode 100644 +index 0000000000..3ddfd85848 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_sdio.c +@@ -0,0 +1,506 @@ ++/* ++ * Copyright 2020 Cypress Semiconductor Corporation ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Provides the porting layer for STM32 SDIO on WHD driver ++ */ ++ ++#include ++#include ++#include "whd_thread.h" ++#include "bus_protocols/whd_bus_sdio_protocol.h" ++#include "cyabs_rtos.h" ++#include "cyhal_sdio.h" ++ ++#define SDIO_RESPONSE_SHORT SDMMC_RESPONSE_SHORT ++#define SDIO_WAIT_NO SDMMC_WAIT_NO ++#define SDIO_CPSM_ENABLE SDMMC_CPSM_ENABLE ++#define SDIO_CMDTRANS SDMMC_CMD_CMDTRANS ++#define SDIO_FLAG_CMDACT (SDMMC_STA_CPSMACT | SDMMC_STA_DPSMACT) ++#define SDIO_TRANSFER_DIR_TO_SDIO SDMMC_TRANSFER_DIR_TO_SDMMC ++#define SDIO_TRANSFER_DIR_TO_CARD SDMMC_TRANSFER_DIR_TO_CARD ++#define SDIO_TRANSFER_MODE_BLOCK SDMMC_TRANSFER_MODE_BLOCK ++#define SDIO_DPSM_ENABLE SDMMC_DPSM_ENABLE ++#define SDIO_DPSM_DISABLE SDMMC_DPSM_DISABLE ++#define SDIO_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN /* 1 << 11 */ ++#define SDIO_DCTRL_DTMODE_1 SDMMC_DCTRL_DTMODE_1 /* 1<<3 */ ++#define SDIO_STA_DTIMEOUT SDMMC_STA_DTIMEOUT ++#define SDIO_STA_CTIMEOUT SDMMC_STA_CTIMEOUT ++#define SDIO_STA_CCRCFAIL SDMMC_STA_CCRCFAIL ++#define SDIO_STA_DCRCFAIL SDMMC_STA_DCRCFAIL ++#define SDIO_STA_TXUNDERR SDMMC_STA_TXUNDERR ++#define SDIO_STA_RXOVERR SDMMC_STA_RXOVERR ++#define SDIO_STA_TXACT SDMMC_STA_CPSMACT ++#define SDIO_STA_RXACT SDMMC_STA_DPSMACT ++#define SDIO_STA_CMDREND SDMMC_STA_CMDREND ++#define SDIO_STA_CMDSENT SDMMC_STA_CMDSENT ++#define SDIO_CMD_CMDTRANS SDMMC_CMD_CMDTRANS ++#define SDIO SDMMC1 ++ ++#define COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS (100000) ++#define BUS_LEVEL_MAX_RETRIES 10 ++ ++#define SDIO_CMD_5 5 ++#define SDIO_CMD_53 53 ++ ++#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!b)?a:b ++ ++/* D-cache maintenance for DMA buffers */ ++#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) ++ #define _CYHAL_DCACHE_MAINTENANCE ++ #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (32u) ++#else ++ #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (4u) ++#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */ ++ ++/* Macro to ALIGN */ ++#if defined (__ARMCC_VERSION) /* ARM Compiler */ ++ #define ALIGN_HAL_COMMON(buf, x) __align(x) buf ++#elif defined (__GNUC__) /* GNU Compiler */ ++ #define ALIGN_HAL_COMMON(buf, x) buf __attribute__ ((aligned (x))) ++#elif defined (__ICCARM__) /* IAR Compiler */ ++ #define ALIGN_HAL_COMMON(buf, x) __ALIGNED(x) buf ++#endif ++ ++/* Macro to get variable aligned for cache maintenance purpose */ ++#define CYHAL_ALIGN_DMA_BUFFER(arg) ALIGN_HAL_COMMON(arg, _CYHAL_DMA_BUFFER_ALIGN_BYTES) ++ ++ ++extern pinconfig_t PinConfig[]; ++extern SD_HandleTypeDef hsd; ++ ++/* for debug prints only */ ++//static int num = 0; ++ ++static uint32_t dctrl; ++ ++static whd_driver_t whd_handler; ++static cyhal_sdio_irq_handler_t sdio_irq_handler; ++ ++CYHAL_ALIGN_DMA_BUFFER(static uint8_t temp_dma_buffer[2048]); ++static uint8_t *user_data; ++static uint32_t user_data_size; ++static uint8_t *dma_data_source; ++static uint32_t dma_transfer_size; ++static cyhal_transfer_t current_transfer_direction; ++ ++static cy_semaphore_t sdio_transfer_finished_semaphore; ++static volatile uint32_t sdio_transfer_failed = 0; ++static volatile uint32_t irqstatus = 0; ++static int current_command = 0; ++ ++static cy_rslt_t sdio_enable_high_speed(void) ++{ ++ SDMMC_InitTypeDef sdio_init_structure; ++ ++ sdio_init_structure.ClockDiv = SDMMC_HSpeed_CLK_DIV; ++ sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; ++ sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; ++ sdio_init_structure.BusWide = SDMMC_BUS_WIDE_4B; ++ sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE; ++ ++ SDMMC_Init(SDMMC1, sdio_init_structure); ++ return CY_RSLT_SUCCESS; ++} ++ ++static uint32_t find_optimal_block_size(uint32_t data_size) ++{ ++ if (data_size > (uint32_t) 256) { ++ return 512; ++ } ++ if (data_size > (uint32_t) 128) { ++ return 256; ++ } ++ if (data_size > (uint32_t) 64) { ++ return 128; ++ } ++ if (data_size > (uint32_t) 32) { ++ return 64; ++ } ++ if (data_size > (uint32_t) 16) { ++ return 32; ++ } ++ if (data_size > (uint32_t) 8) { ++ return 16; ++ } ++ if (data_size > (uint32_t) 4) { ++ return 8; ++ } ++ if (data_size > (uint32_t) 2) { ++ return 4; ++ } ++ ++ return 4; ++} ++ ++static uint32_t sdio_get_blocksize(uint32_t blocksize) ++{ ++ uint32_t n = 0; ++ blocksize >>= 1; ++ while (blocksize) { ++ n++; ++ blocksize >>= 1; ++ } ++ n <<= 4; ++ return n; ++} ++ ++static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t block_size, uint8_t *data, uint16_t data_size) ++{ ++ /* Setup a single transfer using the temp buffer */ ++ user_data = data; ++ user_data_size = data_size; ++ dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size); ++ ++ if (direction == CYHAL_WRITE) { ++ memcpy(temp_dma_buffer, data, data_size); ++ dma_data_source = temp_dma_buffer; ++ } else { ++ dma_data_source = (uint8_t *)temp_dma_buffer; ++ } ++ ++#ifdef _CYHAL_DCACHE_MAINTENANCE ++ if (direction == CYHAL_WRITE) ++ { ++ SCB_CleanDCache_by_Addr((uint32_t*)dma_data_source, block_size * dma_transfer_size); ++ } ++ else ++ { ++ /* Cache-Invalidate the output from DMA */ ++ SCB_InvalidateDCache_by_Addr((uint32_t*)dma_data_source, ++ data_size + __SCB_DCACHE_LINE_SIZE); ++ } ++#endif ++ ++ SDIO->DTIMER = (uint32_t) 0xFFFFFFFF; ++ SDIO->DLEN = dma_transfer_size; ++ dctrl = sdio_get_blocksize(block_size) | ((direction == CYHAL_READ) ? SDIO_TRANSFER_DIR_TO_SDIO : SDIO_TRANSFER_DIR_TO_CARD) | SDIO_TRANSFER_MODE_BLOCK | SDIO_DPSM_DISABLE | SDIO_DCTRL_SDIOEN; ++ SDIO->DCTRL = dctrl; ++ ++ SDMMC1->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; ++ SDMMC1->IDMABASE0 = (uint32_t) dma_data_source; ++} ++ ++static void sdio_enable_bus_irq(void) ++{ ++ SDMMC1->MASK = SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_CMDREND | SDMMC_IT_CMDSENT; ++} ++ ++void SDMMC1_IRQHandler(void) ++{ ++ uint32_t intstatus = SDIO->STA; ++ ++ irqstatus = intstatus; ++ //VIKR | SDIO_STA_STBITERR ) ++ if ((intstatus & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0) { ++ WPRINT_WHD_DEBUG(("sdio error flagged\n")); ++ sdio_transfer_failed = intstatus; ++ SDIO->ICR = (uint32_t) 0xffffffff; ++ cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); ++ } else { ++ if ((intstatus & (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT)) != 0) { ++ if ((SDMMC1->RESP1 & 0x800) != 0) { ++ sdio_transfer_failed = irqstatus; ++ cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); ++ } ++ ++ /* Clear all command/response interrupts */ ++ SDMMC1->ICR = (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT); ++ } ++ ++ /* Check whether the external interrupt was triggered */ ++ if (intstatus & SDMMC_STA_SDIOIT) { ++ /* Clear the interrupt */ ++ SDMMC1->ICR = SDMMC_STA_SDIOIT; ++ /* Inform WICED WWD thread */ ++ sdio_irq_handler(whd_handler, CYHAL_SDIO_CARD_INTERRUPT); ++ } ++ ++ if (intstatus & SDMMC_STA_DATAEND) { ++ SDMMC1->ICR = SDMMC_STA_DATAEND; ++ SDMMC1->DLEN = 0; ++ SDMMC1->DCTRL = SDMMC_DCTRL_SDIOEN; ++ SDMMC1->IDMACTRL = SDMMC_DISABLE_IDMA; ++ SDMMC1->CMD = 0; ++ cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); ++ } ++ } ++} ++ ++//void sdio_dma_irq(void) ++//{ ++// /* Clear interrupt */ ++// DMA2->LIFCR = (uint32_t)(0x3F << 22); ++// cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); ++//} ++ ++cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3) ++{ ++ cy_rslt_t ret = CY_RSLT_SUCCESS; ++ ++ __HAL_RCC_GPIOC_CLK_ENABLE(); ++ __HAL_RCC_GPIOD_CLK_ENABLE(); ++ __HAL_RCC_SDMMC1_CLK_ENABLE(); ++ ++ HAL_GPIO_Init(PinConfig[cmd].port, &PinConfig[cmd].config); ++ HAL_GPIO_Init(PinConfig[clk].port, &PinConfig[clk].config); ++ HAL_GPIO_Init(PinConfig[data0].port, &PinConfig[data0].config); ++ HAL_GPIO_Init(PinConfig[data1].port, &PinConfig[data1].config); ++ HAL_GPIO_Init(PinConfig[data2].port, &PinConfig[data2].config); ++ HAL_GPIO_Init(PinConfig[data3].port, &PinConfig[data3].config); ++ ++ /* Reset SDIO Block */ ++ SDMMC_PowerState_OFF(SDMMC1); ++ __HAL_RCC_SDMMC1_FORCE_RESET(); ++ __HAL_RCC_SDMMC1_RELEASE_RESET(); ++ ++ /* Enable the SDIO Clock */ ++ __HAL_RCC_SDMMC1_CLK_ENABLE(); ++ ++ WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore)); ++ ++ // Lower speed configuration ++ SDMMC_InitTypeDef sdio_init_structure; ++ ++ sdio_init_structure.ClockDiv = SDMMC_INIT_CLK_DIV; ++ sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; ++ sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; ++ sdio_init_structure.BusWide = SDMMC_BUS_WIDE_1B; ++ sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; ++ ret = SDMMC_Init(SDMMC1, sdio_init_structure); ++ ret |= SDMMC_PowerState_ON(SDMMC1); ++ ret |= SDMMC_SetSDMMCReadWaitMode(SDMMC1, SDMMC_READ_WAIT_MODE_CLK); ++ if (ret) { ++ return ret; ++ } ++ ++ /* Clear all SDIO interrupts */ ++ SDMMC1->ICR = (uint32_t) 0xffffffff; ++ ++ /* Turn on SDIO IRQ */ ++ /* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */ ++ /* otherwise FreeRTOS will not be able to mask the interrupt */ ++ /* keep in mind that ARMCM7 interrupt priority logic is inverted, the highest value */ ++ /* is the lowest priority */ ++ HAL_NVIC_EnableIRQ((IRQn_Type) SDMMC1_IRQn); ++ HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0); ++ ++ WPRINT_WHD_DEBUG(("after enable sdio: %p\n", sdio_transfer_finished_semaphore)); ++ ++ if (cy_rtos_init_semaphore(&sdio_transfer_finished_semaphore, 1, 0) != WHD_SUCCESS) { ++ cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); ++ return -1; ++ } ++ ++ WPRINT_WHD_DEBUG(("cy_rtos_init_semaphore: %p\n", sdio_transfer_finished_semaphore)); ++ ++ return ret; ++} ++ ++void cyhal_sdio_free(cyhal_sdio_t *obj) ++{ ++ //TODO ++} ++ ++cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config) ++{ ++ return sdio_enable_high_speed(); ++} ++ ++cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t *response) ++{ ++ uint32_t loop_count = 0; ++ cy_rslt_t result; ++ uint16_t attempts = 0; ++ uint32_t temp_sta; ++ ++ if (response != NULL) { ++ *response = 0; ++ } ++ current_command = 0; ++ ++restart: ++ SDIO->ICR = (uint32_t) 0xFFFFFFFF; ++ ++attempts; ++ ++ /* Check if we've tried too many times */ ++ if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { ++ /* WWD_SDIO_RETRIES_EXCEEDED */ ++ result = -1; ++ goto exit; ++ } ++ ++ /* Send the command */ ++ SDIO->ARG = argument; ++ SDIO->CMD = (uint32_t)(command | SDIO_RESPONSE_SHORT | SDIO_WAIT_NO | SDIO_CPSM_ENABLE); ++ loop_count = (uint32_t) COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS; ++ do { ++ temp_sta = SDIO->STA; ++ loop_count--; ++ if (loop_count == 0 /*|| ((response != NULL) && ((temp_sta & SDIO_ERROR_MASK) != 0))*/) { ++ WPRINT_WHD_DEBUG(("Restart single access loop count %ld stat %lx\n", loop_count, temp_sta)); ++ HAL_Delay(10U); ++ goto restart; ++ } ++ } while ((temp_sta & SDIO_FLAG_CMDACT) != 0); ++ ++ if (response != NULL) { ++ *response = SDIO->RESP1; ++ } ++ result = CY_RSLT_SUCCESS; ++ ++exit: ++ if (result) { ++ WPRINT_WHD_ERROR(("SDIO->POWER %lx \n", SDIO->POWER)); ++ WPRINT_WHD_ERROR(("SDIO->CLKCR %lx \n", SDIO->CLKCR)); ++ WPRINT_WHD_ERROR(("result %lx \n", result)); ++ WPRINT_WHD_ERROR(("cyhal_sdio_send_cmd %s\n", (result == 0) ? "Passed" : "Failed")); ++ while (1); ++ } ++ SDMMC1->CMD = 0; ++ ++ //WPRINT_WHD_DEBUG(("%d %s cmd 0x%x arg 0x%x resp 0x%x\n",num++,(direction!=CYHAL_READ)?"Write":"Read",command,argument,(response)?*response:0)); ++ return result; ++} ++ ++cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length, uint32_t *response) ++{ ++ cy_rslt_t result; ++ uint16_t attempts = 0; ++ uint32_t block_size = 64; ++ sdio_cmd_argument_t arg; ++ uint32_t cmd; ++ current_command = SDIO_CMD_53; ++ current_transfer_direction = direction; ++ arg.value = argument; ++ ++ sdio_enable_bus_irq(); ++ if (response != NULL) { ++ *response = 0; ++ } ++ ++restart: ++ sdio_transfer_failed = 0; ++ SDMMC1->ICR = (uint32_t) 0xFFFFFFFF; ++ ++attempts; ++ ++ /* Check if we've tried too many times */ ++ if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { ++ /* WWD_SDIO_RETRIES_EXCEEDED */ ++ WPRINT_WHD_ERROR(("Too much attempt\n")); ++ result = -1; ++ goto exit; ++ } ++ ++ /* Dodgy STM32 hack to set the CMD53 byte mode size to be the same as the block size */ ++ if (arg.cmd53.block_mode == 0) { ++ block_size = find_optimal_block_size(arg.cmd53.count); ++ if (block_size < SDIO_512B_BLOCK) { ++ arg.cmd53.count = block_size; ++ } else { ++ arg.cmd53.count = 0; ++ } ++ argument = arg.value; ++ } ++ ++ SDMMC1->CMD |= SDMMC_CMD_CMDTRANS; ++ ++ /* Prepare the SDIO for a data transfer */ ++ sdio_prepare_data_transfer(direction, block_size, (uint8_t *) data, (uint32_t) length); ++ ++ /* Send the command */ ++ //WPRINT_WHD_DEBUG(("%d bs=%d argument=%x\n",num++,block_size,argument)); ++ SDMMC1->ARG = argument; ++ cmd = (uint32_t)(SDIO_CMD_53 | SDMMC_RESPONSE_SHORT | SDMMC_WAIT_NO | SDMMC_CPSM_ENABLE | SDMMC_CMD_CMDTRANS); ++ SDMMC1->CMD = cmd; ++ ++ /* Wait for the whole transfer to complete */ ++ //WPRINT_WHD_DEBUG(("cy_rtos_get_semaphore: %d\n", sdio_transfer_finished_semaphore)); ++ result = cy_rtos_get_semaphore(&sdio_transfer_finished_semaphore, 50, WHD_FALSE); ++ ++ if (result != CY_RSLT_SUCCESS) { ++ WPRINT_WHD_ERROR(("failed getting semaphore\n")); ++ goto exit; ++ } ++ if (sdio_transfer_failed) { ++ WPRINT_WHD_DEBUG(("try again sdio_transfer_failed %"PRIu32" irq %"PRIu32"\n", sdio_transfer_failed, irqstatus)); ++ goto restart; ++ } ++ /* Check if there were any SDIO errors */ ++ if ((SDIO->STA & (SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT)) != 0) { ++ WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT\n")); ++ goto restart; ++ } else if (((SDIO->STA & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0)) { ++ WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVER \n")); ++ goto restart; ++ } ++ ++ if (direction == CYHAL_READ) { ++ #ifdef _CYHAL_DCACHE_MAINTENANCE ++ SCB_CleanInvalidateDCache_by_Addr( ++ (uint32_t*)((uint32_t)dma_data_source & ~(__SCB_DCACHE_LINE_SIZE - 1U)), ++ user_data_size + __SCB_DCACHE_LINE_SIZE); ++ #endif /* if defined(_CYHAL_DCACHE_MAINTENANCE) */ ++ ++ memcpy(user_data, dma_data_source, (size_t) user_data_size); ++ } ++ ++ if (response != NULL) { ++ *response = SDIO->RESP1; ++ } ++ result = CY_RSLT_SUCCESS; ++ ++exit: ++ SDMMC1->CMD = 0; ++ ++ //WPRINT_WHD_DEBUG(("%d %s cmd 53 argument %lx datasize %d blocknumber 0x%x cmdis %lx %lu dctrl = %x\n", num++, (direction != CYHAL_READ) ? "Write" : "Read", argument, length, arg.cmd53.count, cmd, cmd, dctrl)); ++ ++ return result; ++} ++ ++cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length) ++{ ++ //TODO ++ return CYHAL_SDIO_RET_NO_SP_ERRORS; ++} ++ ++bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) ++{ ++ return false; ++} ++ ++cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) ++{ ++ //TODO ++ return CYHAL_SDIO_RET_NO_SP_ERRORS; ++} ++ ++void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg) ++{ ++ whd_handler = (whd_driver_t)handler_arg; ++ sdio_irq_handler = handler; ++} ++ ++void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, uint8_t intr_priority, bool enable) ++{ ++ //TODO ++} ++ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_spi.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_spi.c +new file mode 100644 +index 0000000000..162c7a6801 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_spi.c +@@ -0,0 +1,29 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Provides stubs for the WHD driver needed by ARMClang ++ */ ++ ++#include ++#include ++#include "cyhal_spi.h" ++ ++cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill) ++{ ++ // Do nothing ++} +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_system.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_system.h +new file mode 100644 +index 0000000000..7a3dee0ca9 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_system.h +@@ -0,0 +1,20 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Empty file to be compliant with Cypress COMPONENT_WHD ++ */ +\ No newline at end of file +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_bd.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_bd.h +new file mode 100644 +index 0000000000..578b2d9e4e +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_bd.h +@@ -0,0 +1,49 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Provides wiced fs porting to generic mbed APIs ++ */ ++ ++#pragma once ++ ++#include "whd_config.h" ++#include "BlockDevice.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/****************************************************** ++ * Type Definitions ++ ******************************************************/ ++ ++/** ++ * Mount the physical device ++ * ++ * This assumes that the device is ready to read/write immediately. ++ * ++ * @param[in] device - physical media to init ++ * @param[out] fs_handle_out - Receives the filesystem handle. ++ * ++ * @return WICED_SUCCESS on success ++ */ ++wiced_result_t wiced_filesystem_mount(mbed::BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name); ++ ++#ifdef __cplusplus ++} /*extern "C" */ ++#endif +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.cpp +new file mode 100644 +index 0000000000..5973be673a +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.cpp +@@ -0,0 +1,225 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Provides wiced fs porting to generic mbed APIs ++ */ ++ ++#include ++#include ++#include ++#include ++#include "sockets.h" ++#include "resources.h" ++#include "wiced_filesystem.h" ++#include "wiced_bd.h" ++#include "QSPIFBlockDevice.h" ++#include "MBRBlockDevice.h" ++#include "FATFileSystem.h" ++ ++#define WIFI_DEFAULT_FIRMWARE_PATH "/wlan/4343WA1.BIN" ++#define WIFI_DEFAULT_MOUNT_NAME "wlan" ++#define WIFI_DEFAULT_PARTITION 1 ++#define WIFI_DEFAULT_FS 0 ++ ++BlockDevice *qspi_bd = NULL; ++MBRBlockDevice *mbr_bd = NULL; ++FATFileSystem *wifi_fs = NULL; ++ ++wiced_filesystem_t resource_fs_handle; ++ ++MBED_WEAK BlockDevice *BlockDevice::get_default_instance() ++{ ++ static QSPIFBlockDevice default_bd(PD_11, PD_12, PE_2, PF_6, PF_10, PG_6, QSPIF_POLARITY_MODE_1, 40000000); ++ return &default_bd; ++} ++ ++MBED_WEAK void wiced_filesystem_mount_error(void) ++{ ++ WPRINT_WHD_ERROR(("Failed to mount the filesystem containing the WiFi firmware.\n\r")); ++ whd_print_logbuffer(); ++ while (1) {} ++} ++ ++MBED_WEAK void wiced_filesystem_firmware_error(void) ++{ ++ WPRINT_WHD_ERROR(("Please run the \"WiFiFirmwareUpdater\" sketch once to install the WiFi firmware.\n\r")); ++ whd_print_logbuffer(); ++ while (1) {} ++} ++ ++MBED_WEAK wiced_result_t whd_firmware_check_hook(const char *mounted_name, int mount_err) ++{ ++ DIR *dir; ++ struct dirent *ent; ++ std::string dir_name(mounted_name); ++ if (mount_err) { ++ wiced_filesystem_mount_error(); ++ } else { ++ if ((dir = opendir(mounted_name)) != NULL) { ++ // print all the files and directories within directory ++ while ((ent = readdir(dir)) != NULL) { ++ std::string fullname = "/" + dir_name + "/" + std::string(ent->d_name); ++ if (fullname == WIFI_DEFAULT_FIRMWARE_PATH) { ++ closedir(dir); ++ return WICED_SUCCESS; ++ } ++ } ++ closedir(dir); ++ } ++ wiced_filesystem_firmware_error(); ++ } ++ return WICED_ERROR; ++} ++ ++static wiced_result_t whd_default_firmware_restore(void) ++{ ++#if MBED_CONF_APP_WIFI_FIRMWARE_RESTORE ++ size_t ret; ++ FILE *fp; ++ ++ //This should only happen the firs time or if the partition table has been overwritten i.e QSPI tests ++ WPRINT_WHD_DEBUG(("MBRBlockDevice init failed, repatitioning\n\r")); ++ if (mbr_bd->partition(qspi_bd, 1, 0x0B, 0, 1024 * 1024) != BD_ERROR_OK) { ++ return WICED_ERROR; ++ } ++ WPRINT_WHD_DEBUG(("MBRBockDevice repatitioning OK, reinit\n\r")); ++ ++ if (mbr_bd->init() != BD_ERROR_OK) { ++ return WICED_ERROR; ++ } ++ WPRINT_WHD_DEBUG(("MBRBockDevice init OK\n\r")); ++ ++ wifi_fs = new FATFileSystem(WIFI_DEFAULT_MOUNT_NAME); ++ ++ if (wifi_fs->reformat(mbr_bd) != 0) { ++ return WICED_ERROR; ++ } ++ WPRINT_WHD_DEBUG(("FATFileSystem reformat and mount OK\n\r")); ++ ++ fp = fopen(WIFI_DEFAULT_FIRMWARE_PATH, "wb"); ++ if (fp == NULL) { ++ return WICED_ERROR; ++ } ++ ret = fwrite(wifi_firmware_image_data, wifi_firmware_image.size, 1, fp); ++ if (ret != wifi_firmware_image.size) { ++ return WICED_ERROR; ++ } ++ fclose(fp); ++ ++ if (mbr_bd->sync() != 0) { ++ return WICED_ERROR; ++ } ++ WPRINT_WHD_DEBUG(("Sync BlockDevice OK\n\r")); ++ ++ if (wifi_fs->unmount() != 0) { ++ return WICED_ERROR; ++ } ++ WPRINT_WHD_DEBUG(("Unmount FS\n\r")); ++ wifi_fs = NULL; ++#endif ++ ++ return WICED_SUCCESS; ++} ++ ++wiced_result_t wiced_filesystem_init(void) ++{ ++ if (mbr_bd == NULL && wifi_fs == NULL) { ++ WPRINT_WHD_DEBUG(("Initialize FileSystem with Mbed default settings\n\r")); ++ qspi_bd = mbed::BlockDevice::get_default_instance(); ++ ++ if (qspi_bd->init() == BD_ERROR_OK) { ++ mbr_bd = new MBRBlockDevice(qspi_bd, WIFI_DEFAULT_PARTITION); ++ if (mbr_bd->init() == BD_ERROR_OK) { ++ return WICED_SUCCESS; ++ } else { ++ return whd_default_firmware_restore(); ++ } ++ } ++ return WICED_ERROR; ++ } else { ++ WPRINT_WHD_DEBUG(("FileSystem initialized with user settings\n\r")); ++ return WICED_SUCCESS; ++ } ++} ++ ++wiced_result_t wiced_filesystem_mount_default(void) ++{ ++ return wiced_filesystem_mount(mbr_bd, 0, &resource_fs_handle, WIFI_DEFAULT_MOUNT_NAME); ++} ++ ++wiced_result_t wiced_filesystem_mount(BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name) ++{ ++ wifi_fs = new FATFileSystem(mounted_name); ++ ++ int err = wifi_fs->mount(device); ++ whd_firmware_check_hook(mounted_name, err); ++ if (!err) { ++ //fs_handle_out = wifi_fs ++ return WICED_SUCCESS; ++ } ++ return WICED_ERROR; ++} ++ ++wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode) ++{ ++ /* This is called by mbed test system */ ++ //if (mbr_bd == NULL && wifi_fs == NULL) { ++ // wiced_filesystem_init(); ++ //} ++ //This can be called from user sketch to provide custom block device and mount point before WiFi.beginAP or WiFi.begin ++ if (wifi_fs == NULL) { ++ wiced_filesystem_mount(mbr_bd, WIFI_DEFAULT_FS, fs_handle, WIFI_DEFAULT_MOUNT_NAME); ++ } ++ ++ if (wifi_fs == NULL) { ++ return WICED_ERROR; ++ } ++ ++ *file_handle_out = open(filename, mode); ++ if (*file_handle_out == -1) { ++ return WICED_ERROR; ++ } ++ return WICED_SUCCESS; ++} ++ ++wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence) ++{ ++ if (*file_handle == -1) { ++ return WICED_ERROR; ++ } ++ lseek(*file_handle, offset, whence); ++ return WICED_SUCCESS; ++} ++ ++wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count) ++{ ++ if (*file_handle == -1) { ++ return WICED_ERROR; ++ } ++ *returned_bytes_count = read(*file_handle, data, bytes_to_read); ++ return WICED_SUCCESS; ++} ++ ++wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle) ++{ ++ if (*file_handle == -1) { ++ return WICED_ERROR; ++ } ++ close(*file_handle); ++ return WICED_SUCCESS; ++} +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.h +new file mode 100644 +index 0000000000..77d49d1820 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.h +@@ -0,0 +1,148 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Provides wiced fs porting to generic mbed APIs ++ */ ++ ++#pragma once ++ ++#include "whd_config.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ ++/****************************************************** ++ * Enumerations ++ ******************************************************/ ++ ++typedef enum { ++ WICED_FILESYSTEM_OPEN_FOR_READ, /** Specifies read access to the object. Data can be read from the file - equivalent to "r" or "rb" */ ++ WICED_FILESYSTEM_OPEN_FOR_WRITE, /** Specifies read/write access to the object. Data can be written to the file - equivalent to "r+" or "rb+" or "r+b" */ ++ WICED_FILESYSTEM_OPEN_WRITE_CREATE, /** Opens for read/write access, creates it if it doesn't exist */ ++ WICED_FILESYSTEM_OPEN_ZERO_LENGTH, /** Opens for read/write access, Truncates file to zero length if it exists, or creates it if it doesn't - equivalent to "w+", "wb+" or "w+b" */ ++ WICED_FILESYSTEM_OPEN_APPEND, /** Opens for read/write access, places the current location at the end of the file ready for appending - equivalent to "a", "ab" */ ++ WICED_FILESYSTEM_OPEN_APPEND_CREATE, /** Opens for read/write access, creates it if it doesn't exist, and places the current location at the end of the file ready for appending - equivalent to "a+", "ab+" or "a+b" */ ++} wiced_filesystem_open_mode_t; ++ ++typedef enum { ++ WICED_FILESYSTEM_SEEK_SET = SEEK_SET, /* Offset from start of file */ ++ WICED_FILESYSTEM_SEEK_CUR = SEEK_CUR, /* Offset from current position in file */ ++ WICED_FILESYSTEM_SEEK_END = SEEK_END, /* Offset from end of file */ ++} wiced_filesystem_seek_type_t; ++ ++typedef enum { ++ WICED_SUCCESS = 0, ++ WICED_ERROR = 1 ++} wiced_result_t; ++ ++/****************************************************** ++ * Type Definitions ++ ******************************************************/ ++ ++/** ++ * File-system Handle Structure ++ */ ++typedef int wiced_filesystem_t; ++ ++/** ++ * File Handle Structure ++ * ++ */ ++typedef int wiced_file_t; ++ ++/** ++ * File-system type Handle Structure ++ */ ++typedef int wiced_filesystem_handle_type_t; ++ ++/** ++ * Initialise the BlockDevice and filesystem module ++ * ++ * Initialises the BlockDevice and filesystem module before mounting a physical device. ++ * ++ * @return WICED_SUCCESS on success ++ */ ++wiced_result_t wiced_filesystem_init(void); ++ ++/** ++ * Mount the physical device using default parameters ++ * ++ * This assumes that the device is ready to read/write immediately. ++ * ++ * @return WICED_SUCCESS on success ++ */ ++wiced_result_t wiced_filesystem_mount_default(void); ++ ++/** ++ * Open a file for reading or writing ++ * ++ * @param[in] fs_handle - The filesystem handle to use - obtained from wiced_filesystem_mount ++ * @param[out] file_handle_out - a pointer to a wiced_file_t structure which will receive the ++ * file handle after it is opened ++ * @param[in] filename - The filename of the file to open ++ * @param[in] mode - Specifies read or write access ++ * ++ * @return WICED_SUCCESS on success ++ */ ++wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode); ++ ++/** ++ * Seek to a location within a file ++ * ++ * This is similar to the fseek() in ISO C. ++ * ++ * @param[in] file_handle - The file handle on which to perform the seek. ++ * Must have been previously opened with wiced_filesystem_fopen. ++ * @param[in] offset - The offset in bytes ++ * @param[in] whence - WICED_FILESYSTEM_SEEK_SET = Offset from start of file ++ * WICED_FILESYSTEM_SEEK_CUR = Offset from current position in file ++ * WICED_FILESYSTEM_SEEK_END = Offset from end of file ++ * ++ * @return WICED_SUCCESS on success ++ */ ++wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence); ++ ++/** ++ * Reads data from a file into a memory buffer ++ * ++ * @param[in] file_handle - the file handle to read from ++ * @param[out] data - A pointer to the memory buffer that will ++ * receive the data that is read ++ * @param[in] bytes_to_read - the number of bytes to read ++ * @param[out] returned_item_count - the number of items successfully read. ++ * ++ * @return WICED_SUCCESS on success ++ */ ++wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count); ++ ++/** ++ * Close a file ++ * ++ * This is similar to the fclose() in ISO C. ++ * ++ * @param[in] file_handle - the file handle to close ++ * ++ * @return WICED_SUCCESS = success ++ */ ++wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle); ++ ++#ifdef __cplusplus ++} /*extern "C" */ ++#endif +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt +new file mode 100644 +index 0000000000..cbb51f9c99 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt +@@ -0,0 +1,49 @@ ++Permissive Binary License ++ ++Version 1.0, July 2019 ++ ++Redistribution. Redistribution and use in binary form, without ++modification, are permitted provided that the following conditions are ++met: ++ ++1) Redistributions must reproduce the above copyright notice and the ++ following disclaimer in the documentation and/or other materials ++ provided with the distribution. ++ ++2) Unless to the extent explicitly permitted by law, no reverse ++ engineering, decompilation, or disassembly of this software is ++ permitted. ++ ++3) Redistribution as part of a software development kit must include the ++ accompanying file named �DEPENDENCIES� and any dependencies listed in ++ that file. ++ ++4) Neither the name of the copyright holder nor the names of its ++ contributors may be used to endorse or promote products derived from ++ this software without specific prior written permission. ++ ++Limited patent license. The copyright holders (and contributors) grant a ++worldwide, non-exclusive, no-charge, royalty-free patent license to ++make, have made, use, offer to sell, sell, import, and otherwise ++transfer this software, where such license applies only to those patent ++claims licensable by the copyright holders (and contributors) that are ++necessarily infringed by this software. This patent license shall not ++apply to any combinations that include this software. No hardware is ++licensed hereunder. ++ ++If you institute patent litigation against any entity (including a ++cross-claim or counterclaim in a lawsuit) alleging that the software ++itself infringes your patent(s), then your rights granted under this ++license shall terminate as of the date such litigation is filed. ++ ++DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND ++CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT ++NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED ++TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +\ No newline at end of file +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c +new file mode 100644 +index 0000000000..ddaf0f7188 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c +@@ -0,0 +1,25493 @@ ++/* ++ * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved ++ * SPDX-License-Identifier: LicenseRef-PBL ++ * ++ * This file and the related binary are licensed under the ++ * Permissive Binary License, Version 1.0 (the "License"); ++ * you may not use these files except in compliance with the License. ++ * ++ * You may obtain a copy of the License here: ++ * LICENSE-permissive-binary-license-1.0.txt and at ++ * https://www.mbed.com/licenses/PBL-1.0 ++ * ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++#include "wiced_resource.h" ++ ++#if defined(CY_STORAGE_WIFI_DATA) ++CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) ++#endif ++const unsigned char wifi_firmware_image_data[421098] = { ++ 0, 0, 0, 0, 237, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, ++ 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, ++ 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, ++ 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, ++ 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, ++ 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, ++ 25, 33, 0, 0, 25, 33, 0, 0, 0, 72, 0, 71, 237, 33, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 68, 66, 80, 80, 128, 109, 4, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 149, 212, 1, 0, 223, 145, 2, 0, 59, 146, 2, 0, 73, 140, ++ 2, 0, 193, 137, 2, 0, 13, 137, 2, 0, 85, 138, 2, 0, 203, 135, 2, 0, ++ 167, 136, 2, 0, 181, 146, 2, 0, 189, 146, 2, 0, 141, 135, 2, 0, 167, ++ 135, 2, 0, 245, 140, 2, 0, 181, 135, 2, 0, 129, 145, 2, 0, 161, 135, ++ 2, 0, 17, 144, 2, 0, 97, 33, 0, 0, 93, 33, 0, 0, 157, 33, 0, 0, 163, ++ 128, 3, 0, 121, 128, 3, 0, 163, 126, 3, 0, 191, 126, 3, 0, 167, 128, ++ 3, 0, 251, 126, 3, 0, 247, 213, 1, 0, 145, 177, 0, 0, 45, 173, 0, 0, ++ 141, 177, 0, 0, 125, 169, 0, 0, 101, 173, 0, 0, 209, 177, 0, 0, 111, ++ 225, 4, 0, 141, 174, 0, 0, 61, 178, 0, 0, 63, 178, 0, 0, 97, 177, 0, ++ 0, 109, 225, 4, 0, 137, 43, 0, 0, 143, 227, 1, 0, 85, 227, 1, 0, 235, ++ 217, 1, 0, 61, 216, 1, 0, 145, 214, 1, 0, 49, 216, 1, 0, 137, 43, 0, ++ 0, 179, 178, 1, 0, 175, 178, 1, 0, 185, 178, 1, 0, 17, 227, 1, 0, 153, ++ 213, 1, 0, 143, 216, 1, 0, 171, 178, 1, 0, 153, 221, 1, 0, 165, 178, ++ 1, 0, 137, 43, 0, 0, 63, 227, 1, 0, 135, 138, 3, 0, 97, 227, 1, 0, 237, ++ 211, 1, 0, 137, 43, 0, 0, 209, 140, 3, 0, 59, 237, 2, 0, 117, 218, 2, ++ 0, 69, 230, 2, 0, 81, 230, 2, 0, 9, 229, 2, 0, 221, 242, 2, 0, 43, 246, ++ 2, 0, 11, 224, 2, 0, 185, 218, 2, 0, 109, 240, 2, 0, 133, 234, 2, 0, ++ 209, 224, 2, 0, 129, 224, 2, 0, 73, 224, 2, 0, 49, 224, 2, 0, 43, 224, ++ 2, 0, 151, 240, 2, 0, 141, 223, 2, 0, 251, 239, 2, 0, 177, 239, 2, 0, ++ 167, 219, 2, 0, 85, 131, 3, 0, 153, 132, 3, 0, 35, 246, 2, 0, 29, 246, ++ 2, 0, 137, 43, 0, 0, 45, 223, 2, 0, 165, 218, 2, 0, 175, 218, 2, 0, ++ 87, 233, 2, 0, 89, 230, 2, 0, 163, 218, 2, 0, 83, 231, 2, 0, 203, 234, ++ 2, 0, 237, 233, 2, 0, 77, 223, 2, 0, 109, 239, 2, 0, 205, 242, 2, 0, ++ 141, 242, 2, 0, 153, 242, 2, 0, 235, 238, 2, 0, 87, 223, 2, 0, 99, 233, ++ 2, 0, 131, 233, 2, 0, 89, 233, 2, 0, 65, 233, 2, 0, 3, 229, 2, 0, 157, ++ 218, 2, 0, 151, 218, 2, 0, 41, 246, 2, 0, 135, 233, 2, 0, 55, 224, 2, ++ 0, 45, 246, 2, 0, 77, 239, 2, 0, 205, 223, 2, 0, 113, 239, 2, 0, 25, ++ 225, 2, 0, 67, 229, 2, 0, 199, 228, 2, 0, 137, 43, 0, 0, 137, 43, 0, ++ 0, 217, 228, 2, 0, 99, 228, 2, 0, 65, 225, 2, 0, 199, 132, 3, 0, 187, ++ 132, 3, 0, 227, 132, 3, 0, 173, 132, 3, 0, 211, 228, 2, 0, 111, 133, ++ 3, 0, 189, 235, 2, 0, 137, 43, 0, 0, 221, 138, 3, 0, 169, 140, 3, 0, ++ 169, 137, 3, 0, 61, 138, 3, 0, 117, 142, 3, 0, 79, 140, 3, 0, 137, 142, ++ 3, 0, 141, 141, 3, 0, 85, 142, 3, 0, 123, 141, 3, 0, 79, 138, 3, 0, ++ 217, 136, 3, 0, 213, 139, 3, 0, 137, 43, 0, 0, 99, 183, 3, 0, 137, 43, ++ 0, 0, 137, 43, 0, 0, 95, 183, 3, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, ++ 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 215, 209, 3, 0, 137, 43, 0, ++ 0, 137, 43, 0, 0, 137, 43, 0, 0, 189, 217, 3, 0, 145, 217, 3, 0, 137, ++ 43, 0, 0, 89, 215, 3, 0, 39, 217, 3, 0, 69, 215, 3, 0, 97, 217, 3, 0, ++ 57, 214, 3, 0, 185, 218, 1, 0, 113, 247, 3, 0, 147, 247, 3, 0, 151, ++ 247, 3, 0, 137, 43, 0, 0, 137, 43, 0, 0, 93, 233, 3, 0, 83, 235, 3, ++ 0, 137, 43, 0, 0, 149, 239, 3, 0, 137, 43, 0, 0, 137, 43, 0, 0, 157, ++ 19, 4, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, ++ 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, ++ 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, ++ 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, ++ 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 1, 37, 0, ++ 0, 93, 49, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 25, 145, ++ 0, 0, 37, 145, 0, 0, 29, 147, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 137, ++ 43, 0, 0, 137, 43, 0, 0, 137, 43, 0, 0, 41, 232, 0, 0, 137, 43, 0, 0, ++ 239, 35, 0, 0, 21, 36, 0, 0, 213, 36, 0, 0, 13, 37, 0, 0, 29, 38, 0, ++ 0, 25, 44, 0, 0, 105, 49, 0, 0, 117, 49, 0, 0, 1, 50, 0, 0, 173, 52, ++ 0, 0, 221, 52, 0, 0, 249, 53, 0, 0, 157, 55, 0, 0, 135, 58, 0, 0, 133, ++ 60, 0, 0, 65, 64, 0, 0, 209, 69, 0, 0, 249, 70, 0, 0, 105, 72, 0, 0, ++ 9, 146, 0, 0, 137, 43, 0, 0, 85, 146, 0, 0, 51, 147, 0, 0, 57, 147, ++ 0, 0, 85, 147, 0, 0, 117, 148, 0, 0, 141, 148, 0, 0, 165, 148, 0, 0, ++ 185, 149, 0, 0, 83, 153, 0, 0, 187, 153, 0, 0, 33, 154, 0, 0, 47, 154, ++ 0, 0, 115, 154, 0, 0, 29, 155, 0, 0, 99, 155, 0, 0, 173, 155, 0, 0, ++ 201, 157, 0, 0, 117, 156, 0, 0, 121, 155, 0, 0, 215, 157, 0, 0, 37, ++ 158, 0, 0, 247, 158, 0, 0, 41, 159, 0, 0, 81, 160, 0, 0, 73, 179, 0, ++ 0, 79, 179, 0, 0, 83, 179, 0, 0, 113, 179, 0, 0, 181, 179, 0, 0, 241, ++ 179, 0, 0, 5, 180, 0, 0, 45, 197, 0, 0, 213, 197, 0, 0, 209, 200, 0, ++ 0, 29, 201, 0, 0, 85, 201, 0, 0, 93, 201, 0, 0, 237, 202, 0, 0, 75, ++ 203, 0, 0, 93, 203, 0, 0, 251, 205, 0, 0, 33, 212, 0, 0, 177, 212, 0, ++ 0, 7, 213, 0, 0, 11, 213, 0, 0, 33, 213, 0, 0, 139, 213, 0, 0, 59, 214, ++ 0, 0, 189, 214, 0, 0, 41, 215, 0, 0, 117, 217, 0, 0, 89, 215, 0, 0, ++ 237, 219, 0, 0, 137, 43, 0, 0, 63, 32, 1, 0, 237, 225, 0, 0, 1, 226, ++ 0, 0, 13, 226, 0, 0, 105, 226, 0, 0, 89, 230, 0, 0, 69, 232, 0, 0, 69, ++ 233, 0, 0, 219, 233, 0, 0, 41, 235, 0, 0, 169, 252, 0, 0, 173, 255, ++ 0, 0, 5, 2, 1, 0, 111, 2, 1, 0, 217, 10, 1, 0, 181, 14, 1, 0, 133, 33, ++ 1, 0, 11, 35, 1, 0, 39, 36, 1, 0, 243, 38, 1, 0, 21, 39, 1, 0, 35, 39, ++ 1, 0, 21, 40, 1, 0, 111, 40, 1, 0, 139, 40, 1, 0, 199, 45, 1, 0, 69, ++ 57, 1, 0, 237, 70, 1, 0, 137, 71, 1, 0, 205, 90, 1, 0, 147, 97, 1, 0, ++ 225, 117, 1, 0, 197, 121, 1, 0, 69, 130, 1, 0, 13, 138, 1, 0, 209, 146, ++ 1, 0, 133, 232, 1, 0, 161, 241, 1, 0, 105, 7, 2, 0, 139, 7, 2, 0, 247, ++ 8, 2, 0, 99, 12, 2, 0, 137, 43, 0, 0, 77, 18, 2, 0, 85, 78, 2, 0, 149, ++ 80, 2, 0, 5, 86, 2, 0, 35, 88, 2, 0, 81, 88, 2, 0, 185, 94, 2, 0, 199, ++ 102, 2, 0, 235, 102, 2, 0, 241, 102, 2, 0, 17, 103, 2, 0, 101, 103, ++ 2, 0, 177, 103, 2, 0, 255, 103, 2, 0, 57, 104, 2, 0, 233, 119, 2, 0, ++ 53, 169, 2, 0, 243, 209, 3, 0, 255, 209, 3, 0, 185, 210, 3, 0, 11, 211, ++ 3, 0, 61, 211, 3, 0, 129, 211, 3, 0, 165, 211, 3, 0, 173, 211, 3, 0, ++ 177, 211, 3, 0, 19, 213, 3, 0, 23, 213, 3, 0, 47, 19, 4, 0, 1, 0, 0, ++ 0, 0, 0, 0, 8, 32, 0, 0, 0, 0, 2, 0, 0, 4, 0, 0, 0, 255, 3, 0, 0, 80, ++ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 4, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, ++ 1, 0, 0, 0, 1, 0, 0, 0, 232, 3, 0, 0, 4, 0, 0, 0, 10, 7, 8, 0, 110, ++ 25, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 4, 0, 4, 0, 8, 0, 1, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, ++ 244, 18, 176, 0, 0, 0, 0, 5, 244, 102, 177, 0, 0, 0, 0, 5, 244, 14, ++ 176, 0, 0, 0, 0, 4, 244, 248, 177, 0, 0, 0, 0, 4, 244, 194, 177, 0, ++ 0, 0, 0, 2, 244, 207, 180, 0, 0, 0, 0, 2, 244, 34, 181, 0, 0, 0, 0, ++ 250, 247, 190, 156, 0, 0, 0, 0, 250, 247, 250, 156, 0, 0, 0, 0, 250, ++ 247, 64, 158, 0, 0, 0, 0, 250, 247, 218, 157, 0, 0, 0, 0, 250, 247, ++ 49, 155, 0, 0, 0, 0, 4, 244, 246, 179, 0, 0, 0, 0, 250, 247, 214, 156, ++ 0, 0, 0, 0, 0, 244, 202, 181, 0, 0, 0, 0, 234, 247, 153, 153, 0, 0, ++ 0, 0, 247, 247, 84, 159, 0, 0, 0, 0, 247, 247, 116, 153, 0, 0, 0, 0, ++ 247, 247, 52, 153, 0, 0, 0, 0, 253, 247, 115, 153, 0, 0, 0, 0, 253, ++ 247, 172, 154, 0, 0, 0, 0, 253, 247, 64, 155, 0, 0, 0, 0, 253, 247, ++ 66, 153, 0, 0, 0, 0, 248, 247, 78, 157, 0, 0, 0, 0, 248, 247, 198, 155, ++ 0, 0, 0, 0, 243, 247, 174, 156, 0, 0, 0, 0, 243, 247, 50, 153, 0, 0, ++ 0, 0, 242, 247, 116, 158, 0, 0, 0, 0, 247, 247, 96, 157, 0, 0, 0, 0, ++ 247, 247, 244, 153, 0, 0, 0, 0, 240, 247, 214, 157, 0, 0, 0, 0, 242, ++ 247, 161, 157, 0, 0, 0, 0, 237, 247, 192, 158, 0, 0, 0, 0, 234, 247, ++ 180, 159, 0, 0, 0, 0, 235, 247, 96, 152, 0, 0, 0, 0, 243, 247, 1, 153, ++ 0, 0, 0, 0, 231, 247, 252, 158, 0, 0, 0, 0, 241, 247, 32, 154, 0, 0, ++ 0, 0, 231, 247, 4, 154, 0, 0, 0, 0, 230, 247, 180, 157, 0, 0, 0, 0, ++ 230, 247, 118, 154, 0, 0, 0, 0, 230, 247, 66, 154, 0, 0, 0, 0, 229, ++ 247, 70, 157, 0, 0, 0, 0, 229, 247, 24, 158, 0, 0, 0, 0, 229, 247, 28, ++ 156, 0, 0, 0, 0, 233, 247, 174, 159, 0, 0, 0, 0, 233, 247, 138, 154, ++ 0, 0, 0, 0, 233, 247, 154, 153, 0, 0, 0, 0, 232, 247, 4, 155, 0, 0, ++ 0, 0, 231, 247, 238, 157, 0, 0, 0, 0, 231, 247, 6, 155, 0, 0, 0, 0, ++ 231, 247, 52, 157, 0, 0, 0, 0, 230, 247, 42, 158, 0, 0, 0, 0, 230, 247, ++ 129, 156, 0, 0, 0, 0, 230, 247, 41, 153, 0, 0, 0, 0, 230, 247, 37, 154, ++ 0, 0, 0, 0, 230, 247, 249, 152, 0, 0, 0, 0, 229, 247, 113, 159, 0, 0, ++ 0, 0, 230, 247, 66, 152, 0, 0, 0, 0, 229, 247, 251, 157, 0, 0, 0, 0, ++ 229, 247, 101, 156, 0, 0, 0, 0, 230, 247, 54, 159, 0, 0, 0, 0, 231, ++ 247, 144, 157, 0, 0, 0, 0, 230, 247, 140, 155, 0, 0, 0, 0, 229, 247, ++ 251, 155, 0, 0, 0, 0, 226, 247, 224, 153, 0, 0, 0, 0, 227, 247, 28, ++ 156, 0, 0, 0, 0, 226, 247, 95, 152, 0, 0, 0, 0, 225, 247, 174, 157, ++ 0, 0, 0, 0, 225, 247, 201, 158, 0, 0, 0, 0, 225, 247, 231, 156, 0, 0, ++ 0, 0, 226, 247, 26, 155, 0, 0, 0, 0, 237, 247, 163, 154, 0, 0, 0, 0, ++ 224, 247, 170, 157, 0, 0, 0, 0, 225, 247, 152, 155, 0, 0, 0, 0, 225, ++ 247, 150, 152, 0, 0, 0, 0, 225, 247, 153, 154, 0, 0, 0, 0, 225, 247, ++ 41, 154, 0, 0, 0, 0, 223, 247, 69, 157, 0, 0, 0, 0, 223, 247, 90, 154, ++ 0, 0, 0, 0, 223, 247, 184, 153, 0, 0, 0, 0, 222, 247, 64, 158, 0, 0, ++ 0, 0, 223, 247, 223, 156, 0, 0, 0, 0, 223, 247, 86, 154, 0, 0, 0, 0, ++ 223, 247, 152, 154, 0, 0, 0, 0, 222, 247, 38, 158, 0, 0, 0, 0, 222, ++ 247, 84, 159, 0, 0, 0, 0, 222, 247, 116, 156, 0, 0, 0, 0, 222, 247, ++ 147, 156, 0, 0, 0, 0, 222, 247, 127, 155, 0, 0, 0, 0, 222, 247, 137, ++ 155, 0, 0, 0, 0, 219, 247, 51, 156, 0, 0, 0, 0, 216, 247, 12, 158, 0, ++ 0, 0, 0, 216, 247, 90, 156, 0, 0, 0, 0, 216, 247, 100, 157, 0, 0, 0, ++ 0, 223, 247, 126, 153, 0, 0, 0, 0, 216, 247, 218, 153, 0, 0, 0, 0, 216, ++ 247, 16, 157, 0, 0, 0, 0, 216, 247, 178, 155, 0, 0, 0, 0, 216, 247, ++ 176, 155, 0, 0, 0, 0, 234, 247, 105, 158, 0, 0, 0, 0, 216, 247, 24, ++ 157, 0, 0, 0, 0, 221, 247, 146, 158, 0, 0, 0, 0, 232, 247, 13, 154, ++ 0, 0, 0, 0, 216, 247, 56, 155, 0, 0, 0, 0, 216, 247, 95, 153, 0, 0, ++ 0, 0, 216, 247, 56, 153, 0, 0, 0, 0, 216, 247, 65, 153, 0, 0, 0, 0, ++ 216, 247, 200, 152, 0, 0, 0, 0, 216, 247, 189, 153, 0, 0, 0, 0, 216, ++ 247, 109, 152, 0, 0, 0, 0, 215, 247, 41, 159, 0, 0, 0, 0, 215, 247, ++ 7, 155, 0, 0, 0, 0, 215, 247, 233, 154, 0, 0, 0, 0, 216, 247, 20, 153, ++ 0, 0, 0, 0, 229, 247, 186, 159, 0, 0, 0, 0, 213, 247, 100, 159, 0, 0, ++ 0, 0, 213, 247, 153, 153, 0, 0, 0, 0, 213, 247, 36, 153, 0, 0, 0, 0, ++ 229, 247, 1, 157, 0, 0, 0, 0, 227, 247, 220, 153, 0, 0, 0, 0, 231, 247, ++ 42, 159, 0, 0, 0, 0, 225, 247, 12, 153, 0, 0, 0, 0, 226, 247, 200, 158, ++ 0, 0, 0, 0, 211, 247, 0, 157, 0, 0, 0, 0, 211, 247, 30, 156, 0, 0, 0, ++ 0, 210, 247, 153, 158, 0, 0, 0, 0, 229, 247, 247, 156, 0, 0, 0, 0, 230, ++ 247, 9, 157, 0, 0, 0, 0, 210, 247, 179, 155, 0, 0, 0, 0, 210, 247, 61, ++ 159, 0, 0, 0, 0, 210, 247, 246, 152, 0, 0, 0, 0, 208, 247, 67, 159, ++ 0, 0, 0, 0, 208, 247, 212, 155, 0, 0, 0, 0, 207, 247, 172, 159, 0, 0, ++ 0, 0, 207, 247, 175, 158, 0, 0, 0, 0, 208, 247, 22, 154, 0, 0, 0, 0, ++ 207, 247, 170, 153, 0, 0, 0, 0, 207, 247, 158, 153, 0, 0, 0, 0, 208, ++ 247, 218, 152, 0, 0, 0, 0, 208, 247, 45, 152, 0, 0, 0, 0, 207, 247, ++ 187, 155, 0, 0, 0, 0, 207, 247, 93, 156, 0, 0, 0, 0, 207, 247, 51, 153, ++ 0, 0, 0, 0, 206, 247, 202, 158, 0, 0, 0, 0, 206, 247, 109, 156, 0, 0, ++ 0, 0, 230, 247, 152, 154, 0, 0, 0, 0, 205, 247, 170, 159, 0, 0, 0, 0, ++ 205, 247, 96, 155, 0, 0, 0, 0, 203, 247, 110, 154, 0, 0, 0, 0, 203, ++ 247, 110, 153, 0, 0, 0, 0, 202, 247, 94, 159, 0, 0, 0, 0, 212, 247, ++ 0, 154, 0, 0, 0, 0, 211, 247, 30, 158, 0, 0, 0, 0, 211, 247, 211, 157, ++ 0, 0, 0, 0, 211, 247, 34, 157, 0, 0, 0, 0, 225, 247, 242, 156, 0, 0, ++ 0, 0, 229, 247, 211, 154, 0, 0, 0, 0, 232, 247, 226, 157, 0, 0, 0, 0, ++ 210, 247, 37, 155, 0, 0, 0, 0, 210, 247, 120, 154, 0, 0, 0, 0, 210, ++ 247, 139, 153, 0, 0, 0, 0, 216, 247, 156, 154, 0, 0, 0, 0, 232, 247, ++ 92, 153, 0, 0, 0, 0, 231, 247, 0, 156, 0, 0, 0, 0, 225, 247, 116, 153, ++ 0, 0, 0, 0, 223, 247, 51, 158, 0, 0, 0, 0, 225, 247, 218, 152, 0, 0, ++ 0, 0, 211, 247, 198, 157, 0, 0, 0, 0, 211, 247, 236, 156, 0, 0, 0, 0, ++ 211, 247, 252, 155, 0, 0, 0, 0, 210, 247, 30, 158, 0, 0, 0, 0, 210, ++ 247, 174, 152, 0, 0, 0, 0, 231, 247, 168, 158, 0, 0, 0, 0, 229, 247, ++ 196, 152, 0, 0, 0, 0, 226, 247, 28, 153, 0, 0, 0, 0, 229, 247, 8, 158, ++ 0, 0, 0, 0, 226, 247, 112, 159, 0, 0, 0, 0, 211, 247, 170, 159, 0, 0, ++ 0, 0, 229, 247, 29, 156, 0, 0, 0, 0, 226, 247, 69, 158, 0, 0, 0, 0, ++ 226, 247, 91, 156, 0, 0, 0, 0, 223, 247, 162, 152, 0, 0, 0, 0, 210, ++ 247, 186, 152, 0, 0, 0, 0, 210, 247, 71, 159, 0, 0, 0, 0, 210, 247, ++ 28, 157, 0, 0, 0, 0, 210, 247, 30, 156, 0, 0, 0, 0, 210, 247, 47, 156, ++ 0, 0, 0, 0, 226, 247, 100, 154, 0, 0, 0, 0, 229, 247, 212, 154, 0, 0, ++ 0, 0, 202, 247, 210, 157, 0, 0, 0, 0, 202, 247, 25, 152, 0, 0, 0, 0, ++ 207, 247, 139, 153, 0, 0, 0, 0, 201, 247, 240, 159, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 212, 8, 128, 0, 4, 0, 0, 0, 0, 16, ++ 0, 0, 24, 67, 128, 0, 4, 0, 0, 0, 8, 16, 0, 0, 144, 67, 128, 0, 4, 0, ++ 0, 0, 16, 16, 0, 0, 156, 83, 128, 0, 4, 0, 0, 0, 24, 16, 0, 0, 4, 85, ++ 128, 0, 4, 0, 0, 0, 32, 16, 0, 0, 52, 111, 128, 0, 4, 0, 0, 0, 40, 16, ++ 0, 0, 52, 114, 128, 0, 4, 0, 0, 0, 48, 16, 0, 0, 168, 132, 128, 0, 4, ++ 0, 0, 0, 56, 16, 0, 0, 180, 132, 128, 0, 4, 0, 0, 0, 64, 16, 0, 0, 208, ++ 123, 128, 0, 4, 0, 0, 0, 72, 16, 0, 0, 80, 124, 128, 0, 4, 0, 0, 0, ++ 80, 16, 0, 0, 112, 134, 128, 0, 4, 0, 0, 0, 88, 16, 0, 0, 36, 78, 128, ++ 0, 4, 0, 0, 0, 96, 16, 0, 0, 148, 133, 128, 0, 4, 0, 0, 0, 104, 16, ++ 0, 0, 16, 54, 128, 0, 4, 0, 0, 0, 112, 16, 0, 0, 208, 66, 131, 0, 4, ++ 0, 0, 0, 120, 16, 0, 0, 120, 190, 128, 0, 4, 0, 0, 0, 128, 16, 0, 0, ++ 0, 198, 128, 0, 4, 0, 0, 0, 136, 16, 0, 0, 104, 200, 128, 0, 4, 0, 0, ++ 0, 144, 16, 0, 0, 76, 229, 128, 0, 4, 0, 0, 0, 152, 16, 0, 0, 104, 230, ++ 128, 0, 4, 0, 0, 0, 160, 16, 0, 0, 8, 233, 128, 0, 4, 0, 0, 0, 168, ++ 16, 0, 0, 180, 235, 128, 0, 4, 0, 0, 0, 176, 16, 0, 0, 180, 54, 129, ++ 0, 4, 0, 0, 0, 184, 16, 0, 0, 0, 57, 129, 0, 4, 0, 0, 0, 192, 16, 0, ++ 0, 232, 147, 129, 0, 4, 0, 0, 0, 200, 16, 0, 0, 208, 149, 129, 0, 4, ++ 0, 0, 0, 208, 16, 0, 0, 236, 152, 129, 0, 4, 0, 0, 0, 216, 16, 0, 0, ++ 136, 160, 129, 0, 4, 0, 0, 0, 224, 16, 0, 0, 132, 162, 129, 0, 4, 0, ++ 0, 0, 232, 16, 0, 0, 16, 244, 129, 0, 4, 0, 0, 0, 240, 16, 0, 0, 72, ++ 247, 129, 0, 4, 0, 0, 0, 248, 16, 0, 0, 88, 248, 129, 0, 4, 0, 0, 0, ++ 0, 17, 0, 0, 104, 43, 130, 0, 4, 0, 0, 0, 8, 17, 0, 0, 136, 45, 130, ++ 0, 4, 0, 0, 0, 16, 17, 0, 0, 220, 50, 130, 0, 4, 0, 0, 0, 24, 17, 0, ++ 0, 36, 25, 131, 0, 4, 0, 0, 0, 32, 17, 0, 0, 228, 65, 130, 0, 4, 0, ++ 0, 0, 40, 17, 0, 0, 96, 45, 131, 0, 4, 0, 0, 0, 48, 17, 0, 0, 232, 50, ++ 131, 0, 4, 0, 0, 0, 56, 17, 0, 0, 76, 55, 131, 0, 4, 0, 0, 0, 64, 17, ++ 0, 0, 152, 59, 131, 0, 4, 0, 0, 0, 72, 17, 0, 0, 24, 61, 131, 0, 4, ++ 0, 0, 0, 80, 17, 0, 0, 200, 61, 131, 0, 4, 0, 0, 0, 88, 17, 0, 0, 8, ++ 64, 131, 0, 4, 0, 0, 0, 96, 17, 0, 0, 52, 79, 131, 0, 4, 0, 0, 0, 104, ++ 17, 0, 0, 20, 82, 131, 0, 4, 0, 0, 0, 112, 17, 0, 0, 16, 83, 131, 0, ++ 4, 0, 0, 0, 120, 17, 0, 0, 152, 107, 131, 0, 4, 0, 0, 0, 128, 17, 0, ++ 0, 16, 122, 131, 0, 4, 0, 0, 0, 136, 17, 0, 0, 228, 130, 131, 0, 4, ++ 0, 0, 0, 144, 17, 0, 0, 252, 131, 131, 0, 4, 0, 0, 0, 152, 17, 0, 0, ++ 156, 146, 131, 0, 4, 0, 0, 0, 160, 17, 0, 0, 44, 164, 131, 0, 4, 0, ++ 0, 0, 168, 17, 0, 0, 96, 165, 131, 0, 4, 0, 0, 0, 176, 17, 0, 0, 200, ++ 165, 131, 0, 4, 0, 0, 0, 184, 17, 0, 0, 104, 167, 131, 0, 4, 0, 0, 0, ++ 192, 17, 0, 0, 28, 169, 131, 0, 4, 0, 0, 0, 200, 17, 0, 0, 224, 174, ++ 131, 0, 4, 0, 0, 0, 208, 17, 0, 0, 168, 175, 131, 0, 4, 0, 0, 0, 216, ++ 17, 0, 0, 196, 177, 131, 0, 4, 0, 0, 0, 224, 17, 0, 0, 48, 184, 131, ++ 0, 4, 0, 0, 0, 232, 17, 0, 0, 252, 191, 131, 0, 4, 0, 0, 0, 240, 17, ++ 0, 0, 188, 196, 131, 0, 4, 0, 0, 0, 248, 17, 0, 0, 68, 217, 131, 0, ++ 4, 0, 0, 0, 0, 18, 0, 0, 184, 238, 131, 0, 4, 0, 0, 0, 8, 18, 0, 0, ++ 100, 246, 131, 0, 4, 0, 0, 0, 16, 18, 0, 0, 64, 41, 132, 0, 4, 0, 0, ++ 0, 24, 18, 0, 0, 212, 45, 132, 0, 4, 0, 0, 0, 32, 18, 0, 0, 16, 48, ++ 132, 0, 4, 0, 0, 0, 40, 18, 0, 0, 236, 48, 132, 0, 4, 0, 0, 0, 48, 18, ++ 0, 0, 172, 253, 131, 0, 4, 0, 0, 0, 56, 18, 0, 0, 196, 69, 130, 0, 4, ++ 0, 0, 0, 64, 18, 0, 0, 80, 67, 132, 0, 4, 0, 0, 0, 72, 18, 0, 0, 116, ++ 73, 132, 0, 4, 0, 0, 0, 80, 18, 0, 0, 140, 75, 132, 0, 4, 0, 0, 0, 88, ++ 18, 0, 0, 60, 77, 132, 0, 4, 0, 0, 0, 96, 18, 0, 0, 184, 77, 132, 0, ++ 4, 0, 0, 0, 104, 18, 0, 0, 184, 85, 132, 0, 4, 0, 0, 0, 112, 18, 0, ++ 0, 108, 97, 132, 0, 4, 0, 0, 0, 120, 18, 0, 0, 76, 99, 132, 0, 4, 0, ++ 0, 0, 128, 18, 0, 0, 252, 101, 132, 0, 4, 0, 0, 0, 136, 18, 0, 0, 148, ++ 110, 132, 0, 4, 0, 0, 0, 144, 18, 0, 0, 212, 112, 132, 0, 4, 0, 0, 0, ++ 152, 18, 0, 0, 204, 115, 132, 0, 4, 0, 0, 0, 160, 18, 0, 0, 16, 122, ++ 132, 0, 4, 0, 0, 0, 168, 18, 0, 0, 204, 123, 132, 0, 4, 0, 0, 0, 176, ++ 18, 0, 0, 152, 125, 132, 0, 4, 0, 0, 0, 184, 18, 0, 0, 172, 133, 132, ++ 0, 4, 0, 0, 0, 192, 18, 0, 0, 120, 135, 132, 0, 4, 0, 0, 0, 200, 18, ++ 0, 0, 128, 135, 132, 0, 4, 0, 0, 0, 208, 18, 0, 0, 228, 185, 132, 0, ++ 4, 0, 0, 0, 216, 18, 0, 0, 36, 234, 132, 0, 4, 0, 0, 0, 224, 18, 0, ++ 0, 108, 241, 132, 0, 4, 0, 0, 0, 232, 18, 0, 0, 44, 242, 132, 0, 4, ++ 0, 0, 0, 240, 18, 0, 0, 92, 104, 132, 0, 4, 0, 0, 0, 248, 18, 0, 0, ++ 132, 242, 132, 0, 4, 0, 0, 0, 0, 19, 0, 0, 168, 11, 133, 0, 4, 0, 0, ++ 0, 8, 19, 0, 0, 64, 17, 133, 0, 4, 0, 0, 0, 16, 19, 0, 0, 144, 17, 133, ++ 0, 4, 0, 0, 0, 24, 19, 0, 0, 96, 87, 130, 0, 4, 0, 0, 0, 32, 19, 0, ++ 0, 72, 243, 132, 0, 4, 0, 0, 0, 40, 19, 0, 0, 48, 146, 132, 0, 4, 0, ++ 0, 0, 48, 19, 0, 0, 252, 156, 130, 0, 4, 0, 0, 0, 56, 19, 0, 0, 140, ++ 21, 133, 0, 4, 0, 0, 0, 64, 19, 0, 0, 0, 25, 133, 0, 4, 0, 0, 0, 72, ++ 19, 0, 0, 20, 25, 133, 0, 4, 0, 0, 0, 80, 19, 0, 0, 80, 25, 133, 0, ++ 4, 0, 0, 0, 88, 19, 0, 0, 120, 25, 133, 0, 4, 0, 0, 0, 96, 19, 0, 0, ++ 60, 27, 133, 0, 4, 0, 0, 0, 104, 19, 0, 0, 248, 28, 133, 0, 4, 0, 0, ++ 0, 112, 19, 0, 0, 252, 32, 133, 0, 4, 0, 0, 0, 120, 19, 0, 0, 104, 39, ++ 133, 0, 4, 0, 0, 0, 128, 19, 0, 0, 208, 39, 133, 0, 4, 0, 0, 0, 136, ++ 19, 0, 0, 132, 244, 132, 0, 4, 0, 0, 0, 144, 19, 0, 0, 16, 163, 130, ++ 0, 4, 0, 0, 0, 152, 19, 0, 0, 48, 65, 133, 0, 4, 0, 0, 0, 160, 19, 0, ++ 0, 32, 80, 133, 0, 4, 0, 0, 0, 168, 19, 0, 0, 16, 78, 133, 0, 4, 0, ++ 0, 0, 176, 19, 0, 0, 92, 169, 130, 0, 4, 0, 0, 0, 184, 19, 0, 0, 236, ++ 171, 130, 0, 4, 0, 0, 0, 192, 19, 0, 0, 184, 174, 130, 0, 4, 0, 0, 0, ++ 200, 19, 0, 0, 204, 10, 132, 0, 4, 0, 0, 0, 208, 19, 0, 0, 240, 17, ++ 132, 0, 4, 0, 0, 0, 216, 19, 0, 0, 52, 111, 133, 0, 4, 0, 0, 0, 224, ++ 19, 0, 0, 228, 115, 133, 0, 4, 0, 0, 0, 232, 19, 0, 0, 144, 126, 133, ++ 0, 4, 0, 0, 0, 240, 19, 0, 0, 132, 175, 130, 0, 4, 0, 0, 0, 248, 19, ++ 0, 0, 252, 177, 130, 0, 4, 0, 0, 0, 0, 20, 0, 0, 116, 148, 133, 0, 4, ++ 0, 0, 0, 8, 20, 0, 0, 8, 150, 133, 0, 4, 0, 0, 0, 16, 20, 0, 0, 160, ++ 150, 133, 0, 4, 0, 0, 0, 24, 20, 0, 0, 88, 171, 133, 0, 4, 0, 0, 0, ++ 32, 20, 0, 0, 164, 189, 133, 0, 4, 0, 0, 0, 40, 20, 0, 0, 120, 190, ++ 133, 0, 4, 0, 0, 0, 48, 20, 0, 0, 4, 194, 133, 0, 4, 0, 0, 0, 56, 20, ++ 0, 0, 88, 194, 133, 0, 4, 0, 0, 0, 64, 20, 0, 0, 216, 195, 133, 0, 4, ++ 0, 0, 0, 72, 20, 0, 0, 136, 196, 133, 0, 4, 0, 0, 0, 80, 20, 0, 0, 252, ++ 198, 133, 0, 4, 0, 0, 0, 88, 20, 0, 0, 112, 201, 133, 0, 4, 0, 0, 0, ++ 96, 20, 0, 0, 132, 208, 133, 0, 4, 0, 0, 0, 104, 20, 0, 0, 72, 210, ++ 133, 0, 4, 0, 0, 0, 112, 20, 0, 0, 216, 213, 133, 0, 4, 0, 0, 0, 120, ++ 20, 0, 0, 16, 222, 133, 0, 4, 0, 0, 0, 128, 20, 0, 0, 24, 228, 133, ++ 0, 4, 0, 0, 0, 136, 20, 0, 0, 148, 180, 130, 0, 4, 0, 0, 0, 144, 20, ++ 0, 0, 64, 241, 133, 0, 4, 0, 0, 0, 152, 20, 0, 0, 96, 248, 133, 0, 4, ++ 0, 0, 0, 160, 20, 0, 0, 168, 24, 134, 0, 4, 0, 0, 0, 168, 20, 0, 0, ++ 64, 27, 134, 0, 4, 0, 0, 0, 176, 20, 0, 0, 132, 34, 134, 0, 4, 0, 0, ++ 0, 184, 20, 0, 0, 136, 51, 134, 0, 4, 0, 0, 0, 192, 20, 0, 0, 76, 61, ++ 134, 0, 4, 0, 0, 0, 200, 20, 0, 0, 128, 62, 134, 0, 4, 0, 0, 0, 208, ++ 20, 0, 0, 16, 63, 134, 0, 4, 0, 0, 0, 216, 20, 0, 0, 48, 197, 130, 0, ++ 4, 0, 0, 0, 224, 20, 0, 0, 128, 197, 130, 0, 4, 0, 0, 0, 232, 20, 0, ++ 0, 172, 200, 130, 0, 4, 0, 0, 0, 240, 20, 0, 0, 204, 97, 134, 0, 4, ++ 0, 0, 0, 248, 20, 0, 0, 164, 98, 134, 0, 4, 0, 0, 0, 0, 21, 0, 0, 124, ++ 99, 134, 0, 4, 0, 0, 0, 8, 21, 0, 0, 132, 18, 133, 0, 4, 0, 0, 0, 16, ++ 21, 0, 0, 12, 111, 131, 0, 4, 0, 0, 0, 24, 21, 0, 0, 236, 208, 130, ++ 0, 4, 0, 0, 0, 32, 21, 0, 0, 116, 28, 132, 0, 4, 0, 0, 0, 40, 21, 0, ++ 0, 140, 31, 132, 0, 4, 0, 0, 0, 48, 21, 0, 0, 24, 34, 132, 0, 4, 0, ++ 0, 0, 56, 21, 0, 0, 200, 144, 134, 0, 4, 0, 0, 0, 64, 21, 0, 0, 20, ++ 146, 134, 0, 4, 0, 0, 0, 72, 21, 0, 0, 156, 147, 134, 0, 4, 0, 0, 0, ++ 80, 21, 0, 0, 220, 165, 134, 0, 4, 0, 0, 0, 88, 21, 0, 0, 12, 185, 134, ++ 0, 4, 0, 0, 0, 96, 21, 0, 0, 20, 217, 130, 0, 4, 0, 0, 0, 104, 21, 0, ++ 0, 196, 221, 130, 0, 4, 0, 0, 0, 112, 21, 0, 0, 84, 235, 130, 0, 4, ++ 0, 0, 0, 120, 21, 0, 0, 84, 236, 130, 0, 4, 0, 0, 0, 128, 21, 0, 0, ++ 16, 237, 130, 0, 4, 0, 0, 0, 136, 21, 0, 0, 72, 202, 134, 0, 4, 0, 0, ++ 0, 144, 21, 0, 0, 120, 237, 130, 0, 4, 0, 0, 0, 152, 21, 0, 0, 240, ++ 238, 130, 0, 4, 0, 0, 0, 160, 21, 0, 0, 224, 241, 130, 0, 4, 0, 0, 0, ++ 168, 21, 0, 0, 176, 36, 132, 0, 4, 0, 0, 0, 176, 21, 0, 0, 8, 217, 134, ++ 0, 4, 0, 0, 0, 184, 21, 0, 0, 128, 220, 134, 0, 4, 0, 0, 0, 192, 21, ++ 0, 0, 248, 220, 134, 0, 4, 0, 0, 0, 200, 21, 0, 0, 16, 222, 134, 0, ++ 4, 0, 0, 0, 208, 21, 0, 0, 216, 223, 134, 0, 4, 0, 0, 0, 216, 21, 0, ++ 0, 68, 254, 130, 0, 4, 0, 0, 0, 224, 21, 0, 0, 20, 0, 131, 0, 4, 0, ++ 0, 0, 232, 21, 0, 0, 52, 104, 135, 0, 4, 0, 0, 0, 240, 21, 0, 0, 184, ++ 47, 134, 0, 4, 0, 0, 0, 248, 21, 0, 0, 252, 196, 133, 0, 4, 0, 0, 0, ++ 0, 22, 0, 0, 216, 116, 135, 0, 4, 0, 0, 0, 8, 22, 0, 0, 104, 70, 131, ++ 105, 65, 105, 11, 181, 3, 105, 90, 70, 81, 70, 14, 180, 74, 70, 65, ++ 70, 6, 180, 195, 104, 130, 104, 65, 104, 254, 180, 3, 104, 194, 105, ++ 239, 243, 3, 129, 14, 180, 130, 105, 239, 243, 5, 129, 6, 180, 3, 72, ++ 1, 104, 0, 41, 254, 208, 104, 70, 136, 71, 20, 176, 0, 189, 196, 33, ++ 0, 0, 98, 182, 112, 71, 114, 182, 112, 71, 4, 73, 8, 64, 0, 40, 3, 208, ++ 3, 73, 10, 104, 2, 67, 10, 96, 112, 71, 0, 0, 255, 255, 0, 0, 0, 225, ++ 0, 224, 4, 73, 8, 64, 0, 40, 4, 208, 3, 73, 10, 104, 192, 67, 2, 64, ++ 10, 96, 112, 71, 255, 255, 0, 0, 128, 225, 0, 224, 2, 73, 9, 104, 144, ++ 34, 136, 88, 112, 71, 0, 0, 204, 33, 0, 0, 2, 73, 9, 104, 156, 34, 136, ++ 80, 112, 71, 0, 0, 204, 33, 0, 0, 221, 186, 173, 187, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 2, 74, 17, 104, 16, 96, 8, 28, 112, 71, 0, 0, 196, 33, 0, 0, 86, 72, ++ 87, 73, 0, 34, 10, 80, 1, 104, 86, 74, 10, 64, 86, 79, 15, 64, 63, 66, ++ 6, 209, 80, 70, 0, 66, 2, 208, 64, 70, 0, 66, 41, 209, 254, 231, 252, ++ 33, 65, 88, 10, 104, 15, 35, 19, 64, 15, 43, 241, 208, 1, 43, 1, 208, ++ 4, 49, 246, 231, 8, 49, 75, 75, 19, 64, 75, 76, 163, 66, 6, 209, 0, ++ 240, 193, 248, 128, 70, 0, 240, 202, 248, 129, 70, 233, 231, 71, 76, ++ 163, 66, 230, 209, 11, 31, 27, 104, 70, 76, 35, 64, 24, 36, 227, 64, ++ 156, 70, 0, 240, 176, 248, 130, 70, 0, 240, 185, 248, 131, 70, 216, ++ 231, 65, 73, 33, 34, 66, 80, 55, 74, 64, 73, 137, 88, 255, 35, 25, 66, ++ 25, 208, 81, 104, 62, 75, 25, 66, 21, 208, 17, 104, 52, 75, 25, 64, ++ 211, 106, 16, 224, 163, 66, 14, 208, 192, 70, 12, 224, 57, 73, 137, ++ 88, 25, 66, 8, 208, 56, 73, 137, 88, 25, 64, 153, 66, 250, 209, 54, ++ 75, 17, 105, 25, 66, 252, 208, 73, 70, 63, 66, 4, 209, 152, 35, 203, ++ 88, 16, 36, 227, 64, 1, 224, 49, 75, 203, 88, 28, 36, 35, 64, 0, 43, ++ 1, 208, 0, 240, 146, 248, 64, 70, 46, 73, 8, 96, 72, 70, 45, 73, 8, ++ 96, 80, 70, 45, 73, 8, 96, 96, 70, 44, 73, 8, 96, 44, 73, 15, 96, 44, ++ 77, 45, 73, 13, 96, 45, 72, 45, 73, 0, 34, 4, 192, 129, 66, 252, 216, ++ 4, 61, 173, 70, 0, 157, 236, 67, 16, 35, 221, 65, 172, 66, 16, 209, ++ 36, 12, 164, 0, 39, 77, 44, 96, 107, 70, 27, 27, 38, 72, 38, 77, 40, ++ 96, 0, 44, 5, 208, 29, 104, 5, 96, 4, 51, 4, 48, 4, 60, 249, 220, 129, ++ 176, 34, 75, 27, 73, 13, 104, 237, 26, 13, 96, 108, 70, 228, 26, 165, ++ 70, 104, 70, 0, 9, 0, 1, 133, 70, 2, 240, 197, 250, 254, 231, 0, 0, ++ 0, 24, 20, 6, 0, 0, 255, 255, 0, 0, 0, 0, 0, 240, 0, 255, 15, 0, 0, ++ 42, 8, 0, 0, 14, 8, 0, 0, 0, 0, 255, 224, 1, 0, 0, 4, 6, 0, 0, 0, 0, ++ 56, 0, 24, 6, 0, 0, 12, 6, 0, 0, 0, 16, 0, 0, 8, 4, 0, 0, 204, 33, 0, ++ 0, 208, 33, 0, 0, 212, 33, 0, 0, 216, 33, 0, 0, 200, 33, 0, 0, 0, 0, ++ 8, 0, 64, 93, 4, 0, 36, 109, 4, 0, 20, 116, 4, 0, 72, 93, 4, 0, 240, ++ 120, 5, 0, 68, 93, 4, 0, 0, 0, 1, 0, 8, 104, 15, 34, 4, 49, 2, 64, 5, ++ 42, 249, 209, 1, 74, 16, 64, 247, 70, 0, 0, 0, 240, 255, 255, 8, 104, ++ 15, 34, 4, 49, 2, 64, 5, 42, 249, 209, 128, 34, 16, 66, 246, 208, 1, ++ 74, 16, 64, 247, 70, 0, 240, 255, 255, 254, 231, 48, 181, 0, 35, 6, ++ 224, 197, 92, 204, 92, 165, 66, 6, 211, 3, 241, 1, 3, 6, 216, 147, 66, ++ 246, 209, 0, 32, 48, 189, 79, 240, 255, 48, 48, 189, 1, 32, 48, 189, ++ 3, 42, 45, 233, 240, 79, 131, 70, 77, 217, 72, 64, 16, 240, 3, 0, 75, ++ 209, 75, 66, 3, 240, 3, 3, 210, 26, 3, 224, 12, 92, 11, 248, 0, 64, ++ 1, 48, 152, 66, 249, 209, 31, 42, 11, 235, 0, 3, 1, 68, 10, 217, 34, ++ 240, 31, 0, 8, 24, 177, 232, 240, 23, 163, 232, 240, 23, 136, 66, 249, ++ 216, 2, 240, 31, 2, 144, 8, 1, 56, 6, 40, 39, 216, 223, 232, 0, 240, ++ 4, 9, 14, 19, 24, 29, 34, 0, 8, 104, 24, 96, 4, 49, 4, 51, 28, 224, ++ 177, 232, 17, 0, 163, 232, 17, 0, 23, 224, 177, 232, 49, 0, 163, 232, ++ 49, 0, 18, 224, 177, 232, 113, 0, 163, 232, 113, 0, 13, 224, 177, 232, ++ 241, 0, 163, 232, 241, 0, 8, 224, 177, 232, 241, 16, 163, 232, 241, ++ 16, 3, 224, 177, 232, 241, 17, 163, 232, 241, 17, 2, 240, 3, 2, 2, 224, ++ 3, 70, 0, 224, 91, 70, 0, 32, 2, 224, 12, 92, 28, 84, 1, 48, 144, 66, ++ 250, 209, 88, 70, 189, 232, 240, 143, 0, 72, 112, 71, 36, 109, 4, 0, ++ 0, 72, 112, 71, 100, 109, 4, 0, 0, 72, 112, 71, 200, 109, 4, 0, 16, ++ 181, 4, 70, 255, 247, 248, 255, 3, 104, 19, 177, 64, 104, 33, 70, 152, ++ 71, 16, 189, 0, 72, 112, 71, 112, 109, 4, 0, 9, 240, 198, 186, 1, 35, ++ 139, 64, 45, 233, 247, 79, 179, 245, 0, 31, 40, 191, 79, 244, 0, 19, ++ 4, 43, 56, 191, 4, 35, 3, 48, 1, 147, 32, 240, 3, 4, 255, 247, 214, ++ 255, 53, 75, 0, 34, 211, 248, 0, 176, 21, 70, 148, 70, 19, 70, 39, 224, ++ 209, 248, 0, 160, 162, 69, 34, 211, 1, 241, 8, 7, 1, 158, 7, 235, 10, ++ 8, 198, 241, 0, 9, 196, 235, 8, 6, 9, 234, 6, 6, 190, 66, 21, 211, 221, ++ 248, 4, 144, 9, 241, 255, 57, 25, 234, 7, 15, 205, 248, 0, 144, 2, 208, ++ 247, 27, 7, 47, 9, 217, 196, 235, 10, 7, 95, 69, 5, 210, 66, 70, 53, ++ 70, 111, 177, 187, 70, 132, 70, 11, 70, 8, 70, 65, 104, 0, 41, 212, ++ 209, 59, 185, 28, 74, 24, 70, 17, 104, 1, 49, 17, 96, 47, 224, 132, ++ 70, 11, 70, 82, 27, 17, 27, 7, 41, 9, 217, 24, 104, 42, 25, 64, 26, ++ 8, 57, 24, 96, 41, 81, 89, 104, 81, 96, 90, 96, 34, 70, 25, 104, 137, ++ 26, 7, 41, 3, 216, 90, 104, 204, 248, 4, 32, 4, 224, 90, 80, 161, 241, ++ 8, 2, 26, 96, 91, 24, 12, 72, 0, 34, 25, 104, 90, 96, 2, 104, 138, 24, ++ 2, 96, 9, 72, 1, 104, 8, 49, 1, 96, 137, 24, 8, 74, 16, 104, 129, 66, ++ 136, 191, 17, 96, 3, 241, 8, 0, 189, 232, 254, 143, 44, 7, 0, 0, 40, ++ 7, 0, 0, 76, 7, 0, 0, 120, 7, 0, 0, 108, 109, 4, 0, 56, 181, 25, 75, ++ 80, 248, 8, 44, 25, 104, 5, 70, 138, 26, 26, 96, 22, 75, 160, 241, 8, ++ 4, 26, 104, 8, 58, 26, 96, 255, 247, 80, 255, 2, 224, 163, 66, 3, 210, ++ 24, 70, 67, 104, 0, 43, 249, 209, 85, 248, 8, 44, 169, 24, 139, 66, ++ 5, 209, 25, 104, 91, 104, 82, 24, 8, 50, 69, 248, 8, 44, 99, 96, 3, ++ 104, 3, 241, 8, 2, 130, 24, 162, 66, 7, 209, 85, 248, 8, 44, 155, 24, ++ 8, 51, 3, 96, 99, 104, 67, 96, 0, 224, 68, 96, 0, 32, 56, 189, 76, 7, ++ 0, 0, 120, 7, 0, 0, 16, 181, 0, 33, 64, 34, 4, 70, 1, 240, 62, 218, ++ 16, 75, 35, 96, 16, 75, 99, 96, 16, 75, 163, 96, 16, 75, 227, 96, 16, ++ 75, 35, 97, 16, 75, 99, 97, 16, 75, 163, 97, 16, 75, 227, 97, 16, 75, ++ 35, 98, 16, 75, 99, 98, 16, 75, 163, 98, 16, 75, 227, 98, 16, 75, 35, ++ 99, 16, 75, 99, 99, 16, 75, 163, 99, 16, 75, 227, 99, 16, 189, 0, 191, ++ 0, 0, 0, 0, 226, 20, 4, 0, 228, 20, 4, 0, 61, 93, 4, 0, 64, 93, 4, 0, ++ 34, 109, 4, 0, 36, 109, 4, 0, 20, 116, 4, 0, 20, 116, 4, 0, 168, 183, ++ 5, 0, 168, 183, 5, 0, 180, 107, 6, 0, 252, 0, 0, 0, 0, 1, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 240, 181, 45, 77, 145, 176, 104, 70, 255, 247, 178, ++ 255, 41, 120, 0, 41, 55, 209, 8, 152, 9, 156, 36, 26, 6, 208, 34, 70, ++ 1, 240, 236, 217, 8, 152, 33, 70, 5, 240, 2, 218, 34, 70, 36, 73, 36, ++ 72, 1, 240, 9, 218, 36, 75, 0, 36, 28, 112, 1, 35, 43, 112, 34, 77, ++ 5, 240, 47, 217, 43, 104, 0, 43, 51, 208, 26, 120, 0, 42, 48, 208, 159, ++ 137, 94, 137, 12, 224, 43, 104, 29, 74, 217, 137, 16, 104, 8, 240, 118, ++ 254, 1, 52, 1, 70, 48, 177, 24, 75, 24, 104, 2, 240, 29, 217, 163, 25, ++ 187, 66, 239, 219, 22, 75, 41, 104, 24, 104, 1, 34, 6, 240, 142, 253, ++ 22, 224, 20, 78, 49, 120, 153, 185, 10, 152, 11, 156, 36, 26, 6, 208, ++ 34, 70, 1, 240, 177, 217, 10, 152, 33, 70, 5, 240, 199, 217, 8, 72, ++ 13, 73, 34, 70, 1, 240, 206, 217, 0, 35, 43, 112, 1, 35, 51, 112, 5, ++ 240, 246, 216, 17, 176, 240, 189, 52, 7, 0, 0, 226, 216, 135, 0, 235, ++ 22, 4, 0, 124, 109, 4, 0, 116, 7, 0, 0, 16, 111, 4, 0, 252, 109, 4, ++ 0, 216, 109, 4, 0, 144, 204, 135, 0, 1, 75, 24, 104, 112, 71, 0, 191, ++ 64, 93, 4, 0, 0, 32, 112, 71, 127, 181, 13, 74, 13, 75, 21, 104, 13, ++ 74, 27, 104, 20, 104, 13, 74, 18, 104, 122, 177, 22, 120, 110, 177, ++ 235, 24, 227, 26, 3, 245, 126, 116, 7, 52, 164, 10, 0, 148, 20, 137, ++ 1, 148, 82, 137, 2, 146, 6, 74, 1, 240, 210, 217, 127, 189, 0, 191, ++ 120, 7, 0, 0, 76, 7, 0, 0, 44, 7, 0, 0, 116, 7, 0, 0, 22, 22, 136, 0, ++ 8, 181, 131, 106, 51, 177, 0, 35, 131, 98, 128, 248, 32, 48, 16, 48, ++ 5, 240, 156, 217, 1, 32, 8, 189, 112, 181, 35, 78, 48, 104, 0, 40, 64, ++ 208, 11, 240, 131, 222, 1, 32, 5, 240, 158, 219, 1, 32, 255, 247, 51, ++ 254, 1, 36, 22, 224, 29, 75, 28, 104, 9, 224, 227, 104, 29, 66, 5, 208, ++ 37, 234, 3, 5, 99, 104, 11, 177, 160, 104, 152, 71, 36, 104, 13, 177, ++ 0, 44, 242, 209, 5, 240, 243, 216, 21, 75, 4, 70, 24, 104, 5, 240, 106, ++ 219, 48, 104, 12, 240, 207, 216, 18, 75, 29, 104, 5, 64, 225, 209, 0, ++ 44, 223, 209, 16, 77, 43, 104, 35, 177, 27, 104, 19, 177, 88, 104, 5, ++ 240, 179, 220, 43, 104, 35, 177, 27, 104, 19, 177, 91, 104, 0, 43, 231, ++ 208, 0, 32, 255, 247, 255, 253, 0, 32, 189, 232, 112, 64, 5, 240, 98, ++ 155, 112, 189, 0, 191, 56, 7, 0, 0, 112, 7, 0, 0, 64, 7, 0, 0, 72, 7, ++ 0, 0, 100, 7, 0, 0, 2, 75, 26, 104, 1, 50, 26, 96, 112, 71, 0, 191, ++ 212, 109, 4, 0, 1, 75, 24, 104, 112, 71, 0, 191, 212, 109, 4, 0, 45, ++ 233, 240, 79, 157, 176, 10, 168, 255, 247, 170, 254, 255, 247, 94, 255, ++ 4, 70, 255, 247, 97, 255, 10, 155, 11, 154, 15, 153, 210, 26, 14, 155, ++ 13, 157, 195, 235, 1, 9, 17, 153, 16, 155, 110, 78, 203, 26, 12, 153, ++ 223, 248, 0, 130, 193, 235, 5, 11, 147, 68, 50, 104, 216, 248, 0, 16, ++ 2, 245, 0, 82, 82, 26, 74, 68, 210, 24, 90, 68, 20, 25, 36, 24, 9, 148, ++ 223, 248, 228, 161, 100, 76, 100, 79, 34, 104, 218, 248, 0, 80, 99, ++ 72, 173, 24, 58, 104, 8, 147, 197, 235, 2, 12, 205, 248, 28, 192, 1, ++ 240, 224, 216, 8, 155, 9, 245, 126, 113, 1, 147, 3, 245, 126, 115, 7, ++ 51, 155, 10, 7, 49, 11, 245, 126, 114, 137, 10, 7, 50, 2, 147, 8, 35, ++ 146, 10, 0, 145, 3, 147, 89, 70, 75, 70, 85, 72, 1, 240, 201, 216, 51, ++ 104, 32, 104, 57, 104, 221, 248, 28, 192, 1, 144, 3, 147, 0, 245, 126, ++ 112, 3, 245, 126, 115, 12, 245, 126, 118, 1, 245, 126, 114, 7, 48, 7, ++ 51, 128, 10, 155, 10, 7, 50, 7, 54, 182, 10, 146, 10, 2, 144, 4, 147, ++ 72, 72, 99, 70, 0, 150, 1, 240, 171, 216, 9, 153, 5, 245, 126, 114, ++ 1, 245, 126, 115, 7, 51, 155, 10, 7, 50, 146, 10, 0, 147, 41, 70, 9, ++ 155, 65, 72, 1, 240, 156, 216, 64, 75, 65, 79, 25, 104, 65, 72, 1, 240, ++ 150, 216, 57, 104, 64, 75, 10, 104, 70, 70, 154, 66, 3, 208, 62, 72, ++ 1, 240, 141, 216, 37, 224, 26, 145, 11, 70, 4, 224, 21, 104, 57, 72, ++ 19, 29, 133, 66, 3, 209, 26, 70, 27, 171, 154, 66, 246, 211, 51, 104, ++ 26, 173, 0, 147, 54, 72, 43, 70, 26, 146, 1, 240, 120, 216, 59, 104, ++ 26, 154, 233, 26, 51, 72, 211, 26, 10, 70, 0, 147, 1, 240, 111, 216, ++ 51, 104, 26, 154, 89, 27, 47, 72, 155, 26, 10, 70, 0, 147, 1, 240, 102, ++ 216, 45, 75, 27, 104, 75, 179, 26, 120, 58, 179, 89, 137, 221, 137, ++ 26, 137, 1, 251, 5, 246, 56, 53, 77, 67, 6, 245, 126, 115, 7, 51, 155, ++ 18, 141, 232, 40, 0, 5, 245, 126, 115, 7, 51, 155, 18, 2, 147, 35, 72, ++ 51, 70, 1, 240, 75, 216, 35, 104, 218, 248, 0, 32, 153, 27, 155, 24, ++ 91, 27, 3, 245, 126, 112, 1, 245, 126, 114, 7, 48, 128, 10, 7, 50, 0, ++ 144, 146, 10, 26, 72, 1, 240, 57, 216, 26, 75, 29, 104, 5, 240, 99, ++ 217, 4, 70, 255, 247, 18, 255, 41, 70, 3, 70, 34, 70, 22, 72, 1, 240, ++ 44, 216, 29, 176, 189, 232, 240, 143, 0, 191, 108, 109, 4, 0, 76, 7, ++ 0, 0, 44, 7, 0, 0, 30, 23, 4, 0, 45, 23, 4, 0, 108, 23, 4, 0, 177, 23, ++ 4, 0, 40, 7, 0, 0, 208, 109, 4, 0, 236, 23, 4, 0, 75, 65, 84, 83, 7, ++ 24, 4, 0, 43, 24, 4, 0, 98, 24, 4, 0, 135, 24, 4, 0, 116, 7, 0, 0, 173, ++ 24, 4, 0, 218, 24, 4, 0, 60, 7, 0, 0, 2, 25, 4, 0, 120, 109, 4, 0, 120, ++ 7, 0, 0, 16, 181, 4, 70, 8, 240, 112, 253, 0, 32, 5, 240, 101, 219, ++ 5, 240, 89, 219, 32, 70, 5, 240, 88, 219, 32, 70, 5, 240, 47, 217, 251, ++ 231, 8, 181, 113, 70, 3, 72, 0, 240, 231, 223, 1, 32, 189, 232, 8, 64, ++ 0, 240, 0, 186, 48, 25, 4, 0, 247, 181, 7, 70, 14, 70, 20, 70, 5, 240, ++ 8, 217, 88, 179, 0, 37, 32, 70, 13, 241, 6, 1, 106, 70, 173, 248, 6, ++ 80, 0, 149, 5, 240, 65, 221, 0, 152, 41, 70, 255, 247, 161, 252, 4, ++ 70, 216, 177, 41, 70, 0, 154, 0, 240, 159, 223, 99, 104, 242, 28, 103, ++ 243, 20, 3, 34, 240, 3, 2, 99, 96, 1, 58, 27, 12, 98, 243, 79, 19, 227, ++ 128, 167, 96, 166, 129, 32, 70, 5, 240, 204, 216, 1, 35, 32, 128, 163, ++ 112, 189, 248, 6, 48, 227, 129, 4, 224, 3, 75, 0, 36, 26, 104, 1, 50, ++ 26, 96, 32, 70, 254, 189, 8, 110, 4, 0, 45, 233, 243, 65, 7, 70, 12, ++ 70, 5, 240, 204, 216, 16, 185, 255, 247, 115, 254, 58, 224, 0, 38, 32, ++ 70, 13, 241, 6, 1, 106, 70, 173, 248, 6, 96, 0, 150, 7, 241, 3, 8, 5, ++ 240, 0, 221, 0, 157, 40, 240, 3, 8, 69, 68, 64, 246, 56, 3, 157, 66, ++ 38, 216, 45, 179, 40, 70, 49, 70, 255, 247, 87, 252, 4, 70, 248, 177, ++ 49, 70, 0, 154, 0, 240, 85, 223, 0, 155, 167, 129, 237, 26, 226, 24, ++ 200, 235, 5, 8, 2, 235, 8, 3, 163, 96, 99, 104, 1, 61, 98, 243, 20, ++ 3, 99, 96, 27, 12, 101, 243, 79, 19, 227, 128, 32, 70, 5, 240, 126, ++ 216, 1, 35, 32, 128, 163, 112, 189, 248, 6, 48, 227, 129, 4, 224, 4, ++ 75, 0, 36, 26, 104, 1, 50, 26, 96, 32, 70, 189, 232, 252, 129, 0, 191, ++ 8, 110, 4, 0, 56, 181, 0, 33, 5, 70, 128, 137, 255, 247, 170, 255, 4, ++ 70, 32, 177, 128, 104, 169, 104, 170, 137, 255, 247, 161, 251, 32, 70, ++ 56, 189, 45, 233, 240, 65, 6, 70, 136, 70, 23, 70, 5, 240, 108, 216, ++ 4, 70, 16, 185, 255, 247, 18, 254, 46, 224, 184, 241, 0, 15, 42, 219, ++ 0, 47, 40, 219, 60, 32, 0, 33, 255, 247, 6, 252, 4, 70, 24, 179, 243, ++ 137, 191, 178, 91, 6, 76, 191, 181, 107, 53, 70, 171, 120, 0, 33, 1, ++ 51, 171, 112, 60, 34, 0, 240, 251, 222, 178, 104, 99, 104, 66, 68, 98, ++ 243, 20, 3, 99, 96, 27, 12, 103, 243, 79, 19, 227, 128, 227, 137, 162, ++ 96, 67, 240, 64, 3, 167, 129, 227, 129, 32, 70, 5, 240, 38, 216, 165, ++ 99, 32, 128, 0, 224, 0, 36, 32, 70, 189, 232, 240, 129, 0, 0, 16, 181, ++ 1, 35, 66, 104, 131, 112, 195, 136, 194, 243, 20, 2, 2, 235, 83, 18, ++ 131, 104, 1, 50, 91, 13, 91, 5, 210, 24, 8, 75, 204, 28, 35, 64, 211, ++ 26, 131, 96, 195, 137, 129, 129, 3, 244, 12, 83, 195, 129, 0, 33, 16, ++ 48, 40, 34, 189, 232, 16, 64, 0, 240, 193, 158, 0, 191, 252, 255, 1, ++ 0, 56, 181, 4, 70, 227, 137, 89, 6, 33, 212, 162, 120, 1, 58, 210, 178, ++ 162, 112, 0, 42, 39, 209, 226, 120, 98, 177, 19, 75, 32, 70, 83, 248, ++ 34, 80, 233, 137, 255, 247, 202, 255, 40, 70, 33, 70, 189, 232, 56, ++ 64, 6, 240, 102, 186, 218, 5, 22, 212, 12, 75, 32, 70, 163, 96, 33, ++ 136, 4, 240, 246, 223, 32, 70, 189, 232, 56, 64, 255, 247, 27, 188, ++ 7, 75, 32, 70, 163, 96, 33, 136, 165, 107, 4, 240, 234, 223, 32, 70, ++ 255, 247, 17, 252, 44, 70, 206, 231, 56, 189, 192, 110, 4, 0, 239, 190, ++ 173, 222, 16, 181, 7, 224, 5, 75, 130, 138, 27, 104, 83, 248, 34, 64, ++ 255, 247, 191, 255, 32, 70, 0, 40, 245, 209, 16, 189, 0, 191, 32, 7, ++ 0, 0, 248, 181, 31, 78, 1, 34, 13, 70, 48, 104, 0, 33, 8, 240, 96, 255, ++ 0, 33, 8, 34, 7, 70, 48, 104, 8, 240, 90, 255, 2, 45, 1, 70, 16, 209, ++ 7, 234, 0, 4, 20, 244, 128, 100, 6, 208, 48, 104, 33, 244, 128, 97, ++ 0, 34, 8, 240, 76, 255, 44, 70, 250, 4, 30, 213, 68, 240, 4, 4, 27, ++ 224, 5, 45, 16, 209, 7, 244, 0, 100, 212, 241, 1, 4, 56, 191, 0, 36, ++ 187, 5, 17, 213, 48, 104, 65, 244, 128, 97, 0, 34, 8, 240, 54, 255, ++ 68, 240, 32, 4, 8, 224, 53, 185, 48, 104, 41, 70, 5, 34, 189, 232, 248, ++ 64, 8, 240, 43, 191, 0, 36, 32, 70, 248, 189, 56, 7, 0, 0, 41, 185, ++ 3, 75, 17, 70, 24, 104, 7, 34, 8, 240, 31, 191, 112, 71, 56, 7, 0, 0, ++ 248, 181, 6, 70, 0, 32, 13, 70, 4, 70, 0, 33, 41, 96, 51, 70, 0, 224, ++ 1, 51, 26, 120, 32, 42, 251, 208, 10, 179, 42, 104, 12, 177, 64, 248, ++ 34, 48, 1, 50, 42, 96, 12, 224, 34, 42, 9, 209, 129, 240, 1, 1, 52, ++ 177, 95, 30, 90, 120, 3, 248, 1, 43, 0, 42, 250, 209, 59, 70, 1, 51, ++ 26, 120, 26, 177, 0, 41, 238, 209, 32, 42, 236, 209, 0, 44, 223, 208, ++ 0, 42, 221, 208, 0, 34, 3, 248, 1, 43, 217, 231, 68, 185, 40, 104, 33, ++ 70, 1, 48, 128, 0, 255, 247, 239, 250, 8, 185, 40, 96, 248, 189, 1, ++ 52, 2, 44, 199, 209, 43, 104, 0, 34, 64, 248, 35, 32, 248, 189, 55, ++ 181, 19, 75, 27, 104, 211, 248, 160, 80, 3, 120, 251, 177, 1, 169, 255, ++ 247, 180, 255, 1, 155, 4, 70, 59, 185, 136, 185, 23, 224, 40, 104, 33, ++ 104, 0, 240, 97, 222, 24, 177, 237, 104, 0, 45, 247, 209, 10, 224, 107, ++ 104, 168, 104, 1, 153, 34, 70, 152, 71, 5, 240, 145, 218, 32, 70, 255, ++ 247, 74, 251, 3, 224, 3, 72, 0, 240, 232, 221, 245, 231, 62, 189, 124, ++ 7, 0, 0, 101, 208, 136, 0, 16, 181, 4, 70, 5, 240, 202, 218, 12, 177, ++ 0, 35, 27, 96, 6, 75, 0, 33, 24, 104, 4, 240, 18, 216, 4, 75, 27, 104, ++ 3, 177, 152, 71, 5, 240, 188, 218, 254, 231, 0, 191, 56, 7, 0, 0, 128, ++ 7, 0, 0, 45, 233, 255, 71, 73, 75, 4, 70, 216, 98, 3, 104, 3, 43, 3, ++ 209, 71, 75, 24, 104, 11, 240, 206, 218, 35, 104, 163, 241, 16, 2, 15, ++ 42, 4, 216, 4, 176, 189, 232, 240, 71, 255, 247, 58, 188, 3, 43, 15, ++ 209, 64, 74, 227, 108, 34, 240, 1, 2, 147, 66, 9, 209, 98, 108, 6, 51, ++ 147, 97, 99, 108, 79, 240, 255, 50, 26, 96, 4, 176, 189, 232, 240, 135, ++ 57, 75, 58, 78, 101, 108, 27, 104, 241, 105, 50, 104, 56, 72, 197, 235, ++ 3, 10, 0, 240, 151, 221, 163, 108, 33, 104, 0, 147, 99, 108, 34, 70, ++ 1, 147, 163, 104, 51, 72, 2, 147, 227, 104, 0, 39, 3, 147, 227, 108, ++ 0, 240, 136, 221, 227, 105, 4, 241, 16, 1, 0, 147, 35, 106, 46, 72, ++ 1, 147, 99, 106, 79, 234, 154, 10, 2, 147, 163, 106, 185, 70, 3, 147, ++ 14, 201, 0, 240, 119, 221, 163, 107, 4, 241, 44, 1, 0, 147, 227, 107, ++ 38, 72, 1, 147, 35, 108, 184, 70, 2, 147, 14, 201, 0, 240, 106, 221, ++ 235, 104, 35, 72, 0, 147, 149, 232, 14, 0, 0, 240, 99, 221, 235, 105, ++ 5, 241, 16, 1, 0, 147, 31, 72, 14, 201, 0, 240, 91, 221, 24, 224, 122, ++ 89, 211, 7, 15, 213, 255, 42, 13, 217, 27, 75, 154, 66, 4, 217, 2, 241, ++ 98, 67, 179, 245, 128, 31, 5, 216, 24, 72, 57, 70, 0, 240, 73, 221, ++ 9, 241, 1, 9, 4, 55, 185, 241, 15, 15, 8, 241, 1, 8, 1, 216, 208, 69, ++ 228, 209, 51, 104, 0, 32, 67, 244, 128, 99, 134, 232, 24, 0, 4, 176, ++ 189, 232, 240, 71, 255, 247, 82, 191, 128, 109, 4, 0, 56, 7, 0, 0, 37, ++ 135, 128, 0, 64, 93, 4, 0, 220, 109, 4, 0, 92, 25, 4, 0, 114, 25, 4, ++ 0, 167, 25, 4, 0, 218, 25, 4, 0, 9, 26, 4, 0, 39, 26, 4, 0, 226, 20, ++ 4, 0, 69, 26, 4, 0, 3, 104, 16, 181, 2, 43, 4, 70, 3, 208, 8, 75, 24, ++ 104, 8, 240, 205, 250, 32, 70, 255, 247, 68, 255, 35, 104, 2, 43, 5, ++ 208, 3, 75, 24, 104, 189, 232, 16, 64, 8, 240, 125, 186, 16, 189, 56, ++ 7, 0, 0, 1, 75, 24, 104, 112, 71, 0, 191, 40, 110, 4, 0, 195, 104, 152, ++ 108, 192, 243, 64, 0, 112, 71, 0, 0, 112, 181, 144, 248, 124, 49, 4, ++ 70, 255, 43, 19, 77, 4, 209, 213, 248, 164, 48, 64, 106, 152, 71, 232, ++ 185, 107, 111, 96, 106, 152, 71, 213, 248, 164, 80, 96, 106, 168, 71, ++ 212, 248, 0, 50, 152, 66, 11, 210, 148, 248, 32, 18, 65, 185, 11, 70, ++ 32, 70, 8, 74, 4, 240, 87, 222, 1, 35, 132, 248, 32, 50, 112, 189, 96, ++ 106, 148, 248, 9, 97, 168, 71, 48, 24, 132, 248, 10, 1, 112, 189, 0, ++ 191, 208, 134, 135, 0, 177, 57, 0, 0, 137, 177, 145, 248, 20, 50, 1, ++ 43, 13, 208, 145, 248, 121, 49, 83, 177, 74, 105, 5, 75, 16, 106, 3, ++ 64, 43, 177, 79, 240, 128, 115, 8, 70, 19, 98, 9, 240, 103, 154, 112, ++ 71, 0, 252, 1, 1, 45, 233, 240, 79, 0, 241, 40, 7, 1, 33, 187, 176, ++ 4, 70, 56, 70, 1, 240, 238, 220, 1, 40, 64, 243, 66, 129, 212, 248, ++ 152, 49, 152, 66, 0, 242, 61, 129, 32, 70, 9, 240, 79, 218, 1, 33, 56, ++ 70, 1, 240, 223, 220, 1, 40, 129, 70, 64, 243, 50, 129, 212, 248, 168, ++ 33, 1, 33, 0, 38, 4, 168, 82, 24, 55, 150, 79, 240, 1, 8, 1, 240, 118, ++ 220, 40, 224, 0, 33, 4, 168, 42, 70, 1, 240, 48, 221, 184, 241, 1, 15, ++ 10, 209, 171, 104, 106, 104, 35, 240, 127, 67, 194, 243, 20, 2, 35, ++ 244, 96, 3, 155, 26, 11, 43, 18, 221, 171, 104, 91, 121, 25, 6, 16, ++ 212, 26, 7, 14, 208, 135, 75, 8, 241, 1, 8, 27, 104, 1, 224, 8, 241, ++ 1, 8, 170, 138, 83, 248, 34, 80, 0, 45, 248, 209, 2, 224, 70, 70, 0, ++ 224, 1, 38, 56, 70, 0, 33, 1, 240, 178, 220, 5, 70, 0, 40, 207, 209, ++ 3, 224, 56, 70, 0, 33, 1, 240, 0, 221, 4, 168, 0, 33, 1, 240, 166, 220, ++ 2, 70, 0, 40, 244, 209, 0, 46, 64, 240, 231, 128, 212, 248, 240, 48, ++ 27, 104, 152, 69, 0, 242, 225, 128, 212, 248, 228, 49, 212, 248, 232, ++ 17, 3, 235, 73, 9, 31, 250, 137, 249, 160, 104, 73, 68, 173, 248, 226, ++ 144, 8, 240, 60, 248, 130, 70, 0, 40, 0, 240, 207, 128, 58, 173, 53, ++ 248, 6, 45, 208, 248, 8, 128, 130, 129, 49, 70, 64, 70, 0, 240, 0, 220, ++ 41, 70, 2, 34, 64, 70, 255, 247, 123, 248, 189, 248, 226, 48, 8, 241, ++ 2, 0, 219, 67, 41, 70, 2, 34, 173, 248, 226, 48, 255, 247, 112, 248, ++ 8, 241, 12, 3, 1, 147, 173, 248, 230, 96, 179, 70, 106, 224, 88, 74, ++ 171, 137, 17, 104, 169, 70, 2, 224, 144, 137, 145, 70, 27, 24, 185, ++ 248, 20, 32, 81, 248, 34, 32, 0, 42, 246, 209, 173, 248, 226, 48, 171, ++ 104, 26, 121, 25, 29, 2, 145, 3, 146, 187, 241, 0, 15, 3, 208, 45, 136, ++ 171, 248, 20, 80, 24, 224, 3, 153, 74, 74, 8, 241, 4, 0, 10, 67, 58, ++ 169, 65, 248, 16, 45, 8, 34, 0, 147, 255, 247, 65, 248, 148, 248, 10, ++ 33, 46, 70, 132, 248, 11, 33, 136, 248, 9, 32, 189, 248, 226, 32, 0, ++ 155, 12, 50, 173, 248, 226, 32, 2, 153, 8, 34, 54, 168, 0, 147, 255, ++ 247, 46, 248, 3, 154, 2, 152, 81, 28, 54, 154, 201, 178, 34, 240, 255, ++ 2, 10, 67, 54, 146, 54, 169, 8, 34, 255, 247, 33, 248, 148, 248, 10, ++ 33, 0, 155, 132, 248, 11, 33, 90, 114, 212, 248, 160, 33, 189, 248, ++ 226, 16, 83, 30, 91, 24, 179, 251, 242, 243, 83, 67, 189, 248, 230, ++ 32, 155, 178, 89, 26, 173, 248, 228, 48, 155, 24, 173, 248, 230, 48, ++ 1, 155, 169, 248, 16, 16, 157, 28, 24, 70, 57, 169, 2, 34, 255, 247, ++ 0, 248, 203, 70, 1, 149, 56, 70, 0, 33, 1, 240, 248, 219, 5, 70, 0, ++ 40, 141, 209, 41, 70, 82, 70, 56, 70, 1, 240, 70, 220, 214, 248, 8, ++ 128, 179, 137, 168, 241, 12, 0, 12, 51, 152, 248, 4, 144, 13, 241, 230, ++ 1, 179, 129, 2, 34, 176, 96, 254, 247, 227, 255, 189, 248, 230, 48, ++ 13, 241, 230, 1, 219, 67, 2, 34, 168, 241, 10, 0, 173, 248, 230, 48, ++ 254, 247, 215, 255, 73, 240, 64, 99, 67, 244, 64, 115, 58, 169, 65, ++ 248, 16, 61, 8, 34, 168, 241, 8, 0, 254, 247, 203, 255, 148, 248, 10, ++ 49, 56, 70, 132, 248, 11, 49, 41, 70, 8, 248, 3, 60, 50, 70, 1, 240, ++ 20, 220, 148, 248, 8, 49, 1, 51, 132, 248, 8, 49, 59, 176, 189, 232, ++ 240, 143, 32, 7, 0, 0, 0, 131, 0, 12, 208, 248, 132, 17, 16, 181, 4, ++ 70, 129, 177, 212, 248, 136, 33, 2, 35, 192, 104, 11, 240, 143, 218, ++ 212, 248, 132, 17, 212, 248, 136, 33, 224, 104, 74, 64, 2, 35, 189, ++ 232, 16, 64, 11, 240, 132, 154, 16, 189, 0, 0, 45, 233, 248, 67, 0, ++ 241, 40, 7, 2, 33, 4, 70, 56, 70, 1, 240, 129, 219, 0, 40, 32, 70, 212, ++ 191, 79, 240, 0, 8, 79, 240, 1, 8, 79, 240, 0, 9, 255, 247, 56, 254, ++ 64, 224, 160, 104, 41, 70, 5, 240, 35, 255, 212, 248, 240, 48, 27, 104, ++ 152, 66, 5, 217, 56, 70, 65, 70, 42, 70, 1, 240, 235, 219, 61, 224, ++ 174, 104, 0, 35, 179, 113, 148, 248, 124, 49, 41, 70, 51, 114, 148, ++ 248, 10, 49, 132, 248, 11, 49, 115, 114, 212, 248, 8, 50, 96, 106, 1, ++ 51, 196, 248, 8, 50, 114, 121, 42, 75, 130, 240, 128, 2, 210, 9, 155, ++ 106, 152, 71, 184, 185, 212, 248, 248, 48, 131, 177, 184, 241, 0, 15, ++ 8, 209, 50, 120, 112, 120, 66, 234, 0, 32, 15, 48, 0, 9, 2, 10, 24, ++ 191, 0, 32, 155, 104, 152, 113, 148, 248, 124, 33, 26, 114, 196, 248, ++ 248, 80, 79, 240, 1, 9, 212, 248, 240, 48, 27, 104, 1, 43, 6, 217, 56, ++ 70, 65, 70, 1, 240, 59, 219, 5, 70, 0, 40, 178, 209, 0, 35, 132, 248, ++ 252, 48, 196, 248, 248, 48, 185, 241, 0, 15, 5, 208, 99, 105, 4, 34, ++ 90, 100, 32, 70, 9, 240, 112, 218, 1, 33, 56, 70, 1, 240, 22, 219, 212, ++ 248, 204, 49, 152, 66, 4, 217, 32, 105, 189, 232, 248, 67, 3, 240, 83, ++ 152, 1, 33, 56, 70, 1, 240, 9, 219, 212, 248, 208, 49, 152, 66, 4, 210, ++ 32, 105, 189, 232, 248, 67, 3, 240, 60, 152, 189, 232, 248, 131, 208, ++ 134, 135, 0, 248, 181, 4, 70, 212, 248, 168, 49, 192, 141, 14, 70, 152, ++ 66, 12, 211, 2, 42, 10, 209, 160, 104, 1, 34, 7, 240, 208, 254, 212, ++ 248, 172, 49, 0, 37, 1, 51, 196, 248, 172, 49, 184, 224, 4, 241, 40, ++ 0, 10, 185, 1, 33, 0, 224, 0, 33, 50, 70, 4, 241, 40, 5, 1, 240, 66, ++ 219, 2, 33, 40, 70, 1, 240, 216, 218, 0, 40, 2, 221, 32, 70, 255, 247, ++ 73, 255, 40, 70, 1, 33, 1, 240, 207, 218, 7, 70, 0, 40, 0, 240, 156, ++ 128, 212, 248, 164, 81, 7, 45, 30, 208, 8, 45, 50, 208, 1, 45, 3, 208, ++ 32, 70, 255, 247, 54, 255, 143, 224, 212, 248, 152, 49, 152, 66, 6, ++ 211, 32, 70, 255, 247, 192, 253, 32, 70, 255, 247, 43, 255, 133, 224, ++ 148, 248, 126, 33, 0, 42, 64, 240, 129, 128, 212, 248, 148, 1, 212, ++ 248, 156, 17, 4, 240, 67, 218, 117, 224, 148, 248, 126, 49, 35, 185, ++ 60, 75, 96, 106, 27, 109, 152, 71, 224, 177, 212, 248, 152, 49, 159, ++ 66, 24, 210, 212, 248, 176, 49, 0, 43, 91, 208, 178, 137, 212, 248, ++ 180, 49, 154, 66, 86, 216, 14, 224, 148, 248, 126, 49, 35, 185, 49, ++ 75, 96, 106, 27, 109, 152, 71, 48, 177, 212, 248, 152, 49, 159, 66, ++ 2, 210, 179, 137, 64, 43, 16, 216, 32, 70, 255, 247, 136, 253, 32, 70, ++ 255, 247, 243, 254, 148, 248, 126, 49, 27, 179, 212, 248, 148, 1, 255, ++ 247, 168, 248, 0, 35, 132, 248, 126, 49, 27, 224, 212, 248, 176, 33, ++ 146, 179, 212, 248, 180, 33, 147, 66, 46, 216, 31, 75, 96, 106, 27, ++ 109, 152, 71, 5, 70, 144, 185, 32, 70, 255, 247, 106, 253, 32, 70, 255, ++ 247, 213, 254, 148, 248, 126, 49, 43, 177, 212, 248, 148, 1, 255, 247, ++ 138, 248, 132, 248, 126, 81, 0, 35, 132, 248, 40, 50, 34, 224, 148, ++ 248, 40, 50, 251, 185, 148, 248, 126, 49, 27, 177, 212, 248, 148, 1, ++ 255, 247, 122, 248, 0, 33, 1, 37, 212, 248, 148, 1, 10, 70, 4, 240, ++ 219, 217, 132, 248, 126, 81, 132, 248, 40, 82, 13, 224, 148, 248, 126, ++ 33, 74, 185, 212, 248, 148, 1, 212, 248, 156, 17, 4, 240, 205, 217, ++ 1, 37, 132, 248, 126, 81, 0, 224, 1, 37, 40, 70, 248, 189, 208, 134, ++ 135, 0, 45, 233, 240, 79, 144, 248, 120, 49, 133, 176, 0, 39, 5, 70, ++ 12, 70, 146, 70, 208, 248, 8, 128, 2, 151, 1, 151, 11, 177, 64, 70, ++ 42, 224, 139, 104, 208, 248, 216, 97, 144, 248, 42, 34, 30, 64, 82, ++ 177, 66, 104, 17, 58, 5, 42, 6, 216, 138, 137, 243, 42, 3, 216, 244, ++ 54, 34, 240, 3, 2, 182, 26, 98, 104, 35, 240, 127, 67, 194, 243, 20, ++ 2, 35, 244, 96, 3, 6, 241, 12, 9, 155, 26, 75, 69, 43, 210, 180, 248, ++ 12, 176, 213, 248, 228, 17, 64, 70, 89, 68, 137, 25, 7, 240, 179, 253, ++ 7, 70, 40, 185, 64, 70, 33, 70, 1, 34, 7, 240, 206, 253, 97, 224, 213, ++ 248, 228, 49, 128, 104, 186, 137, 243, 24, 192, 24, 184, 96, 211, 26, ++ 187, 129, 90, 70, 161, 104, 254, 247, 240, 253, 44, 75, 162, 138, 27, ++ 104, 83, 248, 34, 48, 3, 177, 27, 136, 33, 70, 187, 130, 64, 70, 0, ++ 34, 7, 240, 179, 253, 60, 70, 78, 177, 160, 104, 163, 137, 128, 27, ++ 243, 24, 160, 96, 163, 129, 0, 33, 50, 70, 0, 240, 87, 217, 213, 248, ++ 228, 49, 162, 137, 166, 104, 33, 70, 246, 26, 155, 24, 163, 129, 166, ++ 96, 64, 70, 5, 240, 93, 253, 4, 175, 39, 248, 2, 13, 57, 70, 2, 34, ++ 48, 70, 254, 247, 195, 253, 189, 248, 14, 48, 57, 70, 219, 67, 2, 34, ++ 176, 28, 173, 248, 14, 48, 254, 247, 185, 253, 149, 248, 8, 33, 79, ++ 234, 10, 35, 3, 244, 112, 99, 19, 67, 4, 169, 67, 234, 9, 99, 65, 248, ++ 12, 61, 8, 34, 48, 29, 254, 247, 169, 253, 40, 70, 33, 70, 82, 70, 255, ++ 247, 150, 254, 48, 177, 149, 248, 8, 49, 1, 39, 1, 51, 133, 248, 8, ++ 49, 0, 224, 7, 70, 56, 70, 5, 176, 189, 232, 240, 143, 0, 191, 32, 7, ++ 0, 0, 56, 181, 144, 248, 126, 49, 4, 70, 75, 177, 208, 248, 148, 1, ++ 254, 247, 171, 255, 0, 33, 212, 248, 148, 1, 10, 70, 4, 240, 13, 217, ++ 227, 141, 0, 43, 78, 209, 148, 248, 42, 50, 27, 177, 99, 104, 17, 59, ++ 5, 43, 8, 217, 212, 248, 28, 2, 40, 177, 3, 120, 27, 177, 5, 240, 148, ++ 252, 5, 70, 144, 185, 148, 248, 42, 50, 160, 104, 212, 248, 228, 17, ++ 43, 177, 99, 104, 17, 59, 5, 43, 1, 216, 244, 49, 2, 224, 212, 248, ++ 232, 49, 89, 24, 7, 240, 15, 253, 5, 70, 0, 179, 148, 248, 42, 34, 212, ++ 248, 228, 49, 34, 177, 98, 104, 17, 58, 5, 42, 152, 191, 244, 51, 171, ++ 129, 32, 70, 255, 247, 1, 252, 212, 248, 228, 49, 170, 104, 32, 70, ++ 210, 24, 170, 96, 170, 137, 41, 70, 211, 26, 171, 129, 1, 34, 255, 247, ++ 8, 255, 80, 185, 212, 248, 16, 50, 1, 51, 196, 248, 16, 50, 212, 248, ++ 248, 49, 1, 51, 196, 248, 248, 49, 56, 189, 212, 248, 12, 50, 1, 51, ++ 196, 248, 12, 50, 56, 189, 16, 181, 4, 104, 0, 35, 132, 248, 32, 50, ++ 32, 70, 255, 247, 218, 251, 212, 248, 244, 49, 107, 185, 148, 248, 11, ++ 49, 148, 248, 10, 33, 154, 66, 12, 208, 148, 248, 9, 33, 155, 26, 212, ++ 248, 0, 34, 219, 178, 147, 66, 4, 216, 32, 70, 189, 232, 16, 64, 255, ++ 247, 128, 191, 16, 189, 0, 0, 112, 181, 12, 70, 0, 41, 53, 208, 72, ++ 106, 0, 40, 50, 208, 145, 248, 121, 49, 0, 43, 46, 208, 145, 248, 20, ++ 50, 1, 43, 42, 208, 209, 248, 252, 49, 0, 43, 38, 208, 20, 78, 214, ++ 248, 164, 80, 168, 71, 212, 248, 240, 49, 152, 66, 30, 210, 115, 111, ++ 96, 106, 152, 71, 96, 106, 148, 248, 9, 97, 168, 71, 212, 248, 244, ++ 49, 54, 24, 246, 178, 132, 248, 10, 97, 91, 185, 148, 248, 11, 49, 158, ++ 66, 12, 208, 148, 248, 9, 33, 155, 26, 212, 248, 0, 34, 219, 178, 147, ++ 66, 4, 216, 32, 70, 189, 232, 112, 64, 255, 247, 68, 191, 112, 189, ++ 0, 191, 208, 134, 135, 0, 16, 181, 4, 104, 0, 35, 32, 70, 132, 248, ++ 126, 49, 255, 247, 194, 251, 32, 70, 189, 232, 16, 64, 255, 247, 43, ++ 189, 208, 248, 0, 49, 144, 248, 123, 33, 11, 67, 192, 248, 0, 49, 234, ++ 177, 90, 7, 5, 213, 144, 248, 124, 33, 67, 234, 2, 99, 192, 248, 0, ++ 49, 208, 248, 0, 49, 19, 240, 10, 15, 28, 191, 67, 244, 128, 35, 192, ++ 248, 0, 49, 208, 248, 0, 33, 67, 105, 218, 100, 0, 34, 192, 248, 0, ++ 33, 128, 248, 123, 33, 8, 34, 90, 100, 8, 240, 229, 159, 112, 71, 115, ++ 181, 142, 104, 13, 70, 170, 137, 115, 136, 8, 58, 155, 178, 6, 241, ++ 8, 1, 146, 178, 19, 240, 15, 15, 4, 70, 169, 96, 170, 129, 29, 208, ++ 217, 7, 4, 213, 208, 248, 88, 33, 1, 50, 192, 248, 88, 33, 154, 7, 4, ++ 213, 212, 248, 92, 33, 1, 50, 196, 248, 92, 33, 88, 7, 4, 213, 212, ++ 248, 96, 33, 1, 50, 196, 248, 96, 33, 25, 7, 64, 241, 135, 128, 212, ++ 248, 100, 49, 1, 51, 196, 248, 100, 49, 128, 224, 3, 42, 7, 216, 208, ++ 248, 72, 49, 1, 51, 192, 248, 72, 49, 208, 248, 24, 2, 120, 224, 2, ++ 34, 1, 168, 254, 247, 100, 252, 169, 104, 13, 241, 6, 0, 2, 49, 2, 34, ++ 254, 247, 93, 252, 32, 70, 255, 247, 4, 251, 200, 177, 148, 248, 5, ++ 50, 170, 104, 75, 177, 189, 248, 6, 16, 68, 75, 201, 67, 137, 178, 3, ++ 49, 11, 64, 219, 67, 173, 248, 6, 48, 189, 248, 6, 48, 189, 248, 4, ++ 0, 219, 67, 153, 178, 136, 66, 3, 209, 19, 128, 51, 128, 173, 248, 4, ++ 48, 50, 136, 189, 248, 4, 48, 146, 178, 154, 66, 2, 208, 212, 248, 36, ++ 34, 42, 177, 218, 67, 189, 248, 6, 16, 146, 178, 145, 66, 20, 208, 50, ++ 136, 146, 178, 154, 66, 4, 208, 212, 248, 76, 33, 1, 50, 196, 248, 76, ++ 33, 219, 67, 189, 248, 6, 32, 155, 178, 154, 66, 47, 208, 212, 248, ++ 80, 49, 1, 51, 196, 248, 80, 49, 41, 224, 170, 104, 212, 248, 36, 98, ++ 19, 29, 171, 96, 171, 137, 25, 31, 137, 178, 169, 129, 94, 177, 7, 41, ++ 5, 216, 212, 248, 72, 49, 1, 51, 196, 248, 72, 49, 23, 224, 12, 50, ++ 12, 59, 170, 96, 171, 129, 169, 137, 7, 41, 16, 217, 171, 104, 8, 57, ++ 26, 120, 216, 120, 137, 178, 8, 51, 171, 96, 169, 129, 22, 185, 160, ++ 241, 12, 3, 1, 224, 160, 241, 20, 3, 219, 178, 153, 66, 14, 210, 212, ++ 248, 24, 2, 32, 177, 3, 120, 19, 177, 1, 33, 5, 240, 120, 251, 160, ++ 104, 41, 70, 0, 34, 7, 240, 180, 251, 0, 32, 22, 224, 148, 248, 9, 49, ++ 147, 66, 6, 208, 212, 248, 84, 49, 132, 248, 9, 33, 1, 51, 196, 248, ++ 84, 49, 148, 248, 9, 49, 1, 32, 1, 51, 132, 248, 9, 49, 171, 104, 8, ++ 59, 171, 96, 171, 137, 8, 51, 171, 129, 124, 189, 252, 255, 1, 0, 247, ++ 181, 0, 37, 4, 70, 46, 70, 67, 224, 35, 75, 202, 138, 27, 104, 136, ++ 104, 83, 248, 34, 112, 0, 35, 203, 130, 66, 120, 212, 248, 36, 194, ++ 2, 240, 15, 2, 195, 120, 188, 241, 0, 15, 1, 209, 4, 59, 0, 224, 12, ++ 59, 219, 178, 192, 24, 136, 96, 136, 137, 2, 42, 195, 235, 0, 3, 139, ++ 129, 18, 209, 21, 177, 11, 136, 235, 130, 0, 224, 14, 70, 47, 177, 187, ++ 104, 91, 120, 3, 240, 15, 3, 2, 43, 24, 208, 49, 70, 32, 105, 0, 38, ++ 0, 240, 79, 253, 53, 70, 18, 224, 26, 185, 32, 105, 2, 240, 85, 220, ++ 13, 224, 1, 42, 5, 209, 1, 145, 4, 240, 23, 220, 160, 104, 1, 153, 0, ++ 224, 160, 104, 0, 34, 7, 240, 82, 251, 0, 224, 13, 70, 57, 70, 0, 41, ++ 185, 209, 254, 189, 32, 7, 0, 0, 0, 105, 112, 71, 112, 181, 144, 248, ++ 34, 98, 0, 35, 5, 106, 4, 70, 3, 98, 206, 185, 144, 248, 125, 49, 179, ++ 177, 208, 248, 132, 17, 153, 177, 208, 248, 136, 33, 2, 35, 192, 104, ++ 74, 64, 10, 240, 73, 222, 148, 248, 127, 49, 132, 248, 125, 97, 132, ++ 248, 128, 97, 43, 177, 212, 248, 144, 1, 254, 247, 120, 253, 132, 248, ++ 127, 97, 106, 0, 6, 213, 32, 70, 8, 240, 203, 219, 32, 70, 8, 240, 246, ++ 217, 33, 225, 0, 45, 47, 218, 99, 105, 94, 104, 22, 240, 4, 6, 24, 208, ++ 148, 248, 120, 17, 41, 185, 32, 70, 8, 240, 198, 220, 32, 70, 8, 240, ++ 245, 219, 0, 35, 132, 248, 120, 49, 32, 105, 2, 240, 17, 220, 99, 105, ++ 32, 70, 26, 104, 2, 33, 66, 240, 4, 2, 26, 96, 255, 247, 103, 254, 17, ++ 224, 1, 35, 132, 248, 120, 49, 32, 105, 2, 240, 79, 220, 32, 70, 49, ++ 70, 8, 240, 169, 220, 32, 70, 8, 240, 216, 219, 99, 105, 26, 104, 34, ++ 240, 4, 2, 26, 96, 148, 248, 120, 49, 0, 43, 64, 240, 235, 128, 235, ++ 7, 7, 213, 32, 70, 1, 33, 8, 240, 150, 220, 32, 70, 1, 33, 255, 247, ++ 69, 254, 46, 7, 8, 213, 148, 248, 9, 33, 148, 248, 11, 49, 154, 66, ++ 2, 208, 32, 70, 255, 247, 109, 253, 168, 7, 9, 213, 1, 35, 132, 248, ++ 123, 49, 212, 248, 0, 49, 27, 177, 32, 70, 0, 33, 255, 247, 46, 254, ++ 233, 5, 4, 213, 212, 248, 104, 49, 1, 51, 196, 248, 104, 49, 170, 5, ++ 18, 213, 212, 248, 108, 49, 212, 248, 244, 16, 1, 51, 196, 248, 108, ++ 49, 49, 177, 160, 104, 1, 34, 7, 240, 176, 250, 0, 35, 196, 248, 244, ++ 48, 32, 70, 0, 33, 8, 240, 95, 220, 171, 1, 4, 213, 212, 248, 112, 49, ++ 1, 51, 196, 248, 112, 49, 110, 1, 4, 213, 212, 248, 116, 49, 1, 51, ++ 196, 248, 116, 49, 148, 248, 40, 50, 171, 177, 212, 248, 164, 49, 8, ++ 43, 17, 209, 32, 70, 255, 247, 183, 249, 32, 70, 255, 247, 34, 251, ++ 148, 248, 126, 49, 0, 38, 132, 248, 40, 98, 43, 177, 212, 248, 148, ++ 1, 254, 247, 212, 252, 132, 248, 126, 97, 68, 78, 46, 64, 38, 177, 32, ++ 70, 41, 70, 8, 240, 205, 217, 6, 70, 104, 7, 34, 213, 212, 248, 132, ++ 17, 249, 177, 1, 35, 132, 248, 125, 49, 99, 105, 29, 106, 91, 106, 29, ++ 64, 21, 240, 240, 5, 3, 208, 32, 70, 8, 240, 220, 221, 17, 224, 212, ++ 248, 136, 33, 2, 35, 224, 104, 74, 64, 10, 240, 118, 221, 148, 248, ++ 127, 49, 132, 248, 128, 81, 43, 177, 212, 248, 144, 1, 254, 247, 167, ++ 252, 132, 248, 127, 81, 4, 241, 40, 5, 2, 33, 40, 70, 0, 240, 109, 222, ++ 0, 40, 2, 221, 32, 70, 255, 247, 222, 250, 40, 70, 1, 33, 0, 240, 100, ++ 222, 0, 40, 73, 208, 212, 248, 164, 81, 7, 45, 16, 208, 8, 45, 32, 208, ++ 1, 45, 60, 209, 148, 248, 126, 33, 0, 42, 61, 209, 212, 248, 148, 1, ++ 212, 248, 156, 17, 3, 240, 234, 221, 132, 248, 126, 81, 52, 224, 148, ++ 248, 126, 49, 83, 177, 212, 248, 152, 49, 152, 66, 6, 210, 35, 107, ++ 155, 104, 91, 120, 3, 240, 15, 3, 3, 43, 38, 209, 0, 35, 132, 248, 40, ++ 50, 26, 224, 148, 248, 126, 49, 107, 177, 148, 248, 40, 34, 82, 185, ++ 212, 248, 152, 33, 144, 66, 6, 210, 34, 107, 146, 104, 82, 120, 2, 240, ++ 15, 2, 3, 42, 17, 209, 0, 37, 132, 248, 40, 82, 43, 177, 212, 248, 148, ++ 1, 254, 247, 84, 252, 132, 248, 126, 81, 32, 70, 255, 247, 37, 249, ++ 32, 70, 255, 247, 144, 250, 0, 224, 0, 38, 48, 70, 112, 189, 0, 252, ++ 1, 1, 203, 137, 16, 181, 27, 5, 14, 212, 139, 104, 208, 248, 236, 33, ++ 220, 120, 2, 235, 132, 2, 155, 24, 154, 137, 70, 246, 136, 67, 154, ++ 66, 20, 191, 2, 34, 1, 34, 0, 224, 1, 34, 189, 232, 16, 64, 255, 247, ++ 210, 187, 83, 28, 10, 208, 2, 42, 79, 240, 1, 3, 0, 208, 10, 185, 130, ++ 240, 2, 2, 19, 250, 2, 242, 210, 178, 0, 224, 255, 34, 144, 248, 124, ++ 49, 1, 41, 12, 191, 26, 67, 35, 234, 2, 2, 128, 248, 124, 33, 255, 247, ++ 97, 188, 131, 105, 152, 105, 0, 240, 115, 187, 137, 105, 3, 70, 136, ++ 105, 25, 70, 0, 240, 119, 187, 0, 0, 45, 233, 240, 79, 133, 176, 3, ++ 146, 15, 154, 2, 145, 16, 153, 23, 70, 4, 70, 221, 248, 56, 160, 1, ++ 146, 155, 70, 0, 43, 24, 191, 0, 39, 161, 177, 141, 104, 74, 104, 37, ++ 240, 127, 67, 194, 243, 20, 2, 35, 244, 96, 3, 155, 26, 66, 108, 20, ++ 50, 147, 66, 1, 210, 128, 104, 62, 224, 139, 137, 16, 61, 16, 51, 141, ++ 96, 139, 129, 80, 224, 3, 108, 66, 107, 3, 241, 16, 1, 120, 24, 144, ++ 66, 38, 191, 162, 241, 16, 8, 195, 235, 8, 8, 184, 70, 160, 104, 65, ++ 68, 7, 240, 98, 249, 6, 70, 0, 40, 81, 208, 99, 108, 133, 104, 237, ++ 24, 8, 241, 16, 3, 133, 96, 131, 129, 186, 241, 0, 15, 11, 208, 184, ++ 241, 0, 15, 8, 208, 81, 70, 5, 241, 16, 0, 66, 70, 254, 247, 158, 249, ++ 194, 68, 200, 235, 7, 7, 0, 150, 169, 70, 176, 70, 28, 224, 102, 107, ++ 160, 104, 183, 66, 56, 191, 62, 70, 49, 70, 7, 240, 61, 249, 5, 70, ++ 56, 185, 160, 104, 65, 70, 1, 34, 5, 176, 189, 232, 240, 79, 7, 240, ++ 85, 185, 81, 70, 50, 70, 128, 104, 254, 247, 128, 249, 0, 155, 42, 136, ++ 178, 68, 191, 27, 154, 130, 0, 149, 186, 241, 0, 15, 1, 208, 0, 47, ++ 221, 209, 77, 70, 65, 70, 1, 154, 2, 155, 106, 96, 3, 154, 43, 96, 19, ++ 12, 27, 4, 187, 241, 0, 15, 1, 208, 67, 240, 1, 3, 171, 96, 4, 75, 197, ++ 248, 12, 176, 27, 104, 96, 104, 27, 105, 152, 71, 5, 176, 189, 232, ++ 240, 143, 188, 7, 0, 0, 45, 233, 240, 65, 4, 70, 76, 32, 14, 70, 21, ++ 70, 152, 70, 7, 240, 235, 248, 7, 70, 160, 177, 0, 33, 76, 34, 255, ++ 243, 203, 244, 79, 244, 240, 99, 123, 99, 79, 244, 122, 115, 251, 99, ++ 28, 35, 59, 100, 12, 35, 123, 100, 4, 35, 199, 248, 12, 128, 62, 96, ++ 125, 96, 188, 96, 187, 100, 56, 70, 189, 232, 240, 129, 0, 0, 45, 233, ++ 240, 79, 143, 104, 177, 248, 12, 176, 187, 104, 145, 176, 9, 147, 0, ++ 35, 187, 241, 15, 15, 215, 248, 0, 144, 128, 70, 12, 70, 13, 147, 14, ++ 147, 15, 147, 5, 108, 70, 108, 64, 242, 238, 129, 122, 104, 17, 12, ++ 13, 146, 10, 208, 146, 178, 139, 69, 13, 146, 5, 210, 13, 147, 30, 70, ++ 8, 147, 111, 240, 13, 7, 227, 225, 10, 70, 13, 155, 179, 245, 0, 95, ++ 3, 217, 0, 38, 13, 150, 8, 150, 216, 225, 171, 241, 16, 11, 90, 69, ++ 56, 191, 147, 70, 98, 104, 123, 13, 91, 5, 194, 243, 20, 2, 155, 24, ++ 226, 136, 49, 29, 194, 243, 74, 18, 1, 50, 210, 24, 210, 27, 251, 26, ++ 146, 178, 139, 66, 162, 129, 4, 217, 91, 26, 249, 26, 211, 24, 161, ++ 96, 163, 129, 163, 104, 180, 248, 12, 160, 16, 51, 163, 96, 150, 75, ++ 161, 138, 26, 104, 170, 241, 16, 10, 82, 248, 33, 16, 31, 250, 138, ++ 250, 164, 248, 12, 160, 49, 177, 216, 248, 8, 0, 0, 34, 7, 240, 167, ++ 248, 0, 33, 161, 130, 13, 155, 173, 27, 234, 24, 82, 69, 6, 149, 16, ++ 216, 165, 104, 97, 104, 37, 240, 127, 66, 193, 243, 20, 1, 34, 244, ++ 96, 2, 82, 26, 20, 54, 178, 66, 4, 211, 1, 34, 163, 129, 0, 38, 8, 146, ++ 24, 224, 216, 248, 64, 16, 216, 248, 8, 0, 89, 24, 20, 49, 7, 240, 100, ++ 248, 6, 70, 88, 177, 216, 248, 68, 80, 131, 104, 20, 53, 93, 25, 189, ++ 248, 52, 48, 0, 33, 133, 96, 131, 129, 8, 145, 2, 224, 1, 34, 8, 146, ++ 5, 70, 0, 35, 10, 147, 7, 147, 67, 70, 205, 248, 44, 144, 184, 70, 31, ++ 70, 100, 224, 13, 155, 155, 69, 44, 191, 217, 70, 153, 70, 185, 241, ++ 0, 15, 83, 208, 72, 70, 7, 240, 43, 248, 7, 144, 64, 179, 202, 235, ++ 9, 9, 38, 70, 19, 224, 123, 107, 184, 104, 153, 69, 56, 191, 75, 70, ++ 25, 70, 5, 147, 7, 240, 48, 248, 5, 155, 0, 177, 0, 136, 98, 73, 176, ++ 130, 10, 104, 82, 248, 32, 96, 62, 177, 195, 235, 9, 9, 185, 241, 0, ++ 15, 232, 220, 7, 157, 0, 38, 57, 224, 163, 138, 82, 248, 35, 16, 166, ++ 130, 184, 104, 1, 34, 7, 240, 57, 248, 7, 152, 7, 240, 3, 248, 86, 75, ++ 27, 120, 219, 177, 13, 155, 6, 153, 202, 24, 90, 69, 12, 217, 193, 245, ++ 128, 98, 82, 68, 147, 66, 7, 217, 163, 245, 128, 99, 13, 147, 1, 34, ++ 0, 35, 10, 146, 7, 147, 180, 231, 6, 153, 1, 34, 193, 235, 10, 3, 13, ++ 147, 0, 35, 165, 104, 10, 146, 7, 147, 15, 224, 184, 70, 221, 248, 44, ++ 144, 13, 147, 111, 240, 26, 7, 17, 225, 9, 155, 184, 70, 221, 248, 44, ++ 144, 13, 149, 6, 147, 79, 240, 255, 55, 212, 224, 0, 45, 152, 208, 59, ++ 70, 221, 248, 44, 144, 71, 70, 152, 70, 187, 241, 0, 15, 5, 208, 40, ++ 70, 7, 241, 16, 1, 90, 70, 254, 247, 39, 248, 56, 75, 153, 69, 32, 209, ++ 187, 241, 7, 15, 64, 242, 186, 128, 7, 153, 213, 248, 4, 144, 171, 241, ++ 8, 11, 8, 53, 137, 185, 22, 177, 51, 70, 50, 70, 1, 224, 35, 70, 34, ++ 70, 146, 104, 8, 50, 154, 96, 22, 177, 51, 70, 50, 70, 1, 224, 35, 70, ++ 34, 70, 146, 137, 8, 58, 154, 129, 9, 155, 67, 240, 2, 3, 0, 224, 9, ++ 155, 223, 248, 164, 160, 6, 147, 202, 68, 186, 245, 162, 127, 136, 191, ++ 202, 70, 186, 245, 131, 127, 74, 208, 6, 216, 186, 241, 2, 15, 87, 208, ++ 186, 241, 253, 15, 91, 209, 16, 224, 64, 242, 7, 19, 154, 69, 29, 208, ++ 64, 242, 11, 19, 154, 69, 82, 209, 216, 248, 0, 0, 0, 33, 23, 74, 216, ++ 248, 60, 48, 3, 240, 5, 221, 70, 224, 171, 120, 106, 120, 27, 4, 67, ++ 234, 2, 35, 42, 120, 233, 120, 19, 67, 216, 248, 0, 0, 67, 234, 1, 97, ++ 2, 240, 154, 216, 209, 70, 0, 39, 106, 224, 40, 70, 12, 73, 4, 34, 255, ++ 243, 4, 244, 3, 70, 0, 40, 48, 209, 10, 74, 1, 33, 18, 104, 0, 145, ++ 151, 105, 216, 248, 4, 0, 41, 70, 90, 70, 29, 224, 0, 191, 32, 7, 0, ++ 0, 220, 6, 0, 0, 62, 218, 254, 255, 149, 101, 128, 0, 253, 26, 136, ++ 0, 188, 7, 0, 0, 224, 235, 27, 0, 40, 70, 66, 73, 4, 34, 255, 243, 227, ++ 243, 136, 185, 64, 75, 13, 154, 27, 104, 0, 144, 216, 248, 4, 0, 159, ++ 105, 41, 70, 13, 171, 184, 71, 3, 224, 216, 248, 0, 0, 2, 240, 101, ++ 216, 7, 70, 209, 70, 49, 224, 9, 155, 3, 244, 112, 65, 6, 155, 9, 11, ++ 19, 240, 2, 2, 12, 208, 15, 171, 1, 147, 14, 171, 2, 147, 1, 35, 187, ++ 241, 0, 15, 8, 191, 0, 37, 205, 248, 0, 176, 3, 147, 7, 224, 16, 171, ++ 83, 248, 12, 13, 3, 146, 141, 232, 9, 0, 14, 171, 2, 147, 216, 248, ++ 0, 0, 74, 70, 43, 70, 2, 240, 25, 216, 16, 241, 14, 15, 7, 70, 10, 209, ++ 10, 153, 65, 177, 0, 35, 13, 147, 111, 240, 26, 7, 3, 224, 9, 155, 111, ++ 240, 23, 7, 6, 147, 7, 153, 65, 177, 0, 149, 216, 248, 8, 0, 33, 70, ++ 0, 34, 13, 155, 0, 240, 190, 217, 8, 224, 189, 248, 52, 32, 0, 46, 20, ++ 191, 51, 70, 35, 70, 154, 129, 0, 35, 7, 147, 15, 177, 14, 155, 13, ++ 147, 8, 153, 49, 185, 33, 70, 216, 248, 8, 0, 8, 154, 6, 240, 19, 255, ++ 52, 70, 13, 155, 6, 154, 1, 147, 64, 70, 73, 70, 59, 70, 0, 149, 2, ++ 148, 255, 247, 78, 253, 7, 154, 90, 177, 16, 70, 6, 240, 208, 254, 7, ++ 224, 30, 70, 8, 147, 111, 240, 23, 7, 9, 155, 0, 37, 6, 147, 210, 231, ++ 17, 176, 189, 232, 240, 143, 0, 191, 253, 26, 136, 0, 188, 7, 0, 0, ++ 45, 233, 240, 65, 138, 104, 12, 70, 7, 70, 129, 108, 134, 104, 96, 104, ++ 34, 240, 127, 67, 192, 243, 20, 0, 35, 244, 96, 3, 27, 26, 139, 66, ++ 48, 210, 180, 248, 12, 128, 48, 70, 65, 68, 6, 240, 185, 254, 5, 70, ++ 48, 185, 33, 70, 48, 70, 1, 34, 6, 240, 212, 254, 44, 70, 54, 224, 195, ++ 137, 226, 137, 35, 240, 7, 3, 27, 4, 2, 240, 7, 2, 27, 12, 19, 67, 195, ++ 129, 226, 137, 209, 6, 76, 191, 67, 240, 16, 3, 35, 240, 16, 3, 195, ++ 129, 163, 124, 161, 104, 131, 116, 187, 108, 128, 104, 66, 70, 192, ++ 24, 253, 247, 231, 254, 33, 70, 48, 70, 1, 34, 6, 240, 178, 254, 44, ++ 70, 4, 224, 163, 137, 82, 26, 201, 24, 162, 96, 161, 129, 163, 104, ++ 32, 34, 26, 112, 226, 137, 210, 6, 1, 213, 36, 34, 26, 112, 226, 137, ++ 2, 240, 7, 2, 90, 112, 0, 34, 154, 112, 162, 124, 218, 112, 32, 70, ++ 189, 232, 240, 129, 3, 70, 112, 181, 154, 108, 140, 137, 128, 104, 148, ++ 66, 45, 211, 138, 104, 21, 120, 45, 9, 110, 30, 1, 46, 39, 216, 200, ++ 137, 86, 120, 32, 240, 7, 0, 0, 4, 6, 240, 7, 6, 0, 12, 48, 67, 200, ++ 129, 22, 120, 22, 240, 8, 15, 28, 191, 64, 240, 8, 0, 200, 129, 16, ++ 120, 16, 240, 3, 0, 5, 208, 142, 105, 38, 244, 64, 54, 70, 234, 0, 64, ++ 136, 97, 1, 45, 1, 209, 0, 32, 0, 224, 208, 120, 136, 116, 155, 108, ++ 0, 32, 210, 24, 227, 26, 138, 96, 139, 129, 112, 189, 0, 34, 6, 240, ++ 96, 254, 1, 32, 112, 189, 0, 41, 195, 107, 9, 221, 130, 108, 0, 42, ++ 6, 221, 1, 57, 145, 66, 186, 191, 3, 108, 83, 248, 33, 48, 0, 35, 24, ++ 70, 112, 71, 0, 0, 8, 181, 3, 75, 0, 104, 27, 104, 91, 105, 152, 71, ++ 8, 189, 0, 191, 188, 7, 0, 0, 112, 181, 4, 70, 14, 70, 64, 104, 17, ++ 70, 6, 240, 101, 254, 1, 70, 224, 104, 255, 247, 71, 255, 5, 70, 224, ++ 177, 32, 70, 49, 70, 42, 70, 1, 240, 62, 223, 0, 40, 21, 219, 41, 70, ++ 96, 104, 4, 240, 238, 253, 9, 75, 6, 70, 27, 104, 32, 104, 219, 104, ++ 41, 70, 152, 71, 48, 177, 227, 105, 158, 25, 99, 105, 230, 97, 1, 51, ++ 99, 97, 2, 224, 227, 106, 1, 51, 227, 98, 0, 32, 112, 189, 188, 7, 0, ++ 0, 45, 233, 247, 79, 0, 36, 5, 70, 138, 70, 39, 70, 1, 148, 38, 70, ++ 90, 224, 50, 75, 186, 248, 22, 32, 27, 104, 83, 248, 34, 128, 218, 248, ++ 8, 48, 147, 248, 2, 144, 9, 240, 15, 9, 184, 241, 0, 15, 5, 208, 216, ++ 248, 8, 48, 155, 120, 3, 240, 15, 3, 1, 147, 232, 104, 81, 70, 255, ++ 247, 92, 255, 131, 70, 0, 187, 164, 185, 40, 70, 73, 70, 255, 247, 143, ++ 255, 6, 70, 48, 177, 104, 104, 81, 70, 6, 240, 35, 254, 4, 70, 7, 70, ++ 53, 224, 104, 104, 81, 70, 50, 70, 6, 240, 223, 253, 79, 240, 1, 11, ++ 10, 224, 104, 104, 81, 70, 6, 240, 20, 254, 8, 177, 3, 136, 0, 224, ++ 3, 70, 227, 130, 4, 70, 34, 224, 171, 106, 1, 51, 171, 98, 207, 177, ++ 184, 241, 0, 15, 5, 208, 187, 241, 0, 15, 2, 209, 1, 155, 153, 69, 16, ++ 208, 0, 35, 227, 130, 51, 105, 168, 107, 219, 104, 49, 70, 58, 70, 152, ++ 71, 40, 177, 171, 106, 0, 36, 1, 51, 171, 98, 39, 70, 1, 224, 4, 70, ++ 7, 70, 194, 70, 186, 241, 0, 15, 161, 209, 3, 224, 43, 105, 1, 51, 43, ++ 97, 219, 231, 189, 232, 254, 143, 32, 7, 0, 0, 115, 181, 11, 70, 4, ++ 70, 0, 41, 42, 208, 0, 42, 40, 208, 129, 107, 145, 185, 193, 107, 33, ++ 187, 194, 99, 131, 99, 90, 98, 83, 98, 0, 145, 64, 104, 33, 70, 34, ++ 104, 255, 247, 103, 252, 224, 96, 0, 40, 12, 191, 79, 240, 255, 48, ++ 0, 32, 21, 224, 153, 66, 17, 209, 195, 107, 147, 66, 14, 208, 134, 108, ++ 0, 32, 9, 224, 35, 108, 3, 235, 128, 5, 83, 248, 32, 48, 1, 48, 19, ++ 185, 42, 96, 81, 98, 3, 224, 176, 66, 243, 219, 79, 240, 255, 48, 124, ++ 189, 112, 71, 16, 181, 68, 240, 211, 248, 68, 240, 225, 248, 67, 240, ++ 189, 250, 68, 240, 141, 249, 4, 70, 67, 240, 118, 250, 32, 70, 73, 240, ++ 55, 254, 253, 247, 21, 255, 32, 70, 189, 232, 16, 64, 254, 247, 54, ++ 185, 45, 233, 243, 65, 7, 70, 5, 70, 0, 36, 62, 224, 213, 248, 116, ++ 131, 216, 248, 8, 105, 22, 240, 3, 3, 53, 208, 3, 34, 200, 248, 4, 41, ++ 216, 248, 8, 41, 144, 7, 251, 209, 2, 43, 3, 208, 3, 43, 19, 208, 25, ++ 72, 18, 224, 216, 248, 0, 56, 24, 72, 67, 240, 1, 3, 200, 248, 0, 56, ++ 216, 248, 0, 56, 216, 248, 0, 56, 35, 240, 1, 3, 200, 248, 0, 56, 216, ++ 248, 0, 56, 0, 224, 17, 72, 255, 243, 3, 241, 33, 70, 16, 72, 255, 243, ++ 255, 240, 216, 248, 12, 25, 216, 248, 16, 41, 216, 248, 20, 57, 216, ++ 248, 28, 9, 0, 144, 11, 72, 255, 243, 243, 240, 11, 72, 49, 70, 255, ++ 243, 239, 240, 1, 52, 4, 53, 215, 248, 112, 51, 156, 66, 188, 211, 189, ++ 232, 252, 129, 0, 191, 127, 26, 4, 0, 143, 26, 4, 0, 155, 26, 4, 0, ++ 174, 28, 136, 0, 172, 26, 4, 0, 228, 26, 4, 0, 240, 181, 0, 35, 5, 224, ++ 204, 92, 5, 104, 1, 51, 68, 234, 5, 36, 4, 96, 2, 240, 3, 4, 163, 66, ++ 245, 219, 29, 70, 28, 70, 201, 24, 23, 224, 17, 248, 3, 124, 0, 45, ++ 17, 248, 4, 204, 212, 191, 0, 38, 1, 38, 63, 4, 71, 234, 12, 103, 17, ++ 248, 1, 204, 0, 235, 134, 6, 71, 234, 12, 7, 17, 248, 2, 204, 54, 27, ++ 71, 234, 12, 39, 247, 80, 4, 51, 4, 49, 147, 66, 228, 219, 240, 189, ++ 112, 181, 2, 240, 3, 4, 5, 104, 35, 70, 2, 224, 1, 59, 205, 84, 45, ++ 10, 0, 43, 250, 209, 9, 25, 35, 70, 21, 224, 37, 28, 24, 191, 1, 37, ++ 0, 235, 133, 5, 45, 27, 238, 88, 54, 14, 1, 248, 4, 108, 238, 88, 54, ++ 12, 1, 248, 3, 108, 238, 88, 54, 10, 1, 248, 2, 108, 237, 88, 4, 51, ++ 1, 248, 1, 92, 4, 49, 147, 66, 230, 219, 112, 189, 3, 48, 32, 240, 3, ++ 0, 8, 48, 112, 71, 48, 181, 11, 70, 0, 36, 7, 224, 4, 52, 0, 235, 129, ++ 5, 45, 25, 85, 248, 4, 92, 101, 185, 1, 51, 85, 30, 171, 66, 244, 219, ++ 80, 248, 35, 32, 1, 42, 6, 216, 91, 27, 88, 66, 64, 235, 3, 0, 48, 189, ++ 0, 32, 48, 189, 0, 32, 48, 189, 48, 181, 11, 70, 0, 36, 0, 224, 1, 51, ++ 0, 235, 65, 5, 45, 91, 29, 177, 1, 45, 5, 217, 0, 32, 48, 189, 85, 30, ++ 2, 52, 171, 66, 242, 219, 80, 30, 26, 26, 80, 66, 64, 235, 2, 0, 48, ++ 189, 240, 181, 21, 70, 0, 36, 10, 224, 86, 0, 135, 25, 142, 25, 63, ++ 91, 54, 91, 183, 66, 7, 211, 4, 241, 2, 4, 7, 216, 1, 53, 157, 66, 242, ++ 219, 0, 32, 240, 189, 79, 240, 255, 48, 240, 189, 1, 32, 240, 189, 45, ++ 233, 240, 79, 14, 104, 23, 104, 208, 248, 0, 160, 133, 176, 132, 70, ++ 2, 145, 147, 70, 52, 70, 79, 240, 0, 9, 0, 37, 56, 70, 81, 70, 1, 150, ++ 0, 151, 26, 224, 2, 158, 1, 154, 1, 57, 6, 235, 130, 3, 0, 158, 95, ++ 89, 11, 235, 134, 3, 83, 248, 5, 128, 1, 56, 0, 35, 1, 60, 24, 235, ++ 7, 2, 67, 241, 0, 3, 18, 235, 9, 6, 67, 241, 0, 7, 12, 235, 138, 3, ++ 94, 81, 185, 70, 4, 61, 0, 40, 1, 221, 0, 44, 7, 220, 2, 70, 11, 70, ++ 15, 70, 6, 70, 162, 70, 0, 37, 1, 144, 20, 224, 0, 41, 214, 220, 244, ++ 231, 1, 152, 1, 59, 11, 235, 128, 1, 73, 89, 1, 58, 3, 145, 3, 158, ++ 0, 33, 25, 235, 6, 8, 65, 241, 0, 9, 12, 235, 135, 1, 65, 248, 5, 128, ++ 4, 61, 0, 42, 2, 220, 29, 70, 0, 34, 18, 224, 0, 43, 230, 220, 249, ++ 231, 2, 159, 1, 59, 7, 235, 138, 1, 142, 88, 1, 60, 0, 33, 25, 235, ++ 6, 8, 65, 241, 0, 9, 12, 235, 133, 1, 65, 248, 2, 128, 4, 58, 0, 44, ++ 2, 220, 25, 70, 0, 34, 11, 224, 0, 43, 232, 220, 249, 231, 200, 70, ++ 12, 235, 129, 0, 64, 248, 2, 128, 1, 59, 79, 240, 0, 9, 4, 58, 0, 43, ++ 244, 220, 72, 70, 5, 176, 189, 232, 240, 143, 45, 233, 240, 79, 146, ++ 70, 218, 248, 0, 48, 10, 104, 7, 104, 135, 176, 139, 70, 1, 146, 20, ++ 70, 3, 147, 29, 70, 2, 151, 57, 70, 0, 34, 0, 35, 0, 38, 29, 224, 1, ++ 159, 1, 61, 11, 235, 135, 12, 92, 248, 6, 192, 1, 60, 1, 57, 18, 235, ++ 12, 8, 3, 154, 67, 241, 0, 9, 10, 235, 130, 3, 83, 248, 6, 192, 2, 159, ++ 66, 70, 75, 70, 178, 235, 12, 2, 99, 241, 0, 3, 0, 235, 135, 12, 76, ++ 248, 6, 32, 26, 70, 4, 62, 0, 45, 1, 221, 0, 44, 4, 220, 140, 70, 47, ++ 70, 3, 148, 0, 38, 18, 224, 0, 41, 214, 220, 247, 231, 10, 235, 135, ++ 8, 88, 248, 6, 128, 1, 57, 178, 235, 8, 2, 99, 241, 0, 3, 0, 235, 140, ++ 8, 72, 248, 6, 32, 1, 61, 26, 70, 4, 62, 0, 45, 2, 220, 14, 70, 0, 37, ++ 22, 224, 0, 41, 232, 220, 249, 231, 221, 248, 12, 128, 1, 57, 11, 235, ++ 136, 7, 127, 89, 1, 60, 18, 235, 7, 8, 67, 241, 0, 9, 205, 233, 4, 137, ++ 0, 235, 134, 3, 67, 248, 5, 128, 74, 70, 0, 35, 4, 61, 0, 44, 4, 220, ++ 13, 70, 31, 70, 22, 70, 0, 36, 9, 224, 0, 41, 226, 220, 247, 231, 0, ++ 235, 133, 12, 76, 248, 4, 96, 1, 57, 4, 60, 62, 70, 0, 41, 246, 220, ++ 24, 70, 7, 176, 189, 232, 240, 143, 3, 104, 0, 235, 131, 0, 5, 224, ++ 2, 136, 65, 136, 1, 59, 1, 128, 66, 128, 4, 56, 0, 43, 247, 209, 112, ++ 71, 45, 233, 247, 79, 3, 104, 14, 70, 91, 0, 13, 104, 0, 147, 4, 70, ++ 7, 29, 255, 247, 232, 255, 48, 70, 255, 247, 229, 255, 109, 0, 51, 29, ++ 0, 224, 1, 61, 25, 70, 10, 136, 2, 51, 0, 42, 249, 208, 79, 240, 0, ++ 8, 79, 240, 1, 14, 10, 136, 0, 35, 8, 241, 1, 0, 158, 69, 20, 191, 150, ++ 70, 2, 241, 1, 14, 4, 235, 64, 0, 23, 224, 48, 248, 2, 207, 99, 243, ++ 31, 67, 221, 248, 0, 144, 108, 243, 15, 3, 197, 241, 2, 12, 8, 241, ++ 1, 8, 204, 68, 224, 69, 8, 219, 32, 70, 255, 247, 186, 255, 48, 70, ++ 3, 176, 189, 232, 240, 79, 255, 247, 180, 191, 115, 69, 229, 211, 2, ++ 241, 1, 14, 168, 68, 168, 241, 2, 2, 179, 251, 254, 254, 0, 35, 1, 146, ++ 172, 70, 26, 70, 24, 70, 27, 224, 1, 235, 69, 9, 145, 68, 57, 248, 2, ++ 156, 27, 12, 14, 251, 9, 51, 4, 235, 72, 11, 59, 248, 2, 144, 12, 241, ++ 255, 60, 195, 235, 9, 10, 192, 235, 10, 10, 31, 250, 138, 250, 80, 68, ++ 129, 69, 43, 248, 2, 160, 172, 191, 0, 32, 1, 32, 2, 58, 188, 241, 0, ++ 15, 224, 220, 221, 248, 4, 144, 37, 234, 229, 120, 200, 235, 9, 8, 55, ++ 248, 24, 32, 162, 235, 19, 67, 24, 26, 39, 248, 24, 0, 159, 231, 45, ++ 233, 240, 79, 79, 234, 67, 11, 133, 176, 2, 145, 2, 235, 11, 5, 31, ++ 70, 79, 240, 1, 12, 57, 224, 53, 248, 2, 28, 1, 63, 0, 41, 49, 208, ++ 0, 36, 57, 70, 152, 70, 38, 70, 1, 147, 23, 224, 53, 248, 2, 60, 194, ++ 235, 0, 10, 3, 147, 2, 155, 170, 68, 3, 235, 11, 9, 57, 248, 6, 144, ++ 3, 155, 8, 241, 255, 56, 9, 251, 3, 249, 9, 235, 20, 68, 58, 248, 6, ++ 144, 1, 57, 76, 68, 42, 248, 6, 64, 2, 62, 224, 69, 228, 218, 1, 155, ++ 138, 70, 0, 38, 10, 224, 0, 41, 16, 219, 0, 235, 74, 9, 57, 248, 6, ++ 128, 1, 57, 68, 68, 41, 248, 6, 64, 2, 62, 36, 12, 242, 209, 2, 61, ++ 12, 241, 1, 12, 0, 47, 195, 220, 1, 33, 8, 70, 5, 176, 189, 232, 240, ++ 143, 3, 136, 91, 24, 3, 128, 4, 224, 48, 248, 2, 44, 155, 24, 32, 248, ++ 2, 61, 27, 12, 248, 209, 112, 71, 45, 233, 240, 79, 137, 176, 221, 248, ++ 72, 144, 29, 70, 2, 144, 138, 70, 6, 146, 16, 70, 0, 33, 79, 234, 73, ++ 2, 254, 243, 33, 246, 47, 70, 10, 235, 69, 3, 0, 224, 1, 55, 30, 136, ++ 26, 70, 2, 51, 0, 46, 249, 208, 9, 241, 255, 48, 135, 66, 7, 146, 4, ++ 144, 5, 218, 123, 28, 58, 248, 19, 128, 72, 234, 6, 72, 112, 224, 176, ++ 70, 110, 224, 11, 241, 1, 11, 1, 224, 171, 70, 0, 35, 2, 153, 2, 51, ++ 1, 235, 69, 2, 210, 24, 50, 248, 2, 44, 0, 42, 241, 208, 4, 157, 171, ++ 69, 8, 218, 11, 241, 1, 3, 49, 248, 19, 48, 98, 243, 31, 68, 99, 243, ++ 15, 4, 0, 224, 20, 70, 7, 152, 199, 235, 11, 3, 5, 136, 170, 66, 2, ++ 216, 13, 209, 187, 69, 11, 209, 4, 153, 176, 69, 11, 68, 4, 217, 68, ++ 69, 19, 208, 8, 241, 1, 5, 12, 224, 178, 251, 245, 245, 14, 224, 176, ++ 69, 148, 191, 53, 70, 117, 28, 180, 251, 245, 245, 173, 178, 75, 68, ++ 45, 185, 117, 28, 180, 251, 245, 244, 165, 178, 0, 224, 1, 37, 6, 153, ++ 90, 0, 136, 24, 41, 70, 5, 146, 1, 147, 255, 247, 134, 255, 1, 155, ++ 0, 36, 3, 147, 74, 70, 35, 70, 0, 149, 186, 66, 6, 221, 1, 58, 58, 248, ++ 18, 16, 0, 157, 1, 251, 5, 68, 0, 224, 180, 177, 2, 157, 5, 152, 161, ++ 178, 5, 235, 0, 14, 62, 248, 3, 0, 3, 157, 193, 235, 0, 12, 46, 248, ++ 3, 192, 2, 59, 1, 61, 3, 149, 6, 212, 136, 66, 44, 191, 0, 33, 1, 33, ++ 1, 235, 20, 68, 222, 231, 93, 70, 2, 152, 81, 70, 42, 70, 75, 70, 255, ++ 247, 109, 253, 0, 40, 139, 218, 40, 70, 9, 176, 189, 232, 240, 143, ++ 45, 233, 240, 79, 11, 104, 139, 176, 147, 70, 5, 70, 7, 70, 0, 32, 8, ++ 145, 7, 147, 28, 70, 85, 248, 4, 43, 11, 70, 219, 248, 0, 96, 6, 144, ++ 1, 70, 0, 224, 1, 49, 83, 248, 4, 15, 0, 40, 250, 208, 6, 145, 0, 33, ++ 91, 70, 5, 145, 0, 224, 1, 49, 83, 248, 4, 15, 0, 40, 250, 208, 5, 145, ++ 40, 70, 0, 33, 146, 0, 254, 243, 102, 245, 7, 155, 79, 240, 0, 10, 3, ++ 241, 255, 57, 177, 68, 7, 235, 137, 9, 55, 224, 0, 33, 0, 32, 205, 233, ++ 2, 1, 7, 154, 8, 153, 1, 60, 1, 235, 130, 3, 83, 248, 10, 48, 4, 235, ++ 6, 8, 9, 147, 180, 70, 0, 33, 39, 70, 1, 149, 24, 224, 11, 235, 134, ++ 3, 88, 88, 9, 235, 1, 3, 92, 104, 4, 147, 34, 70, 9, 156, 0, 35, 228, ++ 251, 0, 35, 3, 152, 12, 241, 255, 60, 20, 24, 67, 241, 0, 5, 4, 154, ++ 205, 233, 2, 69, 84, 96, 8, 241, 255, 56, 4, 57, 5, 155, 156, 69, 227, ++ 220, 1, 157, 3, 152, 60, 70, 69, 248, 40, 0, 170, 241, 4, 10, 169, 241, ++ 4, 9, 6, 155, 156, 66, 196, 220, 11, 176, 189, 232, 240, 143, 45, 233, ++ 240, 79, 4, 70, 209, 248, 0, 144, 84, 248, 4, 59, 137, 176, 5, 145, ++ 130, 70, 0, 33, 32, 70, 79, 234, 201, 2, 6, 147, 254, 243, 14, 245, ++ 5, 155, 9, 241, 1, 5, 201, 241, 2, 6, 3, 235, 133, 5, 73, 70, 49, 224, ++ 0, 35, 0, 34, 205, 233, 2, 35, 85, 248, 4, 61, 1, 57, 79, 234, 65, 8, ++ 7, 147, 140, 70, 0, 32, 15, 70, 4, 148, 1, 149, 0, 150, 10, 235, 136, ++ 1, 9, 24, 1, 156, 3, 157, 78, 104, 35, 24, 83, 248, 4, 188, 7, 154, ++ 0, 35, 172, 25, 67, 241, 0, 5, 226, 251, 11, 69, 4, 56, 188, 241, 1, ++ 12, 205, 233, 2, 69, 76, 96, 232, 209, 0, 158, 4, 156, 8, 241, 255, ++ 56, 3, 155, 176, 68, 1, 157, 57, 70, 68, 248, 40, 48, 1, 54, 1, 41, ++ 203, 220, 79, 234, 73, 5, 0, 39, 44, 70, 0, 33, 204, 70, 15, 224, 10, ++ 235, 133, 0, 70, 88, 0, 35, 1, 60, 178, 25, 67, 235, 3, 3, 18, 235, ++ 7, 8, 67, 241, 0, 9, 64, 248, 1, 128, 79, 70, 4, 57, 0, 44, 237, 220, ++ 6, 155, 225, 70, 0, 39, 10, 235, 131, 1, 96, 70, 0, 36, 20, 224, 5, ++ 157, 58, 70, 5, 235, 137, 3, 29, 89, 0, 35, 229, 251, 5, 35, 141, 104, ++ 1, 56, 86, 25, 77, 104, 67, 241, 0, 7, 142, 96, 0, 35, 126, 25, 67, ++ 241, 0, 7, 78, 96, 4, 60, 8, 57, 0, 40, 231, 220, 9, 176, 189, 232, ++ 240, 143, 248, 181, 13, 70, 20, 70, 31, 70, 6, 70, 104, 177, 81, 177, ++ 16, 70, 82, 177, 16, 33, 0, 34, 176, 71, 48, 177, 6, 96, 69, 96, 132, ++ 96, 199, 96, 248, 189, 8, 70, 248, 189, 248, 189, 56, 181, 4, 70, 64, ++ 177, 1, 104, 49, 177, 11, 70, 77, 104, 136, 104, 16, 34, 168, 71, 0, ++ 35, 35, 96, 56, 189, 45, 233, 248, 67, 13, 70, 20, 70, 152, 70, 7, 70, ++ 0, 40, 48, 208, 3, 241, 3, 9, 41, 240, 3, 9, 72, 70, 255, 247, 5, 252, ++ 59, 104, 1, 70, 58, 70, 184, 104, 152, 71, 6, 70, 24, 179, 79, 234, ++ 169, 3, 7, 96, 67, 96, 0, 241, 8, 7, 44, 185, 56, 70, 33, 70, 74, 70, ++ 254, 243, 81, 244, 22, 224, 2, 45, 13, 209, 200, 235, 9, 9, 0, 33, 74, ++ 70, 56, 70, 254, 243, 71, 244, 7, 235, 9, 0, 33, 70, 66, 70, 253, 247, ++ 193, 248, 6, 224, 56, 70, 33, 70, 66, 70, 255, 247, 135, 251, 0, 224, ++ 6, 70, 48, 70, 189, 232, 248, 131, 67, 104, 8, 48, 0, 224, 1, 59, 80, ++ 248, 4, 43, 10, 185, 0, 43, 249, 220, 67, 177, 88, 1, 79, 240, 0, 67, ++ 1, 224, 91, 8, 1, 56, 19, 66, 251, 208, 112, 71, 24, 70, 112, 71, 45, ++ 233, 240, 67, 69, 104, 8, 48, 207, 15, 2, 208, 75, 66, 92, 17, 1, 224, ++ 76, 17, 11, 70, 98, 1, 155, 26, 0, 47, 70, 209, 0, 41, 91, 221, 106, ++ 30, 20, 27, 38, 70, 57, 70, 19, 224, 0, 235, 132, 7, 7, 235, 1, 8, 216, ++ 248, 4, 128, 127, 88, 195, 241, 32, 9, 40, 250, 3, 248, 7, 250, 9, 247, ++ 0, 235, 133, 12, 72, 234, 7, 7, 1, 62, 76, 248, 1, 112, 4, 57, 0, 46, ++ 232, 220, 36, 234, 228, 113, 100, 26, 82, 26, 80, 248, 36, 16, 0, 235, ++ 130, 5, 49, 250, 3, 243, 64, 248, 34, 48, 0, 35, 1, 224, 0, 33, 233, ++ 80, 4, 59, 1, 58, 250, 213, 189, 232, 240, 131, 0, 235, 132, 7, 7, 235, ++ 2, 8, 216, 248, 4, 128, 191, 88, 195, 241, 32, 12, 40, 250, 12, 248, ++ 7, 250, 3, 252, 72, 234, 12, 7, 135, 80, 1, 49, 1, 54, 4, 50, 2, 224, ++ 0, 34, 33, 70, 22, 70, 111, 30, 185, 66, 229, 219, 80, 248, 33, 16, ++ 50, 70, 17, 250, 3, 243, 0, 235, 134, 4, 64, 248, 38, 48, 0, 35, 1, ++ 224, 0, 33, 225, 80, 1, 50, 4, 51, 170, 66, 249, 219, 189, 232, 240, ++ 131, 45, 233, 248, 67, 70, 104, 13, 70, 182, 0, 158, 66, 20, 70, 152, ++ 70, 0, 241, 8, 9, 9, 221, 247, 26, 72, 70, 0, 33, 58, 70, 70, 70, 254, ++ 243, 160, 243, 79, 240, 0, 8, 2, 224, 198, 235, 3, 8, 0, 39, 2, 45, ++ 4, 235, 8, 1, 5, 209, 9, 235, 7, 0, 50, 70, 253, 247, 17, 248, 5, 224, ++ 39, 240, 3, 0, 72, 68, 50, 70, 255, 247, 214, 250, 48, 70, 189, 232, ++ 248, 131, 66, 104, 3, 70, 82, 1, 82, 26, 0, 42, 1, 221, 8, 51, 8, 224, ++ 0, 34, 1, 33, 19, 70, 255, 247, 200, 191, 0, 34, 67, 248, 4, 43, 32, ++ 57, 32, 41, 249, 220, 2, 34, 193, 241, 31, 1, 18, 250, 1, 241, 26, 104, ++ 1, 57, 17, 64, 25, 96, 112, 71, 3, 70, 64, 104, 8, 51, 128, 0, 0, 224, ++ 4, 56, 83, 248, 4, 43, 10, 185, 0, 40, 249, 220, 3, 70, 96, 177, 2, ++ 41, 10, 208, 178, 241, 128, 127, 7, 210, 1, 56, 178, 245, 128, 63, 3, ++ 210, 152, 30, 255, 42, 152, 191, 216, 30, 112, 71, 45, 233, 248, 67, ++ 71, 104, 13, 70, 191, 0, 159, 66, 20, 70, 0, 241, 8, 9, 4, 219, 255, ++ 26, 30, 70, 79, 240, 0, 8, 8, 224, 199, 235, 3, 8, 16, 70, 0, 33, 66, ++ 70, 254, 243, 57, 243, 62, 70, 0, 39, 2, 45, 4, 235, 8, 1, 6, 209, 8, ++ 70, 50, 70, 9, 235, 7, 1, 252, 247, 173, 255, 6, 224, 39, 240, 3, 7, ++ 9, 235, 7, 0, 50, 70, 255, 247, 158, 250, 48, 70, 189, 232, 248, 131, ++ 0, 104, 112, 71, 112, 181, 4, 70, 136, 177, 0, 104, 120, 177, 255, 247, ++ 247, 255, 35, 104, 6, 70, 88, 104, 128, 0, 255, 247, 180, 250, 51, 70, ++ 2, 70, 117, 104, 176, 104, 33, 104, 168, 71, 0, 35, 35, 96, 112, 189, ++ 248, 181, 12, 70, 1, 33, 5, 70, 255, 247, 154, 255, 1, 33, 6, 70, 32, ++ 70, 255, 247, 149, 255, 134, 66, 31, 220, 27, 219, 104, 104, 97, 104, ++ 3, 54, 182, 16, 0, 35, 128, 27, 8, 53, 137, 27, 8, 52, 26, 70, 12, 224, ++ 5, 235, 128, 7, 87, 248, 3, 192, 4, 235, 129, 7, 255, 88, 188, 69, 10, ++ 216, 3, 241, 4, 3, 9, 211, 1, 50, 178, 66, 240, 219, 0, 32, 248, 189, ++ 79, 240, 255, 48, 248, 189, 1, 32, 248, 189, 79, 240, 255, 48, 248, ++ 189, 240, 181, 70, 104, 77, 104, 51, 70, 8, 48, 42, 70, 8, 49, 0, 36, ++ 9, 224, 1, 235, 133, 7, 87, 248, 4, 192, 0, 235, 134, 7, 1, 59, 1, 58, ++ 71, 248, 4, 192, 0, 43, 2, 220, 28, 70, 0, 33, 8, 224, 4, 60, 0, 42, ++ 237, 220, 248, 231, 0, 235, 132, 5, 0, 38, 1, 59, 110, 80, 4, 57, 0, ++ 43, 247, 220, 210, 241, 1, 0, 56, 191, 0, 32, 240, 189, 66, 104, 8, ++ 48, 83, 30, 80, 248, 35, 48, 48, 181, 139, 66, 18, 209, 0, 33, 0, 224, ++ 1, 49, 80, 248, 4, 75, 85, 30, 12, 185, 169, 66, 248, 211, 169, 66, ++ 4, 209, 225, 26, 75, 66, 67, 235, 1, 3, 0, 224, 0, 35, 216, 178, 48, ++ 189, 0, 32, 48, 189, 67, 104, 0, 235, 131, 0, 64, 104, 0, 240, 1, 0, ++ 112, 71, 56, 181, 69, 104, 0, 241, 8, 4, 1, 61, 32, 70, 0, 33, 42, 70, ++ 254, 243, 129, 242, 1, 35, 68, 248, 37, 48, 56, 189, 8, 181, 3, 70, ++ 0, 33, 8, 48, 90, 104, 255, 247, 28, 250, 192, 178, 8, 189, 112, 181, ++ 6, 29, 4, 70, 29, 70, 48, 70, 4, 49, 4, 50, 255, 247, 92, 250, 109, ++ 177, 40, 185, 32, 70, 41, 70, 255, 247, 91, 255, 0, 40, 6, 221, 48, ++ 70, 49, 70, 42, 29, 189, 232, 112, 64, 255, 247, 203, 186, 112, 189, ++ 56, 181, 5, 29, 28, 70, 40, 70, 4, 49, 4, 50, 255, 247, 194, 250, 60, ++ 177, 48, 177, 40, 70, 41, 70, 34, 29, 189, 232, 56, 64, 255, 247, 59, ++ 186, 56, 189, 45, 233, 243, 65, 28, 70, 13, 241, 8, 8, 130, 234, 226, ++ 115, 163, 235, 226, 115, 13, 70, 23, 70, 6, 70, 72, 248, 8, 61, 255, ++ 247, 23, 255, 2, 33, 4, 35, 106, 70, 255, 247, 193, 253, 0, 47, 2, 70, ++ 1, 144, 41, 70, 48, 70, 35, 70, 2, 218, 255, 247, 208, 255, 1, 224, ++ 255, 247, 180, 255, 1, 168, 255, 247, 5, 255, 189, 232, 252, 129, 240, ++ 181, 133, 176, 20, 70, 13, 70, 6, 70, 255, 247, 250, 254, 99, 104, 2, ++ 33, 4, 241, 8, 2, 139, 64, 7, 70, 255, 247, 161, 253, 107, 104, 2, 33, ++ 1, 51, 139, 64, 1, 144, 0, 34, 56, 70, 255, 247, 152, 253, 99, 104, ++ 2, 33, 2, 144, 0, 34, 139, 64, 56, 70, 255, 247, 144, 253, 3, 144, 32, ++ 70, 255, 247, 201, 253, 100, 104, 100, 1, 4, 27, 0, 224, 32, 52, 20, ++ 241, 31, 15, 251, 219, 2, 152, 41, 70, 255, 247, 27, 255, 60, 177, 1, ++ 152, 33, 70, 255, 247, 205, 253, 2, 152, 33, 70, 255, 247, 201, 253, ++ 2, 152, 1, 153, 4, 48, 4, 49, 255, 247, 224, 250, 2, 152, 1, 153, 255, ++ 247, 214, 254, 0, 40, 5, 219, 2, 152, 1, 154, 1, 70, 0, 35, 255, 247, ++ 125, 255, 28, 177, 2, 152, 97, 66, 255, 247, 178, 253, 2, 153, 48, 70, ++ 255, 247, 247, 254, 3, 168, 255, 247, 172, 254, 2, 168, 255, 247, 169, ++ 254, 1, 168, 255, 247, 166, 254, 5, 176, 240, 189, 45, 233, 247, 67, ++ 4, 70, 136, 70, 145, 70, 29, 70, 8, 241, 4, 7, 255, 247, 152, 254, 9, ++ 241, 4, 6, 1, 148, 77, 185, 217, 248, 4, 32, 216, 248, 4, 48, 211, 24, ++ 98, 104, 154, 66, 1, 211, 32, 29, 11, 224, 217, 248, 4, 32, 216, 248, ++ 4, 48, 1, 33, 211, 24, 155, 0, 0, 34, 255, 247, 47, 253, 1, 144, 4, ++ 48, 57, 70, 50, 70, 255, 247, 14, 252, 53, 185, 1, 153, 140, 66, 8, ++ 208, 32, 70, 255, 247, 189, 254, 4, 224, 32, 70, 1, 153, 42, 70, 255, ++ 247, 108, 255, 1, 155, 156, 66, 2, 208, 1, 168, 255, 247, 105, 254, ++ 189, 232, 254, 131, 240, 181, 133, 176, 4, 172, 68, 248, 12, 45, 14, ++ 70, 29, 70, 7, 70, 255, 247, 91, 254, 2, 33, 34, 70, 4, 35, 255, 247, ++ 5, 253, 4, 172, 68, 248, 4, 13, 2, 70, 49, 70, 56, 70, 43, 70, 255, ++ 247, 171, 255, 32, 70, 255, 247, 76, 254, 5, 176, 240, 189, 247, 181, ++ 4, 70, 15, 70, 21, 70, 62, 29, 255, 247, 65, 254, 1, 148, 53, 185, 122, ++ 104, 99, 104, 179, 235, 66, 15, 1, 211, 32, 29, 7, 224, 123, 104, 1, ++ 33, 0, 34, 219, 0, 255, 247, 225, 252, 1, 144, 4, 48, 49, 70, 255, 247, ++ 48, 252, 53, 185, 1, 153, 140, 66, 8, 208, 32, 70, 255, 247, 112, 254, ++ 4, 224, 32, 70, 1, 153, 42, 70, 255, 247, 31, 255, 1, 155, 156, 66, ++ 2, 208, 1, 168, 255, 247, 28, 254, 254, 189, 45, 233, 240, 79, 143, ++ 176, 3, 144, 16, 70, 137, 70, 146, 70, 255, 247, 16, 254, 217, 248, ++ 4, 80, 1, 33, 108, 0, 173, 0, 0, 34, 43, 70, 6, 70, 255, 247, 181, 252, ++ 1, 33, 0, 34, 43, 70, 9, 144, 48, 70, 255, 247, 174, 252, 1, 33, 0, ++ 34, 43, 70, 10, 144, 48, 70, 255, 247, 167, 252, 1, 33, 0, 34, 43, 70, ++ 11, 144, 48, 70, 255, 247, 160, 252, 1, 33, 0, 34, 43, 70, 12, 144, ++ 48, 70, 255, 247, 153, 252, 10, 159, 1, 70, 7, 241, 8, 3, 7, 147, 12, ++ 155, 1, 34, 4, 147, 8, 51, 5, 147, 0, 241, 8, 3, 6, 147, 0, 35, 128, ++ 70, 13, 144, 9, 157, 11, 158, 255, 247, 175, 254, 3, 152, 13, 153, 255, ++ 247, 234, 253, 8, 53, 0, 40, 6, 241, 8, 11, 2, 220, 80, 70, 3, 153, ++ 77, 224, 73, 70, 11, 152, 255, 247, 16, 254, 3, 153, 10, 152, 255, 247, ++ 12, 254, 56, 29, 255, 247, 208, 249, 8, 241, 4, 8, 48, 29, 255, 247, ++ 203, 249, 64, 70, 255, 247, 200, 249, 7, 159, 0, 38, 51, 70, 57, 70, ++ 42, 70, 88, 70, 0, 148, 255, 247, 160, 250, 6, 153, 6, 70, 42, 70, 5, ++ 152, 35, 70, 255, 247, 64, 250, 88, 70, 49, 70, 34, 70, 255, 247, 134, ++ 248, 80, 177, 4, 155, 24, 29, 255, 247, 174, 249, 80, 70, 73, 70, 12, ++ 154, 0, 35, 255, 247, 94, 254, 27, 224, 51, 70, 89, 70, 42, 70, 56, ++ 70, 0, 148, 255, 247, 129, 250, 5, 153, 6, 70, 42, 70, 6, 152, 35, 70, ++ 255, 247, 33, 250, 56, 70, 49, 70, 34, 70, 255, 247, 103, 248, 0, 40, ++ 203, 208, 64, 70, 255, 247, 143, 249, 13, 153, 80, 70, 255, 247, 196, ++ 253, 13, 168, 255, 247, 121, 253, 12, 168, 255, 247, 118, 253, 11, 168, ++ 255, 247, 115, 253, 10, 168, 255, 247, 112, 253, 9, 168, 255, 247, 109, ++ 253, 15, 176, 189, 232, 240, 143, 247, 181, 5, 70, 30, 70, 16, 70, 15, ++ 70, 20, 70, 255, 247, 96, 253, 115, 104, 1, 33, 0, 34, 155, 0, 255, ++ 247, 9, 252, 1, 144, 40, 70, 255, 247, 237, 253, 1, 152, 57, 70, 255, ++ 247, 156, 253, 19, 224, 32, 70, 255, 247, 222, 253, 40, 177, 40, 70, ++ 41, 70, 1, 154, 51, 70, 255, 247, 165, 254, 32, 70, 1, 33, 255, 247, ++ 68, 252, 1, 152, 51, 70, 1, 70, 2, 70, 255, 247, 155, 254, 32, 70, 0, ++ 33, 255, 247, 172, 253, 0, 40, 229, 208, 1, 168, 255, 247, 54, 253, ++ 254, 189, 240, 181, 7, 70, 133, 176, 8, 70, 12, 70, 255, 247, 44, 253, ++ 101, 104, 1, 33, 173, 0, 0, 34, 43, 70, 6, 70, 255, 247, 211, 251, 1, ++ 33, 1, 144, 0, 34, 43, 70, 48, 70, 255, 247, 204, 251, 1, 33, 0, 34, ++ 43, 70, 2, 144, 48, 70, 255, 247, 197, 251, 3, 144, 2, 152, 255, 247, ++ 169, 253, 2, 154, 35, 70, 1, 152, 33, 70, 255, 247, 211, 253, 1, 152, ++ 1, 33, 255, 247, 9, 252, 3, 152, 57, 70, 1, 154, 35, 70, 255, 247, 154, ++ 255, 1, 33, 3, 152, 255, 247, 113, 253, 1, 70, 64, 185, 3, 152, 255, ++ 247, 108, 253, 0, 40, 12, 191, 79, 240, 255, 52, 0, 36, 0, 224, 1, 36, ++ 3, 168, 255, 247, 241, 252, 2, 168, 255, 247, 238, 252, 1, 168, 255, ++ 247, 235, 252, 32, 70, 5, 176, 240, 189, 45, 233, 240, 79, 128, 70, ++ 195, 176, 24, 70, 28, 70, 137, 70, 22, 70, 221, 248, 48, 161, 221, 248, ++ 52, 177, 255, 247, 216, 252, 101, 104, 1, 33, 173, 0, 0, 34, 43, 70, ++ 7, 70, 255, 247, 127, 251, 1, 33, 64, 144, 0, 34, 43, 70, 56, 70, 255, ++ 247, 120, 251, 1, 33, 65, 144, 32, 170, 32, 70, 43, 70, 255, 247, 149, ++ 252, 88, 70, 105, 70, 42, 70, 208, 71, 104, 70, 32, 169, 42, 70, 252, ++ 247, 72, 252, 0, 40, 244, 218, 1, 33, 106, 70, 43, 70, 65, 152, 255, ++ 247, 33, 252, 65, 153, 64, 152, 10, 70, 35, 70, 255, 247, 9, 254, 64, ++ 152, 35, 70, 2, 70, 49, 70, 255, 247, 3, 254, 65, 152, 255, 247, 50, ++ 253, 64, 155, 88, 177, 24, 70, 25, 70, 66, 70, 35, 70, 255, 247, 248, ++ 253, 64, 152, 33, 70, 255, 247, 99, 255, 1, 40, 10, 224, 24, 70, 25, ++ 70, 74, 70, 35, 70, 255, 247, 236, 253, 64, 152, 33, 70, 255, 247, 87, ++ 255, 1, 48, 65, 168, 20, 191, 0, 36, 1, 36, 255, 247, 133, 252, 64, ++ 168, 255, 247, 130, 252, 32, 70, 67, 176, 189, 232, 240, 143, 66, 104, ++ 211, 8, 3, 96, 131, 104, 82, 6, 66, 234, 211, 18, 34, 240, 112, 66, ++ 66, 96, 194, 104, 155, 5, 67, 234, 146, 35, 35, 240, 96, 67, 131, 96, ++ 3, 105, 146, 4, 66, 234, 147, 50, 34, 240, 112, 66, 194, 96, 66, 105, ++ 155, 3, 67, 234, 146, 67, 35, 240, 112, 67, 3, 97, 131, 105, 210, 2, ++ 66, 234, 83, 82, 34, 240, 96, 66, 66, 97, 194, 105, 219, 1, 67, 234, ++ 82, 99, 35, 240, 112, 67, 131, 97, 3, 106, 210, 0, 66, 234, 83, 114, ++ 34, 240, 112, 66, 35, 240, 96, 67, 194, 97, 3, 98, 112, 71, 195, 105, ++ 2, 106, 66, 234, 67, 114, 2, 98, 130, 105, 219, 8, 67, 234, 66, 99, ++ 195, 97, 67, 105, 210, 9, 66, 234, 67, 82, 130, 97, 2, 105, 219, 10, ++ 67, 234, 130, 67, 67, 97, 195, 104, 146, 11, 66, 234, 131, 50, 2, 97, ++ 130, 104, 155, 12, 67, 234, 130, 35, 195, 96, 67, 104, 146, 13, 66, ++ 234, 195, 18, 130, 96, 2, 104, 91, 14, 67, 234, 194, 3, 67, 96, 0, 35, ++ 3, 96, 112, 71, 45, 233, 247, 79, 12, 106, 207, 105, 164, 251, 4, 35, ++ 192, 233, 32, 35, 167, 251, 4, 35, 209, 248, 24, 192, 146, 24, 67, 235, ++ 3, 3, 192, 233, 30, 35, 172, 251, 4, 35, 231, 251, 7, 35, 146, 24, 67, ++ 235, 3, 3, 192, 233, 28, 35, 172, 251, 7, 35, 209, 248, 20, 128, 146, ++ 24, 67, 235, 3, 3, 228, 251, 8, 35, 209, 248, 16, 176, 146, 24, 67, ++ 235, 3, 3, 192, 233, 26, 35, 171, 251, 4, 35, 231, 251, 8, 35, 146, ++ 24, 67, 235, 3, 3, 236, 251, 12, 35, 130, 70, 192, 233, 24, 35, 200, ++ 104, 14, 70, 1, 144, 160, 251, 4, 1, 171, 251, 7, 35, 236, 251, 8, 1, ++ 214, 248, 8, 144, 146, 24, 67, 235, 3, 3, 128, 24, 65, 235, 3, 1, 169, ++ 251, 4, 35, 0, 24, 65, 235, 1, 1, 1, 157, 202, 233, 22, 1, 144, 24, ++ 67, 235, 3, 1, 165, 251, 7, 35, 236, 251, 11, 35, 232, 251, 8, 1, 146, ++ 24, 117, 104, 67, 235, 3, 3, 146, 24, 67, 235, 3, 3, 128, 24, 65, 235, ++ 3, 1, 165, 251, 4, 35, 231, 251, 9, 35, 232, 251, 11, 35, 54, 104, 202, ++ 233, 20, 1, 1, 152, 236, 251, 0, 35, 166, 251, 4, 1, 236, 251, 9, 1, ++ 146, 24, 235, 251, 11, 1, 67, 235, 3, 3, 202, 233, 18, 35, 1, 155, 232, ++ 251, 3, 1, 165, 251, 7, 35, 146, 24, 67, 235, 3, 3, 128, 24, 65, 235, ++ 3, 1, 166, 251, 7, 35, 0, 24, 236, 251, 5, 35, 65, 235, 1, 1, 202, 233, ++ 16, 1, 1, 152, 235, 251, 0, 35, 146, 24, 67, 235, 3, 3, 232, 251, 9, ++ 35, 146, 24, 67, 235, 3, 3, 202, 233, 14, 35, 166, 251, 12, 35, 232, ++ 251, 5, 35, 235, 251, 9, 35, 146, 24, 67, 235, 3, 3, 224, 251, 0, 35, ++ 166, 251, 8, 1, 202, 233, 12, 35, 1, 155, 227, 251, 9, 1, 165, 251, ++ 11, 35, 146, 24, 67, 235, 3, 3, 128, 24, 65, 235, 3, 1, 0, 24, 166, ++ 251, 11, 35, 65, 235, 1, 1, 202, 233, 10, 1, 1, 152, 224, 251, 5, 35, ++ 146, 24, 67, 235, 3, 3, 146, 24, 67, 235, 3, 3, 233, 251, 9, 35, 202, ++ 233, 8, 35, 166, 251, 0, 35, 233, 251, 5, 35, 146, 24, 67, 235, 3, 3, ++ 202, 233, 6, 35, 166, 251, 9, 35, 229, 251, 5, 35, 146, 24, 67, 235, ++ 3, 3, 202, 233, 4, 35, 166, 251, 5, 35, 166, 251, 6, 103, 146, 24, 67, ++ 235, 3, 3, 146, 24, 67, 235, 3, 3, 202, 233, 2, 35, 202, 233, 0, 103, ++ 189, 232, 254, 143, 45, 233, 240, 79, 209, 248, 32, 192, 210, 248, 32, ++ 128, 20, 70, 168, 251, 12, 35, 145, 176, 192, 233, 32, 35, 5, 144, 224, ++ 105, 13, 70, 160, 251, 12, 35, 201, 105, 167, 105, 225, 251, 8, 35, ++ 6, 144, 168, 105, 7, 145, 9, 144, 5, 158, 167, 251, 12, 1, 198, 233, ++ 30, 35, 9, 154, 6, 158, 226, 251, 8, 1, 7, 154, 0, 35, 18, 235, 2, 10, ++ 67, 235, 3, 11, 170, 251, 6, 35, 6, 251, 11, 51, 128, 24, 8, 151, 5, ++ 159, 65, 235, 3, 1, 199, 233, 28, 1, 96, 105, 105, 105, 10, 144, 4, ++ 145, 160, 251, 12, 1, 4, 154, 8, 158, 7, 159, 226, 251, 8, 1, 166, 251, ++ 7, 35, 6, 158, 9, 159, 231, 251, 6, 35, 146, 24, 67, 235, 3, 3, 128, ++ 24, 38, 105, 65, 235, 3, 1, 5, 155, 47, 105, 195, 233, 26, 1, 166, 251, ++ 12, 35, 231, 251, 8, 35, 11, 150, 12, 151, 6, 152, 4, 153, 10, 158, ++ 225, 251, 0, 35, 7, 159, 8, 152, 231, 251, 6, 35, 9, 153, 231, 104, ++ 225, 251, 0, 35, 232, 104, 5, 158, 14, 144, 167, 251, 12, 1, 198, 233, ++ 24, 35, 14, 154, 10, 155, 226, 251, 8, 1, 9, 158, 13, 151, 230, 251, ++ 3, 1, 8, 159, 4, 154, 11, 158, 226, 251, 7, 1, 7, 159, 212, 248, 8, ++ 160, 166, 251, 7, 35, 6, 158, 12, 159, 231, 251, 6, 35, 174, 104, 146, ++ 24, 67, 235, 3, 3, 128, 24, 65, 235, 3, 1, 1, 150, 5, 155, 170, 251, ++ 12, 103, 195, 233, 22, 1, 1, 152, 10, 153, 224, 251, 8, 103, 4, 154, ++ 13, 152, 226, 251, 1, 103, 7, 153, 160, 251, 1, 35, 6, 152, 14, 153, ++ 225, 251, 0, 35, 8, 152, 12, 153, 225, 251, 0, 35, 11, 152, 9, 153, ++ 225, 251, 0, 35, 146, 24, 67, 235, 3, 3, 182, 24, 71, 235, 3, 7, 5, ++ 155, 195, 233, 20, 103, 102, 104, 213, 248, 4, 176, 166, 251, 12, 35, ++ 235, 251, 8, 35, 6, 159, 1, 152, 7, 153, 224, 251, 7, 35, 225, 251, ++ 10, 35, 8, 159, 14, 152, 13, 153, 224, 251, 7, 35, 9, 159, 10, 152, ++ 231, 251, 1, 35, 12, 153, 11, 159, 225, 251, 0, 35, 4, 152, 36, 104, ++ 224, 251, 7, 35, 5, 159, 15, 148, 199, 233, 18, 35, 15, 154, 44, 104, ++ 162, 251, 12, 1, 228, 251, 8, 1, 9, 155, 13, 157, 227, 251, 10, 1, 4, ++ 159, 8, 154, 231, 251, 5, 1, 1, 155, 10, 157, 227, 251, 2, 1, 7, 154, ++ 6, 155, 166, 251, 2, 137, 14, 159, 235, 251, 3, 137, 231, 251, 5, 1, ++ 11, 157, 12, 159, 231, 251, 5, 137, 24, 235, 8, 2, 73, 235, 9, 3, 128, ++ 24, 65, 235, 3, 1, 10, 157, 5, 155, 1, 159, 195, 233, 16, 1, 165, 251, ++ 7, 137, 15, 153, 7, 157, 6, 159, 161, 251, 5, 35, 4, 152, 228, 251, ++ 7, 35, 224, 251, 10, 137, 8, 152, 9, 153, 235, 251, 0, 35, 225, 251, ++ 6, 35, 13, 157, 12, 159, 11, 152, 231, 251, 5, 35, 14, 153, 225, 251, ++ 0, 35, 146, 24, 67, 235, 3, 3, 24, 235, 2, 8, 73, 235, 3, 9, 5, 155, ++ 195, 233, 14, 137, 15, 157, 9, 159, 8, 152, 165, 251, 7, 35, 228, 251, ++ 0, 35, 10, 153, 4, 157, 235, 251, 1, 35, 229, 251, 6, 35, 11, 159, 1, ++ 152, 12, 153, 224, 251, 7, 35, 225, 251, 10, 35, 14, 159, 13, 157, 5, ++ 152, 231, 251, 5, 35, 192, 233, 12, 35, 15, 154, 4, 155, 10, 157, 162, ++ 251, 3, 1, 228, 251, 5, 1, 231, 251, 10, 1, 12, 157, 13, 159, 1, 154, ++ 226, 251, 7, 1, 166, 251, 5, 35, 11, 159, 235, 251, 7, 35, 146, 24, ++ 67, 235, 3, 3, 128, 24, 65, 235, 3, 1, 15, 159, 5, 155, 195, 233, 10, ++ 1, 167, 251, 5, 35, 11, 152, 13, 153, 228, 251, 0, 35, 235, 251, 1, ++ 35, 14, 157, 1, 159, 229, 251, 6, 35, 146, 24, 67, 235, 3, 3, 231, 251, ++ 10, 35, 5, 152, 15, 153, 192, 233, 8, 35, 161, 251, 5, 35, 13, 157, ++ 228, 251, 5, 35, 235, 251, 10, 35, 231, 251, 6, 35, 192, 233, 6, 35, ++ 0, 35, 161, 251, 7, 1, 27, 235, 11, 8, 67, 235, 3, 9, 168, 251, 6, 35, ++ 228, 251, 10, 1, 6, 251, 9, 51, 128, 24, 65, 235, 3, 1, 15, 157, 5, ++ 155, 195, 233, 4, 1, 165, 251, 11, 35, 228, 251, 6, 35, 165, 251, 4, ++ 69, 146, 24, 5, 158, 67, 235, 3, 3, 198, 233, 2, 35, 198, 233, 0, 69, ++ 17, 176, 189, 232, 240, 143, 140, 70, 129, 111, 45, 233, 240, 79, 208, ++ 233, 32, 35, 76, 7, 198, 111, 18, 25, 67, 241, 0, 3, 204, 8, 7, 111, ++ 68, 234, 70, 116, 245, 8, 228, 24, 69, 241, 0, 5, 123, 6, 208, 248, ++ 116, 128, 228, 24, 69, 241, 0, 5, 204, 248, 60, 32, 250, 9, 208, 248, ++ 104, 144, 66, 234, 72, 98, 86, 25, 79, 234, 216, 19, 208, 248, 108, ++ 160, 67, 241, 0, 7, 79, 234, 73, 83, 204, 248, 56, 64, 79, 234, 217, ++ 34, 244, 24, 1, 110, 71, 241, 0, 5, 66, 234, 74, 82, 18, 235, 5, 8, ++ 79, 234, 218, 35, 67, 241, 0, 9, 139, 4, 70, 110, 204, 248, 52, 64, ++ 24, 235, 3, 4, 73, 241, 0, 5, 138, 11, 135, 109, 66, 234, 134, 66, 179, ++ 11, 18, 235, 5, 10, 67, 241, 0, 11, 187, 3, 208, 248, 92, 128, 204, ++ 248, 48, 64, 26, 235, 3, 4, 75, 241, 0, 5, 186, 12, 1, 109, 66, 234, ++ 136, 50, 79, 234, 152, 67, 18, 235, 5, 8, 67, 241, 0, 9, 139, 2, 70, ++ 109, 204, 248, 44, 64, 24, 235, 3, 4, 73, 241, 0, 5, 138, 13, 135, 108, ++ 66, 234, 134, 34, 179, 13, 18, 235, 5, 10, 67, 241, 0, 11, 251, 1, 208, ++ 248, 76, 128, 204, 248, 40, 64, 26, 235, 3, 4, 75, 241, 0, 5, 122, 14, ++ 1, 108, 66, 234, 200, 18, 79, 234, 88, 99, 18, 235, 5, 8, 67, 241, 0, ++ 9, 203, 0, 208, 233, 14, 171, 204, 248, 36, 64, 24, 235, 3, 4, 79, 234, ++ 202, 115, 70, 108, 73, 241, 0, 5, 20, 235, 3, 8, 69, 241, 0, 9, 76, ++ 15, 95, 234, 91, 3, 79, 234, 58, 2, 68, 234, 198, 4, 7, 107, 117, 15, ++ 18, 25, 67, 235, 5, 3, 18, 235, 9, 2, 67, 241, 0, 3, 57, 7, 84, 24, ++ 204, 248, 32, 128, 208, 248, 52, 128, 67, 241, 0, 5, 58, 9, 129, 106, ++ 66, 234, 8, 114, 79, 234, 24, 19, 18, 235, 5, 8, 67, 241, 0, 9, 11, ++ 6, 198, 106, 204, 248, 28, 64, 24, 235, 3, 4, 73, 241, 0, 5, 10, 10, ++ 7, 106, 66, 234, 6, 98, 51, 10, 18, 235, 5, 10, 67, 241, 0, 11, 59, ++ 5, 208, 248, 36, 128, 204, 248, 24, 64, 26, 235, 3, 4, 75, 241, 0, 5, ++ 58, 11, 204, 248, 20, 64, 66, 234, 8, 82, 129, 105, 79, 234, 24, 51, ++ 18, 235, 5, 8, 67, 241, 0, 9, 75, 4, 198, 105, 24, 235, 3, 4, 73, 241, ++ 0, 5, 202, 11, 208, 248, 16, 128, 66, 234, 70, 66, 243, 11, 86, 25, ++ 208, 248, 20, 144, 67, 241, 0, 7, 79, 234, 72, 51, 246, 24, 79, 234, ++ 216, 66, 66, 234, 73, 50, 71, 241, 0, 7, 204, 248, 16, 64, 132, 104, ++ 18, 235, 7, 8, 79, 234, 217, 67, 67, 241, 0, 9, 99, 2, 197, 104, 204, ++ 248, 12, 96, 24, 235, 3, 6, 73, 241, 0, 7, 226, 13, 66, 234, 69, 34, ++ 204, 248, 8, 96, 6, 104, 235, 13, 210, 25, 65, 104, 67, 241, 0, 3, 176, ++ 1, 20, 24, 67, 241, 0, 5, 178, 14, 66, 234, 129, 18, 82, 25, 204, 248, ++ 4, 64, 204, 248, 0, 32, 189, 232, 240, 143, 45, 233, 240, 79, 208, 233, ++ 18, 137, 208, 233, 20, 171, 4, 104, 19, 34, 164, 251, 2, 69, 67, 104, ++ 24, 235, 4, 8, 2, 251, 3, 85, 132, 104, 73, 235, 5, 9, 164, 251, 2, ++ 69, 195, 104, 26, 235, 4, 10, 2, 251, 3, 85, 4, 105, 75, 235, 5, 11, ++ 164, 251, 2, 69, 67, 105, 143, 176, 2, 251, 3, 85, 205, 233, 0, 137, ++ 192, 233, 18, 137, 208, 233, 22, 137, 24, 235, 4, 8, 132, 105, 73, 235, ++ 5, 9, 164, 251, 2, 69, 195, 105, 205, 233, 2, 171, 2, 251, 3, 85, 192, ++ 233, 20, 171, 208, 233, 24, 171, 26, 235, 4, 10, 4, 106, 75, 235, 5, ++ 11, 164, 251, 2, 69, 67, 106, 205, 233, 4, 137, 2, 251, 3, 85, 131, ++ 106, 192, 233, 22, 137, 208, 233, 26, 137, 24, 235, 4, 8, 73, 235, 5, ++ 9, 163, 251, 2, 69, 14, 70, 193, 106, 3, 107, 2, 251, 1, 85, 205, 233, ++ 6, 171, 192, 233, 24, 171, 208, 233, 28, 171, 26, 235, 4, 10, 75, 235, ++ 5, 11, 163, 251, 2, 69, 65, 107, 205, 233, 10, 171, 2, 251, 1, 85, 192, ++ 233, 28, 171, 208, 233, 30, 171, 26, 235, 4, 10, 75, 235, 5, 11, 205, ++ 233, 8, 137, 192, 233, 26, 137, 192, 233, 30, 171, 208, 233, 16, 35, ++ 205, 233, 12, 35, 12, 156, 13, 157, 34, 15, 221, 248, 4, 144, 66, 234, ++ 5, 18, 43, 15, 208, 233, 14, 69, 164, 24, 79, 234, 25, 98, 69, 235, ++ 3, 5, 0, 35, 164, 24, 69, 235, 3, 5, 11, 35, 164, 251, 3, 137, 3, 251, ++ 5, 153, 226, 0, 235, 0, 67, 234, 84, 115, 192, 233, 14, 69, 18, 235, ++ 8, 4, 67, 235, 9, 5, 208, 233, 32, 35, 164, 24, 69, 235, 3, 5, 68, 69, ++ 117, 235, 9, 1, 192, 233, 32, 69, 9, 210, 128, 34, 0, 35, 221, 233, ++ 10, 137, 18, 235, 8, 2, 67, 235, 9, 3, 192, 233, 28, 35, 36, 240, 96, ++ 65, 79, 234, 84, 120, 111, 240, 112, 68, 72, 234, 197, 8, 79, 234, 85, ++ 121, 10, 234, 4, 2, 0, 37, 11, 234, 5, 3, 18, 235, 8, 2, 67, 235, 9, ++ 3, 208, 233, 28, 137, 79, 234, 26, 112, 111, 240, 112, 74, 20, 15, 64, ++ 234, 11, 16, 34, 240, 112, 76, 10, 145, 8, 234, 10, 2, 49, 98, 79, 234, ++ 27, 113, 79, 240, 0, 11, 29, 15, 68, 234, 3, 20, 18, 24, 9, 234, 11, ++ 3, 67, 235, 1, 3, 18, 25, 67, 235, 5, 3, 111, 240, 96, 74, 20, 15, 34, ++ 240, 112, 71, 79, 234, 24, 114, 66, 234, 9, 18, 79, 240, 0, 11, 221, ++ 233, 8, 1, 0, 234, 10, 0, 29, 15, 68, 234, 3, 20, 128, 24, 79, 234, ++ 25, 115, 1, 234, 11, 1, 65, 235, 3, 1, 0, 25, 65, 235, 5, 1, 68, 15, ++ 77, 15, 68, 234, 193, 4, 8, 153, 221, 248, 36, 128, 32, 240, 96, 67, ++ 74, 15, 66, 234, 200, 2, 115, 97, 79, 234, 88, 115, 111, 240, 112, 72, ++ 221, 233, 6, 1, 79, 240, 0, 9, 0, 234, 8, 0, 128, 24, 1, 234, 9, 1, ++ 65, 235, 3, 1, 0, 25, 65, 235, 5, 1, 221, 248, 24, 144, 4, 15, 13, 15, ++ 68, 234, 1, 20, 7, 153, 32, 240, 112, 67, 79, 234, 25, 114, 111, 240, ++ 112, 72, 66, 234, 1, 18, 79, 240, 0, 9, 51, 97, 11, 15, 221, 233, 4, ++ 1, 0, 234, 8, 0, 128, 24, 1, 234, 9, 1, 65, 235, 3, 1, 0, 25, 65, 235, ++ 5, 1, 221, 248, 16, 144, 4, 15, 13, 15, 68, 234, 1, 20, 5, 153, 32, ++ 240, 112, 67, 79, 234, 25, 114, 66, 234, 1, 18, 243, 96, 11, 15, 221, ++ 233, 2, 1, 0, 234, 10, 0, 128, 24, 221, 248, 8, 144, 1, 234, 11, 1, ++ 65, 235, 3, 1, 221, 248, 12, 160, 0, 25, 65, 235, 5, 1, 32, 240, 96, ++ 67, 68, 15, 111, 240, 112, 72, 79, 234, 89, 112, 64, 234, 202, 0, 79, ++ 240, 0, 9, 179, 96, 221, 233, 0, 35, 2, 234, 8, 2, 68, 234, 193, 4, ++ 77, 15, 3, 234, 9, 3, 79, 234, 90, 113, 18, 24, 221, 248, 0, 144, 67, ++ 235, 1, 3, 221, 248, 4, 160, 18, 25, 67, 235, 5, 3, 34, 240, 112, 65, ++ 20, 15, 79, 234, 25, 114, 66, 234, 10, 18, 111, 240, 112, 72, 68, 234, ++ 3, 20, 2, 234, 8, 0, 221, 233, 12, 35, 2, 234, 8, 2, 128, 24, 0, 25, ++ 111, 240, 112, 66, 144, 66, 198, 248, 28, 192, 183, 97, 113, 96, 48, ++ 96, 21, 217, 10, 153, 0, 234, 2, 3, 51, 96, 1, 241, 19, 3, 179, 241, ++ 0, 95, 51, 98, 11, 211, 35, 240, 96, 67, 51, 98, 12, 241, 1, 3, 147, ++ 66, 243, 97, 3, 209, 0, 35, 1, 55, 243, 97, 183, 97, 15, 176, 189, 232, ++ 240, 143, 16, 181, 4, 104, 0, 35, 98, 24, 67, 241, 0, 3, 25, 70, 2, ++ 96, 8, 224, 80, 248, 4, 76, 0, 35, 10, 25, 67, 241, 0, 3, 25, 70, 64, ++ 248, 4, 45, 0, 41, 244, 209, 16, 189, 2, 104, 82, 26, 98, 235, 2, 3, ++ 2, 96, 6, 224, 80, 248, 4, 28, 90, 24, 67, 241, 0, 3, 64, 248, 4, 45, ++ 0, 43, 246, 209, 112, 71, 3, 104, 219, 5, 219, 13, 64, 248, 64, 59, ++ 255, 247, 212, 191, 56, 181, 4, 70, 13, 70, 28, 48, 255, 247, 206, 255, ++ 4, 241, 32, 0, 41, 70, 255, 247, 201, 255, 4, 241, 40, 0, 41, 70, 255, ++ 247, 217, 255, 4, 241, 44, 0, 41, 70, 189, 232, 56, 64, 255, 247, 189, ++ 191, 56, 181, 4, 70, 13, 70, 28, 48, 255, 247, 204, 255, 4, 241, 32, ++ 0, 41, 70, 255, 247, 199, 255, 4, 241, 40, 0, 41, 70, 255, 247, 173, ++ 255, 4, 241, 44, 0, 41, 70, 189, 232, 56, 64, 255, 247, 187, 191, 56, ++ 181, 5, 70, 12, 70, 255, 247, 161, 255, 40, 29, 33, 70, 255, 247, 178, ++ 255, 5, 241, 16, 0, 33, 70, 255, 247, 173, 255, 5, 241, 28, 0, 33, 70, ++ 189, 232, 56, 64, 255, 247, 145, 191, 56, 181, 5, 70, 12, 70, 255, 247, ++ 161, 255, 40, 29, 33, 70, 255, 247, 136, 255, 5, 241, 16, 0, 33, 70, ++ 255, 247, 131, 255, 5, 241, 28, 0, 33, 70, 189, 232, 56, 64, 255, 247, ++ 145, 191, 45, 233, 240, 71, 196, 105, 197, 107, 0, 35, 42, 25, 132, ++ 105, 67, 241, 0, 3, 18, 25, 4, 105, 67, 241, 0, 3, 18, 27, 99, 241, ++ 0, 3, 196, 104, 18, 27, 99, 241, 0, 3, 132, 104, 18, 27, 99, 241, 0, ++ 3, 68, 104, 18, 27, 99, 241, 0, 3, 202, 97, 132, 107, 133, 105, 100, ++ 43, 140, 191, 79, 240, 255, 57, 79, 240, 0, 9, 152, 70, 0, 35, 42, 25, ++ 68, 105, 67, 241, 0, 3, 18, 235, 8, 2, 67, 235, 9, 3, 18, 25, 4, 104, ++ 67, 241, 0, 3, 18, 27, 99, 241, 0, 3, 196, 104, 18, 27, 99, 241, 0, ++ 3, 68, 104, 18, 27, 99, 241, 0, 3, 132, 104, 18, 27, 99, 241, 0, 3, ++ 138, 97, 68, 107, 69, 105, 100, 43, 140, 191, 79, 240, 255, 57, 79, ++ 240, 0, 9, 152, 70, 0, 35, 42, 25, 4, 105, 67, 241, 0, 3, 18, 235, 8, ++ 2, 67, 235, 9, 3, 18, 25, 4, 104, 67, 241, 0, 3, 18, 27, 99, 241, 0, ++ 3, 132, 104, 0, 37, 18, 27, 99, 241, 0, 3, 68, 104, 18, 27, 99, 241, ++ 0, 3, 74, 97, 100, 43, 140, 191, 79, 240, 255, 57, 79, 240, 0, 9, 152, ++ 70, 3, 105, 208, 248, 48, 192, 28, 70, 195, 104, 20, 235, 12, 2, 30, ++ 70, 69, 241, 0, 3, 18, 235, 8, 2, 67, 235, 9, 3, 18, 25, 67, 235, 5, ++ 3, 132, 104, 146, 25, 67, 235, 5, 3, 146, 25, 67, 235, 5, 3, 18, 25, ++ 196, 105, 67, 241, 0, 3, 18, 27, 99, 241, 0, 3, 132, 105, 18, 27, 99, ++ 241, 0, 3, 4, 104, 18, 27, 99, 241, 0, 3, 10, 97, 100, 43, 140, 191, ++ 79, 240, 255, 57, 169, 70, 152, 70, 195, 104, 208, 248, 44, 192, 28, ++ 70, 131, 104, 20, 235, 12, 2, 30, 70, 69, 241, 0, 3, 18, 235, 8, 2, ++ 67, 235, 9, 3, 18, 25, 67, 235, 5, 3, 68, 104, 146, 25, 67, 235, 5, ++ 3, 146, 25, 67, 235, 5, 3, 18, 25, 132, 105, 67, 241, 0, 3, 18, 27, ++ 99, 241, 0, 3, 68, 105, 18, 27, 99, 241, 0, 3, 202, 96, 100, 43, 140, ++ 191, 79, 240, 255, 57, 169, 70, 152, 70, 131, 104, 208, 248, 40, 192, ++ 28, 70, 67, 104, 20, 235, 12, 2, 30, 70, 69, 241, 0, 3, 18, 235, 8, ++ 2, 67, 235, 9, 3, 18, 25, 67, 235, 5, 3, 4, 104, 146, 25, 67, 235, 5, ++ 3, 146, 25, 67, 235, 5, 3, 18, 25, 68, 105, 67, 241, 0, 3, 18, 27, 99, ++ 241, 0, 3, 4, 105, 18, 27, 99, 241, 0, 3, 138, 96, 100, 43, 140, 191, ++ 79, 240, 255, 57, 169, 70, 152, 70, 67, 104, 208, 248, 36, 160, 208, ++ 248, 8, 192, 28, 70, 3, 104, 28, 235, 10, 2, 30, 70, 69, 241, 0, 3, ++ 18, 235, 8, 2, 67, 235, 9, 3, 18, 25, 67, 235, 5, 3, 18, 25, 67, 235, ++ 5, 3, 18, 25, 67, 235, 5, 3, 146, 25, 196, 105, 67, 235, 5, 3, 146, ++ 25, 67, 235, 5, 3, 18, 27, 99, 241, 0, 3, 132, 105, 18, 27, 99, 241, ++ 0, 3, 74, 96, 7, 106, 198, 105, 100, 43, 140, 191, 79, 240, 255, 57, ++ 169, 70, 152, 70, 3, 104, 242, 25, 28, 70, 69, 241, 0, 3, 18, 235, 8, ++ 2, 67, 235, 9, 3, 18, 25, 67, 235, 5, 3, 18, 25, 67, 235, 5, 3, 18, ++ 25, 4, 105, 67, 235, 5, 3, 18, 27, 99, 241, 0, 3, 196, 104, 18, 27, ++ 99, 241, 0, 3, 132, 104, 64, 105, 18, 27, 99, 241, 0, 3, 18, 26, 99, ++ 241, 0, 3, 100, 43, 10, 96, 8, 70, 4, 217, 89, 66, 189, 232, 240, 71, ++ 255, 247, 161, 190, 25, 70, 189, 232, 240, 71, 255, 247, 135, 190, 1, ++ 40, 9, 208, 2, 40, 9, 208, 3, 40, 9, 208, 5, 75, 4, 40, 12, 191, 24, ++ 70, 0, 32, 112, 71, 3, 72, 112, 71, 3, 72, 112, 71, 3, 72, 112, 71, ++ 192, 96, 4, 0, 16, 96, 4, 0, 28, 98, 4, 0, 40, 95, 4, 0, 8, 181, 255, ++ 247, 227, 255, 0, 177, 0, 122, 8, 189, 45, 233, 240, 79, 1, 57, 80, ++ 248, 33, 48, 4, 70, 133, 176, 152, 70, 79, 240, 0, 9, 14, 70, 32, 32, ++ 69, 224, 16, 185, 1, 57, 31, 32, 0, 224, 1, 56, 142, 66, 14, 217, 0, ++ 37, 84, 248, 33, 48, 205, 248, 8, 144, 3, 149, 221, 233, 2, 137, 24, ++ 235, 3, 8, 73, 241, 0, 9, 68, 248, 33, 128, 14, 70, 26, 77, 0, 39, 85, ++ 248, 32, 48, 1, 151, 0, 147, 221, 233, 0, 171, 8, 234, 10, 2, 9, 234, ++ 11, 3, 82, 234, 3, 11, 32, 208, 16, 185, 1, 57, 31, 32, 4, 224, 1, 56, ++ 2, 209, 1, 57, 31, 32, 0, 224, 1, 56, 84, 248, 33, 32, 85, 248, 32, ++ 48, 0, 157, 26, 66, 20, 191, 79, 240, 8, 10, 79, 240, 3, 10, 170, 251, ++ 5, 35, 79, 240, 0, 11, 5, 251, 11, 51, 24, 235, 2, 8, 73, 235, 3, 9, ++ 68, 248, 38, 128, 0, 46, 183, 209, 5, 176, 189, 232, 240, 143, 248, ++ 26, 4, 0, 45, 233, 240, 67, 5, 70, 8, 106, 12, 70, 162, 251, 0, 1, 32, ++ 240, 96, 73, 22, 70, 197, 248, 32, 144, 66, 15, 231, 105, 66, 234, 193, ++ 2, 75, 15, 16, 70, 25, 70, 230, 251, 7, 1, 32, 240, 112, 72, 197, 248, ++ 28, 128, 2, 15, 167, 105, 66, 234, 1, 18, 11, 15, 16, 70, 25, 70, 230, ++ 251, 7, 1, 32, 240, 112, 76, 197, 248, 24, 192, 2, 15, 103, 105, 66, ++ 234, 1, 18, 11, 15, 16, 70, 25, 70, 230, 251, 7, 1, 32, 240, 96, 67, ++ 107, 97, 66, 15, 39, 105, 66, 234, 193, 2, 75, 15, 16, 70, 25, 70, 230, ++ 251, 7, 1, 32, 240, 112, 67, 43, 97, 2, 15, 231, 104, 66, 234, 1, 18, ++ 11, 15, 16, 70, 25, 70, 230, 251, 7, 1, 32, 240, 112, 67, 235, 96, 2, ++ 15, 167, 104, 66, 234, 1, 18, 11, 15, 16, 70, 25, 70, 230, 251, 7, 1, ++ 32, 240, 96, 67, 171, 96, 66, 15, 103, 104, 66, 234, 193, 2, 75, 15, ++ 16, 70, 25, 70, 230, 251, 7, 1, 32, 240, 112, 67, 107, 96, 36, 104, ++ 2, 15, 11, 15, 66, 234, 1, 18, 230, 251, 4, 35, 34, 240, 112, 65, 18, ++ 15, 82, 234, 3, 18, 41, 96, 19, 208, 19, 35, 3, 251, 2, 146, 178, 241, ++ 0, 95, 42, 98, 12, 211, 8, 241, 1, 3, 179, 241, 128, 95, 34, 240, 96, ++ 66, 235, 97, 8, 191, 12, 241, 1, 3, 42, 98, 8, 191, 171, 97, 189, 232, ++ 240, 131, 16, 181, 180, 176, 43, 170, 36, 35, 4, 70, 8, 70, 2, 33, 254, ++ 247, 192, 251, 43, 168, 254, 247, 110, 255, 104, 70, 43, 169, 254, 247, ++ 205, 255, 34, 169, 104, 70, 255, 247, 107, 251, 34, 168, 254, 247, 155, ++ 255, 32, 70, 2, 33, 34, 170, 36, 35, 254, 247, 73, 251, 52, 176, 16, ++ 189, 48, 181, 191, 176, 36, 35, 4, 70, 21, 70, 8, 70, 44, 170, 2, 33, ++ 254, 247, 160, 251, 44, 168, 254, 247, 78, 255, 36, 35, 2, 33, 53, 170, ++ 40, 70, 254, 247, 151, 251, 53, 168, 254, 247, 69, 255, 53, 170, 104, ++ 70, 44, 169, 255, 247, 141, 248, 35, 169, 104, 70, 255, 247, 65, 251, ++ 35, 168, 254, 247, 113, 255, 32, 70, 2, 33, 35, 170, 36, 35, 254, 247, ++ 31, 251, 63, 176, 48, 189, 45, 233, 240, 65, 180, 176, 136, 70, 1, 170, ++ 2, 33, 136, 35, 254, 247, 119, 251, 17, 153, 16, 156, 75, 10, 202, 5, ++ 34, 153, 52, 174, 82, 24, 67, 241, 0, 3, 24, 70, 33, 155, 0, 33, 192, ++ 24, 65, 241, 0, 1, 51, 146, 226, 5, 99, 10, 128, 24, 32, 156, 65, 235, ++ 3, 1, 50, 144, 0, 35, 8, 25, 15, 156, 67, 241, 0, 1, 226, 5, 99, 10, ++ 128, 24, 31, 156, 65, 235, 3, 1, 49, 144, 0, 35, 8, 25, 14, 156, 67, ++ 241, 0, 1, 226, 5, 99, 10, 128, 24, 30, 156, 65, 235, 3, 1, 48, 144, ++ 0, 35, 8, 25, 13, 156, 67, 241, 0, 1, 226, 5, 99, 10, 128, 24, 29, 156, ++ 65, 235, 3, 1, 47, 144, 0, 35, 8, 25, 12, 156, 67, 241, 0, 1, 226, 5, ++ 99, 10, 128, 24, 28, 156, 65, 235, 3, 1, 46, 144, 0, 35, 8, 25, 11, ++ 156, 67, 241, 0, 1, 226, 5, 99, 10, 128, 24, 27, 156, 65, 235, 3, 1, ++ 45, 144, 0, 35, 8, 25, 10, 156, 67, 241, 0, 1, 226, 5, 99, 10, 128, ++ 24, 26, 156, 65, 235, 3, 1, 44, 144, 0, 35, 8, 25, 9, 156, 67, 241, ++ 0, 1, 226, 5, 99, 10, 128, 24, 25, 156, 65, 235, 3, 1, 43, 144, 0, 35, ++ 8, 25, 8, 156, 67, 241, 0, 1, 226, 5, 99, 10, 128, 24, 24, 156, 65, ++ 235, 3, 1, 42, 144, 0, 35, 8, 25, 7, 156, 67, 241, 0, 1, 226, 5, 99, ++ 10, 128, 24, 23, 156, 65, 235, 3, 1, 41, 144, 0, 35, 8, 25, 6, 156, ++ 67, 241, 0, 1, 226, 5, 99, 10, 128, 24, 40, 144, 22, 156, 65, 235, 3, ++ 1, 0, 35, 8, 25, 5, 156, 67, 241, 0, 1, 226, 5, 99, 10, 128, 24, 21, ++ 156, 65, 235, 3, 1, 39, 144, 0, 35, 8, 25, 4, 156, 67, 241, 0, 1, 226, ++ 5, 99, 10, 128, 24, 20, 156, 65, 235, 3, 1, 38, 144, 0, 35, 8, 25, 3, ++ 156, 67, 241, 0, 1, 226, 5, 99, 10, 128, 24, 19, 156, 65, 235, 3, 1, ++ 37, 144, 0, 35, 8, 25, 2, 156, 67, 241, 0, 1, 226, 5, 99, 10, 128, 24, ++ 65, 235, 3, 1, 18, 155, 0, 37, 204, 24, 1, 153, 69, 241, 0, 5, 202, ++ 5, 75, 10, 164, 24, 69, 235, 3, 5, 70, 248, 68, 77, 233, 5, 36, 144, ++ 65, 234, 84, 33, 48, 70, 255, 247, 47, 252, 64, 70, 2, 33, 50, 70, 68, ++ 35, 254, 247, 61, 250, 52, 176, 189, 232, 240, 129, 45, 233, 240, 79, ++ 179, 176, 96, 35, 13, 145, 14, 170, 2, 33, 254, 247, 148, 250, 16, 154, ++ 0, 39, 25, 158, 17, 152, 37, 153, 141, 232, 132, 0, 6, 144, 7, 151, ++ 114, 24, 221, 233, 6, 69, 71, 241, 0, 3, 18, 25, 221, 248, 56, 128, ++ 221, 233, 0, 1, 67, 235, 5, 3, 18, 24, 185, 70, 67, 235, 1, 3, 178, ++ 235, 8, 2, 99, 235, 9, 3, 221, 248, 144, 224, 49, 146, 15, 154, 24, ++ 152, 100, 43, 140, 191, 79, 240, 255, 53, 61, 70, 2, 146, 28, 70, 24, ++ 235, 14, 2, 71, 241, 0, 3, 18, 25, 3, 151, 67, 235, 5, 3, 18, 24, 221, ++ 233, 2, 69, 67, 235, 7, 3, 18, 25, 67, 235, 5, 3, 221, 248, 140, 224, ++ 221, 233, 6, 69, 18, 27, 99, 235, 5, 3, 146, 27, 99, 235, 7, 3, 221, ++ 248, 92, 160, 100, 43, 140, 191, 79, 240, 255, 53, 61, 70, 28, 70, 48, ++ 146, 24, 235, 14, 2, 71, 241, 0, 3, 18, 25, 67, 235, 5, 3, 18, 235, ++ 10, 2, 67, 235, 7, 3, 57, 70, 18, 26, 99, 235, 1, 3, 221, 233, 0, 69, ++ 18, 27, 99, 235, 5, 3, 47, 146, 22, 154, 100, 43, 140, 191, 79, 240, ++ 255, 53, 61, 70, 28, 70, 8, 146, 221, 233, 6, 35, 146, 25, 34, 158, ++ 67, 235, 7, 3, 205, 233, 4, 35, 221, 233, 0, 35, 146, 25, 9, 151, 67, ++ 241, 0, 3, 18, 25, 67, 235, 5, 3, 221, 233, 8, 69, 18, 25, 187, 70, ++ 67, 235, 5, 3, 221, 233, 4, 103, 146, 25, 67, 235, 7, 3, 178, 235, 8, ++ 2, 99, 235, 9, 3, 221, 233, 2, 69, 18, 27, 99, 235, 5, 3, 178, 235, ++ 10, 2, 99, 235, 11, 3, 46, 146, 100, 43, 140, 191, 79, 240, 255, 53, ++ 77, 70, 28, 70, 221, 233, 0, 35, 146, 24, 67, 235, 3, 3, 18, 25, 67, ++ 235, 5, 3, 18, 24, 221, 233, 2, 69, 21, 158, 67, 235, 9, 3, 18, 25, ++ 33, 156, 10, 150, 205, 248, 44, 144, 67, 235, 5, 3, 18, 25, 221, 233, ++ 10, 103, 67, 241, 0, 3, 146, 25, 221, 233, 4, 69, 67, 235, 7, 3, 18, ++ 25, 67, 235, 5, 3, 221, 233, 8, 103, 146, 27, 99, 235, 7, 3, 178, 235, ++ 8, 2, 99, 235, 9, 3, 178, 235, 8, 2, 99, 235, 9, 3, 100, 43, 140, 191, ++ 79, 240, 255, 53, 77, 70, 28, 70, 45, 146, 221, 233, 0, 35, 18, 235, ++ 8, 2, 67, 235, 9, 3, 18, 25, 67, 235, 5, 3, 18, 24, 221, 233, 2, 69, ++ 67, 235, 9, 3, 18, 25, 20, 159, 67, 235, 5, 3, 32, 153, 18, 25, 67, ++ 235, 5, 3, 18, 235, 10, 2, 4, 151, 205, 248, 20, 144, 67, 235, 9, 3, ++ 82, 24, 221, 233, 4, 103, 67, 241, 0, 3, 146, 25, 67, 235, 7, 3, 221, ++ 233, 10, 1, 18, 26, 99, 235, 1, 3, 100, 43, 140, 191, 79, 240, 255, ++ 53, 77, 70, 28, 70, 44, 146, 24, 235, 8, 2, 73, 235, 9, 3, 18, 25, 67, ++ 235, 5, 3, 221, 233, 2, 69, 18, 25, 67, 235, 5, 3, 18, 235, 10, 2, 221, ++ 233, 8, 1, 67, 235, 9, 3, 18, 24, 67, 235, 1, 3, 31, 153, 19, 158, 82, ++ 24, 67, 241, 0, 3, 146, 25, 67, 235, 9, 3, 221, 233, 4, 69, 18, 27, ++ 99, 235, 5, 3, 100, 43, 140, 191, 79, 240, 255, 53, 77, 70, 28, 70, ++ 43, 146, 221, 233, 8, 35, 18, 235, 8, 2, 67, 235, 9, 3, 18, 25, 221, ++ 233, 10, 1, 67, 235, 5, 3, 18, 24, 67, 235, 1, 3, 30, 153, 221, 248, ++ 72, 160, 82, 24, 67, 241, 0, 3, 18, 235, 10, 2, 67, 235, 9, 3, 79, 70, ++ 146, 27, 99, 235, 7, 3, 221, 233, 10, 1, 100, 43, 140, 191, 79, 240, ++ 255, 53, 77, 70, 28, 70, 42, 146, 221, 233, 6, 35, 18, 24, 67, 235, ++ 1, 3, 18, 25, 29, 153, 67, 235, 5, 3, 221, 233, 4, 69, 18, 25, 67, 235, ++ 5, 3, 82, 24, 67, 241, 0, 3, 178, 235, 10, 2, 99, 235, 11, 3, 41, 146, ++ 100, 43, 140, 191, 79, 240, 255, 53, 77, 70, 221, 233, 4, 1, 28, 70, ++ 221, 233, 0, 35, 18, 24, 67, 235, 1, 3, 18, 25, 28, 153, 67, 235, 5, ++ 3, 146, 25, 67, 235, 9, 3, 82, 24, 67, 241, 0, 3, 221, 233, 6, 69, 18, ++ 27, 99, 235, 5, 3, 100, 43, 140, 191, 79, 240, 255, 53, 77, 70, 28, ++ 70, 40, 146, 221, 233, 2, 35, 146, 25, 67, 235, 9, 3, 27, 153, 18, 25, ++ 67, 235, 5, 3, 18, 235, 10, 2, 67, 235, 9, 3, 82, 24, 67, 241, 0, 3, ++ 221, 233, 0, 103, 146, 27, 99, 235, 7, 3, 100, 43, 140, 191, 79, 240, ++ 255, 53, 77, 70, 221, 233, 6, 1, 16, 235, 8, 0, 65, 235, 9, 1, 26, 156, ++ 192, 24, 65, 235, 5, 1, 16, 235, 10, 0, 65, 235, 9, 1, 39, 146, 2, 25, ++ 65, 241, 0, 3, 221, 233, 2, 1, 18, 26, 99, 235, 1, 3, 100, 43, 50, 168, ++ 64, 248, 48, 45, 11, 217, 89, 66, 255, 247, 123, 250, 13, 152, 2, 33, ++ 38, 170, 48, 35, 254, 247, 107, 248, 51, 176, 189, 232, 240, 143, 25, ++ 70, 255, 247, 88, 250, 242, 231, 16, 181, 196, 176, 51, 170, 36, 35, ++ 4, 70, 8, 70, 2, 33, 254, 247, 190, 248, 51, 168, 254, 247, 108, 252, ++ 104, 70, 51, 169, 254, 247, 203, 252, 104, 70, 35, 169, 254, 247, 76, ++ 255, 35, 168, 60, 169, 255, 247, 151, 250, 32, 70, 2, 33, 60, 170, 32, ++ 35, 254, 247, 70, 248, 68, 176, 16, 189, 48, 181, 205, 176, 36, 35, ++ 4, 70, 21, 70, 8, 70, 50, 170, 2, 33, 254, 247, 157, 248, 50, 168, 254, ++ 247, 75, 252, 36, 35, 2, 33, 59, 170, 40, 70, 254, 247, 148, 248, 59, ++ 168, 254, 247, 66, 252, 59, 170, 104, 70, 50, 169, 254, 247, 138, 253, ++ 104, 70, 34, 169, 254, 247, 33, 255, 34, 168, 68, 169, 255, 247, 108, ++ 250, 32, 70, 2, 33, 68, 170, 32, 35, 254, 247, 27, 248, 77, 176, 48, ++ 189, 56, 181, 5, 70, 28, 70, 24, 70, 0, 35, 254, 247, 0, 250, 32, 70, ++ 41, 70, 189, 232, 56, 64, 255, 247, 239, 188, 56, 181, 5, 70, 28, 70, ++ 24, 70, 0, 35, 254, 247, 243, 249, 32, 70, 41, 70, 189, 232, 56, 64, ++ 255, 247, 197, 189, 240, 181, 153, 176, 22, 70, 48, 35, 4, 70, 15, 70, ++ 8, 70, 12, 170, 2, 33, 254, 247, 87, 248, 4, 46, 12, 157, 1, 209, 173, ++ 15, 0, 224, 109, 15, 32, 70, 57, 70, 50, 70, 0, 35, 254, 247, 19, 250, ++ 125, 177, 106, 70, 48, 35, 2, 33, 32, 70, 254, 247, 68, 248, 104, 70, ++ 41, 70, 255, 247, 208, 249, 32, 70, 2, 33, 106, 70, 48, 35, 253, 247, ++ 215, 255, 25, 176, 240, 189, 240, 181, 145, 176, 22, 70, 32, 35, 4, ++ 70, 15, 70, 8, 70, 8, 170, 2, 33, 254, 247, 45, 248, 4, 46, 8, 157, ++ 1, 209, 173, 15, 0, 224, 109, 15, 32, 70, 57, 70, 50, 70, 0, 35, 254, ++ 247, 233, 249, 125, 177, 106, 70, 32, 35, 2, 33, 32, 70, 254, 247, 26, ++ 248, 104, 70, 41, 70, 255, 247, 212, 249, 32, 70, 2, 33, 106, 70, 32, ++ 35, 253, 247, 173, 255, 17, 176, 240, 189, 48, 181, 0, 35, 139, 176, ++ 4, 70, 254, 247, 208, 249, 36, 35, 2, 33, 32, 70, 1, 170, 254, 247, ++ 2, 248, 1, 155, 38, 37, 93, 67, 0, 35, 1, 147, 2, 155, 0, 43, 3, 218, ++ 3, 241, 0, 67, 2, 147, 19, 53, 32, 70, 33, 33, 253, 247, 186, 255, 32, ++ 70, 33, 70, 42, 70, 0, 35, 254, 247, 242, 248, 11, 176, 48, 189, 48, ++ 181, 0, 35, 147, 176, 4, 70, 254, 247, 172, 249, 2, 33, 68, 35, 32, ++ 70, 1, 170, 253, 247, 222, 255, 1, 157, 109, 10, 9, 208, 32, 70, 23, ++ 33, 253, 247, 159, 255, 32, 70, 33, 70, 42, 70, 0, 35, 254, 247, 215, ++ 248, 19, 176, 48, 189, 45, 233, 240, 65, 4, 70, 14, 70, 8, 70, 17, 70, ++ 23, 70, 254, 247, 11, 248, 0, 35, 5, 70, 49, 70, 32, 70, 58, 70, 254, ++ 247, 179, 248, 0, 45, 12, 218, 32, 70, 1, 33, 253, 247, 129, 255, 32, ++ 70, 33, 70, 111, 240, 18, 2, 0, 35, 189, 232, 240, 65, 254, 247, 182, ++ 184, 189, 232, 240, 129, 45, 233, 240, 65, 4, 70, 14, 70, 8, 70, 17, ++ 70, 23, 70, 253, 247, 234, 255, 0, 35, 5, 70, 49, 70, 32, 70, 58, 70, ++ 254, 247, 146, 248, 0, 45, 12, 218, 32, 70, 23, 33, 253, 247, 96, 255, ++ 32, 70, 33, 70, 79, 240, 255, 50, 0, 35, 189, 232, 240, 65, 254, 247, ++ 149, 184, 189, 232, 240, 129, 240, 181, 4, 70, 141, 176, 14, 70, 8, ++ 70, 17, 70, 23, 70, 253, 247, 201, 255, 0, 35, 5, 70, 49, 70, 32, 70, ++ 58, 70, 254, 247, 113, 248, 0, 45, 15, 218, 106, 70, 48, 35, 2, 33, ++ 32, 70, 253, 247, 117, 255, 104, 70, 1, 33, 255, 247, 24, 249, 32, 70, ++ 2, 33, 106, 70, 48, 35, 253, 247, 8, 255, 13, 176, 240, 189, 240, 181, ++ 4, 70, 137, 176, 14, 70, 8, 70, 17, 70, 23, 70, 253, 247, 165, 255, ++ 0, 35, 5, 70, 49, 70, 32, 70, 58, 70, 254, 247, 77, 248, 0, 45, 15, ++ 218, 106, 70, 32, 35, 2, 33, 32, 70, 253, 247, 81, 255, 104, 70, 1, ++ 33, 255, 247, 32, 249, 32, 70, 2, 33, 106, 70, 32, 35, 253, 247, 228, ++ 254, 9, 176, 240, 189, 112, 181, 0, 35, 4, 70, 21, 70, 254, 247, 26, ++ 248, 1, 33, 32, 70, 253, 247, 3, 255, 32, 70, 41, 70, 253, 247, 124, ++ 255, 0, 40, 7, 218, 32, 70, 33, 70, 19, 34, 0, 35, 189, 232, 112, 64, ++ 254, 247, 51, 184, 112, 189, 112, 181, 0, 35, 4, 70, 21, 70, 254, 247, ++ 1, 248, 23, 33, 32, 70, 253, 247, 234, 254, 32, 70, 41, 70, 253, 247, ++ 99, 255, 0, 40, 7, 218, 32, 70, 33, 70, 1, 34, 0, 35, 189, 232, 112, ++ 64, 254, 247, 26, 184, 112, 189, 48, 181, 0, 35, 21, 70, 141, 176, 4, ++ 70, 253, 247, 231, 255, 32, 70, 41, 70, 253, 247, 77, 255, 0, 40, 15, ++ 218, 106, 70, 48, 35, 2, 33, 32, 70, 253, 247, 0, 255, 104, 70, 1, 33, ++ 255, 247, 140, 248, 32, 70, 2, 33, 106, 70, 48, 35, 253, 247, 147, 254, ++ 13, 176, 48, 189, 48, 181, 0, 35, 21, 70, 137, 176, 4, 70, 253, 247, ++ 200, 255, 32, 70, 41, 70, 253, 247, 46, 255, 0, 40, 15, 218, 106, 70, ++ 32, 35, 2, 33, 32, 70, 253, 247, 225, 254, 104, 70, 1, 33, 255, 247, ++ 155, 248, 32, 70, 2, 33, 106, 70, 32, 35, 253, 247, 116, 254, 9, 176, ++ 48, 189, 56, 181, 5, 70, 20, 70, 16, 70, 0, 34, 254, 247, 179, 248, ++ 32, 70, 41, 70, 189, 232, 56, 64, 255, 247, 72, 187, 56, 181, 5, 70, ++ 20, 70, 16, 70, 0, 34, 254, 247, 166, 248, 32, 70, 41, 70, 189, 232, ++ 56, 64, 255, 247, 30, 188, 45, 233, 240, 65, 4, 70, 21, 70, 14, 70, ++ 31, 70, 254, 247, 152, 248, 32, 70, 33, 70, 50, 70, 43, 70, 254, 247, ++ 56, 248, 32, 70, 33, 70, 58, 70, 43, 70, 253, 247, 130, 255, 32, 70, ++ 33, 70, 50, 70, 43, 70, 253, 247, 149, 255, 32, 70, 33, 70, 50, 70, ++ 43, 70, 253, 247, 143, 255, 32, 70, 33, 70, 50, 70, 43, 70, 189, 232, ++ 240, 65, 253, 247, 135, 191, 45, 233, 240, 65, 134, 176, 7, 70, 14, ++ 70, 144, 70, 28, 70, 255, 247, 193, 249, 5, 70, 0, 46, 63, 208, 184, ++ 241, 0, 15, 62, 208, 0, 44, 63, 208, 0, 40, 60, 208, 48, 70, 65, 70, ++ 34, 70, 107, 104, 253, 247, 52, 253, 6, 70, 0, 40, 51, 208, 1, 33, 0, ++ 34, 8, 35, 253, 247, 78, 253, 1, 33, 4, 70, 0, 34, 12, 35, 48, 70, 5, ++ 151, 253, 247, 70, 253, 4, 144, 32, 70, 1, 148, 253, 247, 146, 254, ++ 2, 33, 234, 106, 43, 122, 253, 247, 60, 253, 2, 144, 32, 70, 253, 247, ++ 137, 254, 2, 33, 42, 107, 43, 122, 253, 247, 51, 253, 6, 173, 3, 144, ++ 85, 248, 8, 13, 1, 33, 1, 170, 12, 35, 253, 247, 235, 253, 32, 70, 1, ++ 33, 42, 70, 8, 35, 253, 247, 229, 253, 4, 224, 52, 70, 2, 224, 68, 70, ++ 0, 224, 4, 70, 32, 70, 6, 176, 189, 232, 240, 129, 7, 181, 8, 35, 1, ++ 33, 106, 70, 253, 247, 56, 254, 1, 152, 14, 189, 45, 233, 240, 67, 6, ++ 70, 133, 176, 24, 70, 29, 70, 136, 70, 23, 70, 255, 247, 238, 255, 255, ++ 247, 97, 249, 4, 70, 40, 70, 253, 247, 83, 254, 129, 70, 40, 70, 255, ++ 247, 228, 255, 255, 247, 113, 249, 1, 33, 67, 0, 0, 34, 72, 70, 253, ++ 247, 246, 252, 0, 144, 40, 70, 253, 247, 67, 254, 129, 70, 40, 70, 255, ++ 247, 212, 255, 255, 247, 97, 249, 1, 33, 3, 70, 0, 34, 72, 70, 253, ++ 247, 230, 252, 1, 144, 40, 70, 253, 247, 51, 254, 129, 70, 40, 70, 255, ++ 247, 196, 255, 255, 247, 81, 249, 1, 33, 3, 70, 0, 34, 72, 70, 253, ++ 247, 214, 252, 2, 144, 40, 70, 253, 247, 35, 254, 129, 70, 40, 70, 255, ++ 247, 180, 255, 255, 247, 65, 249, 1, 33, 3, 70, 0, 34, 72, 70, 253, ++ 247, 198, 252, 35, 105, 3, 144, 49, 70, 1, 152, 0, 154, 152, 71, 35, ++ 105, 3, 152, 57, 70, 0, 154, 152, 71, 3, 152, 35, 105, 1, 70, 0, 154, ++ 152, 71, 1, 152, 163, 105, 1, 70, 3, 154, 152, 71, 1, 153, 99, 105, ++ 2, 152, 10, 70, 152, 71, 1, 152, 99, 105, 1, 70, 2, 154, 152, 71, 229, ++ 104, 2, 152, 57, 70, 66, 70, 0, 155, 168, 71, 2, 153, 99, 105, 56, 70, ++ 10, 70, 152, 71, 35, 105, 2, 152, 65, 70, 0, 154, 152, 71, 35, 105, ++ 3, 152, 2, 153, 0, 154, 152, 71, 2, 152, 229, 104, 1, 70, 50, 70, 0, ++ 155, 168, 71, 2, 152, 227, 105, 1, 70, 4, 34, 152, 71, 35, 105, 48, ++ 70, 1, 153, 0, 154, 152, 71, 163, 105, 48, 70, 49, 70, 2, 154, 152, ++ 71, 163, 105, 48, 70, 49, 70, 2, 154, 152, 71, 2, 152, 163, 105, 1, ++ 70, 50, 70, 152, 71, 1, 152, 229, 104, 1, 70, 2, 154, 0, 155, 168, 71, ++ 3, 152, 227, 105, 1, 70, 8, 34, 152, 71, 163, 105, 4, 172, 84, 248, ++ 4, 45, 1, 153, 64, 70, 152, 71, 32, 70, 253, 247, 177, 253, 2, 168, ++ 253, 247, 174, 253, 1, 168, 253, 247, 171, 253, 104, 70, 253, 247, 168, ++ 253, 5, 176, 189, 232, 240, 131, 45, 233, 255, 71, 13, 158, 5, 70, 48, ++ 70, 23, 70, 136, 70, 153, 70, 255, 247, 46, 255, 255, 247, 161, 248, ++ 4, 70, 48, 70, 253, 247, 147, 253, 130, 70, 48, 70, 255, 247, 36, 255, ++ 255, 247, 177, 248, 1, 33, 67, 0, 0, 34, 80, 70, 253, 247, 54, 252, ++ 0, 144, 48, 70, 253, 247, 131, 253, 130, 70, 48, 70, 255, 247, 20, 255, ++ 255, 247, 161, 248, 1, 33, 3, 70, 0, 34, 80, 70, 253, 247, 38, 252, ++ 1, 144, 48, 70, 253, 247, 115, 253, 130, 70, 48, 70, 255, 247, 4, 255, ++ 255, 247, 145, 248, 1, 33, 3, 70, 0, 34, 80, 70, 253, 247, 22, 252, ++ 2, 144, 48, 70, 253, 247, 99, 253, 130, 70, 48, 70, 255, 247, 244, 254, ++ 255, 247, 129, 248, 1, 33, 3, 70, 0, 34, 80, 70, 253, 247, 6, 252, 35, ++ 105, 0, 154, 3, 144, 57, 70, 2, 152, 152, 71, 2, 153, 1, 152, 253, 247, ++ 151, 253, 1, 152, 230, 104, 1, 70, 58, 70, 0, 155, 176, 71, 1, 152, ++ 230, 104, 1, 70, 12, 154, 0, 155, 176, 71, 1, 152, 163, 105, 1, 70, ++ 66, 70, 152, 71, 2, 152, 230, 104, 1, 70, 74, 70, 0, 155, 176, 71, 2, ++ 152, 163, 105, 1, 70, 42, 70, 152, 71, 230, 104, 56, 70, 57, 70, 2, ++ 154, 0, 155, 176, 71, 35, 105, 3, 152, 2, 153, 0, 154, 152, 71, 2, 152, ++ 230, 104, 1, 70, 3, 154, 0, 155, 176, 71, 3, 152, 42, 70, 1, 70, 0, ++ 155, 230, 104, 176, 71, 35, 105, 40, 70, 1, 153, 0, 154, 152, 71, 163, ++ 105, 40, 70, 41, 70, 3, 154, 152, 71, 163, 105, 40, 70, 41, 70, 3, 154, ++ 152, 71, 163, 105, 40, 70, 41, 70, 2, 154, 152, 71, 3, 152, 163, 105, ++ 1, 70, 42, 70, 152, 71, 3, 152, 229, 104, 1, 70, 1, 154, 0, 155, 168, ++ 71, 2, 152, 66, 70, 1, 70, 0, 155, 229, 104, 168, 71, 163, 105, 3, 153, ++ 2, 154, 64, 70, 152, 71, 3, 168, 253, 247, 239, 252, 2, 168, 253, 247, ++ 236, 252, 1, 168, 253, 247, 233, 252, 104, 70, 253, 247, 230, 252, 189, ++ 232, 255, 135, 112, 181, 14, 70, 21, 70, 255, 247, 114, 254, 254, 247, ++ 229, 255, 4, 70, 56, 185, 40, 70, 1, 33, 34, 70, 35, 70, 253, 247, 67, ++ 252, 32, 70, 112, 189, 1, 62, 6, 46, 71, 216, 223, 232, 6, 240, 4, 8, ++ 12, 22, 43, 51, 60, 0, 40, 70, 1, 33, 98, 106, 37, 224, 40, 70, 1, 33, ++ 162, 106, 33, 224, 53, 177, 1, 33, 40, 70, 4, 241, 9, 2, 11, 70, 253, ++ 247, 40, 252, 96, 122, 112, 189, 141, 177, 67, 107, 1, 33, 0, 43, 40, ++ 70, 2, 221, 0, 34, 19, 70, 1, 224, 98, 106, 35, 122, 253, 247, 25, 252, ++ 40, 70, 41, 70, 98, 107, 0, 35, 253, 247, 124, 253, 96, 107, 112, 189, ++ 162, 107, 40, 70, 1, 33, 35, 122, 253, 247, 11, 252, 1, 32, 112, 189, ++ 45, 177, 2, 33, 40, 70, 34, 29, 11, 70, 253, 247, 2, 252, 96, 104, 112, ++ 189, 53, 177, 1, 33, 40, 70, 4, 241, 8, 2, 11, 70, 253, 247, 248, 251, ++ 32, 122, 112, 189, 1, 32, 112, 189, 45, 233, 240, 67, 193, 176, 23, ++ 70, 4, 70, 136, 70, 255, 247, 17, 254, 254, 247, 132, 255, 6, 106, 32, ++ 70, 53, 104, 253, 247, 117, 252, 129, 70, 32, 70, 255, 247, 6, 254, ++ 254, 247, 147, 255, 1, 33, 3, 70, 0, 34, 72, 70, 253, 247, 24, 251, ++ 62, 144, 32, 70, 253, 247, 101, 252, 129, 70, 32, 70, 255, 247, 246, ++ 253, 254, 247, 131, 255, 1, 33, 3, 70, 0, 34, 72, 70, 253, 247, 8, 251, ++ 1, 33, 2, 70, 63, 144, 32, 70, 255, 247, 113, 255, 56, 70, 63, 153, ++ 62, 154, 253, 247, 53, 254, 2, 33, 35, 170, 36, 35, 56, 70, 253, 247, ++ 27, 252, 35, 168, 253, 247, 201, 255, 2, 33, 53, 170, 36, 35, 62, 152, ++ 253, 247, 18, 252, 53, 168, 253, 247, 192, 255, 44, 168, 35, 169, 36, ++ 34, 250, 247, 217, 251, 31, 224, 86, 248, 4, 79, 0, 44, 184, 191, 100, ++ 66, 8, 224, 104, 70, 44, 169, 254, 247, 19, 248, 104, 70, 44, 169, 254, ++ 247, 177, 251, 1, 61, 165, 66, 244, 220, 2, 45, 14, 221, 51, 104, 104, ++ 70, 0, 43, 44, 169, 180, 191, 53, 170, 35, 170, 254, 247, 235, 248, ++ 104, 70, 44, 169, 254, 247, 159, 251, 2, 45, 221, 220, 44, 168, 253, ++ 247, 205, 255, 2, 33, 44, 170, 36, 35, 64, 70, 253, 247, 123, 251, 63, ++ 168, 253, 247, 10, 252, 62, 168, 253, 247, 7, 252, 65, 176, 189, 232, ++ 240, 131, 45, 233, 255, 65, 14, 70, 21, 70, 4, 33, 0, 34, 4, 70, 255, ++ 247, 23, 255, 7, 70, 32, 70, 253, 247, 245, 251, 128, 70, 32, 70, 255, ++ 247, 134, 253, 254, 247, 19, 255, 1, 33, 3, 70, 0, 34, 64, 70, 253, ++ 247, 152, 250, 0, 144, 32, 70, 253, 247, 229, 251, 128, 70, 32, 70, ++ 255, 247, 118, 253, 254, 247, 3, 255, 1, 33, 3, 70, 0, 34, 64, 70, 253, ++ 247, 136, 250, 1, 144, 32, 70, 253, 247, 213, 251, 128, 70, 32, 70, ++ 255, 247, 102, 253, 254, 247, 243, 254, 1, 33, 3, 70, 0, 34, 64, 70, ++ 253, 247, 120, 250, 2, 144, 32, 70, 253, 247, 197, 251, 128, 70, 32, ++ 70, 255, 247, 86, 253, 254, 247, 227, 254, 1, 33, 3, 70, 0, 34, 64, ++ 70, 253, 247, 104, 250, 1, 33, 3, 144, 0, 154, 32, 70, 255, 247, 209, ++ 254, 5, 33, 1, 154, 32, 70, 255, 247, 204, 254, 49, 70, 40, 70, 253, ++ 247, 244, 251, 2, 152, 49, 70, 0, 154, 253, 247, 93, 253, 3, 152, 2, ++ 153, 50, 70, 0, 155, 253, 247, 253, 252, 2, 152, 58, 70, 1, 70, 0, 155, ++ 253, 247, 52, 253, 3, 152, 2, 154, 1, 70, 0, 155, 253, 247, 65, 252, ++ 3, 152, 0, 155, 1, 70, 50, 70, 253, 247, 59, 252, 32, 70, 41, 70, 3, ++ 154, 255, 247, 4, 255, 2, 152, 41, 70, 0, 154, 253, 247, 59, 253, 3, ++ 152, 2, 153, 253, 247, 151, 251, 184, 177, 40, 70, 41, 70, 1, 154, 0, ++ 155, 253, 247, 214, 252, 2, 152, 41, 70, 0, 154, 253, 247, 43, 253, ++ 3, 152, 2, 153, 253, 247, 135, 251, 56, 177, 0, 34, 40, 70, 1, 33, 19, ++ 70, 253, 247, 216, 250, 0, 36, 0, 224, 1, 36, 3, 168, 253, 247, 100, ++ 251, 2, 168, 253, 247, 97, 251, 1, 168, 253, 247, 94, 251, 104, 70, ++ 253, 247, 91, 251, 32, 70, 4, 176, 189, 232, 240, 129, 45, 233, 240, ++ 71, 128, 70, 134, 176, 24, 70, 28, 70, 137, 70, 23, 70, 255, 247, 224, ++ 252, 254, 247, 83, 254, 1, 37, 6, 70, 32, 70, 141, 248, 23, 80, 253, ++ 247, 66, 251, 130, 70, 32, 70, 255, 247, 211, 252, 254, 247, 96, 254, ++ 41, 70, 16, 250, 5, 243, 0, 34, 80, 70, 253, 247, 228, 249, 1, 144, ++ 32, 70, 253, 247, 49, 251, 130, 70, 32, 70, 255, 247, 194, 252, 254, ++ 247, 79, 254, 41, 70, 3, 70, 0, 34, 80, 70, 253, 247, 212, 249, 2, 144, ++ 32, 70, 253, 247, 33, 251, 130, 70, 32, 70, 255, 247, 178, 252, 254, ++ 247, 63, 254, 41, 70, 3, 70, 0, 34, 80, 70, 253, 247, 196, 249, 3, 144, ++ 32, 70, 253, 247, 17, 251, 130, 70, 32, 70, 255, 247, 162, 252, 254, ++ 247, 47, 254, 41, 70, 3, 70, 0, 34, 80, 70, 253, 247, 180, 249, 41, ++ 70, 4, 144, 2, 154, 32, 70, 255, 247, 29, 254, 56, 70, 2, 153, 3, 154, ++ 253, 247, 225, 252, 51, 105, 4, 152, 3, 153, 1, 154, 152, 71, 244, 104, ++ 64, 70, 65, 70, 4, 154, 1, 155, 160, 71, 4, 152, 244, 104, 1, 70, 3, ++ 154, 1, 155, 160, 71, 72, 70, 73, 70, 4, 154, 1, 155, 244, 104, 160, ++ 71, 41, 70, 13, 241, 23, 2, 43, 70, 56, 70, 253, 247, 76, 250, 4, 168, ++ 253, 247, 219, 250, 3, 168, 253, 247, 216, 250, 2, 168, 253, 247, 213, ++ 250, 1, 168, 253, 247, 210, 250, 6, 176, 189, 232, 240, 135, 45, 233, ++ 255, 71, 14, 156, 128, 70, 32, 70, 30, 70, 15, 70, 12, 157, 145, 70, ++ 253, 247, 194, 250, 130, 70, 32, 70, 255, 247, 83, 252, 254, 247, 224, ++ 253, 1, 33, 3, 70, 0, 34, 80, 70, 253, 247, 101, 249, 2, 144, 32, 70, ++ 253, 247, 178, 250, 130, 70, 32, 70, 255, 247, 67, 252, 254, 247, 208, ++ 253, 1, 33, 3, 70, 0, 34, 80, 70, 253, 247, 85, 249, 0, 35, 1, 70, 1, ++ 34, 3, 144, 253, 247, 121, 251, 1, 33, 2, 154, 32, 70, 255, 247, 185, ++ 253, 58, 70, 0, 35, 72, 70, 2, 153, 253, 247, 92, 251, 65, 70, 48, 70, ++ 253, 247, 219, 250, 57, 70, 40, 70, 253, 247, 215, 250, 48, 70, 41, ++ 70, 3, 154, 35, 70, 255, 247, 36, 252, 48, 70, 41, 70, 3, 154, 67, 70, ++ 0, 151, 1, 148, 255, 247, 220, 252, 48, 70, 41, 70, 3, 154, 35, 70, ++ 255, 247, 36, 255, 13, 152, 2, 153, 42, 70, 0, 35, 253, 247, 58, 251, ++ 3, 168, 253, 247, 114, 250, 2, 168, 253, 247, 111, 250, 189, 232, 255, ++ 135, 45, 233, 255, 71, 7, 70, 145, 70, 12, 70, 255, 247, 249, 251, 254, ++ 247, 108, 253, 208, 248, 32, 128, 6, 70, 56, 70, 216, 248, 0, 80, 253, ++ 247, 90, 250, 130, 70, 56, 70, 255, 247, 235, 251, 254, 247, 120, 253, ++ 1, 33, 67, 0, 0, 34, 80, 70, 253, 247, 253, 248, 1, 144, 56, 70, 253, ++ 247, 74, 250, 130, 70, 56, 70, 255, 247, 219, 251, 254, 247, 104, 253, ++ 1, 33, 3, 70, 0, 34, 80, 70, 253, 247, 237, 248, 2, 144, 56, 70, 253, ++ 247, 58, 250, 130, 70, 56, 70, 255, 247, 203, 251, 254, 247, 88, 253, ++ 1, 33, 3, 70, 0, 34, 80, 70, 253, 247, 221, 248, 1, 33, 2, 70, 3, 144, ++ 56, 70, 255, 247, 70, 253, 72, 70, 3, 153, 2, 154, 253, 247, 10, 252, ++ 32, 70, 73, 70, 253, 247, 105, 250, 26, 224, 88, 248, 4, 127, 0, 47, ++ 184, 191, 127, 66, 5, 224, 51, 105, 32, 70, 33, 70, 1, 154, 152, 71, ++ 1, 61, 189, 66, 247, 220, 2, 45, 12, 221, 216, 248, 0, 48, 32, 70, 0, ++ 43, 33, 70, 247, 104, 180, 191, 2, 154, 74, 70, 1, 155, 184, 71, 2, ++ 45, 226, 220, 3, 168, 253, 247, 0, 250, 2, 168, 253, 247, 253, 249, ++ 1, 168, 253, 247, 250, 249, 189, 232, 255, 135, 45, 233, 240, 71, 134, ++ 176, 14, 156, 6, 70, 32, 70, 136, 70, 23, 70, 153, 70, 255, 247, 128, ++ 251, 254, 247, 243, 252, 5, 70, 32, 70, 253, 247, 229, 249, 130, 70, ++ 32, 70, 255, 247, 118, 251, 254, 247, 3, 253, 1, 33, 67, 0, 0, 34, 80, ++ 70, 253, 247, 136, 248, 1, 144, 32, 70, 253, 247, 213, 249, 130, 70, ++ 32, 70, 255, 247, 102, 251, 254, 247, 243, 252, 1, 33, 3, 70, 0, 34, ++ 80, 70, 253, 247, 120, 248, 2, 144, 32, 70, 253, 247, 197, 249, 130, ++ 70, 32, 70, 255, 247, 86, 251, 254, 247, 227, 252, 1, 33, 3, 70, 0, ++ 34, 80, 70, 253, 247, 104, 248, 3, 144, 32, 70, 253, 247, 181, 249, ++ 130, 70, 32, 70, 255, 247, 70, 251, 254, 247, 211, 252, 1, 33, 3, 70, ++ 0, 34, 80, 70, 253, 247, 88, 248, 4, 144, 32, 70, 253, 247, 165, 249, ++ 130, 70, 32, 70, 255, 247, 54, 251, 254, 247, 195, 252, 0, 34, 3, 70, ++ 1, 33, 80, 70, 253, 247, 72, 248, 1, 33, 5, 144, 2, 154, 32, 70, 255, ++ 247, 177, 252, 171, 105, 3, 152, 73, 70, 66, 70, 152, 71, 171, 105, ++ 4, 152, 57, 70, 50, 70, 152, 71, 4, 152, 2, 153, 2, 70, 253, 247, 107, ++ 251, 3, 152, 4, 154, 1, 70, 1, 155, 236, 104, 160, 71, 43, 105, 4, 152, ++ 3, 153, 1, 154, 152, 71, 43, 104, 4, 43, 6, 209, 106, 107, 4, 152, 82, ++ 66, 1, 70, 0, 35, 253, 247, 72, 250, 4, 152, 171, 105, 1, 70, 58, 70, ++ 152, 71, 4, 152, 171, 105, 1, 70, 50, 70, 152, 71, 171, 105, 4, 154, ++ 5, 152, 49, 70, 152, 71, 4, 153, 48, 70, 253, 247, 166, 249, 5, 152, ++ 236, 104, 1, 70, 3, 154, 1, 155, 160, 71, 6, 172, 84, 248, 4, 29, 171, ++ 105, 66, 70, 64, 70, 152, 71, 32, 70, 253, 247, 78, 249, 4, 168, 253, ++ 247, 75, 249, 3, 168, 253, 247, 72, 249, 2, 168, 253, 247, 69, 249, ++ 1, 168, 253, 247, 66, 249, 6, 176, 189, 232, 240, 135, 127, 181, 4, ++ 70, 253, 247, 57, 249, 1, 33, 0, 34, 12, 35, 252, 247, 227, 255, 5, ++ 70, 32, 70, 1, 148, 253, 247, 47, 249, 6, 70, 32, 70, 255, 247, 192, ++ 250, 254, 247, 77, 252, 1, 33, 3, 70, 0, 34, 48, 70, 252, 247, 210, ++ 255, 2, 144, 32, 70, 253, 247, 31, 249, 6, 70, 32, 70, 255, 247, 176, ++ 250, 254, 247, 61, 252, 1, 33, 3, 70, 0, 34, 48, 70, 252, 247, 194, ++ 255, 1, 33, 3, 144, 1, 170, 40, 70, 12, 35, 253, 247, 124, 248, 40, ++ 70, 4, 176, 112, 189, 31, 181, 4, 70, 120, 177, 0, 104, 104, 177, 1, ++ 33, 1, 170, 12, 35, 253, 247, 210, 248, 3, 168, 253, 247, 254, 248, ++ 2, 168, 253, 247, 251, 248, 32, 70, 253, 247, 248, 248, 31, 189, 48, ++ 181, 4, 70, 135, 176, 208, 177, 5, 104, 197, 177, 40, 70, 253, 247, ++ 236, 248, 1, 33, 5, 144, 3, 170, 8, 35, 40, 70, 253, 247, 184, 248, ++ 1, 33, 106, 70, 12, 35, 3, 152, 253, 247, 178, 248, 3, 168, 255, 247, ++ 211, 255, 32, 70, 253, 247, 219, 248, 5, 168, 252, 247, 120, 255, 7, ++ 176, 48, 189, 31, 181, 1, 33, 1, 170, 12, 35, 253, 247, 161, 248, 1, ++ 152, 5, 176, 0, 189, 48, 181, 133, 176, 13, 70, 20, 70, 1, 33, 1, 170, ++ 12, 35, 253, 247, 149, 248, 13, 177, 2, 155, 43, 96, 12, 177, 3, 155, ++ 35, 96, 5, 176, 48, 189, 127, 181, 12, 35, 14, 70, 21, 70, 1, 33, 1, ++ 170, 4, 70, 253, 247, 132, 248, 49, 70, 2, 152, 253, 247, 247, 248, ++ 41, 70, 3, 152, 253, 247, 243, 248, 32, 70, 1, 33, 1, 170, 12, 35, 253, ++ 247, 19, 248, 1, 32, 4, 176, 112, 189, 45, 233, 240, 67, 159, 176, 12, ++ 70, 145, 70, 6, 70, 255, 247, 196, 255, 5, 70, 253, 247, 149, 248, 7, ++ 70, 40, 70, 255, 247, 38, 250, 254, 247, 179, 251, 1, 33, 3, 70, 0, ++ 34, 56, 70, 252, 247, 56, 255, 26, 144, 40, 70, 253, 247, 133, 248, ++ 7, 70, 40, 70, 255, 247, 22, 250, 254, 247, 163, 251, 1, 33, 3, 70, ++ 0, 34, 56, 70, 252, 247, 40, 255, 27, 144, 40, 70, 253, 247, 117, 248, ++ 7, 70, 40, 70, 255, 247, 6, 250, 254, 247, 147, 251, 1, 33, 3, 70, 0, ++ 34, 56, 70, 252, 247, 24, 255, 28, 144, 40, 70, 253, 247, 101, 248, ++ 7, 70, 40, 70, 255, 247, 246, 249, 254, 247, 131, 251, 1, 33, 3, 70, ++ 0, 34, 56, 70, 252, 247, 8, 255, 21, 169, 29, 144, 22, 170, 48, 70, ++ 255, 247, 136, 255, 28, 155, 22, 153, 0, 147, 29, 155, 26, 154, 1, 147, ++ 21, 152, 27, 155, 2, 149, 255, 247, 123, 253, 40, 70, 253, 247, 69, ++ 248, 6, 70, 40, 70, 255, 247, 214, 249, 254, 247, 99, 251, 1, 33, 3, ++ 70, 0, 34, 48, 70, 252, 247, 232, 254, 23, 144, 40, 70, 253, 247, 53, ++ 248, 6, 70, 40, 70, 255, 247, 198, 249, 254, 247, 83, 251, 1, 33, 3, ++ 70, 0, 34, 48, 70, 252, 247, 216, 254, 24, 144, 40, 70, 253, 247, 37, ++ 248, 6, 70, 40, 70, 255, 247, 182, 249, 254, 247, 67, 251, 1, 33, 3, ++ 70, 0, 34, 48, 70, 252, 247, 200, 254, 1, 34, 1, 70, 0, 35, 25, 144, ++ 253, 247, 236, 248, 40, 70, 255, 247, 165, 249, 40, 70, 255, 247, 162, ++ 249, 254, 247, 47, 251, 40, 70, 255, 247, 157, 249, 254, 247, 42, 251, ++ 2, 33, 3, 29, 4, 170, 32, 70, 252, 247, 211, 255, 40, 70, 255, 247, ++ 146, 249, 254, 247, 31, 251, 0, 241, 4, 8, 79, 234, 168, 8, 65, 70, ++ 4, 168, 254, 247, 29, 251, 8, 241, 255, 56, 0, 38, 12, 36, 87, 224, ++ 31, 44, 2, 209, 1, 54, 0, 36, 0, 224, 1, 52, 117, 74, 30, 168, 0, 235, ++ 134, 3, 82, 248, 36, 16, 83, 248, 104, 60, 25, 66, 71, 208, 31, 44, ++ 2, 209, 1, 54, 0, 35, 0, 224, 99, 28, 30, 168, 0, 235, 134, 1, 82, 248, ++ 35, 64, 81, 248, 104, 28, 12, 64, 29, 208, 31, 43, 2, 209, 1, 54, 0, ++ 36, 0, 224, 92, 28, 30, 169, 1, 235, 134, 3, 82, 248, 36, 32, 83, 248, ++ 104, 60, 23, 152, 26, 66, 5, 208, 21, 153, 253, 247, 6, 248, 24, 152, ++ 26, 153, 4, 224, 27, 153, 253, 247, 0, 248, 24, 152, 28, 153, 252, 247, ++ 252, 255, 125, 224, 31, 43, 1, 209, 1, 54, 0, 224, 92, 28, 30, 168, ++ 0, 235, 134, 3, 82, 248, 36, 32, 83, 248, 104, 60, 23, 152, 26, 66, ++ 5, 208, 27, 153, 252, 247, 233, 255, 24, 152, 29, 153, 231, 231, 21, ++ 153, 252, 247, 227, 255, 24, 152, 22, 153, 225, 231, 70, 69, 165, 211, ++ 30, 44, 168, 217, 93, 224, 23, 168, 7, 200, 43, 70, 255, 247, 41, 249, ++ 31, 44, 2, 209, 1, 54, 0, 36, 0, 224, 1, 52, 68, 79, 30, 169, 1, 235, ++ 134, 3, 87, 248, 36, 32, 83, 248, 104, 60, 26, 66, 72, 208, 23, 168, ++ 7, 200, 43, 70, 255, 247, 20, 249, 23, 168, 7, 200, 43, 70, 255, 247, ++ 15, 249, 31, 44, 2, 209, 1, 54, 0, 35, 0, 224, 99, 28, 30, 168, 0, 235, ++ 134, 2, 87, 248, 35, 64, 82, 248, 104, 44, 20, 64, 18, 208, 31, 43, ++ 2, 209, 1, 54, 0, 36, 0, 224, 92, 28, 30, 169, 1, 235, 134, 3, 87, 248, ++ 36, 32, 83, 248, 104, 60, 26, 66, 1, 208, 26, 155, 23, 224, 28, 155, ++ 14, 224, 31, 43, 1, 209, 1, 54, 0, 224, 92, 28, 30, 170, 2, 235, 134, ++ 3, 83, 248, 104, 60, 87, 248, 36, 32, 26, 66, 6, 208, 29, 155, 141, ++ 232, 40, 0, 23, 168, 7, 200, 27, 155, 5, 224, 22, 155, 141, 232, 40, ++ 0, 21, 155, 23, 168, 7, 200, 255, 247, 144, 249, 70, 69, 159, 211, 30, ++ 44, 157, 217, 23, 153, 27, 152, 252, 247, 117, 255, 30, 172, 24, 153, ++ 28, 152, 252, 247, 112, 255, 84, 248, 20, 29, 26, 152, 252, 247, 107, ++ 255, 32, 70, 252, 247, 32, 255, 24, 168, 252, 247, 29, 255, 23, 168, ++ 252, 247, 26, 255, 29, 168, 252, 247, 23, 255, 30, 172, 43, 70, 27, ++ 152, 28, 153, 26, 154, 255, 247, 185, 251, 84, 248, 8, 45, 27, 153, ++ 72, 70, 255, 247, 78, 254, 32, 70, 252, 247, 7, 255, 27, 168, 252, 247, ++ 4, 255, 26, 168, 252, 247, 1, 255, 31, 176, 189, 232, 240, 131, 248, ++ 26, 4, 0, 45, 233, 240, 65, 134, 176, 4, 70, 23, 70, 13, 70, 255, 247, ++ 135, 248, 6, 70, 32, 70, 252, 247, 238, 254, 128, 70, 32, 70, 255, 247, ++ 127, 248, 254, 247, 12, 250, 1, 33, 3, 70, 0, 34, 64, 70, 252, 247, ++ 145, 253, 1, 144, 32, 70, 252, 247, 222, 254, 128, 70, 32, 70, 255, ++ 247, 111, 248, 254, 247, 252, 249, 1, 33, 3, 70, 0, 34, 64, 70, 252, ++ 247, 129, 253, 2, 144, 32, 70, 252, 247, 206, 254, 128, 70, 32, 70, ++ 255, 247, 95, 248, 254, 247, 236, 249, 1, 33, 3, 70, 0, 34, 64, 70, ++ 252, 247, 113, 253, 3, 144, 32, 70, 252, 247, 190, 254, 128, 70, 32, ++ 70, 255, 247, 79, 248, 254, 247, 220, 249, 1, 33, 3, 70, 0, 34, 64, ++ 70, 252, 247, 97, 253, 4, 144, 32, 70, 252, 247, 174, 254, 128, 70, ++ 32, 70, 255, 247, 63, 248, 254, 247, 204, 249, 1, 33, 3, 70, 0, 34, ++ 64, 70, 252, 247, 81, 253, 5, 33, 5, 144, 1, 154, 32, 70, 255, 247, ++ 186, 249, 1, 33, 2, 154, 32, 70, 255, 247, 181, 249, 5, 152, 57, 70, ++ 2, 154, 253, 247, 74, 248, 4, 46, 36, 209, 32, 70, 49, 70, 0, 34, 255, ++ 247, 169, 249, 2, 154, 4, 70, 41, 70, 4, 152, 253, 247, 61, 248, 4, ++ 153, 3, 152, 252, 247, 203, 254, 4, 152, 34, 70, 1, 70, 2, 155, 253, ++ 247, 22, 248, 4, 152, 42, 70, 1, 70, 2, 155, 252, 247, 35, 255, 3, 152, ++ 42, 70, 1, 70, 2, 155, 252, 247, 205, 255, 4, 152, 3, 154, 1, 70, 20, ++ 224, 4, 152, 41, 70, 2, 154, 253, 247, 30, 248, 4, 152, 111, 240, 2, ++ 2, 1, 70, 0, 35, 252, 247, 56, 255, 4, 152, 42, 70, 1, 70, 2, 155, 252, ++ 247, 183, 255, 4, 152, 1, 154, 1, 70, 2, 155, 6, 172, 252, 247, 0, 255, ++ 84, 248, 4, 29, 4, 152, 252, 247, 101, 254, 5, 70, 32, 70, 252, 247, ++ 75, 254, 4, 168, 252, 247, 72, 254, 3, 168, 252, 247, 69, 254, 2, 168, ++ 252, 247, 66, 254, 1, 168, 252, 247, 63, 254, 213, 241, 1, 0, 56, 191, ++ 0, 32, 6, 176, 189, 232, 240, 129, 19, 181, 4, 70, 1, 170, 8, 70, 105, ++ 70, 255, 247, 100, 253, 157, 232, 6, 0, 32, 70, 255, 247, 48, 255, 28, ++ 189, 240, 181, 133, 176, 13, 70, 6, 70, 255, 247, 79, 253, 4, 70, 252, ++ 247, 32, 254, 7, 70, 32, 70, 254, 247, 177, 255, 254, 247, 62, 249, ++ 1, 33, 3, 70, 0, 34, 56, 70, 252, 247, 195, 252, 2, 144, 32, 70, 252, ++ 247, 16, 254, 7, 70, 32, 70, 254, 247, 161, 255, 254, 247, 46, 249, ++ 1, 33, 3, 70, 0, 34, 56, 70, 252, 247, 179, 252, 105, 70, 3, 144, 1, ++ 170, 48, 70, 255, 247, 51, 253, 1, 33, 2, 154, 32, 70, 255, 247, 23, ++ 249, 4, 172, 0, 35, 3, 152, 2, 153, 1, 154, 252, 247, 185, 254, 84, ++ 248, 4, 45, 0, 153, 40, 70, 255, 247, 50, 253, 32, 70, 252, 247, 235, ++ 253, 2, 168, 252, 247, 232, 253, 5, 176, 240, 189, 45, 233, 240, 65, ++ 134, 176, 14, 70, 21, 70, 7, 70, 255, 247, 8, 253, 4, 70, 252, 247, ++ 217, 253, 128, 70, 32, 70, 254, 247, 106, 255, 254, 247, 247, 248, 1, ++ 33, 3, 70, 0, 34, 64, 70, 252, 247, 124, 252, 4, 144, 32, 70, 252, 247, ++ 201, 253, 128, 70, 32, 70, 254, 247, 90, 255, 254, 247, 231, 248, 1, ++ 33, 3, 70, 0, 34, 64, 70, 252, 247, 108, 252, 3, 170, 5, 144, 2, 169, ++ 56, 70, 255, 247, 236, 252, 2, 153, 4, 152, 252, 247, 253, 253, 3, 153, ++ 5, 152, 252, 247, 249, 253, 48, 70, 2, 169, 3, 170, 255, 247, 223, 252, ++ 3, 155, 0, 148, 4, 152, 5, 153, 2, 154, 6, 172, 255, 247, 172, 251, ++ 84, 248, 4, 45, 4, 153, 40, 70, 255, 247, 226, 252, 32, 70, 252, 247, ++ 155, 253, 4, 168, 252, 247, 152, 253, 6, 176, 189, 232, 240, 129, 45, ++ 233, 240, 65, 136, 176, 4, 70, 13, 70, 31, 70, 22, 70, 252, 247, 138, ++ 253, 128, 70, 32, 70, 254, 247, 27, 255, 254, 247, 168, 248, 1, 33, ++ 3, 70, 0, 34, 64, 70, 252, 247, 45, 252, 3, 144, 32, 70, 252, 247, 122, ++ 253, 128, 70, 32, 70, 254, 247, 11, 255, 254, 247, 152, 248, 1, 33, ++ 3, 70, 0, 34, 64, 70, 252, 247, 29, 252, 4, 144, 32, 70, 252, 247, 106, ++ 253, 128, 70, 32, 70, 254, 247, 251, 254, 254, 247, 136, 248, 1, 33, ++ 3, 70, 0, 34, 64, 70, 252, 247, 13, 252, 5, 144, 32, 70, 252, 247, 90, ++ 253, 128, 70, 32, 70, 254, 247, 235, 254, 254, 247, 120, 248, 1, 33, ++ 3, 70, 0, 34, 64, 70, 252, 247, 253, 251, 6, 144, 32, 70, 252, 247, ++ 74, 253, 128, 70, 32, 70, 254, 247, 219, 254, 254, 247, 104, 248, 1, ++ 33, 3, 70, 0, 34, 64, 70, 252, 247, 237, 251, 1, 33, 7, 144, 3, 154, ++ 32, 70, 255, 247, 86, 248, 5, 33, 4, 154, 32, 70, 255, 247, 81, 248, ++ 6, 152, 41, 70, 3, 154, 4, 155, 254, 247, 69, 254, 15, 155, 56, 70, ++ 0, 147, 16, 155, 14, 153, 1, 147, 6, 154, 3, 155, 253, 247, 61, 248, ++ 88, 177, 32, 70, 5, 153, 6, 154, 255, 247, 178, 250, 48, 70, 41, 70, ++ 5, 154, 255, 247, 94, 252, 0, 36, 1, 224, 79, 240, 255, 52, 7, 168, ++ 252, 247, 19, 253, 6, 168, 252, 247, 16, 253, 5, 168, 252, 247, 13, ++ 253, 4, 168, 252, 247, 10, 253, 3, 168, 252, 247, 7, 253, 32, 70, 8, ++ 176, 189, 232, 240, 129, 11, 106, 48, 181, 20, 106, 227, 24, 179, 241, ++ 0, 95, 3, 98, 4, 211, 35, 240, 96, 67, 3, 98, 1, 36, 0, 224, 0, 36, ++ 213, 105, 203, 105, 235, 24, 27, 25, 179, 241, 128, 95, 195, 97, 4, ++ 211, 35, 240, 112, 67, 195, 97, 1, 36, 0, 224, 0, 36, 149, 105, 139, ++ 105, 235, 24, 27, 25, 179, 241, 128, 95, 131, 97, 4, 211, 35, 240, 112, ++ 67, 131, 97, 1, 36, 0, 224, 0, 36, 85, 105, 75, 105, 235, 24, 27, 25, ++ 179, 241, 0, 95, 67, 97, 4, 211, 35, 240, 96, 67, 67, 97, 1, 36, 0, ++ 224, 0, 36, 21, 105, 11, 105, 235, 24, 27, 25, 179, 241, 128, 95, 3, ++ 97, 4, 211, 35, 240, 112, 67, 3, 97, 1, 36, 0, 224, 0, 36, 213, 104, ++ 203, 104, 235, 24, 27, 25, 179, 241, 128, 95, 195, 96, 4, 211, 35, 240, ++ 112, 67, 195, 96, 1, 36, 0, 224, 0, 36, 149, 104, 139, 104, 235, 24, ++ 27, 25, 179, 241, 0, 95, 131, 96, 4, 211, 35, 240, 96, 67, 131, 96, ++ 1, 36, 0, 224, 0, 36, 85, 104, 75, 104, 235, 24, 27, 25, 179, 241, 128, ++ 95, 67, 96, 4, 211, 35, 240, 112, 67, 67, 96, 1, 36, 0, 224, 0, 36, ++ 18, 104, 11, 104, 211, 24, 27, 25, 179, 241, 128, 95, 3, 96, 14, 211, ++ 35, 240, 112, 67, 3, 96, 3, 106, 19, 51, 179, 241, 0, 95, 3, 98, 5, ++ 211, 35, 240, 96, 67, 3, 98, 195, 105, 1, 51, 195, 97, 48, 189, 19, ++ 106, 48, 181, 12, 106, 227, 26, 179, 241, 0, 95, 3, 98, 4, 211, 35, ++ 240, 96, 67, 3, 98, 1, 36, 0, 224, 0, 36, 205, 105, 211, 105, 235, 26, ++ 27, 27, 179, 241, 128, 95, 195, 97, 4, 211, 35, 240, 112, 67, 195, 97, ++ 1, 36, 0, 224, 0, 36, 141, 105, 147, 105, 235, 26, 27, 27, 179, 241, ++ 128, 95, 131, 97, 4, 211, 35, 240, 112, 67, 131, 97, 1, 36, 0, 224, ++ 0, 36, 77, 105, 83, 105, 235, 26, 27, 27, 179, 241, 0, 95, 67, 97, 4, ++ 211, 35, 240, 96, 67, 67, 97, 1, 36, 0, 224, 0, 36, 13, 105, 19, 105, ++ 235, 26, 27, 27, 179, 241, 128, 95, 3, 97, 4, 211, 35, 240, 112, 67, ++ 3, 97, 1, 36, 0, 224, 0, 36, 205, 104, 211, 104, 235, 26, 27, 27, 179, ++ 241, 128, 95, 195, 96, 4, 211, 35, 240, 112, 67, 195, 96, 1, 36, 0, ++ 224, 0, 36, 141, 104, 147, 104, 235, 26, 27, 27, 179, 241, 0, 95, 131, ++ 96, 4, 211, 35, 240, 96, 67, 131, 96, 1, 36, 0, 224, 0, 36, 77, 104, ++ 83, 104, 235, 26, 27, 27, 179, 241, 128, 95, 67, 96, 4, 211, 35, 240, ++ 112, 67, 67, 96, 1, 36, 0, 224, 0, 36, 9, 104, 19, 104, 203, 26, 27, ++ 27, 179, 241, 128, 95, 3, 96, 14, 211, 35, 240, 112, 67, 3, 96, 3, 106, ++ 19, 59, 179, 241, 0, 95, 3, 98, 5, 211, 35, 240, 96, 67, 3, 98, 195, ++ 105, 1, 59, 195, 97, 48, 189, 0, 0, 48, 181, 12, 70, 191, 176, 5, 70, ++ 34, 70, 35, 168, 41, 70, 255, 247, 230, 254, 104, 70, 35, 169, 252, ++ 247, 202, 255, 104, 70, 35, 169, 253, 247, 104, 251, 34, 70, 44, 168, ++ 41, 70, 255, 247, 97, 255, 104, 70, 44, 169, 252, 247, 189, 255, 104, ++ 70, 44, 169, 253, 247, 91, 251, 44, 170, 104, 70, 35, 169, 253, 247, ++ 158, 248, 104, 70, 41, 70, 253, 247, 82, 251, 44, 168, 35, 169, 2, 70, ++ 255, 247, 75, 255, 53, 168, 44, 169, 9, 74, 253, 247, 67, 255, 32, 70, ++ 53, 169, 35, 170, 255, 247, 185, 254, 104, 70, 33, 70, 44, 170, 253, ++ 247, 134, 248, 104, 70, 33, 70, 253, 247, 58, 251, 63, 176, 48, 189, ++ 0, 191, 65, 219, 1, 0, 240, 181, 6, 70, 191, 176, 12, 70, 31, 70, 21, ++ 70, 35, 168, 49, 70, 34, 70, 255, 247, 160, 254, 44, 168, 41, 70, 58, ++ 70, 255, 247, 35, 255, 44, 170, 104, 70, 35, 169, 253, 247, 104, 248, ++ 104, 70, 35, 169, 253, 247, 28, 251, 44, 168, 49, 70, 34, 70, 255, 247, ++ 21, 255, 53, 168, 41, 70, 58, 70, 255, 247, 136, 254, 53, 170, 104, ++ 70, 44, 169, 253, 247, 85, 248, 104, 70, 44, 169, 253, 247, 9, 251, ++ 35, 170, 53, 168, 44, 169, 255, 247, 122, 254, 104, 70, 53, 169, 252, ++ 247, 94, 255, 104, 70, 49, 70, 253, 247, 252, 250, 35, 170, 53, 168, ++ 44, 169, 255, 247, 245, 254, 104, 70, 53, 169, 252, 247, 81, 255, 104, ++ 70, 33, 70, 253, 247, 239, 250, 157, 248, 20, 49, 43, 177, 32, 70, 33, ++ 70, 9, 34, 253, 247, 226, 254, 8, 224, 104, 70, 33, 70, 68, 154, 253, ++ 247, 41, 248, 104, 70, 33, 70, 253, 247, 221, 250, 40, 70, 57, 70, 255, ++ 247, 96, 255, 63, 176, 240, 189, 45, 233, 240, 71, 198, 176, 13, 70, ++ 4, 70, 146, 70, 255, 247, 114, 250, 0, 33, 6, 70, 36, 34, 30, 168, 250, ++ 243, 98, 246, 1, 39, 0, 33, 36, 34, 39, 168, 38, 151, 250, 243, 91, ++ 246, 0, 33, 36, 34, 48, 168, 47, 151, 250, 243, 85, 246, 9, 35, 48, ++ 70, 56, 147, 252, 247, 46, 251, 128, 70, 48, 70, 254, 247, 191, 252, ++ 253, 247, 76, 254, 0, 34, 3, 70, 57, 70, 64, 70, 252, 247, 209, 249, ++ 67, 144, 48, 70, 252, 247, 30, 251, 128, 70, 48, 70, 254, 247, 175, ++ 252, 253, 247, 60, 254, 0, 34, 3, 70, 57, 70, 64, 70, 252, 247, 193, ++ 249, 68, 144, 48, 70, 252, 247, 14, 251, 128, 70, 48, 70, 254, 247, ++ 159, 252, 253, 247, 44, 254, 0, 34, 3, 70, 57, 70, 64, 70, 252, 247, ++ 177, 249, 2, 33, 32, 35, 69, 144, 57, 170, 40, 70, 252, 247, 206, 250, ++ 57, 155, 32, 70, 65, 169, 66, 170, 3, 240, 128, 73, 255, 247, 40, 250, ++ 2, 33, 21, 170, 65, 152, 36, 35, 252, 247, 192, 250, 21, 168, 48, 169, ++ 36, 34, 249, 247, 119, 250, 24, 177, 21, 168, 252, 247, 104, 254, 0, ++ 39, 21, 169, 36, 34, 3, 168, 249, 247, 128, 250, 12, 168, 21, 169, 36, ++ 34, 249, 247, 123, 250, 0, 37, 44, 70, 62, 75, 70, 169, 1, 235, 133, ++ 2, 82, 248, 52, 44, 83, 248, 36, 16, 152, 70, 10, 64, 4, 208, 12, 168, ++ 39, 169, 255, 247, 216, 254, 31, 224, 31, 44, 2, 209, 1, 53, 20, 70, ++ 0, 224, 1, 52, 7, 45, 231, 217, 30, 224, 70, 170, 2, 235, 133, 3, 83, ++ 248, 52, 60, 88, 248, 36, 32, 26, 66, 21, 171, 141, 232, 136, 0, 4, ++ 208, 3, 168, 30, 169, 12, 170, 39, 171, 3, 224, 12, 168, 39, 169, 3, ++ 170, 30, 171, 255, 247, 251, 254, 31, 44, 2, 209, 1, 53, 0, 36, 0, 224, ++ 1, 52, 7, 45, 224, 217, 30, 168, 252, 247, 88, 254, 2, 33, 30, 170, ++ 36, 35, 69, 152, 252, 247, 6, 250, 3, 168, 252, 247, 79, 254, 36, 35, ++ 2, 33, 3, 170, 68, 152, 252, 247, 253, 249, 1, 33, 67, 154, 48, 70, ++ 254, 247, 166, 253, 69, 152, 67, 153, 2, 70, 252, 247, 106, 252, 68, ++ 152, 69, 154, 1, 70, 67, 155, 252, 247, 219, 251, 185, 241, 0, 15, 5, ++ 209, 48, 70, 68, 153, 69, 154, 254, 247, 115, 254, 5, 224, 0, 34, 69, ++ 152, 1, 33, 19, 70, 252, 247, 222, 249, 70, 172, 84, 248, 4, 45, 68, ++ 153, 80, 70, 255, 247, 173, 249, 32, 70, 252, 247, 102, 250, 68, 168, ++ 252, 247, 99, 250, 67, 168, 252, 247, 96, 250, 70, 176, 189, 232, 240, ++ 135, 0, 191, 248, 26, 4, 0, 112, 181, 14, 70, 21, 70, 4, 70, 255, 247, ++ 126, 249, 254, 247, 229, 251, 4, 40, 49, 70, 32, 70, 42, 70, 3, 209, ++ 189, 232, 112, 64, 255, 247, 249, 190, 189, 232, 112, 64, 255, 247, ++ 163, 185, 0, 0, 45, 233, 240, 65, 31, 70, 0, 235, 1, 8, 0, 241, 14, ++ 3, 152, 69, 4, 70, 13, 70, 22, 70, 3, 217, 144, 249, 14, 48, 0, 43, ++ 69, 218, 23, 45, 63, 217, 33, 124, 99, 124, 4, 241, 18, 2, 67, 234, ++ 1, 35, 211, 24, 152, 69, 54, 211, 227, 123, 162, 123, 67, 234, 2, 34, ++ 72, 242, 1, 3, 154, 66, 50, 209, 28, 72, 4, 241, 19, 1, 3, 34, 249, ++ 247, 168, 249, 88, 187, 162, 125, 227, 125, 67, 234, 2, 35, 1, 43, 37, ++ 209, 71, 45, 31, 217, 148, 248, 45, 48, 148, 248, 44, 32, 27, 4, 67, ++ 234, 2, 99, 148, 248, 47, 32, 19, 67, 148, 248, 46, 32, 67, 234, 2, ++ 35, 72, 51, 155, 178, 227, 24, 152, 69, 12, 211, 14, 177, 1, 46, 13, ++ 209, 56, 70, 127, 177, 4, 241, 24, 1, 48, 34, 249, 247, 149, 249, 0, ++ 32, 189, 232, 240, 129, 111, 240, 23, 0, 189, 232, 240, 129, 111, 240, ++ 29, 0, 189, 232, 240, 129, 189, 232, 240, 129, 228, 20, 4, 0, 0, 72, ++ 112, 71, 80, 110, 4, 0, 0, 72, 112, 71, 136, 98, 4, 0, 1, 75, 67, 248, ++ 32, 16, 112, 71, 192, 110, 4, 0, 3, 75, 83, 248, 32, 0, 67, 26, 88, ++ 66, 64, 235, 3, 0, 112, 71, 192, 110, 4, 0, 1, 35, 112, 181, 4, 70, ++ 3, 116, 5, 70, 0, 38, 4, 224, 235, 106, 32, 70, 41, 107, 152, 71, 1, ++ 54, 227, 124, 8, 53, 158, 66, 246, 219, 0, 32, 32, 116, 112, 189, 112, ++ 181, 133, 105, 4, 70, 29, 177, 43, 104, 105, 104, 152, 71, 25, 224, ++ 134, 124, 1, 62, 15, 224, 35, 137, 99, 177, 99, 124, 19, 185, 50, 70, ++ 1, 62, 0, 224, 42, 70, 12, 50, 4, 235, 194, 2, 83, 104, 32, 70, 145, ++ 104, 152, 71, 1, 53, 163, 124, 157, 66, 236, 219, 99, 124, 131, 240, ++ 1, 3, 99, 116, 0, 32, 112, 189, 16, 181, 82, 8, 0, 35, 3, 224, 49, 248, ++ 2, 75, 1, 51, 0, 25, 147, 66, 249, 209, 16, 189, 48, 181, 19, 70, 12, ++ 70, 3, 224, 52, 248, 2, 91, 2, 59, 64, 25, 1, 43, 249, 216, 83, 8, 210, ++ 7, 68, 191, 17, 248, 19, 48, 192, 24, 131, 178, 3, 235, 16, 64, 0, 235, ++ 16, 64, 192, 67, 128, 178, 48, 189, 56, 181, 20, 70, 16, 34, 13, 70, ++ 255, 247, 215, 255, 5, 241, 18, 1, 164, 241, 18, 2, 189, 232, 56, 64, ++ 255, 247, 218, 191, 66, 104, 6, 75, 16, 181, 74, 97, 4, 70, 65, 96, ++ 0, 34, 24, 104, 2, 240, 68, 249, 35, 137, 1, 51, 35, 129, 16, 189, 16, ++ 111, 4, 0, 56, 181, 4, 137, 5, 70, 108, 177, 68, 104, 1, 34, 99, 105, ++ 33, 70, 67, 96, 5, 75, 24, 104, 2, 240, 49, 249, 0, 35, 99, 97, 43, ++ 137, 1, 59, 43, 129, 32, 70, 56, 189, 16, 111, 4, 0, 248, 181, 4, 70, ++ 71, 109, 255, 247, 229, 255, 5, 70, 72, 185, 227, 124, 19, 177, 32, ++ 70, 255, 247, 102, 255, 32, 70, 255, 247, 219, 255, 5, 70, 112, 177, ++ 102, 120, 102, 185, 95, 177, 103, 109, 32, 70, 161, 109, 42, 70, 1, ++ 35, 184, 71, 32, 177, 41, 70, 32, 70, 255, 247, 187, 255, 53, 70, 40, ++ 70, 248, 189, 16, 181, 4, 70, 255, 247, 180, 255, 35, 125, 67, 185, ++ 163, 124, 51, 177, 35, 124, 35, 185, 32, 70, 189, 232, 16, 64, 255, ++ 247, 84, 191, 16, 189, 45, 233, 248, 67, 6, 70, 12, 70, 143, 137, 2, ++ 177, 191, 16, 180, 248, 10, 128, 0, 37, 20, 224, 48, 70, 225, 137, 98, ++ 120, 255, 243, 54, 242, 129, 70, 152, 177, 32, 70, 73, 70, 251, 243, ++ 112, 243, 1, 53, 56, 177, 48, 70, 73, 70, 0, 34, 2, 240, 97, 248, 79, ++ 240, 255, 53, 7, 224, 5, 235, 8, 3, 187, 66, 230, 219, 0, 37, 1, 224, ++ 111, 240, 26, 5, 163, 124, 35, 177, 35, 124, 19, 185, 32, 70, 255, 247, ++ 36, 255, 40, 70, 189, 232, 248, 131, 66, 137, 40, 41, 40, 191, 40, 33, ++ 3, 70, 145, 66, 44, 191, 8, 70, 16, 70, 152, 129, 112, 71, 1, 117, 112, ++ 71, 0, 0, 5, 75, 0, 32, 27, 104, 4, 224, 138, 137, 128, 24, 138, 138, ++ 83, 248, 34, 16, 0, 41, 248, 209, 112, 71, 32, 7, 0, 0, 5, 75, 0, 32, ++ 27, 104, 3, 224, 138, 138, 1, 48, 83, 248, 34, 16, 0, 41, 249, 209, ++ 112, 71, 0, 191, 32, 7, 0, 0, 48, 181, 3, 70, 186, 177, 13, 72, 4, 104, ++ 208, 138, 84, 248, 32, 0, 144, 177, 12, 37, 5, 251, 1, 49, 13, 138, ++ 1, 61, 13, 130, 217, 136, 1, 57, 217, 128, 195, 138, 84, 248, 35, 48, ++ 3, 177, 27, 136, 211, 130, 0, 35, 195, 130, 48, 189, 16, 70, 48, 189, ++ 0, 191, 32, 7, 0, 0, 240, 181, 4, 120, 46, 79, 3, 70, 62, 93, 1, 48, ++ 22, 240, 32, 6, 247, 209, 43, 44, 1, 209, 3, 70, 5, 224, 45, 44, 8, ++ 191, 3, 70, 20, 191, 0, 38, 1, 38, 106, 185, 26, 120, 48, 42, 22, 209, ++ 90, 120, 120, 42, 1, 208, 88, 42, 2, 209, 2, 51, 16, 34, 15, 224, 1, ++ 51, 8, 34, 12, 224, 16, 42, 10, 209, 24, 120, 48, 40, 7, 209, 88, 120, ++ 120, 40, 1, 208, 88, 40, 2, 209, 2, 51, 0, 224, 10, 34, 0, 32, 17, 224, ++ 2, 251, 0, 68, 132, 66, 12, 210, 94, 185, 41, 179, 43, 70, 26, 120, ++ 1, 53, 186, 92, 18, 240, 68, 15, 248, 209, 11, 96, 79, 240, 255, 48, ++ 240, 189, 32, 70, 29, 70, 44, 120, 1, 51, 23, 248, 4, 192, 28, 240, ++ 68, 15, 12, 208, 28, 240, 4, 15, 1, 208, 48, 60, 5, 224, 28, 240, 2, ++ 15, 1, 208, 87, 60, 0, 224, 55, 60, 148, 66, 216, 211, 6, 177, 64, 66, ++ 25, 177, 13, 96, 240, 189, 79, 240, 255, 48, 240, 189, 22, 119, 135, ++ 0, 6, 34, 8, 181, 3, 73, 248, 247, 184, 255, 208, 241, 1, 0, 56, 191, ++ 0, 32, 8, 189, 236, 125, 135, 0, 6, 34, 8, 181, 3, 73, 248, 247, 172, ++ 255, 208, 241, 1, 0, 56, 191, 0, 32, 8, 189, 248, 125, 135, 0, 131, ++ 137, 112, 181, 14, 43, 132, 104, 64, 242, 130, 128, 163, 137, 129, 43, ++ 51, 209, 227, 137, 30, 10, 70, 234, 3, 38, 35, 138, 182, 178, 117, 11, ++ 8, 43, 3, 208, 77, 246, 134, 82, 147, 66, 19, 209, 162, 124, 19, 9, ++ 4, 43, 1, 209, 227, 124, 8, 224, 6, 43, 5, 209, 227, 124, 27, 9, 67, ++ 234, 2, 19, 219, 178, 0, 224, 0, 35, 91, 9, 2, 208, 79, 244, 128, 114, ++ 2, 224, 43, 70, 79, 244, 0, 114, 0, 41, 78, 208, 171, 66, 76, 208, 241, ++ 4, 201, 12, 65, 234, 67, 49, 137, 178, 13, 10, 69, 234, 1, 33, 225, ++ 129, 66, 244, 128, 98, 64, 224, 8, 43, 3, 208, 77, 246, 134, 82, 147, ++ 66, 52, 209, 162, 123, 19, 9, 4, 43, 1, 209, 227, 123, 8, 224, 6, 43, ++ 5, 209, 227, 123, 27, 9, 67, 234, 2, 19, 219, 178, 0, 224, 0, 35, 154, ++ 8, 20, 42, 26, 208, 9, 216, 12, 42, 23, 208, 1, 216, 10, 42, 2, 224, ++ 14, 42, 18, 208, 18, 42, 20, 209, 15, 224, 28, 42, 24, 208, 4, 216, ++ 22, 42, 10, 208, 26, 42, 12, 209, 18, 224, 30, 42, 16, 208, 46, 42, ++ 7, 209, 79, 244, 0, 98, 6, 35, 13, 224, 79, 244, 0, 98, 3, 35, 9, 224, ++ 91, 9, 79, 244, 0, 98, 5, 224, 0, 34, 19, 70, 2, 224, 79, 244, 0, 98, ++ 4, 35, 193, 137, 3, 240, 7, 4, 33, 240, 7, 1, 33, 67, 193, 129, 66, ++ 234, 3, 0, 112, 189, 0, 32, 112, 189, 0, 241, 52, 2, 52, 42, 8, 181, ++ 3, 70, 6, 217, 5, 72, 32, 33, 5, 74, 250, 243, 9, 243, 3, 72, 8, 189, ++ 4, 74, 67, 66, 82, 248, 35, 0, 8, 189, 158, 110, 4, 0, 247, 27, 4, 0, ++ 24, 121, 135, 0, 48, 181, 96, 185, 16, 224, 68, 120, 163, 28, 153, 66, ++ 11, 211, 5, 120, 149, 66, 9, 208, 192, 24, 111, 240, 1, 3, 27, 27, 201, ++ 24, 1, 41, 241, 216, 0, 32, 48, 189, 0, 32, 48, 189, 0, 0, 45, 233, ++ 240, 67, 137, 70, 161, 176, 144, 70, 1, 70, 32, 177, 3, 120, 19, 177, ++ 24, 72, 250, 243, 154, 242, 0, 38, 128, 37, 108, 70, 30, 224, 22, 240, ++ 15, 7, 7, 209, 32, 70, 41, 70, 19, 74, 51, 70, 250, 243, 205, 242, 36, ++ 24, 45, 26, 0, 45, 8, 221, 32, 70, 41, 70, 15, 74, 25, 248, 6, 48, 250, ++ 243, 194, 242, 36, 24, 45, 26, 15, 47, 5, 209, 11, 72, 105, 70, 250, ++ 243, 122, 242, 128, 37, 108, 70, 1, 54, 70, 69, 222, 209, 105, 70, 140, ++ 66, 2, 208, 5, 72, 250, 243, 111, 242, 33, 176, 189, 232, 240, 131, ++ 142, 31, 136, 0, 10, 28, 4, 0, 156, 31, 136, 0, 68, 78, 136, 0, 11, ++ 104, 154, 26, 154, 66, 10, 96, 2, 217, 3, 104, 1, 59, 3, 96, 112, 71, ++ 56, 181, 4, 70, 13, 70, 10, 34, 33, 70, 0, 32, 255, 247, 118, 253, 4, ++ 241, 12, 1, 165, 241, 12, 2, 189, 232, 56, 64, 255, 247, 121, 189, 127, ++ 181, 5, 70, 20, 70, 14, 70, 12, 34, 0, 33, 1, 168, 250, 243, 28, 242, ++ 5, 241, 16, 1, 4, 34, 2, 168, 248, 247, 150, 254, 5, 241, 12, 1, 4, ++ 34, 1, 168, 248, 247, 144, 254, 107, 122, 0, 32, 141, 248, 13, 48, 35, ++ 10, 67, 234, 4, 35, 1, 169, 12, 34, 141, 248, 12, 0, 173, 248, 14, 48, ++ 255, 247, 74, 253, 49, 70, 34, 70, 255, 247, 105, 253, 4, 176, 112, ++ 189, 112, 181, 138, 176, 4, 70, 14, 70, 21, 70, 0, 33, 36, 34, 1, 168, ++ 250, 243, 241, 241, 4, 241, 8, 1, 16, 34, 1, 168, 248, 247, 107, 254, ++ 4, 241, 24, 1, 16, 34, 5, 168, 248, 247, 101, 254, 98, 121, 35, 121, ++ 1, 169, 67, 234, 2, 35, 173, 248, 36, 48, 163, 121, 36, 34, 0, 32, 141, ++ 248, 39, 48, 255, 247, 32, 253, 49, 70, 42, 70, 255, 247, 63, 253, 10, ++ 176, 112, 189, 32, 40, 12, 191, 3, 32, 0, 32, 112, 71, 8, 181, 1, 34, ++ 252, 243, 54, 243, 24, 177, 67, 120, 5, 43, 152, 191, 0, 32, 8, 189, ++ 112, 181, 12, 70, 22, 70, 50, 73, 3, 34, 5, 70, 248, 247, 39, 254, 168, ++ 185, 235, 120, 8, 43, 86, 216, 223, 232, 3, 240, 74, 11, 13, 5, 8, 11, ++ 13, 85, 15, 0, 68, 242, 64, 3, 73, 224, 79, 244, 129, 67, 70, 224, 64, ++ 35, 68, 224, 128, 35, 66, 224, 32, 35, 64, 224, 40, 70, 36, 73, 3, 34, ++ 248, 247, 11, 254, 32, 185, 235, 120, 1, 43, 61, 209, 64, 34, 49, 224, ++ 40, 70, 32, 73, 3, 34, 248, 247, 0, 254, 56, 185, 235, 120, 0, 43, 50, ++ 209, 14, 185, 16, 35, 41, 224, 8, 35, 39, 224, 40, 70, 26, 73, 3, 34, ++ 248, 247, 242, 253, 96, 185, 235, 120, 1, 43, 3, 208, 21, 211, 2, 43, ++ 33, 209, 2, 224, 79, 244, 128, 98, 19, 224, 79, 244, 0, 99, 20, 224, ++ 40, 70, 17, 73, 3, 34, 248, 247, 223, 253, 152, 185, 235, 120, 1, 43, ++ 6, 208, 2, 211, 2, 43, 14, 209, 6, 224, 1, 32, 32, 96, 112, 189, 2, ++ 34, 34, 96, 24, 70, 112, 189, 4, 35, 35, 96, 1, 32, 112, 189, 0, 32, ++ 112, 189, 0, 32, 112, 189, 0, 191, 240, 20, 4, 0, 68, 29, 136, 0, 232, ++ 20, 4, 0, 244, 20, 4, 0, 236, 20, 4, 0, 1, 56, 192, 178, 10, 40, 154, ++ 191, 2, 75, 51, 248, 16, 0, 0, 32, 112, 71, 0, 191, 20, 28, 4, 0, 75, ++ 246, 255, 115, 3, 64, 64, 43, 20, 208, 128, 43, 18, 208, 16, 43, 16, ++ 208, 32, 43, 14, 208, 179, 245, 128, 95, 11, 208, 179, 245, 0, 79, 8, ++ 208, 179, 245, 128, 127, 7, 208, 163, 245, 0, 115, 88, 66, 64, 235, ++ 3, 0, 112, 71, 1, 32, 112, 71, 1, 32, 112, 71, 73, 242, 240, 51, 3, ++ 64, 24, 28, 24, 191, 1, 32, 112, 71, 45, 233, 240, 71, 170, 176, 51, ++ 156, 128, 70, 15, 70, 13, 241, 10, 0, 17, 70, 26, 70, 153, 70, 248, ++ 247, 146, 253, 42, 170, 229, 0, 2, 235, 9, 3, 3, 248, 158, 92, 45, 18, ++ 20, 241, 31, 10, 72, 191, 4, 241, 62, 10, 3, 248, 157, 92, 9, 241, 4, ++ 9, 79, 234, 106, 26, 50, 156, 0, 35, 21, 224, 43, 18, 141, 248, 9, 48, ++ 0, 35, 34, 174, 1, 147, 64, 70, 75, 70, 57, 70, 2, 170, 141, 248, 8, ++ 80, 0, 150, 253, 243, 148, 242, 32, 70, 49, 70, 32, 34, 248, 247, 105, ++ 253, 32, 52, 43, 70, 93, 28, 83, 69, 230, 219, 42, 176, 189, 232, 240, ++ 135, 248, 181, 7, 156, 208, 248, 172, 96, 100, 4, 221, 248, 24, 192, ++ 100, 12, 22, 177, 18, 240, 64, 79, 4, 209, 31, 1, 205, 25, 146, 25, ++ 170, 96, 8, 224, 149, 15, 31, 1, 34, 240, 64, 66, 68, 234, 5, 68, 150, ++ 25, 205, 25, 174, 96, 208, 248, 176, 32, 234, 96, 220, 248, 0, 32, 202, ++ 81, 108, 96, 130, 104, 210, 7, 14, 213, 27, 1, 205, 24, 168, 104, 238, ++ 104, 202, 88, 112, 64, 107, 104, 80, 64, 88, 64, 253, 243, 226, 247, ++ 16, 177, 68, 244, 128, 36, 108, 96, 248, 189, 130, 107, 129, 104, 16, ++ 181, 20, 104, 17, 240, 1, 15, 4, 244, 64, 52, 68, 240, 1, 3, 4, 191, ++ 68, 244, 0, 99, 67, 240, 1, 3, 137, 7, 144, 248, 181, 16, 72, 191, 67, ++ 244, 128, 99, 67, 234, 129, 67, 144, 248, 186, 16, 35, 244, 96, 3, 67, ++ 234, 65, 83, 144, 248, 187, 16, 35, 240, 64, 115, 67, 234, 1, 99, 144, ++ 248, 50, 16, 9, 177, 67, 234, 65, 35, 144, 248, 222, 16, 9, 177, 67, ++ 244, 0, 115, 208, 248, 160, 16, 67, 234, 65, 3, 19, 96, 16, 189, 176, ++ 248, 160, 48, 11, 128, 176, 248, 148, 0, 16, 128, 112, 71, 176, 248, ++ 70, 16, 16, 181, 3, 70, 209, 177, 66, 107, 20, 105, 208, 248, 196, 32, ++ 128, 110, 20, 64, 36, 26, 20, 64, 36, 9, 164, 178, 163, 248, 210, 64, ++ 179, 248, 72, 32, 7, 224, 216, 108, 80, 248, 34, 0, 64, 185, 1, 50, ++ 72, 30, 2, 64, 146, 178, 162, 66, 245, 209, 0, 32, 16, 189, 8, 70, 16, ++ 189, 45, 233, 240, 67, 176, 248, 70, 64, 36, 185, 12, 96, 79, 240, 255, ++ 48, 189, 232, 240, 131, 0, 37, 1, 43, 209, 248, 0, 192, 13, 96, 176, ++ 248, 210, 80, 2, 209, 176, 248, 74, 48, 30, 224, 208, 248, 52, 128, ++ 208, 248, 196, 96, 216, 248, 16, 48, 216, 248, 20, 144, 208, 248, 200, ++ 128, 135, 110, 51, 64, 9, 234, 8, 8, 219, 27, 199, 235, 8, 7, 51, 64, ++ 62, 64, 27, 9, 54, 9, 155, 178, 182, 178, 179, 66, 160, 248, 210, 48, ++ 3, 208, 115, 30, 1, 60, 35, 64, 155, 178, 13, 177, 0, 36, 19, 224, 176, ++ 248, 74, 64, 156, 66, 249, 210, 20, 224, 198, 108, 86, 248, 37, 96, ++ 38, 177, 100, 69, 10, 218, 66, 248, 36, 96, 1, 52, 176, 248, 70, 96, ++ 1, 53, 1, 62, 53, 64, 173, 178, 157, 66, 238, 209, 12, 96, 0, 32, 189, ++ 232, 240, 131, 79, 240, 255, 48, 189, 232, 240, 131, 176, 248, 108, ++ 16, 16, 181, 3, 70, 217, 177, 130, 107, 20, 105, 208, 248, 204, 32, ++ 208, 248, 144, 0, 20, 64, 36, 26, 20, 64, 36, 9, 164, 178, 163, 248, ++ 208, 64, 179, 248, 110, 32, 7, 224, 88, 111, 80, 248, 34, 0, 64, 185, ++ 1, 50, 72, 30, 2, 64, 146, 178, 162, 66, 245, 209, 0, 32, 16, 189, 8, ++ 70, 16, 189, 176, 248, 108, 32, 176, 248, 112, 16, 176, 248, 110, 48, ++ 1, 58, 203, 26, 2, 234, 3, 0, 112, 71, 16, 181, 160, 177, 131, 104, ++ 35, 234, 1, 1, 10, 67, 211, 7, 12, 213, 67, 107, 25, 104, 65, 244, 0, ++ 100, 28, 96, 67, 107, 28, 104, 20, 244, 0, 111, 20, 191, 25, 96, 34, ++ 240, 1, 2, 130, 96, 0, 224, 2, 70, 16, 70, 16, 189, 3, 70, 176, 248, ++ 70, 0, 240, 181, 0, 40, 89, 208, 1, 41, 179, 248, 72, 32, 2, 209, 179, ++ 248, 74, 64, 34, 224, 179, 248, 210, 64, 93, 107, 162, 66, 10, 209, ++ 44, 105, 211, 248, 196, 96, 159, 110, 52, 64, 228, 27, 52, 64, 36, 9, ++ 164, 178, 163, 248, 210, 64, 3, 41, 16, 209, 105, 105, 211, 248, 200, ++ 80, 41, 64, 157, 110, 73, 27, 211, 248, 196, 80, 137, 178, 41, 64, 9, ++ 9, 140, 66, 3, 208, 76, 30, 1, 56, 4, 64, 164, 178, 10, 177, 0, 32, ++ 26, 224, 179, 248, 74, 16, 161, 66, 249, 210, 38, 224, 217, 107, 21, ++ 1, 73, 25, 136, 104, 72, 104, 18, 72, 136, 96, 217, 107, 77, 25, 217, ++ 108, 232, 96, 0, 37, 81, 248, 34, 0, 65, 248, 34, 80, 179, 248, 70, ++ 16, 1, 50, 1, 57, 10, 64, 146, 178, 162, 66, 1, 208, 0, 40, 229, 208, ++ 179, 248, 70, 16, 179, 248, 74, 64, 163, 248, 72, 32, 162, 26, 76, 30, ++ 34, 64, 137, 26, 1, 57, 89, 96, 240, 189, 16, 70, 240, 189, 0, 191, ++ 239, 190, 173, 222, 192, 248, 188, 16, 0, 32, 112, 71, 177, 245, 128, ++ 127, 42, 208, 7, 216, 1, 41, 30, 208, 26, 211, 2, 41, 30, 208, 3, 41, ++ 51, 209, 30, 224, 64, 242, 3, 19, 153, 66, 38, 208, 7, 216, 64, 242, ++ 1, 19, 153, 66, 27, 208, 177, 245, 129, 127, 38, 209, 26, 224, 64, 242, ++ 5, 19, 153, 66, 28, 208, 64, 242, 7, 19, 153, 66, 29, 209, 26, 224, ++ 128, 248, 183, 32, 112, 71, 128, 248, 184, 32, 112, 71, 128, 248, 185, ++ 32, 112, 71, 128, 248, 182, 32, 112, 71, 128, 248, 186, 32, 112, 71, ++ 128, 248, 187, 32, 112, 71, 128, 248, 181, 32, 112, 71, 128, 248, 214, ++ 32, 112, 71, 128, 248, 50, 32, 112, 71, 128, 248, 222, 32, 112, 71, ++ 248, 181, 4, 70, 15, 70, 180, 248, 110, 80, 180, 248, 112, 48, 171, ++ 66, 83, 208, 180, 248, 208, 48, 157, 66, 12, 209, 163, 107, 212, 248, ++ 204, 32, 27, 105, 212, 248, 144, 16, 19, 64, 91, 26, 19, 64, 27, 9, ++ 155, 178, 164, 248, 208, 48, 15, 185, 157, 66, 65, 208, 99, 111, 0, ++ 34, 83, 248, 37, 96, 67, 248, 37, 32, 31, 75, 49, 70, 24, 104, 1, 34, ++ 1, 240, 171, 251, 148, 248, 50, 48, 19, 185, 148, 248, 222, 48, 155, ++ 177, 182, 241, 0, 79, 16, 209, 180, 248, 108, 48, 1, 53, 90, 30, 21, ++ 64, 180, 248, 112, 16, 173, 178, 164, 248, 110, 80, 77, 27, 42, 64, ++ 155, 26, 1, 59, 196, 248, 216, 48, 191, 231, 33, 108, 42, 1, 137, 24, ++ 139, 104, 14, 75, 1, 53, 139, 96, 33, 108, 138, 24, 211, 96, 180, 248, ++ 108, 48, 180, 248, 112, 16, 90, 30, 21, 64, 173, 178, 164, 248, 110, ++ 80, 77, 27, 42, 64, 155, 26, 1, 59, 196, 248, 216, 48, 2, 224, 0, 38, ++ 0, 224, 62, 70, 48, 70, 248, 189, 16, 111, 4, 0, 239, 190, 173, 222, ++ 176, 248, 108, 48, 11, 177, 255, 247, 149, 191, 24, 70, 112, 71, 56, ++ 181, 5, 70, 208, 248, 188, 0, 88, 177, 3, 120, 75, 177, 250, 243, 42, ++ 246, 4, 70, 88, 185, 213, 248, 188, 0, 1, 33, 255, 247, 158, 250, 5, ++ 224, 1, 36, 3, 224, 168, 106, 0, 34, 1, 240, 216, 250, 1, 33, 40, 70, ++ 255, 247, 222, 255, 1, 70, 0, 40, 244, 209, 52, 185, 213, 248, 188, ++ 0, 33, 70, 189, 232, 56, 64, 255, 247, 136, 186, 56, 189, 45, 233, 240, ++ 65, 4, 70, 0, 37, 32, 70, 0, 33, 255, 247, 202, 255, 6, 70, 0, 40, 90, ++ 208, 163, 104, 130, 104, 19, 240, 128, 15, 8, 208, 212, 248, 160, 48, ++ 91, 8, 2, 51, 50, 248, 19, 48, 4, 51, 19, 128, 0, 224, 19, 136, 212, ++ 248, 160, 16, 180, 248, 148, 32, 88, 24, 144, 66, 56, 191, 2, 70, 148, ++ 248, 50, 0, 72, 177, 181, 137, 170, 66, 2, 216, 178, 129, 0, 34, 0, ++ 224, 82, 27, 166, 248, 80, 32, 0, 224, 178, 129, 180, 248, 148, 112, ++ 207, 27, 255, 24, 0, 47, 47, 221, 163, 104, 91, 6, 23, 213, 160, 106, ++ 49, 70, 0, 34, 34, 224, 3, 136, 168, 248, 20, 48, 180, 248, 148, 48, ++ 148, 248, 50, 16, 159, 66, 180, 191, 58, 70, 26, 70, 17, 177, 170, 66, ++ 40, 191, 42, 70, 255, 26, 0, 47, 130, 129, 2, 220, 8, 224, 176, 70, ++ 0, 224, 128, 70, 32, 70, 0, 33, 255, 247, 122, 255, 0, 40, 226, 209, ++ 162, 104, 18, 240, 4, 2, 7, 209, 160, 106, 49, 70, 1, 240, 102, 250, ++ 227, 104, 1, 51, 227, 96, 157, 231, 48, 70, 189, 232, 240, 129, 56, ++ 181, 176, 248, 72, 32, 176, 248, 74, 48, 4, 70, 154, 66, 13, 70, 7, ++ 209, 56, 189, 163, 104, 26, 7, 3, 212, 160, 106, 1, 34, 1, 240, 78, ++ 250, 41, 70, 32, 70, 255, 247, 70, 254, 1, 70, 0, 40, 241, 209, 56, ++ 189, 45, 233, 255, 71, 0, 35, 3, 147, 4, 70, 14, 70, 144, 70, 176, 248, ++ 74, 80, 11, 70, 76, 224, 67, 73, 159, 138, 9, 104, 5, 241, 1, 10, 81, ++ 248, 39, 112, 180, 248, 70, 16, 180, 248, 72, 144, 1, 57, 10, 234, 1, ++ 10, 202, 69, 154, 104, 152, 137, 179, 248, 16, 192, 98, 208, 28, 235, ++ 0, 0, 52, 208, 179, 66, 79, 240, 0, 14, 8, 191, 79, 240, 0, 67, 205, ++ 248, 12, 224, 8, 191, 3, 147, 87, 185, 3, 155, 67, 240, 128, 78, 205, ++ 248, 12, 224, 184, 241, 0, 15, 2, 208, 67, 240, 192, 67, 3, 147, 141, ++ 66, 3, 209, 3, 155, 67, 240, 128, 83, 3, 147, 148, 248, 214, 48, 27, ++ 177, 3, 155, 67, 244, 128, 35, 3, 147, 3, 171, 0, 147, 1, 144, 43, 70, ++ 32, 70, 225, 107, 255, 247, 200, 252, 180, 248, 70, 48, 1, 53, 1, 59, ++ 29, 64, 180, 248, 72, 48, 173, 178, 171, 66, 42, 208, 59, 70, 0, 43, ++ 176, 209, 3, 155, 89, 0, 9, 212, 180, 248, 70, 32, 105, 30, 1, 58, 10, ++ 64, 225, 107, 18, 1, 67, 240, 192, 67, 139, 80, 180, 248, 70, 48, 104, ++ 30, 90, 30, 225, 108, 16, 64, 65, 248, 32, 96, 164, 248, 74, 80, 184, ++ 241, 0, 15, 4, 208, 160, 110, 97, 107, 0, 235, 5, 16, 72, 96, 180, 248, ++ 72, 16, 0, 32, 109, 26, 42, 64, 155, 26, 1, 59, 99, 96, 11, 224, 160, ++ 106, 49, 70, 1, 34, 1, 240, 191, 249, 0, 35, 99, 96, 99, 105, 79, 240, ++ 255, 48, 1, 51, 99, 97, 4, 176, 189, 232, 240, 135, 0, 191, 32, 7, 0, ++ 0, 45, 233, 240, 79, 0, 35, 143, 176, 13, 147, 131, 104, 144, 248, 50, ++ 16, 144, 248, 222, 32, 3, 240, 16, 11, 4, 70, 187, 241, 0, 15, 12, 191, ++ 79, 240, 1, 11, 79, 240, 16, 11, 0, 41, 12, 191, 1, 35, 2, 35, 162, ++ 177, 208, 248, 188, 48, 27, 177, 26, 120, 10, 177, 218, 137, 1, 224, ++ 180, 248, 148, 32, 17, 177, 194, 245, 0, 98, 1, 33, 2, 245, 244, 114, ++ 79, 244, 246, 115, 3, 50, 146, 251, 243, 242, 139, 24, 180, 248, 108, ++ 32, 180, 248, 112, 96, 180, 248, 110, 16, 85, 30, 113, 26, 41, 64, 195, ++ 241, 1, 0, 137, 178, 65, 26, 212, 248, 156, 0, 145, 251, 243, 241, 146, ++ 251, 243, 243, 131, 66, 148, 191, 201, 24, 9, 24, 180, 248, 148, 48, ++ 8, 145, 204, 43, 3, 217, 212, 248, 152, 32, 5, 146, 1, 224, 0, 35, 5, ++ 147, 79, 240, 0, 10, 246, 224, 212, 248, 188, 0, 120, 177, 3, 120, 107, ++ 177, 3, 137, 4, 43, 7, 216, 4, 241, 32, 0, 126, 73, 249, 243, 142, 245, ++ 120, 185, 212, 248, 188, 0, 255, 247, 157, 248, 8, 224, 180, 248, 148, ++ 16, 5, 154, 1, 57, 89, 68, 160, 106, 137, 24, 1, 240, 33, 249, 5, 70, ++ 112, 185, 186, 241, 0, 15, 6, 209, 32, 70, 253, 243, 245, 241, 0, 48, ++ 24, 191, 1, 32, 0, 224, 0, 32, 35, 105, 1, 51, 35, 97, 206, 224, 163, ++ 104, 19, 240, 16, 3, 5, 208, 131, 104, 11, 241, 255, 50, 195, 235, 11, ++ 3, 19, 64, 5, 154, 155, 24, 5, 208, 170, 104, 210, 24, 170, 96, 170, ++ 137, 211, 26, 171, 129, 213, 248, 8, 128, 99, 111, 0, 39, 200, 248, ++ 0, 112, 67, 248, 38, 80, 96, 75, 41, 70, 24, 104, 58, 70, 1, 240, 137, ++ 249, 148, 248, 50, 48, 193, 70, 0, 43, 54, 209, 180, 248, 148, 112, ++ 148, 248, 222, 80, 79, 240, 0, 67, 0, 45, 12, 191, 61, 70, 79, 244, ++ 246, 117, 13, 147, 197, 241, 0, 8, 127, 27, 180, 248, 108, 32, 123, ++ 25, 1, 58, 150, 66, 3, 209, 13, 154, 66, 240, 128, 82, 13, 146, 13, ++ 170, 171, 66, 212, 191, 1, 147, 1, 149, 0, 146, 51, 70, 74, 70, 32, ++ 70, 33, 108, 255, 247, 182, 251, 180, 248, 108, 48, 1, 54, 1, 59, 30, ++ 64, 0, 47, 182, 178, 169, 68, 115, 221, 99, 111, 79, 240, 0, 66, 67, ++ 248, 38, 32, 0, 35, 13, 147, 71, 68, 215, 231, 180, 248, 108, 48, 13, ++ 151, 1, 59, 158, 66, 4, 191, 79, 240, 128, 83, 13, 147, 13, 153, 170, ++ 137, 14, 171, 65, 240, 0, 65, 67, 248, 4, 29, 0, 147, 1, 146, 51, 70, ++ 66, 70, 32, 70, 33, 108, 255, 247, 140, 251, 181, 248, 82, 112, 180, ++ 248, 108, 48, 213, 248, 64, 144, 213, 248, 68, 128, 148, 248, 222, 80, ++ 1, 54, 0, 45, 12, 191, 61, 70, 79, 244, 246, 117, 1, 59, 30, 64, 197, ++ 241, 0, 12, 205, 248, 36, 160, 182, 178, 127, 27, 226, 70, 98, 111, ++ 79, 240, 0, 65, 66, 248, 38, 16, 0, 34, 13, 146, 180, 248, 108, 32, ++ 123, 25, 1, 58, 150, 66, 4, 191, 79, 240, 128, 82, 13, 146, 13, 170, ++ 171, 66, 212, 191, 2, 147, 2, 149, 0, 150, 205, 248, 44, 144, 205, 248, ++ 48, 128, 1, 146, 11, 171, 12, 203, 33, 108, 32, 70, 253, 243, 203, 240, ++ 180, 248, 108, 48, 1, 54, 1, 59, 30, 64, 0, 47, 182, 178, 14, 221, 0, ++ 35, 205, 248, 28, 128, 6, 147, 221, 233, 6, 35, 66, 234, 9, 2, 82, 25, ++ 67, 241, 0, 3, 152, 70, 145, 70, 87, 68, 199, 231, 221, 248, 36, 160, ++ 10, 241, 1, 10, 8, 154, 146, 69, 127, 244, 5, 175, 0, 32, 212, 248, ++ 144, 32, 163, 107, 164, 248, 112, 96, 2, 235, 6, 22, 94, 96, 15, 176, ++ 189, 232, 240, 143, 228, 46, 4, 0, 16, 111, 4, 0, 0, 72, 112, 71, 192, ++ 98, 4, 0, 0, 72, 112, 71, 8, 48, 4, 0, 0, 32, 112, 71, 8, 181, 255, ++ 247, 243, 255, 65, 120, 2, 120, 1, 35, 19, 250, 1, 241, 19, 250, 2, ++ 242, 10, 67, 129, 120, 139, 64, 66, 234, 3, 0, 8, 189, 45, 233, 247, ++ 67, 79, 240, 0, 8, 4, 70, 15, 70, 22, 70, 153, 70, 69, 70, 1, 35, 3, ++ 250, 8, 243, 19, 234, 9, 15, 43, 208, 99, 105, 32, 70, 34, 43, 10, 221, ++ 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 4, 240, 35, 218, 1, ++ 70, 32, 70, 0, 224, 0, 33, 79, 244, 196, 98, 4, 240, 107, 217, 192, ++ 248, 0, 128, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 91, 6, 7, 213, ++ 64, 246, 39, 1, 0, 34, 4, 240, 13, 218, 1, 70, 32, 70, 0, 224, 0, 33, ++ 64, 242, 36, 98, 4, 240, 85, 217, 3, 104, 29, 67, 8, 241, 1, 8, 184, ++ 241, 31, 15, 200, 209, 157, 248, 40, 48, 75, 177, 69, 177, 1, 35, 0, ++ 147, 32, 70, 43, 70, 57, 70, 50, 70, 255, 247, 180, 255, 5, 67, 40, ++ 70, 189, 232, 254, 131, 129, 104, 56, 181, 64, 246, 60, 3, 153, 66, ++ 4, 70, 40, 209, 195, 104, 11, 43, 3, 216, 79, 240, 168, 113, 153, 64, ++ 1, 212, 12, 43, 31, 217, 73, 242, 24, 35, 154, 66, 5, 208, 73, 246, ++ 64, 67, 154, 66, 23, 209, 12, 77, 0, 224, 12, 77, 99, 105, 32, 70, 34, ++ 43, 10, 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 0, 34, 4, 240, ++ 199, 217, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 220, 98, 4, 240, 15, ++ 217, 5, 96, 56, 189, 0, 191, 153, 1, 1, 0, 182, 1, 1, 0, 56, 181, 67, ++ 105, 4, 70, 34, 43, 10, 221, 195, 105, 93, 6, 7, 213, 64, 246, 39, 1, ++ 0, 34, 4, 240, 171, 217, 1, 70, 32, 70, 1, 224, 32, 70, 0, 33, 79, 244, ++ 192, 98, 4, 240, 242, 216, 5, 104, 32, 70, 5, 240, 124, 5, 173, 8, 255, ++ 247, 71, 255, 3, 224, 131, 120, 171, 66, 7, 208, 12, 48, 16, 177, 3, ++ 136, 0, 43, 247, 209, 32, 70, 255, 247, 63, 255, 3, 136, 79, 244, 122, ++ 112, 88, 67, 56, 189, 112, 181, 4, 70, 22, 70, 13, 70, 1, 240, 195, ++ 248, 148, 248, 96, 35, 9, 75, 0, 40, 24, 191, 1, 35, 1, 42, 148, 248, ++ 104, 35, 8, 191, 212, 248, 92, 51, 1, 42, 12, 191, 212, 248, 100, 35, ++ 111, 240, 0, 66, 43, 96, 50, 96, 112, 189, 0, 191, 1, 0, 130, 14, 45, ++ 233, 255, 71, 29, 70, 67, 105, 144, 70, 0, 34, 34, 43, 4, 70, 137, 70, ++ 2, 146, 3, 146, 9, 221, 195, 105, 95, 6, 6, 213, 64, 246, 39, 1, 4, ++ 240, 89, 217, 1, 70, 32, 70, 1, 224, 32, 70, 0, 33, 79, 244, 196, 98, ++ 4, 240, 160, 216, 5, 96, 35, 106, 32, 70, 12, 43, 99, 105, 22, 221, ++ 34, 43, 10, 221, 227, 105, 94, 6, 7, 213, 64, 246, 39, 1, 0, 34, 4, ++ 240, 64, 217, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 197, 98, 4, 240, ++ 136, 216, 7, 104, 63, 12, 191, 5, 191, 13, 20, 224, 34, 43, 10, 221, ++ 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 0, 34, 4, 240, 41, 217, 1, ++ 70, 32, 70, 0, 224, 0, 33, 79, 244, 197, 98, 4, 240, 113, 216, 7, 104, ++ 63, 10, 255, 178, 1, 35, 171, 64, 0, 38, 32, 70, 73, 70, 66, 70, 0, ++ 150, 255, 247, 215, 254, 5, 70, 1, 34, 18, 250, 6, 243, 43, 66, 7, 208, ++ 0, 146, 32, 70, 73, 70, 66, 70, 255, 247, 203, 254, 37, 234, 0, 5, 1, ++ 54, 31, 46, 239, 209, 32, 70, 2, 169, 3, 170, 255, 247, 117, 255, 2, ++ 155, 0, 38, 37, 234, 3, 10, 53, 70, 1, 35, 171, 64, 19, 234, 10, 15, ++ 8, 208, 32, 70, 73, 70, 66, 70, 235, 178, 255, 247, 131, 255, 134, 66, ++ 56, 191, 6, 70, 1, 53, 31, 45, 238, 209, 184, 28, 128, 25, 4, 176, 189, ++ 232, 240, 135, 45, 233, 240, 65, 6, 158, 4, 70, 21, 70, 31, 70, 255, ++ 247, 142, 254, 0, 40, 112, 208, 16, 234, 6, 8, 0, 234, 7, 7, 44, 208, ++ 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, ++ 39, 1, 0, 34, 4, 240, 201, 216, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, ++ 28, 98, 4, 240, 17, 216, 99, 105, 6, 70, 34, 43, 32, 70, 10, 221, 227, ++ 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, 4, 240, 180, 216, 1, 70, ++ 32, 70, 0, 224, 0, 33, 64, 242, 28, 98, 3, 240, 252, 223, 3, 104, 67, ++ 234, 8, 3, 51, 96, 0, 47, 43, 208, 99, 105, 32, 70, 34, 43, 10, 221, ++ 227, 105, 94, 6, 7, 213, 64, 246, 39, 1, 0, 34, 4, 240, 154, 216, 1, ++ 70, 32, 70, 0, 224, 0, 33, 79, 244, 195, 98, 3, 240, 226, 223, 99, 105, ++ 6, 70, 34, 43, 32, 70, 10, 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, ++ 1, 0, 34, 4, 240, 133, 216, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 195, ++ 98, 3, 240, 205, 223, 3, 104, 31, 67, 55, 96, 7, 155, 154, 3, 5, 212, ++ 189, 232, 240, 129, 10, 32, 253, 243, 140, 245, 1, 224, 64, 242, 221, ++ 84, 213, 248, 224, 49, 155, 3, 1, 212, 1, 60, 243, 209, 189, 232, 240, ++ 129, 247, 181, 30, 70, 67, 105, 4, 70, 34, 43, 15, 70, 21, 70, 11, 221, ++ 195, 105, 90, 6, 8, 213, 64, 246, 39, 1, 0, 34, 4, 240, 87, 216, 0, ++ 151, 1, 70, 32, 70, 2, 224, 0, 151, 32, 70, 0, 33, 79, 240, 255, 51, ++ 79, 244, 202, 98, 4, 240, 8, 218, 99, 105, 34, 43, 12, 221, 227, 105, ++ 91, 6, 9, 213, 64, 246, 39, 1, 32, 70, 0, 34, 4, 240, 62, 216, 0, 150, ++ 1, 70, 32, 70, 2, 224, 0, 150, 32, 70, 0, 33, 64, 242, 84, 98, 43, 70, ++ 4, 240, 240, 217, 254, 189, 247, 181, 30, 70, 67, 105, 4, 70, 34, 43, ++ 15, 70, 21, 70, 11, 221, 195, 105, 91, 6, 8, 213, 64, 246, 39, 1, 0, ++ 34, 4, 240, 33, 216, 0, 151, 1, 70, 32, 70, 2, 224, 0, 151, 32, 70, ++ 0, 33, 79, 240, 255, 51, 79, 244, 203, 98, 4, 240, 210, 217, 99, 105, ++ 34, 43, 12, 221, 227, 105, 89, 6, 9, 213, 64, 246, 39, 1, 32, 70, 0, ++ 34, 4, 240, 8, 216, 0, 150, 1, 70, 32, 70, 2, 224, 0, 150, 32, 70, 0, ++ 33, 64, 242, 92, 98, 43, 70, 4, 240, 186, 217, 254, 189, 247, 181, 30, ++ 70, 67, 105, 4, 70, 34, 43, 15, 70, 21, 70, 11, 221, 195, 105, 89, 6, ++ 8, 213, 64, 246, 39, 1, 0, 34, 3, 240, 235, 223, 0, 151, 1, 70, 32, ++ 70, 2, 224, 0, 151, 32, 70, 0, 33, 79, 240, 255, 51, 79, 244, 204, 98, ++ 4, 240, 156, 217, 99, 105, 34, 43, 12, 221, 227, 105, 90, 6, 9, 213, ++ 64, 246, 39, 1, 32, 70, 0, 34, 3, 240, 210, 223, 0, 150, 1, 70, 32, ++ 70, 2, 224, 0, 150, 32, 70, 0, 33, 64, 242, 100, 98, 43, 70, 4, 240, ++ 132, 217, 254, 189, 67, 105, 19, 181, 34, 43, 4, 70, 13, 221, 195, 105, ++ 91, 6, 10, 213, 64, 246, 39, 1, 0, 34, 3, 240, 184, 223, 79, 244, 128, ++ 99, 1, 70, 0, 147, 32, 70, 4, 224, 79, 244, 128, 99, 0, 147, 32, 70, ++ 0, 33, 79, 244, 192, 98, 4, 240, 103, 217, 28, 189, 45, 233, 240, 79, ++ 1, 58, 210, 178, 8, 42, 133, 176, 4, 70, 154, 70, 21, 216, 55, 75, 158, ++ 92, 55, 75, 159, 92, 55, 75, 19, 248, 2, 144, 54, 75, 155, 92, 3, 147, ++ 54, 75, 19, 248, 2, 176, 53, 75, 155, 92, 2, 147, 53, 75, 19, 248, 2, ++ 128, 52, 75, 157, 92, 7, 224, 0, 37, 168, 70, 2, 149, 171, 70, 3, 149, ++ 169, 70, 47, 70, 46, 70, 99, 105, 34, 43, 13, 221, 227, 105, 91, 6, ++ 10, 213, 64, 246, 39, 1, 32, 70, 0, 34, 3, 240, 117, 223, 205, 248, ++ 0, 144, 1, 70, 32, 70, 3, 224, 205, 248, 0, 144, 32, 70, 0, 33, 79, ++ 240, 255, 51, 79, 244, 203, 98, 4, 240, 36, 217, 99, 105, 34, 43, 15, ++ 221, 227, 105, 88, 6, 12, 213, 64, 246, 39, 1, 32, 70, 0, 34, 3, 240, ++ 90, 223, 7, 234, 10, 3, 179, 64, 1, 70, 0, 147, 32, 70, 5, 224, 7, 234, ++ 10, 3, 179, 64, 32, 70, 0, 147, 0, 33, 23, 250, 6, 243, 64, 242, 92, ++ 98, 4, 240, 5, 217, 3, 155, 131, 177, 72, 250, 11, 242, 8, 234, 10, ++ 8, 72, 250, 11, 251, 32, 70, 2, 156, 41, 70, 162, 64, 11, 250, 4, 243, ++ 5, 176, 189, 232, 240, 79, 255, 247, 3, 191, 5, 176, 189, 232, 240, ++ 143, 0, 191, 237, 46, 4, 0, 246, 46, 4, 0, 255, 46, 4, 0, 8, 47, 4, ++ 0, 17, 47, 4, 0, 124, 49, 4, 0, 136, 47, 4, 0, 145, 47, 4, 0, 45, 233, ++ 248, 67, 4, 70, 137, 70, 3, 240, 100, 222, 0, 33, 6, 70, 32, 70, 4, ++ 240, 173, 217, 128, 70, 32, 70, 255, 247, 185, 252, 7, 70, 32, 70, 4, ++ 240, 83, 216, 73, 70, 5, 70, 66, 70, 59, 120, 32, 70, 255, 247, 154, ++ 253, 11, 35, 2, 48, 88, 67, 7, 75, 49, 70, 235, 24, 179, 251, 245, 245, ++ 69, 67, 32, 70, 4, 240, 146, 217, 10, 35, 181, 251, 243, 245, 168, 178, ++ 189, 232, 248, 131, 63, 66, 15, 0, 56, 181, 67, 105, 4, 70, 34, 43, ++ 10, 221, 195, 105, 93, 6, 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, 229, ++ 222, 1, 70, 32, 70, 1, 224, 32, 70, 0, 33, 64, 242, 20, 98, 3, 240, ++ 44, 222, 99, 105, 5, 104, 34, 43, 32, 70, 10, 221, 227, 105, 89, 6, ++ 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, 207, 222, 1, 70, 32, 70, 0, 224, ++ 0, 33, 64, 242, 20, 98, 3, 240, 23, 222, 3, 104, 157, 66, 20, 208, 99, ++ 105, 32, 70, 34, 43, 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, ++ 1, 0, 34, 3, 240, 184, 222, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 20, ++ 98, 3, 240, 0, 222, 5, 104, 40, 70, 56, 189, 56, 181, 28, 70, 29, 104, ++ 255, 247, 182, 255, 3, 70, 35, 96, 64, 27, 56, 189, 45, 233, 247, 67, ++ 0, 37, 4, 70, 15, 70, 22, 70, 152, 70, 157, 248, 40, 144, 1, 149, 255, ++ 247, 166, 255, 1, 144, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 91, ++ 6, 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, 139, 222, 1, 70, 32, 70, 0, ++ 224, 0, 33, 79, 244, 194, 98, 3, 240, 211, 221, 185, 241, 1, 15, 0, ++ 104, 1, 209, 8, 185, 14, 224, 80, 185, 184, 235, 69, 31, 9, 217, 32, ++ 70, 57, 70, 50, 70, 1, 171, 255, 247, 198, 255, 45, 24, 217, 231, 0, ++ 32, 0, 224, 1, 32, 11, 155, 109, 1, 29, 96, 189, 232, 254, 131, 45, ++ 233, 240, 79, 0, 38, 133, 176, 128, 70, 137, 70, 146, 70, 3, 150, 1, ++ 37, 3, 175, 64, 70, 73, 70, 82, 70, 67, 246, 152, 35, 0, 149, 1, 151, ++ 255, 247, 178, 255, 4, 70, 136, 185, 141, 232, 129, 0, 64, 35, 64, 70, ++ 73, 70, 82, 70, 221, 248, 12, 176, 255, 247, 166, 255, 3, 155, 56, 185, ++ 155, 68, 94, 68, 67, 246, 151, 35, 158, 66, 224, 217, 40, 70, 0, 224, ++ 32, 70, 5, 176, 189, 232, 240, 143, 45, 233, 248, 67, 153, 70, 67, 105, ++ 4, 70, 34, 43, 14, 70, 21, 70, 221, 248, 32, 128, 9, 159, 10, 221, 195, ++ 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, 40, 222, 1, 70, 32, ++ 70, 1, 224, 32, 70, 0, 33, 79, 244, 195, 98, 3, 240, 111, 221, 3, 104, ++ 32, 70, 201, 248, 0, 48, 99, 105, 34, 43, 10, 221, 227, 105, 91, 6, ++ 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, 16, 222, 1, 70, 32, 70, 0, 224, ++ 0, 33, 64, 242, 28, 98, 3, 240, 88, 221, 3, 104, 32, 70, 200, 248, 0, ++ 48, 213, 248, 224, 49, 59, 96, 255, 247, 177, 251, 7, 70, 0, 40, 114, ++ 208, 213, 248, 224, 49, 153, 3, 4, 212, 32, 70, 49, 70, 42, 70, 255, ++ 247, 138, 255, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 90, 6, 7, ++ 213, 64, 246, 39, 1, 0, 34, 3, 240, 231, 221, 1, 70, 32, 70, 0, 224, ++ 0, 33, 79, 244, 195, 98, 3, 240, 47, 221, 99, 105, 6, 70, 34, 43, 32, ++ 70, 10, 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, ++ 210, 221, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 195, 98, 3, 240, 26, ++ 221, 3, 104, 255, 67, 59, 64, 51, 96, 99, 105, 32, 70, 34, 43, 10, 221, ++ 227, 105, 94, 6, 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, 186, 221, 1, ++ 70, 32, 70, 0, 224, 0, 33, 64, 242, 28, 98, 3, 240, 2, 221, 99, 105, ++ 6, 70, 34, 43, 32, 70, 10, 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, ++ 1, 0, 34, 3, 240, 165, 221, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 28, ++ 98, 3, 240, 237, 220, 3, 104, 64, 242, 221, 84, 31, 64, 55, 96, 2, 224, ++ 10, 32, 253, 243, 174, 242, 213, 248, 224, 49, 154, 3, 1, 213, 1, 60, ++ 246, 209, 100, 32, 189, 232, 248, 67, 253, 243, 163, 178, 189, 232, ++ 248, 131, 55, 181, 4, 70, 1, 171, 79, 244, 0, 97, 106, 70, 4, 240, 37, ++ 216, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 93, 6, 7, 213, 64, ++ 246, 39, 1, 0, 34, 3, 240, 115, 221, 1, 70, 32, 70, 0, 224, 0, 33, 79, ++ 244, 206, 98, 3, 240, 187, 220, 5, 104, 21, 240, 0, 83, 22, 208, 99, ++ 105, 32, 70, 34, 43, 10, 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, ++ 1, 0, 34, 3, 240, 91, 221, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 206, ++ 98, 3, 240, 163, 220, 5, 96, 1, 37, 0, 224, 29, 70, 32, 70, 157, 232, ++ 6, 0, 3, 240, 46, 223, 40, 70, 62, 189, 112, 181, 4, 70, 14, 70, 3, ++ 240, 141, 220, 0, 33, 5, 70, 32, 70, 3, 240, 214, 223, 49, 70, 2, 70, ++ 32, 70, 255, 247, 129, 251, 41, 70, 6, 70, 32, 70, 3, 240, 204, 223, ++ 48, 70, 112, 189, 1, 75, 24, 96, 112, 71, 0, 191, 4, 111, 4, 0, 248, ++ 181, 72, 79, 4, 70, 58, 104, 0, 42, 64, 240, 137, 128, 67, 105, 34, ++ 43, 9, 221, 195, 105, 91, 6, 6, 213, 64, 246, 39, 1, 3, 240, 27, 221, ++ 1, 70, 32, 70, 1, 224, 32, 70, 0, 33, 64, 242, 20, 98, 3, 240, 98, 220, ++ 99, 105, 5, 104, 34, 43, 32, 70, 10, 221, 227, 105, 94, 6, 7, 213, 64, ++ 246, 39, 1, 0, 34, 3, 240, 5, 221, 1, 70, 32, 70, 0, 224, 0, 33, 64, ++ 242, 20, 98, 3, 240, 77, 220, 3, 104, 157, 66, 20, 208, 99, 105, 32, ++ 70, 34, 43, 10, 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 0, 34, ++ 3, 240, 238, 220, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 20, 98, 3, ++ 240, 54, 220, 5, 104, 66, 242, 16, 112, 253, 243, 251, 241, 99, 105, ++ 32, 70, 34, 43, 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, ++ 34, 3, 240, 213, 220, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 20, 98, ++ 3, 240, 29, 220, 99, 105, 6, 104, 34, 43, 32, 70, 10, 221, 227, 105, ++ 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, 192, 220, 1, 70, 32, 70, ++ 0, 224, 0, 33, 64, 242, 20, 98, 3, 240, 8, 220, 3, 104, 158, 66, 20, ++ 208, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 94, 6, 7, 213, 64, ++ 246, 39, 1, 0, 34, 3, 240, 169, 220, 1, 70, 32, 70, 0, 224, 0, 33, 64, ++ 242, 20, 98, 3, 240, 241, 219, 6, 104, 117, 27, 100, 38, 117, 67, 61, ++ 96, 56, 104, 248, 189, 4, 111, 4, 0, 45, 233, 247, 79, 4, 70, 136, 70, ++ 145, 70, 31, 70, 3, 240, 230, 221, 131, 70, 0, 40, 64, 240, 217, 128, ++ 32, 70, 3, 240, 211, 219, 89, 70, 130, 70, 32, 70, 3, 240, 28, 223, ++ 99, 105, 5, 70, 45, 43, 12, 209, 208, 248, 244, 48, 185, 241, 0, 15, ++ 2, 208, 35, 240, 0, 115, 1, 224, 67, 240, 0, 115, 197, 248, 244, 48, ++ 184, 224, 32, 70, 255, 247, 24, 250, 195, 120, 1, 38, 158, 64, 0, 240, ++ 177, 128, 185, 241, 0, 15, 94, 208, 99, 105, 32, 70, 34, 43, 10, 221, ++ 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 90, 70, 3, 240, 92, 220, 1, ++ 70, 32, 70, 0, 224, 0, 33, 79, 244, 195, 98, 3, 240, 164, 219, 3, 104, ++ 65, 70, 59, 96, 67, 234, 6, 7, 1, 35, 0, 147, 32, 70, 59, 70, 42, 70, ++ 255, 247, 10, 250, 99, 105, 7, 67, 34, 43, 32, 70, 10, 221, 227, 105, ++ 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, 59, 220, 1, 70, 32, 70, ++ 0, 224, 0, 33, 79, 244, 195, 98, 3, 240, 131, 219, 65, 70, 7, 96, 42, ++ 70, 32, 70, 255, 247, 196, 253, 79, 244, 122, 112, 253, 243, 67, 241, ++ 64, 242, 221, 87, 2, 224, 10, 32, 253, 243, 61, 241, 99, 105, 32, 70, ++ 34, 43, 10, 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, 3, ++ 240, 23, 220, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 12, 98, 3, 240, ++ 95, 219, 3, 104, 51, 66, 66, 209, 1, 63, 227, 209, 63, 224, 58, 104, ++ 154, 185, 99, 105, 32, 70, 34, 43, 9, 221, 227, 105, 95, 6, 6, 213, ++ 64, 246, 39, 1, 3, 240, 252, 219, 1, 70, 32, 70, 0, 224, 0, 33, 79, ++ 244, 195, 98, 3, 240, 68, 219, 2, 104, 34, 234, 6, 7, 1, 35, 0, 147, ++ 32, 70, 59, 70, 65, 70, 42, 70, 255, 247, 171, 249, 99, 105, 7, 67, ++ 55, 66, 12, 191, 0, 38, 1, 38, 34, 43, 32, 70, 10, 221, 227, 105, 89, ++ 6, 7, 213, 64, 246, 39, 1, 0, 34, 3, 240, 216, 219, 1, 70, 32, 70, 0, ++ 224, 0, 33, 79, 244, 195, 98, 3, 240, 32, 219, 65, 70, 7, 96, 42, 70, ++ 32, 70, 255, 247, 97, 253, 0, 224, 1, 38, 64, 242, 45, 23, 2, 224, 10, ++ 32, 253, 243, 220, 240, 43, 105, 3, 244, 128, 83, 179, 235, 6, 63, 1, ++ 208, 1, 63, 244, 209, 32, 70, 81, 70, 3, 176, 189, 232, 240, 79, 3, ++ 240, 75, 158, 3, 176, 189, 232, 240, 143, 240, 181, 137, 176, 4, 70, ++ 13, 70, 6, 170, 7, 171, 79, 244, 0, 97, 3, 240, 76, 222, 41, 70, 32, ++ 70, 255, 247, 90, 254, 79, 244, 122, 118, 0, 34, 176, 251, 246, 246, ++ 19, 70, 2, 33, 32, 70, 255, 247, 157, 251, 0, 34, 7, 70, 19, 70, 0, ++ 240, 15, 5, 3, 33, 32, 70, 255, 247, 148, 251, 79, 246, 128, 115, 59, ++ 64, 223, 9, 79, 244, 0, 3, 32, 240, 127, 66, 0, 147, 3, 168, 4, 169, ++ 51, 70, 249, 243, 233, 241, 5, 168, 3, 153, 4, 154, 24, 35, 119, 67, ++ 249, 243, 38, 242, 5, 185, 45, 96, 5, 154, 79, 244, 0, 99, 0, 147, 79, ++ 244, 128, 83, 3, 168, 4, 169, 186, 24, 147, 251, 245, 243, 249, 243, ++ 211, 241, 2, 168, 3, 153, 4, 154, 12, 35, 249, 243, 17, 242, 32, 70, ++ 6, 153, 7, 154, 3, 240, 68, 221, 2, 152, 9, 176, 240, 189, 16, 181, ++ 4, 70, 3, 240, 229, 220, 1, 70, 32, 70, 189, 232, 16, 64, 255, 247, ++ 163, 191, 112, 181, 4, 70, 22, 70, 255, 247, 241, 255, 99, 105, 5, 70, ++ 34, 43, 32, 70, 10, 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, ++ 34, 3, 240, 65, 219, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 204, 98, ++ 3, 240, 137, 218, 4, 35, 3, 96, 214, 248, 100, 54, 79, 244, 122, 112, ++ 219, 178, 181, 251, 243, 245, 104, 67, 112, 189, 112, 181, 4, 70, 14, ++ 70, 3, 240, 115, 218, 0, 33, 5, 70, 32, 70, 3, 240, 188, 221, 49, 70, ++ 2, 70, 32, 70, 255, 247, 204, 255, 41, 70, 6, 70, 32, 70, 3, 240, 178, ++ 221, 48, 70, 112, 189, 255, 247, 232, 191, 55, 181, 4, 70, 255, 247, ++ 181, 255, 79, 244, 0, 97, 106, 70, 1, 171, 5, 70, 32, 70, 3, 240, 176, ++ 221, 0, 34, 19, 70, 32, 70, 4, 33, 255, 247, 9, 251, 0, 244, 127, 64, ++ 3, 10, 0, 185, 27, 96, 181, 251, 243, 245, 32, 70, 157, 232, 6, 0, 3, ++ 240, 220, 220, 40, 70, 62, 189, 112, 181, 4, 70, 14, 70, 3, 240, 59, ++ 218, 0, 33, 5, 70, 32, 70, 3, 240, 132, 221, 49, 70, 2, 70, 32, 70, ++ 255, 247, 126, 252, 32, 70, 255, 247, 140, 248, 99, 105, 6, 70, 34, ++ 43, 32, 70, 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, ++ 3, 240, 215, 218, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 12, 98, 3, ++ 240, 31, 218, 243, 120, 1, 33, 17, 250, 3, 243, 2, 104, 41, 70, 26, ++ 66, 12, 191, 0, 38, 1, 38, 32, 70, 3, 240, 90, 221, 48, 70, 112, 189, ++ 112, 71, 45, 233, 255, 71, 131, 110, 0, 34, 4, 70, 13, 70, 2, 146, 3, ++ 146, 99, 177, 208, 248, 204, 16, 0, 235, 129, 1, 209, 248, 212, 0, 33, ++ 110, 136, 66, 5, 209, 96, 110, 152, 71, 129, 70, 2, 224, 153, 70, 0, ++ 224, 145, 70, 32, 70, 3, 240, 237, 217, 0, 33, 130, 70, 32, 70, 3, 240, ++ 54, 221, 2, 169, 128, 70, 3, 170, 32, 70, 255, 247, 14, 249, 2, 159, ++ 0, 38, 3, 150, 247, 177, 59, 70, 32, 70, 41, 70, 66, 70, 0, 150, 255, ++ 247, 79, 248, 99, 105, 56, 67, 34, 43, 2, 144, 32, 70, 10, 221, 227, ++ 105, 89, 6, 7, 213, 64, 246, 39, 1, 50, 70, 3, 240, 127, 218, 1, 70, ++ 32, 70, 0, 224, 0, 33, 79, 244, 195, 98, 3, 240, 199, 217, 2, 155, 3, ++ 96, 3, 158, 254, 177, 0, 39, 51, 70, 32, 70, 41, 70, 66, 70, 0, 151, ++ 255, 247, 45, 248, 99, 105, 48, 67, 34, 43, 3, 144, 32, 70, 10, 221, ++ 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 58, 70, 3, 240, 93, 218, 1, ++ 70, 32, 70, 0, 224, 0, 33, 64, 242, 28, 98, 3, 240, 165, 217, 3, 155, ++ 3, 96, 41, 70, 66, 70, 32, 70, 255, 247, 229, 251, 32, 70, 81, 70, 3, ++ 240, 226, 220, 227, 110, 91, 177, 212, 248, 204, 32, 4, 235, 130, 2, ++ 210, 248, 212, 16, 34, 110, 145, 66, 2, 209, 96, 110, 73, 70, 152, 71, ++ 189, 232, 255, 135, 0, 33, 247, 247, 223, 184, 247, 247, 101, 185, 0, ++ 32, 112, 71, 16, 181, 4, 70, 8, 70, 17, 70, 26, 70, 247, 247, 30, 252, ++ 16, 177, 35, 104, 1, 51, 35, 96, 16, 189, 0, 0, 16, 181, 0, 34, 12, ++ 70, 253, 243, 229, 241, 160, 185, 10, 75, 27, 104, 139, 177, 26, 120, ++ 122, 177, 218, 137, 148, 66, 12, 216, 24, 70, 253, 247, 97, 255, 32, ++ 177, 5, 75, 26, 104, 1, 50, 26, 96, 16, 189, 4, 75, 26, 104, 1, 50, ++ 26, 96, 16, 189, 116, 7, 0, 0, 8, 111, 4, 0, 12, 111, 4, 0, 56, 181, ++ 4, 70, 13, 70, 34, 177, 131, 104, 19, 177, 192, 104, 0, 34, 152, 71, ++ 9, 75, 26, 104, 43, 70, 7, 224, 217, 120, 17, 185, 33, 104, 1, 57, 33, ++ 96, 155, 138, 82, 248, 35, 48, 0, 43, 245, 209, 40, 70, 189, 232, 56, ++ 64, 247, 247, 14, 189, 32, 7, 0, 0, 16, 181, 4, 70, 8, 70, 247, 247, ++ 95, 252, 16, 177, 35, 104, 1, 51, 35, 96, 16, 189, 8, 74, 3, 70, 16, ++ 181, 16, 104, 10, 70, 7, 224, 212, 120, 20, 185, 28, 104, 1, 52, 28, ++ 96, 146, 138, 80, 248, 34, 32, 0, 42, 245, 209, 8, 70, 16, 189, 32, ++ 7, 0, 0, 8, 74, 3, 70, 16, 181, 16, 104, 10, 70, 7, 224, 212, 120, 20, ++ 185, 28, 104, 1, 60, 28, 96, 146, 138, 80, 248, 34, 32, 0, 42, 245, ++ 209, 8, 70, 16, 189, 32, 7, 0, 0, 3, 126, 43, 177, 64, 105, 208, 241, ++ 1, 0, 56, 191, 0, 32, 112, 71, 1, 32, 112, 71, 112, 181, 3, 105, 205, ++ 28, 37, 240, 3, 5, 157, 66, 4, 70, 14, 70, 18, 216, 0, 104, 3, 240, ++ 42, 219, 225, 104, 50, 70, 0, 35, 255, 247, 102, 255, 80, 177, 227, ++ 104, 91, 25, 227, 96, 35, 105, 93, 27, 99, 105, 37, 97, 1, 51, 99, 97, ++ 112, 189, 0, 32, 112, 189, 75, 104, 65, 104, 195, 243, 20, 3, 139, 66, ++ 9, 211, 129, 104, 139, 66, 6, 210, 67, 105, 18, 177, 1, 51, 67, 97, ++ 112, 71, 1, 59, 67, 97, 112, 71, 0, 0, 1, 75, 3, 235, 192, 0, 112, 71, ++ 20, 111, 4, 0, 1, 75, 3, 235, 192, 0, 112, 71, 56, 111, 4, 0, 45, 233, ++ 248, 67, 4, 70, 13, 70, 22, 70, 153, 70, 3, 240, 176, 216, 167, 110, ++ 128, 70, 111, 177, 212, 248, 204, 48, 4, 235, 131, 3, 211, 248, 212, ++ 32, 35, 110, 154, 66, 3, 209, 96, 110, 184, 71, 7, 70, 0, 224, 0, 39, ++ 32, 70, 0, 33, 3, 240, 233, 219, 29, 185, 0, 245, 160, 96, 4, 48, 1, ++ 224, 0, 245, 161, 96, 5, 104, 62, 177, 3, 104, 35, 234, 6, 6, 6, 96, ++ 3, 104, 67, 234, 9, 3, 3, 96, 32, 70, 65, 70, 3, 240, 212, 219, 227, ++ 110, 91, 177, 212, 248, 204, 32, 4, 235, 130, 2, 210, 248, 212, 16, ++ 34, 110, 145, 66, 2, 209, 96, 110, 57, 70, 152, 71, 40, 70, 189, 232, ++ 248, 131, 16, 181, 12, 70, 19, 70, 4, 33, 34, 70, 189, 232, 16, 64, ++ 255, 247, 187, 184, 16, 181, 12, 70, 19, 70, 2, 33, 34, 70, 189, 232, ++ 16, 64, 255, 247, 178, 184, 16, 181, 12, 70, 19, 70, 6, 33, 34, 70, ++ 189, 232, 16, 64, 255, 247, 169, 184, 45, 233, 240, 65, 133, 110, 4, ++ 70, 15, 70, 22, 70, 109, 177, 208, 248, 204, 48, 0, 235, 131, 3, 211, ++ 248, 212, 32, 3, 110, 154, 66, 3, 209, 64, 110, 168, 71, 5, 70, 0, 224, ++ 0, 37, 32, 70, 3, 240, 66, 216, 128, 70, 71, 185, 32, 70, 57, 70, 58, ++ 70, 59, 70, 255, 247, 130, 255, 0, 240, 1, 6, 21, 224, 0, 46, 79, 240, ++ 1, 2, 12, 191, 51, 70, 19, 70, 20, 191, 0, 39, 79, 244, 128, 39, 79, ++ 240, 0, 1, 32, 70, 255, 247, 112, 255, 32, 70, 2, 33, 79, 244, 128, ++ 34, 59, 70, 255, 247, 112, 248, 32, 70, 65, 70, 3, 240, 107, 219, 227, ++ 110, 91, 177, 212, 248, 204, 32, 4, 235, 130, 2, 210, 248, 212, 16, ++ 34, 110, 145, 66, 2, 209, 96, 110, 41, 70, 152, 71, 48, 70, 189, 232, ++ 240, 129, 112, 71, 0, 33, 8, 181, 10, 70, 11, 70, 255, 247, 77, 255, ++ 0, 240, 1, 0, 8, 189, 1, 32, 112, 71, 112, 181, 6, 70, 255, 247, 250, ++ 255, 216, 177, 0, 37, 40, 70, 255, 247, 57, 255, 3, 104, 19, 177, 64, ++ 104, 152, 71, 40, 177, 1, 53, 237, 178, 4, 45, 243, 209, 1, 36, 0, 224, ++ 4, 70, 48, 70, 255, 247, 221, 255, 160, 66, 6, 208, 48, 70, 1, 33, 34, ++ 70, 189, 232, 112, 64, 255, 247, 133, 191, 112, 189, 3, 75, 24, 112, ++ 24, 177, 3, 75, 26, 104, 1, 50, 26, 96, 112, 71, 52, 111, 4, 0, 88, ++ 111, 4, 0, 16, 181, 4, 70, 0, 32, 255, 247, 239, 255, 32, 70, 161, 109, ++ 255, 247, 248, 250, 32, 177, 1, 32, 189, 232, 16, 64, 255, 247, 229, ++ 191, 16, 189, 1, 75, 24, 120, 112, 71, 0, 191, 52, 111, 4, 0, 248, 181, ++ 4, 70, 255, 247, 182, 255, 0, 40, 55, 208, 32, 70, 255, 247, 225, 255, ++ 165, 110, 109, 177, 212, 248, 204, 48, 4, 235, 131, 3, 211, 248, 212, ++ 32, 35, 110, 154, 66, 3, 209, 96, 110, 168, 71, 5, 70, 0, 224, 0, 37, ++ 32, 70, 2, 240, 160, 223, 7, 70, 255, 247, 219, 255, 88, 177, 0, 38, ++ 48, 70, 255, 247, 212, 254, 3, 104, 11, 177, 64, 104, 152, 71, 1, 54, ++ 246, 178, 4, 46, 244, 209, 32, 70, 57, 70, 3, 240, 218, 218, 227, 110, ++ 91, 177, 212, 248, 204, 32, 4, 235, 130, 2, 210, 248, 212, 16, 34, 110, ++ 145, 66, 2, 209, 96, 110, 41, 70, 152, 71, 248, 189, 0, 0, 11, 75, 16, ++ 181, 26, 104, 28, 70, 144, 66, 4, 209, 90, 104, 145, 66, 1, 209, 24, ++ 70, 16, 189, 99, 105, 5, 74, 152, 66, 6, 209, 144, 105, 20, 50, 129, ++ 66, 12, 191, 16, 70, 0, 32, 16, 189, 0, 32, 16, 189, 216, 156, 5, 0, ++ 79, 244, 64, 34, 56, 181, 64, 246, 12, 65, 19, 70, 5, 70, 3, 240, 99, ++ 216, 0, 34, 19, 70, 64, 246, 12, 65, 40, 70, 3, 240, 92, 216, 0, 34, ++ 19, 70, 64, 246, 12, 65, 40, 70, 3, 240, 85, 216, 64, 246, 3, 2, 40, ++ 70, 64, 246, 12, 65, 19, 70, 3, 240, 77, 216, 10, 36, 0, 34, 40, 70, ++ 64, 246, 12, 65, 19, 70, 3, 240, 69, 216, 1, 60, 246, 209, 35, 70, 64, ++ 246, 12, 65, 64, 246, 3, 2, 40, 70, 3, 240, 59, 216, 34, 70, 35, 70, ++ 64, 246, 12, 65, 40, 70, 3, 240, 52, 216, 34, 70, 35, 70, 64, 246, 12, ++ 65, 40, 70, 3, 240, 45, 216, 35, 70, 40, 70, 64, 246, 12, 65, 79, 244, ++ 64, 34, 3, 240, 37, 216, 79, 244, 78, 100, 33, 70, 0, 35, 40, 70, 79, ++ 240, 255, 50, 4, 52, 3, 240, 27, 216, 180, 245, 86, 111, 244, 209, 56, ++ 189, 55, 181, 21, 70, 64, 246, 60, 98, 145, 66, 12, 70, 6, 216, 0, 147, ++ 0, 33, 34, 70, 43, 70, 2, 240, 4, 223, 0, 224, 0, 32, 62, 189, 0, 0, ++ 55, 181, 4, 70, 255, 247, 150, 255, 20, 35, 116, 34, 64, 246, 12, 65, ++ 32, 70, 2, 240, 251, 223, 1, 33, 4, 34, 32, 70, 3, 240, 122, 216, 4, ++ 33, 1, 34, 32, 70, 3, 240, 117, 216, 16, 33, 0, 35, 32, 70, 10, 70, ++ 3, 240, 135, 216, 148, 248, 85, 48, 32, 70, 27, 7, 1, 213, 0, 33, 0, ++ 224, 2, 33, 4, 34, 3, 240, 100, 216, 1, 35, 0, 147, 0, 33, 32, 70, 64, ++ 246, 28, 98, 79, 240, 255, 51, 3, 240, 16, 216, 148, 248, 85, 80, 21, ++ 240, 8, 5, 14, 208, 33, 35, 0, 147, 0, 33, 79, 240, 255, 51, 32, 70, ++ 64, 246, 24, 98, 3, 240, 1, 216, 83, 75, 32, 70, 0, 147, 0, 33, 14, ++ 224, 17, 35, 0, 147, 41, 70, 79, 240, 255, 51, 32, 70, 64, 246, 24, ++ 98, 2, 240, 242, 223, 65, 242, 2, 19, 0, 147, 32, 70, 41, 70, 64, 246, ++ 68, 66, 79, 240, 255, 51, 2, 240, 231, 223, 148, 248, 85, 48, 32, 70, ++ 93, 7, 79, 244, 94, 97, 79, 240, 255, 50, 1, 213, 245, 35, 0, 224, 243, ++ 35, 2, 240, 159, 223, 0, 35, 32, 70, 64, 246, 248, 81, 79, 240, 255, ++ 50, 2, 240, 151, 223, 0, 35, 32, 70, 64, 246, 228, 81, 79, 240, 255, ++ 50, 2, 240, 143, 223, 8, 35, 32, 70, 64, 246, 236, 81, 79, 240, 255, ++ 50, 2, 240, 135, 223, 0, 35, 32, 70, 64, 246, 232, 81, 79, 240, 255, ++ 50, 2, 240, 127, 223, 219, 35, 32, 70, 79, 244, 93, 97, 79, 240, 255, ++ 50, 2, 240, 119, 223, 12, 34, 0, 35, 32, 70, 64, 246, 84, 65, 2, 240, ++ 112, 223, 40, 75, 0, 33, 0, 147, 32, 70, 64, 246, 188, 82, 79, 240, ++ 255, 51, 2, 240, 160, 223, 36, 75, 1, 33, 0, 147, 32, 70, 64, 246, 188, ++ 82, 79, 240, 255, 51, 2, 240, 150, 223, 32, 75, 2, 33, 0, 147, 32, 70, ++ 64, 246, 188, 82, 79, 240, 255, 51, 2, 240, 140, 223, 1, 34, 19, 70, ++ 32, 70, 64, 246, 36, 97, 2, 240, 75, 223, 64, 246, 255, 115, 0, 147, ++ 0, 33, 23, 77, 32, 70, 64, 246, 180, 82, 79, 240, 255, 51, 2, 240, 121, ++ 223, 0, 33, 32, 70, 64, 246, 184, 82, 79, 240, 255, 51, 0, 149, 2, 240, ++ 112, 223, 75, 246, 152, 35, 0, 147, 1, 33, 32, 70, 64, 246, 184, 82, ++ 79, 240, 255, 51, 2, 240, 101, 223, 32, 70, 79, 244, 92, 97, 79, 240, ++ 255, 50, 43, 70, 3, 176, 189, 232, 48, 64, 2, 240, 32, 159, 2, 0, 17, ++ 0, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 16, 50, 84, 118, ++ 19, 181, 12, 70, 2, 185, 73, 177, 8, 73, 19, 177, 11, 104, 28, 64, 3, ++ 224, 11, 104, 28, 67, 36, 234, 3, 4, 34, 64, 0, 146, 0, 33, 112, 34, ++ 35, 70, 2, 240, 252, 221, 28, 189, 0, 191, 8, 8, 0, 0, 19, 181, 20, ++ 70, 66, 105, 10, 42, 15, 221, 41, 177, 1, 41, 5, 208, 2, 41, 10, 209, ++ 132, 34, 2, 224, 120, 34, 0, 224, 124, 34, 0, 147, 0, 33, 35, 70, 2, ++ 240, 228, 221, 1, 224, 79, 240, 255, 48, 28, 189, 45, 233, 240, 65, ++ 4, 70, 2, 240, 151, 223, 0, 33, 10, 70, 11, 70, 7, 70, 32, 70, 255, ++ 247, 196, 255, 0, 33, 10, 70, 11, 70, 6, 70, 32, 70, 255, 247, 213, ++ 255, 0, 34, 5, 70, 2, 33, 32, 70, 19, 70, 255, 247, 206, 255, 212, 248, ++ 120, 128, 21, 224, 216, 248, 8, 48, 131, 177, 152, 248, 4, 32, 0, 42, ++ 216, 248, 12, 32, 12, 191, 40, 70, 56, 70, 0, 234, 2, 0, 18, 208, 50, ++ 64, 144, 66, 2, 208, 216, 248, 0, 16, 152, 71, 216, 248, 16, 128, 184, ++ 241, 0, 15, 230, 209, 32, 70, 65, 70, 42, 70, 43, 70, 189, 232, 240, ++ 65, 255, 247, 170, 191, 0, 40, 237, 209, 239, 231, 79, 244, 128, 48, ++ 112, 71, 192, 105, 0, 240, 8, 0, 112, 71, 115, 181, 4, 70, 13, 70, 3, ++ 240, 61, 216, 24, 185, 32, 70, 255, 247, 243, 255, 72, 179, 0, 45, 20, ++ 191, 79, 244, 128, 115, 0, 35, 0, 147, 32, 70, 0, 33, 79, 244, 240, ++ 114, 79, 244, 128, 115, 2, 240, 128, 221, 213, 177, 64, 242, 221, 86, ++ 2, 224, 10, 32, 252, 243, 69, 243, 0, 37, 43, 70, 32, 70, 41, 70, 79, ++ 244, 240, 114, 0, 149, 2, 240, 112, 221, 195, 1, 1, 212, 1, 62, 239, ++ 209, 0, 33, 32, 70, 79, 244, 240, 114, 11, 70, 0, 149, 2, 240, 100, ++ 221, 124, 189, 56, 181, 0, 37, 29, 112, 209, 248, 204, 48, 79, 244, ++ 0, 97, 19, 96, 42, 70, 4, 70, 3, 240, 147, 216, 5, 70, 56, 177, 208, ++ 248, 224, 49, 218, 1, 3, 212, 32, 70, 1, 33, 255, 247, 181, 255, 40, ++ 70, 56, 189, 0, 0, 115, 181, 131, 105, 0, 37, 154, 0, 4, 70, 173, 248, ++ 6, 80, 72, 213, 79, 244, 0, 97, 42, 70, 208, 248, 204, 96, 3, 240, 119, ++ 216, 0, 40, 63, 208, 99, 105, 34, 43, 216, 191, 192, 248, 104, 81, 192, ++ 248, 100, 81, 192, 248, 96, 81, 99, 105, 34, 43, 3, 220, 28, 75, 192, ++ 248, 68, 49, 5, 224, 1, 35, 192, 248, 72, 49, 255, 35, 192, 248, 76, ++ 49, 99, 105, 34, 43, 79, 240, 0, 3, 6, 220, 192, 248, 128, 49, 192, ++ 248, 124, 49, 192, 248, 120, 49, 3, 224, 192, 248, 116, 49, 192, 248, ++ 112, 49, 49, 70, 32, 70, 3, 240, 89, 216, 32, 70, 13, 241, 6, 1, 3, ++ 240, 138, 218, 144, 185, 189, 248, 6, 0, 128, 177, 99, 105, 32, 70, ++ 34, 43, 217, 191, 79, 244, 128, 33, 10, 70, 6, 73, 64, 34, 0, 35, 2, ++ 240, 92, 221, 2, 224, 79, 240, 255, 48, 0, 224, 0, 32, 124, 189, 0, ++ 0, 251, 191, 64, 0, 85, 85, 115, 181, 4, 70, 2, 240, 150, 223, 24, 185, ++ 32, 70, 255, 247, 76, 255, 96, 179, 32, 70, 33, 70, 106, 70, 13, 241, ++ 7, 3, 255, 247, 125, 255, 6, 70, 192, 177, 64, 242, 45, 21, 2, 224, ++ 10, 32, 252, 243, 164, 242, 214, 248, 212, 49, 24, 7, 6, 212, 1, 61, ++ 246, 209, 3, 224, 10, 32, 252, 243, 154, 242, 1, 224, 64, 242, 45, 21, ++ 214, 248, 212, 49, 89, 7, 1, 213, 1, 61, 243, 209, 32, 70, 0, 33, 255, ++ 247, 41, 255, 157, 248, 7, 48, 27, 185, 32, 70, 0, 153, 3, 240, 4, 216, ++ 124, 189, 16, 181, 4, 70, 252, 243, 37, 244, 32, 70, 255, 247, 194, ++ 255, 1, 32, 16, 189, 240, 181, 133, 176, 4, 70, 13, 70, 23, 70, 255, ++ 247, 13, 255, 0, 40, 0, 240, 148, 128, 166, 110, 110, 177, 212, 248, ++ 204, 48, 4, 235, 131, 3, 211, 248, 212, 32, 35, 110, 154, 66, 3, 209, ++ 96, 110, 176, 71, 6, 70, 0, 224, 0, 38, 32, 70, 33, 70, 2, 170, 13, ++ 241, 15, 3, 255, 247, 44, 255, 0, 40, 99, 208, 8, 47, 97, 216, 223, ++ 232, 7, 240, 5, 20, 28, 39, 53, 64, 74, 85, 13, 0, 0, 149, 32, 70, 0, ++ 33, 79, 244, 156, 114, 79, 240, 255, 51, 78, 224, 0, 33, 0, 145, 32, ++ 70, 79, 244, 156, 114, 11, 70, 71, 224, 79, 240, 255, 51, 0, 147, 32, ++ 70, 0, 33, 79, 244, 154, 114, 63, 224, 0, 33, 32, 70, 79, 244, 236, ++ 114, 11, 70, 0, 145, 2, 240, 101, 220, 0, 240, 1, 5, 57, 224, 37, 177, ++ 32, 35, 0, 147, 32, 70, 0, 33, 3, 224, 2, 35, 0, 147, 32, 70, 41, 70, ++ 79, 244, 232, 114, 34, 35, 38, 224, 0, 33, 32, 70, 79, 244, 154, 114, ++ 11, 70, 0, 145, 2, 240, 76, 220, 192, 243, 192, 37, 32, 224, 0, 33, ++ 32, 70, 79, 244, 224, 114, 11, 70, 0, 145, 2, 240, 65, 220, 197, 178, ++ 22, 224, 0, 33, 32, 70, 79, 244, 154, 114, 11, 70, 0, 145, 2, 240, 55, ++ 220, 192, 243, 64, 37, 11, 224, 237, 178, 0, 149, 32, 70, 0, 33, 79, ++ 244, 224, 114, 255, 35, 2, 240, 43, 220, 5, 70, 0, 224, 1, 37, 157, ++ 248, 15, 48, 27, 185, 32, 70, 2, 153, 2, 240, 107, 223, 227, 110, 107, ++ 177, 212, 248, 204, 32, 4, 235, 130, 2, 210, 248, 212, 16, 34, 110, ++ 145, 66, 4, 209, 96, 110, 49, 70, 152, 71, 0, 224, 5, 70, 40, 70, 5, ++ 176, 240, 189, 67, 105, 45, 233, 247, 67, 34, 43, 5, 70, 14, 70, 64, ++ 243, 153, 128, 25, 185, 255, 247, 103, 254, 64, 185, 145, 224, 2, 240, ++ 169, 222, 0, 40, 0, 240, 141, 128, 7, 46, 0, 242, 140, 128, 40, 70, ++ 79, 244, 0, 97, 0, 34, 213, 248, 204, 144, 2, 240, 45, 223, 4, 70, 0, ++ 40, 0, 240, 129, 128, 3, 46, 3, 208, 40, 70, 1, 33, 255, 247, 79, 254, ++ 212, 248, 48, 49, 35, 240, 4, 3, 196, 248, 48, 49, 1, 35, 158, 66, 196, ++ 248, 48, 49, 4, 217, 4, 46, 12, 191, 13, 35, 9, 35, 0, 224, 13, 35, ++ 3, 46, 196, 248, 48, 49, 79, 208, 212, 248, 48, 49, 1, 46, 35, 240, ++ 1, 3, 196, 248, 48, 49, 1, 217, 4, 46, 69, 209, 79, 240, 255, 8, 0, ++ 33, 79, 244, 226, 114, 67, 70, 40, 70, 205, 248, 0, 128, 2, 240, 189, ++ 219, 40, 70, 2, 240, 34, 219, 79, 244, 225, 49, 255, 247, 54, 252, 7, ++ 70, 136, 177, 131, 104, 0, 33, 0, 147, 79, 244, 226, 114, 67, 70, 40, ++ 70, 2, 240, 171, 219, 59, 105, 40, 70, 0, 147, 0, 33, 79, 244, 238, ++ 114, 67, 70, 2, 240, 162, 219, 1, 35, 0, 147, 0, 33, 255, 35, 79, 244, ++ 198, 114, 40, 70, 2, 240, 153, 219, 24, 73, 42, 70, 40, 70, 66, 240, ++ 206, 251, 40, 35, 0, 147, 0, 33, 79, 244, 230, 114, 255, 35, 40, 70, ++ 2, 240, 139, 219, 129, 35, 0, 147, 40, 70, 0, 33, 79, 244, 232, 114, ++ 255, 35, 2, 240, 130, 219, 212, 248, 48, 49, 40, 70, 35, 240, 112, 3, ++ 67, 234, 6, 22, 196, 248, 48, 97, 212, 248, 48, 49, 73, 70, 35, 240, ++ 8, 3, 196, 248, 48, 49, 2, 240, 186, 222, 2, 224, 4, 70, 0, 224, 0, ++ 36, 32, 70, 189, 232, 254, 131, 0, 191, 231, 188, 0, 0, 195, 105, 16, ++ 181, 91, 7, 4, 70, 19, 213, 255, 247, 249, 251, 79, 244, 127, 66, 19, ++ 70, 64, 246, 116, 81, 32, 70, 2, 240, 93, 220, 32, 70, 255, 247, 84, ++ 252, 32, 70, 64, 246, 84, 65, 16, 34, 0, 35, 2, 240, 83, 220, 0, 32, ++ 16, 189, 56, 181, 4, 70, 2, 240, 67, 219, 79, 244, 0, 97, 5, 70, 0, ++ 34, 32, 70, 2, 240, 124, 222, 0, 35, 192, 248, 64, 60, 208, 248, 0, ++ 62, 41, 70, 35, 240, 127, 67, 35, 244, 112, 3, 67, 240, 136, 83, 67, ++ 244, 128, 19, 192, 248, 0, 62, 1, 35, 192, 248, 64, 60, 79, 240, 17, ++ 51, 192, 248, 0, 62, 131, 109, 3, 240, 31, 3, 131, 101, 195, 109, 3, ++ 240, 31, 3, 195, 101, 131, 110, 3, 240, 31, 3, 131, 102, 195, 110, 3, ++ 240, 31, 3, 195, 102, 32, 70, 189, 232, 56, 64, 2, 240, 94, 158, 112, ++ 71, 16, 181, 4, 70, 255, 247, 0, 251, 144, 177, 0, 34, 8, 33, 19, 70, ++ 32, 70, 254, 247, 191, 251, 130, 7, 10, 213, 32, 70, 8, 33, 2, 34, 0, ++ 35, 254, 247, 183, 251, 32, 70, 189, 232, 16, 64, 254, 247, 232, 187, ++ 16, 189, 45, 233, 240, 65, 7, 70, 14, 70, 21, 70, 28, 70, 2, 240, 182, ++ 220, 56, 70, 49, 70, 42, 70, 35, 70, 189, 232, 240, 65, 2, 240, 200, ++ 156, 0, 34, 79, 246, 255, 113, 19, 70, 2, 240, 134, 156, 45, 233, 248, ++ 67, 153, 70, 45, 75, 143, 137, 21, 70, 27, 104, 138, 138, 13, 47, 12, ++ 70, 142, 104, 83, 248, 34, 128, 70, 221, 50, 123, 115, 123, 67, 234, ++ 2, 35, 179, 245, 192, 111, 3, 219, 6, 241, 12, 3, 0, 33, 12, 224, 21, ++ 47, 57, 221, 34, 72, 6, 241, 14, 1, 6, 34, 246, 247, 142, 249, 0, 40, ++ 49, 209, 6, 241, 20, 3, 1, 33, 24, 120, 90, 120, 66, 234, 0, 34, 178, ++ 245, 1, 79, 8, 209, 152, 29, 242, 25, 144, 66, 35, 216, 24, 121, 90, ++ 121, 4, 51, 66, 234, 0, 34, 64, 246, 6, 0, 130, 66, 26, 209, 160, 137, ++ 184, 241, 0, 15, 10, 208, 14, 40, 184, 248, 12, 32, 2, 209, 216, 248, ++ 8, 48, 6, 224, 15, 56, 26, 40, 12, 217, 191, 24, 2, 51, 246, 26, 186, ++ 25, 28, 42, 0, 220, 9, 209, 43, 96, 28, 32, 137, 248, 0, 16, 189, 232, ++ 248, 131, 79, 240, 255, 48, 189, 232, 248, 131, 111, 240, 1, 0, 189, ++ 232, 248, 131, 0, 191, 32, 7, 0, 0, 192, 179, 135, 0, 115, 181, 4, 34, ++ 5, 70, 1, 168, 14, 70, 246, 247, 89, 249, 1, 152, 112, 177, 0, 36, 160, ++ 28, 5, 235, 128, 0, 49, 70, 4, 34, 246, 247, 60, 249, 32, 177, 1, 52, ++ 8, 44, 244, 209, 0, 32, 0, 224, 1, 32, 124, 189, 0, 0, 3, 104, 45, 233, ++ 247, 79, 1, 42, 20, 191, 79, 240, 42, 8, 79, 240, 50, 8, 5, 70, 14, ++ 70, 88, 104, 65, 70, 146, 70, 255, 247, 228, 248, 7, 70, 64, 185, 43, ++ 104, 5, 32, 27, 104, 211, 248, 136, 48, 26, 109, 1, 50, 26, 101, 109, ++ 224, 6, 241, 14, 11, 4, 34, 132, 104, 89, 70, 1, 168, 246, 247, 35, ++ 249, 1, 154, 74, 246, 254, 19, 18, 186, 179, 235, 18, 79, 7, 208, 6, ++ 241, 8, 9, 72, 70, 47, 73, 6, 34, 246, 247, 2, 249, 16, 185, 32, 70, ++ 45, 73, 1, 224, 32, 70, 73, 70, 6, 34, 5, 241, 40, 9, 246, 247, 10, ++ 249, 160, 29, 73, 70, 6, 34, 246, 247, 5, 249, 186, 241, 0, 15, 14, ++ 208, 0, 35, 35, 115, 132, 248, 13, 128, 4, 241, 14, 0, 34, 73, 6, 34, ++ 246, 247, 248, 248, 8, 35, 35, 117, 6, 35, 99, 117, 3, 224, 8, 35, 35, ++ 115, 6, 35, 99, 115, 168, 241, 28, 8, 68, 68, 49, 70, 6, 34, 32, 70, ++ 246, 247, 231, 248, 0, 35, 163, 113, 2, 35, 227, 113, 73, 70, 6, 34, ++ 4, 241, 8, 0, 246, 247, 221, 248, 6, 241, 24, 1, 4, 34, 4, 241, 14, ++ 0, 246, 247, 214, 248, 6, 241, 8, 1, 6, 34, 4, 241, 18, 0, 246, 247, ++ 207, 248, 89, 70, 4, 34, 4, 241, 24, 0, 246, 247, 201, 248, 213, 248, ++ 92, 49, 40, 104, 1, 51, 197, 248, 92, 49, 57, 70, 213, 248, 104, 33, ++ 11, 240, 164, 249, 1, 32, 189, 232, 254, 143, 0, 191, 248, 125, 135, ++ 0, 236, 125, 135, 0, 192, 179, 135, 0, 45, 233, 240, 67, 134, 77, 135, ++ 176, 43, 104, 4, 70, 219, 7, 64, 241, 0, 129, 3, 104, 0, 43, 0, 240, ++ 252, 128, 1, 170, 13, 241, 23, 3, 255, 247, 224, 254, 0, 40, 192, 242, ++ 244, 128, 148, 248, 100, 49, 1, 43, 0, 240, 242, 128, 1, 153, 3, 170, ++ 14, 49, 32, 70, 7, 240, 196, 217, 1, 153, 2, 170, 24, 49, 7, 70, 32, ++ 70, 7, 240, 189, 217, 1, 153, 129, 70, 14, 49, 32, 70, 255, 247, 39, ++ 255, 1, 153, 128, 70, 24, 49, 32, 70, 255, 247, 33, 255, 0, 47, 20, ++ 191, 8, 38, 0, 38, 185, 241, 0, 15, 20, 191, 79, 240, 4, 9, 79, 240, ++ 0, 9, 184, 241, 0, 15, 20, 191, 79, 240, 2, 8, 79, 240, 0, 8, 1, 153, ++ 78, 68, 70, 68, 14, 49, 0, 40, 24, 191, 1, 54, 4, 34, 4, 168, 246, 247, ++ 100, 248, 1, 153, 203, 136, 179, 245, 128, 127, 104, 209, 212, 248, ++ 76, 49, 4, 241, 40, 0, 1, 51, 196, 248, 76, 49, 253, 247, 146, 248, ++ 0, 40, 64, 240, 166, 128, 12, 46, 0, 242, 168, 128, 223, 232, 6, 240, ++ 62, 7, 166, 166, 65, 166, 166, 166, 47, 71, 166, 166, 47, 0, 1, 154, ++ 32, 70, 2, 241, 14, 1, 8, 50, 7, 240, 206, 217, 43, 104, 26, 7, 5, 213, ++ 32, 70, 1, 153, 157, 248, 23, 32, 255, 247, 241, 254, 4, 157, 0, 45, ++ 64, 240, 139, 128, 1, 153, 4, 34, 1, 241, 14, 0, 24, 49, 246, 247, 44, ++ 248, 1, 152, 6, 34, 8, 48, 67, 73, 246, 247, 38, 248, 32, 70, 1, 153, ++ 157, 248, 23, 32, 255, 247, 218, 254, 86, 224, 32, 70, 1, 153, 7, 240, ++ 127, 217, 1, 40, 112, 208, 1, 153, 4, 34, 1, 241, 14, 0, 24, 49, 245, ++ 247, 255, 255, 0, 40, 104, 208, 43, 104, 155, 7, 100, 212, 212, 248, ++ 80, 49, 1, 51, 196, 248, 80, 49, 87, 224, 32, 70, 1, 153, 7, 240, 103, ++ 217, 1, 40, 88, 208, 40, 104, 16, 240, 8, 0, 85, 208, 32, 70, 1, 153, ++ 157, 248, 23, 32, 255, 247, 177, 254, 78, 224, 179, 245, 0, 127, 71, ++ 209, 212, 248, 84, 49, 1, 51, 196, 248, 84, 49, 12, 46, 67, 216, 223, ++ 232, 6, 240, 7, 18, 66, 66, 66, 66, 59, 66, 36, 36, 66, 66, 49, 0, 4, ++ 154, 74, 246, 254, 19, 18, 186, 179, 235, 18, 79, 51, 209, 43, 104, ++ 152, 7, 48, 212, 35, 224, 1, 241, 18, 0, 6, 34, 4, 241, 40, 1, 245, ++ 247, 190, 255, 5, 70, 48, 187, 1, 154, 32, 70, 2, 241, 14, 1, 8, 50, ++ 7, 240, 86, 217, 40, 70, 30, 224, 32, 70, 7, 240, 39, 217, 1, 40, 24, ++ 208, 1, 154, 32, 70, 2, 241, 14, 1, 8, 50, 7, 240, 72, 217, 16, 224, ++ 32, 70, 7, 240, 26, 217, 1, 40, 11, 208, 212, 248, 88, 49, 1, 51, 196, ++ 248, 88, 49, 4, 32, 5, 224, 5, 32, 3, 224, 79, 240, 255, 48, 0, 224, ++ 0, 32, 7, 176, 189, 232, 240, 131, 84, 8, 0, 0, 248, 125, 135, 0, 45, ++ 233, 240, 65, 5, 70, 240, 177, 208, 248, 92, 50, 251, 177, 0, 36, 213, ++ 248, 92, 114, 102, 1, 23, 235, 6, 8, 14, 208, 184, 89, 96, 177, 254, ++ 247, 43, 255, 0, 33, 200, 248, 4, 16, 185, 81, 200, 248, 8, 16, 8, 241, ++ 12, 0, 16, 34, 247, 243, 3, 243, 1, 52, 10, 44, 231, 209, 0, 32, 189, ++ 232, 240, 129, 79, 240, 255, 48, 189, 232, 240, 129, 79, 240, 255, 48, ++ 189, 232, 240, 129, 0, 0, 0, 72, 112, 71, 240, 98, 4, 0, 139, 124, 138, ++ 104, 210, 24, 138, 96, 138, 137, 211, 26, 139, 129, 112, 71, 112, 181, ++ 145, 104, 136, 137, 4, 10, 68, 234, 0, 32, 0, 178, 176, 245, 0, 111, ++ 5, 209, 200, 125, 6, 40, 10, 208, 17, 40, 50, 209, 7, 224, 26, 76, 160, ++ 66, 46, 209, 8, 125, 6, 40, 1, 208, 17, 40, 43, 209, 76, 136, 99, 185, ++ 10, 136, 20, 67, 138, 136, 20, 67, 164, 178, 36, 177, 11, 120, 3, 240, ++ 1, 3, 131, 240, 1, 3, 216, 178, 112, 189, 152, 104, 69, 136, 6, 136, ++ 108, 64, 13, 136, 128, 136, 137, 136, 117, 64, 44, 67, 65, 64, 12, 67, ++ 164, 178, 84, 185, 208, 137, 219, 137, 0, 240, 7, 0, 3, 240, 7, 3, 195, ++ 26, 88, 66, 64, 235, 3, 0, 0, 224, 0, 32, 192, 178, 112, 189, 0, 32, ++ 112, 189, 0, 32, 112, 189, 221, 134, 255, 255, 0, 32, 112, 71, 19, 181, ++ 195, 104, 4, 70, 147, 248, 172, 0, 56, 177, 2, 170, 0, 35, 66, 248, ++ 4, 61, 160, 104, 1, 33, 30, 240, 136, 248, 227, 104, 147, 248, 172, ++ 48, 83, 177, 48, 177, 0, 33, 4, 241, 64, 0, 10, 70, 251, 243, 141, 242, ++ 2, 224, 160, 104, 73, 240, 61, 223, 28, 189, 16, 181, 12, 70, 65, 177, ++ 139, 104, 35, 185, 192, 111, 9, 104, 6, 240, 71, 219, 160, 96, 160, ++ 104, 16, 189, 192, 111, 16, 189, 45, 233, 240, 79, 140, 105, 133, 176, ++ 35, 105, 21, 70, 153, 66, 7, 208, 209, 248, 44, 144, 185, 241, 0, 15, ++ 4, 208, 217, 248, 0, 160, 2, 224, 79, 240, 0, 9, 202, 70, 166, 104, ++ 81, 70, 48, 70, 26, 240, 72, 248, 98, 104, 2, 144, 146, 249, 62, 48, ++ 115, 177, 150, 248, 33, 50, 11, 177, 131, 121, 107, 177, 150, 248, 34, ++ 50, 75, 185, 146, 248, 69, 48, 211, 241, 1, 3, 56, 191, 0, 35, 3, 224, ++ 1, 33, 1, 145, 1, 224, 0, 35, 1, 147, 0, 38, 55, 70, 179, 70, 176, 70, ++ 41, 70, 98, 224, 59, 75, 202, 138, 27, 104, 83, 248, 34, 48, 3, 147, ++ 0, 35, 203, 130, 99, 104, 88, 105, 254, 247, 167, 254, 5, 70, 41, 70, ++ 32, 70, 255, 247, 58, 255, 99, 104, 147, 248, 46, 48, 131, 177, 32, ++ 70, 73, 70, 255, 247, 162, 255, 88, 177, 41, 70, 6, 240, 48, 220, 2, ++ 40, 6, 209, 99, 104, 41, 70, 88, 105, 1, 34, 254, 247, 102, 254, 59, ++ 224, 99, 104, 147, 249, 62, 48, 0, 43, 42, 208, 1, 153, 129, 177, 32, ++ 70, 2, 153, 42, 70, 59, 70, 255, 247, 32, 255, 131, 70, 104, 177, 235, ++ 137, 67, 244, 128, 83, 235, 129, 54, 177, 43, 136, 243, 130, 46, 70, ++ 4, 224, 221, 248, 4, 176, 1, 224, 46, 70, 47, 70, 143, 177, 3, 153, ++ 17, 177, 187, 241, 0, 15, 24, 209, 57, 70, 160, 104, 82, 70, 10, 240, ++ 83, 255, 0, 40, 12, 191, 7, 70, 0, 39, 62, 70, 24, 191, 79, 240, 1, ++ 8, 187, 241, 0, 15, 8, 209, 160, 104, 41, 70, 82, 70, 10, 240, 67, 255, ++ 0, 40, 24, 191, 79, 240, 1, 8, 3, 153, 0, 41, 154, 209, 99, 104, 147, ++ 249, 62, 48, 75, 177, 71, 177, 160, 104, 57, 70, 82, 70, 10, 240, 50, ++ 255, 0, 40, 24, 191, 79, 240, 1, 8, 64, 70, 5, 176, 189, 232, 240, 143, ++ 32, 7, 0, 0, 45, 233, 248, 67, 67, 104, 23, 70, 138, 104, 12, 70, 145, ++ 248, 35, 128, 73, 104, 94, 105, 34, 240, 127, 67, 193, 243, 20, 1, 35, ++ 244, 96, 3, 91, 26, 3, 43, 46, 216, 180, 248, 12, 144, 48, 70, 9, 241, ++ 4, 1, 254, 247, 214, 253, 5, 70, 48, 185, 33, 70, 48, 70, 1, 34, 254, ++ 247, 241, 253, 44, 70, 44, 224, 195, 137, 226, 137, 35, 240, 7, 3, 27, ++ 4, 2, 240, 7, 2, 27, 12, 19, 67, 195, 129, 226, 137, 161, 104, 210, ++ 6, 76, 191, 67, 240, 16, 3, 35, 240, 16, 3, 195, 129, 128, 104, 74, ++ 70, 4, 48, 245, 247, 7, 254, 33, 70, 48, 70, 1, 34, 254, 247, 210, 253, ++ 44, 70, 4, 224, 163, 137, 4, 58, 4, 51, 162, 96, 163, 129, 163, 104, ++ 0, 33, 1, 34, 25, 112, 90, 112, 131, 248, 2, 128, 217, 112, 58, 112, ++ 32, 70, 189, 232, 248, 131, 0, 0, 45, 233, 243, 71, 31, 70, 3, 105, ++ 5, 70, 211, 248, 36, 128, 138, 70, 145, 70, 184, 241, 0, 15, 47, 208, ++ 68, 32, 254, 247, 121, 253, 4, 70, 0, 40, 42, 208, 68, 34, 0, 33, 4, ++ 241, 20, 6, 247, 243, 86, 241, 102, 96, 39, 96, 255, 247, 94, 254, 107, ++ 104, 186, 241, 2, 15, 96, 98, 229, 98, 205, 248, 0, 144, 12, 191, 16, ++ 74, 17, 74, 79, 240, 16, 1, 219, 104, 48, 70, 247, 243, 168, 241, 14, ++ 75, 36, 100, 27, 104, 64, 70, 91, 104, 49, 70, 152, 71, 0, 40, 10, 221, ++ 120, 113, 232, 111, 57, 70, 6, 240, 4, 218, 160, 96, 0, 224, 68, 70, ++ 32, 70, 189, 232, 252, 135, 32, 70, 254, 247, 72, 253, 0, 36, 247, 231, ++ 0, 191, 244, 49, 4, 0, 39, 56, 136, 0, 188, 7, 0, 0, 56, 181, 4, 70, ++ 99, 104, 128, 104, 27, 126, 203, 185, 5, 240, 220, 253, 5, 70, 32, 185, ++ 212, 248, 128, 0, 7, 240, 114, 220, 5, 70, 245, 247, 21, 255, 99, 104, ++ 211, 248, 152, 16, 89, 177, 11, 120, 75, 177, 6, 75, 0, 34, 24, 104, ++ 252, 247, 216, 252, 32, 70, 13, 240, 19, 217, 0, 224, 0, 37, 40, 70, ++ 56, 189, 0, 191, 252, 109, 4, 0, 31, 181, 8, 74, 3, 70, 0, 146, 7, 74, ++ 8, 70, 1, 146, 7, 74, 7, 73, 18, 104, 2, 146, 26, 104, 6, 75, 247, 243, ++ 101, 243, 5, 176, 0, 189, 0, 191, 57, 50, 4, 0, 211, 22, 4, 0, 0, 110, ++ 4, 0, 10, 50, 4, 0, 45, 50, 4, 0, 8, 177, 208, 248, 136, 0, 112, 71, ++ 0, 32, 112, 71, 45, 233, 240, 79, 4, 70, 208, 248, 136, 0, 21, 70, 3, ++ 136, 139, 176, 94, 25, 120, 46, 10, 120, 0, 243, 180, 128, 4, 42, 64, ++ 240, 165, 128, 162, 104, 146, 248, 0, 39, 0, 42, 0, 240, 159, 128, 209, ++ 248, 2, 48, 30, 14, 218, 178, 27, 10, 155, 178, 7, 147, 19, 35, 11, ++ 112, 75, 120, 5, 146, 1, 51, 75, 112, 148, 248, 140, 48, 6, 150, 79, ++ 234, 211, 12, 28, 240, 1, 12, 11, 208, 207, 136, 79, 240, 8, 9, 79, ++ 234, 87, 56, 63, 5, 8, 240, 1, 8, 63, 13, 205, 248, 16, 144, 3, 224, ++ 6, 34, 103, 70, 224, 70, 4, 146, 212, 248, 136, 0, 155, 8, 6, 136, 3, ++ 240, 1, 3, 0, 34, 9, 147, 2, 150, 147, 70, 19, 70, 162, 70, 1, 145, ++ 0, 149, 82, 224, 196, 24, 164, 120, 19, 44, 73, 209, 221, 248, 16, 144, ++ 196, 24, 153, 68, 0, 235, 9, 6, 100, 104, 182, 120, 205, 248, 12, 144, ++ 6, 235, 4, 9, 95, 250, 137, 249, 9, 153, 205, 248, 32, 144, 79, 234, ++ 20, 41, 31, 250, 137, 249, 17, 185, 177, 68, 31, 250, 137, 249, 188, ++ 241, 0, 15, 8, 208, 194, 24, 18, 137, 79, 234, 82, 59, 178, 24, 18, ++ 5, 11, 240, 1, 11, 18, 13, 5, 157, 8, 153, 141, 66, 32, 209, 7, 157, ++ 77, 69, 29, 209, 221, 248, 24, 144, 185, 235, 20, 111, 24, 209, 188, ++ 241, 0, 15, 6, 208, 216, 69, 19, 209, 184, 241, 0, 15, 1, 208, 151, ++ 66, 12, 209, 3, 153, 1, 54, 64, 24, 84, 70, 134, 112, 212, 248, 136, ++ 48, 211, 248, 172, 32, 1, 50, 195, 248, 172, 32, 40, 224, 79, 240, 1, ++ 11, 196, 24, 228, 120, 2, 52, 27, 25, 219, 178, 2, 157, 171, 66, 169, ++ 211, 2, 158, 0, 157, 128, 25, 84, 70, 42, 70, 1, 153, 2, 48, 245, 247, ++ 177, 252, 212, 248, 136, 48, 26, 136, 91, 25, 155, 24, 1, 34, 154, 112, ++ 212, 248, 136, 48, 26, 136, 1, 50, 7, 224, 192, 24, 42, 70, 2, 48, 245, ++ 247, 160, 252, 212, 248, 136, 48, 26, 136, 173, 24, 29, 128, 0, 32, ++ 1, 224, 79, 240, 255, 48, 11, 176, 189, 232, 240, 143, 248, 181, 31, ++ 70, 131, 104, 21, 70, 147, 248, 1, 38, 14, 70, 18, 240, 2, 2, 64, 242, ++ 198, 99, 9, 120, 24, 191, 26, 70, 1, 35, 139, 64, 19, 64, 4, 70, 25, ++ 208, 208, 248, 136, 48, 27, 136, 91, 25, 120, 43, 2, 221, 255, 247, ++ 29, 255, 136, 185, 49, 70, 32, 70, 42, 70, 255, 247, 25, 255, 163, 104, ++ 32, 70, 147, 248, 0, 23, 0, 41, 20, 191, 57, 70, 0, 33, 189, 232, 248, ++ 64, 13, 240, 59, 154, 24, 70, 248, 189, 1, 41, 1, 209, 144, 104, 112, ++ 71, 2, 41, 12, 191, 208, 104, 0, 32, 112, 71, 45, 233, 243, 71, 4, 70, ++ 23, 70, 137, 70, 9, 185, 6, 105, 0, 224, 78, 104, 215, 248, 8, 128, ++ 117, 106, 152, 248, 13, 48, 152, 248, 12, 160, 67, 234, 10, 42, 72, ++ 246, 108, 3, 195, 235, 10, 2, 210, 241, 0, 10, 74, 235, 2, 10, 186, ++ 241, 0, 15, 89, 209, 32, 70, 57, 70, 12, 240, 21, 221, 152, 248, 12, ++ 32, 152, 248, 13, 48, 67, 234, 2, 35, 179, 245, 1, 79, 5, 209, 152, ++ 248, 4, 32, 152, 248, 5, 48, 67, 234, 2, 35, 98, 104, 146, 248, 46, ++ 32, 0, 42, 47, 208, 179, 245, 192, 111, 3, 211, 64, 246, 6, 2, 147, ++ 66, 45, 209, 32, 70, 73, 70, 255, 247, 28, 253, 128, 70, 185, 241, 0, ++ 15, 8, 208, 217, 248, 0, 16, 33, 177, 160, 104, 25, 240, 128, 253, 129, ++ 70, 0, 224, 137, 70, 184, 241, 0, 15, 27, 208, 64, 70, 57, 70, 255, ++ 247, 84, 251, 4, 40, 4, 208, 5, 40, 14, 208, 1, 40, 15, 209, 22, 224, ++ 185, 241, 0, 15, 19, 208, 153, 248, 6, 48, 131, 177, 153, 248, 59, 48, ++ 43, 185, 12, 224, 144, 70, 4, 224, 79, 240, 1, 8, 1, 224, 79, 240, 0, ++ 8, 212, 248, 180, 0, 57, 70, 0, 240, 171, 251, 48, 177, 99, 104, 57, ++ 70, 88, 105, 0, 34, 72, 224, 79, 240, 0, 8, 0, 45, 64, 208, 186, 241, ++ 0, 15, 32, 209, 235, 105, 219, 7, 11, 213, 99, 125, 75, 177, 32, 70, ++ 57, 70, 12, 240, 121, 222, 32, 185, 99, 104, 57, 70, 88, 105, 82, 70, ++ 50, 224, 184, 241, 0, 15, 14, 209, 99, 104, 147, 248, 146, 48, 83, 177, ++ 212, 248, 132, 0, 57, 70, 42, 240, 251, 253, 32, 185, 99, 104, 57, 70, ++ 88, 105, 66, 70, 32, 224, 2, 170, 0, 35, 57, 70, 2, 248, 1, 61, 32, ++ 70, 255, 247, 115, 253, 1, 70, 192, 177, 157, 248, 7, 48, 131, 116, ++ 99, 104, 88, 105, 254, 247, 184, 251, 43, 105, 4, 70, 219, 104, 48, ++ 70, 41, 70, 34, 70, 152, 71, 72, 177, 32, 70, 246, 247, 155, 248, 5, ++ 224, 99, 104, 57, 70, 88, 105, 42, 70, 254, 247, 106, 251, 189, 232, ++ 252, 135, 45, 233, 240, 65, 151, 137, 131, 104, 6, 63, 6, 70, 57, 70, ++ 88, 104, 21, 70, 254, 247, 59, 251, 4, 70, 184, 177, 169, 104, 58, 70, ++ 6, 49, 128, 104, 245, 247, 133, 251, 149, 248, 32, 48, 48, 70, 132, ++ 248, 32, 48, 149, 248, 35, 48, 0, 33, 132, 248, 35, 48, 235, 106, 34, ++ 70, 227, 98, 1, 35, 189, 232, 240, 65, 255, 247, 23, 191, 189, 232, ++ 240, 129, 1, 105, 16, 181, 72, 106, 40, 177, 1, 105, 140, 105, 20, 177, ++ 17, 70, 26, 70, 160, 71, 16, 189, 83, 104, 115, 181, 18, 43, 4, 70, ++ 21, 70, 46, 208, 5, 216, 16, 43, 43, 208, 52, 216, 11, 43, 74, 209, ++ 6, 224, 33, 43, 11, 208, 46, 43, 25, 208, 25, 43, 67, 209, 15, 224, ++ 67, 104, 211, 248, 28, 33, 145, 7, 61, 213, 2, 34, 5, 224, 67, 104, ++ 211, 248, 28, 33, 210, 7, 54, 213, 1, 34, 195, 248, 32, 33, 50, 224, ++ 67, 104, 211, 248, 28, 33, 16, 7, 45, 213, 8, 34, 245, 231, 67, 104, ++ 211, 248, 28, 33, 81, 7, 38, 213, 234, 104, 1, 42, 35, 209, 4, 34, 235, ++ 231, 171, 120, 3, 240, 1, 3, 35, 117, 227, 177, 212, 248, 144, 0, 255, ++ 247, 136, 251, 23, 224, 2, 170, 0, 35, 66, 248, 4, 61, 128, 104, 149, ++ 248, 47, 16, 25, 240, 119, 252, 6, 70, 96, 177, 131, 121, 35, 185, 105, ++ 136, 193, 243, 128, 1, 34, 240, 199, 223, 179, 121, 27, 177, 160, 104, ++ 49, 70, 54, 240, 187, 222, 124, 189, 112, 71, 16, 181, 67, 104, 4, 70, ++ 27, 126, 123, 177, 208, 248, 128, 0, 7, 240, 206, 217, 160, 104, 5, ++ 240, 76, 254, 99, 104, 0, 33, 32, 70, 131, 248, 32, 16, 189, 232, 16, ++ 64, 12, 240, 94, 155, 16, 189, 36, 48, 112, 71, 67, 124, 0, 43, 20, ++ 191, 48, 35, 36, 35, 192, 24, 4, 48, 112, 71, 67, 124, 0, 43, 20, 191, ++ 64, 35, 40, 35, 192, 24, 4, 48, 112, 71, 67, 124, 2, 140, 0, 43, 20, ++ 191, 32, 35, 8, 35, 155, 24, 192, 24, 36, 48, 112, 71, 45, 233, 247, ++ 79, 189, 248, 48, 128, 189, 248, 52, 160, 131, 70, 1, 146, 153, 70, ++ 15, 70, 0, 41, 12, 191, 4, 38, 16, 38, 0, 37, 11, 235, 5, 3, 28, 105, ++ 196, 177, 99, 124, 187, 66, 21, 209, 32, 70, 255, 247, 203, 255, 1, ++ 153, 50, 70, 245, 247, 171, 250, 104, 185, 32, 70, 255, 247, 197, 255, ++ 73, 70, 50, 70, 245, 247, 163, 250, 40, 185, 99, 138, 67, 69, 2, 209, ++ 163, 138, 83, 69, 4, 208, 4, 53, 16, 45, 223, 209, 0, 32, 0, 224, 32, ++ 70, 189, 232, 254, 143, 3, 42, 16, 181, 4, 70, 60, 217, 72, 136, 4, ++ 58, 144, 66, 56, 216, 8, 136, 24, 128, 10, 136, 4, 42, 54, 216, 223, ++ 232, 2, 240, 3, 6, 12, 27, 32, 0, 4, 34, 90, 128, 23, 224, 8, 34, 90, ++ 128, 24, 29, 161, 29, 8, 34, 11, 224, 10, 121, 3, 42, 40, 216, 4, 50, ++ 84, 248, 34, 16, 0, 41, 38, 208, 202, 137, 24, 29, 90, 128, 16, 49, ++ 245, 247, 126, 250, 20, 224, 4, 32, 88, 128, 34, 121, 26, 113, 15, 224, ++ 5, 34, 90, 128, 4, 34, 26, 113, 0, 34, 33, 105, 9, 177, 9, 121, 0, 224, ++ 255, 33, 152, 24, 1, 50, 4, 52, 4, 42, 65, 113, 244, 209, 0, 32, 16, ++ 189, 111, 240, 13, 0, 16, 189, 111, 240, 22, 0, 16, 189, 111, 240, 28, ++ 0, 16, 189, 111, 240, 29, 0, 16, 189, 248, 181, 3, 104, 5, 70, 14, 70, ++ 88, 104, 17, 70, 23, 70, 254, 247, 255, 249, 4, 70, 88, 177, 49, 70, ++ 58, 70, 128, 104, 245, 247, 74, 250, 40, 104, 33, 70, 0, 34, 10, 240, ++ 43, 251, 0, 32, 248, 189, 79, 240, 255, 48, 248, 189, 3, 104, 137, 104, ++ 152, 104, 12, 240, 31, 154, 1, 35, 112, 181, 10, 113, 4, 70, 67, 113, ++ 5, 70, 0, 241, 16, 6, 41, 105, 17, 177, 32, 70, 255, 247, 238, 255, ++ 4, 53, 181, 66, 247, 209, 112, 189, 3, 104, 112, 181, 5, 70, 12, 70, ++ 152, 104, 137, 104, 22, 70, 12, 240, 5, 218, 79, 244, 122, 114, 43, ++ 104, 114, 67, 152, 104, 161, 104, 0, 35, 189, 232, 112, 64, 12, 240, ++ 212, 153, 45, 233, 240, 67, 142, 137, 133, 176, 13, 46, 5, 70, 140, ++ 104, 64, 243, 228, 128, 34, 123, 99, 123, 67, 234, 2, 35, 179, 245, ++ 192, 111, 2, 219, 4, 241, 12, 7, 13, 224, 21, 46, 64, 243, 215, 128, ++ 111, 72, 4, 241, 14, 1, 6, 34, 245, 247, 231, 249, 0, 40, 64, 240, 206, ++ 128, 4, 241, 20, 7, 57, 120, 122, 120, 163, 25, 66, 234, 1, 34, 178, ++ 245, 0, 111, 7, 241, 2, 8, 5, 208, 72, 242, 221, 97, 138, 66, 64, 240, ++ 189, 128, 57, 224, 185, 120, 1, 240, 15, 1, 137, 0, 8, 235, 1, 4, 156, ++ 66, 0, 242, 179, 128, 250, 122, 6, 42, 64, 240, 175, 128, 58, 137, 79, ++ 234, 18, 41, 73, 234, 2, 41, 79, 234, 137, 73, 79, 234, 153, 73, 185, ++ 241, 0, 15, 64, 240, 162, 128, 186, 136, 22, 10, 70, 234, 2, 38, 118, ++ 26, 182, 178, 162, 25, 147, 66, 192, 240, 156, 128, 64, 70, 252, 247, ++ 9, 251, 187, 137, 131, 66, 64, 240, 149, 128, 64, 70, 33, 70, 50, 70, ++ 252, 247, 16, 251, 35, 138, 131, 66, 64, 240, 140, 128, 7, 241, 14, ++ 3, 7, 241, 18, 2, 73, 70, 27, 224, 7, 241, 42, 4, 156, 66, 125, 216, ++ 58, 122, 6, 42, 122, 209, 250, 136, 22, 10, 70, 234, 2, 38, 182, 178, ++ 162, 25, 147, 66, 114, 211, 64, 70, 33, 70, 50, 70, 252, 247, 28, 251, ++ 123, 143, 131, 66, 106, 209, 7, 241, 10, 3, 7, 241, 26, 2, 1, 33, 0, ++ 44, 102, 208, 180, 248, 2, 224, 32, 136, 79, 234, 30, 44, 76, 234, 14, ++ 46, 31, 250, 142, 254, 167, 104, 212, 248, 4, 128, 205, 248, 0, 224, ++ 79, 234, 16, 46, 78, 234, 0, 32, 128, 178, 1, 144, 40, 70, 255, 247, ++ 155, 254, 63, 186, 152, 250, 136, 248, 129, 70, 0, 40, 74, 208, 4, 241, ++ 12, 1, 2, 34, 3, 168, 245, 247, 106, 249, 157, 248, 13, 48, 19, 240, ++ 16, 4, 5, 209, 40, 70, 73, 70, 2, 34, 255, 247, 37, 255, 56, 224, 157, ++ 248, 12, 32, 18, 9, 182, 235, 130, 15, 3, 208, 40, 70, 73, 70, 6, 34, ++ 41, 224, 16, 43, 3, 208, 40, 70, 73, 70, 3, 34, 35, 224, 217, 248, 24, ++ 48, 187, 66, 24, 209, 217, 248, 28, 48, 67, 69, 9, 208, 23, 217, 72, ++ 70, 255, 247, 94, 254, 185, 248, 34, 32, 1, 70, 40, 70, 255, 247, 227, ++ 254, 107, 137, 73, 70, 169, 248, 12, 48, 40, 70, 234, 136, 255, 247, ++ 11, 255, 79, 240, 1, 9, 12, 224, 40, 70, 73, 70, 4, 34, 2, 224, 40, ++ 70, 73, 70, 5, 34, 255, 247, 238, 254, 79, 240, 0, 9, 0, 224, 161, 70, ++ 72, 70, 5, 176, 189, 232, 240, 131, 0, 191, 66, 50, 4, 0, 0, 35, 112, ++ 181, 4, 70, 67, 113, 5, 70, 0, 241, 16, 6, 41, 105, 49, 177, 0, 34, ++ 10, 113, 99, 137, 32, 70, 139, 129, 255, 247, 228, 254, 4, 53, 181, ++ 66, 243, 209, 112, 189, 11, 29, 112, 181, 80, 248, 35, 64, 5, 70, 14, ++ 70, 132, 177, 163, 104, 59, 177, 33, 70, 255, 247, 190, 254, 43, 104, ++ 161, 104, 152, 104, 12, 240, 85, 217, 32, 70, 254, 247, 147, 248, 4, ++ 54, 0, 35, 69, 248, 38, 48, 112, 189, 56, 181, 5, 70, 0, 36, 225, 178, ++ 40, 70, 1, 52, 255, 247, 223, 255, 4, 44, 248, 209, 56, 189, 45, 233, ++ 248, 67, 2, 241, 36, 9, 31, 250, 137, 249, 5, 70, 72, 70, 136, 70, 23, ++ 70, 14, 120, 254, 247, 115, 248, 4, 70, 32, 179, 0, 33, 74, 70, 246, ++ 243, 83, 244, 65, 70, 58, 70, 37, 96, 231, 129, 4, 241, 16, 0, 245, ++ 247, 203, 248, 43, 104, 13, 73, 152, 104, 34, 70, 0, 35, 12, 240, 46, ++ 217, 160, 96, 48, 185, 32, 70, 254, 247, 92, 248, 79, 240, 255, 48, ++ 189, 232, 248, 131, 0, 32, 32, 113, 107, 137, 4, 54, 163, 129, 69, 248, ++ 38, 64, 189, 232, 248, 131, 111, 240, 26, 0, 189, 232, 248, 131, 175, ++ 211, 0, 0, 3, 42, 112, 181, 5, 70, 12, 70, 50, 217, 75, 136, 4, 58, ++ 147, 66, 46, 216, 10, 136, 2, 42, 14, 208, 3, 42, 27, 208, 1, 42, 42, ++ 209, 7, 43, 49, 217, 6, 121, 0, 46, 43, 209, 6, 48, 4, 49, 8, 34, 245, ++ 247, 146, 248, 44, 224, 9, 121, 3, 41, 31, 216, 3, 121, 0, 43, 31, 209, ++ 255, 247, 127, 255, 98, 136, 40, 70, 33, 29, 189, 232, 112, 64, 255, ++ 247, 156, 191, 3, 43, 23, 217, 14, 121, 3, 121, 179, 66, 22, 208, 6, ++ 113, 22, 177, 255, 247, 90, 255, 17, 224, 255, 247, 132, 255, 15, 224, ++ 111, 240, 13, 6, 12, 224, 111, 240, 22, 6, 9, 224, 111, 240, 28, 6, ++ 6, 224, 111, 240, 15, 6, 3, 224, 111, 240, 23, 6, 0, 224, 0, 38, 48, ++ 70, 112, 189, 48, 181, 3, 153, 4, 157, 5, 155, 6, 156, 18, 177, 1, 42, ++ 12, 209, 5, 224, 42, 70, 3, 148, 189, 232, 48, 64, 255, 247, 172, 189, ++ 25, 70, 34, 70, 189, 232, 48, 64, 255, 247, 161, 191, 111, 240, 22, ++ 0, 48, 189, 3, 121, 43, 177, 64, 121, 208, 241, 1, 0, 56, 191, 0, 32, ++ 112, 71, 24, 70, 112, 71, 56, 181, 4, 70, 13, 70, 255, 247, 241, 255, ++ 40, 177, 32, 70, 41, 70, 189, 232, 56, 64, 255, 247, 30, 190, 56, 189, ++ 240, 181, 5, 104, 4, 70, 135, 176, 40, 70, 255, 247, 226, 255, 0, 40, ++ 45, 208, 166, 137, 222, 185, 40, 70, 33, 70, 1, 34, 5, 175, 255, 247, ++ 231, 253, 49, 70, 4, 34, 56, 70, 246, 243, 157, 243, 35, 124, 151, 33, ++ 141, 248, 20, 48, 40, 104, 4, 35, 208, 248, 108, 34, 3, 147, 194, 50, ++ 5, 35, 0, 150, 1, 150, 2, 151, 29, 240, 25, 223, 15, 224, 32, 70, 255, ++ 247, 28, 253, 34, 140, 1, 70, 40, 70, 255, 247, 170, 253, 163, 137, ++ 40, 70, 1, 59, 163, 129, 33, 70, 42, 137, 255, 247, 210, 253, 7, 176, ++ 240, 189, 144, 249, 33, 0, 112, 71, 79, 244, 192, 112, 112, 71, 8, 181, ++ 0, 104, 255, 247, 249, 255, 0, 40, 56, 191, 0, 32, 0, 40, 8, 191, 2, ++ 32, 128, 178, 8, 189, 2, 104, 48, 181, 210, 248, 108, 50, 212, 104, ++ 152, 66, 40, 209, 146, 248, 114, 50, 43, 187, 208, 248, 4, 17, 73, 123, ++ 25, 187, 208, 248, 244, 16, 0, 124, 205, 141, 107, 0, 96, 177, 145, ++ 248, 96, 0, 67, 67, 146, 248, 45, 2, 8, 177, 67, 67, 4, 224, 146, 248, ++ 44, 34, 10, 177, 83, 0, 107, 67, 9, 142, 212, 248, 128, 1, 212, 248, ++ 140, 33, 9, 185, 130, 66, 10, 211, 155, 2, 24, 24, 130, 66, 148, 191, ++ 0, 32, 1, 32, 48, 189, 0, 32, 48, 189, 24, 70, 48, 189, 1, 32, 48, 189, ++ 100, 41, 16, 220, 99, 41, 33, 218, 74, 41, 31, 208, 5, 220, 7, 41, 31, ++ 219, 8, 41, 26, 221, 60, 41, 18, 224, 80, 41, 22, 208, 24, 219, 92, ++ 57, 3, 41, 17, 224, 195, 41, 4, 220, 194, 41, 14, 218, 168, 57, 2, 41, ++ 10, 224, 177, 245, 132, 127, 8, 208, 3, 220, 177, 245, 128, 127, 7, ++ 209, 3, 224, 161, 245, 137, 113, 1, 41, 2, 216, 111, 240, 22, 0, 112, ++ 71, 0, 32, 112, 71, 0, 32, 112, 71, 200, 136, 16, 240, 8, 0, 24, 191, ++ 111, 240, 22, 0, 112, 71, 208, 248, 164, 53, 88, 137, 112, 71, 72, 242, ++ 243, 3, 153, 66, 6, 208, 72, 242, 55, 16, 9, 26, 72, 66, 64, 235, 1, ++ 0, 112, 71, 1, 32, 112, 71, 67, 137, 3, 240, 3, 3, 2, 43, 3, 209, 195, ++ 106, 216, 120, 192, 9, 112, 71, 3, 43, 4, 209, 195, 106, 216, 120, 0, ++ 240, 1, 0, 112, 71, 0, 32, 112, 71, 131, 122, 3, 240, 3, 3, 2, 43, 7, ++ 209, 195, 106, 219, 120, 19, 240, 48, 15, 12, 191, 0, 32, 1, 32, 112, ++ 71, 3, 43, 4, 209, 195, 106, 24, 120, 192, 243, 192, 0, 112, 71, 0, ++ 32, 112, 71, 200, 136, 192, 243, 192, 16, 112, 71, 200, 136, 192, 243, ++ 128, 0, 112, 71, 208, 248, 104, 49, 216, 121, 16, 241, 255, 48, 24, ++ 191, 1, 32, 112, 71, 8, 124, 168, 177, 209, 248, 244, 16, 73, 142, 81, ++ 64, 17, 244, 96, 80, 14, 208, 2, 244, 96, 82, 178, 245, 128, 95, 6, ++ 208, 178, 245, 192, 95, 5, 209, 24, 28, 24, 191, 1, 32, 112, 71, 1, ++ 32, 112, 71, 0, 32, 112, 71, 11, 105, 19, 177, 147, 248, 37, 19, 185, ++ 185, 153, 121, 25, 185, 0, 104, 144, 248, 44, 0, 120, 185, 2, 244, 64, ++ 112, 176, 245, 64, 127, 12, 208, 112, 177, 211, 248, 4, 49, 24, 120, ++ 72, 177, 160, 241, 2, 1, 72, 66, 64, 235, 1, 0, 112, 71, 8, 70, 112, ++ 71, 0, 32, 112, 71, 1, 32, 112, 71, 203, 104, 72, 177, 1, 136, 79, 246, ++ 255, 114, 145, 66, 4, 209, 27, 177, 90, 120, 10, 177, 155, 120, 3, 128, ++ 0, 32, 112, 71, 0, 34, 10, 96, 16, 240, 64, 114, 195, 178, 11, 208, ++ 178, 241, 128, 127, 2, 209, 67, 240, 128, 115, 5, 224, 178, 241, 0, ++ 127, 45, 209, 195, 178, 67, 240, 0, 115, 0, 244, 64, 114, 19, 67, 194, ++ 2, 72, 191, 67, 244, 128, 19, 66, 2, 72, 191, 67, 244, 128, 3, 2, 2, ++ 0, 244, 224, 32, 72, 191, 67, 244, 0, 3, 176, 245, 128, 63, 2, 209, ++ 67, 244, 128, 51, 16, 224, 176, 245, 0, 63, 2, 209, 67, 244, 0, 51, ++ 10, 224, 176, 245, 64, 63, 2, 209, 67, 244, 64, 51, 4, 224, 176, 245, ++ 128, 47, 8, 191, 67, 244, 128, 35, 11, 96, 0, 32, 112, 71, 111, 240, ++ 1, 0, 112, 71, 0, 0, 112, 181, 5, 104, 208, 248, 8, 5, 213, 248, 136, ++ 64, 102, 104, 1, 54, 102, 96, 166, 104, 182, 24, 166, 96, 16, 177, 132, ++ 105, 1, 52, 132, 97, 209, 248, 248, 0, 16, 185, 12, 105, 228, 104, 0, ++ 224, 4, 70, 102, 105, 1, 54, 102, 97, 8, 185, 9, 105, 200, 104, 129, ++ 105, 137, 24, 129, 97, 105, 107, 105, 177, 7, 72, 213, 248, 140, 16, ++ 195, 92, 6, 72, 195, 92, 1, 235, 195, 3, 89, 104, 1, 49, 89, 96, 153, ++ 104, 82, 24, 154, 96, 112, 189, 0, 191, 138, 182, 135, 0, 84, 194, 135, ++ 0, 3, 104, 88, 107, 112, 177, 211, 248, 140, 0, 7, 75, 155, 92, 7, 74, ++ 211, 92, 4, 51, 0, 235, 195, 3, 90, 104, 1, 50, 90, 96, 154, 104, 137, ++ 24, 153, 96, 112, 71, 0, 191, 138, 182, 135, 0, 84, 194, 135, 0, 74, ++ 104, 16, 181, 147, 66, 76, 136, 41, 219, 227, 6, 3, 213, 3, 104, 27, ++ 126, 0, 43, 38, 209, 33, 7, 3, 213, 3, 104, 27, 126, 0, 43, 35, 208, ++ 162, 6, 2, 213, 67, 126, 0, 43, 33, 208, 99, 7, 34, 212, 20, 240, 3, ++ 3, 34, 208, 2, 153, 24, 240, 174, 255, 0, 40, 31, 208, 225, 7, 2, 213, ++ 131, 121, 0, 43, 29, 209, 20, 240, 2, 4, 29, 208, 131, 121, 0, 43, 12, ++ 191, 111, 240, 5, 0, 0, 32, 16, 189, 111, 240, 1, 0, 16, 189, 111, 240, ++ 4, 0, 16, 189, 111, 240, 3, 0, 16, 189, 111, 240, 10, 0, 16, 189, 111, ++ 240, 22, 0, 16, 189, 24, 70, 16, 189, 111, 240, 29, 0, 16, 189, 111, ++ 240, 6, 0, 16, 189, 32, 70, 16, 189, 136, 110, 56, 181, 12, 70, 21, ++ 70, 40, 177, 253, 247, 172, 253, 0, 35, 163, 102, 164, 248, 108, 48, ++ 32, 70, 41, 70, 79, 244, 146, 114, 189, 232, 56, 64, 244, 247, 3, 190, ++ 45, 233, 248, 67, 6, 70, 13, 70, 23, 70, 152, 70, 209, 248, 204, 144, ++ 208, 248, 160, 69, 16, 224, 213, 248, 204, 48, 153, 69, 14, 209, 227, ++ 104, 171, 66, 8, 209, 163, 121, 155, 7, 5, 213, 176, 104, 161, 104, ++ 58, 70, 67, 70, 255, 247, 119, 250, 36, 104, 0, 44, 236, 209, 189, 232, ++ 248, 131, 0, 0, 248, 181, 64, 104, 12, 70, 21, 70, 30, 70, 251, 247, ++ 109, 253, 5, 241, 107, 2, 144, 66, 163, 104, 124, 211, 167, 137, 5, ++ 241, 8, 2, 151, 66, 119, 211, 90, 25, 91, 93, 170, 43, 115, 209, 83, ++ 120, 170, 43, 112, 209, 147, 120, 3, 43, 109, 209, 208, 120, 0, 40, ++ 106, 209, 17, 121, 0, 41, 106, 209, 83, 121, 0, 43, 96, 209, 209, 136, ++ 8, 10, 64, 234, 1, 33, 50, 72, 9, 178, 129, 66, 90, 209, 167, 241, 8, ++ 3, 93, 27, 2, 208, 2, 241, 8, 3, 8, 224, 46, 75, 162, 138, 27, 104, ++ 83, 248, 34, 0, 0, 40, 81, 208, 131, 104, 133, 137, 98, 45, 74, 217, ++ 26, 120, 1, 58, 210, 178, 1, 42, 69, 216, 90, 120, 3, 42, 66, 209, 90, ++ 136, 17, 10, 65, 234, 2, 34, 146, 178, 94, 42, 61, 217, 26, 121, 2, ++ 42, 1, 208, 254, 42, 41, 209, 89, 121, 154, 121, 66, 234, 1, 34, 194, ++ 243, 192, 5, 194, 243, 192, 17, 194, 243, 0, 32, 194, 243, 128, 39, ++ 194, 243, 192, 36, 110, 177, 3, 46, 24, 209, 173, 177, 180, 185, 184, ++ 177, 193, 185, 207, 185, 179, 248, 97, 96, 214, 241, 1, 6, 56, 191, ++ 0, 38, 19, 224, 147, 5, 17, 212, 128, 185, 121, 177, 82, 6, 13, 212, ++ 101, 177, 95, 185, 132, 240, 1, 6, 8, 224, 46, 70, 6, 224, 0, 38, 4, ++ 224, 6, 70, 2, 224, 38, 70, 0, 224, 14, 70, 48, 70, 248, 189, 8, 70, ++ 248, 189, 24, 70, 248, 189, 0, 32, 248, 189, 0, 32, 248, 189, 0, 191, ++ 142, 136, 255, 255, 32, 7, 0, 0, 45, 233, 248, 67, 0, 235, 66, 2, 5, ++ 70, 12, 70, 152, 70, 8, 159, 163, 241, 14, 6, 178, 248, 76, 148, 58, ++ 240, 236, 221, 1, 56, 1, 40, 7, 216, 40, 70, 33, 70, 58, 240, 207, 221, ++ 16, 177, 129, 69, 40, 191, 129, 70, 169, 241, 42, 3, 158, 66, 3, 210, ++ 62, 96, 1, 32, 189, 232, 248, 131, 212, 248, 164, 49, 98, 104, 217, ++ 7, 15, 75, 88, 191, 169, 241, 28, 9, 2, 234, 3, 3, 72, 191, 169, 241, ++ 34, 9, 11, 177, 169, 241, 2, 9, 78, 69, 12, 217, 35, 125, 218, 7, 9, ++ 212, 41, 240, 1, 3, 168, 241, 15, 0, 192, 24, 59, 96, 176, 251, 243, ++ 240, 189, 232, 248, 131, 62, 96, 1, 32, 189, 232, 248, 131, 64, 0, 1, ++ 0, 45, 233, 248, 67, 137, 104, 139, 137, 8, 43, 92, 209, 200, 125, 139, ++ 123, 6, 40, 88, 209, 3, 240, 15, 3, 155, 0, 1, 241, 14, 4, 228, 24, ++ 103, 123, 77, 124, 16, 47, 8, 124, 38, 123, 76, 209, 0, 2, 54, 9, 40, ++ 24, 3, 235, 134, 3, 128, 178, 131, 66, 68, 209, 148, 248, 8, 128, 99, ++ 122, 148, 248, 10, 192, 231, 122, 0, 42, 57, 208, 144, 104, 130, 137, ++ 8, 42, 56, 209, 197, 125, 6, 45, 53, 209, 133, 123, 0, 241, 14, 6, 5, ++ 240, 15, 5, 6, 235, 133, 5, 110, 123, 16, 46, 43, 209, 149, 248, 8, ++ 144, 110, 122, 79, 234, 9, 105, 54, 4, 78, 68, 149, 248, 10, 144, 27, ++ 4, 79, 234, 9, 41, 79, 234, 8, 104, 78, 68, 67, 68, 149, 248, 11, 144, ++ 79, 234, 12, 44, 99, 68, 78, 68, 219, 25, 158, 66, 18, 217, 26, 48, ++ 26, 49, 244, 247, 163, 252, 128, 185, 4, 34, 40, 70, 33, 70, 244, 247, ++ 157, 252, 208, 241, 1, 0, 56, 191, 0, 32, 189, 232, 248, 131, 16, 70, ++ 189, 232, 248, 131, 0, 32, 189, 232, 248, 131, 0, 32, 189, 232, 248, ++ 131, 0, 0, 48, 181, 19, 72, 145, 176, 0, 104, 21, 156, 15, 144, 17, ++ 72, 18, 77, 7, 144, 32, 104, 11, 149, 8, 144, 16, 72, 9, 144, 160, 104, ++ 100, 104, 10, 144, 14, 144, 7, 168, 0, 144, 4, 147, 4, 32, 20, 155, ++ 12, 148, 1, 144, 11, 76, 0, 32, 2, 144, 3, 144, 5, 147, 8, 70, 1, 35, ++ 17, 70, 15, 170, 13, 148, 71, 240, 173, 216, 17, 176, 48, 189, 0, 191, ++ 250, 20, 4, 0, 13, 195, 129, 0, 233, 194, 129, 0, 209, 194, 129, 0, ++ 31, 214, 0, 0, 45, 233, 243, 71, 4, 70, 8, 70, 22, 70, 31, 70, 13, 70, ++ 221, 248, 40, 128, 255, 247, 105, 252, 1, 170, 1, 70, 32, 70, 24, 240, ++ 183, 253, 214, 248, 40, 160, 129, 70, 154, 248, 0, 48, 218, 7, 21, 213, ++ 0, 40, 49, 208, 208, 248, 204, 48, 91, 5, 55, 212, 208, 248, 244, 48, ++ 91, 142, 3, 244, 64, 67, 163, 245, 64, 76, 220, 241, 0, 3, 67, 235, ++ 12, 3, 14, 51, 0, 235, 131, 3, 88, 104, 25, 224, 120, 177, 49, 70, 32, ++ 70, 255, 247, 247, 252, 3, 28, 24, 191, 1, 35, 32, 70, 73, 70, 82, 70, ++ 47, 240, 0, 252, 16, 177, 208, 248, 16, 144, 5, 224, 32, 70, 177, 106, ++ 24, 240, 212, 253, 129, 70, 0, 32, 185, 241, 0, 15, 3, 208, 153, 248, ++ 68, 48, 133, 248, 33, 48, 168, 98, 15, 177, 199, 248, 0, 144, 184, 241, ++ 0, 15, 4, 208, 200, 248, 0, 0, 1, 224, 0, 32, 239, 231, 189, 232, 252, ++ 135, 0, 0, 248, 181, 205, 178, 107, 30, 14, 45, 140, 191, 79, 244, 64, ++ 71, 0, 39, 222, 43, 6, 70, 18, 216, 14, 45, 7, 216, 30, 72, 41, 70, ++ 246, 243, 37, 246, 4, 28, 24, 191, 1, 36, 9, 224, 27, 72, 41, 70, 246, ++ 243, 29, 246, 0, 40, 20, 191, 5, 36, 0, 36, 0, 224, 0, 36, 224, 7, 37, ++ 213, 69, 244, 128, 85, 61, 67, 214, 248, 92, 1, 41, 70, 66, 240, 115, ++ 217, 8, 177, 68, 240, 2, 4, 161, 7, 24, 213, 41, 70, 214, 248, 92, 1, ++ 66, 240, 5, 216, 41, 70, 1, 40, 214, 248, 92, 1, 8, 191, 68, 240, 8, ++ 4, 66, 240, 104, 216, 8, 177, 68, 240, 64, 4, 214, 248, 92, 1, 41, 70, ++ 65, 240, 198, 223, 8, 177, 68, 240, 32, 4, 32, 70, 248, 189, 0, 191, ++ 170, 201, 135, 0, 198, 201, 135, 0, 56, 181, 4, 70, 212, 248, 52, 19, ++ 128, 104, 11, 240, 163, 219, 212, 248, 60, 21, 208, 241, 1, 5, 160, ++ 104, 56, 191, 0, 37, 11, 240, 154, 219, 0, 185, 1, 53, 212, 248, 116, ++ 52, 160, 104, 211, 248, 48, 17, 11, 240, 145, 219, 0, 185, 1, 53, 40, ++ 70, 56, 189, 56, 181, 13, 70, 128, 179, 121, 179, 131, 121, 4, 104, ++ 99, 187, 212, 248, 108, 50, 26, 122, 66, 179, 211, 248, 4, 49, 27, 120, ++ 35, 179, 35, 104, 147, 248, 120, 48, 3, 179, 148, 248, 160, 55, 235, ++ 185, 148, 248, 208, 55, 211, 177, 148, 248, 184, 55, 35, 177, 160, 104, ++ 212, 248, 180, 23, 11, 240, 108, 219, 170, 139, 160, 104, 18, 244, 0, ++ 82, 24, 191, 13, 34, 212, 248, 180, 23, 0, 35, 11, 240, 59, 219, 1, ++ 35, 0, 34, 132, 248, 184, 55, 132, 248, 208, 39, 132, 248, 160, 55, ++ 56, 189, 45, 233, 240, 65, 6, 159, 5, 70, 6, 47, 20, 70, 30, 70, 17, ++ 221, 88, 28, 9, 73, 3, 34, 244, 247, 84, 251, 88, 185, 51, 121, 9, 43, ++ 8, 209, 213, 248, 80, 1, 33, 70, 50, 70, 59, 70, 189, 232, 240, 65, ++ 84, 240, 252, 156, 189, 232, 240, 129, 68, 29, 136, 0, 45, 233, 240, ++ 65, 164, 176, 144, 70, 6, 70, 42, 168, 37, 200, 205, 248, 32, 128, 3, ++ 144, 7, 136, 12, 70, 181, 248, 0, 192, 184, 248, 12, 128, 7, 244, 128, ++ 78, 9, 147, 180, 248, 68, 48, 205, 248, 64, 224, 0, 235, 12, 14, 204, ++ 235, 8, 12, 205, 248, 20, 192, 173, 248, 116, 48, 178, 248, 12, 192, ++ 62, 248, 2, 60, 141, 248, 108, 192, 195, 243, 192, 19, 79, 240, 0, 12, ++ 23, 244, 128, 127, 141, 248, 57, 48, 113, 104, 173, 248, 40, 112, 205, ++ 248, 16, 224, 205, 248, 24, 128, 141, 248, 56, 192, 0, 241, 16, 3, 3, ++ 209, 4, 48, 31, 147, 32, 144, 2, 224, 10, 48, 31, 144, 32, 147, 0, 35, ++ 17, 147, 19, 123, 48, 70, 0, 147, 34, 70, 3, 171, 94, 240, 65, 220, ++ 16, 155, 48, 185, 243, 177, 212, 248, 116, 49, 1, 51, 196, 248, 116, ++ 49, 24, 224, 35, 177, 212, 248, 112, 49, 1, 51, 196, 248, 112, 49, 8, ++ 155, 17, 152, 155, 104, 30, 147, 136, 177, 3, 122, 4, 43, 13, 209, 48, ++ 70, 3, 169, 94, 240, 192, 220, 17, 155, 42, 136, 147, 249, 14, 48, 211, ++ 24, 43, 128, 2, 224, 79, 240, 255, 48, 0, 224, 0, 32, 36, 176, 189, ++ 232, 240, 129, 56, 181, 160, 248, 72, 20, 4, 70, 208, 248, 92, 1, 13, ++ 70, 25, 240, 35, 254, 212, 248, 116, 20, 75, 123, 35, 177, 32, 70, 14, ++ 49, 42, 70, 48, 240, 118, 253, 33, 106, 32, 70, 48, 240, 109, 254, 32, ++ 70, 21, 240, 239, 216, 212, 248, 16, 7, 189, 232, 56, 64, 51, 240, 137, ++ 186, 112, 181, 4, 104, 13, 70, 212, 248, 108, 50, 152, 66, 62, 209, ++ 35, 104, 26, 126, 0, 42, 58, 208, 147, 248, 120, 48, 0, 43, 54, 208, ++ 148, 248, 46, 50, 65, 185, 115, 179, 160, 104, 212, 248, 236, 17, 11, ++ 240, 145, 218, 132, 248, 46, 82, 38, 224, 147, 177, 212, 248, 236, 17, ++ 160, 104, 11, 240, 136, 218, 0, 35, 132, 248, 46, 50, 250, 243, 39, ++ 240, 196, 248, 48, 2, 5, 224, 160, 104, 212, 248, 236, 17, 79, 244, ++ 122, 114, 11, 224, 148, 248, 46, 50, 155, 185, 32, 70, 166, 104, 212, ++ 248, 236, 81, 21, 240, 129, 220, 41, 70, 2, 70, 48, 70, 1, 35, 11, 240, ++ 69, 218, 1, 35, 132, 248, 46, 50, 112, 189, 148, 248, 46, 50, 0, 43, ++ 226, 208, 112, 189, 112, 181, 5, 104, 6, 70, 255, 247, 133, 250, 43, ++ 104, 4, 70, 147, 248, 60, 48, 35, 177, 213, 248, 84, 1, 78, 240, 90, ++ 217, 36, 24, 40, 70, 49, 70, 34, 70, 56, 240, 10, 222, 128, 178, 112, ++ 189, 45, 233, 248, 67, 7, 104, 12, 70, 21, 70, 152, 70, 215, 248, 180, ++ 98, 79, 240, 0, 9, 12, 224, 32, 70, 49, 104, 245, 243, 101, 246, 40, ++ 185, 115, 104, 157, 66, 2, 209, 179, 104, 152, 69, 25, 208, 177, 70, ++ 246, 104, 0, 46, 240, 209, 16, 32, 253, 247, 229, 249, 120, 177, 128, ++ 232, 48, 1, 198, 96, 185, 241, 0, 15, 4, 208, 201, 248, 12, 0, 48, 70, ++ 189, 232, 248, 131, 199, 248, 180, 2, 72, 70, 189, 232, 248, 131, 111, ++ 240, 21, 0, 189, 232, 248, 131, 45, 233, 240, 79, 208, 248, 160, 81, ++ 143, 176, 153, 70, 0, 35, 11, 149, 4, 70, 15, 70, 221, 248, 100, 160, ++ 12, 147, 155, 70, 29, 70, 148, 70, 152, 70, 54, 224, 212, 248, 4, 39, ++ 238, 0, 82, 248, 53, 0, 176, 177, 57, 70, 205, 248, 28, 192, 16, 240, ++ 185, 222, 221, 248, 28, 192, 3, 70, 32, 179, 193, 136, 79, 246, 255, ++ 114, 145, 66, 29, 208, 212, 248, 4, 55, 50, 70, 154, 24, 82, 104, 6, ++ 70, 224, 70, 9, 146, 36, 224, 212, 248, 168, 34, 90, 68, 16, 106, 136, ++ 177, 57, 70, 205, 248, 28, 192, 16, 240, 157, 222, 221, 248, 28, 192, ++ 3, 70, 64, 177, 212, 248, 168, 50, 6, 70, 91, 68, 224, 70, 155, 106, ++ 14, 224, 79, 240, 1, 8, 1, 53, 11, 241, 56, 11, 34, 104, 146, 248, 184, ++ 32, 149, 66, 195, 219, 30, 70, 67, 70, 224, 70, 0, 43, 46, 209, 9, 147, ++ 35, 104, 147, 248, 184, 48, 157, 66, 26, 218, 42, 224, 212, 248, 168, ++ 50, 91, 68, 27, 106, 131, 177, 212, 248, 4, 39, 82, 248, 53, 32, 90, ++ 177, 24, 70, 57, 70, 16, 240, 110, 222, 48, 177, 212, 248, 168, 50, ++ 6, 70, 91, 68, 155, 106, 9, 147, 12, 224, 1, 53, 11, 241, 56, 11, 2, ++ 224, 0, 37, 171, 70, 48, 70, 35, 104, 147, 248, 184, 48, 157, 66, 221, ++ 219, 6, 70, 35, 104, 147, 248, 184, 48, 157, 66, 2, 219, 111, 240, 22, ++ 3, 32, 224, 184, 241, 0, 15, 2, 209, 221, 248, 96, 128, 209, 70, 51, ++ 137, 27, 177, 8, 43, 12, 191, 83, 70, 4, 35, 10, 147, 157, 248, 104, ++ 32, 179, 136, 91, 0, 2, 177, 1, 51, 67, 72, 57, 70, 7, 34, 8, 147, 245, ++ 243, 212, 245, 132, 70, 0, 40, 70, 209, 185, 241, 3, 15, 3, 220, 111, ++ 240, 13, 3, 12, 147, 107, 224, 4, 34, 65, 70, 13, 168, 205, 248, 28, ++ 192, 244, 247, 135, 249, 32, 70, 13, 153, 12, 170, 24, 240, 219, 250, ++ 12, 155, 131, 70, 30, 51, 221, 248, 28, 192, 26, 209, 8, 154, 208, 7, ++ 23, 213, 1, 35, 0, 147, 32, 70, 13, 153, 98, 70, 99, 70, 57, 240, 195, ++ 218, 131, 70, 24, 185, 111, 240, 26, 3, 12, 147, 9, 224, 32, 70, 89, ++ 70, 24, 240, 153, 252, 12, 144, 24, 177, 32, 70, 89, 70, 57, 240, 181, ++ 220, 12, 155, 0, 43, 59, 209, 8, 155, 7, 55, 217, 7, 8, 241, 4, 8, 169, ++ 241, 4, 9, 4, 213, 24, 154, 170, 241, 4, 10, 4, 50, 24, 146, 219, 248, ++ 12, 48, 27, 147, 8, 154, 27, 155, 2, 240, 1, 11, 1, 147, 32, 70, 49, ++ 70, 24, 154, 83, 70, 205, 248, 0, 176, 28, 240, 155, 220, 12, 144, 224, ++ 185, 24, 154, 141, 232, 0, 3, 2, 146, 10, 154, 212, 248, 172, 50, 4, ++ 146, 27, 154, 205, 248, 12, 160, 5, 146, 83, 248, 37, 0, 49, 70, 8, ++ 154, 59, 70, 9, 157, 168, 71, 12, 144, 187, 241, 0, 15, 5, 208, 11, ++ 157, 43, 120, 19, 177, 40, 70, 103, 240, 164, 223, 12, 152, 40, 177, ++ 0, 241, 52, 3, 52, 43, 156, 191, 35, 104, 152, 102, 15, 176, 189, 232, ++ 240, 143, 0, 191, 70, 62, 136, 0, 139, 105, 67, 244, 0, 115, 139, 97, ++ 195, 104, 211, 248, 128, 49, 211, 24, 75, 98, 112, 71, 19, 181, 0, 36, ++ 0, 148, 29, 240, 87, 220, 28, 189, 145, 248, 33, 0, 145, 248, 32, 48, ++ 130, 248, 33, 0, 136, 106, 130, 248, 32, 48, 144, 98, 200, 106, 0, 35, ++ 208, 98, 136, 139, 129, 248, 32, 48, 144, 131, 72, 106, 80, 98, 72, ++ 107, 80, 99, 75, 99, 139, 139, 136, 105, 147, 131, 9, 75, 3, 64, 136, ++ 127, 147, 97, 0, 240, 79, 0, 144, 119, 200, 127, 32, 240, 49, 0, 208, ++ 119, 136, 105, 0, 240, 0, 64, 3, 67, 147, 97, 11, 107, 19, 99, 112, ++ 71, 242, 70, 128, 95, 45, 233, 240, 79, 137, 176, 8, 171, 7, 70, 0, ++ 32, 67, 248, 4, 13, 144, 104, 14, 105, 4, 137, 176, 248, 6, 192, 176, ++ 248, 0, 144, 176, 248, 2, 160, 176, 248, 4, 176, 4, 148, 68, 137, 14, ++ 48, 144, 96, 144, 137, 21, 70, 14, 56, 144, 129, 215, 248, 160, 1, 5, ++ 148, 205, 248, 12, 192, 136, 70, 103, 240, 153, 222, 50, 124, 4, 70, ++ 3, 136, 221, 248, 12, 192, 26, 179, 216, 248, 164, 33, 210, 7, 14, 213, ++ 4, 154, 160, 248, 134, 144, 160, 248, 144, 32, 5, 154, 160, 248, 136, ++ 160, 160, 248, 138, 176, 160, 248, 142, 192, 160, 248, 146, 32, 16, ++ 224, 178, 121, 50, 185, 160, 248, 134, 144, 160, 248, 136, 160, 160, ++ 248, 138, 176, 7, 224, 4, 154, 160, 248, 134, 192, 160, 248, 136, 32, ++ 5, 154, 160, 248, 138, 32, 180, 248, 76, 32, 2, 240, 7, 9, 185, 241, ++ 4, 15, 6, 209, 56, 70, 49, 70, 3, 147, 11, 240, 165, 222, 3, 155, 14, ++ 224, 183, 248, 62, 19, 34, 244, 254, 66, 72, 28, 167, 248, 62, 3, 72, ++ 2, 71, 246, 224, 113, 34, 240, 224, 2, 1, 64, 66, 234, 1, 0, 164, 248, ++ 76, 0, 170, 139, 208, 4, 2, 212, 169, 105, 73, 5, 3, 213, 18, 1, 164, ++ 248, 140, 32, 15, 224, 3, 240, 16, 3, 155, 178, 91, 185, 234, 137, 2, ++ 240, 7, 2, 96, 50, 8, 235, 66, 2, 211, 136, 89, 28, 27, 1, 209, 128, ++ 164, 248, 140, 48, 171, 139, 180, 248, 140, 32, 35, 244, 126, 99, 35, ++ 240, 31, 3, 67, 234, 18, 19, 171, 131, 184, 104, 11, 240, 61, 221, 2, ++ 7, 3, 213, 171, 139, 67, 244, 0, 83, 171, 131, 171, 105, 155, 5, 9, ++ 213, 171, 140, 164, 248, 66, 48, 235, 140, 164, 248, 68, 48, 35, 136, ++ 67, 244, 0, 83, 35, 128, 59, 104, 147, 248, 69, 48, 99, 177, 185, 241, ++ 3, 15, 9, 216, 42, 75, 215, 248, 100, 1, 19, 248, 9, 16, 79, 240, 255, ++ 50, 67, 70, 61, 240, 221, 219, 170, 105, 7, 155, 19, 67, 171, 97, 179, ++ 121, 43, 185, 214, 248, 72, 51, 251, 177, 155, 123, 216, 7, 28, 213, ++ 152, 248, 231, 48, 203, 177, 185, 241, 4, 15, 22, 208, 28, 74, 152, ++ 248, 218, 16, 18, 248, 9, 32, 4, 241, 118, 3, 81, 250, 2, 242, 18, 240, ++ 1, 15, 79, 240, 1, 2, 0, 146, 56, 70, 65, 70, 42, 70, 2, 208, 44, 240, ++ 21, 220, 1, 224, 44, 240, 110, 222, 214, 248, 28, 49, 67, 185, 214, ++ 248, 24, 35, 198, 248, 32, 33, 214, 248, 28, 35, 198, 248, 36, 33, 13, ++ 224, 3, 241, 35, 2, 86, 248, 50, 16, 3, 241, 36, 2, 70, 248, 50, 16, ++ 6, 235, 195, 2, 210, 248, 28, 17, 194, 248, 36, 17, 1, 51, 3, 240, 63, ++ 3, 198, 248, 28, 49, 9, 176, 189, 232, 240, 143, 84, 194, 135, 0, 112, ++ 181, 4, 70, 144, 137, 157, 104, 6, 10, 70, 234, 0, 38, 165, 241, 8, ++ 0, 152, 96, 152, 137, 182, 178, 8, 48, 152, 129, 16, 136, 37, 248, 8, ++ 12, 80, 136, 37, 248, 6, 12, 144, 136, 37, 248, 4, 12, 208, 136, 37, ++ 248, 2, 12, 16, 137, 40, 128, 82, 137, 8, 70, 106, 128, 25, 70, 250, ++ 247, 66, 255, 14, 56, 128, 178, 3, 10, 67, 234, 0, 32, 170, 35, 171, ++ 113, 235, 113, 3, 35, 43, 114, 0, 35, 168, 128, 107, 114, 171, 114, ++ 49, 70, 32, 70, 255, 247, 36, 248, 51, 10, 0, 40, 20, 191, 248, 32, ++ 0, 32, 67, 234, 6, 38, 232, 114, 174, 129, 112, 189, 45, 233, 240, 67, ++ 139, 104, 12, 70, 23, 70, 202, 137, 73, 104, 35, 240, 127, 67, 193, ++ 243, 20, 1, 35, 244, 96, 3, 91, 26, 179, 43, 133, 176, 6, 70, 208, 248, ++ 4, 144, 2, 240, 7, 8, 4, 217, 80, 6, 2, 212, 163, 120, 1, 43, 61, 217, ++ 72, 70, 180, 33, 252, 247, 35, 255, 5, 70, 152, 185, 51, 104, 211, 248, ++ 136, 48, 26, 106, 1, 50, 26, 98, 47, 177, 59, 105, 27, 177, 219, 104, ++ 26, 106, 1, 50, 26, 98, 215, 248, 92, 49, 0, 36, 1, 51, 199, 248, 92, ++ 49, 122, 224, 131, 104, 33, 70, 180, 51, 131, 96, 131, 137, 42, 70, ++ 180, 59, 131, 129, 48, 104, 255, 247, 80, 254, 235, 137, 161, 104, 35, ++ 240, 7, 3, 72, 234, 3, 3, 235, 129, 1, 241, 14, 3, 163, 96, 163, 137, ++ 168, 104, 14, 59, 163, 129, 171, 137, 14, 56, 14, 51, 168, 96, 171, ++ 129, 14, 34, 243, 247, 62, 255, 36, 136, 172, 130, 44, 70, 161, 104, ++ 184, 241, 0, 15, 44, 208, 122, 104, 42, 75, 19, 64, 67, 187, 214, 248, ++ 84, 50, 219, 177, 139, 137, 26, 10, 66, 234, 3, 35, 27, 178, 19, 245, ++ 254, 79, 19, 208, 12, 34, 104, 70, 243, 247, 36, 255, 165, 104, 163, ++ 137, 40, 31, 4, 51, 163, 129, 160, 96, 105, 70, 12, 34, 243, 247, 26, ++ 255, 79, 234, 72, 24, 129, 35, 43, 129, 165, 248, 10, 128, 51, 104, ++ 91, 107, 51, 177, 150, 248, 56, 50, 27, 185, 227, 137, 35, 240, 7, 3, ++ 227, 129, 162, 104, 147, 137, 25, 10, 65, 234, 3, 35, 155, 178, 64, ++ 242, 220, 81, 139, 66, 27, 217, 72, 246, 142, 1, 139, 66, 161, 105, ++ 2, 209, 65, 240, 16, 1, 5, 224, 72, 246, 180, 0, 131, 66, 6, 209, 65, ++ 240, 0, 65, 163, 127, 161, 97, 99, 240, 127, 3, 163, 119, 163, 105, ++ 48, 70, 67, 240, 8, 3, 163, 97, 73, 70, 35, 70, 255, 247, 18, 255, 32, ++ 70, 5, 176, 189, 232, 240, 131, 64, 0, 1, 0, 56, 181, 147, 137, 21, ++ 70, 7, 43, 24, 217, 148, 104, 4, 241, 14, 1, 13, 240, 212, 222, 144, ++ 177, 171, 104, 3, 241, 8, 2, 170, 96, 170, 137, 8, 58, 170, 129, 226, ++ 136, 218, 129, 34, 137, 26, 130, 98, 137, 90, 130, 34, 136, 26, 129, ++ 98, 136, 90, 129, 164, 136, 156, 129, 56, 189, 0, 0, 56, 181, 12, 70, ++ 5, 70, 8, 70, 72, 73, 245, 243, 175, 244, 72, 73, 32, 70, 245, 243, ++ 171, 244, 71, 73, 32, 70, 245, 243, 167, 244, 70, 73, 32, 70, 245, 243, ++ 163, 244, 69, 73, 32, 70, 245, 243, 159, 244, 68, 73, 32, 70, 245, 243, ++ 155, 244, 32, 70, 66, 73, 245, 243, 151, 244, 213, 248, 52, 1, 15, 240, ++ 214, 248, 32, 185, 213, 248, 56, 1, 39, 240, 52, 219, 24, 177, 32, 70, ++ 60, 73, 245, 243, 137, 244, 213, 248, 52, 1, 15, 240, 200, 248, 24, ++ 177, 32, 70, 57, 73, 245, 243, 128, 244, 213, 248, 56, 1, 39, 240, 34, ++ 219, 24, 177, 32, 70, 53, 73, 245, 243, 119, 244, 213, 248, 48, 1, 40, ++ 240, 239, 219, 24, 177, 32, 70, 50, 73, 245, 243, 110, 244, 213, 248, ++ 48, 1, 16, 240, 56, 253, 24, 177, 32, 70, 46, 73, 245, 243, 101, 244, ++ 32, 70, 45, 73, 245, 243, 97, 244, 213, 248, 80, 1, 83, 240, 103, 221, ++ 24, 177, 32, 70, 42, 73, 245, 243, 88, 244, 43, 104, 147, 248, 60, 48, ++ 27, 177, 32, 70, 39, 73, 245, 243, 80, 244, 38, 73, 32, 70, 245, 243, ++ 76, 244, 37, 73, 32, 70, 245, 243, 72, 244, 36, 73, 32, 70, 245, 243, ++ 68, 244, 35, 73, 32, 70, 245, 243, 64, 244, 43, 106, 24, 105, 32, 240, ++ 124, 249, 130, 7, 7, 213, 31, 73, 32, 70, 245, 243, 54, 244, 32, 70, ++ 30, 73, 245, 243, 50, 244, 32, 70, 29, 73, 245, 243, 46, 244, 32, 70, ++ 28, 73, 245, 243, 42, 244, 32, 70, 27, 73, 245, 243, 38, 244, 26, 73, ++ 32, 70, 189, 232, 56, 64, 245, 243, 32, 180, 124, 50, 4, 0, 128, 50, ++ 4, 0, 133, 50, 4, 0, 138, 50, 4, 0, 147, 50, 4, 0, 156, 50, 4, 0, 160, ++ 50, 4, 0, 165, 50, 4, 0, 172, 50, 4, 0, 182, 50, 4, 0, 192, 50, 4, 0, ++ 201, 50, 4, 0, 210, 50, 4, 0, 225, 50, 4, 0, 230, 50, 4, 0, 237, 50, ++ 4, 0, 243, 50, 4, 0, 250, 50, 4, 0, 1, 51, 4, 0, 13, 51, 4, 0, 22, 51, ++ 4, 0, 35, 51, 4, 0, 40, 51, 4, 0, 50, 51, 4, 0, 55, 51, 4, 0, 48, 181, ++ 133, 176, 5, 70, 104, 70, 12, 70, 245, 243, 209, 243, 40, 70, 105, 70, ++ 255, 247, 45, 255, 32, 70, 5, 176, 48, 189, 45, 233, 248, 67, 144, 248, ++ 1, 118, 4, 70, 23, 240, 8, 7, 13, 70, 22, 70, 152, 70, 111, 208, 147, ++ 105, 19, 240, 128, 87, 106, 209, 3, 240, 64, 9, 95, 250, 137, 249, 171, ++ 104, 217, 4, 52, 213, 184, 241, 0, 15, 14, 209, 113, 107, 3, 244, 0, ++ 82, 82, 11, 178, 235, 209, 127, 7, 209, 35, 244, 128, 83, 171, 96, 79, ++ 240, 255, 51, 165, 248, 44, 50, 60, 224, 160, 104, 11, 240, 183, 218, ++ 194, 6, 7, 212, 181, 248, 44, 34, 150, 248, 52, 48, 154, 66, 1, 209, ++ 171, 104, 34, 224, 160, 104, 11, 240, 170, 218, 195, 6, 41, 213, 114, ++ 107, 16, 1, 38, 213, 171, 104, 210, 15, 3, 244, 0, 81, 178, 235, 81, ++ 63, 31, 209, 130, 240, 1, 2, 35, 244, 0, 83, 67, 234, 66, 51, 22, 224, ++ 184, 241, 0, 15, 22, 208, 114, 107, 17, 1, 19, 213, 67, 244, 128, 83, ++ 171, 96, 150, 248, 52, 32, 165, 248, 44, 34, 3, 244, 0, 82, 0, 42, 12, ++ 191, 79, 244, 0, 82, 0, 34, 35, 244, 0, 83, 19, 67, 171, 96, 0, 224, ++ 1, 39, 171, 104, 114, 107, 3, 244, 0, 83, 34, 240, 0, 66, 91, 11, 66, ++ 234, 195, 115, 115, 99, 185, 241, 0, 15, 8, 208, 5, 75, 178, 138, 27, ++ 104, 83, 248, 34, 96, 0, 46, 153, 209, 0, 224, 0, 39, 56, 70, 189, 232, ++ 248, 131, 32, 7, 0, 0, 45, 233, 240, 65, 31, 70, 147, 105, 136, 176, ++ 3, 240, 64, 8, 5, 70, 14, 70, 20, 70, 95, 250, 136, 248, 99, 107, 27, ++ 1, 29, 213, 163, 105, 216, 0, 1, 213, 5, 46, 32, 209, 67, 240, 128, ++ 83, 8, 169, 163, 97, 1, 34, 1, 248, 28, 109, 168, 104, 59, 70, 254, ++ 247, 181, 248, 1, 46, 2, 209, 168, 104, 253, 247, 232, 255, 168, 104, ++ 253, 247, 225, 255, 208, 248, 152, 48, 1, 51, 192, 248, 152, 48, 7, ++ 224, 168, 104, 253, 247, 216, 255, 208, 248, 156, 48, 1, 51, 192, 248, ++ 156, 48, 184, 241, 0, 15, 6, 208, 4, 75, 162, 138, 27, 104, 83, 248, ++ 34, 64, 0, 44, 204, 209, 8, 176, 189, 232, 240, 129, 32, 7, 0, 0, 203, ++ 136, 19, 244, 192, 111, 12, 191, 0, 32, 1, 32, 112, 71, 112, 181, 21, ++ 70, 0, 41, 66, 208, 0, 42, 64, 208, 140, 104, 0, 44, 61, 208, 0, 38, ++ 22, 98, 86, 98, 148, 248, 77, 32, 148, 248, 76, 48, 64, 104, 67, 234, ++ 2, 35, 171, 128, 180, 248, 68, 32, 180, 248, 66, 48, 67, 234, 2, 67, ++ 43, 96, 98, 120, 35, 120, 67, 234, 2, 35, 235, 128, 226, 120, 163, 120, ++ 172, 97, 67, 234, 2, 35, 43, 129, 112, 35, 107, 97, 4, 241, 118, 3, ++ 235, 97, 4, 241, 38, 3, 171, 98, 4, 241, 112, 3, 235, 98, 98, 122, 35, ++ 122, 67, 234, 2, 35, 107, 129, 163, 122, 226, 122, 67, 234, 2, 35, 171, ++ 129, 180, 248, 140, 48, 27, 9, 43, 134, 250, 247, 110, 252, 118, 56, ++ 104, 130, 238, 129, 180, 248, 70, 48, 43, 130, 112, 189, 48, 181, 145, ++ 176, 5, 70, 12, 70, 3, 170, 255, 247, 177, 255, 0, 35, 40, 70, 33, 70, ++ 3, 170, 0, 147, 255, 247, 89, 248, 17, 176, 48, 189, 139, 122, 200, ++ 106, 3, 240, 3, 3, 2, 43, 3, 209, 0, 120, 0, 240, 127, 0, 112, 71, 42, ++ 240, 101, 184, 16, 181, 12, 70, 137, 105, 33, 240, 186, 220, 163, 105, ++ 27, 136, 227, 128, 16, 189, 208, 248, 104, 18, 0, 34, 139, 88, 83, 177, ++ 152, 121, 64, 185, 24, 122, 48, 177, 24, 124, 32, 185, 211, 248, 252, ++ 48, 147, 248, 137, 48, 35, 177, 4, 50, 32, 42, 239, 209, 0, 32, 112, ++ 71, 1, 32, 112, 71, 144, 248, 115, 34, 10, 177, 255, 247, 228, 191, ++ 144, 248, 113, 2, 112, 71, 0, 0, 10, 75, 16, 181, 1, 240, 96, 4, 100, ++ 17, 51, 248, 20, 64, 8, 75, 1, 240, 15, 1, 91, 92, 160, 248, 214, 64, ++ 128, 248, 216, 48, 26, 177, 128, 248, 217, 48, 128, 248, 218, 48, 16, ++ 189, 0, 191, 116, 50, 4, 0, 100, 50, 4, 0, 45, 233, 240, 79, 3, 240, ++ 1, 3, 169, 176, 4, 70, 20, 147, 212, 248, 108, 52, 16, 105, 27, 104, ++ 14, 70, 195, 88, 208, 248, 68, 19, 27, 120, 145, 70, 15, 147, 212, 248, ++ 112, 52, 178, 104, 27, 104, 25, 145, 195, 88, 8, 144, 27, 120, 9, 146, ++ 21, 147, 19, 136, 96, 104, 11, 147, 3, 240, 12, 3, 155, 8, 2, 43, 8, ++ 191, 11, 153, 19, 147, 11, 154, 12, 191, 193, 243, 192, 19, 0, 35, 219, ++ 178, 26, 147, 2, 244, 64, 115, 163, 245, 64, 117, 107, 66, 67, 235, ++ 5, 3, 49, 70, 28, 147, 55, 159, 250, 247, 207, 251, 54, 155, 4, 48, ++ 14, 144, 131, 177, 27, 122, 11, 43, 7, 209, 35, 104, 147, 248, 177, ++ 48, 75, 177, 54, 152, 131, 121, 7, 43, 5, 216, 54, 153, 14, 154, 145, ++ 249, 15, 48, 210, 24, 14, 146, 212, 248, 180, 49, 0, 43, 45, 218, 54, ++ 155, 3, 179, 27, 122, 2, 43, 31, 209, 148, 248, 148, 34, 242, 185, 8, ++ 152, 3, 109, 19, 240, 8, 3, 28, 209, 54, 153, 138, 121, 33, 104, 209, ++ 248, 188, 16, 138, 66, 23, 210, 3, 42, 21, 217, 11, 42, 19, 216, 178, ++ 105, 144, 0, 16, 212, 51, 154, 1, 42, 15, 209, 14, 155, 1, 32, 8, 51, ++ 14, 147, 4, 224, 54, 154, 4, 224, 0, 35, 4, 224, 0, 32, 12, 144, 5, ++ 224, 12, 146, 3, 224, 12, 147, 1, 224, 0, 33, 12, 145, 181, 104, 179, ++ 137, 170, 31, 118, 51, 165, 241, 118, 0, 29, 146, 179, 129, 0, 33, 112, ++ 34, 176, 96, 24, 144, 244, 243, 102, 247, 179, 139, 217, 4, 2, 212, ++ 178, 105, 82, 5, 2, 213, 27, 5, 27, 13, 32, 224, 217, 248, 4, 32, 160, ++ 75, 19, 64, 187, 177, 11, 153, 1, 240, 252, 3, 136, 43, 18, 209, 9, ++ 154, 19, 121, 216, 7, 14, 212, 51, 152, 242, 137, 65, 30, 2, 240, 7, ++ 2, 50, 152, 96, 50, 9, 235, 66, 2, 136, 66, 211, 136, 6, 209, 89, 28, ++ 209, 128, 3, 224, 19, 153, 1, 41, 6, 209, 17, 224, 19, 152, 1, 40, 14, ++ 208, 0, 33, 7, 145, 2, 224, 16, 34, 7, 146, 0, 35, 50, 152, 27, 1, 155, ++ 178, 0, 240, 15, 2, 9, 153, 19, 67, 203, 130, 1, 224, 0, 34, 7, 146, ++ 9, 155, 160, 104, 218, 138, 179, 139, 35, 244, 126, 99, 35, 240, 31, ++ 3, 67, 234, 18, 19, 179, 131, 11, 240, 149, 216, 1, 7, 3, 213, 179, ++ 139, 67, 244, 0, 83, 179, 131, 52, 152, 4, 40, 8, 209, 32, 70, 8, 153, ++ 53, 248, 42, 44, 11, 240, 180, 217, 173, 248, 152, 0, 25, 224, 50, 153, ++ 51, 152, 1, 240, 15, 2, 180, 248, 62, 51, 65, 30, 50, 152, 66, 234, ++ 3, 18, 136, 66, 146, 178, 2, 209, 1, 51, 164, 248, 62, 51, 52, 153, ++ 82, 1, 71, 246, 224, 115, 19, 64, 1, 240, 7, 2, 19, 67, 173, 248, 152, ++ 48, 153, 248, 231, 48, 59, 185, 11, 154, 2, 240, 252, 3, 128, 43, 2, ++ 208, 8, 152, 131, 121, 27, 185, 7, 153, 65, 240, 32, 1, 7, 145, 99, ++ 75, 59, 64, 0, 43, 64, 240, 130, 128, 7, 240, 64, 114, 178, 241, 128, ++ 127, 0, 240, 129, 128, 19, 154, 1, 42, 48, 217, 179, 105, 218, 6, 45, ++ 212, 0, 43, 43, 219, 150, 249, 31, 48, 0, 43, 39, 219, 34, 106, 87, ++ 75, 210, 248, 72, 128, 8, 234, 3, 3, 35, 185, 8, 240, 64, 115, 179, ++ 241, 128, 127, 3, 209, 9, 152, 3, 121, 223, 7, 102, 212, 210, 248, 68, ++ 128, 79, 75, 8, 234, 3, 3, 35, 185, 8, 240, 64, 115, 179, 241, 128, ++ 127, 4, 209, 9, 153, 11, 121, 19, 240, 1, 3, 89, 208, 9, 154, 19, 121, ++ 216, 7, 3, 212, 217, 248, 8, 48, 25, 7, 5, 213, 153, 248, 80, 112, 7, ++ 240, 127, 7, 184, 70, 73, 224, 2, 35, 141, 248, 134, 48, 39, 171, 0, ++ 147, 212, 248, 96, 1, 31, 171, 73, 70, 38, 170, 46, 240, 1, 252, 11, ++ 152, 221, 248, 124, 128, 0, 240, 252, 3, 72, 43, 32, 159, 1, 208, 200, ++ 43, 11, 209, 65, 70, 8, 152, 0, 34, 30, 240, 18, 218, 153, 248, 80, ++ 112, 128, 70, 7, 240, 127, 7, 0, 35, 8, 224, 179, 105, 50, 153, 67, ++ 240, 0, 99, 179, 97, 209, 241, 1, 3, 56, 191, 0, 35, 189, 248, 156, ++ 32, 210, 7, 3, 213, 178, 105, 66, 244, 0, 82, 178, 97, 34, 104, 146, ++ 248, 229, 32, 186, 177, 212, 248, 228, 6, 73, 70, 189, 248, 152, 32, ++ 5, 147, 92, 240, 228, 218, 5, 155, 18, 144, 13, 224, 0, 34, 184, 70, ++ 18, 146, 19, 70, 8, 224, 184, 70, 3, 224, 71, 70, 0, 35, 0, 224, 71, ++ 70, 18, 147, 0, 224, 18, 146, 34, 104, 212, 248, 116, 4, 146, 248, 79, ++ 32, 144, 248, 12, 176, 18, 240, 3, 2, 0, 240, 156, 129, 130, 120, 1, ++ 42, 9, 217, 33, 106, 145, 249, 77, 16, 161, 241, 1, 14, 222, 241, 0, ++ 1, 65, 235, 14, 1, 0, 224, 0, 33, 1, 42, 95, 250, 129, 250, 23, 217, ++ 34, 106, 146, 249, 77, 32, 1, 50, 18, 209, 217, 248, 4, 32, 18, 240, ++ 128, 66, 14, 208, 14, 48, 2, 33, 5, 147, 245, 243, 193, 244, 2, 28, ++ 24, 191, 1, 34, 5, 155, 4, 224, 64, 0, 1, 0, 255, 0, 0, 192, 0, 34, ++ 24, 240, 64, 127, 208, 178, 95, 250, 136, 242, 7, 208, 31, 42, 2, 217, ++ 32, 42, 7, 208, 85, 58, 7, 42, 4, 217, 28, 224, 160, 73, 138, 86, 0, ++ 42, 24, 218, 184, 241, 0, 15, 21, 219, 40, 244, 128, 24, 40, 244, 64, ++ 120, 24, 240, 64, 114, 9, 208, 186, 241, 0, 15, 3, 209, 178, 241, 128, ++ 127, 3, 209, 16, 177, 72, 244, 128, 24, 4, 224, 187, 241, 1, 15, 8, ++ 191, 72, 244, 128, 120, 23, 240, 64, 127, 250, 178, 7, 208, 31, 42, ++ 2, 217, 32, 42, 7, 208, 85, 58, 7, 42, 4, 217, 27, 224, 139, 73, 138, ++ 86, 0, 42, 23, 218, 0, 47, 21, 219, 39, 244, 128, 23, 39, 244, 64, 119, ++ 23, 240, 64, 114, 9, 208, 186, 241, 0, 15, 3, 209, 178, 241, 128, 127, ++ 3, 209, 16, 177, 71, 244, 128, 23, 4, 224, 187, 241, 1, 15, 8, 191, ++ 71, 244, 128, 119, 180, 248, 72, 36, 2, 244, 96, 82, 178, 245, 192, ++ 95, 44, 209, 24, 244, 224, 34, 31, 209, 24, 240, 64, 127, 23, 208, 217, ++ 248, 4, 32, 18, 3, 19, 213, 34, 104, 146, 248, 60, 32, 146, 177, 8, ++ 152, 130, 121, 122, 177, 208, 248, 244, 32, 82, 142, 2, 244, 96, 82, ++ 178, 245, 192, 95, 12, 191, 79, 244, 0, 50, 79, 244, 128, 50, 4, 224, ++ 79, 244, 128, 50, 1, 224, 79, 244, 0, 50, 24, 240, 64, 127, 19, 208, ++ 95, 250, 136, 241, 32, 41, 8, 191, 79, 244, 0, 50, 12, 224, 95, 250, ++ 136, 242, 249, 178, 32, 42, 8, 191, 79, 240, 128, 120, 32, 41, 8, 191, ++ 79, 240, 128, 119, 79, 244, 128, 50, 39, 244, 224, 42, 23, 240, 64, ++ 127, 40, 244, 224, 40, 72, 234, 2, 8, 24, 191, 74, 234, 2, 10, 34, 106, ++ 8, 191, 74, 244, 128, 58, 81, 108, 86, 74, 10, 64, 0, 42, 83, 209, 1, ++ 240, 64, 113, 177, 241, 128, 127, 78, 208, 24, 240, 64, 127, 148, 248, ++ 32, 34, 4, 208, 1, 42, 2, 209, 72, 244, 0, 8, 2, 224, 10, 185, 40, 244, ++ 0, 8, 26, 240, 64, 127, 148, 248, 32, 34, 5, 208, 1, 42, 3, 209, 74, ++ 244, 0, 10, 0, 240, 11, 190, 0, 42, 64, 240, 8, 134, 42, 244, 0, 10, ++ 0, 240, 4, 190, 217, 248, 4, 16, 200, 3, 43, 213, 217, 248, 8, 16, 9, ++ 6, 39, 213, 1, 50, 37, 209, 24, 240, 64, 127, 15, 208, 95, 250, 136, ++ 242, 162, 241, 87, 1, 1, 41, 9, 217, 99, 42, 7, 208, 100, 42, 5, 208, ++ 101, 42, 3, 208, 102, 42, 24, 191, 72, 244, 128, 8, 26, 240, 64, 127, ++ 15, 208, 95, 250, 138, 242, 162, 241, 87, 1, 1, 41, 9, 217, 99, 42, ++ 7, 208, 100, 42, 5, 208, 101, 42, 3, 208, 102, 42, 24, 191, 74, 244, ++ 128, 10, 32, 70, 73, 70, 5, 147, 16, 240, 162, 222, 24, 240, 64, 114, ++ 5, 155, 69, 208, 21, 153, 2, 41, 8, 209, 8, 244, 224, 43, 171, 245, ++ 0, 50, 210, 241, 0, 11, 75, 235, 2, 11, 1, 224, 79, 240, 0, 11, 95, ++ 250, 136, 242, 31, 42, 4, 216, 7, 42, 148, 191, 0, 33, 1, 33, 10, 224, ++ 32, 42, 6, 208, 162, 241, 85, 1, 7, 41, 148, 191, 0, 33, 1, 33, 0, 224, ++ 0, 33, 201, 178, 57, 177, 153, 248, 14, 17, 33, 177, 153, 248, 15, 17, ++ 0, 49, 24, 191, 1, 33, 24, 244, 0, 15, 17, 145, 30, 208, 31, 42, 4, ++ 216, 7, 42, 140, 191, 0, 34, 1, 34, 9, 224, 32, 42, 5, 208, 85, 58, ++ 7, 42, 140, 191, 0, 34, 1, 34, 0, 224, 1, 34, 210, 178, 0, 42, 12, 191, ++ 2, 70, 4, 34, 13, 146, 8, 224, 13, 146, 147, 70, 17, 146, 4, 224, 224, ++ 248, 135, 0, 255, 0, 0, 192, 13, 144, 26, 240, 64, 114, 38, 208, 26, ++ 244, 0, 15, 37, 208, 95, 250, 138, 242, 31, 42, 4, 216, 7, 42, 140, ++ 191, 0, 34, 1, 34, 9, 224, 32, 42, 5, 208, 85, 58, 7, 42, 140, 191, ++ 0, 34, 1, 34, 0, 224, 1, 34, 210, 178, 0, 42, 24, 191, 4, 32, 14, 224, ++ 40, 244, 224, 40, 39, 244, 224, 42, 72, 244, 128, 56, 74, 244, 128, ++ 58, 16, 146, 13, 146, 147, 70, 17, 146, 2, 224, 16, 146, 0, 224, 16, ++ 144, 163, 177, 8, 154, 51, 152, 210, 248, 28, 17, 1, 241, 36, 3, 66, ++ 248, 51, 128, 2, 235, 193, 3, 194, 178, 195, 248, 36, 33, 1, 49, 8, ++ 154, 1, 240, 63, 1, 194, 248, 28, 17, 201, 248, 48, 162, 24, 240, 64, ++ 119, 3, 209, 95, 250, 136, 243, 27, 147, 3, 224, 64, 70, 41, 240, 190, ++ 251, 27, 144, 19, 152, 2, 40, 0, 208, 136, 185, 180, 248, 88, 52, 14, ++ 153, 153, 66, 2, 220, 179, 105, 91, 1, 12, 213, 9, 154, 17, 152, 19, ++ 121, 3, 240, 1, 3, 0, 43, 8, 191, 1, 32, 23, 144, 4, 224, 17, 153, 23, ++ 145, 1, 224, 17, 154, 23, 146, 35, 106, 89, 125, 65, 177, 15, 155, 51, ++ 177, 47, 185, 136, 74, 95, 250, 136, 243, 211, 86, 0, 43, 7, 219, 35, ++ 104, 147, 248, 79, 48, 152, 7, 39, 208, 55, 179, 21, 152, 32, 179, 51, ++ 154, 1, 42, 14, 217, 15, 155, 0, 43, 12, 191, 79, 240, 48, 10, 79, 240, ++ 22, 10, 179, 105, 74, 244, 128, 58, 35, 240, 0, 99, 179, 97, 208, 70, ++ 18, 224, 137, 177, 15, 152, 120, 177, 103, 185, 8, 240, 127, 3, 2, 43, ++ 10, 208, 4, 43, 8, 208, 11, 43, 6, 208, 22, 43, 24, 191, 79, 240, 1, ++ 11, 1, 224, 79, 240, 1, 11, 24, 240, 64, 113, 15, 145, 26, 209, 8, 240, ++ 127, 3, 22, 43, 22, 216, 108, 74, 154, 64, 19, 213, 20, 154, 98, 177, ++ 95, 250, 136, 243, 2, 43, 11, 208, 217, 248, 16, 48, 147, 249, 24, 49, ++ 19, 241, 255, 51, 24, 191, 1, 35, 0, 224, 20, 155, 13, 147, 1, 224, ++ 15, 152, 13, 144, 26, 240, 64, 113, 22, 145, 27, 209, 10, 240, 127, ++ 3, 22, 43, 23, 216, 92, 74, 154, 64, 20, 213, 20, 154, 106, 177, 95, ++ 250, 138, 243, 2, 43, 12, 208, 217, 248, 16, 48, 147, 249, 24, 33, 18, ++ 241, 255, 50, 24, 191, 1, 34, 16, 146, 4, 224, 22, 155, 16, 147, 1, ++ 224, 22, 152, 16, 144, 19, 153, 217, 248, 4, 48, 2, 41, 8, 191, 201, ++ 248, 104, 129, 19, 244, 128, 51, 74, 208, 148, 248, 17, 50, 0, 43, 70, ++ 208, 148, 248, 21, 50, 0, 43, 66, 208, 21, 154, 3, 42, 48, 208, 15, ++ 155, 75, 185, 8, 240, 127, 3, 2, 43, 44, 208, 4, 43, 44, 208, 11, 43, ++ 45, 208, 22, 43, 46, 208, 9, 152, 3, 121, 19, 240, 1, 3, 43, 209, 11, ++ 153, 1, 240, 252, 2, 136, 42, 41, 209, 52, 154, 3, 42, 38, 216, 179, ++ 105, 28, 152, 67, 244, 128, 83, 179, 97, 7, 155, 9, 153, 0, 40, 12, ++ 191, 24, 34, 30, 34, 67, 244, 160, 67, 7, 147, 139, 90, 35, 240, 96, ++ 3, 27, 4, 27, 12, 67, 240, 32, 3, 139, 82, 1, 34, 7, 224, 0, 35, 12, ++ 224, 15, 152, 8, 224, 15, 153, 10, 145, 8, 224, 15, 154, 10, 146, 5, ++ 224, 15, 155, 2, 224, 0, 32, 10, 144, 0, 224, 10, 147, 29, 153, 32, ++ 70, 0, 145, 14, 154, 65, 70, 11, 155, 22, 240, 34, 217, 34, 175, 32, ++ 70, 81, 70, 14, 154, 11, 155, 0, 151, 22, 240, 26, 217, 6, 34, 165, ++ 241, 64, 0, 57, 70, 242, 247, 244, 255, 22, 154, 98, 185, 10, 240, 127, ++ 3, 22, 43, 8, 216, 23, 74, 154, 64, 5, 213, 14, 155, 5, 248, 60, 60, ++ 27, 10, 5, 248, 59, 60, 179, 105, 15, 153, 90, 5, 18, 213, 145, 177, ++ 54, 154, 34, 177, 18, 122, 4, 42, 1, 208, 11, 42, 28, 209, 67, 244, ++ 0, 99, 179, 97, 23, 152, 148, 248, 190, 50, 0, 43, 24, 191, 1, 32, 23, ++ 144, 17, 224, 129, 185, 6, 74, 95, 250, 136, 243, 211, 86, 0, 43, 10, ++ 218, 21, 248, 6, 60, 3, 240, 15, 3, 20, 147, 7, 224, 0, 191, 224, 248, ++ 135, 0, 0, 2, 16, 40, 21, 248, 6, 44, 20, 146, 11, 155, 164, 43, 20, ++ 208, 9, 152, 3, 121, 219, 7, 16, 212, 10, 153, 129, 185, 179, 105, 32, ++ 70, 95, 5, 65, 70, 2, 213, 13, 240, 83, 223, 3, 224, 13, 154, 53, 155, ++ 22, 240, 158, 216, 9, 154, 80, 128, 20, 224, 10, 155, 83, 177, 65, 70, ++ 32, 70, 13, 154, 64, 246, 42, 19, 21, 240, 114, 222, 9, 153, 128, 178, ++ 2, 48, 72, 128, 11, 154, 164, 42, 4, 209, 9, 152, 67, 136, 37, 248, ++ 58, 60, 25, 224, 9, 153, 11, 121, 217, 7, 1, 212, 10, 154, 42, 177, ++ 0, 35, 5, 248, 58, 60, 5, 248, 57, 60, 13, 224, 179, 105, 32, 70, 90, ++ 5, 81, 70, 2, 213, 13, 240, 35, 223, 3, 224, 16, 154, 53, 155, 22, 240, ++ 110, 216, 37, 248, 58, 12, 178, 105, 147, 5, 9, 213, 179, 140, 37, 248, ++ 52, 60, 243, 140, 37, 248, 50, 60, 7, 155, 67, 244, 0, 83, 7, 147, 50, ++ 152, 24, 185, 7, 153, 65, 240, 8, 1, 7, 145, 9, 152, 3, 121, 223, 7, ++ 18, 212, 208, 4, 16, 212, 148, 248, 20, 50, 11, 177, 81, 6, 11, 212, ++ 82, 5, 5, 212, 26, 153, 25, 177, 25, 154, 146, 248, 40, 48, 27, 185, ++ 7, 155, 67, 240, 1, 3, 7, 147, 146, 75, 52, 152, 19, 153, 24, 92, 2, ++ 41, 21, 144, 28, 209, 52, 154, 3, 42, 25, 216, 148, 248, 17, 50, 179, ++ 177, 27, 155, 4, 43, 19, 217, 212, 248, 52, 1, 11, 240, 120, 254, 112, ++ 185, 25, 152, 21, 153, 0, 235, 65, 3, 155, 139, 19, 177, 179, 105, 91, ++ 5, 5, 213, 17, 154, 26, 185, 7, 155, 67, 244, 128, 83, 7, 147, 35, 106, ++ 24, 105, 30, 240, 46, 253, 0, 244, 96, 80, 176, 245, 192, 95, 3, 209, ++ 7, 152, 64, 244, 128, 112, 7, 144, 12, 153, 25, 177, 7, 154, 66, 244, ++ 0, 66, 7, 146, 7, 155, 37, 248, 118, 60, 54, 152, 16, 179, 148, 248, ++ 148, 50, 19, 187, 8, 153, 10, 109, 18, 240, 8, 2, 33, 209, 3, 122, 11, ++ 43, 6, 209, 35, 104, 147, 248, 177, 48, 211, 177, 131, 121, 7, 43, 20, ++ 216, 54, 154, 147, 121, 34, 104, 210, 248, 188, 32, 147, 66, 15, 210, ++ 178, 105, 151, 0, 15, 212, 54, 152, 2, 123, 2, 240, 7, 2, 66, 234, 3, ++ 18, 3, 224, 54, 153, 7, 145, 7, 224, 0, 34, 7, 146, 4, 224, 0, 35, 7, ++ 147, 1, 224, 0, 32, 7, 144, 16, 153, 75, 30, 219, 178, 1, 43, 4, 216, ++ 7, 154, 66, 244, 0, 83, 155, 178, 7, 147, 165, 241, 114, 0, 9, 153, ++ 2, 34, 242, 247, 206, 254, 0, 35, 5, 248, 112, 60, 5, 248, 111, 60, ++ 5, 248, 74, 60, 5, 248, 73, 60, 54, 155, 0, 43, 47, 208, 148, 248, 148, ++ 50, 0, 43, 43, 209, 8, 152, 3, 109, 24, 7, 39, 212, 54, 153, 11, 122, ++ 11, 43, 6, 209, 35, 104, 147, 248, 177, 48, 251, 177, 139, 121, 7, 43, ++ 28, 216, 54, 155, 154, 121, 35, 104, 211, 248, 188, 48, 154, 66, 21, ++ 210, 179, 105, 153, 0, 18, 212, 28, 152, 24, 185, 9, 153, 1, 241, 24, ++ 2, 2, 224, 9, 155, 3, 241, 30, 2, 26, 152, 0, 177, 2, 50, 0, 35, 0, ++ 147, 32, 70, 24, 153, 54, 155, 32, 240, 116, 222, 9, 153, 6, 34, 4, ++ 49, 165, 241, 80, 0, 19, 145, 242, 247, 138, 254, 189, 248, 152, 48, ++ 37, 248, 42, 60, 212, 248, 72, 1, 8, 153, 77, 240, 9, 221, 53, 248, ++ 48, 60, 128, 178, 67, 234, 0, 35, 37, 248, 48, 60, 0, 35, 5, 248, 40, ++ 60, 5, 248, 39, 60, 5, 248, 38, 60, 5, 248, 37, 60, 5, 248, 36, 60, ++ 5, 248, 35, 60, 5, 248, 34, 60, 5, 248, 33, 60, 5, 248, 32, 60, 5, 248, ++ 31, 60, 23, 154, 26, 185, 187, 241, 0, 15, 1, 209, 225, 224, 155, 70, ++ 0, 34, 65, 70, 8, 152, 29, 240, 107, 221, 0, 34, 6, 144, 81, 70, 8, ++ 152, 29, 240, 101, 221, 6, 155, 8, 144, 19, 240, 64, 115, 24, 147, 6, ++ 209, 6, 153, 21, 75, 200, 178, 27, 86, 0, 43, 3, 218, 20, 224, 6, 152, ++ 41, 240, 13, 249, 2, 56, 24, 191, 1, 32, 112, 177, 217, 248, 16, 48, ++ 147, 249, 24, 49, 1, 43, 10, 208, 7, 154, 66, 244, 128, 67, 155, 178, ++ 7, 147, 1, 35, 12, 147, 4, 224, 24, 152, 12, 144, 1, 224, 0, 33, 12, ++ 145, 8, 155, 19, 240, 64, 114, 9, 209, 216, 178, 3, 75, 27, 86, 0, 43, ++ 7, 218, 29, 224, 84, 194, 135, 0, 224, 248, 135, 0, 8, 152, 41, 240, ++ 229, 248, 2, 56, 24, 191, 1, 32, 120, 177, 217, 248, 16, 48, 147, 249, ++ 24, 49, 1, 43, 11, 208, 7, 152, 1, 33, 111, 234, 64, 67, 111, 234, 83, ++ 67, 155, 178, 7, 147, 17, 145, 3, 224, 17, 144, 1, 224, 0, 34, 17, 146, ++ 53, 248, 118, 60, 187, 241, 0, 15, 2, 208, 67, 244, 0, 99, 1, 224, 67, ++ 240, 6, 3, 37, 248, 118, 60, 187, 241, 0, 15, 12, 191, 79, 240, 20, ++ 12, 79, 240, 14, 12, 165, 241, 30, 3, 98, 70, 0, 147, 32, 70, 6, 153, ++ 11, 155, 205, 248, 20, 192, 21, 240, 5, 223, 221, 248, 20, 192, 36, ++ 175, 98, 70, 11, 155, 32, 70, 8, 153, 0, 151, 21, 240, 251, 222, 57, ++ 70, 6, 34, 165, 241, 72, 0, 242, 247, 213, 253, 12, 152, 13, 153, 14, ++ 154, 165, 241, 24, 3, 11, 147, 0, 144, 1, 145, 2, 146, 0, 39, 89, 70, ++ 6, 154, 67, 70, 32, 70, 3, 151, 21, 240, 2, 223, 37, 248, 22, 12, 17, ++ 155, 16, 152, 14, 153, 0, 147, 1, 144, 2, 145, 32, 70, 89, 70, 8, 154, ++ 83, 70, 3, 151, 21, 240, 243, 222, 37, 248, 66, 12, 165, 241, 20, 0, ++ 187, 241, 0, 15, 9, 208, 111, 240, 59, 3, 5, 248, 24, 60, 5, 248, 23, ++ 124, 9, 154, 2, 241, 10, 1, 14, 224, 111, 240, 75, 3, 5, 248, 24, 60, ++ 5, 248, 23, 188, 19, 153, 6, 34, 242, 247, 154, 253, 9, 155, 165, 241, ++ 14, 0, 3, 241, 10, 1, 6, 34, 242, 247, 146, 253, 20, 152, 24, 154, 129, ++ 178, 82, 185, 6, 152, 159, 74, 195, 178, 211, 86, 0, 43, 4, 218, 21, ++ 248, 30, 60, 3, 240, 15, 3, 1, 224, 21, 248, 30, 60, 27, 2, 25, 67, ++ 20, 145, 31, 224, 89, 70, 6, 34, 165, 241, 30, 0, 244, 243, 247, 240, ++ 89, 70, 16, 34, 165, 241, 24, 0, 244, 243, 241, 240, 165, 241, 72, 0, ++ 89, 70, 6, 34, 244, 243, 235, 240, 5, 248, 66, 188, 5, 248, 65, 188, ++ 205, 248, 32, 176, 205, 248, 24, 176, 205, 248, 44, 176, 205, 248, 68, ++ 176, 205, 248, 48, 176, 179, 105, 90, 5, 15, 213, 15, 153, 105, 177, ++ 40, 171, 0, 34, 35, 248, 2, 45, 0, 147, 212, 248, 52, 1, 73, 70, 66, ++ 70, 14, 155, 13, 240, 239, 255, 5, 248, 67, 12, 7, 155, 37, 248, 116, ++ 60, 20, 152, 37, 248, 100, 12, 22, 153, 177, 241, 128, 127, 11, 208, ++ 49, 185, 10, 240, 127, 3, 22, 43, 2, 216, 119, 74, 154, 64, 1, 212, ++ 1, 32, 2, 224, 22, 152, 0, 224, 2, 32, 6, 154, 128, 178, 2, 240, 64, ++ 115, 179, 241, 128, 127, 11, 208, 51, 185, 2, 240, 127, 2, 22, 42, 2, ++ 216, 109, 73, 145, 64, 0, 212, 1, 35, 155, 0, 155, 178, 0, 224, 8, 35, ++ 8, 153, 24, 67, 1, 240, 64, 115, 179, 241, 128, 127, 11, 208, 51, 185, ++ 1, 240, 127, 2, 22, 42, 2, 216, 99, 73, 145, 64, 0, 212, 1, 35, 27, ++ 1, 159, 178, 0, 224, 32, 39, 35, 106, 7, 67, 24, 105, 30, 240, 20, 251, ++ 192, 178, 71, 234, 0, 39, 37, 248, 98, 124, 15, 154, 178, 241, 128, ++ 127, 12, 208, 50, 185, 8, 240, 127, 3, 22, 43, 2, 216, 85, 74, 154, ++ 64, 1, 212, 1, 35, 0, 224, 15, 155, 155, 178, 0, 224, 2, 35, 13, 152, ++ 173, 248, 154, 48, 66, 30, 210, 178, 1, 42, 9, 216, 67, 240, 16, 3, ++ 173, 248, 154, 48, 35, 104, 211, 248, 136, 48, 154, 105, 1, 50, 154, ++ 97, 65, 70, 32, 70, 189, 248, 154, 112, 47, 240, 155, 254, 179, 105, ++ 7, 67, 185, 178, 27, 1, 173, 248, 154, 16, 14, 213, 35, 104, 147, 248, ++ 229, 48, 83, 177, 35, 106, 24, 105, 31, 240, 20, 252, 35, 106, 13, 241, ++ 154, 1, 24, 105, 18, 154, 31, 240, 22, 252, 189, 248, 154, 48, 65, 70, ++ 37, 248, 110, 60, 180, 248, 72, 36, 32, 70, 27, 240, 198, 221, 37, 248, ++ 108, 12, 81, 70, 32, 70, 180, 248, 72, 36, 27, 240, 190, 221, 37, 248, ++ 106, 12, 23, 153, 17, 185, 187, 241, 0, 15, 15, 208, 6, 153, 180, 248, ++ 72, 36, 32, 70, 27, 240, 177, 221, 37, 248, 104, 12, 8, 153, 32, 70, ++ 180, 248, 72, 36, 27, 240, 169, 221, 37, 248, 102, 12, 15, 154, 74, ++ 177, 13, 155, 4, 43, 6, 209, 32, 70, 65, 70, 14, 154, 21, 240, 13, 220, ++ 37, 248, 56, 12, 22, 152, 72, 177, 16, 153, 4, 41, 6, 209, 32, 70, 81, ++ 70, 14, 154, 21, 240, 1, 220, 37, 248, 54, 12, 217, 248, 4, 48, 88, ++ 6, 64, 241, 174, 128, 26, 154, 0, 42, 0, 240, 170, 128, 25, 152, 21, ++ 153, 0, 235, 65, 3, 155, 139, 0, 43, 123, 208, 179, 105, 89, 5, 0, 241, ++ 159, 128, 50, 154, 0, 42, 64, 240, 155, 128, 14, 155, 32, 70, 65, 70, ++ 13, 154, 21, 240, 61, 219, 11, 155, 9, 144, 171, 177, 6, 153, 12, 154, ++ 32, 70, 13, 240, 115, 218, 8, 153, 7, 70, 17, 154, 32, 70, 13, 240, ++ 109, 218, 11, 153, 177, 248, 2, 176, 187, 68, 53, 248, 66, 124, 27, ++ 224, 224, 248, 135, 0, 0, 2, 16, 40, 10, 154, 186, 185, 65, 70, 13, ++ 154, 10, 155, 32, 70, 21, 240, 60, 221, 9, 155, 81, 70, 0, 235, 3, 11, ++ 16, 154, 14, 155, 32, 70, 21, 240, 19, 219, 81, 70, 7, 70, 16, 154, ++ 32, 70, 10, 155, 21, 240, 44, 221, 199, 25, 2, 224, 221, 248, 36, 176, ++ 11, 159, 31, 250, 139, 242, 37, 248, 112, 44, 37, 248, 74, 124, 25, ++ 152, 21, 153, 0, 235, 65, 3, 155, 139, 9, 152, 195, 24, 155, 26, 155, ++ 178, 26, 4, 25, 212, 32, 70, 65, 70, 13, 154, 13, 240, 49, 218, 255, ++ 40, 5, 217, 180, 248, 74, 36, 144, 66, 56, 191, 2, 70, 1, 224, 79, 244, ++ 128, 114, 52, 153, 146, 178, 4, 235, 65, 3, 179, 248, 76, 52, 147, 66, ++ 2, 208, 32, 70, 14, 240, 58, 218, 35, 104, 147, 248, 69, 48, 0, 43, ++ 46, 208, 52, 154, 3, 42, 43, 216, 212, 248, 100, 1, 21, 153, 90, 70, ++ 35, 224, 35, 104, 147, 248, 69, 48, 19, 179, 52, 155, 3, 43, 31, 216, ++ 26, 72, 11, 153, 199, 92, 32, 70, 57, 177, 12, 154, 6, 153, 13, 240, ++ 253, 217, 11, 155, 90, 136, 130, 24, 12, 224, 65, 70, 13, 154, 14, 155, ++ 21, 240, 182, 218, 13, 154, 5, 70, 65, 70, 32, 70, 11, 155, 21, 240, ++ 207, 220, 66, 25, 212, 248, 100, 1, 57, 70, 75, 70, 59, 240, 140, 223, ++ 179, 105, 189, 248, 152, 0, 67, 240, 132, 3, 179, 97, 41, 176, 189, ++ 232, 240, 143, 212, 248, 116, 36, 40, 244, 128, 8, 146, 249, 19, 32, ++ 42, 244, 128, 10, 1, 42, 127, 244, 241, 169, 255, 247, 249, 185, 84, ++ 194, 135, 0, 45, 233, 240, 79, 147, 176, 157, 248, 120, 112, 6, 70, ++ 13, 151, 157, 248, 132, 112, 221, 248, 116, 192, 11, 151, 221, 248, ++ 128, 128, 119, 104, 0, 32, 12, 70, 10, 146, 154, 70, 221, 248, 112, ++ 144, 173, 248, 68, 0, 173, 248, 70, 0, 220, 248, 16, 80, 12, 151, 184, ++ 241, 0, 15, 50, 208, 152, 248, 8, 48, 2, 43, 46, 209, 214, 248, 180, ++ 49, 0, 43, 19, 218, 150, 248, 148, 50, 131, 185, 43, 109, 24, 7, 13, ++ 212, 50, 104, 152, 248, 6, 48, 210, 248, 188, 32, 147, 66, 6, 210, 3, ++ 43, 4, 217, 11, 43, 2, 216, 186, 241, 1, 15, 22, 208, 163, 104, 12, ++ 159, 3, 147, 34, 155, 0, 151, 11, 159, 6, 147, 48, 104, 33, 70, 10, ++ 154, 83, 70, 205, 248, 8, 192, 205, 248, 36, 192, 1, 149, 205, 248, ++ 16, 128, 5, 151, 91, 240, 70, 220, 221, 248, 36, 192, 21, 177, 149, ++ 248, 37, 51, 203, 185, 11, 159, 10, 241, 255, 51, 1, 151, 31, 159, 13, ++ 241, 70, 2, 3, 151, 10, 159, 2, 146, 251, 26, 98, 70, 48, 70, 33, 70, ++ 24, 191, 1, 35, 205, 248, 36, 192, 205, 248, 0, 128, 12, 240, 196, 219, ++ 221, 248, 36, 192, 131, 70, 1, 224, 79, 240, 0, 11, 185, 241, 0, 15, ++ 25, 208, 220, 248, 164, 49, 220, 248, 4, 32, 217, 7, 129, 75, 88, 191, ++ 9, 241, 28, 9, 2, 234, 3, 3, 72, 191, 9, 241, 34, 9, 11, 177, 9, 241, ++ 2, 9, 184, 241, 0, 15, 5, 208, 152, 249, 14, 32, 152, 249, 15, 48, 211, ++ 24, 153, 68, 214, 248, 104, 52, 27, 104, 235, 92, 27, 177, 220, 248, ++ 4, 48, 195, 243, 128, 3, 10, 159, 0, 34, 141, 232, 128, 4, 5, 146, 31, ++ 159, 17, 170, 6, 146, 33, 70, 98, 70, 48, 70, 2, 151, 205, 248, 36, ++ 192, 205, 248, 12, 144, 205, 248, 16, 128, 13, 240, 254, 220, 189, 248, ++ 68, 16, 171, 121, 189, 248, 70, 112, 15, 145, 221, 248, 36, 192, 163, ++ 185, 149, 248, 148, 48, 139, 177, 185, 241, 0, 15, 14, 209, 13, 154, ++ 98, 177, 79, 246, 255, 115, 152, 66, 5, 208, 163, 127, 35, 240, 15, ++ 3, 67, 240, 5, 3, 163, 119, 0, 35, 133, 248, 148, 48, 184, 241, 0, 15, ++ 60, 208, 150, 248, 148, 50, 195, 185, 43, 109, 26, 7, 21, 212, 152, ++ 248, 8, 48, 11, 43, 7, 209, 51, 104, 147, 248, 177, 48, 107, 177, 152, ++ 248, 6, 48, 7, 43, 9, 216, 51, 104, 152, 248, 6, 32, 211, 248, 188, ++ 48, 154, 66, 2, 210, 163, 105, 155, 0, 32, 213, 189, 248, 68, 144, 163, ++ 104, 9, 241, 118, 9, 75, 68, 163, 96, 163, 137, 48, 70, 201, 235, 3, ++ 3, 163, 129, 12, 153, 43, 70, 34, 70, 205, 248, 0, 192, 205, 248, 36, ++ 192, 205, 248, 4, 128, 92, 240, 156, 220, 163, 104, 221, 248, 36, 192, ++ 201, 235, 3, 3, 163, 96, 163, 137, 153, 68, 164, 248, 12, 144, 171, ++ 121, 51, 185, 213, 248, 72, 51, 0, 43, 66, 208, 155, 123, 216, 7, 63, ++ 213, 31, 155, 4, 43, 35, 208, 156, 248, 231, 48, 0, 43, 56, 208, 10, ++ 152, 10, 241, 255, 51, 193, 26, 48, 74, 31, 152, 75, 66, 67, 235, 1, ++ 3, 18, 92, 156, 248, 218, 16, 48, 70, 81, 250, 2, 242, 18, 240, 1, 15, ++ 0, 147, 97, 70, 34, 70, 91, 70, 205, 248, 36, 192, 2, 208, 42, 240, ++ 158, 222, 1, 224, 43, 240, 247, 216, 221, 248, 36, 192, 24, 224, 181, ++ 248, 90, 0, 205, 248, 36, 192, 245, 243, 4, 243, 221, 248, 36, 192, ++ 72, 177, 171, 110, 90, 28, 6, 208, 5, 235, 131, 3, 219, 110, 19, 177, ++ 27, 122, 4, 43, 5, 208, 187, 248, 0, 48, 67, 244, 0, 83, 171, 248, 0, ++ 48, 13, 153, 41, 177, 220, 248, 164, 49, 3, 240, 5, 3, 1, 43, 31, 208, ++ 214, 248, 160, 1, 3, 120, 219, 177, 186, 241, 1, 15, 24, 209, 148, 249, ++ 30, 48, 0, 43, 20, 219, 149, 248, 37, 51, 139, 185, 15, 154, 97, 70, ++ 187, 24, 189, 248, 68, 32, 31, 159, 2, 146, 189, 248, 70, 32, 118, 51, ++ 0, 151, 11, 159, 3, 146, 155, 178, 34, 70, 1, 151, 101, 240, 185, 223, ++ 19, 176, 189, 232, 240, 143, 64, 0, 1, 0, 84, 194, 135, 0, 136, 138, ++ 139, 105, 4, 56, 128, 178, 27, 26, 27, 12, 27, 4, 24, 67, 112, 71, 0, ++ 0, 45, 233, 240, 65, 144, 176, 12, 70, 6, 70, 144, 70, 255, 247, 238, ++ 255, 64, 34, 5, 70, 0, 33, 104, 70, 243, 243, 156, 245, 163, 136, 33, ++ 70, 195, 243, 64, 19, 48, 70, 205, 248, 22, 80, 205, 248, 14, 48, 73, ++ 240, 1, 216, 227, 138, 205, 248, 30, 0, 173, 248, 8, 48, 3, 244, 64, ++ 67, 163, 245, 64, 66, 83, 66, 67, 235, 2, 3, 10, 51, 86, 248, 35, 48, ++ 24, 105, 30, 240, 166, 252, 216, 248, 8, 112, 205, 248, 34, 0, 57, 70, ++ 32, 70, 40, 240, 215, 253, 251, 136, 5, 70, 3, 240, 240, 3, 27, 9, 8, ++ 43, 1, 208, 12, 43, 30, 209, 163, 136, 3, 240, 3, 3, 2, 43, 25, 209, ++ 251, 120, 27, 7, 8, 213, 221, 248, 46, 48, 198, 248, 52, 86, 67, 240, ++ 1, 3, 205, 248, 46, 48, 13, 224, 59, 120, 122, 120, 26, 67, 187, 120, ++ 19, 67, 7, 209, 221, 248, 46, 48, 214, 248, 52, 86, 67, 240, 2, 3, 205, ++ 248, 46, 48, 99, 138, 216, 7, 5, 213, 221, 248, 46, 48, 67, 240, 12, ++ 3, 205, 248, 46, 48, 5, 240, 64, 119, 183, 241, 128, 127, 60, 209, 189, ++ 248, 8, 32, 141, 248, 12, 80, 2, 244, 96, 83, 179, 245, 192, 95, 17, ++ 209, 5, 244, 224, 35, 179, 245, 128, 63, 6, 209, 18, 244, 224, 111, ++ 1, 209, 2, 35, 5, 224, 4, 35, 3, 224, 179, 245, 0, 63, 2, 209, 1, 35, ++ 141, 248, 13, 48, 41, 2, 5, 213, 157, 248, 13, 48, 67, 240, 8, 3, 141, ++ 248, 13, 48, 106, 2, 5, 213, 157, 248, 13, 48, 67, 240, 64, 3, 141, ++ 248, 13, 48, 235, 2, 5, 213, 157, 248, 13, 48, 67, 240, 16, 3, 141, ++ 248, 13, 48, 48, 70, 157, 248, 13, 16, 157, 248, 12, 32, 14, 240, 241, ++ 219, 173, 248, 10, 0, 8, 224, 40, 70, 40, 240, 75, 252, 79, 244, 250, ++ 115, 144, 251, 243, 243, 173, 248, 10, 48, 35, 136, 6, 59, 205, 248, ++ 18, 48, 227, 136, 27, 10, 205, 248, 26, 48, 189, 248, 8, 48, 19, 244, ++ 64, 79, 12, 191, 179, 106, 243, 106, 27, 137, 1, 147, 1, 155, 7, 43, ++ 13, 216, 79, 240, 104, 66, 154, 64, 11, 212, 79, 240, 64, 114, 154, ++ 64, 5, 212, 79, 240, 128, 98, 154, 64, 1, 213, 2, 35, 0, 224, 4, 35, ++ 1, 147, 47, 187, 5, 240, 127, 3, 22, 43, 15, 216, 34, 74, 154, 64, 12, ++ 213, 1, 35, 173, 248, 42, 48, 163, 136, 173, 248, 44, 112, 3, 240, 128, ++ 3, 0, 43, 12, 191, 2, 35, 1, 35, 30, 224, 27, 75, 237, 178, 91, 87, ++ 0, 43, 12, 218, 2, 35, 173, 248, 42, 48, 0, 35, 173, 248, 44, 48, 1, ++ 35, 173, 248, 38, 48, 0, 35, 173, 248, 40, 48, 14, 224, 3, 35, 173, ++ 248, 42, 48, 0, 35, 173, 248, 44, 48, 99, 137, 27, 5, 27, 13, 0, 43, ++ 12, 191, 4, 35, 3, 35, 205, 248, 38, 48, 35, 138, 216, 6, 3, 213, 0, ++ 154, 66, 240, 128, 2, 0, 146, 217, 7, 3, 213, 0, 155, 67, 240, 1, 3, ++ 0, 147, 176, 104, 105, 70, 66, 70, 252, 247, 119, 253, 16, 176, 189, ++ 232, 240, 129, 0, 2, 16, 40, 224, 248, 135, 0, 248, 181, 31, 70, 0, ++ 35, 59, 112, 1, 35, 123, 112, 12, 70, 22, 70, 5, 70, 16, 240, 185, 222, ++ 64, 244, 128, 83, 155, 178, 14, 40, 140, 191, 79, 244, 64, 64, 0, 32, ++ 24, 67, 3, 10, 67, 234, 0, 32, 120, 128, 33, 70, 40, 70, 72, 240, 220, ++ 222, 3, 6, 0, 244, 127, 66, 67, 234, 16, 99, 67, 234, 2, 35, 0, 244, ++ 127, 0, 67, 234, 16, 32, 120, 96, 33, 70, 40, 70, 255, 247, 168, 254, ++ 0, 186, 184, 96, 49, 70, 32, 70, 40, 240, 182, 252, 0, 186, 248, 96, ++ 248, 189, 56, 181, 29, 70, 20, 70, 255, 247, 154, 254, 43, 104, 131, ++ 66, 2, 210, 35, 104, 1, 59, 35, 96, 40, 96, 56, 189, 240, 181, 4, 104, ++ 173, 245, 59, 125, 5, 70, 0, 33, 208, 248, 244, 96, 79, 244, 55, 114, ++ 1, 168, 185, 145, 39, 106, 243, 243, 55, 244, 42, 122, 66, 177, 115, ++ 142, 19, 244, 64, 79, 12, 191, 0, 35, 1, 35, 10, 51, 84, 248, 35, 112, ++ 123, 108, 184, 147, 0, 43, 59, 208, 3, 240, 64, 113, 177, 241, 128, ++ 127, 38, 209, 19, 244, 224, 47, 27, 209, 10, 177, 112, 142, 3, 224, ++ 35, 106, 24, 105, 29, 240, 167, 254, 0, 244, 96, 80, 176, 245, 128, ++ 95, 184, 155, 2, 209, 67, 244, 128, 51, 10, 224, 176, 245, 192, 95, ++ 2, 209, 67, 244, 0, 51, 4, 224, 176, 245, 32, 95, 2, 209, 67, 244, 128, ++ 35, 184, 147, 148, 249, 32, 50, 1, 43, 3, 209, 184, 155, 67, 244, 0, ++ 3, 184, 147, 184, 153, 32, 70, 33, 244, 64, 113, 184, 145, 46, 240, ++ 53, 254, 184, 156, 5, 70, 32, 70, 40, 240, 210, 250, 40, 26, 68, 234, ++ 0, 32, 15, 224, 40, 70, 1, 169, 184, 170, 185, 171, 22, 240, 32, 252, ++ 184, 152, 24, 185, 40, 70, 25, 240, 239, 222, 3, 224, 148, 248, 229, ++ 53, 3, 177, 185, 152, 13, 245, 59, 125, 240, 189, 45, 233, 247, 67, ++ 136, 70, 17, 70, 5, 70, 23, 70, 22, 240, 191, 249, 6, 70, 0, 40, 91, ++ 208, 213, 248, 124, 2, 0, 40, 87, 208, 54, 33, 65, 240, 55, 218, 4, ++ 70, 0, 40, 81, 208, 0, 241, 24, 9, 6, 241, 194, 1, 6, 34, 72, 70, 242, ++ 247, 60, 248, 54, 35, 5, 34, 196, 248, 48, 144, 99, 96, 98, 97, 213, ++ 248, 124, 2, 105, 104, 65, 240, 45, 218, 160, 99, 56, 185, 213, 248, ++ 124, 2, 33, 70, 3, 176, 189, 232, 240, 67, 65, 240, 45, 154, 123, 121, ++ 128, 248, 1, 128, 3, 112, 0, 35, 131, 112, 214, 248, 204, 48, 25, 5, ++ 1, 213, 1, 35, 131, 112, 150, 248, 68, 48, 195, 112, 59, 121, 1, 43, ++ 15, 209, 178, 121, 214, 248, 204, 48, 50, 177, 3, 244, 0, 83, 0, 43, ++ 12, 191, 1, 35, 3, 35, 5, 224, 19, 244, 0, 83, 24, 191, 4, 35, 0, 224, ++ 2, 35, 3, 113, 213, 248, 108, 50, 40, 70, 219, 104, 33, 70, 0, 147, ++ 50, 70, 59, 70, 9, 240, 7, 223, 40, 70, 33, 70, 3, 176, 189, 232, 240, ++ 67, 28, 240, 42, 153, 3, 176, 189, 232, 240, 131, 45, 233, 240, 79, ++ 16, 41, 171, 176, 4, 70, 13, 70, 147, 70, 0, 240, 161, 128, 208, 248, ++ 104, 49, 219, 121, 1, 43, 20, 209, 176, 248, 148, 53, 12, 33, 42, 170, ++ 173, 248, 36, 48, 109, 35, 66, 248, 140, 29, 8, 147, 0, 35, 3, 146, ++ 4, 145, 173, 248, 38, 48, 0, 149, 1, 147, 2, 147, 89, 70, 69, 34, 84, ++ 224, 3, 104, 147, 248, 23, 49, 0, 43, 72, 208, 208, 248, 16, 35, 12, ++ 38, 16, 104, 0, 35, 11, 224, 145, 104, 128, 54, 177, 248, 108, 16, 12, ++ 41, 3, 217, 9, 57, 33, 240, 3, 1, 118, 24, 1, 51, 4, 50, 131, 66, 241, ++ 209, 48, 70, 250, 247, 74, 255, 129, 70, 0, 40, 103, 208, 0, 241, 12, ++ 7, 178, 70, 79, 240, 0, 8, 17, 224, 1, 33, 8, 241, 2, 2, 0, 145, 83, ++ 248, 34, 16, 32, 70, 58, 70, 83, 70, 20, 240, 208, 218, 80, 185, 123, ++ 104, 8, 241, 1, 8, 195, 235, 10, 10, 255, 24, 212, 248, 16, 51, 26, ++ 104, 144, 69, 232, 211, 201, 248, 8, 128, 0, 35, 32, 70, 89, 70, 26, ++ 34, 0, 149, 1, 147, 2, 147, 205, 248, 12, 144, 4, 150, 20, 240, 144, ++ 220, 72, 70, 250, 247, 28, 255, 8, 224, 141, 232, 10, 0, 2, 147, 17, ++ 70, 3, 147, 4, 147, 26, 34, 20, 240, 131, 220, 212, 248, 32, 51, 2, ++ 43, 4, 209, 160, 104, 212, 248, 52, 19, 8, 240, 80, 223, 8, 45, 11, ++ 208, 93, 177, 212, 248, 32, 51, 2, 43, 79, 240, 3, 3, 12, 191, 196, ++ 248, 32, 51, 196, 248, 28, 51, 24, 224, 1, 37, 32, 70, 212, 248, 24, ++ 19, 20, 240, 54, 220, 212, 248, 16, 3, 212, 248, 24, 19, 20, 240, 72, ++ 220, 212, 248, 32, 51, 2, 43, 2, 209, 196, 248, 32, 83, 5, 224, 212, ++ 248, 28, 51, 2, 43, 8, 191, 196, 248, 28, 83, 43, 176, 189, 232, 240, ++ 143, 45, 233, 240, 79, 219, 176, 221, 248, 144, 177, 8, 145, 11, 146, ++ 153, 70, 208, 248, 104, 81, 187, 248, 10, 48, 4, 70, 221, 248, 148, ++ 129, 7, 147, 157, 177, 175, 121, 151, 177, 40, 70, 89, 240, 134, 219, ++ 7, 70, 104, 177, 212, 248, 104, 6, 57, 70, 9, 241, 16, 2, 72, 240, 205, ++ 222, 1, 40, 0, 240, 206, 129, 4, 40, 1, 209, 202, 225, 47, 70, 185, ++ 248, 0, 160, 10, 240, 252, 10, 170, 241, 128, 1, 209, 241, 0, 10, 74, ++ 235, 1, 10, 186, 241, 0, 15, 14, 208, 171, 136, 90, 7, 13, 212, 8, 158, ++ 212, 248, 92, 1, 241, 138, 201, 178, 63, 240, 251, 218, 208, 241, 1, ++ 6, 56, 191, 0, 38, 2, 224, 86, 70, 0, 224, 0, 38, 168, 241, 12, 1, 0, ++ 34, 11, 241, 12, 0, 248, 247, 224, 255, 171, 104, 1, 70, 2, 43, 11, ++ 208, 27, 185, 7, 155, 155, 7, 7, 213, 154, 225, 1, 43, 64, 240, 152, ++ 129, 7, 155, 152, 7, 64, 241, 148, 129, 40, 70, 50, 70, 89, 240, 60, ++ 221, 0, 40, 0, 240, 141, 129, 43, 123, 217, 7, 9, 212, 5, 241, 12, 0, ++ 9, 241, 16, 1, 6, 34, 241, 247, 194, 254, 0, 40, 64, 240, 128, 129, ++ 9, 241, 16, 6, 7, 150, 32, 70, 13, 174, 8, 153, 7, 154, 83, 70, 205, ++ 248, 0, 176, 205, 248, 4, 128, 2, 150, 28, 240, 197, 219, 0, 40, 64, ++ 240, 110, 129, 212, 248, 104, 1, 113, 142, 89, 240, 189, 219, 0, 40, ++ 0, 240, 102, 129, 212, 248, 104, 49, 123, 177, 155, 121, 107, 177, 212, ++ 248, 80, 1, 57, 70, 82, 70, 27, 171, 205, 248, 0, 176, 205, 248, 4, ++ 128, 82, 240, 22, 217, 0, 40, 64, 240, 83, 129, 157, 248, 60, 48, 189, ++ 248, 102, 32, 0, 147, 32, 70, 7, 153, 13, 241, 61, 3, 12, 240, 114, ++ 217, 6, 70, 8, 179, 195, 136, 186, 241, 0, 15, 2, 208, 218, 5, 2, 212, ++ 62, 225, 219, 5, 24, 212, 189, 248, 94, 16, 0, 41, 0, 240, 56, 129, ++ 243, 136, 152, 7, 4, 213, 189, 248, 58, 32, 146, 7, 64, 241, 48, 129, ++ 189, 248, 58, 32, 83, 64, 152, 7, 15, 212, 115, 141, 107, 177, 27, 178, ++ 9, 178, 139, 66, 9, 219, 35, 225, 212, 248, 20, 51, 43, 177, 189, 249, ++ 94, 32, 27, 178, 154, 66, 192, 242, 27, 129, 35, 104, 147, 248, 175, ++ 48, 51, 177, 212, 248, 136, 1, 13, 169, 90, 70, 67, 70, 32, 240, 10, ++ 220, 212, 248, 104, 49, 219, 121, 1, 43, 69, 209, 171, 136, 0, 34, 173, ++ 248, 160, 32, 154, 7, 12, 213, 64, 70, 250, 247, 238, 253, 39, 144, ++ 0, 40, 0, 240, 254, 128, 89, 70, 66, 70, 241, 247, 76, 254, 173, 248, ++ 160, 128, 189, 248, 160, 0, 140, 48, 250, 247, 223, 253, 189, 248, 160, ++ 48, 5, 70, 32, 179, 1, 38, 32, 70, 13, 169, 5, 241, 12, 2, 128, 51, ++ 0, 150, 20, 240, 108, 217, 168, 185, 180, 248, 148, 53, 8, 34, 43, 129, ++ 109, 35, 107, 96, 43, 105, 110, 129, 12, 51, 43, 96, 57, 70, 0, 146, ++ 1, 144, 2, 144, 4, 147, 32, 70, 69, 34, 9, 241, 10, 3, 3, 149, 20, 240, ++ 47, 219, 40, 70, 250, 247, 187, 253, 189, 248, 160, 48, 0, 43, 0, 240, ++ 199, 128, 39, 152, 134, 224, 190, 185, 212, 248, 32, 51, 2, 43, 22, ++ 209, 8, 154, 32, 70, 211, 138, 189, 248, 102, 32, 219, 178, 2, 244, ++ 127, 66, 26, 67, 157, 248, 60, 48, 7, 153, 0, 147, 13, 241, 61, 3, 10, ++ 146, 12, 240, 4, 216, 32, 177, 171, 224, 0, 34, 10, 146, 0, 224, 10, ++ 150, 171, 136, 19, 240, 2, 3, 14, 208, 64, 70, 250, 247, 141, 253, 9, ++ 144, 0, 40, 0, 240, 157, 128, 89, 70, 66, 70, 39, 144, 241, 247, 234, ++ 253, 173, 248, 160, 128, 0, 224, 9, 147, 222, 185, 32, 70, 13, 169, ++ 252, 247, 164, 254, 0, 40, 0, 240, 137, 128, 32, 70, 11, 240, 169, 223, ++ 6, 70, 0, 40, 0, 240, 130, 128, 212, 248, 32, 51, 2, 43, 9, 209, 157, ++ 248, 60, 48, 32, 70, 0, 147, 7, 153, 10, 154, 13, 241, 61, 3, 11, 240, ++ 105, 223, 13, 170, 49, 70, 32, 70, 252, 247, 174, 255, 247, 243, 74, ++ 243, 11, 153, 112, 102, 8, 152, 40, 240, 157, 249, 8, 153, 3, 70, 32, ++ 70, 6, 147, 255, 247, 131, 251, 6, 155, 131, 70, 198, 248, 172, 0, 25, ++ 70, 32, 70, 20, 240, 97, 222, 88, 68, 198, 248, 172, 0, 212, 248, 104, ++ 1, 3, 123, 219, 7, 25, 212, 12, 48, 248, 247, 224, 253, 168, 185, 212, ++ 248, 104, 1, 89, 240, 253, 217, 1, 40, 15, 209, 0, 47, 72, 208, 215, ++ 248, 204, 16, 17, 244, 0, 81, 10, 209, 212, 248, 104, 1, 89, 240, 76, ++ 220, 5, 224, 9, 152, 250, 247, 43, 253, 58, 224, 0, 47, 56, 208, 212, ++ 248, 124, 2, 71, 33, 65, 240, 148, 216, 184, 177, 86, 174, 32, 70, 8, ++ 153, 11, 154, 51, 70, 255, 247, 118, 252, 0, 35, 0, 147, 1, 147, 2, ++ 147, 8, 241, 24, 3, 4, 147, 32, 70, 57, 70, 71, 34, 9, 241, 10, 3, 205, ++ 248, 12, 144, 5, 150, 20, 240, 141, 218, 215, 248, 204, 48, 153, 4, ++ 22, 213, 215, 248, 248, 48, 155, 177, 155, 104, 139, 177, 5, 241, 12, ++ 0, 7, 153, 6, 34, 241, 247, 75, 253, 80, 185, 186, 241, 0, 15, 7, 209, ++ 40, 70, 81, 70, 89, 240, 16, 220, 2, 224, 9, 155, 0, 43, 192, 209, 91, ++ 176, 189, 232, 240, 143, 45, 233, 247, 79, 221, 248, 48, 176, 6, 70, ++ 1, 146, 28, 70, 211, 248, 244, 112, 136, 70, 41, 185, 211, 248, 248, ++ 48, 25, 116, 132, 248, 234, 19, 4, 224, 144, 248, 198, 53, 0, 43, 64, ++ 240, 152, 128, 0, 35, 132, 248, 152, 51, 184, 241, 0, 15, 13, 208, 212, ++ 248, 252, 48, 147, 248, 60, 48, 83, 177, 187, 241, 0, 15, 7, 209, 32, ++ 70, 1, 153, 22, 240, 48, 249, 16, 177, 131, 224, 132, 248, 118, 131, ++ 214, 248, 124, 2, 16, 33, 64, 240, 14, 223, 5, 70, 0, 40, 121, 208, ++ 16, 35, 67, 96, 24, 241, 0, 3, 24, 191, 1, 35, 67, 128, 192, 248, 12, ++ 176, 163, 121, 0, 43, 96, 209, 35, 122, 0, 43, 93, 208, 34, 109, 64, ++ 242, 55, 19, 19, 64, 0, 43, 87, 208, 187, 110, 0, 43, 84, 208, 183, ++ 248, 108, 160, 186, 241, 12, 15, 79, 217, 180, 248, 90, 0, 3, 241, 12, ++ 9, 170, 241, 12, 10, 244, 243, 132, 245, 40, 177, 72, 70, 81, 70, 244, ++ 243, 9, 244, 7, 70, 216, 185, 180, 248, 90, 0, 248, 247, 39, 255, 48, ++ 177, 72, 70, 81, 70, 48, 34, 248, 247, 207, 253, 7, 70, 120, 185, 180, ++ 248, 90, 48, 179, 245, 128, 111, 2, 208, 179, 245, 0, 111, 44, 209, ++ 72, 70, 81, 70, 68, 34, 248, 247, 192, 253, 7, 70, 0, 40, 36, 208, 214, ++ 248, 108, 50, 179, 248, 90, 0, 248, 247, 9, 255, 104, 177, 184, 241, ++ 0, 15, 10, 208, 187, 241, 0, 15, 7, 208, 214, 248, 124, 2, 41, 70, 3, ++ 176, 189, 232, 240, 79, 64, 240, 196, 158, 122, 120, 214, 248, 124, ++ 2, 113, 104, 2, 50, 16, 35, 64, 240, 178, 222, 168, 99, 40, 177, 122, ++ 120, 57, 70, 2, 50, 106, 97, 241, 247, 174, 252, 48, 70, 33, 70, 42, ++ 70, 1, 155, 25, 240, 68, 217, 48, 70, 41, 70, 3, 176, 189, 232, 240, ++ 79, 27, 240, 217, 157, 3, 176, 189, 232, 240, 143, 45, 233, 240, 79, ++ 78, 104, 147, 176, 209, 248, 8, 176, 5, 70, 198, 243, 192, 64, 12, 70, ++ 3, 144, 23, 70, 153, 70, 4, 168, 198, 243, 0, 67, 0, 33, 40, 34, 38, ++ 240, 134, 70, 2, 147, 38, 244, 234, 22, 243, 243, 5, 240, 43, 240, 131, ++ 3, 212, 248, 16, 160, 102, 96, 163, 96, 0, 47, 0, 240, 208, 128, 59, ++ 120, 151, 248, 1, 128, 67, 234, 8, 40, 164, 248, 16, 129, 187, 120, ++ 132, 248, 18, 49, 70, 244, 128, 51, 99, 96, 43, 104, 147, 248, 66, 32, ++ 178, 177, 147, 248, 67, 48, 155, 177, 70, 244, 160, 38, 212, 248, 52, ++ 49, 102, 96, 147, 248, 93, 48, 123, 185, 27, 244, 0, 127, 3, 208, 148, ++ 248, 36, 48, 218, 6, 8, 213, 40, 70, 33, 70, 35, 240, 71, 221, 3, 224, ++ 40, 70, 33, 70, 35, 240, 52, 221, 162, 104, 18, 240, 0, 98, 34, 209, ++ 8, 240, 12, 3, 155, 16, 1, 43, 148, 248, 14, 1, 148, 248, 15, 17, 6, ++ 208, 3, 43, 9, 208, 67, 185, 1, 34, 132, 248, 14, 33, 1, 224, 132, 248, ++ 14, 49, 132, 248, 15, 49, 3, 224, 132, 248, 14, 33, 132, 248, 15, 33, ++ 148, 248, 14, 49, 131, 66, 7, 209, 148, 248, 15, 97, 118, 26, 24, 191, ++ 1, 38, 2, 224, 0, 38, 0, 224, 1, 38, 24, 244, 64, 127, 3, 208, 99, 104, ++ 67, 240, 128, 67, 99, 96, 24, 240, 1, 15, 3, 208, 163, 104, 67, 240, ++ 128, 3, 163, 96, 24, 240, 32, 15, 3, 208, 163, 104, 67, 240, 1, 3, 163, ++ 96, 24, 240, 64, 15, 3, 208, 163, 104, 67, 240, 2, 3, 163, 96, 163, ++ 104, 11, 240, 3, 11, 3, 240, 3, 3, 155, 69, 24, 191, 1, 38, 24, 240, ++ 16, 15, 3, 209, 99, 104, 67, 244, 128, 19, 99, 96, 24, 244, 128, 79, ++ 3, 208, 99, 104, 67, 240, 0, 115, 99, 96, 200, 243, 64, 8, 185, 241, ++ 0, 15, 42, 208, 5, 245, 54, 112, 7, 48, 73, 70, 22, 34, 241, 247, 232, ++ 251, 184, 241, 0, 15, 3, 208, 153, 248, 1, 128, 200, 243, 128, 8, 153, ++ 248, 1, 48, 27, 7, 3, 213, 99, 104, 67, 240, 128, 115, 99, 96, 153, ++ 248, 2, 48, 19, 240, 8, 3, 13, 208, 218, 248, 244, 48, 64, 246, 8, 66, ++ 91, 142, 65, 246, 16, 1, 3, 244, 64, 67, 179, 245, 64, 79, 20, 191, ++ 11, 70, 19, 70, 165, 248, 192, 50, 43, 104, 147, 249, 82, 48, 251, 177, ++ 28, 155, 235, 177, 154, 248, 6, 48, 211, 185, 28, 153, 14, 34, 14, 168, ++ 241, 247, 182, 251, 40, 70, 14, 169, 1, 34, 25, 240, 181, 221, 80, 70, ++ 14, 169, 13, 240, 209, 221, 11, 224, 40, 70, 33, 70, 6, 34, 31, 240, ++ 221, 219, 40, 70, 33, 70, 35, 240, 135, 220, 62, 70, 184, 70, 25, 224, ++ 16, 34, 249, 28, 13, 241, 37, 0, 241, 247, 154, 251, 213, 248, 116, ++ 52, 4, 168, 153, 120, 39, 240, 177, 254, 213, 248, 108, 18, 40, 70, ++ 25, 240, 141, 218, 255, 35, 1, 144, 0, 34, 4, 168, 0, 147, 1, 70, 19, ++ 70, 40, 240, 66, 248, 2, 152, 136, 177, 99, 104, 19, 244, 128, 51, 16, ++ 208, 9, 170, 0, 35, 225, 24, 18, 248, 1, 15, 145, 248, 97, 16, 136, ++ 66, 6, 209, 1, 51, 16, 43, 245, 209, 0, 35, 2, 224, 2, 155, 0, 224, ++ 1, 35, 98, 104, 2, 152, 2, 244, 128, 49, 194, 243, 0, 66, 144, 66, 0, ++ 209, 99, 177, 4, 241, 97, 0, 41, 177, 13, 241, 37, 1, 16, 34, 241, 247, ++ 94, 251, 2, 224, 16, 34, 242, 243, 218, 246, 1, 38, 184, 241, 0, 15, ++ 3, 208, 99, 104, 67, 244, 0, 35, 99, 96, 3, 155, 67, 69, 0, 209, 70, ++ 177, 213, 248, 116, 52, 147, 248, 123, 48, 27, 185, 40, 70, 33, 70, ++ 44, 240, 231, 252, 19, 176, 189, 232, 240, 143, 240, 181, 135, 176, ++ 4, 70, 13, 70, 14, 240, 202, 220, 6, 70, 0, 40, 64, 240, 133, 128, 107, ++ 28, 4, 43, 0, 242, 129, 128, 223, 232, 3, 240, 71, 3, 78, 127, 78, 0, ++ 35, 104, 0, 39, 131, 248, 79, 112, 35, 104, 131, 248, 81, 112, 212, ++ 248, 56, 3, 195, 136, 35, 240, 32, 3, 195, 128, 56, 48, 39, 240, 210, ++ 255, 37, 106, 57, 70, 5, 241, 101, 0, 16, 34, 242, 243, 152, 246, 107, ++ 108, 51, 177, 19, 240, 64, 127, 3, 208, 111, 100, 32, 70, 28, 240, 109, ++ 217, 171, 108, 35, 177, 19, 240, 64, 127, 1, 208, 0, 35, 171, 100, 0, ++ 37, 212, 248, 104, 50, 90, 89, 154, 177, 212, 248, 36, 1, 3, 169, 89, ++ 240, 234, 221, 5, 224, 0, 34, 32, 70, 19, 70, 0, 146, 255, 247, 89, ++ 254, 3, 169, 212, 248, 36, 1, 44, 240, 134, 250, 1, 70, 0, 40, 241, ++ 209, 4, 53, 32, 45, 228, 209, 55, 224, 212, 248, 116, 52, 157, 120, ++ 3, 45, 12, 191, 3, 37, 1, 37, 1, 33, 32, 70, 10, 70, 29, 240, 15, 221, ++ 3, 45, 35, 104, 1, 209, 7, 34, 0, 224, 3, 34, 131, 248, 79, 32, 212, ++ 248, 56, 3, 195, 136, 67, 240, 32, 3, 195, 128, 212, 248, 116, 52, 56, ++ 48, 25, 121, 39, 240, 235, 255, 0, 33, 32, 70, 212, 248, 56, 83, 25, ++ 240, 195, 217, 56, 53, 0, 34, 255, 35, 0, 147, 1, 144, 41, 70, 40, 70, ++ 19, 70, 39, 240, 119, 255, 32, 106, 212, 248, 56, 19, 101, 48, 77, 49, ++ 16, 34, 241, 247, 179, 250, 48, 70, 7, 176, 240, 189, 248, 181, 3, 104, ++ 6, 70, 147, 248, 69, 48, 12, 70, 21, 70, 26, 79, 59, 177, 11, 104, 208, ++ 248, 100, 1, 249, 92, 58, 240, 83, 221, 0, 40, 40, 209, 43, 105, 33, ++ 104, 211, 248, 68, 35, 121, 92, 146, 248, 41, 0, 8, 65, 16, 240, 1, ++ 0, 30, 208, 33, 104, 137, 185, 50, 104, 219, 104, 210, 248, 136, 32, ++ 79, 240, 255, 48, 17, 106, 1, 49, 17, 98, 26, 106, 1, 50, 26, 98, 213, ++ 248, 92, 49, 1, 51, 197, 248, 92, 49, 248, 189, 1, 57, 33, 96, 146, ++ 248, 41, 0, 121, 92, 8, 65, 16, 240, 1, 0, 226, 209, 248, 189, 0, 32, ++ 248, 189, 84, 194, 135, 0, 45, 233, 240, 79, 153, 70, 153, 176, 0, 35, ++ 20, 146, 22, 147, 66, 104, 3, 104, 13, 104, 14, 146, 26, 126, 4, 70, ++ 138, 70, 213, 248, 40, 128, 50, 185, 211, 248, 136, 48, 12, 146, 89, ++ 106, 1, 49, 89, 98, 97, 227, 144, 248, 116, 34, 0, 42, 64, 240, 126, ++ 131, 216, 248, 16, 112, 174, 105, 58, 124, 122, 177, 152, 248, 20, 16, ++ 200, 7, 11, 212, 152, 248, 36, 16, 17, 240, 2, 1, 6, 209, 211, 248, ++ 136, 48, 12, 145, 90, 106, 1, 50, 90, 98, 71, 227, 33, 106, 216, 248, ++ 48, 0, 73, 104, 136, 66, 7, 208, 211, 248, 136, 48, 90, 106, 1, 50, ++ 90, 98, 0, 35, 12, 147, 57, 227, 216, 248, 4, 48, 143, 73, 25, 64, 17, ++ 177, 233, 137, 1, 240, 7, 1, 12, 145, 185, 121, 1, 185, 210, 185, 152, ++ 248, 20, 32, 209, 7, 22, 213, 215, 248, 204, 32, 82, 5, 18, 212, 215, ++ 248, 244, 32, 82, 142, 2, 244, 64, 66, 162, 245, 64, 76, 220, 241, 0, ++ 2, 66, 235, 12, 2, 14, 50, 7, 235, 130, 2, 82, 104, 18, 177, 146, 248, ++ 231, 32, 178, 185, 88, 6, 23, 213, 24, 171, 0, 34, 67, 248, 4, 45, 0, ++ 147, 32, 70, 12, 155, 65, 70, 42, 70, 31, 240, 32, 221, 23, 155, 131, ++ 70, 0, 43, 64, 240, 1, 131, 235, 137, 3, 240, 7, 3, 12, 147, 4, 224, ++ 79, 240, 4, 11, 1, 224, 79, 240, 1, 11, 157, 248, 136, 32, 201, 248, ++ 0, 176, 35, 104, 18, 177, 179, 248, 98, 48, 1, 224, 179, 248, 96, 48, ++ 187, 241, 3, 15, 7, 216, 226, 105, 2, 235, 75, 2, 178, 249, 28, 32, ++ 154, 66, 128, 242, 190, 128, 14, 152, 41, 70, 248, 247, 103, 249, 21, ++ 40, 129, 70, 18, 216, 35, 104, 211, 248, 136, 48, 154, 106, 1, 50, 154, ++ 98, 216, 248, 16, 48, 27, 177, 219, 104, 90, 106, 1, 50, 90, 98, 216, ++ 248, 92, 49, 1, 51, 200, 248, 92, 49, 198, 226, 170, 104, 187, 121, ++ 18, 146, 91, 177, 19, 120, 217, 7, 8, 213, 212, 248, 8, 5, 57, 70, 75, ++ 70, 41, 240, 50, 216, 0, 40, 64, 240, 183, 130, 6, 240, 16, 3, 219, ++ 178, 17, 147, 151, 248, 89, 48, 91, 177, 152, 248, 20, 48, 218, 7, 7, ++ 212, 152, 248, 36, 48, 219, 6, 3, 212, 17, 155, 0, 43, 0, 240, 164, ++ 130, 212, 248, 156, 33, 6, 240, 0, 67, 186, 92, 82, 177, 152, 248, 20, ++ 32, 208, 7, 6, 212, 152, 248, 36, 32, 209, 6, 2, 212, 0, 43, 0, 240, ++ 147, 130, 58, 109, 64, 242, 55, 22, 22, 64, 254, 177, 151, 248, 37, ++ 35, 202, 185, 17, 154, 82, 177, 184, 248, 68, 96, 190, 177, 216, 248, ++ 12, 96, 166, 177, 51, 105, 0, 43, 8, 191, 0, 38, 15, 224, 107, 185, ++ 216, 248, 12, 96, 94, 185, 187, 110, 90, 28, 0, 240, 118, 130, 7, 235, ++ 131, 3, 222, 110, 30, 185, 112, 226, 0, 38, 0, 224, 17, 158, 151, 248, ++ 80, 51, 155, 177, 17, 155, 139, 177, 151, 248, 37, 51, 115, 185, 32, ++ 70, 41, 70, 14, 34, 3, 35, 252, 247, 118, 251, 56, 177, 212, 248, 120, ++ 4, 35, 73, 183, 248, 26, 33, 43, 70, 82, 240, 131, 216, 62, 177, 51, ++ 122, 2, 43, 6, 209, 1, 34, 9, 241, 8, 9, 16, 146, 3, 224, 16, 150, 1, ++ 224, 0, 35, 16, 147, 171, 105, 19, 244, 136, 111, 14, 209, 151, 248, ++ 37, 51, 91, 185, 22, 171, 0, 147, 32, 70, 65, 70, 90, 70, 75, 70, 252, ++ 247, 227, 251, 1, 40, 13, 144, 9, 209, 2, 224, 169, 241, 14, 3, 22, ++ 147, 14, 152, 41, 70, 248, 247, 200, 248, 1, 34, 13, 146, 148, 248, ++ 74, 54, 3, 177, 64, 0, 227, 105, 3, 235, 139, 3, 91, 104, 27, 104, 131, ++ 66, 14, 216, 4, 235, 75, 3, 179, 248, 90, 34, 180, 248, 88, 50, 35, ++ 234, 2, 3, 164, 248, 88, 50, 56, 226, 64, 0, 1, 0, 125, 32, 1, 0, 13, ++ 154, 79, 240, 0, 12, 162, 241, 1, 14, 222, 241, 0, 3, 67, 235, 14, 3, ++ 14, 34, 205, 248, 84, 176, 19, 146, 195, 70, 205, 248, 60, 192, 184, ++ 70, 25, 70, 103, 70, 149, 225, 0, 46, 126, 208, 148, 248, 148, 50, 155, ++ 185, 216, 248, 80, 48, 24, 7, 15, 212, 51, 122, 11, 43, 6, 209, 35, ++ 104, 147, 248, 177, 48, 67, 177, 179, 121, 7, 43, 5, 216, 35, 104, 178, ++ 121, 211, 248, 188, 48, 154, 66, 7, 211, 150, 249, 14, 48, 150, 249, ++ 15, 0, 180, 51, 10, 147, 0, 33, 2, 224, 180, 35, 0, 32, 10, 147, 16, ++ 154, 0, 42, 94, 208, 15, 155, 144, 74, 2, 51, 156, 70, 13, 155, 210, ++ 248, 0, 224, 170, 138, 156, 69, 94, 248, 34, 32, 53, 211, 8, 48, 202, ++ 177, 178, 248, 20, 192, 94, 248, 44, 224, 190, 241, 0, 15, 43, 209, ++ 210, 248, 4, 192, 178, 248, 6, 224, 147, 104, 204, 243, 20, 12, 12, ++ 235, 94, 28, 79, 234, 83, 94, 79, 234, 78, 94, 12, 241, 1, 12, 244, ++ 68, 178, 248, 12, 224, 17, 224, 213, 248, 4, 192, 181, 248, 6, 224, ++ 171, 104, 204, 243, 20, 12, 12, 235, 94, 28, 79, 234, 83, 94, 79, 234, ++ 78, 94, 12, 241, 1, 12, 244, 68, 181, 248, 12, 224, 158, 68, 206, 235, ++ 12, 14, 134, 69, 56, 191, 0, 33, 0, 224, 0, 33, 181, 248, 14, 224, 30, ++ 240, 64, 15, 64, 240, 170, 128, 149, 248, 2, 224, 190, 241, 1, 15, 0, ++ 242, 164, 128, 122, 177, 178, 248, 14, 224, 30, 240, 64, 15, 64, 240, ++ 157, 128, 146, 120, 1, 42, 0, 242, 153, 128, 4, 224, 79, 240, 180, 12, ++ 48, 70, 205, 248, 40, 192, 0, 41, 0, 240, 144, 128, 152, 248, 37, 51, ++ 0, 43, 64, 240, 135, 128, 171, 105, 26, 4, 0, 241, 131, 128, 149, 249, ++ 30, 48, 0, 43, 126, 219, 212, 248, 160, 193, 156, 248, 0, 48, 0, 43, ++ 120, 208, 16, 154, 218, 177, 212, 248, 180, 49, 0, 43, 23, 218, 182, ++ 177, 51, 122, 2, 43, 19, 209, 148, 248, 148, 50, 131, 185, 216, 248, ++ 80, 48, 27, 7, 12, 212, 34, 104, 179, 121, 210, 248, 188, 32, 147, 66, ++ 6, 210, 3, 43, 4, 217, 11, 43, 2, 216, 169, 241, 8, 3, 0, 224, 75, 70, ++ 21, 154, 96, 70, 0, 146, 12, 154, 89, 70, 1, 146, 42, 70, 205, 248, ++ 44, 192, 100, 240, 52, 222, 221, 248, 44, 192, 0, 40, 64, 208, 71, 70, ++ 216, 70, 0, 46, 44, 208, 0, 35, 96, 70, 89, 70, 50, 70, 100, 240, 184, ++ 222, 51, 122, 2, 43, 35, 209, 212, 248, 180, 49, 0, 43, 15, 218, 148, ++ 248, 148, 50, 99, 185, 59, 109, 24, 7, 9, 212, 34, 104, 179, 121, 210, ++ 248, 188, 32, 147, 66, 3, 210, 3, 43, 1, 217, 11, 43, 15, 217, 14, 155, ++ 18, 154, 141, 232, 136, 1, 12, 155, 3, 146, 5, 147, 32, 104, 41, 70, ++ 0, 34, 1, 35, 4, 150, 205, 248, 24, 144, 90, 240, 221, 216, 42, 70, ++ 75, 70, 32, 70, 65, 70, 252, 247, 33, 255, 35, 104, 211, 248, 136, 48, ++ 218, 106, 1, 50, 218, 98, 20, 154, 1, 35, 19, 96, 222, 224, 171, 105, ++ 67, 244, 0, 67, 171, 97, 35, 104, 211, 248, 136, 48, 26, 107, 1, 50, ++ 26, 99, 202, 248, 0, 80, 1, 33, 117, 224, 22, 154, 1, 144, 0, 146, 14, ++ 152, 41, 70, 19, 154, 10, 155, 11, 240, 162, 219, 74, 248, 7, 0, 48, ++ 187, 216, 70, 86, 70, 7, 70, 6, 224, 14, 152, 86, 248, 4, 27, 1, 34, ++ 249, 247, 153, 255, 1, 55, 221, 248, 60, 192, 103, 69, 244, 209, 202, ++ 248, 0, 80, 35, 104, 211, 248, 136, 48, 26, 106, 1, 50, 26, 98, 216, ++ 248, 16, 48, 27, 177, 219, 104, 26, 106, 1, 50, 26, 98, 216, 248, 92, ++ 49, 1, 51, 200, 248, 92, 49, 215, 224, 0, 191, 32, 7, 0, 0, 190, 177, ++ 51, 122, 11, 43, 20, 209, 148, 248, 148, 50, 115, 185, 216, 248, 80, ++ 48, 25, 7, 10, 212, 34, 104, 146, 248, 177, 48, 51, 177, 179, 121, 7, ++ 43, 3, 216, 210, 248, 188, 32, 147, 66, 2, 211, 131, 137, 16, 51, 131, ++ 129, 131, 104, 18, 153, 14, 59, 131, 96, 90, 248, 7, 48, 154, 137, 152, ++ 104, 14, 50, 154, 129, 14, 34, 240, 247, 134, 255, 13, 154, 221, 248, ++ 60, 192, 83, 30, 156, 69, 5, 209, 32, 104, 41, 70, 90, 248, 7, 32, 252, ++ 247, 118, 254, 90, 248, 7, 48, 233, 137, 218, 137, 1, 240, 7, 1, 34, ++ 240, 7, 2, 10, 67, 221, 248, 76, 192, 218, 129, 22, 155, 0, 33, 156, ++ 68, 205, 248, 76, 192, 221, 248, 60, 192, 4, 55, 12, 241, 1, 12, 205, ++ 248, 60, 192, 221, 248, 60, 192, 13, 154, 148, 69, 127, 244, 100, 174, ++ 216, 70, 67, 70, 79, 240, 0, 12, 205, 248, 60, 144, 176, 70, 169, 70, ++ 221, 248, 84, 176, 87, 70, 101, 70, 30, 70, 42, 224, 157, 66, 17, 210, ++ 16, 154, 74, 177, 22, 155, 32, 104, 14, 51, 0, 147, 14, 153, 151, 232, ++ 12, 0, 91, 240, 5, 218, 3, 224, 14, 152, 121, 104, 247, 247, 206, 254, ++ 14, 56, 0, 224, 0, 32, 17, 155, 57, 104, 12, 154, 2, 147, 22, 155, 141, ++ 232, 65, 0, 5, 146, 6, 147, 42, 70, 13, 155, 32, 70, 205, 248, 12, 176, ++ 205, 248, 16, 128, 254, 247, 113, 251, 87, 248, 4, 59, 1, 53, 158, 98, ++ 13, 155, 157, 66, 3, 241, 255, 51, 207, 209, 90, 248, 35, 48, 77, 70, ++ 171, 66, 221, 248, 60, 144, 176, 70, 4, 208, 14, 152, 41, 70, 1, 34, ++ 249, 247, 225, 254, 13, 154, 20, 155, 26, 96, 216, 248, 88, 49, 65, ++ 70, 1, 51, 200, 248, 88, 49, 241, 233, 96, 35, 18, 235, 9, 2, 67, 241, ++ 0, 3, 193, 233, 0, 35, 32, 70, 65, 70, 74, 70, 12, 155, 252, 247, 78, ++ 248, 0, 32, 34, 224, 20, 154, 0, 35, 19, 96, 41, 70, 14, 152, 247, 247, ++ 131, 254, 12, 154, 1, 70, 32, 70, 252, 247, 118, 248, 35, 104, 147, ++ 248, 66, 32, 66, 177, 147, 248, 67, 48, 43, 177, 212, 248, 52, 1, 65, ++ 70, 42, 70, 12, 240, 127, 254, 14, 152, 41, 70, 1, 34, 249, 247, 170, ++ 254, 79, 240, 255, 48, 1, 224, 111, 240, 15, 0, 25, 176, 189, 232, 240, ++ 143, 112, 181, 4, 70, 64, 33, 32, 70, 27, 240, 202, 219, 22, 34, 20, ++ 33, 5, 70, 32, 105, 51, 240, 252, 220, 79, 244, 209, 113, 6, 70, 32, ++ 70, 27, 240, 190, 219, 79, 244, 210, 113, 32, 70, 27, 240, 185, 219, ++ 64, 33, 32, 70, 27, 240, 181, 219, 133, 66, 228, 209, 7, 45, 226, 208, ++ 212, 248, 64, 55, 79, 244, 122, 114, 246, 26, 182, 251, 242, 246, 2, ++ 251, 6, 51, 212, 248, 56, 7, 64, 246, 184, 49, 48, 24, 196, 248, 56, ++ 7, 164, 248, 60, 23, 196, 248, 64, 55, 112, 189, 45, 233, 240, 65, 197, ++ 104, 12, 70, 213, 248, 84, 49, 134, 176, 75, 96, 213, 248, 88, 49, 6, ++ 70, 11, 96, 181, 248, 144, 52, 0, 105, 139, 129, 181, 248, 216, 52, ++ 79, 240, 0, 8, 203, 129, 184, 33, 52, 240, 174, 218, 64, 33, 164, 248, ++ 186, 0, 48, 105, 52, 240, 168, 218, 213, 248, 32, 17, 164, 248, 188, ++ 0, 161, 96, 181, 248, 144, 38, 167, 137, 146, 178, 0, 151, 3, 146, 231, ++ 137, 162, 131, 180, 248, 186, 32, 51, 104, 1, 151, 4, 146, 5, 144, 2, ++ 145, 217, 104, 98, 104, 35, 104, 99, 72, 242, 243, 12, 242, 181, 248, ++ 192, 23, 137, 178, 33, 130, 181, 248, 208, 39, 146, 178, 98, 130, 181, ++ 248, 210, 55, 155, 178, 163, 130, 181, 248, 72, 4, 164, 248, 210, 0, ++ 181, 248, 74, 4, 164, 248, 212, 0, 181, 248, 76, 4, 164, 248, 214, 0, ++ 86, 72, 242, 243, 241, 241, 181, 248, 0, 53, 48, 70, 227, 131, 181, ++ 248, 14, 53, 35, 131, 181, 248, 238, 51, 99, 131, 181, 248, 26, 52, ++ 164, 248, 172, 48, 181, 248, 28, 52, 181, 248, 2, 116, 164, 248, 174, ++ 48, 191, 178, 121, 0, 27, 240, 49, 219, 121, 28, 164, 248, 166, 0, 73, ++ 0, 48, 70, 27, 240, 42, 219, 249, 28, 164, 248, 168, 0, 73, 0, 48, 70, ++ 27, 240, 35, 219, 0, 33, 164, 248, 170, 0, 128, 34, 4, 241, 34, 0, 242, ++ 243, 157, 241, 8, 235, 71, 1, 48, 70, 27, 240, 22, 219, 4, 235, 8, 3, ++ 8, 241, 2, 8, 184, 241, 128, 15, 88, 132, 242, 209, 56, 72, 242, 243, ++ 179, 241, 160, 70, 34, 70, 0, 35, 67, 244, 0, 49, 197, 248, 96, 17, ++ 213, 248, 96, 17, 213, 248, 100, 17, 1, 51, 81, 132, 2, 50, 64, 43, ++ 242, 209, 48, 72, 242, 243, 160, 241, 0, 39, 57, 70, 48, 70, 54, 240, ++ 179, 222, 1, 55, 64, 47, 168, 248, 34, 0, 8, 241, 2, 8, 244, 209, 41, ++ 72, 242, 243, 145, 241, 35, 104, 83, 177, 40, 72, 242, 243, 140, 241, ++ 0, 35, 226, 24, 213, 248, 88, 17, 2, 51, 128, 43, 81, 132, 248, 209, ++ 35, 72, 242, 243, 129, 241, 0, 35, 226, 24, 213, 248, 84, 17, 2, 51, ++ 128, 43, 81, 132, 248, 209, 181, 248, 152, 54, 164, 248, 190, 48, 243, ++ 104, 211, 248, 40, 33, 196, 248, 192, 32, 211, 248, 44, 33, 211, 248, ++ 80, 49, 196, 248, 196, 32, 196, 248, 200, 48, 51, 105, 211, 248, 240, ++ 48, 196, 248, 204, 48, 79, 244, 248, 115, 165, 248, 252, 51, 181, 248, ++ 254, 51, 164, 248, 208, 48, 181, 248, 70, 54, 164, 248, 216, 48, 181, ++ 248, 72, 54, 164, 248, 218, 48, 181, 248, 102, 54, 164, 248, 220, 48, ++ 181, 248, 112, 54, 164, 248, 222, 48, 6, 176, 189, 232, 240, 129, 87, ++ 68, 136, 0, 235, 68, 136, 0, 134, 69, 136, 0, 147, 69, 136, 0, 158, ++ 69, 136, 0, 176, 69, 136, 0, 186, 69, 136, 0, 127, 181, 5, 70, 228, ++ 32, 14, 70, 246, 243, 26, 247, 4, 70, 32, 177, 40, 70, 33, 70, 255, ++ 247, 234, 254, 2, 224, 11, 72, 242, 243, 42, 241, 0, 34, 228, 35, 3, ++ 147, 40, 70, 41, 33, 19, 70, 0, 150, 1, 146, 2, 148, 25, 240, 133, 220, ++ 44, 177, 32, 70, 4, 176, 189, 232, 112, 64, 249, 247, 15, 189, 4, 176, ++ 112, 189, 9, 70, 136, 0, 112, 181, 13, 70, 0, 33, 4, 70, 27, 240, 102, ++ 218, 2, 33, 6, 70, 32, 70, 27, 240, 97, 218, 49, 70, 2, 70, 25, 72, ++ 242, 243, 4, 241, 34, 104, 212, 248, 36, 24, 147, 106, 89, 26, 3, 41, ++ 20, 216, 209, 104, 20, 72, 42, 70, 242, 243, 248, 240, 2, 45, 20, 191, ++ 41, 70, 3, 33, 32, 70, 255, 247, 183, 255, 16, 72, 242, 243, 238, 240, ++ 35, 104, 147, 248, 156, 48, 1, 43, 15, 209, 10, 224, 210, 248, 136, ++ 48, 209, 104, 211, 248, 20, 50, 42, 70, 1, 51, 9, 72, 242, 243, 222, ++ 240, 3, 224, 32, 70, 0, 33, 11, 240, 31, 253, 35, 104, 155, 106, 196, ++ 248, 36, 56, 112, 189, 190, 69, 136, 0, 60, 51, 4, 0, 39, 70, 136, 0, ++ 117, 51, 4, 0, 45, 233, 240, 67, 3, 106, 143, 176, 27, 104, 4, 70, 1, ++ 43, 20, 191, 79, 240, 10, 9, 79, 240, 16, 9, 136, 70, 14, 240, 77, 219, ++ 2, 169, 39, 240, 49, 249, 212, 248, 116, 52, 2, 168, 153, 120, 39, 240, ++ 43, 248, 212, 248, 108, 18, 32, 70, 24, 240, 7, 220, 255, 35, 1, 144, ++ 0, 34, 2, 168, 0, 147, 1, 70, 19, 70, 39, 240, 188, 249, 0, 37, 58, ++ 224, 14, 170, 83, 25, 19, 248, 44, 124, 32, 70, 7, 240, 127, 7, 57, ++ 70, 27, 240, 210, 216, 12, 171, 6, 70, 57, 70, 0, 147, 32, 70, 66, 70, ++ 79, 244, 0, 115, 19, 240, 10, 222, 57, 70, 0, 34, 67, 70, 32, 70, 19, ++ 240, 190, 219, 157, 248, 49, 32, 157, 248, 48, 48, 18, 2, 210, 24, 72, ++ 68, 135, 178, 6, 241, 10, 1, 32, 70, 146, 178, 31, 240, 94, 216, 157, ++ 248, 51, 32, 157, 248, 50, 48, 18, 2, 210, 24, 32, 70, 6, 241, 12, 1, ++ 146, 178, 31, 240, 82, 216, 32, 70, 6, 241, 16, 1, 58, 70, 31, 240, ++ 76, 216, 1, 53, 2, 155, 157, 66, 193, 211, 15, 176, 189, 232, 240, 131, ++ 240, 181, 141, 176, 4, 70, 14, 240, 238, 218, 2, 169, 39, 240, 210, ++ 248, 212, 248, 116, 52, 2, 168, 153, 120, 38, 240, 204, 255, 212, 248, ++ 108, 18, 32, 70, 24, 240, 168, 219, 255, 35, 1, 144, 0, 34, 2, 168, ++ 0, 147, 1, 70, 19, 70, 39, 240, 93, 249, 0, 37, 22, 224, 12, 170, 83, ++ 25, 19, 248, 36, 108, 39, 106, 6, 240, 127, 6, 48, 70, 38, 240, 169, ++ 255, 56, 24, 144, 248, 120, 32, 26, 185, 157, 248, 12, 32, 2, 240, 127, ++ 2, 32, 70, 49, 70, 18, 240, 41, 216, 1, 53, 2, 155, 157, 66, 229, 211, ++ 13, 176, 240, 189, 144, 248, 45, 50, 1, 43, 2, 209, 182, 33, 0, 34, ++ 4, 224, 144, 248, 44, 34, 182, 33, 66, 234, 3, 34, 30, 240, 253, 159, ++ 16, 181, 131, 121, 4, 104, 91, 177, 251, 247, 123, 252, 227, 104, 2, ++ 70, 163, 248, 18, 6, 150, 33, 32, 70, 189, 232, 16, 64, 30, 240, 237, ++ 159, 16, 189, 112, 181, 4, 70, 14, 70, 30, 240, 123, 216, 79, 240, 128, ++ 97, 5, 70, 0, 40, 20, 191, 79, 240, 128, 98, 0, 34, 32, 70, 25, 240, ++ 74, 220, 53, 177, 114, 1, 4, 212, 32, 105, 189, 232, 112, 64, 19, 240, ++ 130, 187, 112, 189, 112, 181, 4, 104, 6, 70, 99, 126, 0, 43, 51, 208, ++ 26, 240, 241, 221, 212, 248, 108, 50, 2, 70, 158, 66, 34, 209, 51, 124, ++ 3, 179, 212, 248, 28, 55, 0, 40, 20, 191, 79, 240, 0, 117, 0, 37, 26, ++ 104, 130, 177, 219, 104, 115, 177, 246, 243, 183, 241, 212, 248, 28, ++ 55, 218, 104, 130, 26, 178, 245, 122, 127, 1, 217, 1, 34, 26, 114, 212, ++ 248, 28, 55, 0, 34, 218, 96, 32, 70, 79, 240, 0, 113, 42, 70, 25, 240, ++ 18, 220, 4, 224, 212, 248, 72, 1, 49, 70, 75, 240, 26, 220, 32, 70, ++ 189, 232, 112, 64, 10, 240, 7, 156, 112, 189, 208, 248, 4, 49, 16, 181, ++ 25, 114, 3, 104, 4, 70, 27, 106, 24, 105, 28, 240, 32, 254, 32, 70, ++ 189, 232, 16, 64, 255, 247, 182, 191, 16, 181, 144, 248, 114, 50, 4, ++ 70, 59, 177, 3, 104, 147, 248, 79, 48, 155, 7, 7, 209, 3, 106, 91, 125, ++ 35, 185, 212, 248, 12, 34, 50, 240, 127, 66, 4, 208, 79, 244, 128, 17, ++ 32, 70, 10, 70, 2, 224, 32, 70, 79, 244, 128, 17, 25, 240, 219, 219, ++ 32, 70, 90, 33, 63, 34, 189, 232, 16, 64, 30, 240, 102, 159, 45, 233, ++ 240, 67, 133, 176, 15, 70, 12, 153, 4, 70, 22, 70, 152, 70, 20, 240, ++ 66, 253, 57, 70, 5, 70, 50, 70, 32, 70, 67, 70, 251, 247, 27, 252, 176, ++ 241, 0, 9, 192, 242, 218, 129, 35, 104, 91, 126, 59, 185, 32, 105, 66, ++ 240, 237, 217, 24, 177, 160, 104, 251, 247, 178, 248, 192, 225, 70, ++ 177, 184, 241, 3, 15, 5, 217, 2, 168, 49, 70, 4, 34, 240, 247, 181, ++ 251, 1, 224, 0, 35, 2, 147, 163, 47, 226, 104, 33, 208, 9, 220, 28, ++ 47, 5, 220, 27, 47, 28, 218, 187, 30, 1, 43, 18, 216, 24, 224, 52, 47, ++ 14, 224, 64, 242, 11, 19, 159, 66, 18, 208, 3, 220, 214, 47, 15, 208, ++ 251, 47, 5, 224, 183, 245, 139, 127, 10, 208, 64, 242, 27, 19, 159, ++ 66, 6, 208, 0, 46, 0, 240, 154, 129, 184, 241, 0, 15, 64, 243, 150, ++ 129, 63, 47, 0, 240, 178, 128, 14, 220, 22, 47, 69, 208, 5, 220, 20, ++ 47, 34, 208, 21, 47, 64, 240, 141, 129, 48, 224, 61, 47, 97, 208, 62, ++ 47, 64, 240, 135, 129, 104, 224, 127, 47, 0, 240, 1, 129, 6, 220, 64, ++ 47, 0, 240, 184, 128, 113, 47, 64, 240, 124, 129, 219, 224, 64, 242, ++ 29, 19, 159, 66, 0, 240, 88, 129, 183, 245, 162, 127, 0, 240, 32, 129, ++ 183, 245, 134, 127, 64, 240, 110, 129, 43, 225, 171, 121, 2, 154, 19, ++ 177, 0, 42, 0, 240, 83, 129, 0, 50, 212, 248, 56, 51, 24, 191, 1, 34, ++ 131, 248, 52, 32, 32, 70, 41, 70, 20, 240, 136, 252, 21, 224, 181, 249, ++ 84, 48, 3, 43, 0, 240, 210, 128, 181, 249, 86, 32, 26, 185, 0, 51, 24, ++ 191, 1, 35, 202, 224, 2, 35, 200, 224, 2, 155, 1, 43, 7, 216, 165, 248, ++ 84, 48, 0, 35, 165, 248, 86, 48, 79, 240, 0, 9, 70, 225, 34, 104, 146, ++ 248, 102, 113, 127, 177, 3, 43, 246, 209, 165, 248, 84, 48, 181, 248, ++ 90, 48, 212, 248, 80, 8, 67, 240, 32, 3, 165, 248, 90, 48, 41, 70, 42, ++ 240, 151, 249, 232, 231, 1, 35, 165, 248, 84, 112, 165, 248, 86, 48, ++ 204, 224, 212, 248, 116, 52, 147, 248, 28, 81, 21, 177, 147, 248, 69, ++ 49, 155, 224, 147, 249, 8, 48, 78, 224, 35, 104, 29, 126, 0, 45, 0, ++ 240, 7, 129, 212, 248, 116, 36, 2, 153, 146, 248, 28, 49, 147, 177, ++ 203, 178, 130, 248, 70, 49, 212, 248, 116, 36, 0, 37, 17, 114, 212, ++ 248, 116, 36, 146, 248, 172, 16, 1, 34, 141, 232, 36, 0, 42, 70, 32, ++ 105, 19, 240, 109, 250, 237, 224, 32, 70, 73, 178, 45, 240, 157, 252, ++ 176, 241, 0, 9, 192, 242, 252, 128, 212, 248, 116, 52, 2, 154, 32, 70, ++ 26, 114, 29, 240, 158, 223, 32, 70, 45, 240, 160, 252, 32, 70, 212, ++ 248, 160, 20, 18, 240, 2, 222, 32, 70, 23, 240, 73, 223, 232, 224, 212, ++ 248, 116, 52, 147, 248, 28, 81, 21, 177, 147, 248, 172, 48, 87, 224, ++ 34, 104, 23, 126, 15, 185, 219, 121, 122, 224, 35, 106, 13, 241, 15, ++ 1, 24, 105, 28, 240, 221, 251, 24, 177, 157, 248, 15, 48, 51, 96, 186, ++ 224, 212, 248, 116, 52, 219, 121, 51, 96, 166, 224, 2, 155, 90, 28, ++ 4, 42, 0, 242, 179, 128, 1, 51, 1, 209, 3, 35, 2, 147, 212, 248, 116, ++ 52, 2, 153, 147, 248, 28, 33, 114, 177, 201, 178, 131, 248, 173, 16, ++ 212, 248, 116, 52, 0, 34, 147, 248, 69, 49, 0, 146, 1, 146, 32, 105, ++ 1, 34, 19, 240, 23, 250, 4, 224, 35, 106, 201, 178, 24, 105, 28, 240, ++ 182, 251, 212, 248, 116, 52, 2, 154, 218, 113, 89, 231, 35, 104, 27, ++ 126, 0, 43, 0, 240, 142, 128, 212, 248, 116, 52, 147, 248, 28, 17, 17, ++ 177, 147, 248, 175, 48, 13, 224, 178, 248, 232, 51, 77, 246, 173, 98, ++ 155, 178, 147, 66, 0, 240, 129, 128, 79, 246, 255, 114, 147, 66, 124, ++ 208, 195, 243, 64, 19, 51, 96, 60, 231, 184, 241, 12, 15, 37, 209, 55, ++ 121, 23, 240, 1, 7, 119, 209, 32, 70, 41, 70, 50, 29, 43, 240, 50, 250, ++ 4, 70, 136, 177, 3, 105, 155, 121, 67, 177, 1, 33, 58, 70, 88, 240, ++ 191, 221, 32, 70, 88, 240, 122, 221, 48, 96, 12, 224, 213, 248, 0, 33, ++ 153, 70, 18, 105, 50, 96, 102, 224, 175, 121, 0, 47, 88, 209, 213, 248, ++ 0, 49, 27, 105, 51, 96, 185, 70, 93, 224, 184, 241, 4, 15, 82, 209, ++ 175, 121, 0, 47, 79, 209, 242, 231, 171, 121, 0, 43, 78, 209, 212, 248, ++ 188, 6, 3, 104, 235, 88, 0, 43, 72, 208, 27, 121, 0, 43, 69, 208, 41, ++ 70, 50, 70, 46, 240, 156, 250, 32, 224, 5, 245, 104, 112, 6, 48, 49, ++ 70, 68, 34, 240, 247, 46, 250, 171, 121, 155, 185, 212, 248, 188, 6, ++ 3, 104, 234, 88, 43, 122, 50, 177, 18, 121, 34, 177, 41, 70, 50, 70, ++ 91, 240, 226, 223, 10, 224, 212, 248, 192, 6, 41, 70, 50, 70, 65, 240, ++ 65, 216, 3, 224, 104, 105, 49, 70, 49, 240, 126, 221, 129, 70, 34, 224, ++ 184, 245, 10, 127, 29, 211, 48, 70, 161, 106, 79, 244, 10, 114, 240, ++ 247, 9, 250, 206, 230, 111, 240, 6, 9, 21, 224, 169, 70, 19, 224, 111, ++ 240, 28, 9, 16, 224, 111, 240, 3, 9, 13, 224, 79, 240, 255, 57, 10, ++ 224, 111, 240, 29, 9, 7, 224, 111, 240, 1, 9, 4, 224, 111, 240, 22, ++ 9, 1, 224, 111, 240, 13, 9, 72, 70, 5, 176, 189, 232, 240, 131, 45, ++ 233, 243, 65, 8, 156, 7, 70, 14, 70, 21, 70, 152, 70, 0, 148, 255, 247, ++ 3, 254, 16, 241, 47, 15, 12, 208, 16, 241, 23, 15, 11, 209, 56, 70, ++ 49, 70, 42, 70, 67, 70, 8, 148, 2, 176, 189, 232, 240, 65, 13, 240, ++ 145, 153, 111, 240, 22, 0, 2, 176, 189, 232, 240, 129, 45, 233, 240, ++ 71, 12, 70, 136, 176, 145, 178, 129, 70, 20, 240, 214, 251, 7, 70, 0, ++ 40, 64, 208, 162, 7, 62, 213, 208, 248, 84, 67, 0, 44, 58, 208, 37, ++ 70, 0, 38, 0, 35, 4, 235, 6, 8, 7, 147, 152, 248, 2, 48, 19, 179, 164, ++ 33, 113, 67, 96, 24, 97, 24, 1, 241, 176, 10, 213, 248, 152, 16, 170, ++ 105, 107, 105, 213, 248, 136, 192, 213, 248, 132, 224, 28, 48, 17, 177, ++ 4, 235, 198, 1, 4, 49, 4, 145, 7, 169, 2, 144, 5, 145, 72, 70, 57, 70, ++ 141, 232, 0, 80, 205, 248, 12, 160, 24, 240, 155, 253, 136, 185, 136, ++ 248, 2, 0, 32, 112, 1, 54, 164, 53, 2, 46, 209, 209, 251, 104, 72, 70, ++ 0, 147, 121, 33, 6, 35, 7, 241, 188, 2, 255, 247, 151, 255, 1, 35, 99, ++ 112, 8, 176, 189, 232, 240, 135, 19, 181, 208, 248, 44, 70, 10, 64, ++ 36, 234, 1, 1, 17, 67, 3, 104, 192, 248, 44, 22, 27, 126, 107, 177, ++ 3, 35, 0, 147, 33, 177, 4, 33, 79, 244, 0, 66, 0, 35, 3, 224, 79, 244, ++ 0, 66, 4, 33, 19, 70, 25, 240, 109, 217, 28, 189, 19, 181, 4, 70, 255, ++ 247, 161, 252, 32, 70, 16, 240, 181, 223, 212, 248, 116, 52, 0, 32, ++ 147, 248, 173, 16, 1, 34, 147, 248, 70, 49, 1, 144, 32, 105, 0, 146, ++ 19, 240, 199, 248, 32, 105, 2, 176, 189, 232, 16, 64, 65, 240, 132, ++ 159, 195, 105, 115, 181, 1, 241, 12, 5, 3, 235, 69, 5, 174, 136, 0, ++ 235, 65, 1, 178, 26, 170, 128, 177, 248, 90, 18, 176, 248, 88, 34, 4, ++ 70, 10, 67, 160, 248, 88, 34, 179, 249, 28, 16, 179, 249, 30, 32, 138, ++ 24, 179, 249, 32, 16, 179, 249, 34, 48, 82, 24, 218, 66, 43, 209, 144, ++ 248, 116, 50, 219, 6, 1, 213, 53, 240, 127, 222, 148, 248, 116, 50, ++ 25, 7, 2, 213, 32, 70, 14, 240, 236, 253, 148, 248, 116, 50, 154, 6, ++ 13, 213, 212, 248, 116, 52, 147, 248, 80, 48, 67, 177, 32, 70, 44, 240, ++ 66, 253, 148, 248, 116, 50, 35, 240, 32, 3, 132, 248, 116, 50, 148, ++ 248, 116, 50, 91, 6, 8, 213, 32, 70, 45, 240, 67, 250, 148, 248, 116, ++ 50, 35, 240, 64, 3, 132, 248, 116, 50, 35, 104, 147, 248, 47, 48, 115, ++ 177, 148, 248, 117, 50, 91, 177, 227, 105, 179, 249, 36, 48, 59, 185, ++ 132, 248, 117, 50, 32, 70, 1, 33, 64, 34, 0, 147, 25, 240, 244, 216, ++ 212, 248, 168, 4, 8, 179, 208, 248, 248, 48, 155, 104, 6, 43, 28, 209, ++ 195, 104, 219, 104, 91, 137, 195, 185, 227, 105, 179, 249, 28, 16, 179, ++ 249, 30, 32, 138, 24, 179, 249, 32, 16, 179, 249, 34, 48, 82, 24, 218, ++ 66, 11, 209, 212, 248, 208, 36, 212, 248, 204, 52, 2, 50, 83, 248, 34, ++ 16, 2, 176, 189, 232, 112, 64, 15, 240, 47, 189, 2, 176, 112, 189, 45, ++ 233, 240, 65, 6, 104, 4, 70, 138, 176, 33, 70, 214, 248, 72, 1, 74, ++ 240, 65, 223, 2, 173, 7, 70, 0, 33, 32, 34, 40, 70, 241, 243, 50, 244, ++ 48, 70, 2, 33, 28, 34, 79, 244, 128, 115, 4, 241, 188, 8, 0, 149, 19, ++ 240, 200, 217, 72, 35, 173, 248, 14, 48, 65, 70, 0, 35, 6, 34, 13, 241, ++ 18, 0, 173, 248, 16, 48, 240, 247, 156, 248, 4, 241, 194, 1, 6, 34, ++ 6, 168, 240, 247, 150, 248, 65, 70, 6, 34, 13, 241, 30, 0, 240, 247, ++ 144, 248, 7, 241, 52, 1, 48, 70, 73, 1, 32, 34, 43, 70, 30, 240, 20, ++ 220, 10, 176, 189, 232, 240, 129, 0, 105, 18, 240, 194, 190, 45, 233, ++ 240, 65, 134, 176, 0, 147, 11, 124, 0, 39, 4, 70, 1, 146, 12, 158, 221, ++ 248, 52, 128, 2, 151, 3, 151, 197, 104, 43, 185, 209, 248, 244, 48, ++ 31, 142, 0, 55, 24, 191, 1, 39, 212, 248, 72, 1, 75, 240, 243, 216, ++ 157, 248, 64, 48, 163, 177, 32, 70, 5, 169, 4, 170, 255, 247, 220, 255, ++ 4, 155, 2, 168, 2, 147, 5, 155, 3, 169, 3, 147, 50, 70, 67, 70, 99, ++ 240, 189, 223, 1, 168, 105, 70, 2, 154, 3, 155, 99, 240, 159, 223, 79, ++ 240, 128, 81, 32, 70, 10, 70, 25, 240, 65, 216, 15, 153, 0, 155, 1, ++ 154, 71, 234, 129, 23, 14, 153, 197, 248, 128, 49, 5, 168, 197, 248, ++ 132, 33, 197, 248, 136, 113, 197, 248, 140, 17, 5, 146, 4, 147, 4, 169, ++ 2, 154, 3, 155, 99, 240, 155, 223, 67, 70, 5, 168, 4, 169, 50, 70, 99, ++ 240, 149, 223, 5, 153, 4, 154, 212, 248, 72, 1, 2, 145, 3, 146, 75, ++ 240, 35, 218, 32, 70, 79, 240, 128, 81, 0, 34, 25, 240, 23, 216, 212, ++ 248, 72, 1, 75, 240, 151, 216, 6, 176, 189, 232, 240, 129, 208, 248, ++ 96, 1, 1, 240, 1, 1, 43, 240, 74, 185, 16, 181, 4, 70, 245, 243, 152, ++ 245, 212, 248, 40, 53, 196, 248, 44, 5, 1, 51, 196, 248, 40, 53, 16, ++ 189, 16, 181, 4, 70, 245, 243, 140, 245, 212, 248, 44, 53, 66, 242, ++ 16, 114, 195, 26, 147, 66, 4, 217, 0, 35, 196, 248, 40, 53, 196, 248, ++ 44, 53, 16, 189, 0, 35, 55, 181, 4, 70, 29, 70, 226, 24, 210, 248, 152, ++ 34, 4, 51, 0, 42, 24, 191, 1, 37, 16, 43, 246, 209, 212, 248, 16, 53, ++ 3, 185, 69, 177, 0, 35, 0, 41, 164, 248, 36, 53, 12, 191, 13, 70, 111, ++ 240, 25, 5, 1, 224, 164, 248, 36, 21, 35, 104, 27, 126, 187, 177, 32, ++ 70, 29, 240, 143, 220, 32, 70, 124, 33, 180, 248, 36, 37, 30, 240, 87, ++ 219, 180, 248, 36, 53, 32, 34, 3, 33, 32, 70, 0, 43, 20, 191, 19, 70, ++ 0, 35, 0, 145, 24, 240, 205, 223, 32, 70, 23, 240, 48, 220, 40, 70, ++ 62, 189, 55, 181, 3, 104, 4, 70, 91, 126, 0, 43, 64, 240, 33, 129, 0, ++ 105, 65, 240, 222, 221, 0, 40, 64, 240, 27, 129, 35, 104, 147, 248, ++ 32, 48, 51, 185, 32, 105, 18, 240, 178, 254, 35, 104, 1, 34, 131, 248, ++ 32, 32, 32, 105, 18, 240, 109, 253, 32, 70, 54, 240, 50, 216, 212, 248, ++ 116, 52, 3, 34, 147, 248, 81, 48, 0, 146, 128, 34, 0, 43, 20, 191, 19, ++ 70, 0, 35, 32, 70, 4, 33, 24, 240, 155, 223, 35, 104, 219, 110, 227, ++ 185, 32, 105, 51, 240, 229, 223, 9, 48, 23, 209, 34, 104, 211, 110, ++ 19, 240, 2, 5, 18, 209, 67, 240, 2, 3, 211, 102, 212, 248, 104, 50, ++ 89, 89, 65, 177, 139, 121, 51, 185, 75, 121, 35, 177, 11, 124, 19, 177, ++ 32, 70, 53, 240, 98, 217, 4, 53, 32, 45, 239, 209, 35, 104, 219, 110, ++ 27, 177, 32, 70, 13, 240, 213, 220, 209, 224, 32, 105, 51, 240, 97, ++ 221, 32, 105, 144, 249, 52, 17, 77, 28, 3, 209, 1, 33, 51, 240, 87, ++ 221, 1, 224, 51, 240, 172, 220, 1, 35, 99, 118, 32, 70, 26, 240, 77, ++ 218, 35, 104, 32, 70, 89, 107, 3, 35, 0, 147, 33, 177, 79, 244, 128, ++ 114, 0, 33, 19, 70, 2, 224, 79, 244, 128, 114, 11, 70, 24, 240, 81, ++ 223, 160, 104, 6, 240, 172, 223, 35, 104, 1, 34, 26, 118, 148, 248, ++ 211, 49, 115, 177, 32, 70, 29, 240, 245, 219, 212, 248, 56, 51, 32, ++ 70, 89, 142, 28, 240, 193, 216, 0, 35, 132, 248, 211, 49, 32, 70, 23, ++ 240, 159, 219, 212, 248, 44, 38, 3, 33, 32, 70, 255, 247, 172, 253, ++ 32, 70, 10, 240, 40, 223, 180, 248, 36, 21, 32, 70, 255, 247, 42, 255, ++ 32, 105, 51, 240, 100, 223, 3, 35, 32, 34, 0, 147, 32, 70, 19, 70, 1, ++ 33, 24, 240, 32, 223, 35, 104, 147, 248, 47, 48, 27, 177, 212, 248, ++ 8, 5, 39, 240, 78, 221, 35, 104, 147, 248, 49, 48, 147, 177, 0, 37, ++ 212, 248, 104, 50, 89, 89, 81, 177, 139, 121, 67, 185, 75, 121, 51, ++ 177, 209, 248, 204, 48, 216, 7, 2, 213, 32, 70, 47, 240, 86, 216, 4, ++ 53, 32, 45, 237, 209, 32, 70, 17, 240, 192, 217, 32, 70, 88, 240, 219, ++ 222, 1, 37, 79, 244, 122, 114, 1, 35, 212, 248, 236, 17, 160, 104, 6, ++ 240, 166, 222, 212, 248, 160, 1, 132, 248, 46, 82, 46, 240, 168, 254, ++ 32, 70, 45, 240, 158, 248, 212, 248, 116, 52, 32, 70, 147, 249, 18, ++ 16, 12, 240, 32, 218, 32, 70, 30, 240, 39, 216, 32, 70, 30, 240, 16, ++ 216, 32, 70, 41, 70, 30, 240, 200, 216, 227, 104, 132, 248, 72, 86, ++ 211, 248, 36, 33, 41, 70, 66, 240, 64, 2, 195, 248, 36, 33, 35, 106, ++ 0, 34, 24, 105, 28, 240, 35, 254, 32, 70, 132, 248, 116, 86, 53, 240, ++ 104, 223, 126, 33, 32, 105, 51, 240, 222, 218, 66, 30, 146, 178, 79, ++ 246, 253, 115, 154, 66, 7, 216, 16, 250, 5, 243, 64, 25, 168, 64, 164, ++ 248, 64, 56, 164, 248, 66, 8, 180, 248, 64, 24, 33, 177, 32, 70, 180, ++ 248, 92, 39, 30, 240, 40, 218, 180, 248, 66, 24, 73, 177, 32, 70, 180, ++ 248, 68, 40, 30, 240, 32, 218, 0, 32, 3, 224, 111, 240, 8, 0, 0, 224, ++ 8, 70, 62, 189, 83, 28, 3, 208, 1, 35, 19, 250, 2, 242, 0, 224, 255, ++ 34, 209, 248, 204, 0, 16, 64, 194, 235, 0, 12, 220, 241, 0, 0, 64, 235, ++ 12, 0, 112, 71, 209, 248, 204, 48, 26, 66, 12, 191, 0, 32, 1, 32, 112, ++ 71, 112, 181, 92, 28, 2, 208, 1, 36, 156, 64, 0, 224, 255, 36, 209, ++ 248, 204, 80, 4, 234, 5, 6, 26, 177, 166, 66, 15, 208, 44, 67, 2, 224, ++ 102, 177, 37, 234, 4, 4, 193, 248, 204, 64, 209, 248, 204, 64, 52, 240, ++ 255, 5, 3, 209, 189, 232, 112, 64, 251, 247, 88, 184, 112, 189, 45, ++ 233, 240, 71, 23, 70, 209, 248, 248, 32, 4, 70, 14, 70, 10, 185, 10, ++ 105, 210, 104, 213, 104, 186, 105, 41, 29, 18, 244, 128, 111, 34, 104, ++ 32, 70, 210, 105, 183, 248, 14, 144, 20, 191, 210, 248, 52, 128, 210, ++ 248, 48, 128, 58, 70, 251, 247, 52, 253, 168, 185, 1, 34, 96, 104, 57, ++ 70, 248, 247, 8, 254, 35, 104, 211, 248, 136, 48, 26, 106, 1, 50, 26, ++ 98, 51, 105, 27, 177, 219, 104, 26, 106, 1, 50, 26, 98, 214, 248, 92, ++ 49, 1, 51, 198, 248, 92, 49, 35, 104, 90, 107, 18, 177, 154, 109, 18, ++ 7, 8, 213, 107, 137, 67, 69, 25, 219, 32, 70, 41, 70, 1, 34, 79, 240, ++ 255, 51, 15, 224, 147, 248, 83, 48, 131, 177, 9, 74, 9, 240, 7, 3, 210, ++ 92, 12, 33, 1, 251, 2, 82, 146, 138, 66, 69, 6, 219, 32, 70, 41, 70, ++ 1, 34, 189, 232, 240, 71, 255, 247, 139, 191, 189, 232, 240, 135, 72, ++ 194, 135, 0, 45, 233, 240, 65, 209, 248, 204, 64, 6, 70, 13, 70, 36, ++ 240, 255, 7, 42, 177, 35, 67, 193, 248, 204, 48, 239, 185, 1, 34, 6, ++ 224, 36, 234, 3, 4, 159, 66, 193, 248, 204, 64, 21, 209, 44, 185, 79, ++ 240, 255, 51, 189, 232, 240, 65, 250, 247, 225, 191, 7, 36, 1, 34, 162, ++ 64, 213, 248, 204, 48, 26, 64, 4, 209, 48, 70, 41, 70, 35, 70, 250, ++ 247, 213, 255, 20, 241, 255, 52, 241, 210, 189, 232, 240, 129, 209, ++ 248, 204, 48, 16, 181, 12, 70, 59, 177, 79, 240, 255, 51, 0, 34, 250, ++ 247, 198, 255, 0, 35, 196, 248, 204, 48, 16, 189, 56, 181, 5, 70, 208, ++ 248, 120, 66, 4, 224, 33, 70, 40, 70, 255, 247, 233, 255, 36, 104, 0, ++ 44, 248, 209, 56, 189, 121, 177, 114, 177, 72, 106, 11, 106, 195, 24, ++ 203, 97, 8, 109, 203, 108, 195, 24, 72, 109, 27, 24, 139, 100, 16, 70, ++ 20, 49, 72, 34, 239, 247, 167, 189, 112, 71, 45, 233, 240, 71, 0, 38, ++ 142, 176, 5, 70, 138, 70, 144, 70, 15, 70, 52, 70, 30, 224, 249, 7, ++ 26, 213, 107, 105, 83, 248, 38, 144, 185, 241, 0, 15, 12, 209, 19, 224, ++ 184, 241, 1, 15, 4, 209, 104, 104, 66, 70, 248, 247, 92, 253, 3, 224, ++ 4, 177, 36, 136, 204, 130, 12, 70, 74, 75, 1, 33, 72, 70, 219, 107, ++ 152, 71, 1, 70, 0, 40, 235, 209, 1, 54, 127, 8, 0, 47, 222, 209, 213, ++ 248, 180, 117, 7, 241, 4, 9, 82, 224, 66, 75, 226, 138, 27, 104, 40, ++ 70, 83, 248, 34, 128, 0, 35, 33, 70, 1, 170, 227, 130, 252, 247, 77, ++ 248, 40, 70, 33, 70, 1, 170, 13, 240, 249, 219, 16, 177, 227, 127, 218, ++ 6, 5, 213, 104, 104, 33, 70, 1, 34, 248, 247, 44, 253, 54, 224, 227, ++ 137, 53, 74, 3, 240, 7, 3, 209, 92, 163, 105, 67, 244, 128, 115, 35, ++ 244, 0, 66, 162, 97, 12, 34, 2, 251, 1, 114, 144, 138, 210, 138, 144, ++ 66, 32, 211, 91, 5, 166, 106, 5, 213, 213, 248, 52, 1, 49, 70, 34, 70, ++ 11, 240, 224, 252, 1, 34, 104, 104, 33, 70, 248, 247, 11, 253, 43, 104, ++ 211, 248, 136, 48, 26, 106, 1, 50, 26, 98, 46, 177, 51, 105, 27, 177, ++ 219, 104, 26, 106, 1, 50, 26, 98, 214, 248, 92, 49, 1, 51, 198, 248, ++ 92, 49, 3, 224, 72, 70, 34, 70, 242, 243, 150, 241, 68, 70, 0, 44, 170, ++ 209, 86, 70, 18, 224, 240, 7, 14, 213, 107, 105, 83, 248, 36, 48, 83, ++ 177, 235, 105, 3, 235, 68, 3, 154, 139, 19, 178, 0, 43, 3, 221, 40, ++ 70, 33, 70, 255, 247, 198, 251, 1, 52, 118, 8, 0, 46, 234, 209, 213, ++ 248, 128, 65, 197, 248, 180, 101, 133, 248, 177, 101, 100, 177, 40, ++ 70, 19, 240, 107, 254, 1, 70, 32, 70, 83, 240, 46, 221, 129, 7, 3, 213, ++ 213, 248, 128, 1, 83, 240, 44, 221, 14, 176, 189, 232, 240, 135, 0, ++ 191, 208, 134, 135, 0, 32, 7, 0, 0, 72, 194, 135, 0, 56, 181, 144, 248, ++ 177, 53, 203, 185, 26, 70, 63, 36, 20, 240, 1, 15, 5, 208, 197, 105, ++ 5, 235, 67, 5, 181, 249, 28, 80, 82, 25, 1, 51, 100, 8, 6, 43, 242, ++ 209, 1, 35, 82, 177, 192, 248, 180, 21, 128, 248, 177, 53, 63, 33, 0, ++ 105, 0, 34, 18, 240, 36, 254, 0, 32, 56, 189, 24, 70, 56, 189, 144, ++ 248, 176, 53, 131, 185, 3, 104, 147, 248, 60, 48, 43, 177, 208, 248, ++ 172, 37, 208, 248, 164, 53, 154, 66, 6, 208, 208, 248, 172, 21, 1, 35, ++ 128, 248, 176, 53, 10, 240, 78, 153, 112, 71, 247, 181, 144, 248, 214, ++ 49, 4, 70, 0, 43, 64, 240, 175, 128, 3, 104, 30, 126, 0, 46, 0, 240, ++ 171, 128, 23, 240, 241, 218, 1, 35, 132, 248, 214, 49, 32, 105, 19, ++ 240, 248, 251, 6, 70, 32, 105, 65, 240, 199, 218, 5, 70, 16, 177, 0, ++ 39, 61, 70, 66, 224, 212, 248, 104, 1, 4, 33, 87, 240, 149, 216, 212, ++ 248, 104, 50, 95, 89, 71, 179, 187, 121, 59, 177, 59, 121, 35, 179, ++ 32, 70, 57, 70, 52, 240, 183, 222, 54, 24, 30, 224, 56, 70, 44, 240, ++ 202, 220, 123, 121, 54, 24, 195, 177, 35, 104, 32, 70, 147, 248, 49, ++ 48, 57, 70, 91, 177, 215, 248, 204, 48, 223, 7, 7, 213, 52, 240, 163, ++ 222, 54, 24, 212, 248, 92, 1, 61, 240, 92, 216, 6, 224, 52, 240, 89, ++ 222, 54, 24, 79, 244, 122, 96, 245, 243, 84, 243, 4, 53, 32, 45, 207, ++ 209, 198, 231, 212, 248, 168, 50, 219, 25, 27, 107, 43, 177, 212, 248, ++ 172, 34, 82, 248, 37, 0, 152, 71, 54, 24, 1, 53, 56, 55, 35, 104, 147, ++ 248, 184, 48, 157, 66, 237, 219, 148, 248, 46, 50, 75, 177, 160, 104, ++ 212, 248, 236, 17, 6, 240, 44, 220, 0, 185, 1, 54, 0, 35, 132, 248, ++ 46, 50, 32, 70, 251, 247, 122, 248, 35, 104, 0, 33, 25, 118, 35, 106, ++ 79, 240, 255, 50, 134, 25, 24, 105, 27, 240, 215, 249, 32, 70, 12, 240, ++ 155, 221, 32, 70, 255, 247, 107, 254, 212, 248, 120, 82, 7, 224, 0, ++ 35, 41, 29, 96, 104, 1, 34, 0, 147, 241, 243, 160, 247, 45, 104, 0, ++ 45, 245, 209, 212, 248, 124, 2, 16, 177, 62, 240, 54, 222, 54, 24, 32, ++ 105, 50, 240, 124, 220, 0, 37, 134, 25, 212, 248, 104, 50, 89, 89, 97, ++ 177, 139, 121, 83, 185, 35, 104, 147, 248, 49, 48, 27, 177, 209, 248, ++ 204, 48, 216, 7, 2, 212, 32, 70, 69, 240, 39, 217, 4, 53, 32, 45, 235, ++ 209, 0, 35, 99, 118, 132, 248, 214, 49, 0, 224, 0, 38, 48, 70, 254, ++ 189, 45, 233, 247, 67, 11, 158, 23, 70, 179, 137, 72, 246, 142, 2, 79, ++ 234, 19, 40, 72, 234, 3, 40, 31, 250, 136, 248, 194, 235, 8, 12, 220, ++ 241, 0, 8, 72, 235, 12, 8, 5, 70, 12, 70, 184, 241, 0, 15, 13, 208, ++ 97, 177, 145, 248, 80, 51, 75, 177, 57, 70, 6, 34, 0, 35, 250, 247, ++ 249, 253, 24, 177, 40, 70, 33, 70, 53, 240, 180, 219, 148, 248, 6, 144, ++ 185, 241, 0, 15, 20, 209, 32, 70, 12, 153, 81, 240, 249, 216, 212, 248, ++ 4, 49, 147, 248, 72, 48, 91, 177, 57, 70, 104, 104, 246, 247, 86, 251, ++ 1, 33, 3, 70, 74, 70, 32, 70, 205, 248, 0, 144, 81, 240, 84, 217, 184, ++ 241, 0, 15, 51, 208, 213, 248, 188, 54, 27, 104, 224, 88, 0, 40, 46, ++ 208, 0, 104, 96, 179, 104, 104, 57, 70, 50, 70, 18, 35, 29, 240, 211, ++ 221, 88, 177, 51, 138, 104, 104, 26, 10, 66, 234, 3, 35, 57, 70, 6, ++ 241, 18, 2, 155, 178, 29, 240, 199, 221, 64, 185, 43, 104, 79, 240, ++ 255, 48, 211, 248, 136, 48, 90, 110, 1, 50, 90, 102, 16, 224, 10, 155, ++ 213, 248, 188, 6, 27, 136, 33, 70, 50, 70, 195, 243, 128, 51, 45, 240, ++ 35, 252, 0, 40, 20, 191, 79, 240, 255, 48, 0, 32, 0, 224, 64, 70, 189, ++ 232, 254, 131, 68, 242, 33, 51, 152, 66, 82, 208, 68, 242, 19, 51, 152, ++ 66, 78, 208, 68, 242, 26, 51, 152, 66, 74, 208, 68, 242, 42, 51, 152, ++ 66, 70, 208, 68, 242, 22, 51, 152, 66, 66, 208, 68, 242, 29, 51, 152, ++ 66, 62, 208, 68, 242, 45, 51, 152, 66, 58, 208, 68, 242, 82, 51, 152, ++ 66, 54, 208, 68, 242, 90, 51, 152, 66, 50, 208, 68, 242, 72, 51, 152, ++ 66, 46, 208, 68, 242, 51, 51, 152, 66, 42, 208, 68, 242, 162, 51, 152, ++ 66, 38, 208, 68, 242, 176, 51, 152, 66, 34, 208, 68, 242, 173, 51, 152, ++ 66, 30, 208, 68, 242, 229, 51, 152, 66, 26, 208, 68, 242, 179, 51, 152, ++ 66, 22, 208, 68, 242, 165, 51, 152, 66, 18, 208, 68, 242, 185, 51, 152, ++ 66, 14, 208, 68, 242, 194, 51, 152, 66, 10, 208, 68, 242, 79, 51, 152, ++ 66, 8, 208, 68, 242, 188, 51, 195, 26, 88, 66, 64, 235, 3, 0, 112, 71, ++ 1, 32, 112, 71, 1, 32, 112, 71, 45, 233, 240, 71, 144, 248, 116, 50, ++ 162, 176, 219, 6, 4, 70, 14, 70, 0, 241, 183, 128, 144, 248, 177, 53, ++ 0, 43, 64, 240, 178, 128, 208, 248, 164, 53, 153, 66, 64, 240, 173, ++ 128, 144, 248, 32, 49, 0, 43, 64, 240, 168, 128, 1, 35, 128, 248, 32, ++ 49, 208, 248, 4, 160, 1, 241, 4, 9, 176, 248, 88, 82, 139, 224, 151, ++ 106, 57, 105, 209, 248, 204, 48, 152, 3, 27, 213, 209, 248, 148, 51, ++ 91, 7, 2, 213, 147, 105, 152, 7, 20, 212, 32, 70, 31, 155, 53, 240, ++ 61, 216, 0, 40, 120, 208, 2, 154, 147, 105, 91, 5, 4, 213, 212, 248, ++ 52, 1, 57, 70, 11, 240, 139, 250, 80, 70, 2, 153, 1, 34, 248, 247, 179, ++ 250, 105, 224, 147, 105, 88, 5, 7, 213, 212, 248, 52, 1, 49, 70, 2, ++ 170, 31, 155, 10, 240, 248, 249, 69, 224, 19, 240, 4, 3, 7, 208, 1, ++ 35, 17, 70, 32, 70, 33, 170, 32, 147, 24, 240, 179, 222, 6, 224, 0, ++ 147, 32, 70, 2, 169, 32, 170, 33, 171, 254, 247, 83, 248, 0, 40, 49, ++ 209, 33, 153, 3, 41, 9, 216, 35, 104, 147, 248, 156, 48, 1, 43, 4, 209, ++ 212, 248, 52, 1, 3, 34, 9, 240, 228, 250, 1, 175, 79, 240, 0, 8, 28, ++ 224, 121, 104, 18, 170, 32, 70, 251, 247, 144, 253, 189, 248, 76, 32, ++ 17, 4, 7, 213, 121, 104, 0, 35, 0, 147, 212, 248, 96, 1, 137, 106, 42, ++ 240, 163, 251, 1, 35, 0, 147, 1, 147, 32, 70, 33, 153, 87, 248, 4, 47, ++ 18, 171, 1, 240, 81, 252, 8, 241, 1, 8, 32, 155, 152, 69, 223, 219, ++ 24, 224, 16, 48, 22, 209, 72, 70, 31, 153, 2, 154, 241, 243, 252, 246, ++ 148, 248, 116, 50, 75, 177, 180, 248, 88, 50, 1, 34, 29, 64, 31, 155, ++ 18, 250, 3, 243, 37, 234, 3, 5, 4, 224, 180, 248, 88, 50, 157, 66, 11, ++ 208, 29, 70, 77, 177, 31, 170, 72, 70, 41, 70, 241, 243, 26, 246, 2, ++ 70, 2, 144, 0, 40, 127, 244, 105, 175, 32, 70, 49, 70, 18, 240, 99, ++ 218, 0, 35, 132, 248, 32, 49, 34, 176, 189, 232, 240, 135, 0, 0, 45, ++ 233, 243, 65, 12, 70, 25, 105, 144, 70, 5, 70, 30, 70, 8, 154, 0, 41, ++ 72, 208, 88, 104, 44, 75, 231, 137, 3, 64, 7, 240, 7, 7, 35, 177, 43, ++ 104, 91, 107, 11, 177, 40, 75, 218, 93, 166, 98, 145, 248, 68, 48, 1, ++ 146, 132, 248, 33, 48, 9, 155, 0, 34, 0, 147, 33, 70, 19, 70, 40, 70, ++ 12, 240, 34, 220, 50, 105, 33, 75, 145, 121, 25, 185, 210, 248, 148, ++ 35, 81, 7, 17, 213, 150, 248, 231, 32, 114, 177, 162, 105, 146, 7, 11, ++ 212, 218, 93, 13, 42, 1, 220, 1, 50, 0, 224, 15, 34, 40, 70, 33, 70, ++ 13, 240, 77, 254, 168, 177, 33, 224, 219, 93, 8, 241, 4, 1, 13, 43, ++ 1, 220, 1, 51, 0, 224, 15, 35, 40, 70, 34, 70, 251, 247, 14, 249, 56, ++ 177, 157, 248, 40, 48, 139, 185, 40, 70, 65, 70, 255, 247, 233, 254, ++ 12, 224, 104, 104, 1, 34, 33, 70, 248, 247, 218, 249, 43, 104, 0, 32, ++ 211, 248, 136, 48, 26, 106, 1, 50, 26, 98, 0, 224, 1, 32, 189, 232, ++ 252, 129, 0, 191, 64, 0, 1, 0, 138, 182, 135, 0, 72, 194, 135, 0, 45, ++ 233, 240, 79, 181, 176, 221, 248, 252, 128, 13, 147, 184, 248, 10, 112, ++ 13, 70, 173, 248, 88, 112, 17, 70, 191, 178, 145, 70, 18, 151, 4, 70, ++ 13, 240, 162, 223, 185, 248, 22, 112, 192, 178, 26, 151, 185, 248, 4, ++ 112, 16, 144, 13, 153, 72, 70, 27, 151, 37, 240, 186, 253, 65, 159, ++ 79, 240, 0, 10, 135, 248, 0, 160, 8, 241, 12, 7, 21, 151, 64, 159, 15, ++ 144, 12, 63, 24, 151, 16, 159, 221, 248, 96, 176, 12, 151, 21, 158, ++ 205, 248, 68, 160, 205, 248, 36, 160, 205, 248, 100, 160, 205, 248, ++ 40, 160, 205, 248, 56, 160, 205, 248, 44, 160, 205, 248, 80, 160, 205, ++ 248, 76, 160, 205, 248, 32, 160, 205, 248, 28, 160, 47, 70, 79, 224, ++ 51, 120, 149, 28, 45, 43, 33, 208, 7, 216, 1, 43, 19, 208, 67, 211, ++ 3, 43, 18, 208, 42, 43, 64, 209, 20, 224, 61, 43, 29, 208, 5, 216, 8, ++ 153, 50, 43, 8, 191, 49, 70, 8, 145, 54, 224, 74, 43, 27, 208, 221, ++ 43, 50, 209, 31, 224, 7, 150, 47, 224, 178, 120, 79, 240, 1, 10, 12, ++ 146, 42, 224, 179, 28, 19, 147, 20, 146, 38, 224, 32, 70, 49, 70, 42, ++ 70, 66, 240, 18, 223, 10, 144, 31, 224, 32, 70, 49, 70, 42, 70, 66, ++ 240, 225, 222, 14, 144, 24, 224, 32, 70, 49, 70, 42, 70, 65, 240, 82, ++ 223, 25, 144, 17, 224, 3, 42, 15, 217, 176, 28, 4, 34, 143, 73, 239, ++ 247, 94, 249, 17, 155, 0, 40, 8, 191, 43, 70, 17, 147, 9, 155, 8, 191, ++ 51, 70, 9, 147, 0, 224, 11, 150, 118, 25, 197, 235, 11, 11, 187, 241, ++ 1, 15, 3, 221, 114, 120, 83, 28, 91, 69, 168, 219, 61, 70, 9, 159, 63, ++ 177, 10, 159, 47, 185, 32, 70, 9, 153, 17, 154, 66, 240, 144, 222, 10, ++ 144, 0, 45, 119, 209, 18, 159, 187, 7, 64, 241, 214, 131, 11, 155, 0, ++ 43, 0, 240, 210, 131, 32, 70, 153, 28, 90, 120, 19, 240, 55, 251, 49, ++ 144, 0, 40, 0, 240, 201, 131, 3, 124, 0, 43, 64, 240, 197, 131, 3, 122, ++ 0, 43, 0, 240, 193, 131, 208, 248, 244, 48, 88, 142, 241, 243, 43, 247, ++ 12, 159, 135, 66, 64, 240, 184, 131, 49, 158, 32, 70, 49, 70, 11, 240, ++ 42, 221, 0, 40, 69, 208, 48, 70, 73, 70, 13, 154, 67, 70, 17, 240, 0, ++ 220, 0, 40, 61, 208, 64, 153, 62, 155, 214, 248, 240, 112, 3, 241, 16, ++ 2, 1, 145, 32, 70, 73, 70, 1, 35, 205, 248, 0, 128, 2, 151, 25, 240, ++ 17, 222, 0, 40, 46, 209, 59, 142, 35, 177, 35, 104, 147, 248, 73, 49, ++ 0, 43, 42, 208, 33, 106, 212, 248, 116, 52, 80, 49, 0, 34, 7, 241, 56, ++ 0, 155, 120, 37, 240, 96, 252, 64, 159, 48, 70, 73, 70, 13, 154, 67, ++ 70, 0, 151, 16, 240, 172, 254, 0, 35, 0, 147, 1, 147, 50, 124, 32, 70, ++ 215, 26, 122, 66, 66, 235, 7, 2, 2, 146, 3, 147, 4, 147, 49, 70, 125, ++ 34, 6, 241, 188, 3, 17, 240, 240, 221, 1, 39, 2, 224, 11, 149, 3, 224, ++ 0, 39, 11, 151, 0, 224, 11, 147, 78, 179, 53, 70, 1, 224, 0, 39, 11, ++ 151, 26, 159, 62, 153, 23, 244, 64, 79, 12, 191, 79, 240, 0, 11, 79, ++ 240, 1, 11, 1, 241, 10, 7, 32, 70, 41, 70, 58, 70, 91, 70, 42, 240, ++ 144, 248, 6, 70, 0, 187, 43, 124, 0, 43, 64, 240, 76, 131, 32, 70, 41, ++ 70, 58, 70, 91, 70, 42, 240, 55, 249, 6, 70, 0, 40, 0, 240, 66, 131, ++ 32, 70, 49, 70, 87, 240, 102, 223, 13, 224, 148, 248, 114, 50, 0, 43, ++ 0, 240, 56, 131, 62, 159, 32, 70, 7, 241, 10, 1, 49, 170, 87, 240, 145, ++ 223, 6, 70, 16, 177, 115, 104, 216, 7, 32, 212, 8, 159, 39, 177, 120, ++ 120, 185, 28, 25, 240, 124, 221, 88, 185, 7, 159, 103, 177, 185, 28, ++ 120, 120, 25, 240, 117, 221, 16, 241, 0, 11, 24, 191, 79, 240, 1, 11, ++ 4, 224, 79, 240, 1, 11, 1, 224, 221, 248, 28, 176, 102, 177, 187, 241, ++ 0, 15, 7, 209, 115, 104, 67, 240, 1, 3, 115, 96, 4, 224, 79, 240, 0, ++ 11, 1, 224, 79, 240, 1, 11, 205, 177, 171, 121, 219, 185, 43, 122, 3, ++ 179, 213, 248, 244, 48, 91, 142, 7, 147, 3, 244, 96, 83, 163, 245, 192, ++ 82, 83, 66, 67, 235, 2, 3, 7, 152, 8, 147, 241, 243, 94, 246, 12, 159, ++ 193, 27, 72, 66, 64, 235, 1, 0, 9, 144, 13, 224, 8, 149, 7, 149, 9, ++ 149, 9, 224, 0, 39, 8, 151, 7, 151, 9, 151, 4, 224, 254, 20, 4, 0, 8, ++ 147, 7, 147, 9, 147, 180, 248, 114, 50, 0, 43, 127, 208, 35, 106, 91, ++ 125, 195, 177, 12, 159, 212, 248, 108, 4, 14, 47, 140, 191, 79, 244, ++ 64, 66, 0, 34, 71, 244, 128, 81, 18, 159, 17, 67, 7, 240, 32, 3, 211, ++ 241, 1, 3, 56, 191, 0, 35, 1, 147, 19, 154, 20, 155, 205, 248, 0, 176, ++ 81, 240, 155, 223, 35, 104, 147, 248, 79, 48, 155, 7, 18, 208, 12, 159, ++ 212, 248, 112, 4, 14, 47, 140, 191, 79, 244, 64, 67, 0, 35, 71, 244, ++ 128, 81, 8, 159, 25, 67, 14, 154, 10, 155, 205, 248, 0, 176, 1, 151, ++ 82, 240, 181, 220, 148, 248, 114, 50, 0, 43, 71, 208, 0, 33, 12, 34, ++ 46, 168, 240, 243, 142, 243, 148, 75, 29, 175, 46, 147, 148, 75, 56, ++ 70, 0, 33, 36, 34, 47, 147, 48, 148, 240, 243, 131, 243, 189, 248, 88, ++ 16, 13, 241, 152, 12, 221, 248, 48, 224, 173, 248, 122, 16, 96, 70, ++ 0, 33, 32, 34, 205, 248, 24, 192, 29, 150, 141, 248, 120, 224, 141, ++ 248, 124, 176, 240, 243, 111, 243, 45, 151, 13, 159, 35, 104, 39, 151, ++ 62, 159, 147, 248, 79, 48, 40, 151, 16, 159, 3, 240, 3, 3, 141, 248, ++ 168, 112, 15, 159, 221, 248, 24, 192, 43, 151, 21, 159, 141, 248, 176, ++ 48, 1, 151, 24, 159, 212, 248, 124, 6, 0, 33, 144, 34, 46, 171, 205, ++ 248, 152, 144, 205, 248, 164, 128, 205, 248, 0, 192, 2, 151, 64, 240, ++ 195, 223, 148, 248, 112, 50, 0, 43, 0, 240, 86, 130, 9, 159, 0, 47, ++ 0, 240, 82, 130, 35, 104, 147, 248, 79, 32, 151, 7, 0, 240, 138, 128, ++ 14, 159, 0, 47, 0, 240, 134, 128, 10, 159, 0, 47, 0, 240, 130, 128, ++ 147, 248, 173, 48, 51, 177, 212, 248, 124, 1, 41, 70, 61, 240, 186, ++ 222, 0, 40, 119, 209, 14, 159, 32, 70, 122, 120, 57, 120, 23, 240, 94, ++ 216, 7, 159, 3, 70, 23, 244, 64, 79, 12, 191, 0, 34, 1, 34, 10, 50, ++ 84, 248, 34, 32, 17, 146, 213, 248, 244, 32, 98, 177, 210, 136, 18, ++ 240, 32, 2, 8, 208, 10, 159, 58, 120, 18, 240, 2, 2, 3, 208, 14, 159, ++ 122, 120, 194, 243, 128, 2, 9, 146, 186, 241, 0, 15, 11, 209, 16, 159, ++ 218, 178, 186, 66, 7, 208, 24, 70, 6, 147, 241, 243, 119, 245, 184, ++ 66, 6, 155, 64, 240, 9, 130, 213, 248, 244, 32, 0, 42, 45, 208, 24, ++ 70, 6, 147, 241, 243, 107, 245, 7, 70, 7, 152, 241, 243, 103, 245, 135, ++ 66, 6, 155, 34, 209, 213, 248, 244, 32, 82, 142, 154, 66, 50, 208, 0, ++ 46, 48, 208, 42, 122, 0, 42, 45, 208, 32, 70, 17, 153, 42, 70, 23, 240, ++ 3, 223, 255, 40, 7, 70, 0, 240, 231, 129, 221, 248, 36, 224, 32, 70, ++ 41, 70, 58, 70, 95, 250, 142, 243, 250, 247, 25, 248, 208, 177, 32, ++ 70, 41, 70, 58, 70, 29, 240, 48, 216, 20, 224, 186, 241, 0, 15, 17, ++ 208, 24, 70, 6, 147, 241, 243, 58, 245, 12, 159, 6, 155, 184, 66, 0, ++ 240, 203, 129, 3, 244, 96, 83, 179, 245, 128, 95, 3, 208, 179, 245, ++ 192, 95, 64, 240, 194, 129, 65, 159, 1, 35, 59, 112, 35, 104, 213, 248, ++ 4, 161, 147, 248, 79, 48, 152, 7, 22, 208, 174, 177, 10, 159, 55, 177, ++ 25, 159, 32, 70, 0, 151, 49, 70, 10, 154, 14, 155, 10, 224, 43, 124, ++ 83, 185, 115, 104, 217, 3, 7, 213, 10, 159, 32, 70, 0, 151, 49, 70, ++ 58, 70, 59, 70, 11, 240, 3, 216, 43, 124, 0, 43, 0, 240, 191, 128, 62, ++ 159, 13, 155, 32, 70, 41, 70, 74, 70, 141, 232, 128, 1, 9, 240, 202, ++ 221, 35, 104, 147, 248, 60, 48, 67, 177, 13, 159, 32, 70, 41, 70, 50, ++ 70, 75, 70, 141, 232, 128, 1, 72, 240, 139, 222, 154, 248, 9, 48, 27, ++ 177, 40, 70, 0, 33, 27, 240, 70, 219, 154, 248, 13, 48, 219, 177, 212, ++ 248, 28, 55, 26, 104, 10, 177, 31, 122, 55, 177, 40, 70, 0, 33, 16, ++ 224, 37, 206, 129, 0, 41, 206, 129, 0, 244, 243, 102, 244, 212, 248, ++ 28, 55, 26, 105, 130, 26, 178, 245, 122, 127, 5, 217, 1, 34, 26, 114, ++ 40, 70, 57, 70, 27, 240, 255, 221, 212, 248, 28, 55, 27, 104, 0, 43, ++ 72, 208, 27, 159, 1, 35, 199, 243, 192, 18, 15, 153, 32, 70, 17, 240, ++ 146, 223, 152, 248, 2, 48, 152, 248, 1, 16, 27, 4, 67, 234, 1, 35, 152, ++ 248, 0, 16, 184, 248, 8, 112, 11, 67, 152, 248, 3, 16, 2, 70, 67, 234, ++ 1, 99, 50, 147, 152, 248, 6, 48, 152, 248, 5, 16, 27, 4, 67, 234, 1, ++ 35, 152, 248, 4, 16, 52, 168, 11, 67, 152, 248, 7, 16, 0, 47, 8, 191, ++ 100, 39, 67, 234, 1, 99, 64, 248, 4, 61, 50, 169, 245, 247, 221, 255, ++ 56, 70, 50, 154, 51, 153, 98, 240, 98, 221, 212, 248, 28, 55, 191, 2, ++ 26, 104, 186, 26, 144, 66, 11, 217, 90, 104, 186, 26, 144, 66, 7, 210, ++ 63, 26, 95, 96, 212, 248, 72, 1, 41, 70, 1, 34, 74, 240, 165, 217, 35, ++ 106, 91, 125, 43, 177, 18, 159, 32, 70, 199, 243, 128, 33, 28, 240, ++ 56, 219, 212, 248, 92, 1, 7, 153, 60, 240, 107, 218, 128, 177, 212, ++ 248, 92, 1, 7, 153, 59, 240, 85, 221, 35, 106, 24, 105, 26, 240, 121, ++ 252, 7, 159, 184, 66, 4, 209, 0, 33, 32, 70, 10, 70, 23, 240, 19, 223, ++ 74, 70, 13, 155, 212, 248, 72, 1, 41, 70, 205, 248, 0, 128, 73, 240, ++ 254, 220, 213, 248, 204, 48, 154, 4, 88, 213, 212, 248, 80, 1, 41, 70, ++ 66, 70, 64, 155, 25, 240, 254, 252, 80, 224, 187, 241, 0, 15, 3, 209, ++ 18, 159, 199, 243, 64, 19, 0, 224, 1, 35, 219, 178, 62, 177, 114, 104, ++ 19, 177, 66, 240, 4, 2, 1, 224, 34, 240, 4, 2, 114, 96, 34, 106, 82, ++ 125, 74, 177, 1, 147, 212, 248, 108, 4, 41, 70, 19, 154, 20, 155, 205, ++ 248, 0, 176, 81, 240, 243, 221, 35, 104, 147, 248, 79, 48, 155, 7, 10, ++ 208, 8, 159, 212, 248, 112, 4, 41, 70, 14, 154, 10, 155, 205, 248, 0, ++ 176, 1, 151, 82, 240, 21, 219, 11, 159, 255, 185, 212, 248, 108, 50, ++ 157, 66, 12, 208, 40, 70, 73, 70, 13, 154, 67, 70, 17, 240, 243, 216, ++ 40, 177, 40, 70, 73, 70, 13, 154, 67, 70, 28, 240, 152, 219, 148, 248, ++ 114, 50, 91, 185, 212, 248, 108, 50, 157, 66, 7, 209, 40, 70, 249, 247, ++ 26, 254, 24, 177, 32, 70, 65, 70, 15, 240, 127, 216, 0, 33, 12, 34, ++ 46, 168, 240, 243, 120, 241, 69, 75, 29, 175, 46, 147, 69, 75, 0, 33, ++ 36, 34, 56, 70, 47, 147, 48, 148, 240, 243, 109, 241, 189, 248, 88, ++ 16, 221, 248, 48, 224, 29, 150, 38, 174, 32, 34, 173, 248, 122, 16, ++ 48, 70, 0, 33, 141, 248, 120, 224, 141, 248, 124, 176, 240, 243, 92, ++ 241, 45, 151, 13, 159, 35, 104, 39, 151, 62, 159, 147, 248, 79, 48, ++ 40, 151, 16, 159, 3, 240, 3, 3, 141, 248, 168, 112, 15, 159, 141, 248, ++ 176, 48, 43, 151, 21, 159, 128, 34, 1, 151, 24, 159, 46, 171, 212, 248, ++ 124, 6, 41, 70, 205, 248, 152, 144, 205, 248, 164, 128, 0, 150, 2, 151, ++ 64, 240, 179, 221, 154, 248, 2, 48, 1, 59, 219, 178, 1, 43, 19, 216, ++ 171, 121, 139, 185, 42, 124, 122, 177, 213, 248, 4, 33, 146, 248, 108, ++ 32, 2, 42, 9, 209, 79, 240, 255, 50, 1, 146, 32, 70, 41, 70, 5, 241, ++ 188, 2, 0, 147, 26, 240, 157, 219, 15, 159, 23, 240, 64, 127, 1, 209, ++ 56, 70, 2, 224, 15, 152, 37, 240, 98, 248, 0, 240, 127, 0, 2, 40, 10, ++ 208, 4, 40, 8, 208, 11, 40, 6, 208, 160, 241, 22, 12, 220, 241, 0, 0, ++ 64, 235, 12, 0, 0, 224, 1, 32, 1, 144, 185, 248, 4, 0, 185, 248, 6, ++ 16, 128, 11, 2, 144, 1, 32, 0, 34, 3, 144, 153, 249, 28, 48, 32, 70, ++ 9, 10, 0, 146, 4, 149, 45, 240, 252, 249, 4, 224, 0, 39, 11, 151, 194, ++ 228, 0, 38, 209, 228, 53, 176, 189, 232, 240, 143, 0, 191, 37, 206, ++ 129, 0, 41, 206, 129, 0, 45, 233, 240, 79, 145, 249, 21, 48, 159, 176, ++ 0, 37, 4, 70, 137, 70, 28, 149, 29, 149, 123, 177, 15, 240, 173, 219, ++ 96, 177, 35, 104, 185, 248, 28, 32, 211, 248, 136, 48, 171, 70, 211, ++ 248, 200, 17, 138, 24, 195, 248, 200, 33, 0, 240, 79, 188, 185, 248, ++ 2, 48, 96, 104, 3, 240, 7, 3, 5, 43, 9, 144, 8, 147, 0, 242, 67, 132, ++ 99, 105, 8, 153, 83, 248, 33, 0, 0, 40, 0, 240, 60, 132, 153, 248, 24, ++ 32, 2, 42, 7, 146, 0, 240, 51, 132, 112, 75, 2, 33, 219, 107, 152, 71, ++ 128, 70, 56, 185, 32, 70, 8, 153, 8, 240, 94, 221, 128, 70, 0, 40, 0, ++ 240, 40, 132, 32, 70, 65, 70, 15, 170, 251, 247, 6, 248, 35, 104, 147, ++ 248, 156, 48, 1, 43, 6, 208, 185, 248, 2, 32, 189, 248, 64, 48, 154, ++ 66, 64, 240, 29, 132, 184, 248, 14, 48, 97, 78, 3, 240, 7, 3, 243, 92, ++ 96, 77, 65, 70, 235, 92, 15, 170, 10, 147, 22, 155, 11, 147, 24, 136, ++ 28, 171, 12, 144, 0, 147, 32, 70, 29, 171, 250, 247, 148, 248, 35, 104, ++ 147, 248, 79, 48, 153, 7, 23, 208, 15, 168, 249, 247, 141, 253, 56, ++ 177, 35, 104, 211, 248, 136, 48, 211, 248, 164, 34, 1, 50, 195, 248, ++ 164, 34, 15, 168, 249, 247, 147, 253, 56, 177, 35, 104, 211, 248, 136, ++ 48, 211, 248, 172, 34, 1, 50, 195, 248, 172, 34, 216, 248, 24, 48, 90, ++ 5, 108, 213, 15, 173, 32, 70, 41, 70, 250, 247, 184, 255, 8, 187, 75, ++ 70, 212, 248, 52, 1, 28, 153, 66, 70, 0, 149, 9, 240, 65, 252, 35, 104, ++ 147, 248, 229, 48, 0, 43, 89, 208, 28, 153, 0, 41, 86, 208, 189, 248, ++ 72, 0, 185, 248, 2, 32, 0, 144, 189, 248, 70, 48, 212, 248, 228, 6, ++ 87, 240, 2, 221, 212, 248, 96, 1, 28, 153, 10, 154, 41, 240, 136, 255, ++ 68, 224, 29, 153, 161, 177, 7, 154, 7, 42, 17, 209, 209, 248, 204, 48, ++ 155, 3, 13, 212, 212, 248, 80, 1, 78, 240, 204, 221, 40, 185, 212, 248, ++ 80, 1, 29, 153, 78, 240, 40, 222, 16, 177, 29, 152, 52, 240, 116, 218, ++ 15, 171, 0, 147, 212, 248, 52, 1, 75, 70, 28, 153, 66, 70, 9, 240, 9, ++ 252, 35, 104, 131, 70, 147, 248, 229, 48, 147, 177, 28, 153, 129, 177, ++ 189, 248, 72, 0, 185, 248, 2, 32, 0, 144, 189, 248, 70, 48, 212, 248, ++ 228, 6, 87, 240, 201, 220, 212, 248, 96, 1, 28, 153, 10, 154, 41, 240, ++ 79, 255, 29, 152, 0, 40, 0, 240, 127, 131, 131, 121, 0, 43, 64, 240, ++ 123, 131, 9, 241, 8, 1, 80, 240, 161, 217, 117, 227, 32, 70, 15, 169, ++ 216, 248, 52, 112, 249, 247, 45, 253, 185, 248, 28, 96, 255, 14, 7, ++ 240, 1, 7, 13, 144, 185, 248, 26, 80, 230, 177, 35, 104, 211, 248, 136, ++ 48, 218, 104, 1, 58, 146, 25, 218, 96, 28, 155, 155, 177, 103, 177, ++ 211, 248, 60, 34, 1, 58, 146, 25, 195, 248, 60, 34, 11, 224, 208, 134, ++ 135, 0, 138, 182, 135, 0, 84, 194, 135, 0, 211, 248, 72, 34, 1, 58, ++ 146, 25, 195, 248, 72, 34, 53, 177, 35, 104, 211, 248, 136, 48, 218, ++ 104, 1, 58, 82, 25, 218, 96, 12, 155, 9, 152, 3, 244, 128, 107, 219, ++ 241, 1, 11, 65, 70, 56, 191, 79, 240, 0, 11, 245, 247, 198, 251, 216, ++ 248, 24, 48, 153, 249, 25, 32, 195, 243, 192, 106, 0, 42, 121, 208, ++ 35, 104, 211, 248, 136, 48, 211, 248, 168, 33, 1, 50, 195, 248, 168, ++ 33, 211, 248, 200, 33, 1, 58, 146, 25, 195, 248, 200, 33, 28, 155, 43, ++ 177, 26, 105, 26, 177, 210, 104, 209, 107, 1, 49, 209, 99, 1, 46, 5, ++ 221, 212, 248, 124, 84, 1, 61, 173, 25, 196, 248, 124, 84, 187, 241, ++ 0, 15, 66, 208, 34, 104, 210, 248, 136, 32, 210, 248, 216, 17, 1, 49, ++ 194, 248, 216, 17, 43, 177, 26, 105, 26, 177, 210, 104, 81, 107, 1, ++ 49, 81, 99, 212, 248, 124, 36, 114, 177, 34, 104, 210, 248, 136, 32, ++ 210, 248, 180, 17, 1, 49, 194, 248, 180, 17, 43, 177, 27, 105, 27, 177, ++ 219, 104, 218, 106, 1, 50, 218, 98, 212, 248, 124, 52, 1, 43, 15, 217, ++ 35, 104, 211, 248, 136, 48, 211, 248, 184, 33, 1, 50, 195, 248, 184, ++ 33, 28, 155, 43, 177, 27, 105, 27, 177, 219, 104, 26, 107, 1, 50, 26, ++ 99, 28, 155, 91, 177, 47, 177, 211, 248, 56, 34, 1, 50, 195, 248, 56, ++ 34, 4, 224, 211, 248, 68, 34, 1, 50, 195, 248, 68, 34, 28, 155, 19, ++ 177, 34, 104, 146, 106, 154, 98, 29, 155, 0, 43, 0, 240, 230, 129, 154, ++ 121, 0, 42, 64, 240, 208, 130, 29, 124, 0, 45, 0, 240, 205, 130, 211, ++ 248, 252, 48, 21, 70, 154, 113, 199, 226, 19, 244, 130, 83, 63, 208, ++ 35, 104, 211, 248, 136, 48, 211, 248, 168, 33, 1, 50, 195, 248, 168, ++ 33, 28, 155, 43, 177, 26, 105, 26, 177, 210, 104, 209, 107, 1, 49, 209, ++ 99, 187, 241, 0, 15, 28, 208, 34, 104, 210, 248, 136, 32, 210, 248, ++ 216, 17, 1, 49, 194, 248, 216, 17, 155, 177, 26, 105, 0, 42, 0, 240, ++ 155, 130, 210, 104, 81, 107, 1, 49, 81, 99, 149, 226, 211, 248, 56, ++ 34, 1, 50, 195, 248, 56, 34, 4, 224, 211, 248, 68, 34, 1, 50, 195, 248, ++ 68, 34, 28, 154, 0, 42, 0, 240, 164, 129, 29, 155, 0, 43, 0, 240, 165, ++ 129, 157, 121, 0, 45, 64, 240, 165, 129, 35, 104, 155, 106, 147, 98, ++ 161, 225, 7, 152, 3, 40, 0, 240, 161, 129, 4, 40, 8, 209, 34, 104, 210, ++ 248, 136, 32, 210, 248, 16, 18, 1, 49, 194, 248, 16, 18, 149, 225, 7, ++ 153, 5, 41, 35, 209, 35, 104, 90, 107, 211, 248, 140, 16, 58, 177, 184, ++ 248, 14, 32, 140, 72, 2, 240, 7, 2, 130, 92, 139, 72, 130, 92, 20, 50, ++ 1, 235, 194, 1, 74, 104, 211, 248, 136, 48, 1, 50, 74, 96, 211, 248, ++ 160, 34, 180, 248, 36, 85, 1, 50, 195, 248, 160, 34, 0, 45, 0, 240, ++ 121, 129, 32, 70, 254, 247, 39, 251, 0, 37, 115, 225, 7, 153, 1, 41, ++ 31, 209, 29, 155, 139, 177, 155, 121, 123, 177, 28, 155, 107, 177, 26, ++ 125, 208, 7, 3, 212, 147, 248, 36, 48, 153, 7, 8, 213, 32, 70, 65, 70, ++ 74, 70, 91, 70, 13, 240, 159, 249, 82, 224, 7, 159, 0, 224, 1, 39, 32, ++ 70, 9, 241, 20, 1, 15, 240, 98, 217, 0, 37, 46, 70, 170, 70, 94, 225, ++ 7, 154, 6, 42, 0, 240, 72, 129, 7, 42, 69, 209, 29, 153, 0, 41, 236, ++ 208, 209, 248, 204, 48, 154, 0, 232, 213, 155, 3, 13, 212, 212, 248, ++ 80, 1, 78, 240, 35, 220, 40, 185, 212, 248, 80, 1, 29, 153, 78, 240, ++ 127, 220, 16, 177, 29, 152, 52, 240, 203, 216, 28, 153, 0, 41, 213, ++ 208, 29, 155, 155, 121, 91, 177, 145, 248, 36, 48, 159, 7, 7, 213, 139, ++ 104, 94, 6, 4, 213, 1, 34, 32, 70, 19, 70, 39, 240, 89, 219, 216, 248, ++ 24, 48, 93, 5, 68, 191, 67, 244, 128, 115, 200, 248, 24, 48, 216, 248, ++ 24, 48, 35, 244, 0, 67, 200, 248, 24, 48, 29, 155, 211, 248, 204, 48, ++ 152, 3, 179, 213, 32, 70, 28, 153, 66, 70, 23, 240, 107, 220, 7, 70, ++ 0, 40, 0, 240, 9, 129, 170, 231, 185, 248, 6, 32, 50, 177, 34, 104, ++ 210, 248, 136, 32, 145, 107, 1, 49, 145, 99, 245, 224, 25, 155, 27, ++ 120, 217, 7, 60, 213, 126, 177, 35, 104, 211, 248, 136, 48, 211, 248, ++ 168, 33, 1, 50, 195, 248, 168, 33, 28, 155, 43, 177, 27, 105, 27, 177, ++ 219, 104, 218, 107, 1, 50, 218, 99, 187, 241, 0, 15, 0, 240, 233, 128, ++ 35, 104, 211, 248, 136, 48, 211, 248, 216, 33, 1, 50, 195, 248, 216, ++ 33, 28, 155, 43, 177, 27, 105, 27, 177, 219, 104, 90, 107, 1, 50, 90, ++ 99, 0, 46, 0, 240, 216, 128, 35, 104, 28, 157, 211, 248, 136, 48, 211, ++ 248, 172, 33, 1, 50, 195, 248, 172, 33, 0, 45, 0, 240, 158, 129, 45, ++ 105, 0, 45, 0, 240, 154, 129, 235, 104, 154, 107, 1, 50, 154, 99, 147, ++ 225, 29, 155, 0, 43, 67, 208, 154, 121, 0, 42, 64, 209, 27, 124, 0, ++ 43, 61, 208, 11, 152, 3, 124, 218, 7, 57, 213, 62, 177, 35, 104, 211, ++ 248, 136, 48, 211, 248, 168, 33, 1, 50, 195, 248, 168, 33, 187, 241, ++ 0, 15, 0, 240, 167, 128, 35, 104, 211, 248, 136, 48, 211, 248, 216, ++ 33, 1, 50, 195, 248, 216, 33, 28, 155, 43, 177, 27, 105, 27, 177, 219, ++ 104, 90, 107, 1, 50, 90, 99, 0, 46, 0, 240, 150, 128, 35, 104, 28, 157, ++ 211, 248, 136, 48, 211, 248, 172, 33, 1, 50, 195, 248, 172, 33, 0, 45, ++ 0, 240, 92, 129, 43, 105, 0, 43, 0, 240, 82, 129, 219, 104, 154, 107, ++ 1, 50, 154, 99, 76, 225, 0, 191, 138, 182, 135, 0, 84, 194, 135, 0, ++ 13, 154, 180, 248, 90, 52, 26, 177, 157, 66, 3, 218, 180, 248, 92, 52, ++ 158, 66, 74, 219, 35, 104, 211, 248, 136, 48, 211, 248, 200, 81, 173, ++ 25, 195, 248, 200, 81, 187, 241, 0, 15, 104, 208, 211, 248, 176, 33, ++ 212, 248, 116, 20, 1, 50, 195, 248, 176, 33, 145, 248, 29, 49, 155, ++ 177, 32, 70, 1, 245, 130, 113, 45, 240, 16, 248, 212, 248, 116, 52, ++ 1, 34, 131, 248, 40, 33, 212, 248, 116, 52, 160, 104, 211, 248, 48, ++ 17, 211, 248, 36, 33, 0, 35, 5, 240, 195, 217, 28, 155, 131, 177, 47, ++ 177, 211, 248, 64, 34, 1, 50, 195, 248, 64, 34, 20, 225, 211, 248, 76, ++ 34, 1, 50, 195, 248, 76, 34, 14, 225, 219, 104, 154, 106, 1, 50, 154, ++ 98, 0, 38, 2, 35, 141, 232, 72, 0, 32, 70, 29, 153, 20, 34, 25, 155, ++ 2, 150, 3, 150, 4, 150, 1, 37, 16, 240, 242, 222, 42, 224, 35, 104, ++ 0, 37, 211, 248, 136, 48, 46, 70, 218, 105, 1, 39, 1, 50, 218, 97, 192, ++ 230, 29, 70, 236, 224, 1, 38, 21, 70, 55, 70, 146, 70, 26, 224, 1, 38, ++ 29, 70, 55, 70, 6, 224, 0, 37, 1, 38, 55, 70, 177, 230, 29, 70, 30, ++ 70, 1, 39, 154, 70, 13, 224, 46, 70, 1, 39, 10, 224, 5, 70, 6, 70, 130, ++ 70, 6, 224, 93, 70, 209, 224, 53, 70, 207, 224, 1, 37, 94, 70, 47, 70, ++ 180, 248, 36, 53, 67, 177, 212, 248, 40, 53, 43, 177, 7, 155, 5, 43, ++ 2, 208, 32, 70, 254, 247, 163, 249, 186, 241, 0, 15, 78, 208, 28, 155, ++ 0, 43, 75, 208, 15, 168, 249, 247, 53, 250, 157, 248, 70, 48, 130, 70, ++ 3, 240, 3, 3, 2, 59, 219, 178, 1, 43, 4, 216, 32, 70, 15, 169, 250, ++ 247, 208, 252, 0, 224, 255, 32, 8, 153, 3, 41, 10, 216, 89, 74, 83, ++ 92, 4, 235, 67, 3, 179, 248, 58, 34, 19, 9, 3, 240, 15, 3, 18, 11, 3, ++ 224, 180, 248, 94, 52, 180, 248, 96, 36, 0, 146, 0, 34, 3, 146, 189, ++ 248, 68, 32, 1, 144, 194, 243, 0, 50, 4, 146, 212, 248, 96, 1, 28, 153, ++ 74, 70, 205, 248, 8, 160, 41, 240, 133, 250, 35, 104, 147, 248, 229, ++ 48, 147, 177, 28, 153, 129, 177, 189, 248, 72, 0, 185, 248, 2, 32, 0, ++ 144, 189, 248, 70, 48, 212, 248, 228, 6, 87, 240, 161, 217, 212, 248, ++ 96, 1, 28, 153, 10, 154, 41, 240, 39, 252, 32, 70, 8, 153, 1, 34, 254, ++ 247, 12, 248, 221, 248, 116, 160, 186, 241, 0, 15, 23, 208, 9, 241, ++ 20, 1, 32, 70, 28, 240, 254, 217, 1, 70, 80, 70, 28, 240, 170, 218, ++ 12, 152, 0, 240, 252, 3, 8, 43, 1, 208, 136, 43, 7, 209, 187, 241, 0, ++ 15, 4, 208, 29, 152, 9, 241, 8, 1, 79, 240, 99, 222, 28, 153, 193, 177, ++ 11, 125, 219, 7, 21, 212, 29, 155, 155, 177, 154, 121, 138, 185, 26, ++ 124, 122, 177, 26, 122, 106, 177, 211, 248, 204, 32, 144, 4, 9, 212, ++ 211, 248, 252, 48, 91, 121, 43, 185, 32, 70, 74, 70, 51, 70, 0, 149, ++ 46, 240, 2, 218, 127, 177, 9, 241, 20, 1, 32, 70, 28, 240, 202, 217, ++ 65, 70, 2, 70, 212, 248, 120, 4, 79, 240, 28, 216, 9, 152, 65, 70, 1, ++ 34, 247, 247, 219, 248, 187, 241, 0, 15, 9, 208, 79, 240, 0, 11, 196, ++ 248, 124, 180, 4, 224, 79, 240, 0, 11, 1, 224, 79, 240, 1, 11, 88, 70, ++ 31, 176, 189, 232, 240, 143, 9, 152, 65, 70, 1, 34, 247, 247, 197, 248, ++ 243, 231, 0, 47, 127, 244, 103, 173, 107, 229, 213, 248, 120, 49, 1, ++ 51, 197, 248, 120, 49, 0, 37, 1, 38, 55, 70, 47, 231, 211, 248, 92, ++ 33, 1, 50, 195, 248, 92, 33, 27, 105, 0, 43, 127, 244, 232, 174, 234, ++ 230, 0, 191, 84, 194, 135, 0, 247, 181, 5, 70, 8, 70, 12, 70, 209, 248, ++ 252, 96, 209, 248, 244, 112, 16, 240, 206, 220, 43, 104, 147, 248, 173, ++ 48, 43, 177, 213, 248, 92, 1, 121, 142, 59, 240, 235, 220, 40, 185, ++ 213, 248, 92, 1, 121, 142, 59, 240, 81, 221, 32, 177, 213, 248, 92, ++ 1, 121, 142, 59, 240, 183, 221, 40, 70, 21, 240, 200, 222, 179, 107, ++ 9, 43, 5, 216, 79, 240, 79, 82, 154, 64, 1, 213, 2, 35, 0, 224, 1, 35, ++ 148, 248, 117, 35, 122, 177, 1, 43, 13, 209, 212, 248, 204, 32, 144, ++ 4, 9, 212, 212, 248, 248, 32, 81, 104, 2, 41, 4, 209, 146, 104, 18, ++ 177, 132, 248, 118, 51, 13, 224, 148, 248, 155, 19, 0, 147, 40, 70, ++ 25, 177, 0, 33, 4, 245, 104, 114, 1, 224, 4, 241, 216, 2, 35, 70, 252, ++ 247, 62, 251, 0, 34, 1, 35, 134, 248, 137, 48, 40, 70, 33, 70, 19, 70, ++ 0, 146, 68, 240, 175, 222, 32, 70, 3, 176, 189, 232, 240, 64, 68, 240, ++ 19, 158, 45, 233, 240, 79, 6, 70, 137, 176, 79, 240, 0, 8, 214, 248, ++ 104, 50, 83, 248, 8, 80, 0, 45, 0, 240, 51, 129, 171, 121, 0, 43, 64, ++ 240, 47, 129, 43, 122, 0, 43, 0, 240, 43, 129, 213, 248, 108, 35, 43, ++ 124, 213, 248, 252, 64, 213, 248, 244, 176, 7, 146, 0, 43, 0, 240, 218, ++ 128, 5, 241, 188, 7, 41, 70, 58, 70, 48, 70, 41, 240, 30, 248, 129, ++ 70, 243, 243, 219, 245, 212, 248, 220, 48, 195, 26, 179, 245, 72, 127, ++ 4, 211, 1, 35, 196, 248, 220, 0, 6, 147, 1, 224, 0, 34, 6, 146, 227, ++ 106, 59, 177, 148, 248, 60, 48, 35, 177, 6, 155, 19, 177, 35, 108, 1, ++ 51, 35, 100, 148, 248, 92, 48, 179, 177, 185, 241, 0, 15, 19, 208, 51, ++ 104, 154, 106, 217, 248, 44, 48, 211, 26, 10, 43, 12, 217, 99, 109, ++ 43, 185, 187, 249, 42, 48, 19, 241, 50, 15, 184, 191, 99, 101, 99, 109, ++ 19, 177, 40, 70, 13, 240, 169, 249, 161, 121, 0, 41, 72, 208, 187, 248, ++ 46, 160, 212, 248, 0, 144, 149, 248, 117, 195, 79, 244, 122, 115, 79, ++ 234, 138, 42, 213, 248, 4, 33, 186, 251, 243, 250, 180, 248, 152, 0, ++ 3, 251, 9, 249, 188, 241, 0, 15, 2, 208, 169, 245, 122, 121, 1, 224, ++ 79, 234, 89, 9, 79, 244, 250, 115, 3, 251, 1, 161, 129, 69, 40, 191, ++ 129, 70, 185, 235, 65, 15, 27, 216, 19, 122, 75, 177, 83, 120, 59, 185, ++ 56, 70, 245, 247, 48, 248, 24, 185, 40, 70, 1, 33, 26, 240, 29, 223, ++ 148, 248, 200, 48, 99, 185, 148, 248, 228, 48, 75, 185, 176, 104, 212, ++ 248, 196, 16, 79, 234, 74, 2, 4, 240, 160, 223, 1, 35, 132, 248, 200, ++ 48, 163, 121, 79, 244, 122, 114, 83, 67, 75, 69, 2, 210, 0, 35, 132, ++ 248, 138, 48, 163, 121, 5, 43, 5, 217, 148, 248, 137, 48, 19, 185, 48, ++ 70, 9, 240, 107, 223, 148, 248, 6, 160, 186, 241, 0, 15, 24, 209, 148, ++ 248, 137, 48, 171, 177, 5, 241, 216, 9, 73, 70, 6, 34, 132, 248, 137, ++ 160, 56, 70, 237, 247, 188, 255, 73, 70, 6, 34, 88, 70, 237, 247, 183, ++ 255, 48, 70, 1, 33, 58, 70, 43, 70, 205, 248, 0, 160, 252, 247, 96, ++ 250, 162, 121, 35, 104, 154, 66, 15, 217, 148, 248, 137, 48, 99, 185, ++ 48, 70, 41, 70, 43, 240, 62, 217, 56, 177, 213, 248, 248, 48, 91, 104, ++ 27, 185, 48, 70, 41, 70, 255, 247, 193, 254, 99, 106, 27, 177, 6, 154, ++ 10, 177, 1, 59, 99, 98, 163, 106, 11, 177, 1, 59, 163, 98, 214, 248, ++ 168, 52, 83, 185, 214, 248, 104, 49, 11, 177, 155, 121, 43, 185, 212, ++ 248, 204, 16, 17, 177, 40, 70, 45, 240, 11, 219, 43, 124, 235, 185, ++ 162, 121, 35, 104, 154, 66, 25, 217, 148, 248, 137, 144, 185, 241, 0, ++ 15, 20, 209, 48, 70, 41, 70, 10, 240, 109, 248, 1, 39, 48, 70, 41, 70, ++ 15, 34, 75, 70, 141, 232, 128, 2, 205, 248, 8, 144, 205, 248, 12, 144, ++ 205, 248, 16, 144, 16, 240, 115, 220, 132, 248, 137, 112, 7, 154, 19, ++ 104, 115, 185, 163, 121, 34, 104, 147, 66, 10, 216, 50, 104, 146, 248, ++ 49, 32, 34, 177, 213, 248, 248, 32, 82, 104, 3, 42, 1, 208, 1, 51, 163, ++ 113, 148, 248, 80, 48, 131, 177, 224, 108, 35, 70, 0, 34, 9, 224, 179, ++ 248, 104, 16, 33, 177, 1, 57, 137, 178, 163, 248, 104, 16, 33, 185, ++ 1, 50, 10, 51, 130, 66, 243, 219, 6, 224, 8, 241, 4, 8, 184, 241, 32, ++ 15, 127, 244, 192, 174, 3, 224, 0, 35, 132, 248, 80, 48, 244, 231, 9, ++ 176, 189, 232, 240, 143, 45, 233, 243, 65, 4, 70, 13, 70, 208, 248, ++ 0, 128, 208, 248, 4, 97, 16, 240, 255, 222, 163, 121, 0, 43, 64, 240, ++ 138, 128, 35, 124, 35, 185, 212, 248, 148, 51, 89, 7, 64, 241, 131, ++ 128, 133, 185, 51, 127, 0, 43, 116, 208, 32, 70, 41, 70, 26, 240, 72, ++ 216, 111, 224, 161, 121, 49, 185, 35, 124, 35, 177, 35, 122, 19, 177, ++ 32, 70, 79, 240, 52, 220, 41, 70, 32, 70, 253, 247, 244, 250, 32, 70, ++ 24, 240, 175, 216, 1, 70, 32, 70, 26, 240, 145, 219, 216, 248, 0, 48, ++ 27, 126, 0, 43, 96, 208, 35, 122, 0, 43, 93, 208, 32, 70, 23, 240, 52, ++ 218, 40, 185, 216, 248, 0, 48, 147, 248, 61, 48, 0, 43, 83, 208, 182, ++ 122, 35, 122, 0, 46, 20, 191, 130, 38, 2, 38, 75, 177, 39, 124, 71, ++ 177, 4, 241, 188, 0, 244, 247, 26, 255, 7, 28, 24, 191, 1, 39, 0, 224, ++ 1, 39, 212, 248, 148, 51, 90, 7, 2, 213, 0, 45, 8, 191, 1, 39, 152, ++ 248, 176, 53, 216, 248, 128, 1, 0, 43, 24, 191, 1, 39, 32, 177, 33, ++ 70, 81, 240, 249, 222, 195, 7, 20, 212, 159, 185, 216, 248, 104, 49, ++ 4, 241, 188, 2, 35, 177, 155, 121, 19, 177, 47, 28, 24, 191, 1, 39, ++ 7, 35, 0, 147, 255, 178, 64, 70, 33, 70, 0, 35, 1, 151, 14, 240, 33, ++ 219, 24, 185, 32, 70, 49, 70, 8, 240, 204, 219, 41, 70, 32, 70, 24, ++ 240, 168, 216, 32, 70, 41, 70, 2, 176, 189, 232, 240, 65, 15, 240, 27, ++ 158, 0, 35, 134, 248, 108, 48, 115, 96, 216, 248, 0, 48, 27, 126, 0, ++ 43, 134, 209, 142, 231, 2, 176, 189, 232, 240, 129, 2, 240, 79, 3, 112, ++ 181, 13, 109, 12, 70, 11, 101, 2, 244, 192, 97, 177, 245, 128, 111, ++ 6, 70, 3, 209, 37, 101, 111, 240, 1, 0, 112, 189, 2, 244, 96, 97, 11, ++ 67, 180, 248, 90, 16, 35, 101, 17, 244, 16, 79, 28, 191, 67, 244, 0, ++ 99, 35, 101, 35, 109, 2, 244, 128, 114, 26, 67, 163, 121, 34, 101, 91, ++ 185, 212, 248, 4, 49, 32, 70, 25, 122, 255, 247, 60, 255, 35, 122, 27, ++ 185, 32, 70, 1, 33, 16, 240, 63, 222, 51, 104, 24, 126, 208, 177, 32, ++ 109, 69, 64, 21, 240, 8, 0, 14, 209, 112, 189, 214, 248, 128, 50, 83, ++ 248, 37, 48, 51, 177, 27, 105, 35, 177, 48, 70, 41, 70, 34, 70, 22, ++ 240, 226, 248, 1, 53, 0, 224, 0, 37, 51, 104, 211, 248, 188, 48, 157, ++ 66, 235, 219, 0, 32, 112, 189, 45, 233, 247, 67, 14, 70, 145, 106, 21, ++ 70, 10, 105, 4, 70, 31, 70, 144, 121, 219, 105, 157, 248, 40, 128, 157, ++ 249, 44, 144, 27, 136, 232, 185, 232, 127, 64, 7, 26, 212, 3, 240, 12, ++ 0, 128, 16, 1, 40, 4, 209, 27, 9, 19, 240, 10, 15, 11, 208, 16, 224, ++ 2, 40, 8, 209, 88, 6, 6, 213, 210, 248, 4, 33, 18, 120, 1, 42, 7, 209, ++ 27, 7, 5, 213, 32, 70, 42, 70, 1, 35, 0, 150, 11, 240, 178, 217, 171, ++ 105, 152, 5, 11, 213, 107, 106, 32, 70, 57, 70, 1, 34, 59, 96, 250, ++ 247, 85, 249, 32, 70, 41, 70, 58, 70, 26, 240, 33, 221, 4, 46, 12, 191, ++ 186, 136, 79, 246, 255, 114, 184, 241, 0, 15, 7, 208, 227, 105, 6, 241, ++ 12, 1, 3, 235, 65, 3, 153, 136, 73, 68, 153, 128, 79, 246, 255, 115, ++ 154, 66, 3, 208, 32, 105, 168, 33, 49, 240, 199, 223, 99, 105, 41, 70, ++ 83, 248, 38, 0, 10, 75, 66, 70, 155, 106, 152, 71, 0, 40, 11, 218, 184, ++ 241, 0, 15, 8, 208, 227, 105, 12, 54, 3, 235, 70, 6, 179, 136, 201, ++ 235, 3, 9, 166, 248, 4, 144, 189, 232, 254, 131, 0, 191, 208, 134, 135, ++ 0, 2, 41, 248, 181, 4, 70, 14, 70, 21, 70, 210, 248, 4, 113, 54, 216, ++ 58, 120, 203, 178, 154, 66, 53, 208, 59, 112, 3, 104, 27, 126, 75, 177, ++ 40, 70, 79, 240, 83, 219, 213, 248, 4, 49, 219, 139, 19, 177, 40, 70, ++ 79, 240, 166, 218, 123, 127, 11, 177, 118, 177, 19, 224, 2, 46, 11, ++ 209, 171, 121, 75, 185, 43, 124, 27, 185, 213, 248, 148, 51, 91, 7, ++ 3, 213, 40, 70, 35, 240, 246, 248, 5, 224, 49, 28, 40, 70, 24, 191, ++ 1, 33, 255, 247, 117, 254, 40, 70, 23, 240, 79, 223, 1, 70, 40, 70, ++ 249, 247, 216, 250, 32, 70, 57, 120, 9, 240, 46, 253, 0, 32, 248, 189, ++ 79, 240, 255, 48, 248, 189, 0, 32, 248, 189, 112, 181, 3, 104, 0, 38, ++ 128, 248, 35, 98, 147, 248, 63, 48, 4, 70, 179, 177, 212, 248, 104, ++ 50, 157, 89, 125, 177, 169, 121, 105, 185, 43, 122, 91, 177, 43, 121, ++ 75, 177, 40, 70, 255, 247, 77, 254, 40, 70, 1, 33, 26, 240, 166, 220, ++ 1, 35, 132, 248, 228, 53, 4, 54, 32, 46, 232, 209, 32, 70, 26, 240, ++ 187, 222, 227, 105, 128, 34, 152, 106, 0, 33, 239, 243, 233, 240, 1, ++ 33, 212, 248, 120, 4, 24, 240, 122, 252, 32, 105, 49, 240, 63, 218, ++ 212, 248, 120, 4, 0, 33, 24, 240, 114, 252, 32, 105, 0, 33, 48, 240, ++ 246, 220, 212, 248, 52, 1, 8, 240, 22, 254, 0, 35, 196, 248, 124, 52, ++ 112, 189, 45, 233, 240, 79, 207, 176, 92, 155, 137, 70, 144, 70, 93, ++ 153, 0, 34, 72, 146, 73, 146, 7, 147, 5, 70, 221, 248, 96, 161, 221, ++ 248, 100, 177, 90, 156, 91, 159, 17, 240, 170, 254, 208, 248, 4, 33, ++ 208, 248, 252, 16, 8, 146, 185, 249, 6, 32, 6, 70, 0, 42, 9, 145, 7, ++ 155, 28, 218, 24, 240, 1, 15, 185, 248, 4, 16, 185, 248, 8, 32, 8, 208, ++ 3, 147, 73, 0, 0, 151, 1, 148, 2, 151, 40, 105, 1, 49, 35, 70, 7, 224, ++ 3, 147, 205, 248, 0, 176, 1, 148, 2, 151, 40, 105, 73, 0, 83, 70, 16, ++ 240, 52, 255, 129, 70, 0, 240, 57, 189, 187, 241, 3, 15, 13, 217, 4, ++ 34, 72, 168, 81, 70, 237, 247, 11, 253, 187, 241, 7, 15, 5, 217, 73, ++ 168, 10, 241, 4, 1, 4, 34, 237, 247, 2, 253, 184, 241, 163, 15, 221, ++ 248, 32, 145, 0, 240, 101, 131, 64, 216, 184, 241, 88, 15, 0, 240, 145, ++ 128, 30, 216, 184, 241, 57, 15, 0, 240, 86, 129, 12, 216, 184, 241, ++ 5, 15, 0, 240, 196, 130, 184, 241, 56, 15, 0, 240, 20, 129, 184, 241, ++ 4, 15, 64, 240, 255, 132, 171, 226, 184, 241, 78, 15, 0, 240, 143, 130, ++ 184, 241, 79, 15, 0, 240, 142, 130, 184, 241, 61, 15, 64, 240, 242, ++ 132, 2, 226, 184, 241, 147, 15, 0, 240, 205, 130, 12, 216, 184, 241, ++ 92, 15, 0, 240, 177, 128, 184, 241, 93, 15, 0, 240, 182, 128, 184, 241, ++ 89, 15, 64, 240, 224, 132, 118, 224, 184, 241, 161, 15, 0, 240, 88, ++ 131, 0, 242, 37, 131, 184, 241, 160, 15, 64, 240, 213, 132, 68, 227, ++ 64, 242, 19, 35, 152, 69, 0, 240, 207, 131, 33, 216, 64, 242, 211, 19, ++ 152, 69, 0, 240, 19, 129, 13, 216, 64, 242, 17, 19, 152, 69, 0, 240, ++ 187, 131, 184, 245, 233, 127, 0, 240, 212, 128, 184, 245, 136, 127, ++ 64, 240, 187, 132, 174, 227, 184, 245, 241, 127, 0, 240, 71, 131, 64, ++ 242, 18, 35, 152, 69, 0, 240, 199, 131, 184, 245, 235, 127, 64, 240, ++ 173, 132, 218, 226, 184, 245, 10, 127, 0, 240, 61, 132, 15, 216, 64, ++ 242, 35, 35, 152, 69, 0, 240, 219, 131, 64, 242, 39, 35, 152, 69, 0, ++ 240, 9, 132, 64, 242, 34, 35, 152, 69, 64, 240, 152, 132, 255, 227, ++ 64, 242, 43, 35, 152, 69, 0, 240, 171, 131, 5, 216, 64, 242, 42, 35, ++ 152, 69, 64, 240, 140, 132, 192, 227, 184, 245, 11, 127, 0, 240, 116, ++ 132, 64, 242, 45, 35, 152, 69, 64, 240, 130, 132, 0, 240, 100, 188, ++ 43, 106, 77, 170, 24, 105, 76, 169, 3, 50, 25, 240, 225, 250, 129, 70, ++ 0, 40, 64, 240, 129, 132, 157, 248, 55, 49, 157, 248, 48, 33, 0, 43, ++ 20, 191, 79, 240, 0, 67, 0, 35, 19, 67, 35, 96, 0, 240, 116, 188, 43, ++ 106, 24, 105, 26, 240, 78, 253, 35, 240, 175, 252, 181, 248, 72, 20, ++ 104, 104, 1, 244, 96, 81, 161, 245, 192, 84, 97, 66, 65, 235, 4, 1, ++ 35, 240, 131, 249, 4, 70, 0, 40, 0, 240, 67, 132, 34, 70, 213, 248, ++ 92, 1, 181, 248, 72, 20, 18, 240, 27, 254, 127, 33, 32, 70, 35, 240, ++ 95, 250, 43, 106, 79, 250, 137, 241, 79, 234, 217, 114, 24, 105, 35, ++ 70, 25, 240, 75, 252, 33, 70, 129, 70, 104, 104, 35, 240, 116, 249, ++ 0, 240, 67, 188, 182, 248, 90, 48, 32, 43, 64, 240, 34, 132, 79, 244, ++ 128, 35, 0, 240, 30, 188, 179, 121, 3, 187, 48, 70, 23, 240, 189, 221, ++ 189, 248, 32, 49, 4, 70, 166, 248, 90, 48, 213, 248, 192, 6, 49, 70, ++ 62, 240, 67, 217, 48, 70, 23, 240, 176, 221, 132, 66, 4, 208, 8, 155, ++ 48, 70, 25, 122, 255, 247, 204, 252, 214, 248, 8, 49, 211, 248, 220, ++ 64, 68, 185, 48, 70, 44, 240, 61, 221, 161, 70, 8, 224, 51, 121, 35, ++ 185, 166, 248, 90, 144, 79, 240, 0, 9, 1, 224, 111, 240, 22, 9, 72, ++ 155, 179, 245, 128, 47, 2, 209, 32, 33, 166, 248, 90, 16, 43, 104, 147, ++ 248, 102, 49, 0, 43, 0, 240, 1, 132, 213, 248, 80, 8, 49, 70, 39, 240, ++ 74, 250, 250, 227, 79, 240, 255, 51, 74, 147, 12, 224, 187, 241, 4, ++ 15, 64, 242, 247, 131, 4, 34, 74, 168, 81, 70, 237, 247, 200, 251, 154, ++ 248, 4, 32, 221, 42, 22, 209, 56, 70, 246, 247, 91, 251, 5, 70, 0, 40, ++ 0, 240, 225, 131, 41, 70, 58, 70, 74, 155, 48, 70, 51, 240, 25, 220, ++ 41, 70, 129, 70, 58, 70, 32, 70, 237, 247, 177, 251, 40, 70, 246, 247, ++ 75, 251, 210, 227, 49, 70, 40, 70, 50, 240, 109, 223, 1, 70, 0, 40, ++ 0, 240, 179, 131, 66, 120, 2, 50, 151, 66, 192, 242, 202, 131, 32, 70, ++ 237, 247, 157, 251, 166, 227, 79, 240, 0, 9, 13, 47, 141, 248, 55, 145, ++ 141, 248, 48, 145, 64, 243, 189, 131, 35, 123, 221, 43, 47, 208, 64, ++ 242, 211, 19, 152, 69, 43, 209, 33, 29, 74, 168, 4, 34, 4, 241, 12, ++ 8, 237, 247, 133, 251, 79, 240, 8, 10, 76, 70, 25, 224, 10, 241, 6, ++ 10, 87, 69, 192, 242, 166, 131, 152, 248, 1, 48, 154, 68, 87, 69, 192, ++ 242, 160, 131, 76, 171, 0, 147, 77, 171, 66, 70, 3, 51, 40, 70, 49, ++ 70, 51, 240, 17, 216, 152, 248, 1, 48, 129, 70, 6, 51, 152, 68, 1, 52, ++ 74, 155, 156, 66, 117, 218, 185, 241, 0, 15, 223, 208, 133, 227, 16, ++ 47, 64, 243, 135, 131, 56, 70, 246, 247, 244, 250, 128, 70, 0, 40, 0, ++ 240, 122, 131, 33, 70, 58, 70, 237, 247, 82, 251, 8, 241, 4, 9, 167, ++ 241, 4, 10, 72, 70, 81, 70, 74, 170, 75, 171, 97, 240, 186, 218, 4, ++ 30, 80, 219, 227, 28, 187, 66, 79, 218, 157, 248, 55, 49, 43, 185, 74, ++ 155, 0, 43, 2, 221, 1, 35, 141, 248, 55, 49, 157, 248, 48, 49, 43, 185, ++ 75, 155, 0, 43, 2, 221, 1, 35, 141, 248, 48, 49, 64, 70, 146, 73, 238, ++ 243, 57, 247, 40, 185, 48, 70, 73, 70, 82, 70, 51, 240, 101, 219, 9, ++ 224, 64, 70, 142, 73, 238, 243, 46, 247, 56, 185, 48, 70, 73, 70, 82, ++ 70, 51, 240, 102, 219, 129, 70, 80, 177, 1, 224, 111, 240, 1, 9, 51, ++ 124, 27, 187, 25, 241, 30, 15, 8, 191, 79, 240, 0, 9, 29, 224, 111, ++ 240, 3, 3, 27, 27, 255, 24, 24, 208, 33, 29, 64, 70, 65, 68, 58, 70, ++ 238, 243, 96, 246, 16, 47, 16, 221, 64, 70, 123, 73, 238, 243, 10, 247, ++ 0, 40, 169, 208, 64, 70, 121, 73, 238, 243, 4, 247, 0, 40, 163, 208, ++ 3, 224, 161, 70, 1, 224, 111, 240, 13, 9, 64, 70, 246, 247, 139, 250, ++ 185, 241, 0, 15, 64, 240, 16, 131, 51, 121, 0, 43, 0, 240, 12, 131, ++ 157, 248, 55, 49, 27, 177, 40, 70, 49, 70, 16, 240, 9, 217, 157, 248, ++ 48, 49, 0, 43, 0, 240, 0, 131, 40, 70, 49, 70, 1, 34, 16, 240, 71, 217, ++ 249, 226, 164, 34, 11, 168, 33, 70, 237, 247, 207, 250, 11, 155, 26, ++ 31, 1, 42, 6, 216, 213, 248, 100, 6, 49, 70, 11, 170, 23, 240, 54, 255, ++ 206, 226, 3, 43, 0, 242, 210, 130, 157, 248, 200, 16, 17, 240, 1, 1, ++ 64, 240, 218, 130, 12, 159, 55, 185, 40, 70, 49, 70, 11, 170, 66, 240, ++ 128, 223, 185, 70, 215, 226, 70, 168, 8, 34, 76, 145, 238, 243, 45, ++ 246, 44, 155, 51, 177, 46, 155, 189, 248, 188, 32, 70, 147, 173, 248, ++ 28, 33, 70, 171, 150, 248, 80, 35, 90, 179, 182, 248, 90, 32, 42, 185, ++ 178, 110, 1, 50, 2, 209, 50, 109, 210, 7, 34, 212, 214, 248, 84, 115, ++ 58, 120, 242, 177, 151, 248, 1, 144, 185, 241, 0, 15, 23, 209, 50, 168, ++ 244, 247, 200, 250, 4, 28, 24, 191, 1, 36, 70, 154, 7, 235, 196, 3, ++ 90, 96, 164, 34, 2, 251, 4, 112, 189, 248, 28, 17, 20, 48, 25, 129, ++ 11, 169, 237, 247, 123, 250, 63, 25, 1, 35, 187, 112, 156, 226, 0, 34, ++ 58, 112, 40, 154, 4, 147, 0, 146, 39, 154, 76, 171, 1, 146, 13, 170, ++ 2, 146, 50, 170, 3, 146, 5, 147, 40, 70, 49, 70, 12, 154, 11, 155, 21, ++ 240, 108, 254, 129, 70, 0, 40, 64, 240, 134, 130, 76, 153, 0, 41, 0, ++ 240, 130, 130, 138, 121, 11, 155, 154, 66, 0, 240, 125, 130, 32, 70, ++ 6, 49, 4, 34, 237, 247, 82, 250, 118, 226, 181, 248, 74, 52, 87, 226, ++ 31, 250, 137, 249, 169, 245, 128, 114, 146, 178, 64, 246, 42, 3, 154, ++ 66, 0, 242, 91, 130, 165, 248, 74, 148, 0, 36, 33, 70, 40, 70, 74, 70, ++ 1, 52, 9, 240, 115, 216, 6, 44, 247, 209, 66, 226, 182, 249, 84, 48, ++ 3, 43, 6, 208, 182, 249, 86, 32, 42, 185, 0, 51, 24, 191, 1, 35, 54, ++ 226, 3, 35, 52, 226, 2, 35, 50, 226, 185, 241, 1, 15, 3, 216, 166, 248, ++ 84, 144, 0, 34, 20, 224, 43, 104, 147, 248, 102, 49, 99, 177, 185, 241, ++ 3, 15, 9, 209, 3, 35, 166, 248, 84, 48, 182, 248, 90, 48, 67, 240, 32, ++ 3, 166, 248, 90, 48, 27, 226, 0, 33, 166, 248, 84, 16, 1, 34, 166, 248, ++ 86, 32, 20, 226, 41, 49, 136, 0, 31, 96, 136, 0, 43, 104, 40, 70, 211, ++ 248, 136, 112, 26, 240, 76, 219, 215, 248, 156, 32, 215, 248, 192, 49, ++ 240, 104, 211, 24, 199, 248, 156, 48, 215, 248, 160, 32, 215, 248, 212, ++ 49, 0, 36, 211, 24, 199, 248, 160, 48, 215, 248, 164, 32, 215, 248, ++ 196, 49, 199, 248, 180, 66, 211, 24, 199, 248, 164, 48, 199, 248, 220, ++ 65, 199, 248, 216, 65, 199, 248, 212, 65, 199, 248, 88, 65, 199, 248, ++ 208, 65, 199, 248, 204, 65, 188, 100, 60, 100, 199, 248, 200, 65, 199, ++ 248, 196, 65, 199, 248, 192, 65, 199, 248, 216, 64, 199, 248, 76, 67, ++ 199, 248, 188, 65, 199, 248, 184, 65, 199, 248, 180, 65, 252, 97, 60, ++ 97, 199, 248, 176, 65, 199, 248, 172, 65, 199, 248, 168, 65, 124, 96, ++ 0, 40, 63, 244, 167, 172, 20, 48, 33, 70, 72, 34, 238, 243, 56, 245, ++ 228, 224, 43, 104, 211, 248, 136, 112, 107, 126, 19, 177, 40, 70, 26, ++ 240, 251, 218, 0, 33, 56, 70, 79, 244, 84, 114, 238, 243, 41, 245, 240, ++ 104, 10, 35, 79, 244, 84, 113, 59, 128, 121, 128, 32, 177, 20, 48, 0, ++ 33, 72, 34, 238, 243, 29, 245, 0, 35, 35, 96, 187, 225, 149, 249, 32, ++ 50, 160, 225, 9, 241, 1, 3, 1, 43, 3, 217, 185, 241, 1, 15, 64, 240, ++ 166, 129, 43, 106, 24, 105, 25, 240, 195, 252, 64, 7, 64, 241, 162, ++ 129, 72, 155, 149, 248, 32, 34, 89, 28, 82, 178, 2, 208, 1, 50, 7, 209, ++ 1, 224, 1, 50, 4, 208, 42, 104, 18, 126, 0, 42, 64, 240, 140, 129, 133, ++ 248, 32, 50, 127, 225, 181, 248, 197, 50, 195, 243, 64, 18, 3, 240, ++ 64, 3, 0, 43, 20, 191, 2, 35, 0, 35, 19, 67, 114, 225, 185, 241, 3, ++ 15, 0, 243, 124, 129, 43, 106, 24, 105, 25, 240, 153, 252, 66, 7, 64, ++ 241, 120, 129, 40, 70, 72, 153, 9, 240, 212, 220, 43, 106, 24, 105, ++ 25, 240, 142, 252, 95, 225, 79, 240, 0, 8, 196, 248, 0, 128, 149, 248, ++ 188, 114, 205, 248, 24, 129, 1, 47, 21, 208, 3, 211, 2, 47, 64, 240, ++ 82, 129, 55, 224, 70, 174, 0, 150, 213, 248, 92, 1, 33, 70, 79, 244, ++ 128, 82, 1, 35, 58, 240, 20, 219, 0, 150, 213, 248, 92, 1, 33, 70, 79, ++ 244, 128, 82, 33, 224, 70, 174, 0, 150, 213, 248, 92, 1, 33, 70, 79, ++ 244, 128, 82, 59, 70, 58, 240, 3, 219, 0, 150, 213, 248, 92, 1, 33, ++ 70, 79, 244, 192, 82, 59, 70, 58, 240, 250, 218, 0, 150, 213, 248, 92, ++ 1, 33, 70, 79, 244, 128, 82, 67, 70, 58, 240, 241, 218, 0, 150, 213, ++ 248, 92, 1, 33, 70, 79, 244, 192, 82, 67, 70, 58, 240, 232, 218, 193, ++ 70, 51, 225, 70, 174, 0, 150, 213, 248, 92, 1, 33, 70, 1, 35, 79, 244, ++ 128, 82, 58, 240, 220, 218, 0, 150, 213, 248, 92, 1, 33, 70, 0, 35, ++ 79, 244, 128, 82, 58, 240, 211, 218, 0, 150, 213, 248, 92, 1, 33, 70, ++ 79, 244, 192, 82, 0, 35, 58, 240, 202, 218, 251, 224, 8, 154, 211, 137, ++ 247, 224, 8, 155, 48, 70, 163, 248, 14, 144, 1, 33, 23, 240, 231, 218, ++ 240, 224, 31, 250, 137, 242, 43, 104, 165, 248, 92, 39, 147, 248, 32, ++ 48, 0, 43, 0, 240, 254, 128, 149, 248, 94, 71, 0, 44, 64, 240, 226, ++ 128, 40, 70, 181, 248, 64, 24, 27, 240, 90, 220, 161, 70, 245, 224, ++ 181, 248, 92, 55, 214, 224, 185, 245, 0, 79, 4, 219, 79, 246, 255, 115, ++ 153, 69, 64, 240, 228, 128, 43, 104, 165, 248, 68, 152, 211, 248, 216, ++ 0, 249, 243, 26, 244, 0, 40, 63, 244, 165, 171, 181, 248, 66, 24, 0, ++ 41, 0, 240, 211, 128, 40, 70, 181, 248, 68, 40, 27, 240, 57, 220, 186, ++ 224, 181, 248, 68, 56, 182, 224, 185, 241, 2, 15, 0, 242, 200, 128, ++ 185, 241, 0, 15, 23, 208, 150, 248, 155, 51, 0, 43, 64, 240, 172, 128, ++ 40, 70, 102, 73, 1, 34, 21, 240, 222, 221, 129, 70, 0, 40, 64, 240, ++ 190, 128, 72, 155, 49, 70, 134, 248, 155, 51, 213, 248, 188, 6, 43, ++ 240, 83, 252, 255, 247, 120, 187, 134, 248, 155, 147, 40, 70, 92, 73, ++ 74, 70, 21, 240, 201, 221, 214, 248, 156, 3, 0, 40, 0, 240, 141, 128, ++ 246, 247, 29, 248, 198, 248, 156, 147, 135, 224, 150, 248, 155, 51, ++ 131, 224, 214, 248, 156, 3, 32, 177, 246, 247, 18, 248, 0, 35, 198, ++ 248, 156, 51, 72, 168, 33, 70, 4, 34, 237, 247, 109, 248, 72, 155, 0, ++ 43, 0, 240, 139, 128, 100, 43, 1, 221, 100, 35, 72, 147, 72, 155, 6, ++ 37, 93, 67, 4, 53, 40, 70, 245, 247, 248, 255, 198, 248, 156, 3, 0, ++ 40, 125, 208, 42, 70, 33, 70, 237, 247, 86, 248, 214, 248, 156, 51, ++ 72, 154, 26, 96, 91, 224, 93, 153, 52, 170, 40, 70, 253, 247, 148, 250, ++ 52, 155, 1, 33, 163, 96, 53, 155, 33, 128, 35, 97, 54, 155, 0, 33, 163, ++ 97, 55, 155, 176, 34, 35, 98, 56, 155, 98, 128, 163, 98, 57, 155, 225, ++ 96, 35, 99, 58, 155, 97, 97, 163, 99, 59, 155, 225, 97, 35, 100, 60, ++ 155, 97, 98, 163, 100, 61, 155, 225, 98, 35, 101, 62, 155, 97, 99, 225, ++ 99, 97, 100, 225, 100, 97, 101, 163, 101, 63, 155, 0, 34, 35, 102, 64, ++ 155, 225, 101, 163, 102, 65, 155, 97, 102, 35, 103, 66, 155, 225, 102, ++ 163, 103, 67, 155, 97, 103, 196, 248, 128, 48, 68, 155, 225, 103, 196, ++ 248, 136, 48, 69, 155, 196, 248, 132, 16, 196, 248, 144, 48, 0, 35, ++ 196, 248, 140, 16, 196, 248, 148, 16, 196, 233, 38, 35, 196, 233, 40, ++ 35, 196, 233, 42, 35, 30, 224, 25, 241, 0, 9, 9, 155, 24, 191, 79, 240, ++ 1, 9, 131, 248, 228, 144, 3, 224, 9, 153, 145, 248, 228, 48, 35, 96, ++ 79, 240, 0, 9, 23, 224, 111, 240, 29, 9, 20, 224, 111, 240, 7, 9, 17, ++ 224, 111, 240, 4, 9, 14, 224, 111, 240, 28, 9, 11, 224, 111, 240, 22, ++ 9, 8, 224, 137, 70, 6, 224, 111, 240, 1, 9, 3, 224, 153, 70, 1, 224, ++ 111, 240, 26, 9, 72, 70, 79, 176, 189, 232, 240, 143, 111, 240, 13, ++ 9, 248, 231, 0, 191, 233, 79, 136, 0, 45, 233, 247, 79, 12, 159, 6, ++ 70, 12, 70, 146, 70, 29, 70, 27, 185, 3, 106, 157, 105, 23, 185, 47, ++ 105, 0, 47, 116, 208, 105, 104, 72, 75, 180, 248, 14, 128, 162, 104, ++ 11, 64, 8, 240, 7, 8, 178, 248, 0, 176, 51, 177, 51, 104, 91, 107, 27, ++ 177, 66, 75, 19, 248, 8, 144, 1, 224, 79, 240, 3, 9, 163, 105, 155, ++ 0, 10, 213, 19, 121, 216, 7, 7, 212, 214, 248, 100, 6, 33, 70, 42, 70, ++ 73, 240, 60, 217, 0, 40, 82, 209, 165, 98, 11, 240, 252, 11, 151, 248, ++ 68, 48, 187, 241, 208, 15, 132, 248, 33, 48, 14, 208, 187, 241, 160, ++ 15, 11, 208, 187, 241, 192, 15, 8, 208, 187, 241, 80, 15, 1, 209, 59, ++ 124, 27, 177, 163, 105, 67, 240, 2, 3, 163, 97, 157, 248, 52, 32, 15, ++ 155, 0, 50, 141, 232, 8, 2, 24, 191, 1, 34, 14, 155, 48, 70, 33, 70, ++ 10, 240, 94, 217, 186, 121, 38, 75, 26, 185, 215, 248, 148, 35, 81, ++ 7, 18, 213, 149, 248, 231, 32, 122, 177, 162, 105, 146, 7, 12, 212, ++ 19, 248, 8, 32, 13, 42, 1, 220, 1, 50, 0, 224, 15, 34, 48, 70, 33, 70, ++ 11, 240, 137, 251, 152, 177, 36, 224, 19, 248, 8, 48, 10, 241, 4, 1, ++ 13, 43, 1, 220, 1, 51, 0, 224, 15, 35, 48, 70, 34, 70, 248, 247, 73, ++ 254, 32, 177, 48, 70, 81, 70, 253, 247, 39, 252, 17, 224, 1, 34, 112, ++ 104, 33, 70, 245, 247, 24, 255, 51, 104, 211, 248, 136, 48, 26, 106, ++ 1, 50, 26, 98, 43, 105, 59, 177, 219, 104, 26, 106, 1, 50, 26, 98, 2, ++ 224, 1, 32, 189, 232, 254, 143, 213, 248, 92, 49, 0, 32, 1, 51, 197, ++ 248, 92, 49, 246, 231, 0, 191, 64, 0, 1, 0, 138, 182, 135, 0, 72, 194, ++ 135, 0, 127, 181, 20, 70, 146, 104, 6, 70, 19, 121, 13, 70, 219, 7, ++ 11, 212, 4, 50, 39, 240, 231, 254, 3, 70, 56, 177, 144, 248, 36, 32, ++ 18, 240, 2, 2, 8, 191, 19, 70, 0, 224, 0, 35, 213, 248, 204, 32, 0, ++ 149, 18, 244, 0, 82, 12, 191, 17, 70, 12, 33, 162, 127, 3, 145, 34, ++ 240, 15, 2, 66, 240, 3, 2, 162, 119, 0, 34, 1, 146, 2, 146, 48, 70, ++ 33, 70, 214, 248, 164, 37, 255, 247, 45, 255, 0, 40, 12, 191, 79, 240, ++ 255, 48, 0, 32, 4, 176, 112, 189, 248, 181, 6, 70, 8, 70, 12, 70, 23, ++ 70, 84, 240, 73, 219, 227, 121, 5, 70, 2, 43, 19, 209, 97, 105, 137, ++ 177, 208, 248, 204, 48, 154, 4, 6, 213, 59, 104, 79, 244, 250, 98, 48, ++ 70, 90, 67, 248, 247, 202, 253, 48, 70, 41, 70, 98, 105, 255, 247, 175, ++ 255, 0, 35, 99, 97, 248, 189, 45, 233, 240, 79, 0, 43, 179, 176, 7, ++ 147, 12, 191, 4, 35, 10, 35, 9, 147, 7, 155, 21, 105, 13, 241, 40, 9, ++ 24, 191, 32, 35, 4, 70, 20, 175, 136, 70, 147, 70, 0, 33, 40, 34, 72, ++ 70, 6, 147, 213, 248, 248, 96, 13, 241, 176, 10, 238, 243, 57, 242, ++ 0, 33, 40, 34, 56, 70, 238, 243, 52, 242, 0, 33, 12, 34, 80, 70, 238, ++ 243, 47, 242, 51, 107, 32, 70, 141, 232, 8, 4, 41, 70, 6, 154, 243, ++ 106, 205, 248, 176, 144, 45, 151, 7, 240, 245, 218, 0, 40, 64, 240, ++ 248, 128, 184, 248, 6, 48, 216, 7, 21, 213, 33, 106, 75, 125, 147, 177, ++ 10, 109, 11, 168, 84, 49, 10, 146, 236, 247, 147, 254, 213, 248, 204, ++ 48, 153, 4, 5, 213, 212, 248, 80, 1, 41, 70, 74, 70, 77, 240, 225, 216, ++ 0, 35, 20, 147, 8, 224, 20, 171, 0, 147, 32, 70, 41, 70, 8, 241, 56, ++ 2, 10, 171, 23, 240, 109, 218, 243, 106, 131, 177, 38, 168, 0, 33, 24, ++ 34, 238, 243, 246, 241, 243, 106, 43, 148, 38, 147, 51, 107, 39, 147, ++ 103, 75, 41, 147, 103, 75, 40, 147, 103, 75, 42, 147, 38, 171, 30, 175, ++ 0, 33, 32, 34, 56, 70, 8, 147, 238, 243, 227, 241, 10, 171, 0, 33, 8, ++ 34, 32, 147, 47, 168, 20, 171, 33, 147, 205, 248, 120, 176, 205, 248, ++ 124, 128, 238, 243, 214, 241, 35, 104, 41, 70, 147, 248, 79, 32, 50, ++ 171, 18, 240, 3, 2, 24, 191, 219, 248, 4, 32, 212, 248, 124, 6, 24, ++ 191, 194, 243, 0, 66, 3, 248, 12, 45, 0, 147, 6, 154, 8, 155, 48, 151, ++ 62, 240, 15, 222, 9, 155, 6, 153, 0, 235, 3, 10, 49, 171, 2, 147, 32, ++ 70, 66, 70, 5, 241, 194, 3, 141, 232, 0, 5, 20, 240, 223, 219, 7, 70, ++ 48, 185, 32, 70, 57, 70, 181, 248, 26, 33, 42, 240, 51, 217, 128, 224, ++ 32, 70, 41, 70, 66, 70, 221, 248, 196, 144, 14, 240, 41, 222, 169, 248, ++ 0, 0, 115, 140, 169, 248, 2, 48, 49, 155, 4, 51, 49, 147, 7, 155, 19, ++ 185, 170, 241, 4, 10, 19, 224, 6, 241, 36, 9, 72, 70, 243, 247, 75, ++ 254, 16, 185, 49, 152, 73, 70, 2, 224, 49, 152, 5, 241, 216, 1, 6, 34, ++ 236, 247, 5, 254, 49, 155, 170, 241, 10, 10, 6, 51, 49, 147, 47, 171, ++ 0, 147, 49, 155, 212, 248, 124, 6, 1, 147, 41, 70, 6, 154, 8, 155, 205, ++ 248, 8, 160, 62, 240, 49, 221, 129, 70, 40, 177, 96, 104, 57, 70, 1, ++ 34, 245, 247, 188, 253, 66, 224, 49, 155, 0, 144, 1, 144, 2, 144, 3, ++ 147, 32, 70, 41, 70, 87, 34, 75, 70, 205, 248, 16, 160, 15, 240, 236, ++ 218, 112, 107, 24, 177, 245, 247, 119, 253, 198, 248, 52, 144, 7, 155, ++ 35, 177, 49, 155, 10, 241, 6, 10, 6, 59, 49, 147, 49, 155, 10, 241, ++ 4, 10, 4, 59, 49, 147, 7, 155, 80, 70, 134, 248, 60, 48, 245, 247, 96, ++ 253, 112, 99, 8, 185, 176, 99, 5, 224, 49, 153, 82, 70, 236, 247, 190, ++ 253, 198, 248, 56, 160, 184, 248, 98, 48, 0, 149, 195, 243, 64, 19, ++ 1, 147, 0, 35, 2, 147, 3, 147, 57, 70, 32, 70, 212, 248, 164, 37, 91, ++ 70, 255, 247, 220, 253, 0, 40, 8, 191, 0, 39, 0, 224, 0, 39, 56, 70, ++ 51, 176, 189, 232, 240, 143, 0, 191, 9, 205, 129, 0, 25, 205, 129, 0, ++ 57, 205, 129, 0, 45, 233, 240, 79, 149, 176, 4, 70, 6, 145, 7, 146, ++ 221, 248, 128, 128, 33, 158, 5, 104, 154, 70, 0, 43, 0, 240, 223, 128, ++ 184, 241, 0, 15, 28, 209, 30, 154, 1, 42, 27, 209, 31, 154, 147, 30, ++ 1, 43, 23, 216, 3, 42, 21, 209, 0, 46, 64, 240, 213, 128, 131, 110, ++ 95, 28, 5, 208, 0, 235, 131, 3, 222, 110, 0, 46, 64, 240, 204, 128, ++ 40, 70, 0, 33, 180, 248, 26, 33, 14, 240, 202, 252, 0, 39, 191, 224, ++ 0, 38, 0, 224, 70, 70, 79, 240, 176, 11, 6, 39, 43, 104, 147, 248, 102, ++ 49, 99, 177, 30, 155, 3, 43, 9, 209, 205, 248, 0, 128, 213, 248, 80, ++ 8, 33, 70, 82, 70, 31, 155, 38, 240, 158, 253, 32, 224, 9, 171, 24, ++ 70, 0, 33, 32, 34, 5, 147, 238, 243, 208, 240, 30, 154, 13, 241, 68, ++ 9, 9, 146, 31, 154, 0, 33, 10, 146, 34, 154, 72, 70, 12, 146, 8, 34, ++ 205, 248, 44, 160, 238, 243, 193, 240, 5, 155, 205, 248, 0, 144, 18, ++ 147, 213, 248, 124, 6, 33, 70, 176, 34, 0, 35, 62, 240, 6, 221, 7, 155, ++ 0, 235, 7, 9, 141, 232, 8, 2, 19, 171, 2, 147, 40, 70, 89, 70, 6, 154, ++ 4, 241, 194, 3, 20, 240, 214, 218, 7, 70, 0, 40, 118, 208, 43, 104, ++ 147, 248, 102, 49, 51, 177, 30, 154, 3, 42, 5, 209, 19, 155, 3, 235, ++ 9, 12, 3, 224, 156, 70, 1, 224, 79, 240, 0, 12, 158, 177, 0, 35, 0, ++ 147, 1, 147, 50, 70, 19, 155, 40, 70, 33, 70, 205, 248, 20, 192, 66, ++ 240, 200, 216, 150, 249, 14, 48, 19, 154, 221, 248, 20, 192, 210, 24, ++ 19, 146, 195, 235, 9, 9, 221, 248, 76, 176, 30, 155, 171, 248, 0, 48, ++ 31, 154, 171, 248, 4, 128, 171, 248, 2, 32, 42, 104, 11, 241, 6, 3, ++ 146, 248, 102, 33, 19, 147, 162, 177, 30, 154, 3, 42, 17, 209, 156, ++ 69, 44, 191, 195, 235, 12, 2, 0, 34, 213, 248, 80, 8, 33, 70, 1, 147, ++ 2, 146, 31, 155, 82, 70, 205, 248, 0, 128, 38, 240, 59, 253, 19, 144, ++ 20, 224, 17, 170, 141, 232, 12, 0, 169, 241, 6, 3, 2, 147, 213, 248, ++ 124, 6, 33, 70, 176, 34, 0, 35, 62, 240, 12, 220, 184, 241, 0, 15, 4, ++ 209, 189, 248, 52, 48, 11, 177, 171, 248, 4, 48, 163, 121, 19, 177, ++ 227, 104, 218, 104, 1, 224, 213, 248, 164, 37, 157, 248, 140, 48, 57, ++ 70, 1, 147, 0, 35, 3, 147, 40, 70, 83, 70, 0, 148, 2, 150, 255, 247, ++ 227, 252, 0, 40, 8, 191, 0, 39, 0, 224, 31, 70, 56, 70, 21, 176, 189, ++ 232, 240, 143, 150, 249, 14, 112, 68, 242, 176, 11, 6, 55, 59, 231, ++ 45, 233, 240, 79, 3, 104, 135, 176, 147, 248, 63, 48, 4, 70, 198, 104, ++ 19, 177, 176, 248, 70, 84, 2, 224, 9, 240, 194, 216, 5, 70, 35, 106, ++ 212, 248, 56, 35, 0, 33, 32, 70, 3, 241, 28, 10, 179, 248, 8, 144, 211, ++ 248, 0, 128, 2, 241, 56, 11, 20, 240, 132, 219, 5, 244, 96, 83, 179, ++ 245, 32, 95, 8, 208, 179, 245, 192, 95, 7, 208, 179, 245, 128, 95, 20, ++ 191, 10, 35, 20, 35, 2, 224, 160, 35, 0, 224, 40, 35, 0, 39, 255, 34, ++ 3, 147, 212, 248, 116, 52, 1, 146, 2, 144, 0, 151, 27, 121, 88, 70, ++ 4, 147, 81, 70, 74, 70, 67, 70, 35, 240, 159, 249, 59, 70, 41, 70, 58, ++ 70, 32, 105, 16, 240, 227, 250, 32, 70, 10, 240, 210, 218, 86, 33, 32, ++ 105, 48, 240, 128, 216, 212, 248, 180, 49, 64, 0, 187, 66, 196, 248, ++ 252, 2, 6, 218, 32, 105, 178, 33, 48, 240, 117, 216, 64, 0, 196, 248, ++ 0, 3, 32, 70, 251, 247, 196, 255, 148, 248, 16, 50, 51, 185, 32, 105, ++ 76, 33, 48, 240, 104, 216, 192, 9, 132, 248, 16, 2, 32, 70, 23, 240, ++ 152, 218, 79, 240, 0, 8, 32, 70, 65, 240, 111, 219, 71, 70, 12, 224, ++ 212, 248, 168, 50, 67, 68, 219, 106, 35, 177, 212, 248, 172, 34, 82, ++ 248, 39, 0, 152, 71, 1, 55, 8, 241, 56, 8, 35, 104, 147, 248, 184, 48, ++ 159, 66, 237, 219, 0, 39, 212, 248, 104, 50, 83, 248, 7, 128, 184, 241, ++ 0, 15, 5, 208, 64, 70, 24, 240, 152, 223, 64, 70, 24, 240, 117, 221, ++ 4, 55, 32, 47, 239, 209, 32, 70, 41, 70, 7, 240, 174, 216, 116, 33, ++ 32, 70, 180, 248, 88, 35, 26, 240, 142, 223, 148, 248, 21, 34, 66, 242, ++ 16, 115, 0, 42, 12, 191, 26, 70, 79, 244, 188, 98, 130, 33, 32, 70, ++ 26, 240, 129, 223, 35, 106, 148, 248, 21, 18, 24, 105, 25, 240, 161, ++ 249, 32, 70, 41, 240, 183, 253, 35, 104, 65, 242, 107, 1, 211, 248, ++ 216, 48, 26, 107, 138, 66, 23, 209, 219, 107, 68, 242, 49, 50, 147, ++ 66, 35, 208, 68, 242, 96, 50, 147, 66, 28, 208, 74, 246, 196, 18, 147, ++ 66, 24, 208, 74, 246, 6, 34, 147, 66, 20, 208, 68, 242, 82, 50, 147, ++ 66, 20, 191, 7, 34, 1, 34, 14, 224, 65, 242, 228, 65, 138, 66, 19, 209, ++ 155, 106, 64, 242, 39, 82, 147, 66, 7, 208, 64, 242, 198, 82, 147, 66, ++ 10, 209, 2, 224, 1, 34, 0, 37, 1, 224, 5, 34, 1, 37, 32, 70, 106, 73, ++ 21, 240, 251, 216, 0, 224, 0, 37, 105, 73, 42, 70, 32, 70, 21, 240, ++ 244, 216, 212, 248, 56, 1, 32, 240, 212, 216, 35, 104, 147, 248, 79, ++ 32, 145, 7, 8, 208, 212, 248, 116, 36, 179, 248, 204, 48, 32, 70, 83, ++ 133, 1, 33, 41, 240, 108, 249, 32, 70, 252, 247, 59, 250, 35, 104, 91, ++ 107, 203, 177, 182, 248, 136, 54, 0, 37, 155, 178, 67, 240, 4, 3, 166, ++ 248, 136, 54, 212, 248, 104, 50, 89, 89, 81, 177, 35, 104, 91, 107, ++ 59, 177, 209, 248, 204, 32, 18, 240, 2, 2, 2, 209, 32, 70, 19, 240, ++ 193, 223, 4, 53, 32, 45, 237, 209, 32, 70, 13, 240, 125, 217, 212, 248, ++ 176, 17, 97, 185, 32, 70, 23, 240, 117, 216, 5, 4, 196, 248, 176, 81, ++ 32, 70, 2, 33, 23, 240, 110, 216, 40, 67, 196, 248, 176, 1, 15, 33, ++ 212, 248, 52, 1, 7, 240, 186, 254, 32, 70, 19, 240, 213, 223, 32, 70, ++ 6, 240, 88, 219, 180, 248, 36, 21, 32, 70, 252, 247, 102, 251, 32, 70, ++ 252, 247, 149, 253, 227, 104, 59, 74, 0, 38, 132, 248, 52, 96, 37, 70, ++ 195, 248, 220, 35, 32, 70, 6, 245, 64, 113, 23, 240, 75, 216, 181, 248, ++ 58, 50, 26, 7, 6, 209, 35, 240, 15, 3, 0, 240, 15, 2, 19, 67, 165, 248, ++ 58, 50, 181, 248, 58, 50, 19, 240, 240, 15, 6, 209, 35, 240, 240, 3, ++ 0, 240, 240, 2, 19, 67, 165, 248, 58, 50, 181, 248, 58, 50, 19, 244, ++ 112, 111, 6, 209, 35, 244, 112, 99, 0, 244, 112, 98, 19, 67, 165, 248, ++ 58, 50, 181, 248, 58, 50, 26, 11, 8, 209, 27, 5, 32, 244, 126, 96, 27, ++ 13, 32, 240, 31, 0, 24, 67, 165, 248, 58, 2, 2, 54, 2, 53, 8, 46, 198, ++ 209, 35, 104, 32, 70, 147, 249, 82, 16, 8, 240, 69, 222, 148, 248, 116, ++ 50, 3, 240, 2, 3, 132, 248, 116, 50, 35, 104, 26, 126, 98, 177, 147, ++ 248, 47, 48, 51, 177, 0, 35, 132, 248, 114, 50, 212, 248, 8, 5, 36, ++ 240, 64, 217, 32, 70, 12, 240, 199, 221, 0, 37, 212, 248, 104, 50, 88, ++ 89, 24, 177, 131, 121, 11, 185, 41, 240, 60, 219, 4, 53, 32, 45, 244, ++ 209, 212, 248, 104, 1, 4, 33, 83, 240, 238, 222, 0, 35, 132, 248, 42, ++ 56, 7, 176, 189, 232, 240, 143, 154, 51, 4, 0, 244, 75, 136, 0, 128, ++ 150, 152, 0, 45, 233, 240, 79, 139, 70, 17, 136, 139, 176, 20, 70, 219, ++ 248, 0, 32, 5, 145, 1, 240, 252, 8, 20, 153, 9, 146, 219, 138, 14, 104, ++ 5, 153, 19, 244, 64, 79, 193, 243, 129, 1, 12, 191, 0, 35, 1, 35, 1, ++ 41, 7, 70, 21, 157, 6, 147, 7, 145, 2, 221, 2, 41, 99, 209, 76, 224, ++ 5, 154, 18, 244, 64, 127, 7, 208, 184, 241, 80, 15, 0, 240, 106, 129, ++ 184, 241, 164, 15, 87, 209, 51, 224, 184, 241, 132, 15, 48, 208, 13, ++ 216, 184, 241, 16, 15, 87, 208, 3, 216, 184, 241, 0, 15, 83, 208, 89, ++ 225, 184, 241, 32, 15, 79, 208, 184, 241, 48, 15, 8, 224, 184, 241, ++ 164, 15, 30, 208, 7, 216, 184, 241, 148, 15, 26, 208, 184, 241, 160, ++ 15, 64, 240, 73, 129, 64, 224, 184, 241, 192, 15, 61, 208, 184, 241, ++ 208, 15, 64, 240, 65, 129, 32, 70, 41, 70, 9, 240, 107, 216, 0, 40, ++ 64, 240, 58, 129, 56, 70, 33, 70, 42, 70, 9, 240, 77, 216, 0, 40, 64, ++ 240, 50, 129, 9, 155, 99, 187, 9, 171, 0, 147, 56, 70, 33, 29, 4, 241, ++ 10, 2, 6, 155, 39, 240, 67, 250, 6, 70, 33, 224, 5, 155, 19, 244, 64, ++ 117, 0, 240, 39, 129, 181, 245, 64, 127, 25, 209, 226, 185, 6, 155, ++ 33, 29, 4, 241, 10, 2, 205, 248, 0, 176, 39, 240, 48, 250, 219, 248, ++ 0, 48, 6, 70, 9, 147, 15, 224, 59, 104, 1, 37, 211, 248, 136, 48, 218, ++ 109, 1, 50, 218, 101, 13, 225, 79, 240, 2, 10, 6, 37, 6, 224, 79, 240, ++ 3, 10, 7, 37, 2, 224, 79, 240, 4, 10, 1, 37, 9, 153, 57, 177, 70, 185, ++ 56, 70, 4, 241, 10, 2, 6, 155, 39, 240, 13, 250, 6, 70, 0, 46, 71, 208, ++ 9, 152, 130, 121, 18, 187, 3, 124, 27, 187, 2, 122, 10, 179, 184, 241, ++ 148, 15, 32, 208, 184, 241, 132, 15, 29, 208, 184, 241, 208, 15, 29, ++ 209, 176, 248, 190, 48, 97, 138, 34, 138, 89, 64, 176, 248, 188, 48, ++ 90, 64, 10, 67, 176, 248, 192, 48, 161, 138, 75, 64, 19, 67, 31, 250, ++ 131, 249, 217, 241, 1, 9, 56, 191, 79, 240, 0, 9, 8, 224, 79, 240, 0, ++ 9, 5, 224, 145, 70, 3, 224, 79, 240, 1, 9, 0, 224, 153, 70, 208, 248, ++ 204, 48, 19, 244, 0, 3, 22, 208, 184, 241, 148, 15, 21, 208, 184, 241, ++ 132, 15, 18, 208, 184, 241, 208, 15, 17, 209, 188, 48, 6, 34, 4, 241, ++ 16, 1, 236, 247, 232, 249, 208, 241, 1, 0, 56, 191, 0, 32, 7, 224, 48, ++ 70, 177, 70, 4, 224, 24, 70, 2, 224, 1, 32, 0, 224, 0, 32, 186, 241, ++ 4, 15, 8, 209, 0, 46, 0, 240, 147, 128, 214, 248, 164, 49, 217, 7, 0, ++ 241, 149, 128, 140, 224, 126, 177, 150, 248, 36, 48, 19, 240, 2, 2, ++ 64, 240, 141, 128, 0, 40, 64, 240, 140, 128, 185, 241, 0, 15, 64, 240, ++ 138, 128, 218, 7, 4, 213, 95, 224, 184, 241, 192, 15, 0, 240, 134, 128, ++ 35, 121, 216, 7, 116, 212, 30, 177, 150, 248, 36, 48, 89, 7, 111, 212, ++ 59, 106, 6, 153, 91, 104, 153, 66, 106, 209, 5, 154, 2, 244, 64, 115, ++ 179, 245, 128, 127, 2, 209, 4, 241, 4, 8, 12, 224, 179, 245, 0, 127, ++ 2, 209, 4, 241, 10, 8, 6, 224, 7, 155, 1, 43, 20, 191, 4, 241, 16, 8, ++ 79, 240, 0, 8, 9, 155, 99, 185, 6, 155, 56, 70, 33, 29, 4, 241, 10, ++ 2, 205, 248, 0, 176, 39, 240, 109, 249, 219, 248, 0, 48, 6, 70, 9, 147, ++ 9, 155, 59, 177, 3, 241, 194, 2, 184, 241, 0, 15, 11, 209, 3, 241, 188, ++ 8, 8, 224, 34, 29, 184, 241, 0, 15, 1, 209, 4, 241, 10, 8, 215, 248, ++ 108, 50, 9, 147, 14, 185, 59, 106, 158, 105, 10, 52, 1, 146, 9, 153, ++ 50, 70, 35, 70, 56, 70, 205, 248, 0, 128, 2, 149, 23, 240, 184, 222, ++ 0, 34, 56, 70, 9, 153, 35, 70, 0, 149, 1, 146, 42, 240, 68, 218, 27, ++ 224, 186, 241, 3, 15, 37, 209, 34, 121, 210, 7, 21, 212, 27, 7, 19, ++ 212, 59, 106, 6, 153, 91, 104, 153, 66, 14, 209, 49, 105, 56, 70, 1, ++ 241, 188, 3, 0, 147, 1, 241, 194, 3, 1, 147, 50, 70, 4, 241, 10, 3, ++ 9, 145, 2, 149, 23, 240, 235, 222, 59, 104, 211, 248, 136, 48, 26, 111, ++ 1, 50, 26, 103, 6, 224, 0, 37, 4, 224, 21, 70, 2, 224, 5, 70, 0, 224, ++ 77, 70, 20, 154, 40, 70, 22, 96, 11, 176, 189, 232, 240, 143, 45, 233, ++ 240, 71, 4, 70, 164, 176, 144, 70, 154, 70, 13, 70, 0, 41, 109, 208, ++ 209, 248, 88, 51, 0, 43, 105, 208, 5, 175, 15, 174, 51, 70, 58, 70, ++ 13, 241, 100, 9, 20, 240, 38, 217, 0, 33, 32, 34, 72, 70, 237, 243, ++ 167, 244, 35, 106, 0, 33, 101, 51, 8, 34, 33, 168, 25, 147, 205, 248, ++ 104, 128, 141, 248, 108, 160, 28, 151, 29, 150, 237, 243, 153, 244, ++ 35, 104, 205, 248, 136, 144, 147, 248, 79, 48, 19, 240, 3, 3, 7, 208, ++ 213, 248, 204, 48, 3, 244, 128, 83, 211, 241, 1, 3, 56, 191, 0, 35, ++ 36, 175, 7, 248, 12, 61, 41, 70, 64, 34, 0, 35, 212, 248, 124, 6, 0, ++ 151, 62, 240, 206, 216, 45, 155, 1, 144, 0, 147, 35, 171, 2, 147, 128, ++ 70, 64, 33, 32, 70, 44, 154, 5, 241, 194, 3, 19, 240, 159, 222, 6, 70, ++ 32, 179, 35, 155, 212, 248, 124, 6, 1, 147, 41, 70, 64, 34, 0, 35, 0, ++ 151, 205, 248, 8, 128, 62, 240, 33, 216, 40, 177, 96, 104, 49, 70, 1, ++ 34, 245, 247, 173, 248, 17, 224, 213, 248, 204, 48, 19, 244, 0, 83, ++ 6, 208, 212, 248, 80, 1, 41, 70, 50, 70, 76, 240, 185, 221, 5, 224, ++ 32, 70, 49, 70, 212, 248, 164, 37, 23, 240, 184, 222, 36, 176, 189, ++ 232, 240, 135, 45, 233, 240, 79, 143, 176, 139, 70, 25, 153, 144, 70, ++ 31, 70, 24, 158, 4, 70, 66, 240, 172, 222, 26, 153, 9, 144, 25, 152, ++ 34, 240, 151, 252, 0, 46, 7, 144, 64, 243, 16, 129, 1, 46, 61, 120, ++ 20, 191, 151, 248, 1, 160, 79, 240, 0, 10, 187, 241, 0, 15, 2, 208, ++ 219, 248, 16, 144, 12, 224, 32, 70, 8, 241, 16, 1, 16, 240, 73, 250, ++ 129, 70, 40, 185, 32, 70, 8, 241, 4, 1, 16, 240, 24, 250, 129, 70, 4, ++ 45, 6, 208, 1, 216, 1, 45, 2, 224, 10, 45, 1, 208, 127, 45, 48, 209, ++ 8, 241, 10, 3, 8, 147, 0, 35, 0, 147, 1, 147, 2, 147, 59, 34, 32, 70, ++ 73, 70, 8, 155, 3, 151, 4, 150, 14, 240, 143, 221, 4, 45, 5, 209, 170, ++ 241, 32, 3, 1, 43, 1, 216, 7, 45, 27, 224, 13, 241, 40, 12, 99, 70, ++ 32, 70, 25, 153, 26, 154, 205, 248, 24, 192, 249, 247, 103, 255, 0, ++ 35, 221, 248, 24, 192, 0, 147, 1, 147, 2, 147, 32, 70, 73, 70, 75, 34, ++ 8, 155, 3, 151, 4, 150, 205, 248, 20, 192, 14, 240, 127, 221, 7, 45, ++ 104, 208, 14, 216, 4, 45, 115, 208, 4, 216, 221, 177, 1, 45, 64, 240, ++ 151, 128, 131, 224, 5, 45, 0, 240, 180, 128, 6, 45, 64, 240, 144, 128, ++ 74, 224, 11, 45, 6, 216, 10, 45, 128, 240, 171, 128, 8, 45, 64, 240, ++ 135, 128, 105, 224, 21, 45, 0, 240, 164, 128, 127, 45, 48, 208, 17, ++ 45, 126, 209, 20, 224, 35, 104, 147, 248, 173, 48, 0, 43, 0, 240, 153, ++ 128, 1, 46, 0, 240, 138, 128, 9, 155, 212, 248, 116, 1, 0, 147, 7, 155, ++ 65, 70, 1, 147, 58, 70, 51, 70, 27, 240, 128, 217, 137, 224, 185, 241, ++ 0, 15, 4, 208, 35, 104, 91, 107, 0, 43, 0, 240, 130, 128, 66, 46, 115, ++ 221, 35, 104, 147, 248, 69, 48, 0, 43, 122, 208, 72, 70, 81, 70, 212, ++ 248, 100, 33, 67, 70, 0, 151, 1, 150, 53, 240, 157, 221, 112, 224, 25, ++ 155, 32, 70, 1, 147, 7, 155, 73, 70, 2, 147, 66, 70, 59, 70, 0, 150, ++ 247, 247, 143, 252, 100, 224, 185, 241, 0, 15, 97, 208, 15, 46, 83, ++ 221, 212, 248, 192, 6, 73, 70, 66, 70, 59, 70, 0, 150, 60, 240, 237, ++ 219, 86, 224, 35, 104, 147, 248, 79, 48, 155, 7, 81, 208, 32, 70, 81, ++ 70, 90, 70, 67, 70, 0, 151, 1, 150, 7, 240, 111, 222, 72, 224, 25, 155, ++ 32, 70, 1, 147, 7, 155, 73, 70, 2, 147, 66, 70, 59, 70, 0, 150, 7, 240, ++ 195, 222, 60, 224, 212, 248, 100, 6, 89, 70, 82, 70, 67, 70, 0, 151, ++ 1, 150, 71, 240, 177, 223, 50, 224, 35, 104, 147, 248, 176, 48, 0, 43, ++ 45, 208, 186, 241, 4, 15, 42, 209, 2, 46, 40, 221, 212, 248, 144, 1, ++ 73, 70, 186, 28, 179, 30, 27, 240, 75, 220, 32, 224, 5, 240, 127, 3, ++ 3, 43, 7, 209, 32, 70, 89, 70, 66, 70, 59, 70, 0, 150, 30, 240, 73, ++ 216, 20, 224, 40, 6, 18, 212, 32, 70, 65, 70, 58, 70, 51, 70, 23, 240, ++ 238, 216, 11, 224, 32, 70, 65, 70, 58, 70, 51, 70, 23, 240, 231, 216, ++ 35, 104, 211, 248, 136, 48, 26, 111, 1, 50, 26, 103, 0, 32, 15, 176, ++ 189, 232, 240, 143, 45, 233, 240, 67, 144, 248, 144, 55, 135, 176, 4, ++ 70, 43, 177, 0, 35, 128, 248, 144, 55, 79, 240, 1, 8, 0, 224, 152, 70, ++ 35, 104, 26, 126, 50, 185, 184, 241, 0, 15, 0, 240, 107, 130, 32, 70, ++ 2, 33, 101, 226, 32, 105, 61, 240, 168, 221, 24, 177, 160, 104, 246, ++ 247, 109, 252, 87, 226, 34, 105, 210, 248, 68, 49, 131, 177, 33, 104, ++ 7, 43, 136, 191, 0, 35, 209, 248, 136, 16, 202, 51, 1, 235, 131, 3, ++ 89, 104, 1, 49, 89, 96, 194, 248, 68, 1, 32, 70, 19, 240, 134, 220, ++ 35, 105, 211, 248, 136, 48, 179, 248, 208, 52, 93, 6, 2, 213, 32, 70, ++ 19, 240, 124, 220, 32, 70, 13, 240, 183, 217, 35, 106, 32, 70, 31, 105, ++ 212, 248, 108, 50, 211, 248, 0, 33, 157, 121, 22, 124, 13, 240, 238, ++ 223, 3, 28, 24, 191, 1, 35, 56, 70, 113, 178, 42, 70, 25, 240, 94, 248, ++ 148, 248, 116, 54, 171, 177, 35, 105, 211, 248, 136, 48, 211, 248, 36, ++ 81, 21, 240, 64, 5, 13, 209, 32, 70, 25, 240, 240, 219, 35, 106, 132, ++ 248, 116, 86, 24, 105, 41, 70, 42, 70, 24, 240, 146, 254, 32, 70, 19, ++ 240, 155, 219, 35, 104, 32, 70, 154, 106, 1, 50, 154, 98, 13, 240, 198, ++ 223, 24, 185, 212, 248, 116, 52, 131, 248, 41, 1, 32, 70, 42, 240, 71, ++ 253, 35, 106, 24, 105, 24, 240, 191, 249, 1, 70, 32, 70, 66, 240, 144, ++ 220, 35, 106, 24, 105, 24, 240, 199, 249, 1, 70, 32, 70, 20, 240, 42, ++ 254, 35, 104, 147, 249, 62, 48, 123, 177, 212, 248, 36, 1, 3, 169, 0, ++ 34, 84, 240, 238, 217, 1, 224, 0, 35, 195, 97, 212, 248, 36, 1, 3, 169, ++ 38, 240, 142, 254, 0, 40, 246, 209, 148, 248, 216, 49, 75, 177, 32, ++ 70, 8, 240, 118, 220, 40, 177, 148, 248, 232, 49, 19, 177, 1, 59, 132, ++ 248, 232, 49, 32, 70, 22, 240, 242, 217, 32, 70, 9, 240, 57, 220, 32, ++ 70, 22, 240, 70, 218, 148, 248, 216, 49, 19, 177, 32, 70, 20, 240, 136, ++ 220, 35, 104, 221, 110, 0, 45, 64, 240, 182, 129, 32, 70, 16, 240, 157, ++ 253, 32, 70, 47, 240, 237, 223, 35, 104, 147, 248, 47, 32, 194, 177, ++ 147, 248, 48, 48, 171, 177, 32, 70, 13, 240, 145, 222, 136, 177, 212, ++ 248, 104, 34, 83, 89, 43, 177, 153, 121, 25, 177, 89, 121, 9, 177, 27, ++ 121, 27, 177, 4, 53, 32, 45, 244, 209, 3, 224, 212, 248, 8, 5, 35, 240, ++ 244, 220, 212, 248, 24, 53, 27, 104, 163, 177, 32, 70, 24, 240, 249, ++ 223, 212, 248, 24, 53, 90, 104, 27, 104, 178, 251, 243, 241, 3, 251, ++ 17, 35, 19, 185, 32, 70, 7, 240, 155, 216, 212, 248, 24, 53, 90, 104, ++ 1, 50, 90, 96, 10, 224, 35, 104, 154, 106, 30, 35, 178, 251, 243, 241, ++ 3, 251, 17, 35, 19, 185, 32, 70, 24, 240, 220, 223, 148, 248, 112, 50, ++ 67, 177, 148, 248, 224, 52, 1, 59, 219, 178, 2, 43, 2, 216, 32, 70, ++ 7, 240, 58, 222, 0, 37, 212, 248, 104, 50, 95, 89, 31, 179, 187, 121, ++ 11, 187, 59, 122, 251, 177, 215, 248, 4, 49, 155, 122, 219, 177, 56, ++ 70, 22, 240, 34, 216, 184, 177, 59, 124, 171, 177, 215, 248, 4, 49, ++ 155, 122, 139, 177, 59, 122, 123, 177, 7, 241, 188, 6, 48, 70, 242, ++ 247, 162, 254, 3, 70, 64, 185, 79, 240, 255, 50, 0, 144, 1, 146, 32, ++ 70, 57, 70, 50, 70, 23, 240, 87, 220, 4, 53, 32, 45, 212, 209, 32, 70, ++ 253, 247, 216, 253, 35, 106, 91, 125, 179, 177, 35, 104, 154, 106, 60, ++ 35, 178, 251, 243, 245, 3, 251, 21, 37, 117, 185, 212, 248, 104, 50, ++ 88, 89, 56, 177, 131, 121, 43, 185, 3, 122, 27, 177, 3, 124, 11, 185, ++ 9, 240, 72, 220, 4, 53, 32, 45, 240, 209, 32, 70, 248, 247, 159, 249, ++ 32, 185, 212, 248, 8, 5, 35, 240, 159, 217, 32, 177, 35, 106, 32, 33, ++ 24, 105, 0, 34, 3, 224, 35, 106, 32, 33, 24, 105, 1, 34, 23, 240, 179, ++ 251, 0, 38, 212, 248, 104, 50, 157, 89, 197, 177, 43, 122, 179, 177, ++ 35, 104, 147, 248, 79, 48, 152, 7, 17, 208, 213, 248, 92, 51, 27, 120, ++ 107, 177, 171, 121, 19, 185, 40, 70, 7, 240, 224, 223, 171, 121, 27, ++ 185, 213, 248, 92, 51, 27, 121, 19, 177, 40, 70, 7, 240, 201, 223, 4, ++ 54, 32, 46, 223, 209, 0, 38, 212, 248, 104, 50, 157, 89, 253, 177, 213, ++ 248, 136, 48, 19, 177, 1, 59, 197, 248, 136, 48, 213, 248, 140, 112, ++ 31, 177, 1, 63, 197, 248, 140, 112, 18, 224, 171, 121, 131, 177, 43, ++ 109, 153, 7, 13, 213, 149, 248, 132, 48, 83, 177, 241, 243, 114, 243, ++ 213, 248, 144, 16, 41, 240, 172, 222, 24, 177, 197, 248, 136, 112, 133, ++ 248, 132, 112, 4, 54, 32, 46, 216, 209, 180, 248, 60, 55, 27, 177, 1, ++ 59, 164, 248, 60, 55, 2, 224, 32, 70, 19, 240, 30, 220, 0, 38, 53, 70, ++ 11, 224, 212, 248, 168, 50, 155, 25, 91, 106, 35, 177, 212, 248, 172, ++ 34, 82, 248, 37, 0, 152, 71, 1, 53, 56, 54, 35, 104, 147, 248, 184, ++ 32, 149, 66, 238, 219, 147, 248, 60, 80, 69, 177, 147, 248, 61, 80, ++ 45, 177, 148, 248, 228, 85, 21, 177, 227, 104, 211, 248, 128, 81, 0, ++ 38, 212, 248, 104, 50, 83, 248, 6, 144, 185, 241, 0, 15, 64, 208, 153, ++ 248, 6, 48, 0, 43, 60, 209, 153, 248, 8, 48, 0, 43, 56, 208, 153, 248, ++ 66, 51, 218, 7, 4, 213, 32, 70, 73, 70, 153, 248, 64, 35, 5, 224, 152, ++ 7, 5, 213, 153, 248, 65, 35, 32, 70, 73, 70, 20, 240, 161, 221, 148, ++ 248, 228, 53, 35, 179, 153, 248, 4, 48, 11, 179, 217, 248, 4, 49, 74, ++ 70, 25, 120, 32, 70, 253, 247, 176, 255, 35, 104, 147, 248, 60, 32, ++ 178, 177, 147, 248, 61, 48, 155, 177, 148, 248, 114, 50, 131, 185, 217, ++ 248, 244, 48, 212, 248, 84, 1, 223, 141, 147, 248, 96, 48, 191, 2, 1, ++ 51, 95, 67, 153, 248, 68, 16, 43, 70, 58, 70, 69, 240, 36, 221, 237, ++ 25, 4, 54, 32, 46, 180, 209, 35, 104, 147, 248, 60, 32, 106, 177, 147, ++ 248, 61, 48, 83, 177, 148, 248, 114, 34, 58, 185, 148, 248, 228, 53, ++ 35, 177, 212, 248, 84, 1, 1, 33, 20, 240, 228, 254, 0, 35, 132, 248, ++ 228, 53, 32, 70, 39, 240, 191, 255, 212, 248, 108, 50, 35, 177, 211, ++ 248, 4, 33, 10, 177, 18, 120, 26, 177, 212, 248, 104, 2, 0, 34, 2, 224, ++ 27, 122, 203, 185, 248, 231, 131, 88, 147, 177, 157, 121, 211, 248, ++ 204, 16, 21, 177, 137, 4, 5, 212, 11, 224, 17, 244, 0, 95, 8, 208, 201, ++ 3, 6, 212, 25, 122, 33, 177, 211, 248, 4, 49, 11, 177, 27, 120, 27, ++ 177, 4, 50, 32, 42, 231, 209, 3, 224, 160, 104, 2, 33, 2, 240, 138, ++ 221, 32, 70, 12, 240, 141, 217, 184, 241, 0, 15, 4, 208, 32, 70, 2, ++ 33, 0, 34, 25, 240, 45, 223, 7, 176, 189, 232, 240, 131, 45, 233, 240, ++ 79, 139, 176, 7, 147, 221, 248, 80, 128, 0, 35, 141, 248, 39, 48, 4, ++ 70, 21, 158, 221, 248, 28, 160, 184, 248, 4, 0, 22, 159, 154, 66, 24, ++ 191, 146, 70, 145, 70, 0, 240, 3, 0, 242, 136, 6, 63, 2, 40, 17, 70, ++ 7, 209, 18, 178, 154, 66, 4, 218, 17, 240, 12, 15, 20, 191, 0, 35, 1, ++ 35, 27, 185, 6, 241, 30, 5, 28, 35, 2, 224, 6, 241, 34, 5, 32, 35, 255, ++ 26, 11, 47, 64, 243, 4, 129, 179, 29, 6, 147, 35, 104, 147, 248, 21, ++ 49, 115, 177, 148, 248, 1, 55, 91, 185, 212, 248, 92, 1, 57, 240, 62, ++ 216, 48, 177, 32, 70, 65, 70, 6, 154, 43, 70, 0, 151, 6, 240, 242, 220, ++ 212, 248, 104, 49, 75, 177, 155, 121, 59, 177, 32, 70, 65, 70, 50, 70, ++ 6, 155, 141, 232, 160, 0, 249, 247, 131, 253, 6, 155, 32, 70, 141, 232, ++ 168, 0, 13, 241, 39, 3, 3, 147, 73, 70, 51, 70, 66, 70, 252, 247, 193, ++ 250, 212, 248, 108, 50, 153, 69, 78, 209, 148, 248, 144, 55, 0, 43, ++ 74, 208, 148, 248, 46, 50, 59, 177, 160, 104, 212, 248, 236, 17, 2, ++ 240, 141, 220, 0, 35, 132, 248, 46, 50, 148, 248, 184, 55, 59, 177, ++ 160, 104, 212, 248, 180, 23, 2, 240, 130, 220, 0, 35, 132, 248, 184, ++ 55, 148, 248, 160, 55, 79, 240, 0, 11, 1, 43, 5, 209, 32, 70, 255, 247, ++ 249, 252, 132, 248, 208, 183, 23, 224, 79, 240, 1, 12, 132, 248, 208, ++ 199, 32, 70, 2, 33, 90, 70, 132, 248, 144, 183, 205, 248, 20, 192, 25, ++ 240, 150, 222, 160, 104, 212, 248, 180, 23, 13, 34, 91, 70, 2, 240, ++ 57, 220, 221, 248, 20, 192, 132, 248, 184, 199, 212, 248, 236, 17, 32, ++ 70, 212, 248, 8, 176, 5, 145, 12, 240, 99, 222, 1, 35, 2, 70, 5, 153, ++ 88, 70, 2, 240, 39, 220, 1, 35, 132, 248, 46, 50, 157, 248, 39, 48, ++ 91, 177, 157, 248, 92, 48, 67, 177, 6, 155, 32, 70, 141, 232, 168, 0, ++ 73, 70, 66, 70, 51, 70, 11, 240, 87, 223, 107, 137, 219, 7, 58, 213, ++ 212, 248, 124, 1, 41, 70, 58, 70, 58, 240, 96, 219, 0, 40, 50, 209, ++ 148, 248, 1, 55, 1, 43, 46, 208, 184, 248, 22, 48, 19, 244, 64, 79, ++ 95, 250, 131, 251, 21, 209, 5, 241, 12, 0, 167, 241, 12, 1, 3, 34, 242, ++ 247, 36, 253, 248, 177, 67, 120, 235, 177, 131, 120, 91, 69, 26, 209, ++ 34, 106, 16, 105, 5, 147, 23, 240, 61, 250, 5, 155, 192, 178, 131, 66, ++ 12, 224, 35, 106, 24, 105, 23, 240, 53, 250, 192, 178, 131, 69, 10, ++ 209, 32, 70, 41, 70, 58, 70, 7, 240, 165, 220, 131, 69, 3, 209, 212, ++ 248, 104, 1, 83, 240, 35, 218, 7, 155, 59, 185, 6, 241, 22, 1, 32, 70, ++ 15, 240, 224, 253, 1, 70, 8, 185, 10, 224, 7, 153, 139, 121, 59, 185, ++ 32, 70, 42, 70, 43, 70, 141, 232, 128, 1, 2, 150, 9, 240, 194, 216, ++ 185, 241, 0, 15, 29, 208, 218, 248, 248, 48, 155, 104, 15, 43, 24, 209, ++ 43, 70, 80, 70, 65, 70, 50, 70, 25, 240, 130, 217, 80, 70, 0, 33, 12, ++ 240, 56, 249, 35, 104, 147, 248, 47, 48, 35, 177, 212, 248, 8, 5, 35, ++ 240, 42, 218, 5, 224, 218, 248, 4, 49, 80, 70, 25, 122, 253, 247, 180, ++ 252, 11, 176, 189, 232, 240, 143, 45, 233, 240, 79, 31, 70, 155, 176, ++ 0, 35, 189, 104, 16, 145, 23, 147, 24, 147, 25, 147, 146, 70, 234, 136, ++ 4, 70, 144, 178, 6, 144, 186, 248, 4, 16, 0, 240, 12, 8, 13, 145, 1, ++ 240, 3, 1, 2, 41, 79, 234, 152, 8, 7, 209, 18, 178, 154, 66, 4, 218, ++ 195, 235, 8, 0, 67, 66, 67, 235, 0, 3, 219, 178, 8, 147, 186, 137, 8, ++ 152, 162, 241, 10, 3, 9, 147, 14, 146, 131, 0, 184, 241, 0, 15, 3, 209, ++ 9, 153, 23, 51, 139, 66, 11, 218, 6, 154, 2, 240, 252, 6, 148, 46, 3, ++ 208, 164, 46, 1, 208, 132, 46, 4, 209, 9, 155, 15, 43, 1, 220, 35, 104, ++ 236, 225, 171, 122, 19, 240, 1, 3, 11, 147, 10, 209, 32, 70, 5, 241, ++ 10, 1, 15, 240, 20, 253, 12, 144, 0, 48, 24, 191, 1, 32, 10, 144, 2, ++ 224, 0, 33, 12, 145, 10, 145, 184, 241, 0, 15, 69, 209, 11, 155, 5, ++ 241, 22, 2, 7, 146, 139, 185, 186, 248, 22, 48, 24, 170, 219, 178, 14, ++ 43, 0, 146, 32, 70, 5, 241, 10, 1, 5, 241, 16, 2, 148, 191, 0, 35, 1, ++ 35, 38, 240, 67, 251, 23, 144, 36, 224, 195, 70, 193, 70, 176, 70, 212, ++ 248, 104, 50, 83, 248, 11, 96, 174, 177, 6, 241, 188, 0, 7, 153, 6, ++ 34, 235, 247, 82, 251, 112, 185, 51, 124, 59, 177, 32, 70, 49, 70, 5, ++ 241, 16, 2, 38, 240, 36, 251, 23, 144, 32, 177, 51, 70, 24, 147, 70, ++ 70, 200, 70, 6, 224, 11, 241, 4, 11, 187, 241, 32, 15, 223, 209, 70, ++ 70, 200, 70, 24, 155, 25, 147, 75, 185, 32, 70, 7, 153, 15, 240, 21, ++ 253, 7, 144, 25, 144, 4, 224, 0, 32, 7, 144, 1, 224, 0, 33, 7, 145, ++ 212, 248, 8, 50, 27, 185, 35, 104, 147, 248, 44, 32, 10, 179, 148, 46, ++ 3, 208, 164, 46, 1, 208, 132, 46, 2, 209, 10, 154, 26, 187, 3, 224, ++ 128, 46, 32, 208, 80, 46, 30, 208, 184, 241, 0, 15, 64, 240, 224, 131, ++ 10, 155, 195, 185, 5, 241, 10, 0, 242, 247, 81, 251, 0, 40, 0, 240, ++ 215, 131, 25, 155, 123, 185, 5, 241, 22, 0, 242, 247, 72, 251, 80, 185, ++ 206, 227, 11, 152, 56, 185, 10, 153, 41, 185, 211, 248, 136, 48, 154, ++ 111, 1, 50, 154, 103, 196, 227, 212, 248, 8, 50, 99, 185, 25, 155, 11, ++ 185, 212, 248, 108, 50, 147, 248, 233, 32, 42, 177, 32, 70, 81, 70, ++ 58, 70, 219, 104, 249, 247, 210, 248, 184, 241, 1, 15, 14, 209, 196, ++ 46, 12, 208, 212, 46, 10, 208, 5, 241, 16, 0, 242, 247, 45, 251, 0, ++ 40, 64, 240, 167, 131, 43, 124, 217, 7, 0, 241, 163, 131, 187, 104, ++ 9, 154, 6, 51, 187, 96, 147, 178, 34, 104, 187, 129, 210, 248, 136, ++ 32, 5, 241, 6, 11, 209, 108, 32, 70, 1, 49, 209, 100, 23, 170, 141, ++ 232, 12, 0, 25, 169, 90, 70, 83, 70, 254, 247, 243, 255, 48, 177, 35, ++ 104, 211, 248, 136, 48, 218, 111, 1, 50, 218, 103, 131, 227, 23, 153, ++ 17, 177, 35, 104, 155, 106, 139, 98, 184, 241, 1, 15, 60, 209, 148, ++ 46, 4, 208, 164, 46, 2, 208, 132, 46, 64, 240, 117, 131, 187, 137, 184, ++ 104, 163, 241, 16, 5, 189, 129, 8, 157, 0, 241, 16, 2, 186, 96, 37, ++ 177, 0, 241, 20, 2, 20, 59, 186, 96, 187, 129, 164, 46, 187, 137, 14, ++ 209, 11, 105, 155, 121, 0, 43, 0, 240, 94, 131, 145, 248, 231, 48, 0, ++ 43, 0, 240, 89, 131, 32, 70, 6, 154, 10, 240, 181, 248, 83, 227, 32, ++ 104, 144, 248, 66, 80, 0, 45, 0, 240, 78, 131, 144, 248, 67, 0, 0, 40, ++ 0, 240, 73, 131, 132, 46, 2, 208, 148, 46, 64, 240, 68, 131, 32, 70, ++ 0, 150, 29, 240, 211, 218, 62, 227, 186, 248, 22, 48, 11, 154, 19, 244, ++ 64, 79, 12, 191, 0, 32, 1, 32, 15, 144, 0, 42, 64, 240, 132, 128, 171, ++ 139, 152, 178, 173, 248, 36, 48, 11, 144, 89, 185, 25, 155, 59, 177, ++ 25, 70, 32, 70, 5, 241, 16, 2, 15, 155, 38, 240, 55, 250, 0, 224, 8, ++ 70, 23, 144, 6, 155, 19, 244, 0, 99, 17, 147, 19, 208, 35, 104, 211, ++ 248, 136, 48, 211, 248, 76, 35, 1, 50, 195, 248, 76, 35, 23, 154, 74, ++ 177, 210, 248, 52, 18, 11, 152, 1, 49, 194, 248, 52, 18, 178, 248, 196, ++ 32, 130, 66, 51, 208, 23, 155, 195, 177, 189, 248, 36, 16, 163, 248, ++ 196, 16, 81, 224, 9, 241, 168, 8, 4, 235, 200, 8, 64, 70, 242, 247, ++ 125, 250, 128, 185, 5, 241, 16, 0, 65, 70, 6, 34, 235, 247, 39, 250, ++ 88, 177, 9, 241, 1, 9, 95, 250, 137, 249, 0, 224, 153, 70, 148, 248, ++ 144, 53, 75, 69, 230, 210, 79, 240, 0, 8, 17, 155, 171, 177, 35, 104, ++ 211, 248, 136, 48, 211, 248, 76, 35, 1, 50, 195, 248, 76, 35, 184, 241, ++ 0, 15, 13, 208, 184, 248, 6, 32, 11, 152, 130, 66, 32, 209, 211, 248, ++ 188, 33, 1, 50, 195, 248, 188, 33, 205, 226, 184, 241, 0, 15, 23, 209, ++ 148, 248, 144, 53, 5, 241, 16, 1, 3, 241, 168, 8, 4, 235, 200, 8, 1, ++ 51, 132, 248, 144, 53, 6, 34, 64, 70, 235, 247, 3, 250, 148, 248, 144, ++ 37, 10, 35, 178, 251, 243, 241, 3, 251, 17, 35, 132, 248, 144, 53, 189, ++ 248, 36, 16, 168, 248, 6, 16, 10, 154, 90, 177, 24, 155, 75, 177, 25, ++ 152, 131, 121, 51, 185, 208, 248, 4, 49, 27, 123, 19, 177, 6, 153, 9, ++ 240, 182, 216, 186, 104, 187, 137, 8, 152, 2, 241, 24, 9, 163, 241, ++ 24, 1, 199, 248, 8, 144, 185, 129, 40, 177, 2, 241, 28, 9, 28, 59, 199, ++ 248, 8, 144, 187, 129, 13, 153, 192, 46, 193, 243, 192, 17, 8, 145, ++ 187, 137, 3, 208, 208, 46, 1, 208, 160, 46, 17, 209, 205, 248, 0, 176, ++ 1, 151, 212, 248, 100, 6, 25, 153, 23, 154, 83, 70, 71, 240, 130, 218, ++ 0, 40, 0, 240, 120, 130, 215, 248, 8, 144, 183, 248, 12, 128, 22, 224, ++ 6, 154, 152, 70, 82, 4, 18, 213, 7, 43, 35, 104, 5, 220, 211, 248, 136, ++ 48, 90, 110, 1, 50, 90, 102, 101, 226, 176, 46, 49, 208, 211, 248, 136, ++ 48, 211, 248, 220, 33, 1, 50, 195, 248, 220, 33, 91, 226, 80, 46, 0, ++ 240, 230, 128, 16, 216, 32, 46, 0, 240, 37, 130, 6, 216, 0, 46, 0, 240, ++ 33, 130, 16, 46, 64, 240, 78, 130, 120, 224, 48, 46, 118, 208, 64, 46, ++ 64, 240, 72, 130, 134, 224, 176, 46, 14, 208, 6, 216, 128, 46, 0, 240, ++ 14, 129, 160, 46, 64, 240, 62, 130, 23, 225, 192, 46, 0, 240, 121, 129, ++ 208, 46, 64, 240, 55, 130, 35, 226, 184, 241, 5, 15, 64, 243, 44, 130, ++ 35, 104, 147, 248, 102, 49, 27, 177, 185, 248, 0, 48, 3, 43, 9, 208, ++ 185, 248, 2, 48, 1, 43, 5, 209, 32, 70, 5, 241, 22, 1, 15, 240, 16, ++ 251, 25, 144, 25, 153, 0, 41, 0, 240, 28, 130, 139, 121, 0, 43, 52, ++ 208, 11, 121, 0, 43, 0, 240, 21, 130, 23, 155, 243, 177, 154, 104, 144, ++ 5, 27, 213, 147, 248, 36, 32, 210, 7, 23, 213, 216, 104, 3, 241, 20, ++ 4, 209, 248, 240, 32, 24, 177, 5, 105, 0, 45, 8, 191, 0, 32, 3, 144, ++ 32, 32, 0, 37, 2, 38, 5, 144, 8, 70, 33, 70, 141, 232, 96, 0, 2, 149, ++ 4, 149, 254, 247, 160, 251, 243, 225, 8, 157, 205, 248, 0, 128, 1, 149, ++ 186, 248, 16, 48, 90, 70, 3, 240, 8, 3, 2, 147, 212, 248, 8, 5, 75, ++ 70, 8, 240, 222, 252, 227, 225, 212, 248, 56, 51, 147, 249, 52, 48, ++ 0, 43, 0, 240, 221, 129, 8, 157, 8, 70, 74, 70, 89, 70, 67, 70, 0, 149, ++ 12, 240, 146, 255, 211, 225, 184, 241, 5, 15, 64, 243, 202, 129, 25, ++ 152, 0, 40, 0, 240, 204, 129, 131, 121, 0, 43, 64, 240, 200, 129, 23, ++ 153, 90, 70, 75, 70, 205, 248, 0, 128, 12, 240, 144, 253, 191, 225, ++ 212, 248, 124, 2, 44, 33, 58, 240, 16, 220, 128, 177, 0, 35, 0, 147, ++ 1, 147, 2, 147, 8, 241, 24, 3, 4, 147, 205, 248, 12, 176, 32, 70, 212, ++ 248, 108, 18, 44, 34, 5, 241, 16, 3, 13, 240, 254, 221, 212, 248, 124, ++ 2, 137, 33, 58, 240, 249, 219, 192, 177, 19, 174, 32, 70, 81, 70, 42, ++ 70, 51, 70, 248, 247, 219, 255, 0, 35, 0, 147, 1, 147, 2, 147, 8, 241, ++ 24, 3, 4, 147, 205, 248, 12, 176, 5, 150, 32, 70, 212, 248, 108, 18, ++ 137, 34, 5, 241, 16, 3, 13, 240, 241, 221, 32, 70, 81, 70, 42, 70, 91, ++ 70, 205, 248, 0, 144, 205, 248, 4, 128, 10, 240, 157, 220, 0, 35, 2, ++ 147, 205, 248, 0, 160, 1, 149, 212, 248, 80, 1, 89, 70, 74, 70, 67, ++ 70, 75, 240, 151, 219, 114, 225, 184, 241, 11, 15, 64, 243, 105, 129, ++ 35, 104, 147, 248, 21, 49, 123, 177, 148, 248, 1, 55, 99, 185, 212, ++ 248, 92, 1, 56, 240, 15, 220, 56, 177, 32, 70, 81, 70, 90, 70, 75, 70, ++ 205, 248, 0, 128, 6, 240, 194, 216, 91, 70, 32, 70, 81, 70, 42, 70, ++ 205, 248, 0, 144, 205, 248, 4, 128, 10, 240, 112, 220, 212, 248, 80, ++ 1, 73, 70, 66, 70, 75, 240, 86, 221, 212, 248, 104, 49, 0, 43, 0, 240, ++ 70, 129, 155, 121, 0, 43, 0, 240, 66, 129, 10, 152, 0, 40, 0, 240, 62, ++ 129, 32, 70, 81, 70, 42, 70, 91, 70, 205, 248, 0, 144, 205, 248, 4, ++ 128, 249, 247, 57, 249, 50, 225, 1, 35, 1, 149, 14, 157, 3, 147, 32, ++ 70, 16, 153, 24, 154, 7, 155, 205, 248, 0, 160, 2, 149, 255, 247, 87, ++ 251, 36, 225, 184, 241, 1, 15, 64, 243, 27, 129, 25, 155, 0, 43, 0, ++ 240, 29, 129, 154, 121, 185, 248, 0, 96, 90, 187, 32, 70, 23, 153, 22, ++ 240, 74, 217, 23, 152, 144, 248, 36, 48, 155, 7, 20, 213, 2, 33, 83, ++ 240, 6, 219, 23, 155, 147, 248, 36, 32, 18, 240, 8, 2, 11, 209, 32, ++ 70, 25, 153, 5, 241, 16, 3, 0, 150, 1, 146, 205, 248, 8, 144, 205, 248, ++ 12, 128, 41, 240, 52, 218, 24, 155, 0, 43, 0, 240, 247, 128, 25, 152, ++ 208, 248, 248, 48, 155, 104, 11, 177, 40, 240, 127, 216, 25, 152, 3, ++ 33, 157, 224, 23, 153, 10, 105, 154, 66, 64, 240, 232, 128, 32, 70, ++ 22, 240, 26, 217, 23, 152, 144, 248, 36, 48, 153, 7, 26, 213, 18, 33, ++ 83, 240, 214, 218, 0, 34, 5, 241, 16, 3, 32, 70, 25, 153, 1, 146, 0, ++ 150, 205, 248, 8, 144, 205, 248, 12, 128, 41, 240, 9, 218, 25, 155, ++ 154, 121, 0, 42, 0, 240, 150, 128, 211, 248, 204, 48, 154, 4, 0, 241, ++ 198, 128, 143, 224, 16, 33, 83, 240, 187, 218, 192, 224, 184, 241, 1, ++ 15, 64, 243, 183, 128, 25, 158, 38, 185, 12, 152, 0, 40, 0, 240, 183, ++ 128, 6, 70, 23, 155, 185, 248, 0, 160, 59, 185, 32, 70, 49, 70, 5, 241, ++ 16, 2, 15, 155, 37, 240, 190, 255, 23, 144, 23, 153, 17, 177, 32, 70, ++ 22, 240, 218, 216, 179, 121, 23, 152, 0, 43, 84, 209, 0, 40, 59, 208, ++ 18, 33, 83, 240, 149, 218, 23, 152, 144, 248, 36, 48, 219, 7, 2, 212, ++ 67, 104, 153, 0, 48, 213, 1, 33, 83, 240, 138, 218, 170, 241, 13, 3, ++ 155, 178, 9, 43, 7, 216, 35, 104, 211, 248, 136, 48, 211, 248, 248, ++ 33, 1, 50, 195, 248, 248, 33, 14, 34, 212, 248, 188, 6, 49, 70, 86, ++ 240, 151, 222, 23, 155, 147, 248, 36, 32, 18, 240, 4, 2, 15, 209, 205, ++ 248, 0, 160, 91, 104, 32, 70, 195, 243, 64, 115, 1, 147, 49, 70, 5, ++ 241, 16, 3, 205, 248, 8, 144, 205, 248, 12, 128, 41, 240, 175, 216, ++ 23, 155, 90, 104, 34, 240, 0, 82, 90, 96, 24, 155, 0, 43, 95, 208, 25, ++ 152, 3, 124, 0, 43, 91, 208, 208, 248, 248, 48, 90, 104, 155, 104, 2, ++ 42, 1, 209, 10, 43, 83, 216, 11, 177, 39, 240, 224, 223, 25, 152, 2, ++ 33, 11, 240, 114, 255, 75, 224, 0, 40, 73, 208, 3, 105, 179, 66, 70, ++ 209, 144, 248, 36, 48, 218, 7, 66, 213, 0, 34, 32, 70, 49, 70, 5, 241, ++ 16, 3, 205, 248, 0, 160, 1, 146, 205, 248, 8, 144, 205, 248, 12, 128, ++ 41, 240, 124, 216, 32, 70, 23, 153, 83, 240, 132, 222, 47, 224, 184, ++ 241, 3, 15, 38, 221, 25, 153, 81, 179, 11, 121, 67, 179, 139, 121, 51, ++ 179, 5, 241, 22, 0, 188, 49, 6, 34, 234, 247, 85, 255, 248, 185, 23, ++ 155, 8, 157, 1, 147, 205, 248, 0, 128, 2, 149, 212, 248, 8, 5, 25, 153, ++ 90, 70, 75, 70, 8, 240, 120, 254, 17, 224, 32, 70, 23, 153, 90, 70, ++ 75, 70, 141, 232, 0, 5, 2, 149, 3, 151, 254, 247, 136, 254, 48, 177, ++ 10, 224, 35, 104, 211, 248, 136, 48, 26, 111, 1, 50, 26, 103, 16, 152, ++ 57, 70, 0, 34, 243, 247, 18, 255, 27, 176, 189, 232, 240, 143, 112, ++ 181, 144, 248, 46, 50, 0, 37, 4, 70, 128, 248, 184, 87, 51, 177, 128, ++ 104, 212, 248, 236, 17, 1, 240, 22, 223, 132, 248, 46, 82, 32, 70, 254, ++ 247, 148, 255, 0, 35, 132, 248, 208, 55, 32, 70, 166, 104, 212, 248, ++ 236, 81, 12, 240, 24, 217, 1, 35, 2, 70, 41, 70, 48, 70, 1, 240, 220, ++ 222, 1, 35, 132, 248, 46, 50, 112, 189, 45, 233, 240, 79, 139, 137, ++ 137, 176, 13, 43, 6, 70, 15, 70, 146, 70, 13, 217, 16, 224, 114, 75, ++ 250, 138, 27, 104, 57, 70, 83, 248, 34, 64, 0, 35, 251, 130, 112, 104, ++ 1, 34, 243, 247, 212, 254, 39, 70, 0, 47, 240, 209, 1, 32, 202, 225, ++ 67, 104, 17, 70, 7, 147, 15, 240, 104, 248, 48, 70, 81, 70, 215, 248, ++ 8, 176, 15, 240, 98, 248, 5, 70, 186, 241, 0, 15, 1, 209, 208, 248, ++ 12, 160, 51, 104, 147, 248, 176, 48, 43, 177, 214, 248, 144, 1, 41, ++ 70, 58, 70, 26, 240, 84, 219, 154, 248, 4, 48, 2, 43, 5, 209, 218, 248, ++ 16, 64, 20, 241, 20, 8, 31, 209, 0, 224, 0, 36, 43, 121, 0, 43, 0, 240, ++ 135, 128, 171, 121, 67, 185, 5, 241, 188, 0, 241, 247, 11, 255, 24, ++ 177, 126, 224, 71, 70, 0, 32, 147, 225, 170, 121, 26, 177, 217, 70, ++ 79, 240, 0, 8, 9, 224, 43, 124, 27, 177, 5, 241, 188, 9, 144, 70, 3, ++ 224, 217, 70, 152, 70, 0, 224, 193, 70, 213, 248, 244, 48, 91, 142, ++ 3, 244, 64, 67, 163, 245, 64, 66, 83, 66, 67, 235, 2, 3, 6, 147, 184, ++ 241, 0, 15, 46, 209, 171, 121, 99, 179, 153, 248, 0, 48, 219, 7, 40, ++ 213, 187, 248, 12, 48, 26, 10, 66, 234, 3, 35, 27, 178, 6, 43, 32, 209, ++ 187, 105, 216, 5, 29, 213, 48, 70, 41, 70, 11, 241, 6, 2, 6, 155, 37, ++ 240, 96, 254, 4, 70, 160, 177, 8, 35, 1, 147, 48, 70, 41, 70, 12, 34, ++ 4, 241, 20, 3, 205, 248, 0, 128, 205, 248, 8, 128, 205, 248, 12, 128, ++ 205, 248, 16, 128, 13, 240, 143, 219, 48, 70, 33, 70, 83, 240, 137, ++ 221, 187, 105, 35, 244, 128, 115, 187, 97, 184, 241, 0, 15, 15, 209, ++ 43, 124, 107, 177, 153, 248, 0, 48, 217, 7, 9, 212, 48, 70, 41, 70, ++ 74, 70, 6, 155, 37, 240, 54, 254, 4, 70, 0, 40, 66, 209, 23, 224, 153, ++ 248, 0, 48, 218, 7, 26, 213, 213, 248, 204, 48, 91, 5, 15, 212, 213, ++ 248, 244, 48, 91, 142, 3, 244, 64, 67, 163, 245, 64, 64, 67, 66, 67, ++ 235, 0, 3, 14, 51, 5, 235, 131, 3, 92, 104, 0, 44, 41, 209, 51, 104, ++ 211, 248, 136, 48, 90, 106, 1, 50, 90, 98, 122, 231, 12, 187, 48, 70, ++ 41, 70, 74, 70, 6, 155, 37, 240, 12, 254, 4, 70, 200, 185, 48, 70, 41, ++ 70, 74, 70, 6, 155, 37, 240, 183, 254, 4, 70, 104, 185, 51, 104, 211, ++ 248, 136, 48, 26, 106, 1, 50, 26, 98, 218, 248, 32, 48, 1, 51, 202, ++ 248, 32, 48, 93, 231, 32, 7, 0, 0, 48, 70, 33, 70, 83, 240, 218, 220, ++ 48, 70, 57, 70, 34, 70, 246, 247, 139, 254, 128, 70, 0, 40, 63, 244, ++ 79, 175, 149, 248, 37, 51, 187, 185, 42, 109, 64, 242, 55, 19, 19, 64, ++ 147, 177, 81, 6, 16, 212, 131, 105, 218, 6, 13, 212, 0, 43, 11, 219, ++ 227, 104, 75, 185, 171, 110, 88, 28, 63, 244, 57, 175, 5, 235, 131, ++ 3, 219, 110, 0, 43, 63, 244, 51, 175, 149, 248, 68, 48, 200, 248, 40, ++ 64, 136, 248, 33, 48, 51, 104, 147, 248, 69, 48, 19, 179, 184, 248, ++ 14, 48, 97, 79, 3, 240, 7, 3, 223, 248, 132, 145, 251, 92, 214, 248, ++ 100, 1, 25, 248, 3, 16, 34, 70, 52, 240, 153, 216, 0, 40, 63, 244, 23, ++ 175, 171, 121, 115, 177, 35, 125, 217, 7, 11, 212, 184, 248, 14, 48, ++ 214, 248, 100, 1, 3, 240, 7, 3, 251, 92, 34, 70, 25, 248, 3, 16, 52, ++ 240, 135, 217, 216, 248, 24, 48, 154, 5, 23, 212, 99, 104, 19, 240, ++ 64, 3, 7, 208, 184, 248, 14, 48, 76, 74, 3, 240, 7, 3, 211, 92, 75, ++ 74, 211, 92, 166, 51, 86, 248, 35, 144, 185, 241, 0, 15, 7, 208, 48, ++ 70, 65, 70, 74, 70, 246, 247, 164, 252, 1, 224, 79, 240, 0, 9, 216, ++ 248, 24, 48, 67, 240, 128, 67, 200, 248, 24, 48, 213, 248, 4, 49, 147, ++ 248, 72, 48, 83, 177, 65, 70, 112, 104, 241, 247, 56, 253, 0, 33, 0, ++ 144, 1, 34, 40, 70, 11, 70, 76, 240, 55, 219, 184, 248, 14, 48, 56, ++ 74, 3, 240, 7, 3, 18, 248, 3, 176, 212, 248, 52, 49, 26, 122, 7, 42, ++ 6, 209, 29, 104, 88, 104, 33, 70, 66, 70, 91, 70, 168, 71, 33, 224, ++ 48, 75, 69, 70, 234, 138, 27, 104, 83, 248, 34, 128, 0, 35, 235, 130, ++ 235, 137, 35, 244, 128, 83, 235, 129, 184, 241, 0, 15, 7, 208, 48, 70, ++ 33, 70, 42, 70, 67, 70, 205, 248, 0, 144, 19, 240, 111, 223, 212, 248, ++ 52, 49, 33, 70, 31, 104, 88, 104, 42, 70, 91, 70, 184, 71, 184, 241, ++ 0, 15, 221, 209, 48, 70, 218, 248, 12, 16, 251, 247, 62, 250, 0, 32, ++ 46, 224, 28, 75, 250, 138, 27, 104, 83, 248, 34, 64, 0, 35, 251, 130, ++ 251, 137, 50, 104, 35, 244, 128, 83, 27, 4, 81, 107, 27, 12, 251, 129, ++ 169, 177, 17, 73, 3, 240, 7, 3, 203, 92, 16, 73, 210, 248, 140, 32, ++ 205, 92, 7, 152, 4, 53, 2, 235, 197, 5, 107, 104, 57, 70, 1, 51, 107, ++ 96, 213, 248, 8, 128, 241, 247, 209, 252, 64, 68, 168, 96, 7, 152, 57, ++ 70, 1, 34, 243, 247, 8, 253, 39, 70, 1, 32, 0, 47, 208, 209, 9, 176, ++ 189, 232, 240, 143, 0, 191, 138, 182, 135, 0, 84, 194, 135, 0, 72, 194, ++ 135, 0, 32, 7, 0, 0, 45, 233, 240, 79, 141, 176, 22, 156, 7, 146, 212, ++ 248, 8, 128, 155, 70, 184, 248, 12, 48, 208, 248, 4, 144, 26, 10, 66, ++ 234, 3, 35, 14, 105, 155, 178, 5, 70, 15, 70, 72, 70, 33, 70, 4, 147, ++ 241, 247, 162, 252, 5, 144, 4, 152, 176, 245, 1, 79, 53, 209, 30, 177, ++ 150, 248, 37, 51, 0, 43, 73, 209, 213, 248, 84, 50, 0, 43, 69, 208, ++ 184, 248, 14, 48, 26, 10, 66, 234, 3, 34, 146, 178, 19, 5, 27, 13, 0, ++ 43, 59, 209, 227, 137, 65, 70, 35, 240, 7, 3, 67, 234, 82, 50, 226, ++ 129, 8, 168, 12, 34, 234, 247, 237, 252, 163, 104, 162, 137, 3, 241, ++ 4, 8, 4, 58, 162, 129, 196, 248, 8, 128, 27, 138, 33, 70, 26, 10, 66, ++ 234, 3, 35, 155, 178, 72, 70, 4, 147, 241, 247, 109, 252, 8, 169, 5, ++ 144, 12, 34, 64, 70, 234, 247, 213, 252, 4, 153, 72, 246, 108, 3, 153, ++ 66, 19, 209, 0, 34, 64, 70, 5, 153, 19, 70, 241, 247, 230, 250, 30, ++ 48, 11, 208, 0, 34, 72, 70, 33, 70, 243, 247, 147, 252, 43, 104, 211, ++ 248, 136, 48, 26, 111, 1, 50, 26, 103, 29, 225, 152, 248, 0, 48, 3, ++ 240, 1, 3, 6, 147, 179, 121, 0, 43, 0, 240, 153, 128, 6, 154, 40, 70, ++ 0, 146, 49, 70, 58, 70, 35, 70, 5, 240, 77, 218, 0, 40, 64, 240, 10, ++ 129, 7, 155, 19, 185, 214, 248, 12, 160, 0, 224, 130, 70, 150, 248, ++ 59, 48, 216, 7, 0, 241, 131, 128, 7, 152, 0, 40, 127, 209, 6, 153, 81, ++ 179, 153, 7, 4, 213, 88, 70, 241, 247, 195, 252, 0, 40, 118, 208, 214, ++ 248, 204, 48, 154, 4, 19, 213, 88, 70, 241, 247, 186, 252, 120, 185, ++ 150, 248, 69, 48, 99, 185, 213, 248, 8, 50, 75, 185, 43, 104, 147, 248, ++ 44, 48, 43, 185, 48, 70, 89, 70, 48, 240, 93, 216, 0, 40, 88, 209, 33, ++ 70, 72, 70, 243, 247, 99, 252, 1, 70, 0, 40, 87, 208, 40, 70, 82, 70, ++ 10, 240, 28, 221, 82, 224, 182, 248, 196, 48, 184, 248, 2, 32, 184, ++ 248, 0, 16, 90, 64, 182, 248, 194, 48, 75, 64, 26, 67, 184, 248, 4, ++ 16, 182, 248, 198, 48, 75, 64, 19, 67, 155, 178, 0, 43, 62, 208, 40, ++ 70, 49, 70, 66, 70, 37, 240, 28, 252, 0, 40, 55, 208, 144, 248, 36, ++ 48, 155, 7, 51, 213, 43, 104, 90, 107, 202, 177, 226, 137, 87, 73, 2, ++ 240, 7, 2, 138, 92, 86, 73, 211, 248, 140, 48, 138, 92, 72, 70, 16, ++ 50, 3, 235, 194, 2, 81, 104, 19, 29, 1, 49, 81, 96, 33, 70, 210, 248, ++ 8, 176, 3, 147, 241, 247, 198, 251, 3, 155, 88, 68, 88, 96, 43, 104, ++ 147, 248, 44, 48, 99, 177, 33, 70, 72, 70, 243, 247, 23, 252, 1, 70, ++ 48, 177, 40, 70, 82, 70, 10, 240, 209, 220, 79, 240, 0, 9, 7, 224, 40, ++ 70, 33, 70, 82, 70, 10, 240, 201, 220, 123, 224, 79, 240, 1, 9, 42, ++ 104, 5, 152, 210, 248, 136, 48, 25, 108, 1, 49, 25, 100, 89, 108, 9, ++ 24, 89, 100, 213, 248, 8, 53, 19, 177, 89, 105, 1, 49, 89, 97, 215, ++ 248, 248, 48, 19, 185, 57, 105, 201, 104, 0, 224, 25, 70, 8, 108, 1, ++ 48, 8, 100, 11, 185, 59, 105, 219, 104, 89, 108, 5, 152, 9, 24, 89, ++ 100, 83, 107, 139, 177, 227, 137, 44, 73, 3, 240, 7, 3, 203, 92, 43, ++ 73, 210, 248, 140, 32, 203, 92, 8, 51, 2, 235, 195, 3, 90, 104, 1, 50, ++ 90, 96, 154, 104, 130, 24, 154, 96, 4, 153, 72, 246, 142, 3, 153, 66, ++ 3, 208, 72, 246, 180, 3, 153, 66, 7, 209, 40, 70, 33, 70, 58, 70, 51, ++ 70, 205, 248, 0, 128, 13, 240, 90, 216, 43, 104, 90, 107, 26, 185, 147, ++ 248, 79, 48, 152, 7, 6, 208, 225, 137, 17, 240, 7, 1, 2, 209, 32, 70, ++ 241, 247, 12, 252, 6, 154, 210, 185, 215, 248, 164, 49, 153, 4, 22, ++ 213, 185, 241, 0, 15, 19, 208, 178, 121, 213, 248, 96, 22, 56, 105, ++ 0, 42, 20, 191, 24, 34, 0, 34, 139, 24, 136, 80, 226, 137, 10, 73, 2, ++ 240, 7, 2, 154, 129, 138, 92, 9, 73, 95, 96, 138, 92, 26, 117, 251, ++ 105, 40, 70, 1, 51, 251, 97, 49, 70, 58, 70, 35, 70, 22, 240, 20, 218, ++ 13, 176, 189, 232, 240, 143, 0, 191, 138, 182, 135, 0, 84, 194, 135, ++ 0, 45, 233, 240, 79, 194, 104, 147, 176, 210, 248, 128, 33, 0, 35, 15, ++ 146, 208, 248, 96, 38, 4, 70, 19, 99, 146, 248, 52, 32, 173, 248, 68, ++ 48, 213, 26, 106, 66, 66, 235, 5, 2, 1, 37, 14, 145, 141, 248, 71, 32, ++ 12, 149, 8, 147, 154, 70, 7, 147, 9, 147, 31, 70, 11, 145, 231, 225, ++ 158, 104, 15, 154, 49, 138, 178, 97, 212, 248, 200, 5, 17, 240, 4, 2, ++ 14, 153, 24, 191, 2, 34, 18, 24, 136, 104, 128, 24, 136, 96, 153, 137, ++ 211, 248, 8, 128, 138, 26, 154, 129, 65, 70, 48, 70, 32, 240, 62, 255, ++ 14, 153, 131, 70, 141, 104, 139, 137, 175, 29, 6, 59, 26, 32, 139, 129, ++ 173, 248, 66, 0, 143, 96, 96, 104, 10, 151, 241, 247, 225, 250, 13, ++ 144, 115, 138, 216, 7, 4, 212, 96, 104, 14, 153, 4, 34, 240, 243, 178, ++ 244, 235, 136, 212, 248, 96, 38, 19, 244, 128, 115, 24, 191, 24, 35, ++ 210, 24, 87, 104, 14, 155, 13, 152, 159, 98, 215, 248, 96, 49, 57, 70, ++ 1, 51, 199, 248, 96, 49, 7, 146, 241, 233, 100, 35, 18, 24, 67, 241, ++ 0, 3, 193, 233, 0, 35, 152, 248, 1, 32, 152, 248, 0, 48, 215, 248, 16, ++ 160, 19, 67, 152, 248, 2, 32, 26, 67, 7, 208, 212, 248, 96, 1, 89, 70, ++ 114, 138, 37, 240, 45, 252, 199, 248, 108, 177, 154, 248, 6, 48, 0, ++ 43, 86, 209, 218, 248, 252, 32, 49, 70, 147, 113, 35, 105, 211, 248, ++ 148, 48, 88, 106, 22, 240, 196, 253, 32, 70, 49, 70, 65, 240, 247, 216, ++ 128, 70, 152, 177, 65, 70, 150, 249, 29, 32, 1, 35, 80, 70, 65, 240, ++ 78, 217, 49, 70, 212, 248, 172, 38, 32, 70, 65, 240, 140, 216, 129, ++ 70, 73, 70, 80, 70, 1, 34, 65, 240, 144, 217, 0, 224, 129, 70, 14, 155, ++ 12, 153, 131, 248, 35, 128, 131, 248, 34, 144, 81, 179, 27, 240, 64, ++ 127, 88, 70, 1, 208, 32, 240, 173, 253, 0, 240, 127, 2, 2, 42, 9, 208, ++ 4, 42, 7, 208, 11, 42, 5, 208, 162, 241, 22, 1, 74, 66, 66, 235, 1, ++ 2, 0, 224, 1, 34, 79, 240, 0, 8, 241, 136, 150, 249, 28, 48, 205, 248, ++ 0, 128, 1, 146, 178, 136, 32, 70, 146, 11, 2, 146, 9, 10, 66, 70, 205, ++ 248, 12, 128, 205, 248, 16, 160, 40, 240, 70, 255, 205, 248, 48, 128, ++ 235, 136, 223, 248, 164, 131, 19, 244, 128, 79, 8, 209, 218, 248, 80, ++ 32, 64, 242, 55, 19, 19, 64, 147, 177, 154, 248, 88, 48, 123, 177, 7, ++ 155, 10, 154, 1, 147, 13, 241, 66, 3, 0, 146, 2, 147, 32, 70, 57, 70, ++ 14, 154, 51, 70, 245, 247, 76, 255, 0, 40, 64, 240, 215, 128, 7, 152, ++ 41, 127, 130, 137, 104, 127, 7, 235, 66, 3, 65, 234, 0, 33, 163, 248, ++ 180, 16, 14, 155, 216, 248, 0, 16, 216, 138, 2, 240, 7, 2, 81, 248, ++ 32, 176, 217, 137, 212, 248, 56, 1, 33, 240, 7, 1, 10, 67, 218, 129, ++ 177, 136, 58, 70, 1, 240, 3, 1, 10, 155, 6, 240, 183, 252, 14, 153, ++ 139, 105, 138, 104, 19, 240, 128, 15, 189, 248, 66, 48, 21, 208, 210, ++ 24, 138, 96, 138, 137, 212, 248, 48, 1, 211, 26, 139, 129, 13, 241, ++ 71, 3, 141, 232, 136, 0, 0, 35, 2, 147, 14, 169, 7, 154, 17, 171, 7, ++ 240, 3, 250, 0, 40, 64, 240, 154, 128, 147, 224, 2, 235, 3, 9, 211, ++ 92, 170, 43, 51, 209, 153, 248, 1, 48, 170, 43, 47, 209, 153, 248, 2, ++ 48, 3, 43, 43, 209, 153, 248, 3, 48, 67, 187, 153, 248, 4, 48, 43, 187, ++ 153, 248, 5, 48, 75, 185, 185, 248, 6, 48, 32, 70, 25, 10, 65, 234, ++ 3, 33, 137, 178, 245, 247, 200, 250, 104, 177, 153, 248, 5, 48, 248, ++ 43, 20, 209, 185, 248, 6, 48, 32, 70, 25, 10, 65, 234, 3, 33, 137, 178, ++ 245, 247, 186, 250, 80, 177, 14, 154, 189, 248, 66, 16, 147, 104, 144, ++ 137, 6, 57, 91, 24, 65, 26, 147, 96, 145, 129, 18, 224, 14, 154, 189, ++ 248, 66, 16, 144, 137, 161, 241, 14, 14, 147, 104, 65, 26, 137, 178, ++ 115, 68, 206, 235, 0, 14, 8, 10, 64, 234, 1, 33, 147, 96, 162, 248, ++ 12, 224, 153, 129, 234, 136, 210, 5, 11, 212, 233, 138, 217, 128, 42, ++ 139, 26, 129, 104, 139, 88, 129, 233, 137, 153, 128, 170, 137, 90, 128, ++ 109, 137, 10, 224, 40, 138, 216, 128, 105, 138, 25, 129, 170, 138, 90, ++ 129, 104, 139, 152, 128, 41, 139, 89, 128, 237, 138, 29, 128, 157, 248, ++ 71, 32, 98, 177, 154, 137, 8, 42, 6, 208, 77, 246, 134, 81, 85, 26, ++ 106, 66, 66, 235, 5, 2, 0, 224, 1, 34, 141, 248, 71, 32, 1, 147, 15, ++ 171, 2, 147, 189, 248, 66, 48, 10, 157, 3, 147, 32, 70, 81, 70, 14, ++ 154, 51, 70, 0, 149, 250, 247, 224, 253, 144, 185, 14, 155, 9, 157, ++ 218, 137, 13, 152, 66, 244, 128, 82, 218, 129, 189, 248, 68, 48, 45, ++ 24, 1, 51, 173, 248, 68, 48, 9, 149, 14, 157, 205, 248, 56, 176, 8, ++ 149, 57, 224, 14, 157, 216, 248, 0, 32, 235, 138, 8, 152, 82, 248, 35, ++ 48, 32, 177, 3, 177, 27, 136, 8, 153, 203, 130, 0, 224, 11, 147, 234, ++ 138, 216, 248, 0, 48, 7, 152, 83, 248, 34, 48, 0, 34, 14, 147, 235, ++ 137, 234, 130, 35, 244, 128, 83, 235, 129, 35, 104, 2, 125, 211, 248, ++ 140, 48, 12, 50, 3, 235, 194, 2, 81, 104, 1, 49, 81, 96, 6, 125, 41, ++ 70, 12, 54, 3, 235, 198, 6, 96, 104, 214, 248, 8, 128, 241, 247, 43, ++ 249, 64, 68, 176, 96, 41, 70, 96, 104, 0, 34, 243, 247, 98, 249, 11, ++ 157, 0, 45, 0, 240, 160, 128, 14, 155, 0, 43, 127, 244, 20, 174, 157, ++ 248, 71, 80, 184, 70, 11, 158, 0, 45, 115, 208, 32, 104, 189, 248, 68, ++ 16, 208, 248, 136, 32, 9, 159, 210, 248, 24, 51, 194, 248, 28, 19, 139, ++ 66, 44, 191, 194, 248, 24, 51, 194, 248, 24, 19, 19, 108, 208, 248, ++ 140, 80, 91, 24, 19, 100, 83, 108, 219, 25, 7, 159, 83, 100, 59, 125, ++ 8, 51, 5, 235, 195, 3, 95, 104, 207, 25, 95, 96, 7, 159, 59, 125, 9, ++ 159, 8, 51, 5, 235, 195, 3, 157, 104, 125, 25, 157, 96, 212, 248, 8, ++ 53, 19, 177, 93, 105, 109, 24, 93, 97, 218, 248, 12, 48, 9, 159, 29, ++ 108, 128, 106, 109, 24, 29, 100, 93, 108, 237, 25, 93, 100, 200, 248, ++ 40, 0, 210, 248, 12, 3, 65, 24, 194, 248, 12, 19, 160, 104, 153, 104, ++ 50, 70, 1, 35, 244, 247, 226, 252, 78, 224, 41, 75, 242, 138, 27, 104, ++ 0, 32, 83, 248, 34, 112, 240, 130, 96, 104, 49, 70, 241, 247, 196, 248, ++ 142, 40, 22, 216, 175, 177, 96, 104, 57, 70, 241, 247, 189, 248, 142, ++ 40, 15, 216, 32, 70, 49, 70, 58, 70, 245, 247, 26, 252, 72, 177, 243, ++ 137, 96, 104, 35, 244, 128, 83, 243, 129, 49, 70, 0, 34, 243, 247, 234, ++ 248, 6, 224, 29, 177, 49, 136, 233, 130, 53, 70, 1, 224, 53, 70, 176, ++ 70, 62, 70, 0, 224, 168, 70, 0, 46, 207, 209, 67, 70, 26, 224, 16, 74, ++ 217, 138, 18, 104, 32, 70, 82, 248, 33, 80, 0, 34, 218, 130, 218, 137, ++ 34, 244, 128, 82, 218, 129, 34, 104, 210, 248, 136, 32, 210, 248, 16, ++ 19, 1, 49, 194, 248, 16, 19, 0, 147, 153, 106, 0, 34, 155, 104, 255, ++ 247, 201, 251, 43, 70, 0, 43, 226, 209, 19, 176, 189, 232, 240, 143, ++ 0, 191, 32, 7, 0, 0, 45, 233, 240, 79, 147, 139, 14, 105, 141, 176, ++ 7, 70, 13, 70, 20, 70, 208, 248, 4, 160, 195, 243, 128, 43, 46, 177, ++ 150, 248, 37, 35, 0, 42, 24, 191, 79, 240, 0, 11, 148, 248, 42, 32, ++ 18, 177, 148, 248, 34, 128, 0, 224, 144, 70, 148, 248, 44, 32, 226, ++ 185, 24, 5, 26, 213, 59, 104, 211, 248, 136, 48, 211, 248, 76, 35, 1, ++ 50, 195, 248, 76, 35, 213, 248, 52, 34, 1, 50, 197, 248, 52, 34, 5, ++ 235, 72, 2, 178, 248, 180, 16, 180, 248, 126, 32, 145, 66, 5, 209, 211, ++ 248, 188, 33, 1, 50, 195, 248, 188, 33, 127, 227, 179, 121, 147, 187, ++ 214, 248, 4, 145, 153, 248, 12, 48, 131, 177, 148, 248, 44, 48, 107, ++ 185, 187, 241, 0, 15, 10, 209, 149, 248, 218, 32, 99, 106, 82, 250, ++ 3, 243, 217, 7, 3, 212, 48, 70, 161, 139, 7, 240, 100, 223, 59, 104, ++ 91, 107, 203, 177, 153, 248, 28, 48, 179, 177, 148, 248, 42, 48, 155, ++ 177, 148, 248, 40, 48, 131, 177, 0, 33, 48, 70, 22, 240, 188, 217, 214, ++ 248, 204, 48, 154, 4, 8, 213, 162, 139, 18, 244, 0, 82, 4, 209, 215, ++ 248, 80, 1, 49, 70, 73, 240, 111, 223, 35, 140, 19, 240, 4, 2, 64, 240, ++ 70, 131, 163, 139, 3, 244, 128, 67, 99, 99, 150, 248, 37, 19, 9, 177, ++ 162, 99, 35, 224, 59, 185, 50, 109, 64, 242, 55, 19, 19, 64, 235, 177, ++ 150, 248, 88, 48, 211, 177, 0, 35, 163, 99, 56, 70, 35, 70, 81, 70, ++ 42, 70, 205, 248, 0, 128, 84, 240, 140, 217, 99, 107, 64, 185, 0, 43, ++ 0, 240, 37, 131, 213, 248, 116, 49, 1, 51, 197, 248, 116, 49, 30, 227, ++ 35, 177, 213, 248, 112, 49, 1, 51, 197, 248, 112, 49, 148, 248, 44, ++ 48, 67, 185, 8, 241, 88, 3, 180, 248, 126, 0, 5, 235, 67, 3, 154, 136, ++ 152, 128, 0, 224, 0, 34, 148, 248, 44, 48, 0, 43, 64, 240, 73, 129, ++ 180, 248, 126, 0, 8, 241, 28, 9, 16, 240, 15, 3, 64, 240, 154, 128, ++ 5, 235, 137, 9, 217, 248, 4, 16, 121, 177, 26, 70, 80, 70, 2, 147, 242, ++ 247, 243, 255, 2, 155, 5, 235, 136, 2, 194, 248, 148, 48, 8, 241, 78, ++ 2, 201, 248, 4, 48, 69, 248, 34, 48, 187, 241, 0, 15, 0, 240, 40, 129, ++ 212, 248, 20, 224, 8, 241, 28, 9, 227, 104, 5, 235, 137, 9, 201, 248, ++ 4, 224, 3, 147, 222, 248, 8, 48, 222, 248, 4, 0, 90, 13, 190, 248, 6, ++ 192, 82, 5, 192, 243, 20, 0, 16, 24, 57, 104, 190, 248, 12, 32, 204, ++ 243, 74, 28, 12, 241, 1, 12, 3, 235, 2, 14, 201, 105, 132, 68, 206, ++ 235, 12, 14, 27, 26, 137, 104, 115, 68, 154, 24, 138, 66, 48, 218, 80, ++ 70, 242, 247, 151, 255, 201, 248, 4, 0, 0, 40, 0, 240, 182, 130, 98, ++ 105, 128, 104, 145, 104, 83, 104, 33, 240, 127, 78, 46, 244, 96, 14, ++ 146, 137, 195, 243, 20, 3, 195, 235, 14, 3, 201, 26, 154, 24, 233, 247, ++ 211, 255, 97, 105, 139, 104, 74, 104, 35, 240, 127, 67, 35, 244, 96, ++ 3, 194, 243, 20, 2, 154, 26, 217, 248, 4, 48, 152, 104, 128, 24, 152, ++ 96, 152, 137, 130, 26, 154, 129, 136, 137, 0, 34, 152, 129, 80, 70, ++ 242, 247, 139, 255, 58, 104, 3, 153, 210, 105, 5, 235, 136, 3, 146, ++ 104, 165, 72, 82, 26, 215, 248, 200, 21, 6, 58, 82, 26, 195, 248, 148, ++ 32, 97, 104, 8, 34, 233, 247, 150, 255, 107, 104, 16, 185, 67, 240, ++ 8, 3, 1, 224, 35, 240, 8, 3, 107, 96, 156, 72, 97, 104, 8, 34, 233, ++ 247, 137, 255, 171, 104, 16, 185, 67, 240, 32, 3, 1, 224, 35, 240, 32, ++ 3, 171, 96, 166, 224, 5, 235, 137, 1, 73, 104, 33, 185, 150, 248, 37, ++ 195, 188, 241, 0, 15, 60, 208, 80, 64, 32, 240, 15, 0, 32, 185, 2, 240, ++ 15, 2, 1, 50, 147, 66, 19, 208, 0, 34, 80, 70, 242, 247, 77, 255, 8, ++ 241, 28, 2, 0, 35, 5, 235, 130, 2, 83, 96, 8, 241, 36, 2, 5, 235, 130, ++ 2, 8, 241, 78, 8, 83, 96, 69, 248, 40, 48, 31, 224, 150, 248, 37, 147, ++ 185, 241, 0, 15, 123, 209, 8, 241, 36, 12, 5, 235, 140, 12, 163, 104, ++ 220, 248, 4, 32, 147, 66, 32, 217, 80, 70, 74, 70, 205, 248, 8, 192, ++ 242, 247, 41, 255, 221, 248, 8, 192, 5, 235, 136, 3, 8, 241, 78, 8, ++ 195, 248, 116, 144, 204, 248, 4, 144, 69, 248, 40, 144, 59, 104, 211, ++ 248, 136, 48, 26, 110, 1, 50, 26, 102, 43, 105, 0, 43, 0, 240, 21, 130, ++ 219, 104, 90, 109, 1, 50, 90, 101, 15, 226, 12, 241, 4, 2, 141, 232, ++ 8, 4, 56, 70, 99, 104, 205, 248, 8, 192, 4, 240, 116, 219, 80, 70, 97, ++ 105, 74, 70, 242, 247, 255, 254, 221, 248, 8, 192, 187, 241, 0, 15, ++ 61, 209, 8, 241, 28, 3, 5, 235, 131, 3, 90, 104, 98, 97, 195, 248, 4, ++ 176, 8, 241, 78, 3, 69, 248, 35, 176, 147, 104, 146, 137, 3, 241, 24, ++ 1, 204, 248, 4, 176, 97, 96, 162, 241, 24, 1, 161, 96, 148, 248, 41, ++ 16, 35, 96, 226, 96, 33, 177, 3, 241, 30, 1, 30, 58, 97, 96, 162, 96, ++ 148, 248, 42, 32, 58, 177, 98, 104, 132, 248, 34, 128, 2, 50, 98, 96, ++ 162, 104, 2, 58, 162, 96, 26, 120, 91, 120, 66, 234, 3, 35, 163, 131, ++ 99, 107, 91, 177, 163, 107, 75, 177, 147, 249, 14, 32, 97, 104, 138, ++ 24, 98, 96, 147, 249, 14, 48, 162, 104, 211, 26, 163, 96, 163, 107, ++ 99, 177, 27, 122, 4, 43, 4, 209, 56, 70, 33, 70, 84, 240, 177, 216, ++ 4, 224, 11, 43, 2, 209, 32, 70, 10, 240, 35, 222, 187, 241, 0, 15, 64, ++ 240, 201, 129, 98, 105, 147, 105, 91, 6, 24, 213, 150, 248, 37, 51, ++ 0, 43, 64, 240, 162, 129, 179, 121, 43, 185, 212, 248, 128, 16, 48, ++ 70, 24, 49, 75, 240, 244, 219, 99, 105, 155, 105, 24, 6, 64, 241, 149, ++ 129, 215, 248, 48, 1, 41, 70, 34, 70, 30, 240, 101, 217, 171, 225, 35, ++ 104, 152, 136, 217, 136, 173, 248, 16, 0, 173, 248, 18, 16, 24, 137, ++ 89, 137, 173, 248, 20, 0, 173, 248, 24, 16, 152, 137, 217, 137, 173, ++ 248, 26, 0, 173, 248, 28, 16, 24, 138, 89, 138, 173, 248, 32, 0, 173, ++ 248, 34, 16, 152, 138, 148, 248, 41, 16, 173, 248, 36, 0, 65, 177, 25, ++ 139, 88, 139, 155, 139, 173, 248, 40, 16, 173, 248, 42, 0, 173, 248, ++ 44, 48, 163, 139, 19, 244, 128, 127, 3, 244, 0, 115, 4, 209, 4, 169, ++ 97, 103, 35, 177, 8, 171, 5, 224, 8, 169, 97, 103, 11, 185, 6, 171, ++ 0, 224, 10, 171, 97, 104, 35, 103, 147, 104, 56, 70, 195, 235, 1, 8, ++ 3, 240, 123, 222, 99, 105, 153, 137, 136, 177, 7, 41, 64, 242, 71, 129, ++ 154, 104, 168, 241, 6, 8, 66, 68, 200, 235, 1, 8, 154, 96, 163, 248, ++ 12, 128, 226, 102, 21, 224, 84, 251, 135, 0, 3, 21, 4, 0, 13, 41, 64, ++ 242, 53, 129, 154, 104, 168, 241, 14, 8, 66, 68, 200, 235, 1, 8, 154, ++ 96, 163, 248, 12, 128, 35, 137, 226, 102, 25, 10, 65, 234, 3, 35, 147, ++ 129, 163, 107, 107, 177, 27, 122, 1, 43, 10, 208, 3, 43, 8, 208, 56, ++ 70, 81, 70, 42, 70, 35, 70, 83, 240, 49, 221, 0, 40, 0, 240, 22, 129, ++ 163, 107, 51, 177, 27, 122, 2, 43, 3, 209, 56, 70, 33, 70, 84, 240, ++ 9, 216, 150, 248, 80, 51, 155, 177, 227, 110, 155, 137, 26, 10, 66, ++ 234, 3, 35, 147, 74, 27, 178, 147, 66, 10, 209, 56, 70, 97, 105, 6, ++ 34, 0, 35, 245, 247, 71, 248, 24, 177, 56, 70, 49, 70, 47, 240, 2, 222, ++ 98, 111, 227, 110, 17, 136, 25, 128, 80, 136, 88, 128, 145, 136, 153, ++ 128, 33, 111, 8, 136, 216, 128, 72, 136, 24, 129, 137, 136, 89, 129, ++ 97, 105, 148, 248, 34, 224, 200, 137, 14, 240, 7, 14, 32, 240, 7, 0, ++ 78, 234, 0, 0, 200, 129, 17, 120, 201, 7, 11, 213, 57, 104, 209, 248, ++ 136, 16, 209, 248, 208, 1, 1, 48, 193, 248, 208, 1, 241, 104, 136, 109, ++ 1, 48, 136, 101, 150, 248, 89, 16, 97, 177, 149, 248, 36, 16, 200, 6, ++ 8, 212, 153, 137, 8, 10, 64, 234, 1, 33, 113, 72, 9, 178, 129, 66, 64, ++ 240, 189, 128, 215, 248, 156, 17, 113, 92, 121, 177, 149, 248, 36, 16, ++ 201, 6, 11, 212, 155, 137, 25, 10, 65, 234, 3, 35, 106, 73, 27, 178, ++ 139, 66, 3, 208, 38, 57, 139, 66, 64, 240, 169, 128, 179, 121, 235, ++ 185, 146, 248, 0, 128, 24, 240, 1, 8, 24, 209, 214, 248, 4, 49, 48, ++ 70, 147, 248, 116, 32, 1, 50, 131, 248, 116, 32, 212, 248, 128, 16, ++ 24, 49, 75, 240, 239, 218, 97, 105, 80, 70, 240, 247, 81, 253, 1, 33, ++ 3, 70, 66, 70, 48, 70, 205, 248, 0, 128, 75, 240, 79, 219, 215, 248, ++ 188, 54, 27, 104, 243, 88, 0, 43, 53, 208, 27, 104, 0, 43, 50, 208, ++ 212, 248, 108, 128, 184, 248, 12, 48, 26, 10, 66, 234, 3, 35, 77, 74, ++ 27, 178, 147, 66, 39, 209, 150, 248, 155, 51, 19, 177, 150, 248, 234, ++ 51, 11, 179, 80, 70, 97, 105, 66, 70, 18, 35, 23, 240, 191, 223, 0, ++ 40, 59, 208, 184, 248, 16, 48, 80, 70, 26, 10, 66, 234, 3, 35, 97, 105, ++ 8, 241, 18, 2, 155, 178, 23, 240, 177, 223, 0, 40, 45, 208, 99, 107, ++ 215, 248, 188, 6, 0, 51, 24, 191, 1, 35, 49, 70, 66, 70, 39, 240, 21, ++ 254, 0, 40, 76, 209, 115, 105, 0, 43, 47, 208, 212, 248, 108, 128, 184, ++ 248, 12, 48, 26, 10, 66, 234, 3, 35, 50, 74, 27, 178, 147, 66, 36, 209, ++ 80, 70, 97, 105, 66, 70, 18, 35, 23, 240, 143, 223, 96, 177, 184, 248, ++ 16, 48, 80, 70, 26, 10, 66, 234, 3, 35, 97, 105, 8, 241, 18, 2, 155, ++ 178, 23, 240, 130, 223, 48, 185, 59, 104, 211, 248, 136, 48, 90, 110, ++ 1, 50, 90, 102, 35, 224, 98, 107, 112, 105, 0, 50, 24, 191, 1, 34, 65, ++ 70, 43, 70, 42, 240, 219, 223, 200, 185, 213, 248, 164, 49, 219, 7, ++ 11, 213, 148, 248, 41, 48, 67, 185, 227, 110, 155, 137, 26, 10, 66, ++ 234, 3, 35, 23, 74, 27, 178, 147, 66, 9, 209, 99, 105, 148, 248, 41, ++ 32, 0, 147, 56, 70, 41, 70, 99, 111, 255, 247, 7, 248, 29, 224, 59, ++ 104, 90, 107, 170, 177, 97, 105, 16, 72, 202, 137, 211, 248, 140, 48, ++ 2, 240, 7, 2, 130, 92, 14, 72, 133, 92, 80, 70, 12, 53, 3, 235, 197, ++ 5, 107, 104, 174, 104, 1, 51, 107, 96, 240, 247, 169, 252, 128, 25, ++ 168, 96, 80, 70, 97, 105, 0, 34, 242, 247, 224, 252, 13, 176, 189, 232, ++ 240, 143, 0, 191, 142, 136, 255, 255, 180, 136, 255, 255, 138, 182, ++ 135, 0, 84, 194, 135, 0, 45, 233, 240, 79, 79, 240, 0, 9, 177, 176, ++ 205, 248, 184, 144, 205, 248, 188, 144, 214, 138, 152, 70, 18, 147, ++ 155, 137, 4, 70, 33, 43, 15, 70, 21, 70, 205, 248, 108, 144, 141, 248, ++ 86, 144, 205, 248, 88, 144, 141, 248, 95, 144, 141, 248, 92, 144, 141, ++ 248, 148, 144, 141, 248, 96, 144, 141, 248, 99, 144, 19, 146, 45, 146, ++ 205, 248, 144, 144, 1, 216, 3, 104, 74, 224, 216, 248, 8, 176, 16, 70, ++ 89, 70, 32, 240, 182, 248, 11, 241, 6, 3, 10, 144, 200, 248, 44, 0, ++ 13, 147, 187, 248, 6, 48, 25, 70, 173, 248, 80, 48, 1, 240, 12, 2, 24, ++ 70, 1, 240, 240, 3, 1, 244, 64, 113, 161, 245, 64, 126, 146, 8, 27, ++ 9, 222, 241, 0, 1, 65, 235, 14, 1, 2, 42, 8, 191, 79, 234, 211, 9, 173, ++ 248, 82, 32, 95, 250, 137, 242, 173, 248, 84, 48, 141, 248, 93, 16, ++ 141, 248, 94, 32, 181, 248, 4, 224, 14, 240, 3, 14, 190, 241, 2, 15, ++ 4, 209, 0, 178, 0, 40, 1, 218, 219, 8, 0, 224, 0, 35, 216, 178, 141, ++ 248, 95, 0, 0, 41, 20, 191, 40, 35, 34, 35, 2, 177, 2, 51, 0, 177, 4, ++ 51, 18, 152, 128, 137, 152, 66, 6, 210, 35, 104, 211, 248, 136, 48, ++ 90, 110, 1, 50, 90, 102, 205, 227, 155, 248, 10, 48, 3, 240, 1, 3, 141, ++ 248, 96, 48, 11, 241, 30, 3, 14, 147, 17, 177, 11, 241, 36, 3, 14, 147, ++ 0, 35, 141, 248, 97, 48, 74, 177, 14, 155, 90, 120, 27, 120, 67, 234, ++ 2, 34, 219, 9, 9, 146, 141, 248, 97, 48, 0, 224, 9, 146, 65, 70, 56, ++ 70, 240, 247, 253, 251, 18, 153, 11, 144, 139, 104, 56, 70, 6, 51, 139, ++ 96, 139, 137, 6, 59, 139, 129, 157, 248, 97, 48, 27, 177, 235, 243, ++ 39, 247, 1, 70, 56, 70, 4, 34, 239, 243, 196, 245, 22, 244, 64, 79, ++ 157, 248, 93, 32, 12, 191, 0, 33, 1, 33, 0, 35, 8, 145, 47, 147, 2, ++ 187, 189, 248, 80, 48, 13, 153, 19, 244, 64, 127, 9, 209, 1, 241, 16, ++ 6, 32, 70, 10, 49, 8, 154, 47, 171, 82, 240, 11, 220, 46, 144, 5, 224, ++ 216, 5, 1, 213, 14, 29, 1, 224, 1, 241, 10, 6, 47, 155, 35, 185, 32, ++ 70, 49, 70, 13, 240, 217, 253, 47, 144, 47, 155, 0, 51, 24, 191, 1, ++ 35, 141, 248, 100, 48, 47, 155, 19, 241, 0, 9, 157, 248, 96, 48, 24, ++ 191, 79, 240, 1, 9, 67, 185, 13, 153, 32, 70, 4, 49, 13, 240, 154, 253, ++ 6, 28, 24, 191, 1, 38, 0, 224, 0, 38, 212, 248, 8, 50, 27, 185, 35, ++ 104, 147, 248, 44, 48, 107, 179, 35, 104, 147, 248, 63, 32, 0, 42, 8, ++ 191, 79, 240, 0, 9, 126, 187, 189, 248, 80, 32, 210, 5, 6, 212, 157, ++ 248, 96, 32, 26, 177, 185, 241, 0, 15, 64, 240, 70, 131, 157, 248, 93, ++ 32, 18, 177, 157, 248, 96, 32, 58, 187, 147, 248, 44, 48, 0, 43, 0, ++ 240, 25, 131, 185, 241, 0, 15, 4, 209, 32, 70, 41, 70, 64, 240, 219, ++ 217, 16, 227, 47, 155, 155, 121, 0, 43, 64, 240, 12, 131, 79, 240, 1, ++ 10, 20, 224, 157, 248, 96, 48, 27, 185, 0, 46, 0, 240, 3, 131, 2, 224, ++ 0, 46, 0, 240, 33, 131, 157, 248, 93, 48, 43, 185, 185, 241, 0, 15, ++ 0, 240, 248, 130, 154, 70, 1, 224, 79, 240, 0, 10, 157, 248, 94, 48, ++ 67, 179, 157, 248, 97, 48, 131, 177, 47, 155, 35, 177, 147, 248, 37, ++ 51, 0, 43, 64, 240, 231, 130, 148, 248, 18, 50, 0, 43, 0, 240, 226, ++ 130, 18, 155, 154, 105, 66, 240, 64, 2, 154, 97, 9, 154, 111, 73, 2, ++ 240, 7, 3, 110, 74, 141, 248, 86, 48, 210, 92, 141, 248, 148, 48, 138, ++ 92, 9, 153, 22, 146, 1, 240, 16, 2, 18, 17, 141, 248, 92, 32, 14, 154, ++ 2, 50, 14, 146, 18, 155, 217, 137, 152, 137, 17, 244, 0, 82, 24, 191, ++ 179, 248, 80, 32, 14, 153, 155, 104, 130, 24, 195, 235, 1, 9, 16, 146, ++ 65, 70, 201, 235, 2, 2, 56, 70, 15, 146, 240, 247, 30, 251, 13, 154, ++ 201, 235, 0, 0, 17, 144, 147, 125, 209, 125, 67, 234, 1, 35, 173, 248, ++ 178, 48, 186, 241, 0, 15, 92, 209, 46, 171, 0, 147, 16, 155, 32, 70, ++ 1, 147, 47, 169, 43, 70, 253, 247, 150, 248, 0, 40, 64, 240, 154, 130, ++ 188, 226, 47, 153, 0, 41, 0, 240, 149, 130, 13, 154, 32, 70, 10, 50, ++ 8, 155, 36, 240, 52, 251, 46, 144, 40, 187, 47, 155, 27, 124, 19, 179, ++ 180, 70, 209, 70, 212, 248, 104, 34, 82, 248, 9, 96, 174, 177, 178, ++ 121, 154, 185, 50, 122, 138, 177, 214, 248, 204, 32, 19, 2, 13, 212, ++ 13, 152, 214, 248, 244, 16, 16, 48, 6, 34, 205, 248, 28, 192, 233, 247, ++ 56, 251, 221, 248, 28, 192, 8, 185, 50, 124, 138, 185, 9, 241, 4, 9, ++ 185, 241, 32, 15, 223, 209, 102, 70, 46, 155, 155, 185, 13, 154, 47, ++ 153, 32, 70, 10, 50, 8, 155, 36, 240, 182, 251, 1, 70, 46, 144, 48, ++ 185, 35, 104, 211, 248, 136, 48, 218, 110, 1, 50, 218, 102, 83, 226, ++ 32, 70, 82, 240, 224, 217, 47, 155, 211, 248, 204, 48, 195, 243, 192, ++ 83, 141, 248, 99, 48, 114, 226, 189, 248, 80, 48, 19, 244, 64, 127, ++ 4, 209, 47, 155, 27, 124, 0, 43, 58, 209, 6, 224, 157, 248, 93, 48, ++ 27, 185, 47, 155, 27, 124, 0, 43, 50, 208, 32, 70, 47, 153, 10, 50, ++ 8, 155, 36, 240, 138, 251, 46, 144, 24, 185, 46, 226, 46, 155, 27, 105, ++ 47, 147, 30, 177, 35, 104, 154, 106, 46, 155, 154, 98, 47, 155, 211, ++ 248, 252, 32, 8, 146, 186, 241, 0, 15, 38, 209, 157, 248, 93, 32, 26, ++ 187, 157, 248, 96, 32, 26, 177, 189, 248, 80, 32, 208, 5, 16, 212, 153, ++ 121, 189, 248, 80, 32, 17, 177, 209, 5, 10, 213, 21, 224, 27, 124, 2, ++ 244, 64, 114, 0, 43, 20, 191, 79, 244, 0, 115, 0, 35, 154, 66, 11, 208, ++ 35, 104, 211, 248, 136, 48, 154, 109, 1, 50, 154, 101, 253, 225, 0, ++ 191, 84, 194, 135, 0, 138, 182, 135, 0, 32, 70, 41, 70, 64, 240, 190, ++ 216, 0, 35, 136, 248, 35, 0, 129, 70, 47, 152, 136, 248, 34, 48, 131, ++ 121, 195, 185, 157, 248, 99, 48, 171, 185, 185, 241, 0, 15, 18, 208, ++ 73, 70, 149, 249, 29, 32, 51, 70, 64, 240, 9, 217, 41, 70, 212, 248, ++ 172, 38, 32, 70, 64, 240, 71, 216, 50, 70, 1, 70, 136, 248, 34, 0, 47, ++ 152, 64, 240, 74, 217, 46, 155, 147, 248, 162, 33, 42, 185, 157, 248, ++ 99, 32, 18, 185, 211, 248, 4, 33, 82, 179, 185, 241, 0, 15, 39, 208, ++ 211, 248, 0, 17, 211, 248, 252, 32, 66, 248, 33, 144, 212, 248, 116, ++ 36, 81, 121, 17, 240, 1, 0, 211, 248, 0, 17, 24, 191, 149, 249, 31, ++ 0, 3, 235, 129, 1, 193, 248, 172, 1, 82, 121, 82, 16, 18, 240, 1, 1, ++ 211, 248, 0, 33, 24, 191, 149, 249, 32, 16, 3, 235, 130, 2, 194, 248, ++ 204, 17, 211, 248, 0, 33, 1, 50, 2, 240, 7, 2, 195, 248, 0, 33, 157, ++ 248, 93, 32, 47, 155, 18, 177, 179, 248, 90, 48, 84, 224, 154, 121, ++ 50, 185, 211, 248, 72, 35, 0, 42, 67, 208, 146, 123, 210, 7, 64, 213, ++ 46, 153, 177, 248, 68, 32, 173, 248, 156, 32, 74, 104, 80, 6, 43, 213, ++ 157, 248, 94, 0, 64, 179, 189, 248, 178, 0, 0, 7, 36, 209, 145, 248, ++ 231, 0, 8, 179, 8, 125, 192, 7, 30, 212, 189, 248, 80, 0, 192, 4, 26, ++ 213, 144, 3, 24, 213, 145, 248, 217, 0, 22, 154, 80, 250, 2, 242, 210, ++ 7, 17, 213, 211, 248, 72, 51, 75, 177, 155, 123, 216, 7, 6, 213, 157, ++ 248, 92, 48, 27, 177, 32, 70, 8, 240, 85, 249, 32, 177, 32, 70, 46, ++ 153, 22, 154, 33, 240, 23, 223, 189, 248, 80, 48, 19, 244, 128, 95, ++ 46, 155, 90, 104, 20, 191, 66, 244, 0, 50, 34, 244, 0, 50, 90, 96, 12, ++ 224, 46, 154, 178, 248, 68, 32, 173, 248, 156, 32, 26, 124, 42, 185, ++ 179, 248, 90, 48, 217, 7, 1, 213, 173, 248, 156, 48, 47, 155, 154, 121, ++ 82, 185, 27, 124, 67, 177, 157, 248, 96, 48, 43, 185, 186, 241, 0, 15, ++ 2, 209, 8, 155, 131, 248, 6, 160, 157, 248, 96, 48, 251, 177, 47, 153, ++ 139, 121, 0, 43, 64, 240, 42, 129, 11, 124, 67, 177, 13, 152, 194, 49, ++ 16, 48, 6, 34, 233, 247, 232, 249, 0, 40, 0, 240, 31, 129, 13, 152, ++ 4, 48, 240, 247, 36, 250, 80, 185, 47, 152, 144, 248, 69, 48, 51, 185, ++ 13, 153, 4, 49, 46, 240, 205, 221, 0, 40, 64, 240, 15, 129, 10, 153, ++ 189, 248, 178, 32, 13, 155, 200, 248, 44, 16, 168, 248, 28, 32, 27, ++ 124, 46, 153, 19, 240, 1, 15, 11, 158, 79, 240, 0, 7, 7, 208, 209, 248, ++ 100, 49, 1, 51, 193, 248, 100, 49, 241, 233, 102, 35, 6, 224, 209, 248, ++ 96, 49, 1, 51, 193, 248, 96, 49, 241, 233, 100, 35, 146, 25, 67, 235, ++ 7, 3, 193, 233, 0, 35, 157, 248, 96, 48, 155, 185, 155, 248, 0, 48, ++ 155, 248, 1, 32, 26, 67, 155, 248, 2, 48, 19, 67, 10, 208, 216, 248, ++ 44, 16, 212, 248, 96, 1, 106, 138, 36, 240, 195, 250, 46, 155, 10, 153, ++ 195, 248, 108, 17, 155, 249, 3, 48, 0, 43, 7, 218, 35, 104, 211, 248, ++ 136, 48, 211, 248, 168, 34, 1, 50, 195, 248, 168, 34, 155, 248, 3, 48, ++ 19, 240, 48, 15, 7, 208, 35, 104, 211, 248, 136, 48, 211, 248, 176, ++ 34, 1, 50, 195, 248, 176, 34, 157, 248, 96, 48, 0, 43, 113, 209, 216, ++ 248, 44, 0, 35, 104, 16, 240, 64, 127, 211, 248, 136, 96, 1, 209, 192, ++ 178, 1, 224, 31, 240, 78, 252, 22, 40, 58, 208, 12, 216, 11, 40, 37, ++ 208, 4, 216, 2, 40, 22, 208, 4, 40, 91, 209, 25, 224, 12, 40, 35, 208, ++ 18, 40, 86, 209, 38, 224, 48, 40, 60, 208, 4, 216, 24, 40, 45, 208, ++ 36, 40, 78, 209, 48, 224, 96, 40, 64, 208, 108, 40, 68, 208, 72, 40, ++ 71, 209, 53, 224, 214, 248, 56, 50, 1, 51, 198, 248, 56, 50, 64, 224, ++ 214, 248, 60, 50, 1, 51, 198, 248, 60, 50, 58, 224, 214, 248, 64, 50, ++ 1, 51, 198, 248, 64, 50, 52, 224, 214, 248, 68, 50, 1, 51, 198, 248, ++ 68, 50, 46, 224, 214, 248, 72, 50, 1, 51, 198, 248, 72, 50, 40, 224, ++ 214, 248, 76, 50, 1, 51, 198, 248, 76, 50, 34, 224, 214, 248, 80, 50, ++ 1, 51, 198, 248, 80, 50, 28, 224, 214, 248, 84, 50, 1, 51, 198, 248, ++ 84, 50, 22, 224, 214, 248, 88, 50, 1, 51, 198, 248, 88, 50, 16, 224, ++ 214, 248, 92, 50, 1, 51, 198, 248, 92, 50, 10, 224, 214, 248, 96, 50, ++ 1, 51, 198, 248, 96, 50, 4, 224, 214, 248, 100, 50, 1, 51, 198, 248, ++ 100, 50, 157, 248, 96, 48, 27, 177, 47, 152, 13, 169, 244, 247, 110, ++ 253, 157, 248, 96, 48, 43, 187, 216, 248, 44, 0, 16, 240, 64, 127, 1, ++ 208, 31, 240, 215, 251, 0, 240, 127, 0, 2, 40, 9, 208, 4, 40, 7, 208, ++ 11, 40, 5, 208, 160, 241, 22, 2, 80, 66, 64, 235, 2, 0, 0, 224, 1, 32, ++ 0, 34, 233, 136, 149, 249, 28, 48, 0, 146, 1, 144, 168, 136, 9, 10, ++ 128, 11, 2, 144, 47, 152, 3, 146, 4, 144, 32, 70, 39, 240, 116, 253, ++ 46, 153, 75, 104, 91, 3, 11, 213, 157, 248, 96, 48, 67, 185, 186, 241, ++ 0, 15, 5, 209, 212, 248, 56, 1, 13, 170, 5, 240, 149, 251, 51, 224, ++ 32, 70, 13, 170, 254, 247, 242, 255, 46, 224, 35, 104, 90, 107, 194, ++ 177, 157, 248, 96, 32, 170, 185, 18, 153, 21, 72, 202, 137, 211, 248, ++ 140, 48, 2, 240, 7, 2, 130, 92, 19, 72, 132, 92, 56, 70, 12, 52, 3, ++ 235, 196, 4, 99, 104, 165, 104, 1, 51, 99, 96, 240, 247, 81, 248, 64, ++ 25, 160, 96, 56, 70, 18, 153, 0, 34, 242, 247, 136, 248, 12, 224, 178, ++ 70, 231, 228, 189, 248, 80, 48, 19, 244, 64, 127, 63, 244, 61, 173, ++ 47, 155, 0, 43, 127, 244, 166, 173, 161, 229, 49, 176, 189, 232, 240, ++ 143, 0, 191, 138, 182, 135, 0, 84, 194, 135, 0, 208, 248, 96, 54, 0, ++ 34, 45, 233, 240, 71, 142, 104, 71, 104, 26, 99, 208, 248, 200, 53, ++ 13, 70, 242, 24, 138, 96, 137, 137, 4, 70, 203, 26, 155, 178, 171, 129, ++ 49, 138, 73, 7, 7, 213, 1, 43, 1, 216, 3, 104, 79, 224, 2, 50, 2, 59, ++ 170, 96, 171, 129, 35, 106, 181, 248, 14, 144, 26, 137, 25, 244, 0, ++ 89, 24, 191, 181, 248, 80, 144, 12, 42, 213, 248, 8, 128, 181, 248, ++ 12, 160, 13, 216, 179, 249, 8, 48, 79, 244, 40, 2, 154, 64, 7, 213, ++ 179, 136, 217, 5, 4, 213, 35, 244, 128, 115, 27, 4, 27, 12, 179, 128, ++ 179, 136, 19, 244, 68, 127, 64, 240, 146, 128, 212, 248, 8, 50, 195, ++ 177, 212, 248, 220, 6, 69, 240, 96, 218, 152, 177, 115, 138, 32, 70, ++ 19, 240, 1, 3, 49, 70, 42, 70, 2, 208, 6, 240, 98, 217, 1, 224, 246, ++ 247, 37, 254, 212, 248, 8, 50, 35, 177, 35, 104, 147, 248, 63, 48, 0, ++ 43, 124, 208, 51, 138, 218, 7, 114, 212, 209, 68, 185, 241, 7, 15, 5, ++ 217, 184, 248, 6, 144, 25, 244, 0, 111, 7, 209, 14, 224, 35, 104, 211, ++ 248, 136, 48, 90, 110, 1, 50, 90, 102, 97, 224, 35, 104, 211, 248, 136, ++ 48, 211, 248, 148, 33, 1, 50, 195, 248, 148, 33, 182, 248, 18, 160, ++ 26, 240, 1, 10, 33, 209, 9, 240, 12, 3, 155, 16, 2, 43, 0, 208, 187, ++ 185, 8, 241, 16, 0, 240, 247, 88, 248, 24, 185, 152, 248, 16, 48, 219, ++ 7, 6, 213, 35, 104, 211, 248, 136, 48, 90, 111, 1, 50, 90, 103, 62, ++ 224, 35, 104, 211, 248, 136, 48, 211, 248, 204, 33, 1, 50, 195, 248, ++ 204, 33, 212, 248, 48, 1, 5, 240, 204, 254, 171, 105, 19, 240, 128, ++ 3, 21, 209, 186, 241, 0, 15, 11, 208, 148, 248, 18, 34, 0, 42, 39, 208, ++ 212, 248, 48, 1, 49, 70, 42, 70, 189, 232, 240, 71, 5, 240, 203, 190, ++ 9, 240, 12, 9, 79, 234, 169, 9, 185, 241, 2, 15, 7, 209, 32, 70, 57, ++ 70, 50, 70, 43, 70, 189, 232, 240, 71, 255, 247, 222, 186, 185, 241, ++ 1, 15, 7, 216, 32, 70, 57, 70, 50, 70, 43, 70, 189, 232, 240, 71, 253, ++ 247, 247, 187, 35, 104, 211, 248, 136, 48, 26, 111, 1, 50, 26, 103, ++ 56, 70, 41, 70, 0, 34, 189, 232, 240, 71, 241, 247, 154, 191, 189, 232, ++ 240, 135, 56, 181, 5, 70, 0, 36, 213, 248, 104, 50, 83, 248, 36, 32, ++ 74, 177, 210, 248, 4, 49, 40, 70, 25, 120, 43, 25, 131, 248, 43, 24, ++ 0, 33, 251, 247, 224, 249, 1, 52, 8, 44, 237, 209, 56, 189, 56, 181, ++ 5, 70, 0, 36, 213, 248, 104, 50, 83, 248, 36, 32, 42, 177, 43, 25, 40, ++ 70, 147, 248, 43, 24, 251, 247, 206, 249, 1, 52, 8, 44, 241, 209, 56, ++ 189, 45, 233, 240, 67, 0, 35, 133, 176, 1, 147, 13, 155, 5, 70, 3, 43, ++ 22, 70, 14, 159, 221, 248, 60, 128, 4, 104, 4, 217, 1, 168, 12, 153, ++ 4, 34, 232, 247, 141, 255, 221, 248, 4, 144, 3, 46, 0, 242, 129, 128, ++ 223, 232, 6, 240, 2, 18, 58, 64, 4, 53, 40, 70, 234, 243, 180, 243, ++ 1, 48, 128, 69, 108, 217, 56, 70, 41, 70, 8, 241, 255, 50, 234, 243, ++ 215, 243, 45, 224, 1, 54, 0, 224, 0, 38, 70, 69, 2, 218, 187, 93, 0, ++ 43, 247, 209, 3, 46, 94, 220, 0, 33, 4, 34, 3, 168, 234, 243, 231, 242, ++ 3, 168, 57, 70, 50, 70, 234, 243, 194, 243, 0, 46, 85, 208, 32, 70, ++ 3, 169, 2, 170, 53, 240, 137, 222, 6, 70, 0, 40, 77, 209, 32, 70, 14, ++ 240, 88, 248, 0, 40, 75, 208, 40, 29, 3, 169, 3, 34, 234, 243, 174, ++ 243, 48, 70, 73, 224, 35, 104, 147, 248, 175, 48, 59, 96, 0, 32, 67, ++ 224, 32, 70, 14, 240, 70, 248, 0, 40, 57, 208, 212, 248, 104, 18, 0, ++ 35, 202, 88, 34, 177, 144, 121, 16, 185, 18, 122, 0, 42, 50, 209, 4, ++ 51, 32, 43, 245, 209, 51, 224, 131, 121, 19, 177, 4, 33, 80, 240, 48, ++ 219, 25, 241, 0, 3, 34, 104, 24, 191, 1, 35, 146, 248, 175, 128, 111, ++ 122, 130, 248, 175, 48, 107, 114, 43, 177, 212, 248, 92, 1, 41, 29, ++ 54, 240, 217, 219, 3, 224, 212, 248, 140, 1, 54, 240, 176, 223, 32, ++ 177, 35, 104, 131, 248, 175, 128, 111, 114, 15, 224, 40, 114, 13, 224, ++ 111, 240, 13, 0, 10, 224, 111, 240, 14, 0, 7, 224, 111, 240, 1, 0, 4, ++ 224, 111, 240, 22, 0, 1, 224, 111, 240, 27, 0, 5, 176, 189, 232, 240, ++ 131, 212, 248, 104, 1, 0, 40, 199, 209, 203, 231, 45, 233, 255, 65, ++ 145, 232, 12, 0, 82, 104, 4, 104, 210, 248, 4, 128, 0, 34, 141, 248, ++ 15, 32, 34, 104, 14, 70, 146, 248, 173, 32, 0, 42, 81, 208, 211, 248, ++ 204, 112, 23, 244, 128, 71, 76, 209, 96, 104, 57, 70, 30, 240, 39, 252, ++ 5, 70, 144, 177, 35, 106, 184, 248, 50, 16, 0, 151, 24, 105, 13, 241, ++ 15, 2, 43, 70, 20, 240, 106, 253, 40, 70, 30, 240, 26, 253, 41, 70, ++ 199, 178, 96, 104, 30, 240, 33, 252, 0, 224, 7, 70, 35, 106, 24, 105, ++ 21, 240, 205, 255, 5, 70, 212, 248, 92, 1, 53, 240, 215, 220, 16, 240, ++ 1, 15, 157, 248, 15, 48, 14, 208, 34, 106, 4, 51, 146, 248, 4, 33, 211, ++ 24, 237, 24, 109, 178, 0, 45, 184, 191, 3, 53, 173, 16, 141, 248, 12, ++ 80, 191, 24, 8, 224, 4, 51, 237, 24, 109, 178, 0, 45, 184, 191, 3, 53, ++ 173, 16, 141, 248, 12, 80, 127, 178, 0, 47, 184, 191, 3, 55, 191, 16, ++ 33, 32, 3, 169, 2, 34, 179, 105, 141, 248, 13, 112, 234, 243, 45, 247, ++ 0, 32, 4, 176, 189, 232, 240, 129, 16, 181, 68, 104, 12, 25, 224, 104, ++ 24, 177, 241, 247, 41, 254, 0, 35, 227, 96, 32, 70, 0, 33, 20, 34, 189, ++ 232, 16, 64, 234, 243, 3, 178, 64, 104, 8, 181, 8, 24, 20, 34, 0, 33, ++ 234, 243, 252, 241, 0, 32, 8, 189, 56, 181, 3, 104, 76, 104, 27, 104, ++ 147, 248, 176, 48, 91, 177, 69, 104, 96, 89, 72, 177, 32, 70, 107, 33, ++ 46, 240, 202, 222, 96, 81, 24, 177, 64, 120, 2, 48, 56, 189, 24, 70, ++ 56, 189, 0, 0, 248, 181, 20, 70, 57, 179, 50, 179, 13, 125, 21, 240, ++ 1, 5, 34, 209, 147, 127, 35, 240, 15, 3, 67, 240, 12, 3, 147, 119, 6, ++ 104, 142, 25, 1, 224, 37, 70, 60, 70, 12, 75, 226, 138, 27, 104, 83, ++ 248, 34, 112, 0, 35, 227, 130, 243, 137, 1, 51, 243, 129, 227, 137, ++ 3, 240, 7, 3, 4, 59, 3, 43, 2, 216, 238, 243, 199, 243, 112, 97, 13, ++ 177, 35, 136, 235, 130, 0, 47, 229, 209, 248, 189, 32, 7, 0, 0, 248, ++ 181, 22, 70, 208, 248, 136, 38, 1, 43, 5, 70, 12, 70, 82, 104, 65, 221, ++ 3, 104, 91, 107, 59, 177, 209, 248, 204, 48, 3, 240, 2, 3, 0, 43, 12, ++ 191, 3, 35, 0, 35, 155, 0, 219, 178, 51, 112, 161, 121, 73, 177, 180, ++ 248, 90, 16, 73, 6, 5, 213, 162, 92, 1, 42, 4, 191, 67, 240, 1, 3, 51, ++ 112, 0, 35, 115, 112, 213, 248, 100, 6, 33, 109, 55, 120, 68, 240, 225, ++ 223, 56, 67, 48, 112, 43, 104, 147, 248, 102, 49, 107, 177, 180, 248, ++ 90, 48, 155, 6, 9, 213, 213, 248, 80, 8, 33, 70, 34, 240, 106, 252, ++ 24, 177, 51, 120, 99, 240, 63, 3, 51, 112, 212, 248, 204, 0, 16, 244, ++ 0, 0, 8, 208, 115, 120, 0, 32, 67, 240, 2, 3, 48, 112, 115, 112, 248, ++ 189, 79, 240, 255, 48, 248, 189, 45, 233, 248, 79, 177, 248, 90, 160, ++ 131, 70, 80, 70, 13, 70, 20, 70, 152, 70, 15, 109, 235, 243, 78, 246, ++ 0, 40, 0, 240, 197, 128, 64, 242, 55, 19, 59, 64, 0, 43, 0, 240, 191, ++ 128, 213, 248, 244, 48, 147, 249, 52, 48, 0, 43, 56, 209, 184, 241, ++ 23, 15, 64, 243, 181, 128, 24, 34, 32, 70, 91, 73, 232, 247, 196, 253, ++ 120, 7, 11, 213, 213, 248, 244, 48, 147, 248, 112, 32, 4, 42, 3, 208, ++ 147, 248, 132, 48, 4, 43, 1, 209, 4, 35, 20, 224, 185, 7, 1, 213, 2, ++ 35, 16, 224, 171, 110, 90, 28, 12, 208, 5, 235, 131, 3, 219, 110, 67, ++ 177, 27, 122, 1, 43, 6, 208, 3, 43, 1, 209, 5, 35, 2, 224, 4, 43, 0, ++ 208, 1, 35, 99, 116, 227, 114, 0, 35, 227, 117, 41, 70, 88, 70, 4, 241, ++ 24, 2, 2, 35, 255, 247, 96, 255, 22, 37, 125, 224, 184, 241, 13, 15, ++ 124, 221, 221, 35, 32, 70, 3, 34, 0, 248, 2, 59, 62, 73, 232, 247, 137, ++ 253, 79, 240, 1, 9, 0, 35, 227, 113, 3, 34, 58, 73, 132, 248, 5, 144, ++ 132, 248, 6, 144, 4, 241, 8, 0, 232, 247, 123, 253, 88, 70, 41, 70, ++ 23, 240, 187, 216, 23, 240, 4, 3, 168, 241, 14, 6, 224, 114, 13, 208, ++ 3, 46, 90, 221, 4, 241, 14, 0, 47, 73, 3, 34, 232, 247, 105, 253, 4, ++ 35, 99, 116, 168, 241, 18, 6, 16, 37, 1, 224, 153, 70, 12, 37, 184, ++ 7, 18, 213, 3, 46, 72, 221, 79, 234, 137, 7, 224, 25, 14, 48, 37, 73, ++ 3, 34, 232, 247, 85, 253, 231, 25, 2, 35, 9, 241, 1, 9, 123, 116, 31, ++ 250, 137, 249, 4, 53, 4, 62, 0, 35, 1, 46, 132, 248, 12, 144, 99, 115, ++ 49, 221, 4, 241, 12, 3, 3, 235, 137, 9, 179, 30, 26, 240, 2, 2, 9, 241, ++ 2, 7, 1, 209, 2, 53, 10, 224, 3, 43, 35, 221, 3, 34, 184, 28, 19, 73, ++ 232, 247, 51, 253, 1, 34, 122, 113, 6, 53, 179, 31, 26, 240, 4, 15, ++ 22, 70, 15, 208, 3, 43, 20, 221, 7, 235, 130, 8, 8, 241, 2, 0, 11, 73, ++ 3, 34, 232, 247, 33, 253, 1, 54, 2, 35, 136, 248, 5, 48, 182, 178, 4, ++ 53, 0, 35, 137, 248, 2, 96, 123, 112, 101, 112, 2, 53, 100, 25, 32, ++ 70, 189, 232, 248, 143, 0, 191, 188, 53, 4, 0, 26, 21, 4, 0, 45, 233, ++ 240, 79, 177, 248, 90, 176, 133, 176, 20, 70, 10, 109, 2, 144, 88, 70, ++ 1, 145, 30, 70, 0, 146, 239, 247, 88, 255, 0, 40, 0, 240, 7, 129, 0, ++ 154, 64, 242, 55, 19, 19, 64, 0, 43, 0, 240, 0, 129, 9, 46, 64, 243, ++ 253, 128, 48, 35, 35, 112, 1, 35, 163, 112, 3, 34, 0, 35, 187, 245, ++ 0, 95, 166, 241, 10, 9, 227, 112, 122, 73, 4, 241, 4, 0, 4, 209, 232, ++ 247, 224, 252, 7, 35, 227, 113, 6, 224, 232, 247, 219, 252, 2, 152, ++ 1, 153, 23, 240, 27, 216, 224, 113, 0, 155, 19, 240, 4, 5, 17, 208, ++ 185, 241, 3, 15, 64, 243, 218, 128, 4, 241, 10, 0, 109, 73, 3, 34, 232, ++ 247, 200, 252, 4, 35, 99, 115, 166, 241, 14, 9, 1, 37, 79, 240, 12, ++ 10, 1, 224, 79, 240, 8, 10, 0, 154, 144, 7, 19, 213, 185, 241, 3, 15, ++ 64, 243, 195, 128, 174, 0, 160, 25, 10, 48, 97, 73, 3, 34, 232, 247, ++ 176, 252, 166, 25, 2, 35, 1, 53, 115, 115, 173, 178, 10, 241, 4, 10, ++ 169, 241, 4, 9, 0, 35, 185, 241, 1, 15, 37, 114, 99, 114, 64, 243, 172, ++ 128, 4, 241, 8, 2, 2, 235, 133, 2, 151, 28, 27, 240, 64, 6, 3, 146, ++ 10, 241, 2, 8, 169, 241, 2, 5, 44, 208, 0, 154, 81, 5, 14, 212, 3, 45, ++ 64, 243, 153, 128, 184, 28, 77, 73, 3, 34, 1, 38, 232, 247, 135, 252, ++ 10, 241, 6, 8, 126, 113, 169, 241, 6, 5, 0, 224, 30, 70, 0, 155, 19, ++ 244, 64, 111, 2, 209, 27, 244, 128, 95, 18, 208, 3, 45, 64, 243, 130, ++ 128, 7, 235, 134, 9, 9, 241, 2, 0, 64, 73, 3, 34, 232, 247, 110, 252, ++ 1, 54, 5, 35, 137, 248, 5, 48, 182, 178, 8, 241, 4, 8, 4, 61, 27, 240, ++ 128, 15, 45, 208, 0, 154, 82, 5, 17, 212, 3, 45, 105, 221, 7, 235, 134, ++ 9, 9, 241, 2, 0, 52, 73, 3, 34, 232, 247, 86, 252, 1, 54, 2, 35, 137, ++ 248, 5, 48, 182, 178, 8, 241, 4, 8, 4, 61, 0, 155, 19, 244, 64, 111, ++ 2, 209, 27, 244, 0, 79, 17, 208, 3, 45, 80, 221, 7, 235, 134, 9, 9, ++ 241, 2, 0, 40, 73, 3, 34, 232, 247, 61, 252, 1, 54, 6, 35, 137, 248, ++ 5, 48, 182, 178, 8, 241, 4, 8, 4, 61, 27, 244, 0, 95, 17, 208, 3, 45, ++ 59, 221, 7, 235, 134, 9, 9, 241, 2, 0, 29, 73, 3, 34, 232, 247, 40, ++ 252, 1, 54, 7, 35, 137, 248, 5, 48, 182, 178, 8, 241, 4, 8, 4, 61, 3, ++ 155, 79, 240, 0, 9, 1, 45, 158, 112, 135, 248, 1, 144, 35, 221, 7, 235, ++ 134, 6, 183, 28, 58, 70, 2, 35, 2, 152, 1, 153, 255, 247, 217, 253, ++ 0, 154, 147, 5, 2, 212, 8, 241, 2, 8, 15, 224, 3, 45, 18, 221, 184, ++ 28, 2, 34, 73, 70, 233, 243, 130, 247, 7, 45, 11, 221, 176, 29, 8, 73, ++ 4, 34, 232, 247, 251, 251, 8, 241, 8, 8, 132, 248, 1, 128, 8, 241, 2, ++ 8, 68, 68, 32, 70, 5, 176, 189, 232, 240, 143, 34, 21, 4, 0, 38, 21, ++ 4, 0, 45, 233, 247, 79, 145, 248, 1, 128, 1, 144, 184, 241, 1, 15, 13, ++ 70, 20, 70, 64, 243, 246, 128, 202, 120, 139, 120, 67, 234, 2, 35, 1, ++ 43, 64, 240, 239, 128, 4, 34, 184, 241, 5, 15, 132, 248, 131, 48, 132, ++ 248, 132, 32, 132, 248, 133, 48, 132, 248, 134, 32, 132, 248, 138, 48, ++ 132, 248, 139, 48, 64, 243, 225, 128, 136, 24, 113, 73, 3, 34, 232, ++ 247, 177, 251, 88, 185, 235, 121, 1, 43, 6, 217, 7, 43, 6, 216, 90, ++ 178, 79, 240, 116, 81, 145, 64, 1, 213, 132, 248, 132, 48, 184, 241, ++ 7, 15, 64, 243, 203, 128, 149, 248, 9, 160, 43, 122, 0, 38, 67, 234, ++ 10, 42, 168, 241, 8, 8, 55, 70, 28, 224, 5, 241, 8, 9, 9, 235, 135, ++ 9, 9, 241, 2, 0, 95, 73, 3, 34, 232, 247, 140, 251, 112, 185, 153, 248, ++ 5, 48, 1, 43, 6, 217, 7, 43, 8, 216, 90, 178, 79, 240, 116, 81, 145, ++ 64, 3, 213, 162, 25, 130, 248, 134, 48, 1, 54, 1, 55, 168, 241, 4, 8, ++ 87, 69, 4, 210, 3, 46, 2, 216, 184, 241, 3, 15, 219, 220, 199, 235, ++ 10, 7, 191, 0, 199, 235, 8, 8, 184, 241, 1, 15, 132, 248, 133, 96, 64, ++ 243, 146, 128, 8, 53, 5, 235, 138, 5, 5, 241, 2, 11, 171, 120, 155, ++ 248, 1, 160, 0, 37, 67, 234, 10, 42, 168, 241, 2, 8, 46, 70, 63, 224, ++ 11, 235, 134, 9, 9, 241, 2, 7, 56, 70, 64, 73, 3, 34, 232, 247, 79, ++ 251, 104, 187, 153, 248, 5, 48, 90, 30, 210, 178, 1, 42, 34, 217, 218, ++ 30, 210, 178, 1, 42, 8, 216, 98, 25, 130, 248, 139, 48, 148, 248, 131, ++ 48, 1, 53, 67, 240, 4, 3, 11, 224, 90, 31, 210, 178, 1, 42, 10, 216, ++ 98, 25, 130, 248, 139, 48, 148, 248, 131, 48, 1, 53, 67, 240, 32, 3, ++ 132, 248, 131, 48, 16, 224, 1, 153, 10, 104, 146, 248, 102, 33, 90, ++ 177, 8, 43, 9, 209, 98, 25, 130, 248, 139, 48, 1, 53, 4, 224, 56, 70, ++ 39, 73, 3, 34, 232, 247, 27, 251, 1, 54, 168, 241, 4, 8, 86, 69, 4, ++ 210, 3, 45, 2, 216, 184, 241, 3, 15, 184, 220, 198, 235, 10, 6, 227, ++ 136, 182, 0, 198, 235, 8, 8, 67, 240, 128, 3, 184, 241, 1, 15, 132, ++ 248, 138, 80, 227, 128, 45, 221, 11, 235, 138, 5, 170, 120, 171, 28, ++ 210, 7, 5, 213, 148, 248, 131, 32, 66, 240, 2, 2, 132, 248, 131, 32, ++ 91, 120, 158, 7, 5, 213, 148, 248, 131, 48, 67, 240, 64, 3, 132, 248, ++ 131, 48, 1, 155, 169, 120, 211, 248, 100, 6, 148, 248, 131, 96, 68, ++ 240, 175, 219, 6, 67, 132, 248, 131, 96, 171, 120, 184, 241, 2, 15, ++ 132, 248, 147, 48, 7, 208, 102, 240, 127, 6, 132, 248, 131, 96, 2, 224, ++ 111, 240, 22, 0, 0, 224, 0, 32, 189, 232, 254, 143, 0, 191, 34, 21, ++ 4, 0, 30, 21, 4, 0, 45, 233, 247, 79, 29, 70, 146, 248, 1, 128, 20, ++ 70, 170, 104, 177, 248, 90, 48, 34, 244, 192, 98, 184, 241, 1, 15, 7, ++ 70, 14, 70, 0, 147, 170, 96, 64, 242, 203, 128, 148, 248, 3, 192, 162, ++ 120, 66, 234, 12, 34, 1, 42, 64, 240, 195, 128, 168, 241, 2, 2, 210, ++ 178, 3, 42, 14, 216, 90, 6, 64, 241, 187, 128, 4, 34, 26, 240, 184, ++ 217, 0, 40, 0, 240, 181, 128, 64, 35, 165, 248, 68, 48, 4, 35, 171, ++ 100, 172, 224, 4, 241, 4, 9, 72, 70, 88, 73, 3, 34, 232, 247, 151, 250, ++ 130, 70, 0, 40, 64, 240, 164, 128, 56, 70, 49, 70, 226, 121, 26, 240, ++ 159, 217, 0, 40, 0, 240, 156, 128, 5, 241, 72, 11, 72, 70, 89, 70, 235, ++ 243, 202, 242, 168, 241, 6, 3, 219, 178, 1, 43, 18, 216, 0, 155, 91, ++ 6, 64, 241, 141, 128, 56, 70, 49, 70, 4, 34, 26, 240, 136, 217, 0, 40, ++ 0, 240, 133, 128, 64, 35, 165, 248, 68, 48, 4, 35, 171, 100, 80, 70, ++ 128, 224, 98, 122, 35, 122, 67, 234, 2, 35, 1, 43, 119, 209, 4, 241, ++ 10, 9, 72, 70, 61, 73, 3, 34, 232, 247, 96, 250, 0, 40, 110, 209, 56, ++ 70, 49, 70, 98, 123, 26, 240, 106, 217, 0, 40, 103, 208, 72, 70, 89, ++ 70, 235, 243, 152, 242, 168, 241, 12, 3, 219, 178, 1, 43, 6, 216, 0, ++ 155, 88, 6, 91, 213, 64, 35, 165, 248, 68, 48, 85, 224, 226, 123, 163, ++ 123, 67, 234, 2, 35, 1, 43, 81, 209, 4, 241, 16, 0, 42, 73, 3, 34, 232, ++ 247, 59, 250, 0, 40, 73, 209, 227, 124, 1, 43, 1, 208, 5, 43, 2, 209, ++ 0, 154, 81, 6, 6, 212, 6, 43, 1, 208, 2, 43, 61, 209, 0, 154, 18, 6, ++ 58, 213, 5, 59, 219, 178, 1, 43, 10, 216, 51, 109, 88, 5, 3, 212, 0, ++ 155, 19, 244, 16, 79, 49, 208, 171, 104, 67, 244, 128, 99, 171, 96, ++ 51, 109, 89, 5, 2, 213, 171, 104, 90, 5, 39, 213, 4, 241, 16, 0, 105, ++ 70, 0, 34, 239, 247, 224, 251, 240, 177, 189, 248, 0, 48, 168, 241, ++ 18, 8, 95, 250, 136, 248, 184, 241, 1, 15, 165, 248, 68, 48, 136, 191, ++ 34, 125, 215, 248, 100, 6, 152, 191, 0, 34, 49, 109, 13, 241, 7, 3, ++ 18, 240, 171, 254, 80, 177, 157, 248, 7, 0, 64, 177, 171, 104, 67, 244, ++ 0, 115, 171, 96, 0, 32, 2, 224, 12, 32, 0, 224, 31, 32, 189, 232, 254, ++ 143, 0, 191, 34, 21, 4, 0, 248, 181, 28, 70, 83, 120, 7, 70, 227, 112, ++ 0, 35, 99, 114, 11, 109, 14, 70, 91, 7, 21, 70, 6, 213, 16, 70, 4, 33, ++ 92, 240, 2, 217, 8, 177, 4, 35, 60, 224, 51, 109, 152, 7, 6, 213, 40, ++ 70, 2, 33, 92, 240, 248, 216, 8, 177, 2, 35, 50, 224, 182, 248, 90, ++ 48, 25, 7, 47, 213, 40, 70, 9, 33, 92, 240, 237, 216, 8, 177, 9, 35, ++ 26, 224, 40, 70, 8, 33, 92, 240, 230, 216, 8, 177, 8, 35, 19, 224, 40, ++ 70, 10, 33, 92, 240, 223, 216, 8, 177, 10, 35, 12, 224, 40, 70, 5, 33, ++ 92, 240, 216, 216, 8, 177, 5, 35, 5, 224, 40, 70, 1, 33, 92, 240, 209, ++ 216, 8, 177, 1, 35, 99, 114, 99, 122, 8, 59, 219, 178, 2, 43, 7, 216, ++ 160, 29, 44, 73, 3, 34, 232, 247, 172, 249, 99, 122, 8, 59, 99, 114, ++ 182, 248, 90, 48, 154, 7, 20, 212, 88, 7, 39, 212, 89, 6, 18, 213, 90, ++ 4, 4, 213, 43, 120, 91, 7, 1, 213, 3, 35, 51, 224, 51, 109, 24, 5, 4, ++ 212, 40, 70, 5, 33, 92, 240, 155, 216, 8, 177, 5, 35, 41, 224, 1, 35, ++ 39, 224, 25, 6, 18, 213, 90, 4, 4, 213, 43, 120, 91, 7, 1, 213, 4, 35, ++ 30, 224, 51, 109, 24, 5, 4, 212, 40, 70, 6, 33, 92, 240, 134, 216, 8, ++ 177, 6, 35, 20, 224, 2, 35, 18, 224, 58, 104, 146, 248, 102, 33, 26, ++ 177, 153, 6, 1, 213, 8, 35, 10, 224, 8, 43, 1, 208, 16, 43, 7, 209, ++ 4, 241, 12, 0, 10, 73, 3, 34, 232, 247, 103, 249, 0, 35, 227, 115, 4, ++ 241, 16, 2, 2, 35, 56, 70, 49, 70, 255, 247, 40, 251, 43, 124, 34, 124, ++ 67, 240, 127, 3, 19, 64, 35, 116, 248, 189, 0, 191, 30, 21, 4, 0, 45, ++ 233, 247, 79, 177, 248, 90, 160, 221, 248, 48, 176, 26, 244, 128, 71, ++ 24, 191, 146, 248, 131, 112, 5, 70, 24, 191, 199, 243, 128, 7, 12, 70, ++ 145, 70, 30, 70, 221, 248, 52, 128, 255, 178, 187, 241, 0, 15, 24, 208, ++ 15, 177, 11, 177, 21, 224, 19, 185, 202, 243, 0, 26, 1, 224, 79, 240, ++ 1, 10, 186, 241, 0, 15, 5, 208, 40, 70, 89, 70, 18, 240, 62, 223, 79, ++ 240, 1, 10, 88, 70, 65, 70, 233, 243, 92, 247, 223, 177, 0, 39, 21, ++ 224, 65, 70, 28, 72, 233, 243, 85, 247, 40, 70, 33, 70, 9, 241, 131, ++ 2, 8, 241, 4, 3, 255, 247, 29, 255, 87, 177, 0, 46, 38, 208, 213, 248, ++ 192, 6, 33, 70, 56, 240, 177, 220, 7, 70, 32, 224, 22, 185, 20, 224, ++ 79, 240, 1, 10, 180, 248, 90, 0, 239, 247, 65, 251, 104, 177, 186, 241, ++ 0, 15, 10, 208, 180, 248, 90, 48, 213, 248, 200, 6, 1, 147, 33, 70, ++ 74, 70, 67, 70, 0, 151, 29, 240, 105, 252, 213, 248, 192, 6, 33, 70, ++ 74, 70, 3, 176, 189, 232, 240, 79, 56, 240, 57, 158, 55, 70, 79, 240, ++ 1, 10, 219, 231, 0, 191, 74, 195, 135, 0, 144, 248, 116, 2, 0, 240, ++ 2, 0, 208, 241, 1, 0, 56, 191, 0, 32, 112, 71, 48, 181, 141, 104, 67, ++ 104, 44, 5, 203, 88, 12, 213, 177, 248, 114, 64, 34, 9, 2, 240, 3, 2, ++ 3, 58, 24, 191, 1, 34, 164, 8, 4, 240, 3, 4, 3, 60, 7, 224, 145, 248, ++ 99, 32, 145, 248, 98, 64, 0, 50, 24, 191, 1, 34, 0, 52, 73, 104, 24, ++ 191, 1, 36, 201, 5, 10, 213, 105, 7, 8, 212, 66, 185, 2, 104, 18, 104, ++ 210, 105, 82, 105, 11, 42, 168, 191, 11, 34, 13, 224, 34, 177, 2, 104, ++ 18, 104, 210, 105, 146, 105, 7, 224, 2, 104, 18, 104, 210, 105, 12, ++ 177, 82, 105, 1, 224, 210, 248, 188, 32, 90, 113, 90, 121, 0, 241, 208, ++ 1, 128, 248, 222, 35, 2, 70, 178, 248, 240, 66, 180, 245, 122, 127, ++ 132, 191, 144, 248, 222, 67, 92, 113, 52, 50, 138, 66, 244, 209, 144, ++ 248, 40, 32, 81, 178, 1, 49, 24, 191, 90, 113, 89, 121, 144, 248, 226, ++ 35, 145, 66, 56, 191, 10, 70, 217, 104, 154, 113, 57, 177, 79, 244, ++ 200, 100, 177, 251, 244, 241, 138, 66, 40, 191, 10, 70, 154, 113, 153, ++ 121, 144, 248, 61, 35, 145, 66, 56, 191, 10, 70, 154, 113, 48, 189, ++ 48, 181, 0, 34, 52, 33, 81, 67, 0, 36, 1, 245, 60, 113, 67, 24, 68, ++ 82, 0, 33, 92, 24, 1, 49, 255, 37, 31, 41, 165, 112, 249, 209, 1, 50, ++ 0, 33, 4, 42, 25, 99, 153, 98, 89, 132, 89, 98, 233, 209, 48, 189, 128, ++ 248, 196, 19, 112, 71, 208, 248, 0, 50, 90, 104, 192, 248, 0, 34, 0, ++ 34, 90, 96, 24, 70, 112, 71, 208, 248, 4, 50, 35, 185, 79, 240, 255, ++ 50, 10, 128, 24, 70, 112, 71, 26, 136, 10, 128, 90, 104, 208, 248, 0, ++ 18, 89, 96, 192, 248, 0, 50, 192, 248, 4, 34, 1, 32, 112, 71, 112, 181, ++ 4, 70, 13, 70, 22, 70, 255, 247, 221, 255, 212, 248, 4, 50, 0, 34, 5, ++ 128, 14, 224, 25, 136, 141, 66, 4, 217, 105, 26, 137, 178, 177, 66, ++ 4, 217, 8, 224, 73, 27, 137, 178, 177, 66, 4, 217, 89, 104, 26, 70, ++ 11, 70, 0, 43, 238, 209, 18, 185, 196, 248, 4, 2, 0, 224, 80, 96, 67, ++ 96, 112, 189, 247, 181, 79, 240, 255, 51, 12, 70, 209, 248, 244, 96, ++ 143, 120, 131, 131, 2, 169, 0, 35, 5, 70, 33, 248, 2, 61, 4, 241, 252, ++ 0, 255, 247, 184, 255, 48, 177, 189, 248, 6, 48, 1, 32, 67, 244, 128, ++ 83, 171, 131, 10, 224, 96, 55, 6, 235, 71, 6, 242, 136, 19, 5, 27, 13, ++ 1, 50, 171, 131, 242, 128, 164, 248, 92, 48, 254, 189, 3, 104, 27, 104, ++ 147, 248, 156, 48, 1, 43, 17, 209, 36, 35, 3, 251, 1, 1, 177, 248, 92, ++ 50, 177, 248, 94, 2, 131, 66, 195, 235, 0, 0, 1, 210, 1, 56, 112, 71, ++ 145, 248, 98, 50, 1, 59, 24, 24, 112, 71, 0, 32, 112, 71, 45, 233, 240, ++ 65, 23, 70, 10, 104, 4, 70, 210, 248, 248, 48, 14, 70, 11, 185, 19, ++ 105, 219, 104, 221, 104, 79, 244, 0, 114, 41, 70, 32, 70, 248, 247, ++ 70, 249, 35, 104, 241, 138, 183, 248, 84, 32, 219, 105, 138, 24, 91, ++ 107, 40, 177, 154, 66, 14, 220, 32, 70, 41, 70, 0, 34, 4, 224, 154, ++ 66, 8, 219, 32, 70, 41, 70, 1, 34, 79, 244, 0, 115, 189, 232, 240, 65, ++ 248, 247, 173, 185, 189, 232, 240, 129, 31, 181, 3, 104, 4, 70, 1, 169, ++ 211, 248, 36, 1, 0, 34, 80, 240, 142, 218, 5, 224, 75, 104, 91, 3, 2, ++ 213, 32, 70, 255, 247, 190, 254, 35, 104, 1, 169, 211, 248, 36, 1, 34, ++ 240, 41, 255, 1, 70, 0, 40, 240, 209, 31, 189, 48, 181, 3, 104, 133, ++ 176, 4, 70, 1, 169, 211, 248, 36, 1, 0, 34, 80, 240, 115, 218, 0, 37, ++ 6, 224, 67, 104, 90, 3, 3, 213, 99, 104, 195, 88, 219, 138, 237, 24, ++ 35, 104, 1, 169, 211, 248, 36, 1, 34, 240, 12, 255, 0, 40, 240, 209, ++ 40, 70, 5, 176, 48, 189, 147, 105, 112, 181, 91, 5, 5, 70, 57, 213, ++ 0, 41, 55, 208, 75, 104, 91, 3, 52, 213, 67, 104, 203, 88, 209, 137, ++ 1, 240, 7, 1, 54, 49, 83, 248, 33, 64, 0, 44, 42, 208, 3, 104, 150, ++ 139, 152, 104, 255, 243, 84, 244, 54, 5, 54, 13, 1, 7, 16, 213, 180, ++ 248, 84, 48, 4, 241, 252, 0, 1, 59, 164, 248, 84, 48, 49, 70, 98, 120, ++ 255, 247, 17, 255, 180, 248, 248, 48, 1, 51, 164, 248, 248, 48, 112, ++ 189, 149, 248, 225, 83, 4, 241, 67, 0, 1, 61, 53, 64, 41, 70, 234, 243, ++ 94, 241, 48, 177, 4, 241, 75, 0, 41, 70, 189, 232, 112, 64, 234, 243, ++ 126, 180, 112, 189, 16, 181, 79, 244, 0, 114, 0, 33, 4, 70, 233, 243, ++ 172, 242, 0, 34, 1, 35, 4, 235, 195, 0, 1, 51, 161, 24, 8, 50, 64, 43, ++ 72, 96, 247, 209, 0, 35, 196, 248, 0, 66, 196, 248, 4, 50, 16, 189, ++ 248, 181, 36, 35, 83, 67, 3, 245, 22, 118, 132, 25, 5, 70, 0, 104, 226, ++ 122, 3, 104, 147, 248, 156, 48, 1, 43, 27, 209, 163, 136, 180, 248, ++ 2, 192, 0, 42, 20, 191, 79, 244, 128, 66, 0, 34, 156, 69, 231, 136, ++ 1, 209, 174, 91, 1, 224, 94, 28, 182, 178, 190, 66, 27, 208, 10, 67, ++ 146, 178, 89, 0, 22, 240, 128, 218, 166, 128, 40, 104, 33, 137, 50, ++ 70, 22, 240, 122, 218, 213, 248, 80, 50, 0, 32, 211, 248, 152, 32, 1, ++ 50, 195, 248, 152, 32, 211, 248, 160, 32, 1, 50, 195, 248, 160, 32, ++ 227, 105, 1, 51, 227, 97, 248, 189, 79, 240, 255, 48, 248, 189, 45, ++ 233, 247, 79, 146, 248, 241, 48, 4, 70, 22, 70, 0, 43, 71, 208, 208, ++ 248, 52, 49, 211, 248, 252, 83, 0, 45, 65, 208, 224, 33, 18, 240, 203, ++ 219, 234, 33, 131, 70, 32, 70, 18, 240, 198, 219, 226, 33, 130, 70, ++ 32, 70, 18, 240, 193, 219, 79, 244, 141, 113, 129, 70, 32, 70, 18, 240, ++ 187, 219, 79, 244, 154, 113, 128, 70, 32, 70, 18, 240, 181, 219, 79, ++ 244, 136, 113, 7, 70, 32, 70, 18, 240, 175, 219, 64, 242, 218, 97, 3, ++ 70, 32, 70, 1, 147, 18, 240, 168, 219, 32, 70, 79, 244, 219, 97, 18, ++ 240, 163, 219, 150, 248, 241, 32, 1, 155, 1, 42, 6, 217, 226, 104, 178, ++ 248, 70, 21, 178, 248, 104, 21, 178, 248, 34, 37, 165, 248, 0, 176, ++ 165, 248, 2, 160, 165, 248, 4, 144, 165, 248, 6, 128, 47, 129, 107, ++ 129, 232, 96, 189, 232, 254, 143, 0, 35, 45, 233, 240, 65, 5, 70, 12, ++ 70, 11, 112, 11, 224, 212, 248, 244, 16, 163, 120, 209, 248, 52, 1, ++ 15, 79, 3, 240, 7, 3, 70, 109, 251, 92, 128, 109, 176, 71, 5, 241, 16, ++ 0, 161, 120, 234, 243, 114, 242, 2, 70, 0, 40, 235, 209, 213, 248, 56, ++ 49, 42, 104, 24, 104, 210, 248, 248, 48, 11, 185, 19, 105, 219, 104, ++ 217, 104, 0, 34, 79, 244, 0, 115, 189, 232, 240, 65, 248, 247, 96, 184, ++ 72, 194, 135, 0, 56, 181, 208, 248, 0, 68, 13, 70, 225, 66, 5, 208, ++ 8, 89, 24, 177, 240, 247, 241, 253, 0, 35, 43, 81, 56, 189, 0, 181, ++ 143, 176, 1, 170, 244, 247, 47, 249, 189, 248, 52, 0, 15, 176, 0, 189, ++ 45, 233, 240, 79, 178, 248, 2, 128, 143, 176, 7, 70, 13, 70, 22, 70, ++ 4, 104, 178, 248, 4, 176, 8, 240, 7, 8, 79, 240, 0, 9, 44, 224, 32, ++ 70, 41, 70, 1, 170, 244, 247, 22, 249, 215, 248, 80, 50, 96, 104, 154, ++ 110, 41, 70, 1, 50, 154, 102, 1, 34, 189, 248, 10, 160, 240, 247, 247, ++ 253, 35, 104, 147, 248, 156, 32, 1, 42, 4, 208, 10, 244, 192, 106, 186, ++ 245, 192, 111, 8, 224, 9, 241, 1, 9, 32, 70, 65, 70, 31, 250, 137, 249, ++ 247, 247, 205, 252, 217, 69, 9, 208, 99, 105, 2, 33, 83, 248, 40, 0, ++ 18, 75, 219, 107, 152, 71, 5, 70, 0, 45, 208, 209, 35, 104, 147, 248, ++ 156, 48, 1, 43, 5, 208, 32, 70, 65, 70, 151, 248, 46, 32, 247, 247, ++ 182, 252, 150, 249, 25, 48, 59, 185, 12, 224, 1, 61, 1, 32, 237, 178, ++ 237, 243, 227, 244, 13, 185, 5, 224, 11, 37, 227, 104, 211, 248, 112, ++ 49, 218, 7, 242, 213, 15, 176, 189, 232, 240, 143, 208, 134, 135, 0, ++ 52, 35, 75, 67, 45, 233, 240, 65, 3, 245, 60, 115, 197, 24, 105, 126, ++ 144, 249, 222, 35, 79, 244, 225, 102, 145, 66, 184, 191, 10, 70, 210, ++ 178, 114, 67, 27, 79, 193, 90, 215, 248, 208, 97, 100, 35, 81, 26, 182, ++ 251, 243, 246, 78, 67, 182, 251, 242, 246, 94, 67, 79, 240, 255, 52, ++ 46, 99, 246, 9, 23, 44, 4, 208, 1, 52, 102, 44, 2, 221, 189, 232, 240, ++ 129, 87, 36, 20, 35, 3, 251, 4, 115, 91, 104, 219, 9, 179, 66, 240, ++ 217, 181, 248, 0, 128, 79, 244, 225, 98, 3, 251, 8, 248, 155, 27, 83, ++ 67, 32, 70, 184, 251, 243, 248, 25, 240, 207, 220, 8, 241, 1, 8, 40, ++ 24, 184, 241, 255, 15, 40, 191, 79, 240, 255, 8, 128, 248, 2, 128, 216, ++ 231, 172, 240, 135, 0, 45, 233, 247, 79, 79, 240, 52, 8, 8, 251, 1, ++ 248, 15, 70, 73, 0, 236, 49, 208, 248, 52, 81, 6, 70, 18, 240, 142, ++ 218, 8, 245, 60, 120, 5, 235, 8, 4, 180, 248, 34, 160, 202, 235, 0, ++ 10, 31, 250, 138, 250, 186, 241, 0, 15, 0, 240, 136, 128, 213, 248, ++ 236, 50, 96, 132, 0, 43, 0, 240, 133, 128, 7, 241, 220, 3, 106, 107, ++ 54, 248, 19, 48, 214, 248, 84, 150, 1, 146, 9, 251, 3, 242, 1, 152, ++ 130, 66, 119, 217, 50, 104, 146, 248, 156, 32, 1, 42, 9, 209, 48, 70, ++ 250, 33, 213, 248, 80, 178, 0, 147, 18, 240, 97, 218, 0, 155, 203, 248, ++ 0, 0, 213, 248, 80, 34, 225, 106, 16, 104, 98, 106, 82, 68, 9, 42, 98, ++ 98, 97, 217, 65, 26, 213, 248, 236, 98, 177, 251, 242, 242, 178, 66, ++ 8, 217, 65, 242, 135, 51, 153, 66, 79, 240, 0, 3, 86, 217, 224, 98, ++ 99, 98, 83, 224, 149, 248, 222, 195, 98, 126, 79, 250, 140, 246, 178, ++ 66, 184, 191, 22, 70, 246, 178, 79, 244, 225, 106, 10, 251, 6, 246, ++ 53, 248, 8, 16, 177, 66, 1, 219, 224, 98, 54, 224, 9, 251, 3, 243, 1, ++ 152, 27, 26, 155, 178, 153, 66, 25, 210, 1, 245, 122, 113, 137, 178, ++ 153, 66, 56, 191, 11, 70, 37, 248, 8, 48, 40, 70, 255, 247, 119, 253, ++ 24, 74, 53, 248, 8, 16, 210, 248, 208, 33, 100, 35, 113, 26, 178, 251, ++ 243, 242, 74, 67, 178, 251, 246, 246, 115, 67, 35, 99, 17, 224, 1, 42, ++ 15, 217, 255, 42, 4, 209, 12, 241, 255, 60, 132, 248, 25, 192, 1, 224, ++ 1, 58, 98, 118, 40, 70, 57, 70, 255, 247, 28, 255, 40, 70, 255, 247, ++ 86, 253, 213, 248, 80, 50, 27, 104, 227, 98, 0, 32, 96, 98, 7, 224, ++ 79, 240, 255, 48, 4, 224, 1, 32, 2, 224, 0, 32, 0, 224, 24, 70, 189, ++ 232, 254, 143, 172, 240, 135, 0, 45, 233, 240, 65, 4, 70, 0, 43, 59, ++ 208, 194, 243, 192, 23, 206, 9, 1, 240, 127, 5, 30, 74, 20, 33, 55, ++ 177, 1, 251, 5, 34, 14, 177, 210, 104, 8, 224, 146, 104, 6, 224, 30, ++ 177, 1, 251, 5, 34, 82, 104, 1, 224, 105, 67, 82, 88, 79, 234, 146, ++ 40, 219, 8, 31, 250, 136, 248, 40, 70, 3, 251, 8, 248, 25, 240, 237, ++ 219, 6, 235, 64, 2, 7, 235, 66, 2, 14, 50, 227, 124, 84, 248, 34, 32, ++ 31, 250, 136, 248, 83, 67, 152, 69, 18, 211, 40, 70, 25, 240, 221, 219, ++ 6, 235, 64, 6, 7, 235, 70, 7, 14, 55, 84, 248, 39, 48, 224, 124, 88, ++ 67, 128, 178, 189, 232, 240, 129, 79, 246, 255, 112, 189, 232, 240, ++ 129, 64, 70, 189, 232, 240, 129, 172, 240, 135, 0, 112, 181, 5, 121, ++ 1, 35, 197, 241, 16, 5, 19, 250, 5, 245, 6, 70, 79, 240, 255, 52, 23, ++ 44, 3, 208, 1, 52, 102, 44, 1, 221, 54, 224, 87, 36, 32, 70, 25, 240, ++ 180, 219, 0, 35, 124, 48, 38, 248, 16, 48, 51, 121, 5, 43, 238, 216, ++ 164, 241, 12, 3, 3, 43, 7, 216, 32, 70, 25, 240, 166, 219, 22, 75, 124, ++ 48, 211, 248, 168, 49, 24, 224, 164, 241, 21, 3, 1, 43, 7, 216, 32, ++ 70, 25, 240, 154, 219, 16, 75, 124, 48, 211, 248, 208, 49, 12, 224, ++ 164, 241, 87, 3, 15, 43, 210, 216, 32, 70, 25, 240, 142, 219, 10, 75, ++ 20, 34, 2, 251, 4, 51, 91, 104, 124, 48, 1, 59, 91, 25, 179, 251, 245, ++ 243, 38, 248, 16, 48, 194, 231, 4, 75, 211, 248, 216, 49, 1, 59, 91, ++ 25, 179, 251, 245, 245, 53, 129, 112, 189, 172, 240, 135, 0, 45, 233, ++ 240, 65, 4, 70, 142, 10, 79, 240, 255, 53, 23, 45, 4, 208, 1, 53, 102, ++ 45, 2, 221, 189, 232, 240, 129, 87, 37, 20, 35, 107, 67, 23, 74, 40, ++ 70, 215, 24, 82, 248, 3, 128, 25, 240, 95, 219, 8, 251, 6, 248, 4, 235, ++ 0, 16, 79, 234, 216, 3, 131, 99, 40, 70, 215, 248, 4, 128, 25, 240, ++ 83, 219, 8, 251, 6, 248, 4, 235, 0, 16, 79, 234, 216, 3, 3, 100, 40, ++ 70, 215, 248, 8, 128, 25, 240, 71, 219, 8, 251, 6, 248, 4, 235, 0, 16, ++ 79, 234, 216, 3, 195, 99, 40, 70, 255, 104, 25, 240, 60, 219, 119, 67, ++ 4, 235, 0, 16, 255, 8, 71, 100, 197, 231, 172, 240, 135, 0, 56, 181, ++ 149, 105, 145, 98, 69, 244, 128, 117, 37, 244, 0, 69, 149, 97, 157, ++ 248, 16, 80, 53, 177, 16, 240, 159, 221, 208, 241, 1, 0, 56, 191, 0, ++ 32, 56, 189, 17, 70, 26, 70, 1, 35, 6, 240, 117, 250, 208, 241, 1, 0, ++ 56, 191, 0, 32, 56, 189, 45, 233, 240, 79, 20, 70, 210, 248, 244, 144, ++ 146, 248, 2, 160, 2, 104, 187, 176, 21, 104, 7, 70, 7, 149, 152, 70, ++ 0, 43, 0, 240, 46, 129, 9, 235, 74, 3, 180, 248, 92, 96, 179, 248, 198, ++ 48, 246, 67, 158, 25, 54, 5, 53, 13, 5, 235, 8, 6, 2, 149, 180, 248, ++ 96, 0, 180, 248, 248, 80, 69, 25, 174, 66, 13, 221, 101, 120, 133, 66, ++ 0, 242, 24, 129, 180, 248, 84, 0, 0, 40, 64, 240, 19, 129, 1, 59, 27, ++ 5, 27, 13, 164, 248, 92, 48, 16, 49, 82, 104, 184, 241, 1, 15, 148, ++ 191, 0, 37, 1, 37, 4, 145, 5, 146, 6, 149, 0, 45, 0, 240, 148, 128, ++ 95, 250, 136, 245, 8, 168, 1, 33, 79, 244, 128, 98, 3, 149, 0, 38, 233, ++ 243, 63, 247, 163, 70, 127, 224, 4, 152, 81, 70, 233, 243, 163, 247, ++ 133, 137, 4, 70, 142, 45, 87, 220, 0, 46, 85, 208, 178, 137, 119, 75, ++ 81, 28, 11, 64, 3, 241, 64, 14, 115, 104, 176, 104, 241, 136, 195, 243, ++ 20, 3, 3, 235, 81, 19, 65, 13, 73, 5, 1, 51, 128, 24, 194, 235, 14, ++ 14, 91, 24, 31, 250, 142, 254, 27, 26, 49, 70, 5, 152, 114, 68, 206, ++ 235, 3, 3, 237, 243, 37, 245, 6, 70, 0, 40, 52, 208, 128, 104, 179, ++ 137, 192, 48, 192, 59, 176, 96, 179, 129, 161, 104, 42, 70, 231, 247, ++ 116, 251, 50, 70, 181, 129, 7, 152, 33, 70, 243, 247, 106, 250, 226, ++ 137, 243, 137, 2, 240, 7, 2, 35, 240, 7, 3, 19, 67, 243, 129, 92, 75, ++ 162, 138, 27, 104, 83, 248, 34, 48, 3, 177, 27, 136, 0, 32, 179, 130, ++ 1, 34, 160, 130, 33, 70, 5, 152, 240, 247, 39, 251, 179, 127, 3, 240, ++ 15, 3, 12, 43, 6, 209, 59, 104, 73, 70, 211, 248, 104, 7, 50, 70, 254, ++ 247, 231, 252, 52, 70, 0, 38, 8, 168, 0, 33, 34, 70, 233, 243, 152, ++ 247, 206, 185, 75, 75, 38, 70, 25, 104, 19, 224, 112, 104, 178, 104, ++ 243, 136, 192, 243, 20, 0, 0, 235, 83, 16, 83, 13, 1, 48, 91, 5, 195, ++ 24, 176, 137, 18, 24, 155, 26, 179, 245, 0, 127, 4, 220, 179, 138, 81, ++ 248, 35, 96, 0, 46, 233, 209, 3, 157, 107, 30, 219, 178, 255, 43, 3, ++ 147, 127, 244, 121, 175, 92, 70, 0, 38, 67, 70, 53, 70, 176, 70, 78, ++ 70, 153, 70, 6, 152, 16, 177, 8, 168, 0, 33, 1, 224, 4, 152, 81, 70, ++ 233, 243, 16, 247, 131, 70, 0, 40, 55, 208, 131, 105, 1, 53, 67, 244, ++ 128, 99, 131, 97, 33, 70, 173, 178, 255, 247, 239, 250, 24, 177, 8, ++ 241, 1, 8, 31, 250, 136, 248, 187, 248, 28, 48, 58, 104, 27, 5, 27, ++ 13, 144, 104, 1, 147, 254, 243, 242, 247, 16, 240, 8, 15, 1, 155, 5, ++ 208, 187, 248, 28, 32, 66, 244, 0, 82, 171, 248, 28, 32, 151, 248, 225, ++ 19, 4, 241, 67, 0, 1, 57, 25, 64, 234, 243, 48, 240, 214, 248, 52, 49, ++ 10, 240, 7, 14, 211, 248, 84, 192, 152, 109, 26, 75, 49, 70, 90, 70, ++ 19, 248, 14, 48, 224, 71, 77, 69, 187, 209, 180, 248, 84, 48, 70, 70, ++ 235, 24, 164, 248, 84, 48, 59, 104, 152, 104, 254, 243, 199, 247, 1, ++ 7, 11, 213, 180, 248, 248, 48, 67, 69, 3, 216, 0, 34, 164, 248, 248, ++ 32, 3, 224, 200, 235, 3, 3, 164, 248, 248, 48, 180, 248, 96, 48, 2, ++ 152, 27, 26, 246, 24, 118, 27, 164, 248, 96, 96, 2, 224, 29, 70, 0, ++ 224, 0, 37, 40, 70, 59, 176, 189, 232, 240, 143, 0, 191, 254, 255, 1, ++ 0, 32, 7, 0, 0, 72, 194, 135, 0, 45, 233, 248, 67, 144, 232, 8, 2, 27, ++ 104, 6, 70, 211, 248, 28, 128, 12, 70, 233, 177, 143, 104, 23, 240, ++ 8, 7, 28, 209, 79, 244, 160, 112, 240, 247, 48, 250, 5, 70, 200, 177, ++ 57, 70, 79, 244, 160, 114, 232, 243, 15, 246, 68, 248, 9, 80, 5, 241, ++ 16, 0, 44, 96, 197, 248, 56, 97, 8, 33, 216, 248, 108, 32, 233, 243, ++ 23, 246, 56, 70, 189, 232, 248, 131, 8, 70, 189, 232, 248, 131, 0, 32, ++ 189, 232, 248, 131, 111, 240, 26, 0, 189, 232, 248, 131, 112, 181, 4, ++ 70, 208, 248, 0, 100, 12, 32, 13, 70, 237, 243, 250, 243, 112, 177, ++ 168, 81, 128, 232, 48, 0, 148, 248, 192, 51, 35, 177, 255, 35, 3, 114, ++ 67, 129, 0, 32, 112, 189, 3, 114, 67, 129, 24, 70, 112, 189, 111, 240, ++ 26, 0, 112, 189, 45, 233, 243, 71, 23, 70, 2, 122, 5, 70, 14, 70, 208, ++ 248, 0, 144, 209, 248, 0, 128, 10, 177, 0, 43, 81, 208, 235, 25, 156, ++ 122, 0, 44, 78, 208, 152, 248, 18, 49, 149, 248, 39, 32, 3, 240, 28, ++ 3, 155, 8, 147, 66, 56, 191, 19, 70, 51, 113, 48, 70, 255, 247, 152, ++ 253, 152, 248, 18, 49, 79, 244, 0, 82, 3, 240, 3, 3, 18, 250, 3, 243, ++ 243, 96, 152, 248, 18, 49, 40, 70, 3, 240, 3, 3, 13, 51, 134, 248, 61, ++ 49, 65, 70, 7, 241, 54, 10, 255, 247, 73, 249, 86, 248, 42, 64, 60, ++ 185, 79, 244, 65, 112, 240, 247, 185, 249, 4, 70, 8, 179, 70, 248, 42, ++ 0, 0, 33, 79, 244, 65, 114, 32, 70, 232, 243, 149, 245, 2, 35, 35, 112, ++ 0, 35, 167, 112, 196, 248, 244, 128, 132, 248, 237, 48, 170, 124, 235, ++ 124, 0, 146, 149, 248, 47, 32, 72, 70, 1, 146, 65, 70, 58, 70, 3, 240, ++ 14, 250, 213, 248, 80, 50, 26, 109, 1, 50, 26, 101, 0, 224, 28, 70, ++ 32, 70, 189, 232, 252, 135, 45, 233, 240, 79, 4, 70, 0, 104, 152, 70, ++ 3, 104, 133, 176, 93, 105, 148, 248, 196, 51, 139, 70, 22, 70, 35, 185, ++ 144, 248, 132, 55, 0, 43, 0, 240, 37, 129, 49, 70, 18, 240, 31, 219, ++ 8, 40, 64, 240, 31, 129, 40, 70, 49, 70, 238, 247, 110, 249, 49, 70, ++ 5, 70, 32, 104, 18, 240, 1, 219, 3, 120, 7, 70, 3, 240, 15, 3, 155, ++ 0, 3, 241, 22, 2, 149, 66, 192, 240, 12, 129, 66, 122, 6, 42, 64, 240, ++ 8, 129, 197, 24, 106, 123, 210, 6, 45, 213, 130, 120, 193, 120, 18, ++ 2, 82, 24, 41, 123, 146, 178, 9, 9, 3, 235, 129, 3, 154, 66, 34, 209, ++ 212, 248, 200, 51, 1, 51, 196, 248, 200, 51, 148, 248, 216, 51, 27, ++ 177, 243, 127, 67, 240, 2, 3, 243, 119, 107, 123, 16, 43, 10, 209, 243, ++ 127, 67, 240, 32, 3, 243, 119, 148, 248, 196, 51, 212, 248, 212, 35, ++ 154, 66, 9, 211, 219, 224, 35, 104, 147, 248, 132, 55, 35, 177, 243, ++ 127, 67, 240, 32, 3, 243, 119, 213, 224, 243, 127, 153, 6, 64, 241, ++ 210, 128, 148, 248, 196, 51, 0, 43, 0, 240, 205, 128, 42, 122, 107, ++ 122, 18, 6, 27, 4, 210, 24, 171, 122, 27, 2, 210, 24, 235, 122, 211, ++ 24, 2, 147, 12, 35, 3, 251, 8, 179, 211, 248, 28, 144, 185, 241, 0, ++ 15, 68, 208, 153, 248, 31, 48, 154, 6, 64, 213, 217, 248, 24, 48, 91, ++ 6, 60, 212, 73, 70, 32, 104, 18, 240, 153, 218, 6, 120, 185, 248, 28, ++ 144, 6, 240, 15, 6, 0, 235, 134, 6, 25, 244, 128, 95, 150, 248, 8, 192, ++ 113, 122, 178, 122, 243, 122, 64, 240, 158, 128, 9, 4, 79, 234, 12, ++ 108, 97, 68, 18, 2, 138, 24, 2, 153, 211, 24, 153, 66, 30, 217, 12, ++ 48, 7, 241, 12, 1, 8, 34, 231, 247, 60, 249, 184, 185, 48, 70, 41, 70, ++ 4, 34, 231, 247, 54, 249, 136, 185, 65, 70, 11, 241, 16, 0, 233, 243, ++ 93, 245, 35, 104, 1, 70, 27, 104, 1, 34, 88, 105, 240, 247, 12, 249, ++ 212, 248, 204, 51, 1, 51, 196, 248, 204, 51, 93, 224, 12, 35, 3, 251, ++ 8, 179, 148, 248, 216, 35, 25, 140, 145, 66, 105, 210, 79, 240, 0, 10, ++ 193, 70, 158, 105, 168, 70, 205, 248, 4, 160, 37, 70, 89, 224, 243, ++ 127, 156, 6, 77, 213, 179, 105, 88, 6, 74, 212, 49, 70, 40, 104, 18, ++ 240, 69, 218, 4, 120, 4, 240, 15, 4, 0, 235, 132, 4, 225, 122, 34, 122, ++ 3, 145, 177, 139, 99, 122, 1, 244, 128, 81, 137, 178, 148, 248, 10, ++ 192, 0, 41, 72, 209, 27, 4, 18, 6, 210, 24, 79, 234, 12, 44, 3, 155, ++ 98, 68, 210, 24, 2, 155, 147, 66, 42, 217, 12, 48, 7, 241, 12, 1, 8, ++ 34, 231, 247, 230, 248, 24, 187, 32, 70, 65, 70, 4, 34, 231, 247, 224, ++ 248, 232, 185, 44, 70, 11, 241, 16, 0, 73, 70, 186, 241, 0, 15, 2, 209, ++ 233, 243, 231, 244, 2, 224, 82, 70, 238, 247, 147, 248, 1, 70, 8, 179, ++ 35, 104, 1, 34, 27, 104, 88, 105, 240, 247, 173, 248, 212, 248, 208, ++ 51, 1, 51, 196, 248, 208, 51, 212, 248, 212, 51, 1, 51, 16, 224, 10, ++ 75, 1, 153, 242, 138, 27, 104, 1, 49, 178, 70, 83, 248, 34, 96, 1, 145, ++ 38, 177, 149, 248, 216, 51, 1, 154, 154, 66, 159, 219, 44, 70, 0, 35, ++ 196, 248, 212, 51, 5, 176, 189, 232, 240, 143, 32, 7, 0, 0, 8, 177, ++ 144, 248, 223, 3, 112, 71, 128, 248, 39, 16, 112, 71, 193, 116, 112, ++ 71, 192, 124, 112, 71, 144, 248, 225, 3, 112, 71, 208, 248, 0, 52, 203, ++ 88, 152, 122, 112, 71, 0, 0, 45, 233, 255, 71, 4, 70, 0, 104, 13, 70, ++ 3, 146, 152, 70, 12, 158, 254, 247, 184, 255, 3, 154, 0, 40, 100, 208, ++ 19, 120, 1, 43, 92, 209, 146, 248, 2, 160, 12, 35, 3, 251, 10, 83, 24, ++ 140, 0, 40, 89, 208, 178, 248, 96, 16, 149, 248, 6, 192, 178, 248, 248, ++ 48, 132, 69, 56, 191, 96, 70, 203, 24, 152, 66, 184, 191, 3, 70, 40, ++ 104, 155, 178, 208, 248, 248, 16, 146, 248, 1, 144, 178, 248, 84, 112, ++ 9, 185, 1, 105, 201, 104, 34, 72, 10, 240, 7, 10, 201, 104, 16, 248, ++ 10, 0, 79, 240, 12, 10, 10, 251, 0, 16, 176, 248, 22, 160, 129, 138, ++ 193, 235, 10, 1, 137, 178, 153, 66, 42, 217, 0, 43, 42, 208, 94, 185, ++ 148, 248, 48, 0, 184, 66, 7, 216, 225, 69, 56, 191, 204, 70, 99, 69, ++ 2, 208, 184, 241, 0, 15, 31, 208, 141, 232, 66, 0, 32, 70, 41, 70, 255, ++ 247, 93, 252, 134, 185, 148, 248, 48, 48, 187, 66, 4, 217, 212, 248, ++ 80, 50, 218, 106, 18, 24, 218, 98, 171, 121, 131, 66, 4, 209, 212, 248, ++ 80, 50, 26, 107, 18, 24, 26, 99, 0, 48, 24, 191, 1, 32, 4, 224, 0, 32, ++ 2, 224, 24, 70, 0, 224, 64, 70, 4, 176, 189, 232, 240, 135, 0, 191, ++ 72, 194, 135, 0, 19, 181, 0, 36, 0, 148, 255, 247, 131, 255, 28, 189, ++ 45, 233, 240, 71, 83, 120, 4, 70, 13, 70, 22, 70, 0, 43, 69, 208, 178, ++ 248, 92, 144, 178, 248, 90, 48, 9, 241, 1, 9, 144, 248, 225, 131, 195, ++ 235, 9, 9, 79, 234, 9, 89, 8, 241, 255, 56, 79, 234, 25, 89, 8, 234, ++ 3, 8, 0, 39, 10, 224, 148, 248, 225, 51, 8, 241, 1, 8, 1, 59, 1, 55, ++ 8, 234, 3, 8, 191, 178, 31, 250, 136, 248, 79, 69, 12, 208, 6, 241, ++ 67, 0, 65, 70, 233, 243, 30, 242, 48, 185, 6, 241, 75, 0, 65, 70, 233, ++ 243, 24, 242, 0, 40, 229, 208, 182, 248, 90, 48, 251, 24, 27, 5, 27, ++ 13, 166, 248, 90, 48, 182, 248, 96, 48, 251, 24, 166, 248, 96, 48, 23, ++ 177, 1, 35, 134, 248, 236, 48, 32, 70, 41, 70, 50, 70, 0, 35, 189, 232, ++ 240, 71, 255, 247, 172, 191, 189, 232, 240, 135, 255, 247, 174, 191, ++ 45, 233, 248, 67, 0, 35, 137, 7, 208, 248, 52, 81, 6, 70, 20, 70, 130, ++ 248, 234, 48, 54, 213, 178, 248, 90, 112, 39, 224, 149, 248, 225, 131, ++ 4, 241, 75, 9, 8, 241, 255, 56, 7, 234, 8, 8, 72, 70, 65, 70, 233, 243, ++ 224, 241, 184, 177, 72, 70, 65, 70, 4, 241, 67, 9, 233, 243, 127, 241, ++ 72, 70, 65, 70, 233, 243, 213, 241, 96, 177, 72, 70, 65, 70, 233, 243, ++ 118, 241, 4, 235, 8, 3, 0, 34, 218, 112, 180, 248, 84, 48, 1, 59, 164, ++ 248, 84, 48, 1, 55, 63, 5, 63, 13, 180, 248, 98, 48, 187, 66, 211, 209, ++ 212, 248, 244, 32, 107, 104, 40, 70, 209, 88, 34, 70, 255, 247, 188, ++ 255, 212, 248, 244, 32, 107, 104, 48, 70, 209, 88, 34, 70, 254, 247, ++ 182, 255, 214, 248, 52, 1, 33, 70, 0, 34, 189, 232, 248, 67, 0, 240, ++ 0, 184, 45, 233, 240, 65, 0, 35, 129, 248, 237, 48, 145, 248, 234, 48, ++ 134, 176, 5, 70, 12, 70, 0, 43, 64, 240, 141, 128, 11, 120, 1, 43, 64, ++ 240, 137, 128, 145, 248, 238, 48, 49, 43, 0, 242, 132, 128, 25, 43, ++ 6, 209, 26, 35, 129, 248, 238, 48, 3, 35, 129, 248, 237, 48, 122, 224, ++ 177, 248, 90, 96, 66, 187, 144, 248, 225, 51, 79, 240, 255, 55, 1, 59, ++ 30, 64, 144, 70, 14, 224, 49, 70, 4, 241, 75, 0, 233, 243, 121, 241, ++ 149, 248, 225, 51, 1, 54, 1, 59, 0, 40, 24, 191, 71, 70, 30, 64, 8, ++ 241, 1, 8, 98, 120, 180, 248, 96, 48, 211, 26, 152, 69, 234, 219, 120, ++ 28, 3, 209, 0, 35, 132, 248, 238, 48, 84, 224, 180, 248, 90, 96, 1, ++ 54, 246, 25, 54, 5, 54, 13, 107, 122, 0, 43, 48, 209, 0, 147, 13, 241, ++ 23, 3, 2, 147, 162, 120, 51, 70, 1, 39, 40, 104, 212, 248, 244, 16, ++ 1, 151, 2, 240, 193, 255, 157, 248, 23, 48, 128, 70, 11, 177, 4, 35, ++ 21, 224, 16, 185, 132, 248, 237, 112, 52, 224, 43, 104, 27, 73, 211, ++ 248, 120, 4, 34, 70, 59, 70, 17, 240, 11, 254, 43, 104, 23, 73, 211, ++ 248, 120, 4, 34, 70, 67, 70, 71, 240, 69, 222, 24, 177, 2, 35, 132, ++ 248, 237, 48, 31, 224, 213, 248, 80, 50, 154, 109, 1, 50, 154, 101, ++ 148, 248, 238, 48, 164, 248, 98, 96, 1, 51, 132, 248, 238, 48, 1, 35, ++ 132, 248, 234, 48, 164, 248, 86, 96, 107, 122, 1, 43, 11, 209, 42, 104, ++ 7, 73, 210, 248, 120, 4, 34, 70, 17, 240, 227, 253, 40, 104, 2, 33, ++ 34, 70, 255, 247, 20, 255, 6, 176, 189, 232, 240, 129, 0, 191, 101, ++ 180, 1, 0, 45, 233, 248, 67, 157, 248, 32, 192, 5, 70, 12, 70, 22, 70, ++ 188, 241, 0, 15, 14, 208, 177, 248, 94, 48, 211, 26, 27, 5, 27, 13, ++ 179, 245, 0, 111, 128, 242, 203, 128, 86, 28, 54, 5, 54, 13, 161, 248, ++ 94, 96, 210, 224, 144, 248, 225, 115, 122, 30, 50, 64, 138, 24, 208, ++ 120, 0, 40, 71, 209, 177, 248, 94, 32, 178, 66, 61, 208, 183, 26, 63, ++ 5, 63, 13, 1, 33, 183, 245, 0, 111, 25, 96, 4, 217, 213, 248, 80, 50, ++ 154, 108, 82, 24, 11, 224, 180, 248, 90, 48, 97, 120, 243, 26, 27, 5, ++ 27, 13, 139, 66, 213, 248, 80, 50, 4, 219, 154, 108, 1, 50, 154, 100, ++ 189, 232, 248, 131, 25, 108, 128, 70, 201, 25, 25, 100, 149, 248, 225, ++ 147, 9, 241, 255, 57, 9, 234, 2, 9, 15, 224, 73, 70, 4, 241, 75, 0, ++ 233, 243, 223, 243, 149, 248, 225, 51, 9, 241, 1, 9, 1, 59, 9, 234, ++ 3, 9, 8, 241, 1, 8, 31, 250, 137, 249, 184, 69, 237, 211, 40, 70, 33, ++ 70, 0, 34, 255, 247, 253, 254, 1, 54, 54, 5, 54, 13, 164, 248, 94, 96, ++ 130, 224, 177, 248, 232, 16, 169, 177, 180, 248, 228, 48, 3, 241, 48, ++ 2, 4, 235, 66, 2, 144, 136, 176, 66, 12, 209, 162, 248, 4, 192, 149, ++ 248, 225, 35, 1, 51, 1, 58, 19, 64, 1, 57, 164, 248, 228, 48, 164, 248, ++ 232, 16, 102, 224, 180, 248, 228, 32, 0, 35, 10, 224, 4, 235, 66, 0, ++ 176, 248, 100, 0, 176, 66, 39, 208, 1, 50, 120, 30, 2, 64, 1, 51, 146, ++ 178, 139, 66, 242, 211, 76, 224, 149, 248, 225, 19, 4, 241, 75, 0, 1, ++ 57, 25, 64, 233, 243, 148, 243, 213, 248, 80, 50, 0, 33, 90, 108, 1, ++ 50, 90, 100, 180, 248, 228, 48, 4, 235, 67, 2, 162, 248, 100, 16, 149, ++ 248, 225, 35, 1, 51, 1, 58, 19, 64, 164, 248, 228, 48, 180, 248, 232, ++ 48, 1, 59, 164, 248, 232, 48, 180, 248, 228, 48, 4, 235, 67, 3, 179, ++ 248, 100, 48, 179, 66, 215, 209, 33, 70, 0, 34, 40, 70, 255, 247, 159, ++ 254, 180, 248, 228, 48, 0, 33, 4, 235, 67, 2, 162, 248, 100, 16, 149, ++ 248, 225, 35, 1, 51, 1, 58, 19, 64, 164, 248, 228, 48, 180, 248, 232, ++ 48, 1, 59, 164, 248, 232, 48, 19, 224, 149, 248, 225, 19, 4, 241, 75, ++ 0, 1, 57, 49, 64, 233, 243, 83, 243, 7, 224, 1, 32, 189, 232, 248, 131, ++ 213, 248, 80, 50, 154, 108, 1, 50, 154, 100, 0, 32, 189, 232, 248, 131, ++ 35, 120, 3, 43, 232, 208, 1, 32, 189, 232, 248, 131, 16, 181, 157, 248, ++ 8, 64, 2, 148, 189, 232, 16, 64, 255, 247, 9, 191, 0, 0, 45, 233, 240, ++ 79, 171, 176, 15, 70, 5, 70, 146, 70, 4, 104, 0, 33, 37, 168, 11, 34, ++ 9, 147, 221, 248, 208, 176, 221, 248, 212, 144, 232, 243, 93, 241, 231, ++ 177, 123, 104, 91, 3, 25, 213, 107, 104, 251, 88, 30, 147, 186, 248, ++ 14, 48, 30, 152, 3, 240, 7, 3, 21, 147, 221, 248, 84, 192, 54, 51, 80, ++ 248, 35, 96, 5, 235, 12, 3, 147, 248, 23, 192, 219, 127, 205, 248, 128, ++ 192, 33, 147, 22, 177, 51, 120, 2, 43, 7, 209, 40, 70, 81, 70, 9, 154, ++ 0, 35, 254, 247, 113, 255, 0, 240, 19, 188, 0, 33, 8, 34, 40, 168, 232, ++ 243, 50, 241, 9, 152, 57, 105, 67, 136, 144, 248, 24, 128, 3, 240, 7, ++ 3, 26, 147, 218, 248, 24, 48, 34, 145, 195, 243, 192, 99, 10, 147, 35, ++ 104, 147, 248, 156, 32, 1, 42, 65, 208, 144, 249, 25, 48, 0, 43, 0, ++ 240, 188, 128, 184, 241, 6, 15, 6, 208, 10, 154, 184, 241, 7, 15, 8, ++ 191, 0, 34, 10, 146, 1, 224, 0, 35, 10, 147, 9, 152, 11, 240, 30, 2, ++ 131, 136, 27, 9, 27, 147, 3, 140, 141, 248, 164, 144, 27, 11, 67, 234, ++ 194, 3, 141, 248, 160, 48, 79, 234, 27, 35, 141, 248, 161, 48, 79, 234, ++ 27, 67, 141, 248, 162, 48, 79, 234, 25, 35, 141, 248, 165, 48, 79, 234, ++ 25, 67, 79, 234, 25, 105, 79, 234, 27, 107, 141, 248, 167, 144, 79, ++ 240, 0, 9, 141, 248, 163, 176, 141, 248, 166, 48, 205, 248, 52, 144, ++ 205, 248, 68, 144, 205, 248, 48, 144, 205, 248, 88, 144, 117, 224, 182, ++ 248, 90, 192, 9, 152, 205, 248, 108, 192, 128, 136, 9, 153, 22, 144, ++ 8, 140, 11, 240, 30, 3, 0, 11, 64, 234, 195, 0, 79, 234, 27, 33, 79, ++ 234, 27, 67, 201, 178, 219, 178, 79, 234, 27, 107, 141, 248, 160, 0, ++ 141, 248, 161, 16, 141, 248, 162, 48, 141, 248, 163, 176, 40, 185, 33, ++ 185, 27, 185, 27, 241, 0, 2, 24, 191, 1, 34, 79, 234, 25, 35, 219, 178, ++ 17, 147, 79, 234, 25, 67, 219, 178, 13, 147, 213, 248, 80, 50, 95, 250, ++ 137, 252, 217, 104, 17, 152, 1, 49, 217, 96, 213, 248, 80, 50, 79, 234, ++ 25, 105, 211, 248, 136, 16, 205, 248, 48, 192, 97, 68, 195, 248, 136, ++ 16, 211, 248, 144, 16, 9, 24, 195, 248, 144, 16, 13, 152, 211, 248, ++ 140, 16, 9, 24, 195, 248, 140, 16, 211, 248, 148, 16, 17, 152, 73, 68, ++ 195, 248, 148, 16, 35, 104, 17, 153, 211, 248, 136, 48, 1, 235, 9, 14, ++ 211, 248, 168, 17, 192, 235, 12, 11, 113, 68, 195, 248, 168, 17, 211, ++ 248, 216, 17, 13, 152, 113, 68, 195, 248, 216, 17, 201, 235, 0, 1, 11, ++ 235, 1, 0, 217, 104, 9, 24, 217, 96, 215, 248, 56, 50, 215, 248, 60, ++ 18, 115, 68, 8, 24, 199, 248, 56, 50, 199, 248, 60, 2, 114, 177, 35, ++ 104, 147, 248, 156, 48, 1, 43, 17, 208, 1, 33, 16, 145, 11, 145, 102, ++ 224, 153, 70, 13, 147, 17, 147, 12, 147, 22, 147, 27, 147, 213, 248, ++ 80, 50, 26, 110, 1, 50, 26, 102, 0, 34, 16, 146, 0, 224, 16, 147, 184, ++ 241, 0, 15, 64, 208, 213, 248, 232, 50, 8, 241, 180, 2, 83, 248, 34, ++ 16, 1, 49, 184, 241, 4, 15, 67, 248, 34, 16, 10, 209, 35, 104, 211, ++ 248, 136, 48, 211, 248, 16, 34, 1, 50, 195, 248, 16, 34, 0, 35, 10, ++ 147, 60, 224, 184, 241, 5, 15, 14, 209, 35, 104, 211, 248, 136, 48, ++ 211, 248, 160, 34, 1, 50, 195, 248, 160, 34, 180, 248, 36, 53, 75, 179, ++ 32, 70, 246, 247, 144, 252, 10, 224, 184, 241, 3, 15, 32, 70, 11, 209, ++ 179, 75, 221, 248, 84, 192, 19, 248, 12, 16, 254, 247, 250, 254, 1, ++ 32, 0, 33, 11, 144, 10, 145, 27, 224, 66, 70, 81, 70, 19, 240, 21, 220, ++ 1, 34, 11, 146, 0, 35, 15, 224, 9, 152, 195, 136, 115, 177, 35, 104, ++ 1, 33, 211, 248, 136, 48, 11, 145, 154, 107, 205, 248, 40, 128, 1, 50, ++ 154, 99, 5, 224, 1, 34, 11, 146, 10, 147, 1, 224, 1, 35, 11, 147, 180, ++ 248, 36, 53, 0, 43, 0, 240, 43, 130, 212, 248, 40, 53, 0, 43, 0, 240, ++ 38, 130, 184, 241, 5, 15, 0, 240, 34, 130, 32, 70, 246, 247, 94, 252, ++ 29, 226, 218, 248, 8, 176, 14, 152, 187, 248, 0, 192, 205, 248, 140, ++ 192, 187, 248, 140, 48, 27, 9, 18, 147, 0, 40, 64, 240, 174, 128, 155, ++ 248, 112, 48, 34, 104, 3, 240, 127, 3, 15, 147, 146, 248, 156, 32, 155, ++ 248, 115, 48, 217, 9, 1, 42, 20, 145, 64, 240, 159, 128, 187, 248, 76, ++ 192, 24, 6, 205, 248, 100, 192, 22, 213, 213, 248, 80, 50, 221, 248, ++ 48, 192, 26, 106, 98, 68, 26, 98, 213, 248, 232, 50, 99, 177, 15, 152, ++ 24, 240, 89, 219, 213, 248, 232, 50, 86, 48, 3, 235, 128, 3, 90, 104, ++ 221, 248, 48, 192, 98, 68, 90, 96, 155, 248, 115, 48, 19, 240, 48, 15, ++ 22, 208, 213, 248, 80, 50, 221, 248, 48, 192, 90, 106, 98, 68, 90, 98, ++ 213, 248, 232, 50, 99, 177, 15, 152, 24, 240, 61, 219, 213, 248, 232, ++ 50, 118, 48, 83, 248, 32, 32, 221, 248, 48, 192, 98, 68, 67, 248, 32, ++ 32, 213, 248, 232, 50, 195, 177, 15, 152, 24, 240, 45, 219, 213, 248, ++ 232, 50, 44, 48, 83, 248, 32, 32, 221, 248, 48, 192, 98, 68, 67, 248, ++ 32, 32, 15, 152, 24, 240, 32, 219, 213, 248, 232, 50, 148, 48, 3, 235, ++ 128, 3, 90, 104, 17, 152, 18, 24, 90, 96, 187, 248, 20, 48, 153, 7, ++ 69, 208, 155, 248, 54, 128, 213, 248, 232, 50, 8, 240, 127, 8, 91, 177, ++ 64, 70, 24, 240, 9, 219, 213, 248, 232, 50, 44, 48, 83, 248, 32, 32, ++ 13, 153, 82, 24, 67, 248, 32, 32, 155, 249, 57, 48, 0, 43, 20, 218, ++ 213, 248, 80, 50, 13, 152, 26, 106, 18, 24, 26, 98, 213, 248, 232, 50, ++ 91, 177, 64, 70, 24, 240, 240, 218, 213, 248, 232, 50, 86, 48, 3, 235, ++ 128, 3, 90, 104, 13, 153, 82, 24, 90, 96, 155, 248, 57, 48, 19, 240, ++ 48, 15, 20, 208, 213, 248, 80, 50, 13, 152, 90, 106, 18, 24, 90, 98, ++ 213, 248, 232, 50, 91, 177, 64, 70, 24, 240, 214, 218, 213, 248, 232, ++ 50, 118, 48, 83, 248, 32, 32, 13, 153, 82, 24, 67, 248, 32, 32, 35, ++ 104, 149, 248, 225, 131, 147, 248, 156, 48, 18, 154, 8, 241, 255, 56, ++ 1, 43, 8, 234, 2, 8, 3, 208, 6, 235, 8, 3, 219, 120, 24, 147, 182, 248, ++ 90, 48, 221, 248, 72, 192, 114, 120, 195, 235, 12, 3, 27, 5, 27, 13, ++ 147, 66, 128, 242, 6, 129, 6, 241, 67, 12, 96, 70, 65, 70, 205, 248, ++ 76, 192, 232, 243, 167, 245, 16, 152, 32, 185, 35, 104, 147, 248, 156, ++ 48, 1, 43, 71, 209, 35, 104, 147, 248, 156, 48, 1, 43, 1, 209, 14, 153, ++ 6, 224, 18, 154, 221, 248, 108, 192, 204, 235, 2, 1, 9, 5, 9, 13, 63, ++ 41, 55, 216, 40, 168, 232, 243, 141, 245, 0, 40, 50, 208, 19, 152, 65, ++ 70, 232, 243, 135, 245, 184, 177, 19, 152, 65, 70, 6, 241, 75, 11, 232, ++ 243, 38, 245, 88, 70, 65, 70, 232, 243, 124, 245, 24, 177, 88, 70, 65, ++ 70, 232, 243, 29, 245, 6, 235, 8, 3, 0, 34, 218, 112, 182, 248, 84, ++ 48, 1, 59, 166, 248, 84, 48, 2, 34, 212, 248, 120, 4, 81, 70, 71, 240, ++ 82, 218, 221, 248, 92, 192, 12, 241, 1, 3, 219, 178, 23, 147, 35, 104, ++ 147, 248, 156, 48, 1, 43, 64, 240, 179, 128, 179, 224, 0, 191, 138, ++ 182, 135, 0, 11, 152, 202, 248, 40, 112, 0, 40, 49, 208, 35, 104, 147, ++ 248, 156, 48, 1, 43, 44, 209, 43, 104, 147, 248, 1, 198, 28, 240, 8, ++ 12, 38, 209, 185, 241, 1, 15, 35, 209, 32, 70, 57, 70, 82, 70, 9, 155, ++ 205, 248, 0, 192, 205, 248, 32, 192, 254, 247, 9, 255, 221, 248, 32, ++ 192, 11, 144, 0, 40, 64, 240, 144, 128, 6, 235, 8, 3, 216, 112, 182, ++ 248, 84, 48, 19, 152, 1, 59, 166, 248, 84, 48, 65, 70, 232, 243, 41, ++ 245, 0, 40, 0, 240, 131, 128, 19, 152, 65, 70, 232, 243, 200, 244, 125, ++ 224, 35, 104, 147, 248, 156, 48, 1, 43, 62, 208, 11, 153, 0, 41, 59, ++ 208, 221, 248, 96, 192, 32, 152, 132, 69, 54, 218, 185, 241, 0, 15, ++ 2, 208, 185, 241, 3, 15, 48, 209, 187, 248, 118, 48, 67, 244, 0, 99, ++ 171, 248, 118, 48, 6, 235, 8, 3, 218, 120, 221, 248, 72, 192, 1, 50, ++ 218, 112, 182, 248, 230, 48, 21, 153, 6, 235, 67, 2, 162, 248, 100, ++ 192, 149, 248, 225, 35, 1, 51, 1, 58, 19, 64, 166, 248, 230, 48, 182, ++ 248, 232, 48, 1, 51, 166, 248, 232, 48, 215, 248, 52, 49, 211, 248, ++ 84, 192, 152, 109, 147, 75, 91, 92, 13, 43, 1, 220, 1, 51, 0, 224, 15, ++ 35, 57, 70, 82, 70, 224, 71, 0, 35, 58, 224, 160, 104, 253, 243, 178, ++ 247, 2, 7, 21, 213, 31, 154, 154, 185, 6, 235, 8, 3, 218, 112, 182, ++ 248, 84, 48, 6, 241, 252, 0, 1, 59, 166, 248, 84, 48, 18, 153, 114, ++ 120, 254, 247, 108, 250, 182, 248, 248, 48, 1, 51, 166, 248, 248, 48, ++ 6, 224, 6, 241, 75, 0, 65, 70, 232, 243, 229, 247, 1, 35, 29, 147, 35, ++ 104, 211, 248, 136, 48, 211, 248, 176, 33, 1, 50, 195, 248, 176, 33, ++ 215, 248, 64, 50, 1, 51, 199, 248, 64, 50, 215, 248, 92, 49, 1, 51, ++ 199, 248, 92, 49, 1, 35, 4, 224, 16, 147, 2, 224, 99, 70, 0, 224, 75, ++ 70, 14, 152, 66, 28, 210, 178, 14, 146, 35, 177, 96, 104, 81, 70, 1, ++ 34, 239, 247, 70, 250, 35, 104, 147, 248, 156, 32, 1, 42, 20, 209, 213, ++ 248, 80, 50, 32, 70, 211, 248, 160, 16, 1, 57, 195, 248, 160, 16, 211, ++ 248, 156, 16, 1, 49, 195, 248, 156, 16, 26, 153, 246, 247, 25, 249, ++ 14, 153, 221, 248, 88, 192, 97, 69, 5, 224, 221, 248, 140, 192, 12, ++ 244, 192, 99, 179, 245, 192, 111, 37, 208, 99, 105, 221, 248, 104, 192, ++ 2, 33, 83, 248, 44, 0, 88, 75, 219, 107, 152, 71, 130, 70, 0, 40, 127, ++ 244, 227, 173, 23, 224, 73, 35, 67, 250, 8, 243, 79, 246, 255, 124, ++ 0, 32, 3, 240, 1, 3, 205, 248, 100, 192, 79, 240, 255, 60, 205, 248, ++ 112, 144, 31, 147, 205, 248, 96, 192, 14, 144, 23, 144, 29, 144, 20, ++ 144, 15, 144, 193, 70, 201, 229, 35, 104, 221, 248, 112, 144, 147, 248, ++ 156, 48, 1, 43, 4, 208, 213, 248, 232, 50, 26, 110, 1, 50, 26, 102, ++ 29, 153, 33, 177, 40, 70, 49, 70, 0, 34, 255, 247, 150, 250, 35, 104, ++ 147, 248, 156, 48, 1, 43, 42, 209, 12, 154, 13, 152, 19, 24, 17, 209, ++ 10, 153, 0, 41, 64, 208, 15, 154, 20, 152, 0, 147, 1, 147, 2, 147, 3, ++ 147, 4, 146, 6, 147, 5, 144, 212, 248, 96, 1, 57, 70, 25, 154, 22, 155, ++ 17, 224, 17, 153, 13, 154, 0, 145, 15, 152, 20, 153, 0, 35, 1, 146, ++ 3, 147, 5, 145, 6, 147, 205, 248, 8, 144, 4, 144, 212, 248, 96, 1, 25, ++ 154, 12, 155, 57, 70, 33, 240, 49, 251, 28, 224, 10, 154, 210, 177, ++ 14, 155, 16, 152, 221, 248, 96, 192, 0, 147, 128, 240, 1, 3, 1, 147, ++ 33, 152, 95, 250, 140, 243, 15, 153, 20, 154, 2, 147, 0, 35, 4, 147, ++ 5, 145, 6, 146, 7, 147, 3, 144, 212, 248, 96, 1, 57, 70, 9, 154, 23, ++ 155, 33, 240, 57, 251, 35, 104, 147, 248, 156, 48, 1, 43, 5, 208, 32, ++ 70, 26, 153, 149, 248, 46, 32, 246, 247, 124, 248, 187, 104, 3, 244, ++ 128, 83, 79, 234, 19, 56, 43, 177, 148, 248, 116, 130, 72, 240, 2, 3, ++ 132, 248, 116, 50, 40, 70, 30, 153, 50, 70, 255, 247, 217, 249, 187, ++ 104, 32, 70, 219, 4, 9, 155, 72, 191, 132, 248, 116, 130, 3, 241, 20, ++ 1, 20, 240, 92, 218, 1, 70, 34, 152, 20, 240, 8, 219, 43, 176, 189, ++ 232, 240, 143, 0, 191, 72, 194, 135, 0, 208, 134, 135, 0, 45, 233, 240, ++ 71, 4, 70, 153, 70, 0, 41, 0, 240, 135, 128, 75, 104, 91, 3, 64, 241, ++ 131, 128, 67, 104, 206, 88, 211, 137, 3, 240, 7, 3, 54, 51, 86, 248, ++ 35, 80, 0, 45, 120, 208, 43, 120, 2, 43, 117, 208, 17, 70, 0, 104, 254, ++ 247, 47, 251, 181, 248, 90, 48, 106, 120, 195, 26, 27, 5, 27, 13, 147, ++ 66, 128, 70, 104, 218, 148, 248, 225, 115, 5, 241, 67, 10, 1, 63, 7, ++ 64, 191, 178, 80, 70, 57, 70, 232, 243, 142, 243, 0, 40, 91, 208, 153, ++ 249, 25, 48, 251, 177, 80, 70, 57, 70, 5, 241, 75, 8, 232, 243, 41, ++ 243, 64, 70, 57, 70, 232, 243, 127, 243, 24, 177, 64, 70, 57, 70, 232, ++ 243, 32, 243, 0, 35, 239, 25, 251, 112, 181, 248, 84, 48, 213, 248, ++ 244, 32, 1, 59, 165, 248, 84, 48, 99, 104, 32, 70, 209, 88, 42, 70, ++ 255, 247, 110, 249, 49, 224, 212, 248, 80, 50, 218, 108, 1, 50, 218, ++ 100, 35, 104, 27, 104, 147, 248, 47, 32, 153, 248, 24, 48, 10, 177, ++ 1, 43, 1, 208, 7, 43, 23, 209, 239, 25, 251, 120, 1, 51, 251, 112, 181, ++ 248, 230, 48, 5, 235, 67, 2, 162, 248, 100, 128, 148, 248, 225, 35, ++ 1, 51, 1, 58, 19, 64, 165, 248, 230, 48, 181, 248, 232, 48, 1, 51, 165, ++ 248, 232, 48, 189, 232, 240, 135, 5, 241, 75, 0, 57, 70, 232, 243, 100, ++ 246, 32, 70, 41, 70, 0, 34, 255, 247, 143, 249, 32, 104, 49, 70, 42, ++ 70, 189, 232, 240, 71, 254, 247, 54, 185, 189, 232, 240, 135, 45, 233, ++ 240, 65, 13, 70, 20, 70, 17, 70, 26, 70, 30, 70, 157, 248, 24, 112, ++ 254, 247, 41, 249, 40, 70, 33, 70, 50, 70, 59, 70, 189, 232, 240, 65, ++ 255, 247, 201, 184, 0, 0, 45, 233, 240, 79, 7, 70, 13, 105, 154, 70, ++ 215, 248, 0, 52, 137, 176, 85, 248, 3, 192, 0, 32, 156, 249, 8, 144, ++ 14, 70, 20, 70, 7, 144, 61, 104, 211, 137, 185, 241, 0, 15, 0, 240, ++ 3, 129, 188, 248, 10, 144, 3, 240, 7, 3, 73, 250, 3, 249, 25, 240, 1, ++ 9, 4, 209, 248, 224, 129, 70, 246, 224, 193, 70, 244, 224, 146, 248, ++ 31, 128, 24, 240, 8, 8, 246, 209, 7, 168, 0, 144, 40, 70, 20, 240, 236, ++ 219, 7, 154, 0, 42, 240, 209, 227, 137, 3, 240, 7, 3, 4, 147, 163, 105, ++ 153, 5, 8, 212, 115, 74, 4, 152, 115, 73, 18, 92, 138, 92, 166, 50, ++ 85, 248, 34, 144, 0, 224, 145, 70, 122, 104, 4, 153, 178, 88, 3, 146, ++ 3, 152, 1, 241, 54, 2, 80, 248, 34, 128, 184, 241, 0, 15, 12, 209, 218, ++ 6, 0, 241, 200, 128, 67, 70, 56, 70, 3, 153, 4, 154, 254, 247, 70, 254, ++ 128, 70, 0, 40, 0, 240, 190, 128, 152, 248, 0, 48, 1, 43, 64, 240, 185, ++ 128, 205, 248, 20, 128, 79, 240, 0, 11, 176, 70, 46, 70, 223, 248, 120, ++ 161, 226, 138, 218, 248, 0, 48, 0, 33, 83, 248, 34, 80, 225, 130, 112, ++ 104, 33, 70, 237, 247, 23, 248, 142, 40, 5, 216, 56, 70, 3, 153, 34, ++ 70, 4, 155, 254, 247, 133, 254, 163, 139, 3, 244, 128, 83, 155, 178, ++ 0, 43, 24, 191, 79, 240, 1, 11, 59, 104, 147, 248, 132, 55, 51, 177, ++ 227, 127, 3, 240, 32, 3, 0, 43, 24, 191, 79, 240, 1, 11, 0, 35, 0, 147, ++ 3, 155, 48, 70, 3, 241, 16, 1, 34, 70, 4, 155, 15, 240, 178, 219, 184, ++ 185, 170, 70, 53, 70, 70, 70, 221, 248, 20, 128, 186, 241, 0, 15, 1, ++ 208, 186, 248, 0, 160, 164, 248, 22, 160, 57, 70, 67, 70, 40, 70, 3, ++ 154, 205, 248, 0, 176, 79, 240, 0, 8, 255, 247, 61, 255, 33, 70, 49, ++ 224, 227, 137, 35, 244, 128, 83, 227, 129, 77, 177, 34, 70, 48, 70, ++ 65, 70, 43, 70, 205, 248, 0, 144, 44, 70, 15, 240, 51, 218, 165, 231, ++ 221, 248, 20, 128, 48, 70, 57, 70, 3, 154, 67, 70, 205, 248, 0, 176, ++ 255, 247, 34, 255, 80, 224, 44, 72, 202, 138, 3, 104, 83, 248, 34, 144, ++ 0, 35, 203, 130, 203, 137, 104, 104, 35, 244, 128, 83, 203, 129, 1, ++ 34, 238, 247, 238, 255, 51, 105, 27, 177, 219, 104, 26, 106, 1, 50, ++ 26, 98, 8, 241, 1, 8, 73, 70, 0, 41, 229, 209, 184, 241, 0, 15, 51, ++ 208, 43, 104, 211, 248, 136, 48, 26, 106, 66, 68, 26, 98, 215, 248, ++ 80, 50, 218, 107, 66, 68, 218, 99, 214, 248, 92, 49, 67, 68, 198, 248, ++ 92, 49, 34, 224, 21, 75, 226, 138, 27, 104, 0, 32, 83, 248, 34, 128, ++ 227, 137, 224, 130, 35, 244, 128, 83, 227, 129, 184, 241, 0, 15, 7, ++ 208, 56, 70, 49, 70, 34, 70, 67, 70, 205, 248, 0, 144, 15, 240, 227, ++ 217, 214, 248, 52, 49, 34, 70, 93, 109, 152, 109, 49, 70, 83, 70, 168, ++ 71, 68, 70, 0, 224, 47, 70, 0, 44, 220, 209, 9, 176, 189, 232, 240, ++ 143, 0, 191, 138, 182, 135, 0, 84, 194, 135, 0, 32, 7, 0, 0, 36, 35, ++ 3, 251, 1, 3, 1, 34, 131, 248, 100, 34, 112, 71, 0, 0, 45, 233, 240, ++ 79, 208, 248, 0, 128, 245, 176, 216, 248, 4, 112, 37, 145, 17, 104, ++ 5, 70, 28, 146, 0, 36, 97, 170, 64, 70, 21, 147, 11, 151, 115, 148, ++ 112, 145, 242, 247, 153, 250, 112, 155, 218, 137, 155, 106, 2, 240, ++ 7, 2, 15, 146, 15, 159, 165, 74, 8, 147, 210, 93, 9, 146, 9, 159, 52, ++ 34, 122, 67, 2, 245, 60, 114, 175, 24, 16, 151, 31, 105, 107, 104, 35, ++ 151, 8, 159, 42, 146, 251, 88, 15, 159, 20, 147, 7, 241, 54, 3, 20, ++ 159, 87, 248, 35, 176, 15, 159, 235, 25, 219, 127, 9, 159, 31, 147, ++ 36, 35, 3, 251, 7, 83, 3, 245, 22, 115, 7, 147, 216, 248, 0, 48, 147, ++ 248, 156, 48, 1, 43, 45, 209, 40, 70, 57, 70, 253, 247, 144, 255, 3, ++ 70, 213, 248, 232, 34, 11, 43, 40, 191, 11, 35, 74, 51, 2, 235, 131, ++ 3, 90, 104, 19, 144, 1, 50, 90, 96, 0, 40, 0, 240, 136, 134, 152, 248, ++ 74, 54, 11, 152, 112, 153, 19, 177, 232, 243, 77, 244, 1, 224, 236, ++ 247, 8, 255, 216, 248, 28, 48, 9, 159, 3, 235, 135, 3, 91, 104, 27, ++ 104, 131, 66, 7, 216, 213, 248, 80, 50, 90, 105, 1, 50, 90, 97, 0, 240, ++ 110, 190, 19, 148, 9, 159, 121, 75, 219, 93, 35, 159, 41, 147, 215, ++ 248, 68, 51, 41, 159, 3, 235, 71, 3, 155, 139, 12, 147, 12, 159, 184, ++ 248, 192, 50, 39, 177, 27, 177, 159, 66, 40, 191, 31, 70, 3, 224, 12, ++ 159, 0, 43, 24, 191, 31, 70, 12, 151, 31, 159, 79, 240, 0, 9, 63, 2, ++ 44, 151, 12, 159, 43, 70, 255, 8, 45, 151, 79, 240, 255, 55, 69, 70, ++ 205, 248, 160, 144, 205, 248, 156, 144, 205, 248, 56, 144, 205, 248, ++ 152, 144, 205, 248, 72, 144, 205, 248, 104, 144, 205, 248, 68, 144, ++ 205, 248, 136, 144, 202, 70, 205, 248, 100, 144, 205, 248, 120, 144, ++ 205, 248, 132, 144, 205, 248, 96, 144, 205, 248, 24, 144, 205, 248, ++ 92, 144, 205, 248, 116, 144, 205, 248, 88, 144, 13, 151, 205, 248, 172, ++ 144, 152, 70, 0, 240, 134, 188, 140, 139, 136, 105, 36, 5, 36, 13, 16, ++ 240, 4, 0, 4, 208, 40, 70, 113, 170, 15, 240, 229, 218, 17, 224, 43, ++ 104, 147, 248, 156, 48, 1, 43, 5, 209, 213, 248, 96, 1, 8, 153, 41, ++ 154, 32, 240, 199, 255, 0, 144, 112, 169, 40, 70, 114, 170, 113, 171, ++ 244, 247, 122, 252, 10, 144, 10, 159, 111, 179, 67, 70, 16, 55, 168, ++ 70, 29, 70, 211, 248, 80, 50, 8, 209, 90, 107, 28, 159, 1, 50, 90, 99, ++ 112, 155, 0, 38, 59, 96, 0, 240, 94, 188, 154, 107, 1, 50, 154, 99, ++ 187, 248, 94, 48, 163, 66, 17, 209, 149, 248, 225, 19, 11, 241, 75, ++ 0, 1, 57, 33, 64, 1, 52, 36, 5, 232, 243, 18, 244, 36, 13, 40, 70, 89, ++ 70, 0, 34, 254, 247, 60, 255, 171, 248, 94, 64, 28, 159, 0, 38, 62, ++ 96, 0, 240, 64, 188, 112, 155, 156, 104, 152, 248, 225, 51, 180, 248, ++ 140, 96, 1, 59, 54, 9, 51, 64, 4, 241, 122, 0, 27, 147, 236, 247, 233, ++ 254, 8, 179, 67, 70, 168, 70, 29, 70, 211, 248, 80, 50, 187, 248, 94, ++ 64, 218, 107, 1, 50, 180, 66, 218, 99, 14, 209, 1, 52, 11, 241, 75, ++ 0, 27, 153, 36, 5, 232, 243, 227, 243, 36, 13, 40, 70, 89, 70, 10, 154, ++ 254, 247, 13, 255, 171, 248, 94, 64, 11, 152, 112, 153, 1, 34, 238, ++ 247, 92, 254, 0, 38, 31, 224, 112, 155, 154, 139, 2, 244, 128, 81, 137, ++ 178, 33, 177, 34, 244, 128, 82, 1, 32, 154, 131, 43, 144, 155, 105, ++ 223, 5, 27, 212, 43, 153, 64, 70, 0, 145, 50, 70, 89, 70, 115, 171, ++ 255, 247, 125, 248, 144, 185, 67, 70, 6, 70, 112, 153, 11, 152, 1, 34, ++ 168, 70, 29, 70, 238, 247, 58, 254, 28, 159, 62, 96, 79, 240, 255, 55, ++ 10, 151, 232, 227, 138, 182, 135, 0, 84, 194, 135, 0, 112, 155, 27, ++ 153, 154, 105, 79, 246, 255, 22, 208, 5, 68, 191, 34, 244, 128, 114, ++ 154, 97, 11, 241, 67, 0, 232, 243, 116, 240, 35, 136, 30, 64, 163, 138, ++ 3, 240, 3, 3, 211, 241, 1, 3, 56, 191, 0, 35, 32, 147, 0, 35, 132, 248, ++ 72, 48, 132, 248, 73, 48, 43, 104, 147, 248, 156, 48, 1, 43, 45, 208, ++ 13, 159, 1, 55, 9, 209, 27, 159, 11, 235, 7, 3, 219, 120, 13, 147, 112, ++ 155, 155, 105, 195, 243, 64, 51, 23, 147, 13, 159, 207, 177, 31, 152, ++ 135, 66, 4, 218, 23, 159, 167, 177, 152, 248, 45, 48, 155, 177, 32, ++ 159, 231, 177, 67, 70, 168, 70, 29, 70, 79, 242, 249, 19, 51, 64, 67, ++ 240, 8, 3, 35, 128, 99, 136, 1, 38, 67, 244, 128, 83, 99, 128, 29, 150, ++ 153, 227, 1, 39, 1, 224, 1, 39, 23, 151, 22, 151, 32, 159, 63, 177, ++ 148, 248, 59, 112, 148, 248, 58, 48, 63, 2, 6, 224, 1, 39, 29, 151, ++ 148, 248, 56, 112, 148, 248, 55, 48, 63, 2, 112, 153, 255, 24, 138, ++ 105, 191, 178, 18, 244, 0, 98, 33, 208, 155, 248, 0, 48, 3, 43, 4, 208, ++ 27, 177, 8, 152, 144, 248, 231, 48, 35, 179, 67, 70, 168, 70, 29, 70, ++ 186, 177, 8, 153, 145, 248, 231, 48, 35, 185, 155, 248, 0, 48, 3, 43, ++ 0, 208, 115, 185, 148, 248, 115, 48, 132, 248, 113, 112, 35, 240, 8, ++ 3, 63, 10, 132, 248, 115, 48, 132, 248, 114, 112, 2, 224, 67, 70, 168, ++ 70, 29, 70, 38, 244, 96, 102, 38, 240, 6, 6, 54, 4, 54, 12, 38, 128, ++ 1, 38, 80, 227, 27, 154, 11, 235, 2, 3, 219, 120, 35, 177, 216, 248, ++ 80, 50, 218, 104, 1, 50, 218, 96, 148, 248, 51, 48, 11, 152, 36, 147, ++ 149, 248, 74, 54, 43, 177, 232, 243, 155, 242, 24, 153, 9, 24, 24, 145, ++ 4, 224, 236, 247, 83, 253, 24, 154, 18, 24, 24, 146, 43, 104, 147, 248, ++ 156, 48, 1, 43, 64, 240, 205, 128, 7, 152, 8, 153, 3, 105, 153, 66, ++ 3, 209, 3, 125, 15, 154, 147, 66, 9, 208, 7, 152, 15, 153, 8, 155, 1, ++ 117, 3, 97, 9, 153, 64, 70, 4, 34, 255, 247, 197, 253, 148, 248, 115, ++ 32, 7, 152, 66, 240, 8, 2, 132, 248, 115, 32, 148, 248, 112, 48, 129, ++ 126, 153, 66, 4, 209, 193, 126, 2, 240, 240, 2, 138, 66, 11, 208, 7, ++ 153, 64, 70, 139, 118, 148, 248, 115, 48, 0, 34, 35, 240, 15, 3, 203, ++ 118, 9, 153, 255, 247, 168, 253, 180, 248, 76, 48, 31, 250, 131, 249, ++ 27, 178, 0, 43, 13, 218, 64, 70, 9, 153, 1, 34, 255, 247, 156, 253, ++ 0, 35, 0, 147, 213, 248, 96, 1, 8, 153, 74, 70, 1, 35, 32, 240, 103, ++ 254, 180, 248, 140, 48, 148, 248, 112, 160, 164, 248, 74, 48, 20, 154, ++ 147, 75, 10, 240, 127, 10, 146, 248, 5, 144, 20, 34, 2, 251, 10, 51, ++ 16, 152, 90, 104, 3, 107, 70, 244, 0, 118, 154, 66, 18, 211, 3, 136, ++ 80, 70, 155, 8, 164, 248, 72, 48, 23, 240, 108, 220, 16, 153, 8, 24, ++ 131, 120, 75, 69, 6, 210, 80, 70, 23, 240, 100, 220, 16, 154, 16, 24, ++ 144, 248, 2, 144, 12, 155, 64, 70, 148, 248, 112, 16, 148, 248, 115, ++ 32, 254, 247, 70, 248, 164, 248, 82, 0, 32, 155, 83, 185, 64, 70, 148, ++ 248, 54, 16, 148, 248, 57, 32, 12, 155, 254, 247, 58, 248, 164, 248, ++ 84, 0, 4, 224, 0, 35, 132, 248, 84, 48, 132, 248, 85, 48, 79, 234, 9, ++ 35, 67, 234, 9, 9, 164, 248, 80, 144, 112, 154, 15, 152, 146, 105, 18, ++ 244, 0, 95, 8, 235, 0, 2, 10, 208, 210, 125, 66, 244, 128, 114, 164, ++ 248, 64, 32, 152, 248, 45, 32, 19, 67, 164, 248, 80, 48, 4, 224, 211, ++ 125, 44, 153, 11, 67, 164, 248, 64, 48, 43, 104, 147, 248, 156, 48, ++ 1, 43, 9, 209, 36, 154, 42, 177, 83, 28, 3, 55, 3, 235, 151, 7, 191, ++ 0, 0, 224, 4, 55, 191, 178, 7, 152, 3, 123, 99, 177, 195, 122, 211, ++ 241, 1, 3, 56, 191, 0, 35, 195, 114, 0, 35, 3, 115, 216, 248, 80, 50, ++ 218, 110, 1, 50, 218, 102, 64, 70, 57, 70, 9, 154, 253, 247, 194, 253, ++ 48, 224, 6, 153, 177, 185, 4, 241, 94, 2, 39, 146, 180, 248, 94, 48, ++ 70, 244, 2, 118, 3, 240, 252, 3, 180, 43, 4, 209, 1, 35, 70, 240, 4, ++ 6, 34, 147, 11, 224, 196, 43, 9, 209, 1, 32, 70, 244, 0, 102, 17, 144, ++ 4, 224, 70, 244, 128, 99, 79, 242, 243, 86, 30, 64, 3, 55, 79, 246, ++ 252, 115, 59, 64, 36, 159, 11, 152, 122, 28, 30, 159, 3, 235, 130, 3, ++ 255, 24, 112, 153, 30, 151, 236, 247, 66, 252, 33, 159, 56, 24, 128, ++ 178, 33, 144, 38, 128, 6, 152, 112, 154, 47, 171, 67, 248, 32, 32, 43, ++ 104, 1, 48, 147, 248, 156, 48, 6, 144, 1, 43, 0, 240, 97, 129, 1, 40, ++ 64, 240, 94, 129, 22, 159, 39, 177, 148, 248, 112, 160, 148, 248, 115, ++ 96, 178, 224, 27, 159, 148, 248, 54, 160, 11, 235, 7, 3, 219, 120, 31, ++ 159, 148, 248, 57, 96, 187, 66, 64, 242, 167, 128, 152, 248, 84, 50, ++ 0, 43, 0, 240, 162, 128, 148, 248, 112, 48, 83, 69, 0, 240, 157, 128, ++ 6, 240, 207, 6, 132, 248, 57, 96, 83, 70, 213, 248, 96, 1, 8, 153, 180, ++ 248, 76, 32, 32, 240, 171, 253, 163, 137, 199, 178, 3, 240, 7, 3, 2, ++ 59, 32, 244, 224, 41, 3, 43, 8, 216, 223, 232, 3, 240, 2, 2, 5, 5, 73, ++ 244, 128, 57, 1, 224, 73, 244, 0, 57, 9, 244, 224, 35, 179, 245, 0, ++ 63, 6, 209, 181, 248, 72, 52, 3, 244, 96, 83, 179, 245, 128, 95, 9, ++ 208, 25, 240, 64, 127, 10, 209, 9, 240, 127, 3, 22, 43, 6, 216, 12, ++ 74, 154, 64, 3, 213, 41, 244, 224, 41, 73, 244, 128, 57, 31, 47, 4, ++ 216, 7, 47, 140, 191, 0, 35, 1, 35, 14, 224, 32, 47, 10, 208, 167, 241, ++ 78, 3, 14, 43, 140, 191, 0, 35, 1, 35, 4, 224, 172, 240, 135, 0, 0, ++ 2, 16, 40, 1, 35, 219, 178, 0, 43, 55, 208, 213, 248, 116, 4, 41, 244, ++ 128, 25, 131, 120, 41, 244, 64, 121, 1, 43, 4, 217, 42, 106, 146, 249, ++ 77, 32, 1, 42, 20, 208, 9, 240, 64, 114, 178, 241, 128, 127, 29, 209, ++ 1, 43, 27, 217, 43, 106, 147, 249, 77, 48, 1, 51, 22, 209, 8, 153, 75, ++ 104, 89, 0, 18, 213, 14, 48, 2, 33, 231, 243, 46, 246, 104, 177, 6, ++ 240, 207, 6, 70, 240, 16, 6, 132, 248, 57, 96, 216, 248, 80, 50, 73, ++ 244, 128, 25, 154, 106, 1, 50, 154, 98, 6, 224, 213, 248, 116, 52, 27, ++ 123, 1, 43, 8, 191, 73, 244, 128, 121, 149, 249, 32, 50, 40, 70, 1, ++ 43, 8, 191, 73, 244, 0, 9, 73, 70, 181, 248, 72, 36, 14, 240, 248, 220, ++ 42, 240, 127, 10, 71, 234, 10, 10, 1, 39, 160, 129, 132, 248, 54, 160, ++ 40, 151, 20, 152, 79, 234, 218, 23, 10, 240, 127, 10, 208, 248, 12, ++ 144, 80, 70, 23, 240, 251, 218, 246, 9, 7, 235, 64, 3, 6, 235, 67, 3, ++ 14, 51, 88, 248, 35, 48, 153, 69, 3, 210, 20, 153, 201, 104, 25, 145, ++ 10, 224, 80, 70, 23, 240, 234, 218, 7, 235, 64, 3, 6, 235, 67, 3, 14, ++ 51, 88, 248, 35, 48, 25, 147, 12, 154, 202, 177, 147, 75, 20, 34, 54, ++ 177, 2, 251, 10, 51, 15, 177, 219, 104, 9, 224, 155, 104, 7, 224, 31, ++ 177, 2, 251, 10, 51, 91, 104, 2, 224, 2, 251, 10, 242, 155, 88, 45, ++ 159, 155, 10, 123, 67, 25, 159, 159, 66, 40, 191, 31, 70, 25, 151, 148, ++ 248, 112, 32, 2, 240, 127, 3, 67, 240, 128, 119, 26, 151, 18, 6, 32, ++ 159, 68, 191, 67, 240, 129, 115, 26, 147, 148, 248, 54, 48, 39, 177, ++ 5, 34, 179, 251, 242, 243, 18, 147, 9, 224, 3, 240, 127, 2, 66, 240, ++ 128, 119, 18, 151, 31, 6, 68, 191, 66, 240, 129, 114, 18, 146, 34, 159, ++ 23, 185, 17, 159, 0, 47, 64, 208, 26, 153, 0, 34, 35, 152, 16, 240, ++ 139, 218, 18, 153, 38, 144, 0, 34, 35, 152, 16, 240, 133, 218, 40, 159, ++ 14, 144, 0, 47, 49, 208, 14, 153, 181, 248, 72, 36, 40, 70, 148, 248, ++ 51, 144, 14, 240, 117, 220, 32, 130, 39, 159, 110, 174, 59, 136, 17, ++ 159, 40, 70, 0, 47, 12, 191, 20, 34, 14, 34, 14, 153, 0, 150, 8, 240, ++ 121, 220, 6, 34, 49, 70, 4, 241, 46, 0, 229, 247, 83, 251, 14, 159, ++ 162, 138, 79, 246, 207, 115, 23, 240, 64, 113, 132, 248, 51, 144, 2, ++ 234, 3, 3, 6, 209, 7, 240, 127, 2, 22, 42, 2, 216, 88, 72, 144, 64, ++ 0, 212, 1, 33, 67, 234, 1, 17, 161, 130, 43, 104, 147, 248, 156, 48, ++ 1, 43, 31, 208, 81, 75, 20, 34, 2, 251, 10, 51, 16, 159, 90, 104, 59, ++ 107, 154, 66, 8, 211, 80, 70, 23, 240, 80, 218, 56, 24, 131, 120, 6, ++ 152, 152, 66, 0, 240, 176, 128, 23, 159, 47, 177, 152, 248, 45, 48, ++ 6, 152, 152, 66, 0, 240, 168, 128, 20, 159, 6, 152, 123, 121, 152, 66, ++ 13, 209, 161, 224, 6, 153, 19, 159, 185, 66, 8, 211, 64, 70, 9, 153, ++ 253, 247, 30, 251, 0, 40, 0, 240, 151, 128, 63, 24, 19, 151, 6, 152, ++ 50, 40, 0, 240, 145, 128, 21, 159, 37, 152, 12, 35, 3, 251, 7, 2, 152, ++ 248, 44, 16, 210, 104, 112, 146, 73, 177, 66, 185, 254, 7, 6, 213, 39, ++ 240, 1, 7, 3, 251, 7, 3, 219, 104, 21, 151, 112, 147, 112, 153, 0, 41, ++ 107, 208, 139, 105, 88, 5, 92, 213, 139, 106, 8, 159, 187, 66, 88, 209, ++ 203, 137, 15, 159, 3, 240, 7, 3, 187, 66, 82, 209, 149, 248, 74, 54, ++ 11, 152, 19, 177, 231, 243, 191, 247, 1, 224, 236, 247, 122, 250, 235, ++ 105, 113, 154, 24, 159, 3, 235, 130, 3, 91, 104, 192, 25, 27, 104, 131, ++ 66, 5, 216, 216, 248, 80, 50, 90, 105, 1, 50, 90, 97, 67, 224, 43, 104, ++ 147, 248, 156, 48, 1, 43, 41, 208, 11, 152, 112, 153, 236, 247, 83, ++ 250, 20, 159, 59, 48, 59, 137, 30, 159, 128, 178, 152, 66, 44, 191, ++ 63, 24, 255, 24, 59, 70, 25, 159, 187, 66, 45, 216, 112, 155, 152, 248, ++ 225, 35, 155, 139, 1, 58, 27, 5, 27, 13, 19, 64, 152, 248, 44, 32, 91, ++ 68, 219, 120, 50, 177, 31, 159, 187, 66, 52, 191, 29, 159, 22, 159, ++ 47, 177, 25, 224, 13, 159, 159, 66, 1, 208, 112, 146, 22, 224, 37, 159, ++ 21, 153, 56, 29, 231, 243, 148, 246, 112, 144, 15, 224, 172, 240, 135, ++ 0, 0, 2, 16, 40, 43, 104, 147, 248, 156, 48, 1, 43, 4, 209, 64, 70, ++ 9, 153, 4, 34, 255, 247, 180, 250, 0, 35, 112, 147, 112, 153, 0, 41, ++ 127, 244, 118, 171, 67, 70, 14, 70, 168, 70, 10, 145, 29, 70, 6, 152, ++ 0, 40, 0, 240, 98, 129, 3, 224, 67, 70, 0, 38, 168, 70, 29, 70, 213, ++ 248, 80, 50, 6, 153, 90, 104, 82, 24, 90, 96, 216, 248, 0, 32, 146, ++ 248, 156, 32, 1, 42, 0, 240, 31, 129, 26, 104, 213, 248, 232, 66, 1, ++ 50, 26, 96, 68, 177, 80, 70, 23, 240, 128, 217, 44, 48, 84, 248, 32, ++ 48, 1, 51, 68, 248, 32, 48, 6, 155, 90, 30, 47, 171, 83, 248, 34, 48, ++ 79, 246, 255, 18, 155, 104, 25, 136, 10, 64, 66, 244, 192, 98, 0, 33, ++ 26, 128, 147, 248, 51, 32, 131, 248, 51, 16, 153, 138, 30, 159, 146, ++ 0, 137, 7, 194, 235, 7, 2, 5, 209, 147, 248, 59, 16, 147, 248, 58, 48, ++ 9, 2, 4, 224, 147, 248, 56, 16, 147, 248, 55, 48, 9, 2, 203, 24, 155, ++ 178, 223, 28, 39, 240, 3, 7, 223, 27, 47, 155, 215, 25, 156, 104, 59, ++ 10, 132, 248, 114, 48, 148, 248, 115, 48, 132, 248, 113, 112, 67, 240, ++ 8, 3, 132, 248, 115, 48, 227, 143, 67, 177, 64, 70, 26, 153, 58, 70, ++ 8, 240, 149, 217, 79, 240, 4, 9, 224, 135, 1, 224, 79, 240, 2, 9, 180, ++ 248, 64, 48, 75, 177, 64, 70, 18, 153, 58, 70, 8, 240, 135, 217, 164, ++ 248, 64, 0, 4, 32, 7, 144, 1, 224, 2, 33, 7, 145, 143, 75, 20, 34, 2, ++ 251, 10, 51, 16, 152, 90, 104, 3, 107, 154, 66, 9, 211, 42, 153, 33, ++ 154, 104, 90, 130, 66, 56, 191, 16, 70, 128, 8, 164, 248, 72, 0, 4, ++ 224, 0, 35, 132, 248, 72, 48, 132, 248, 73, 48, 180, 248, 2, 176, 34, ++ 155, 31, 250, 139, 252, 11, 185, 17, 152, 72, 179, 204, 243, 128, 51, ++ 141, 232, 8, 2, 17, 153, 79, 240, 1, 9, 38, 154, 26, 155, 64, 70, 205, ++ 248, 20, 192, 2, 151, 205, 248, 12, 144, 8, 240, 15, 219, 164, 248, ++ 96, 0, 7, 153, 31, 250, 139, 251, 79, 234, 219, 51, 0, 147, 1, 145, ++ 18, 155, 64, 70, 17, 153, 14, 154, 2, 151, 205, 248, 12, 144, 8, 240, ++ 253, 218, 180, 248, 96, 48, 160, 134, 227, 128, 160, 133, 221, 248, ++ 20, 192, 29, 159, 119, 179, 213, 248, 80, 50, 6, 152, 154, 105, 76, ++ 244, 128, 92, 18, 24, 154, 97, 218, 105, 1, 50, 218, 97, 148, 248, 115, ++ 48, 164, 248, 2, 192, 67, 240, 8, 3, 132, 248, 115, 48, 148, 248, 57, ++ 48, 67, 240, 8, 3, 31, 6, 132, 248, 57, 48, 16, 213, 213, 248, 80, 50, ++ 26, 106, 1, 50, 26, 98, 213, 248, 232, 114, 71, 177, 80, 70, 23, 240, ++ 180, 216, 86, 48, 7, 235, 128, 7, 123, 104, 1, 51, 123, 96, 148, 248, ++ 57, 48, 22, 224, 148, 249, 115, 48, 0, 43, 16, 218, 213, 248, 80, 50, ++ 26, 106, 1, 50, 26, 98, 213, 248, 232, 114, 71, 177, 80, 70, 23, 240, ++ 156, 216, 86, 48, 7, 235, 128, 7, 123, 104, 1, 51, 123, 96, 148, 248, ++ 115, 48, 19, 240, 48, 15, 16, 208, 213, 248, 80, 50, 90, 106, 1, 50, ++ 90, 98, 213, 248, 232, 114, 71, 177, 80, 70, 23, 240, 134, 216, 118, ++ 48, 87, 248, 32, 48, 1, 51, 71, 248, 32, 48, 13, 159, 39, 177, 213, ++ 248, 80, 50, 26, 105, 1, 50, 26, 97, 180, 248, 76, 48, 154, 178, 27, ++ 178, 0, 43, 8, 218, 13, 159, 8, 153, 251, 178, 0, 147, 216, 248, 96, ++ 1, 1, 35, 32, 240, 72, 250, 216, 248, 0, 48, 147, 248, 156, 48, 1, 43, ++ 4, 208, 46, 175, 0, 36, 221, 248, 24, 144, 35, 224, 46, 172, 0, 39, ++ 10, 224, 1, 35, 0, 147, 1, 147, 64, 70, 113, 153, 84, 248, 4, 47, 97, ++ 171, 247, 247, 232, 250, 1, 55, 6, 154, 151, 66, 241, 209, 19, 224, ++ 9, 241, 255, 51, 224, 26, 67, 66, 67, 235, 0, 3, 0, 147, 149, 249, 46, ++ 48, 64, 70, 1, 147, 113, 153, 87, 248, 4, 47, 97, 171, 247, 247, 210, ++ 250, 1, 52, 76, 69, 235, 209, 0, 46, 43, 208, 112, 155, 155, 104, 179, ++ 248, 76, 48, 154, 178, 27, 178, 0, 43, 6, 218, 0, 35, 0, 147, 216, 248, ++ 96, 1, 8, 153, 32, 240, 6, 250, 213, 248, 80, 50, 64, 70, 154, 104, ++ 113, 153, 1, 50, 154, 96, 1, 35, 0, 147, 1, 147, 112, 154, 97, 171, ++ 247, 247, 176, 250, 216, 248, 0, 48, 147, 248, 156, 48, 1, 43, 8, 209, ++ 40, 70, 9, 153, 2, 34, 255, 247, 25, 249, 2, 224, 111, 240, 15, 7, 10, ++ 151, 10, 152, 117, 176, 189, 232, 240, 143, 0, 191, 172, 240, 135, 0, ++ 45, 233, 240, 71, 208, 248, 0, 144, 20, 104, 6, 70, 144, 70, 217, 248, ++ 4, 192, 0, 44, 59, 208, 165, 106, 111, 104, 23, 244, 128, 39, 14, 209, ++ 208, 248, 80, 50, 33, 70, 154, 110, 96, 70, 1, 50, 154, 102, 1, 34, ++ 238, 247, 150, 248, 200, 248, 0, 112, 56, 70, 189, 232, 240, 135, 71, ++ 104, 239, 89, 229, 137, 5, 240, 7, 5, 54, 53, 87, 248, 37, 80, 21, 177, ++ 47, 120, 2, 47, 20, 209, 214, 248, 80, 50, 154, 110, 1, 50, 154, 102, ++ 37, 177, 181, 248, 84, 48, 1, 59, 165, 248, 84, 48, 96, 70, 33, 70, ++ 1, 34, 238, 247, 117, 248, 0, 32, 200, 248, 0, 0, 189, 232, 240, 135, ++ 153, 248, 116, 66, 52, 185, 189, 232, 240, 71, 255, 247, 207, 184, 32, ++ 70, 189, 232, 240, 135, 111, 240, 15, 0, 189, 232, 240, 135, 254, 247, ++ 244, 190, 45, 233, 240, 79, 6, 104, 137, 70, 49, 104, 31, 70, 145, 248, ++ 156, 48, 133, 176, 1, 43, 4, 70, 144, 70, 26, 209, 122, 136, 36, 35, ++ 2, 240, 7, 2, 90, 67, 2, 245, 22, 114, 131, 24, 52, 248, 2, 224, 184, ++ 136, 218, 136, 93, 136, 130, 24, 146, 178, 170, 66, 218, 128, 5, 217, ++ 14, 241, 255, 62, 197, 235, 14, 5, 82, 25, 218, 128, 218, 105, 16, 26, ++ 216, 97, 185, 241, 0, 15, 20, 208, 217, 248, 4, 48, 88, 3, 16, 213, ++ 99, 104, 89, 248, 3, 176, 184, 248, 14, 48, 3, 240, 7, 3, 54, 51, 91, ++ 248, 35, 160, 186, 241, 0, 15, 3, 208, 154, 248, 0, 48, 2, 43, 7, 209, ++ 32, 70, 65, 70, 58, 70, 0, 35, 253, 247, 2, 250, 0, 32, 47, 224, 151, ++ 249, 25, 48, 211, 177, 139, 106, 11, 37, 201, 248, 40, 48, 13, 224, ++ 1, 61, 1, 32, 237, 178, 234, 243, 41, 247, 61, 185, 32, 70, 65, 70, ++ 58, 70, 43, 70, 253, 247, 236, 249, 1, 32, 25, 224, 243, 104, 211, 248, ++ 112, 33, 209, 7, 236, 213, 211, 248, 116, 49, 0, 224, 26, 70, 141, 232, ++ 12, 0, 0, 37, 32, 70, 73, 70, 66, 70, 59, 70, 2, 149, 3, 149, 254, 247, ++ 48, 250, 48, 70, 89, 70, 82, 70, 253, 247, 65, 248, 40, 70, 5, 176, ++ 189, 232, 240, 143, 0, 0, 45, 233, 248, 67, 67, 126, 5, 70, 35, 185, ++ 33, 73, 33, 72, 230, 243, 177, 243, 58, 224, 32, 72, 30, 73, 230, 243, ++ 172, 243, 43, 104, 147, 248, 156, 48, 1, 43, 36, 209, 213, 248, 52, ++ 65, 0, 38, 27, 72, 49, 70, 180, 248, 94, 34, 180, 248, 92, 50, 230, ++ 243, 156, 243, 0, 39, 180, 248, 88, 130, 11, 224, 79, 234, 73, 1, 40, ++ 70, 15, 240, 235, 220, 57, 70, 3, 70, 74, 70, 18, 72, 230, 243, 141, ++ 243, 1, 55, 180, 248, 90, 50, 7, 235, 8, 9, 153, 69, 237, 221, 1, 54, ++ 36, 52, 4, 46, 221, 209, 213, 248, 52, 49, 11, 72, 211, 248, 80, 50, ++ 211, 248, 160, 16, 211, 248, 152, 32, 211, 248, 156, 48, 230, 243, 117, ++ 243, 0, 32, 189, 232, 248, 131, 212, 53, 4, 0, 225, 54, 4, 0, 142, 31, ++ 136, 0, 238, 54, 4, 0, 8, 55, 4, 0, 35, 55, 4, 0, 45, 233, 247, 67, ++ 152, 70, 67, 104, 7, 42, 5, 70, 207, 88, 7, 217, 208, 248, 80, 50, 211, ++ 248, 164, 32, 1, 50, 195, 248, 164, 32, 108, 224, 54, 50, 87, 248, 34, ++ 64, 0, 44, 103, 208, 148, 248, 234, 96, 3, 35, 35, 112, 46, 179, 40, ++ 224, 4, 241, 75, 9, 72, 70, 49, 70, 231, 243, 193, 241, 176, 177, 72, ++ 70, 49, 70, 4, 241, 67, 9, 231, 243, 96, 241, 72, 70, 49, 70, 231, 243, ++ 182, 241, 88, 177, 72, 70, 49, 70, 231, 243, 87, 241, 163, 25, 0, 34, ++ 218, 112, 180, 248, 84, 48, 1, 59, 164, 248, 84, 48, 40, 70, 57, 70, ++ 34, 70, 253, 247, 168, 255, 1, 54, 182, 178, 149, 248, 225, 51, 179, ++ 66, 214, 216, 180, 248, 84, 48, 27, 177, 184, 241, 0, 15, 4, 209, 49, ++ 224, 43, 104, 152, 104, 252, 243, 107, 244, 212, 248, 244, 32, 107, ++ 104, 214, 88, 162, 120, 0, 35, 54, 50, 70, 248, 34, 48, 41, 104, 162, ++ 120, 0, 147, 1, 147, 72, 104, 1, 35, 6, 241, 16, 1, 231, 243, 234, 243, ++ 43, 104, 34, 70, 211, 248, 120, 4, 12, 73, 1, 35, 15, 240, 72, 254, ++ 32, 70, 237, 247, 240, 254, 50, 104, 40, 104, 210, 248, 248, 48, 11, ++ 185, 19, 105, 219, 104, 217, 104, 0, 34, 79, 244, 0, 115, 3, 176, 189, ++ 232, 240, 67, 245, 247, 67, 185, 3, 176, 189, 232, 240, 131, 101, 180, ++ 1, 0, 240, 181, 3, 104, 133, 176, 4, 70, 1, 169, 211, 248, 36, 1, 0, ++ 34, 77, 240, 32, 218, 24, 224, 107, 104, 91, 3, 21, 213, 99, 104, 0, ++ 38, 239, 88, 215, 248, 216, 32, 82, 177, 19, 120, 1, 43, 7, 209, 178, ++ 248, 84, 32, 34, 177, 32, 70, 41, 70, 50, 70, 255, 247, 95, 255, 1, ++ 54, 246, 178, 4, 55, 8, 46, 236, 209, 35, 104, 1, 169, 211, 248, 36, ++ 1, 31, 240, 168, 254, 5, 70, 0, 40, 221, 209, 5, 176, 240, 189, 67, ++ 104, 247, 181, 207, 88, 5, 70, 14, 70, 0, 36, 34, 70, 1, 52, 1, 35, ++ 40, 70, 49, 70, 228, 178, 255, 247, 65, 255, 8, 44, 245, 209, 42, 104, ++ 0, 35, 0, 147, 80, 104, 7, 241, 16, 1, 1, 34, 231, 243, 112, 242, 254, ++ 189, 255, 247, 228, 191, 48, 181, 3, 104, 133, 176, 4, 70, 1, 169, 211, ++ 248, 36, 1, 0, 34, 77, 240, 213, 217, 6, 224, 107, 104, 90, 3, 3, 213, ++ 32, 70, 41, 70, 255, 247, 210, 255, 35, 104, 1, 169, 211, 248, 36, 1, ++ 31, 240, 111, 254, 5, 70, 0, 40, 239, 209, 32, 70, 252, 247, 98, 254, ++ 40, 70, 5, 176, 48, 189, 112, 181, 68, 104, 13, 70, 225, 66, 8, 208, ++ 14, 89, 54, 177, 255, 247, 186, 255, 48, 70, 237, 247, 99, 254, 0, 35, ++ 43, 81, 112, 189, 0, 0, 45, 233, 240, 79, 67, 104, 133, 176, 81, 248, ++ 3, 160, 146, 249, 0, 48, 5, 70, 0, 43, 14, 70, 208, 248, 0, 144, 2, ++ 218, 208, 248, 80, 50, 40, 224, 148, 121, 83, 121, 209, 120, 67, 234, ++ 4, 35, 3, 240, 60, 8, 79, 234, 152, 8, 184, 241, 7, 15, 16, 121, 25, ++ 216, 8, 241, 54, 2, 90, 248, 34, 64, 164, 177, 34, 120, 2, 42, 17, 209, ++ 81, 234, 0, 33, 10, 209, 168, 124, 195, 243, 64, 2, 144, 66, 5, 209, ++ 155, 9, 149, 248, 225, 3, 218, 178, 144, 66, 13, 210, 80, 70, 33, 70, ++ 252, 247, 254, 255, 213, 248, 80, 50, 211, 248, 164, 32, 1, 50, 195, ++ 248, 164, 32, 5, 176, 189, 232, 240, 143, 99, 112, 164, 248, 96, 32, ++ 164, 248, 248, 16, 4, 241, 252, 0, 252, 247, 68, 255, 6, 235, 72, 3, ++ 179, 248, 198, 48, 1, 34, 27, 5, 27, 13, 164, 248, 90, 48, 164, 248, ++ 94, 48, 1, 59, 27, 5, 34, 112, 27, 13, 164, 248, 92, 48, 164, 248, 88, ++ 48, 213, 248, 80, 50, 40, 70, 89, 109, 137, 24, 89, 101, 33, 70, 253, ++ 247, 213, 254, 214, 248, 248, 48, 11, 185, 51, 105, 219, 104, 218, 104, ++ 12, 32, 19, 29, 2, 147, 46, 75, 47, 70, 19, 248, 8, 16, 77, 70, 0, 251, ++ 1, 34, 146, 138, 79, 240, 0, 11, 3, 146, 161, 70, 68, 224, 223, 248, ++ 160, 224, 2, 152, 30, 248, 8, 16, 231, 243, 60, 242, 4, 70, 0, 40, 61, ++ 208, 131, 105, 89, 0, 5, 213, 130, 106, 150, 66, 2, 209, 19, 244, 128, ++ 99, 9, 208, 223, 248, 120, 224, 40, 70, 2, 153, 34, 70, 30, 248, 8, ++ 48, 240, 247, 31, 253, 7, 224, 0, 147, 40, 70, 10, 241, 16, 1, 34, 70, ++ 67, 70, 14, 240, 114, 217, 208, 185, 1, 34, 104, 104, 33, 70, 237, 247, ++ 234, 253, 43, 104, 211, 248, 136, 48, 26, 106, 1, 50, 26, 98, 215, 248, ++ 80, 50, 218, 107, 1, 50, 218, 99, 51, 105, 27, 177, 219, 104, 26, 106, ++ 1, 50, 26, 98, 214, 248, 92, 49, 1, 51, 198, 248, 92, 49, 11, 241, 1, ++ 11, 31, 250, 139, 251, 3, 155, 155, 69, 183, 209, 56, 70, 81, 70, 74, ++ 70, 0, 35, 5, 176, 189, 232, 240, 79, 253, 247, 196, 189, 72, 194, 135, ++ 0, 208, 248, 80, 50, 218, 109, 1, 50, 218, 101, 112, 71, 16, 181, 67, ++ 104, 4, 70, 200, 88, 211, 120, 3, 240, 60, 3, 155, 8, 7, 43, 7, 217, ++ 212, 248, 80, 50, 211, 248, 164, 32, 1, 50, 195, 248, 164, 32, 16, 189, ++ 146, 249, 0, 32, 0, 42, 15, 218, 54, 51, 80, 248, 35, 16, 33, 177, 11, ++ 120, 2, 43, 1, 209, 252, 247, 65, 255, 212, 248, 80, 50, 211, 248, 164, ++ 32, 1, 50, 195, 248, 164, 32, 16, 189, 1, 32, 112, 71, 45, 233, 243, ++ 65, 4, 104, 0, 34, 35, 104, 6, 70, 131, 248, 66, 32, 144, 248, 221, ++ 131, 13, 70, 79, 250, 136, 243, 179, 241, 255, 63, 8, 191, 79, 240, ++ 2, 8, 225, 177, 35, 104, 147, 248, 79, 112, 23, 240, 3, 7, 44, 208, ++ 255, 247, 227, 255, 104, 179, 184, 241, 2, 15, 16, 209, 79, 244, 0, ++ 114, 3, 35, 0, 147, 32, 70, 19, 70, 4, 33, 13, 240, 165, 221, 35, 104, ++ 64, 34, 163, 248, 96, 32, 79, 240, 1, 8, 64, 39, 6, 224, 35, 104, 6, ++ 34, 79, 240, 0, 8, 163, 248, 96, 32, 71, 70, 35, 104, 147, 248, 66, ++ 48, 171, 66, 18, 208, 214, 248, 80, 2, 0, 33, 188, 34, 230, 243, 1, ++ 241, 35, 104, 131, 248, 66, 80, 8, 224, 111, 240, 22, 5, 184, 70, 5, ++ 224, 111, 240, 22, 5, 7, 70, 128, 70, 0, 224, 0, 37, 35, 104, 147, 248, ++ 156, 32, 66, 69, 13, 208, 131, 248, 156, 128, 3, 35, 0, 147, 32, 70, ++ 2, 33, 64, 34, 59, 70, 13, 240, 110, 221, 32, 70, 1, 33, 6, 240, 90, ++ 220, 40, 70, 189, 232, 252, 129, 45, 233, 240, 65, 30, 70, 67, 104, ++ 4, 70, 81, 248, 3, 128, 21, 70, 152, 248, 4, 112, 0, 47, 51, 208, 0, ++ 104, 42, 240, 90, 222, 2, 40, 52, 220, 5, 47, 15, 216, 35, 104, 147, ++ 248, 17, 50, 91, 177, 5, 244, 224, 35, 179, 245, 0, 63, 6, 209, 235, ++ 178, 23, 43, 3, 220, 124, 51, 56, 248, 19, 0, 128, 185, 1, 35, 199, ++ 241, 16, 7, 19, 250, 7, 247, 21, 240, 64, 127, 1, 209, 232, 178, 2, ++ 224, 40, 70, 26, 240, 247, 255, 125, 30, 40, 24, 176, 251, 247, 240, ++ 6, 155, 176, 66, 24, 128, 10, 221, 134, 27, 240, 28, 72, 191, 176, 29, ++ 128, 16, 192, 178, 189, 232, 240, 129, 56, 70, 189, 232, 240, 129, 0, ++ 32, 189, 232, 240, 129, 6, 39, 218, 231, 19, 181, 8, 34, 4, 70, 0, 33, ++ 104, 70, 230, 243, 142, 240, 33, 104, 6, 34, 4, 49, 104, 70, 228, 247, ++ 8, 253, 32, 70, 72, 33, 8, 34, 107, 70, 19, 240, 142, 216, 28, 189, ++ 0, 0, 45, 233, 240, 65, 208, 248, 232, 34, 0, 37, 7, 70, 14, 70, 168, ++ 70, 43, 70, 210, 248, 176, 16, 4, 50, 0, 41, 24, 191, 152, 70, 1, 51, ++ 24, 43, 13, 68, 245, 209, 40, 240, 7, 8, 48, 70, 24, 73, 8, 241, 7, ++ 8, 230, 243, 221, 242, 5, 187, 34, 224, 215, 248, 232, 50, 4, 241, 44, ++ 2, 83, 248, 34, 32, 100, 35, 83, 67, 48, 70, 179, 251, 245, 243, 16, ++ 73, 230, 243, 205, 242, 16, 75, 35, 64, 0, 43, 3, 218, 1, 59, 99, 240, ++ 7, 3, 1, 51, 7, 43, 5, 209, 68, 69, 3, 208, 48, 70, 10, 73, 230, 243, ++ 189, 242, 1, 52, 0, 224, 0, 36, 68, 69, 220, 221, 48, 70, 7, 73, 230, ++ 243, 180, 242, 0, 32, 189, 232, 240, 129, 0, 191, 91, 55, 4, 0, 101, ++ 55, 4, 0, 7, 0, 0, 128, 112, 55, 4, 0, 236, 252, 135, 0, 45, 233, 247, ++ 79, 59, 75, 208, 248, 0, 128, 130, 70, 24, 104, 216, 248, 0, 48, 139, ++ 70, 147, 248, 156, 48, 1, 144, 1, 43, 104, 209, 186, 248, 16, 48, 67, ++ 185, 157, 248, 7, 16, 157, 248, 5, 32, 141, 248, 7, 48, 138, 24, 141, ++ 248, 5, 32, 154, 248, 12, 48, 91, 185, 154, 248, 11, 48, 67, 185, 157, ++ 248, 4, 16, 157, 248, 5, 32, 141, 248, 4, 48, 138, 24, 141, 248, 5, ++ 32, 64, 70, 210, 33, 15, 240, 126, 217, 0, 241, 50, 7, 127, 0, 4, 70, ++ 191, 178, 0, 38, 1, 35, 179, 64, 19, 234, 11, 15, 45, 208, 36, 35, 115, ++ 67, 3, 245, 22, 115, 10, 235, 3, 5, 42, 248, 3, 64, 1, 171, 243, 92, ++ 98, 30, 154, 24, 171, 114, 106, 128, 64, 70, 57, 70, 34, 70, 172, 128, ++ 236, 128, 18, 240, 232, 223, 7, 241, 4, 9, 64, 70, 185, 28, 106, 136, ++ 18, 240, 225, 223, 64, 70, 73, 70, 170, 136, 18, 240, 220, 223, 64, ++ 70, 185, 29, 234, 136, 18, 240, 215, 223, 64, 70, 7, 241, 8, 1, 0, 34, ++ 18, 240, 209, 223, 165, 248, 8, 144, 1, 171, 243, 92, 1, 54, 228, 24, ++ 10, 55, 4, 46, 164, 178, 196, 209, 218, 248, 80, 50, 0, 34, 195, 248, ++ 160, 32, 195, 248, 156, 32, 195, 248, 152, 32, 189, 232, 254, 143, 43, ++ 21, 4, 0, 16, 181, 0, 33, 4, 70, 188, 34, 208, 248, 80, 2, 229, 243, ++ 170, 247, 212, 248, 232, 2, 192, 179, 0, 33, 48, 34, 229, 243, 163, ++ 247, 212, 248, 232, 2, 0, 33, 48, 34, 48, 48, 229, 243, 156, 247, 212, ++ 248, 232, 2, 0, 33, 48, 34, 96, 48, 229, 243, 149, 247, 212, 248, 232, ++ 2, 0, 33, 40, 34, 0, 245, 52, 112, 229, 243, 141, 247, 212, 248, 232, ++ 2, 0, 33, 124, 34, 176, 48, 229, 243, 134, 247, 212, 248, 232, 2, 0, ++ 33, 124, 34, 0, 245, 174, 112, 229, 243, 126, 247, 212, 248, 232, 2, ++ 0, 33, 124, 34, 0, 245, 236, 112, 229, 243, 118, 247, 212, 248, 232, ++ 2, 0, 33, 0, 245, 21, 112, 124, 34, 229, 243, 110, 247, 0, 33, 35, 104, ++ 196, 248, 200, 19, 196, 248, 204, 19, 196, 248, 208, 19, 91, 126, 195, ++ 177, 212, 248, 232, 2, 32, 177, 0, 245, 150, 112, 48, 34, 229, 243, ++ 92, 247, 32, 104, 3, 104, 147, 248, 156, 48, 1, 43, 10, 209, 232, 33, ++ 0, 34, 18, 240, 90, 223, 32, 104, 250, 33, 0, 34, 189, 232, 16, 64, ++ 18, 240, 83, 159, 16, 189, 247, 181, 29, 70, 0, 35, 4, 70, 15, 70, 22, ++ 70, 255, 247, 2, 252, 189, 248, 32, 48, 50, 70, 0, 147, 32, 104, 43, ++ 70, 57, 70, 22, 240, 197, 221, 212, 248, 80, 50, 211, 248, 168, 32, ++ 1, 50, 195, 248, 168, 32, 254, 189, 45, 233, 240, 79, 7, 104, 11, 70, ++ 135, 176, 6, 70, 147, 70, 215, 248, 36, 1, 3, 169, 26, 70, 76, 240, ++ 144, 222, 58, 224, 99, 104, 90, 3, 55, 213, 148, 248, 36, 48, 155, 7, ++ 51, 213, 215, 248, 52, 49, 0, 37, 91, 104, 84, 248, 3, 160, 208, 70, ++ 75, 250, 5, 243, 216, 7, 95, 250, 133, 249, 33, 213, 216, 248, 216, ++ 48, 147, 177, 27, 120, 1, 59, 219, 178, 1, 43, 7, 216, 39, 35, 0, 147, ++ 48, 70, 33, 70, 74, 70, 1, 35, 255, 247, 181, 255, 48, 70, 33, 70, 74, ++ 70, 0, 35, 255, 247, 185, 251, 51, 104, 10, 241, 16, 1, 26, 104, 0, ++ 35, 0, 147, 1, 147, 80, 105, 1, 35, 42, 70, 230, 243, 249, 247, 1, 53, ++ 8, 45, 8, 241, 4, 8, 210, 209, 215, 248, 36, 1, 3, 169, 31, 240, 247, ++ 250, 4, 70, 0, 40, 188, 209, 7, 176, 189, 232, 240, 143, 48, 181, 208, ++ 248, 0, 84, 144, 248, 192, 67, 77, 89, 180, 177, 1, 42, 4, 209, 105, ++ 137, 219, 178, 11, 67, 107, 129, 48, 189, 108, 137, 226, 178, 34, 234, ++ 3, 2, 149, 249, 8, 48, 106, 129, 1, 51, 6, 209, 98, 64, 210, 178, 26, ++ 177, 189, 232, 48, 64, 255, 247, 142, 191, 48, 189, 16, 181, 144, 248, ++ 192, 51, 208, 248, 0, 68, 12, 89, 115, 177, 148, 249, 8, 48, 1, 42, ++ 8, 191, 79, 240, 255, 50, 147, 66, 6, 208, 34, 114, 34, 185, 255, 34, ++ 189, 232, 16, 64, 255, 247, 119, 191, 16, 189, 0, 0, 45, 233, 240, 79, ++ 208, 248, 0, 128, 137, 176, 5, 70, 5, 169, 216, 248, 36, 1, 0, 34, 79, ++ 240, 0, 11, 76, 240, 4, 222, 218, 70, 236, 224, 115, 104, 3, 244, 128, ++ 50, 0, 42, 24, 191, 79, 240, 1, 11, 88, 3, 64, 241, 227, 128, 216, 248, ++ 52, 49, 0, 39, 91, 104, 86, 248, 3, 144, 205, 248, 12, 144, 3, 154, ++ 210, 248, 216, 64, 0, 44, 0, 240, 205, 128, 35, 120, 3, 43, 0, 242, ++ 201, 128, 223, 232, 19, 240, 179, 0, 4, 0, 122, 0, 155, 0, 1, 35, 40, ++ 70, 73, 70, 34, 70, 253, 247, 190, 250, 148, 248, 237, 48, 0, 43, 49, ++ 208, 1, 43, 41, 209, 163, 120, 12, 34, 2, 251, 3, 147, 105, 74, 27, ++ 140, 17, 104, 155, 8, 0, 41, 1, 220, 8, 33, 17, 96, 18, 104, 79, 240, ++ 0, 10, 147, 66, 168, 191, 19, 70, 20, 224, 161, 120, 9, 241, 16, 0, ++ 2, 147, 230, 243, 205, 246, 216, 248, 0, 32, 1, 70, 80, 105, 1, 34, ++ 237, 247, 152, 250, 213, 248, 80, 34, 2, 155, 209, 107, 10, 241, 1, ++ 10, 1, 49, 209, 99, 154, 69, 232, 219, 40, 70, 33, 70, 0, 34, 253, 247, ++ 51, 251, 132, 224, 148, 248, 238, 32, 49, 42, 8, 217, 39, 35, 0, 147, ++ 40, 70, 49, 70, 58, 70, 1, 35, 255, 247, 226, 254, 119, 224, 148, 248, ++ 236, 32, 34, 177, 132, 248, 236, 48, 132, 248, 241, 48, 111, 224, 180, ++ 248, 84, 48, 35, 177, 148, 248, 241, 48, 1, 51, 132, 248, 241, 48, 64, ++ 70, 49, 70, 34, 70, 252, 247, 184, 251, 148, 248, 241, 48, 2, 43, 94, ++ 209, 213, 248, 80, 50, 40, 70, 90, 110, 49, 70, 1, 50, 90, 102, 39, ++ 35, 0, 147, 58, 70, 1, 35, 255, 247, 187, 254, 40, 70, 49, 70, 58, 70, ++ 1, 35, 255, 247, 191, 250, 74, 224, 148, 248, 239, 48, 90, 28, 3, 43, ++ 132, 248, 239, 32, 4, 221, 72, 70, 33, 70, 252, 247, 231, 251, 64, 224, ++ 150, 248, 36, 48, 217, 6, 10, 213, 170, 124, 235, 124, 0, 146, 149, ++ 248, 47, 32, 64, 70, 1, 146, 49, 70, 58, 70, 0, 240, 111, 250, 213, ++ 248, 80, 50, 26, 109, 1, 50, 26, 101, 43, 224, 148, 248, 240, 48, 90, ++ 28, 1, 43, 132, 248, 240, 32, 9, 217, 213, 248, 80, 50, 40, 70, 90, ++ 110, 49, 70, 1, 50, 90, 102, 58, 70, 1, 35, 3, 224, 40, 70, 49, 70, ++ 58, 70, 0, 35, 255, 247, 134, 250, 19, 224, 148, 248, 242, 48, 90, 28, ++ 59, 43, 132, 248, 242, 32, 12, 217, 40, 70, 73, 70, 58, 70, 0, 35, 252, ++ 247, 221, 255, 40, 177, 4, 35, 128, 248, 239, 48, 1, 224, 79, 240, 1, ++ 10, 1, 55, 3, 155, 255, 178, 4, 51, 8, 47, 3, 147, 127, 244, 37, 175, ++ 216, 248, 36, 1, 5, 169, 31, 240, 184, 249, 6, 70, 0, 40, 127, 244, ++ 10, 175, 149, 248, 224, 51, 43, 177, 187, 241, 0, 15, 3, 208, 138, 240, ++ 1, 11, 0, 224, 155, 70, 133, 248, 223, 179, 0, 32, 9, 176, 189, 232, ++ 240, 143, 28, 99, 4, 0, 45, 233, 255, 71, 0, 35, 3, 147, 13, 155, 4, ++ 70, 3, 43, 144, 70, 12, 158, 14, 159, 4, 217, 3, 168, 49, 70, 4, 34, ++ 228, 247, 254, 249, 212, 248, 0, 144, 17, 153, 72, 70, 221, 248, 12, ++ 160, 8, 240, 100, 251, 5, 70, 184, 241, 75, 15, 0, 242, 101, 129, 223, ++ 232, 24, 240, 76, 0, 81, 0, 87, 0, 98, 0, 109, 0, 113, 0, 99, 1, 123, ++ 0, 99, 1, 174, 0, 219, 0, 221, 0, 99, 1, 99, 1, 240, 0, 243, 0, 99, ++ 1, 99, 1, 254, 0, 1, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, ++ 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, ++ 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 230, ++ 0, 224, 0, 237, 0, 233, 0, 5, 1, 99, 1, 10, 1, 13, 1, 99, 1, 99, 1, ++ 31, 1, 34, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 42, 1, 45, 1, ++ 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 99, 1, 49, 1, 67, 1, ++ 217, 248, 0, 48, 147, 248, 66, 48, 29, 224, 32, 70, 157, 248, 12, 16, ++ 255, 247, 214, 251, 18, 225, 51, 120, 7, 43, 0, 242, 2, 129, 228, 24, ++ 163, 122, 56, 70, 115, 112, 49, 70, 2, 34, 221, 224, 59, 120, 7, 43, ++ 0, 242, 247, 128, 228, 24, 123, 120, 0, 51, 24, 191, 1, 35, 163, 114, ++ 234, 224, 148, 248, 39, 48, 59, 96, 230, 224, 3, 155, 7, 43, 0, 243, ++ 241, 128, 4, 43, 64, 243, 238, 128, 132, 248, 39, 48, 220, 224, 217, ++ 248, 0, 48, 147, 248, 66, 32, 0, 42, 0, 240, 219, 128, 147, 248, 67, ++ 48, 0, 43, 0, 240, 214, 128, 187, 121, 7, 43, 0, 242, 210, 128, 72, ++ 70, 41, 70, 58, 70, 31, 240, 39, 249, 0, 40, 0, 240, 205, 128, 99, 104, ++ 193, 88, 0, 41, 0, 240, 203, 128, 67, 104, 90, 3, 64, 241, 199, 128, ++ 186, 121, 2, 241, 54, 3, 81, 248, 35, 48, 0, 43, 64, 240, 182, 128, ++ 32, 70, 1, 35, 252, 247, 236, 254, 0, 40, 12, 191, 79, 240, 255, 48, ++ 0, 32, 187, 224, 217, 248, 0, 48, 147, 248, 66, 32, 0, 42, 0, 240, 168, ++ 128, 147, 248, 67, 48, 0, 43, 0, 240, 163, 128, 187, 121, 7, 43, 0, ++ 242, 159, 128, 41, 70, 72, 70, 58, 70, 31, 240, 244, 248, 1, 70, 0, ++ 40, 0, 240, 153, 128, 99, 104, 195, 88, 0, 43, 0, 240, 151, 128, 67, ++ 104, 91, 3, 64, 241, 147, 128, 251, 121, 37, 32, 0, 51, 186, 121, 24, ++ 191, 1, 35, 0, 144, 32, 70, 255, 247, 75, 253, 124, 224, 35, 122, 145, ++ 231, 3, 155, 35, 114, 119, 224, 32, 70, 157, 248, 12, 16, 252, 247, ++ 176, 248, 113, 224, 148, 248, 196, 51, 133, 231, 3, 155, 132, 248, 216, ++ 51, 106, 224, 148, 248, 216, 51, 126, 231, 148, 249, 40, 48, 123, 231, ++ 3, 155, 0, 43, 111, 208, 11, 43, 109, 220, 132, 248, 40, 48, 32, 70, ++ 252, 247, 71, 249, 89, 224, 153, 248, 190, 50, 109, 231, 3, 155, 137, ++ 248, 190, 50, 82, 224, 217, 248, 0, 48, 147, 248, 156, 48, 100, 231, ++ 148, 249, 221, 51, 97, 231, 3, 155, 90, 28, 3, 42, 84, 216, 79, 240, ++ 48, 65, 145, 64, 80, 213, 132, 248, 221, 51, 217, 248, 0, 48, 32, 70, ++ 147, 248, 66, 16, 255, 247, 14, 251, 56, 224, 148, 248, 224, 51, 76, ++ 231, 26, 241, 0, 10, 24, 191, 79, 240, 1, 10, 132, 248, 224, 163, 45, ++ 224, 148, 248, 226, 51, 65, 231, 3, 155, 132, 248, 226, 51, 38, 224, ++ 212, 248, 0, 52, 0, 33, 196, 88, 6, 34, 48, 70, 229, 243, 54, 244, 35, ++ 122, 56, 70, 51, 112, 100, 137, 49, 70, 180, 128, 6, 34, 228, 247, 173, ++ 248, 20, 224, 190, 136, 122, 136, 6, 234, 2, 3, 219, 178, 34, 234, 6, ++ 6, 246, 178, 35, 177, 32, 70, 41, 70, 1, 34, 255, 247, 65, 253, 182, ++ 177, 32, 70, 41, 70, 0, 34, 51, 70, 255, 247, 58, 253, 0, 32, 15, 224, ++ 111, 240, 24, 0, 12, 224, 111, 240, 1, 0, 9, 224, 111, 240, 29, 0, 6, ++ 224, 111, 240, 22, 0, 3, 224, 111, 240, 28, 0, 0, 224, 48, 70, 4, 176, ++ 189, 232, 240, 135, 27, 6, 16, 181, 4, 70, 7, 213, 208, 248, 80, 50, ++ 211, 248, 164, 32, 1, 50, 195, 248, 164, 32, 16, 189, 0, 35, 255, 247, ++ 179, 248, 212, 248, 80, 50, 211, 248, 172, 32, 1, 50, 195, 248, 172, ++ 32, 16, 189, 1, 41, 208, 248, 52, 49, 1, 209, 32, 34, 1, 224, 79, 244, ++ 128, 114, 163, 248, 228, 35, 112, 71, 1, 35, 252, 247, 234, 184, 0, ++ 35, 252, 247, 231, 184, 248, 181, 6, 70, 145, 177, 75, 104, 91, 3, 15, ++ 213, 67, 104, 204, 88, 100, 177, 37, 70, 4, 241, 32, 7, 213, 248, 216, ++ 32, 26, 177, 48, 104, 33, 70, 252, 247, 111, 248, 4, 53, 189, 66, 245, ++ 209, 248, 189, 127, 181, 3, 104, 4, 70, 13, 70, 211, 248, 36, 1, 1, ++ 169, 0, 34, 76, 240, 37, 219, 15, 224, 51, 105, 171, 66, 12, 209, 115, ++ 104, 90, 3, 9, 213, 99, 104, 32, 104, 241, 88, 16, 49, 14, 240, 25, ++ 254, 32, 70, 49, 70, 255, 247, 206, 255, 35, 104, 1, 169, 211, 248, ++ 36, 1, 30, 240, 182, 255, 6, 70, 0, 40, 230, 209, 127, 189, 55, 181, ++ 0, 35, 1, 147, 7, 155, 4, 70, 3, 43, 21, 70, 4, 217, 1, 168, 6, 153, ++ 4, 34, 228, 247, 17, 248, 7, 45, 9, 209, 212, 248, 52, 1, 255, 247, ++ 217, 251, 212, 248, 56, 1, 0, 240, 42, 254, 0, 32, 1, 224, 111, 240, ++ 22, 0, 62, 189, 56, 181, 4, 70, 13, 70, 208, 248, 52, 1, 255, 247, 251, ++ 250, 212, 248, 56, 1, 41, 70, 0, 240, 254, 252, 0, 32, 56, 189, 45, ++ 233, 240, 67, 144, 248, 116, 114, 135, 176, 5, 70, 12, 70, 22, 70, 153, ++ 70, 0, 47, 112, 209, 11, 105, 1, 241, 20, 8, 3, 241, 188, 2, 0, 146, ++ 9, 34, 1, 146, 5, 170, 2, 146, 208, 33, 66, 70, 194, 51, 11, 240, 136, ++ 221, 1, 70, 0, 40, 97, 208, 5, 155, 3, 34, 26, 112, 95, 112, 149, 248, ++ 62, 35, 154, 112, 58, 185, 181, 248, 62, 35, 1, 50, 165, 248, 62, 35, ++ 154, 120, 1, 50, 154, 112, 178, 0, 2, 240, 60, 2, 66, 234, 137, 25, ++ 157, 248, 56, 32, 82, 0, 2, 240, 2, 2, 73, 234, 2, 9, 157, 248, 60, ++ 32, 31, 250, 137, 249, 131, 248, 3, 144, 90, 113, 79, 234, 25, 41, 0, ++ 34, 154, 113, 131, 248, 4, 144, 4, 235, 70, 2, 178, 248, 198, 32, 18, ++ 1, 146, 178, 218, 113, 18, 10, 26, 114, 203, 137, 6, 240, 7, 2, 35, ++ 240, 7, 3, 19, 67, 203, 129, 212, 248, 248, 48, 11, 185, 35, 105, 219, ++ 104, 218, 104, 40, 70, 35, 70, 15, 240, 130, 221, 33, 105, 143, 121, ++ 247, 185, 8, 124, 232, 177, 209, 248, 4, 49, 24, 120, 200, 177, 14, ++ 75, 14, 74, 155, 93, 148, 248, 218, 0, 211, 92, 24, 65, 16, 240, 1, ++ 0, 15, 208, 40, 70, 66, 70, 59, 70, 0, 151, 1, 150, 15, 240, 118, 221, ++ 56, 70, 6, 224, 111, 240, 24, 0, 3, 224, 111, 240, 26, 0, 0, 224, 0, ++ 32, 7, 176, 189, 232, 240, 131, 138, 182, 135, 0, 84, 194, 135, 0, 45, ++ 233, 255, 71, 144, 248, 116, 162, 153, 70, 6, 70, 13, 70, 23, 70, 14, ++ 155, 186, 241, 0, 15, 3, 208, 1, 34, 26, 112, 0, 36, 78, 224, 131, 248, ++ 0, 160, 20, 33, 11, 240, 219, 220, 4, 70, 0, 40, 70, 208, 208, 248, ++ 8, 128, 111, 240, 123, 3, 136, 248, 0, 48, 5, 241, 20, 1, 6, 34, 136, ++ 248, 1, 160, 136, 248, 2, 160, 136, 248, 3, 160, 8, 241, 4, 0, 227, ++ 247, 63, 255, 41, 105, 6, 34, 8, 241, 10, 0, 194, 49, 227, 247, 56, ++ 255, 189, 248, 48, 32, 79, 242, 1, 3, 2, 240, 1, 2, 66, 234, 7, 50, ++ 19, 64, 67, 240, 4, 3, 79, 234, 9, 25, 168, 248, 16, 48, 168, 248, 18, ++ 144, 227, 137, 7, 240, 7, 7, 35, 240, 7, 3, 31, 67, 213, 248, 248, 48, ++ 231, 129, 11, 185, 43, 105, 219, 104, 3, 33, 0, 34, 141, 232, 6, 0, ++ 157, 248, 52, 32, 33, 70, 2, 146, 218, 104, 48, 70, 43, 70, 244, 247, ++ 172, 252, 0, 40, 8, 191, 0, 36, 32, 70, 4, 176, 189, 232, 240, 135, ++ 48, 181, 133, 176, 4, 70, 10, 70, 208, 248, 36, 1, 1, 169, 76, 240, ++ 234, 217, 12, 224, 107, 104, 88, 3, 9, 213, 212, 248, 52, 1, 41, 70, ++ 254, 247, 230, 255, 212, 248, 56, 1, 41, 70, 22, 240, 146, 217, 212, ++ 248, 36, 1, 1, 169, 30, 240, 127, 254, 5, 70, 0, 40, 234, 209, 5, 176, ++ 48, 189, 45, 233, 240, 79, 1, 235, 130, 3, 91, 104, 167, 176, 4, 70, ++ 136, 70, 145, 70, 14, 104, 0, 43, 96, 208, 208, 248, 56, 33, 0, 39, ++ 146, 248, 42, 80, 218, 136, 1, 61, 21, 64, 73, 224, 153, 120, 1, 57, ++ 153, 112, 33, 104, 145, 248, 213, 16, 49, 185, 41, 72, 0, 104, 80, 248, ++ 34, 112, 42, 29, 35, 248, 18, 16, 1, 34, 26, 113, 218, 136, 1, 50, 18, ++ 5, 18, 13, 218, 128, 34, 104, 146, 248, 213, 32, 34, 177, 90, 25, 0, ++ 33, 130, 248, 136, 16, 35, 224, 123, 106, 32, 70, 0, 147, 49, 70, 59, ++ 70, 3, 170, 22, 240, 169, 222, 214, 248, 16, 160, 214, 248, 48, 176, ++ 6, 241, 20, 1, 6, 34, 36, 168, 227, 247, 161, 254, 32, 70, 49, 70, 3, ++ 170, 249, 247, 180, 253, 32, 70, 81, 70, 36, 170, 91, 70, 30, 240, 98, ++ 254, 216, 177, 176, 66, 25, 209, 8, 235, 137, 3, 91, 104, 171, 177, ++ 212, 248, 56, 33, 1, 53, 146, 248, 42, 32, 1, 58, 21, 64, 173, 178, ++ 42, 29, 51, 248, 18, 32, 0, 42, 176, 209, 33, 104, 145, 248, 213, 16, ++ 33, 177, 89, 25, 145, 248, 136, 16, 1, 41, 167, 208, 39, 176, 189, 232, ++ 240, 143, 32, 7, 0, 0, 45, 233, 240, 71, 31, 70, 1, 235, 130, 3, 144, ++ 70, 90, 104, 166, 176, 5, 70, 14, 70, 12, 104, 0, 42, 91, 209, 92, 224, ++ 213, 248, 56, 49, 208, 136, 147, 248, 42, 16, 1, 57, 1, 64, 8, 29, 50, ++ 248, 16, 192, 188, 241, 0, 15, 9, 209, 40, 104, 144, 248, 213, 0, 0, ++ 40, 59, 208, 80, 24, 144, 248, 136, 0, 1, 40, 54, 209, 147, 120, 1, ++ 59, 147, 112, 43, 104, 147, 248, 213, 0, 32, 177, 81, 24, 0, 35, 129, ++ 248, 136, 48, 46, 224, 30, 75, 4, 49, 27, 104, 83, 248, 44, 48, 34, ++ 248, 17, 0, 90, 106, 40, 70, 0, 146, 33, 70, 3, 170, 22, 240, 51, 222, ++ 212, 248, 16, 144, 212, 248, 48, 160, 4, 241, 20, 1, 6, 34, 36, 168, ++ 227, 247, 43, 254, 40, 70, 33, 70, 3, 170, 249, 247, 62, 253, 40, 70, ++ 73, 70, 36, 170, 83, 70, 30, 240, 236, 253, 168, 177, 160, 66, 19, 209, ++ 6, 235, 136, 3, 90, 104, 34, 185, 14, 224, 155, 105, 217, 105, 1, 49, ++ 217, 97, 1, 35, 19, 113, 211, 136, 1, 63, 1, 51, 27, 5, 27, 13, 211, ++ 128, 191, 178, 0, 47, 162, 209, 38, 176, 189, 232, 240, 135, 32, 7, ++ 0, 0, 1, 235, 130, 3, 45, 233, 240, 67, 94, 104, 5, 70, 12, 70, 23, ++ 70, 0, 46, 47, 208, 3, 104, 147, 248, 213, 48, 27, 177, 75, 107, 147, ++ 248, 42, 48, 35, 224, 208, 248, 56, 33, 241, 136, 146, 248, 42, 192, ++ 8, 70, 12, 241, 255, 56, 31, 250, 136, 248, 10, 70, 14, 224, 2, 234, ++ 8, 9, 9, 241, 4, 9, 54, 248, 25, 144, 1, 51, 185, 241, 0, 15, 24, 191, ++ 16, 70, 1, 50, 18, 5, 155, 178, 18, 13, 99, 69, 238, 211, 67, 26, 27, ++ 5, 27, 13, 40, 70, 33, 70, 58, 70, 1, 51, 189, 232, 240, 67, 255, 247, ++ 86, 191, 189, 232, 240, 131, 2, 41, 112, 181, 4, 70, 29, 70, 115, 209, ++ 19, 248, 5, 44, 19, 248, 6, 60, 26, 67, 21, 248, 4, 60, 19, 67, 131, ++ 105, 101, 208, 26, 104, 1, 50, 26, 96, 90, 104, 1, 50, 90, 96, 21, 248, ++ 3, 44, 18, 7, 2, 212, 154, 104, 1, 50, 154, 96, 230, 105, 166, 177, ++ 21, 248, 6, 12, 0, 240, 127, 0, 32, 40, 7, 221, 160, 241, 87, 3, 1, ++ 43, 3, 217, 160, 241, 99, 3, 3, 43, 6, 216, 21, 240, 190, 220, 86, 248, ++ 32, 48, 1, 51, 70, 248, 32, 48, 21, 249, 3, 60, 0, 43, 27, 218, 163, ++ 105, 230, 105, 26, 105, 1, 50, 26, 97, 174, 177, 21, 248, 6, 12, 0, ++ 240, 127, 0, 32, 40, 7, 221, 160, 241, 87, 3, 1, 43, 3, 217, 160, 241, ++ 99, 3, 3, 43, 7, 216, 21, 240, 159, 220, 30, 48, 6, 235, 128, 6, 115, ++ 104, 1, 51, 115, 96, 21, 248, 3, 60, 19, 240, 48, 15, 36, 208, 163, ++ 105, 228, 105, 90, 105, 1, 50, 90, 97, 244, 177, 21, 248, 6, 12, 0, ++ 240, 127, 0, 32, 40, 7, 221, 160, 241, 87, 3, 1, 43, 3, 217, 160, 241, ++ 99, 3, 3, 43, 16, 216, 21, 240, 126, 220, 62, 48, 84, 248, 32, 48, 1, ++ 51, 68, 248, 32, 48, 112, 189, 90, 104, 1, 50, 90, 96, 112, 189, 131, ++ 105, 218, 104, 1, 50, 218, 96, 112, 189, 45, 233, 240, 79, 19, 140, ++ 137, 176, 8, 43, 6, 70, 136, 70, 21, 70, 146, 248, 34, 160, 4, 104, ++ 1, 208, 32, 70, 38, 224, 67, 104, 210, 248, 0, 144, 81, 248, 3, 176, ++ 147, 105, 66, 70, 153, 136, 75, 70, 1, 240, 3, 1, 255, 247, 103, 255, ++ 11, 235, 138, 3, 95, 104, 199, 185, 171, 105, 155, 136, 3, 240, 3, 3, ++ 2, 43, 12, 209, 25, 248, 3, 60, 27, 7, 8, 213, 11, 235, 74, 3, 1, 34, ++ 131, 248, 36, 32, 179, 105, 154, 105, 1, 50, 154, 97, 32, 70, 65, 70, ++ 42, 70, 249, 247, 43, 252, 90, 225, 216, 248, 4, 48, 216, 3, 18, 212, ++ 171, 105, 155, 136, 3, 240, 3, 3, 2, 43, 12, 209, 25, 248, 3, 60, 25, ++ 7, 8, 213, 11, 235, 74, 3, 1, 34, 131, 248, 36, 32, 179, 105, 154, 105, ++ 1, 50, 154, 97, 181, 248, 126, 48, 26, 7, 64, 240, 46, 129, 150, 248, ++ 42, 144, 250, 136, 27, 9, 9, 241, 255, 57, 147, 66, 9, 234, 3, 9, 69, ++ 209, 1, 34, 155, 24, 27, 5, 58, 113, 27, 13, 251, 128, 216, 248, 48, ++ 48, 6, 168, 8, 241, 20, 1, 6, 34, 4, 147, 216, 248, 16, 96, 227, 247, ++ 219, 252, 35, 104, 147, 248, 213, 48, 131, 185, 32, 70, 65, 70, 42, ++ 70, 249, 247, 234, 251, 32, 70, 49, 70, 6, 170, 4, 155, 30, 240, 152, ++ 252, 0, 40, 0, 240, 18, 129, 64, 69, 64, 240, 15, 129, 35, 104, 147, ++ 248, 213, 96, 30, 177, 190, 120, 0, 54, 24, 191, 1, 38, 32, 70, 89, ++ 70, 82, 70, 255, 247, 211, 253, 35, 104, 147, 248, 213, 48, 0, 43, 0, ++ 240, 252, 128, 0, 46, 152, 208, 0, 35, 0, 147, 1, 147, 2, 147, 32, 70, ++ 57, 70, 106, 105, 75, 70, 23, 240, 159, 216, 141, 231, 155, 26, 27, ++ 5, 122, 120, 27, 13, 147, 66, 15, 210, 9, 241, 4, 1, 55, 248, 17, 16, ++ 105, 185, 33, 104, 145, 248, 213, 16, 217, 177, 7, 235, 9, 1, 145, 248, ++ 136, 16, 1, 41, 21, 209, 2, 224, 179, 245, 0, 111, 17, 217, 0, 34, 96, ++ 104, 105, 105, 236, 247, 88, 252, 35, 104, 211, 248, 136, 48, 211, 248, ++ 188, 33, 1, 50, 195, 248, 188, 33, 179, 105, 90, 106, 1, 50, 90, 98, ++ 195, 224, 185, 120, 209, 241, 1, 0, 56, 191, 0, 32, 147, 66, 4, 144, ++ 102, 211, 194, 241, 1, 2, 155, 24, 155, 178, 32, 70, 89, 70, 82, 70, ++ 5, 147, 255, 247, 245, 253, 11, 235, 138, 3, 95, 104, 135, 179, 35, ++ 104, 147, 248, 213, 48, 171, 177, 7, 235, 9, 3, 1, 34, 131, 248, 136, ++ 32, 105, 105, 96, 104, 238, 247, 74, 249, 107, 105, 9, 241, 4, 2, 25, ++ 138, 39, 248, 18, 16, 218, 137, 111, 234, 66, 66, 111, 234, 82, 66, ++ 218, 129, 8, 224, 107, 105, 9, 241, 4, 2, 24, 136, 39, 248, 18, 0, 213, ++ 248, 128, 32, 90, 98, 187, 120, 1, 51, 187, 112, 150, 248, 41, 48, 59, ++ 185, 1, 35, 134, 248, 41, 48, 160, 104, 113, 105, 100, 34, 250, 243, ++ 242, 243, 32, 70, 89, 70, 82, 70, 255, 247, 73, 253, 35, 104, 147, 248, ++ 213, 48, 203, 177, 123, 120, 5, 153, 139, 66, 79, 240, 0, 3, 4, 210, ++ 4, 154, 141, 232, 12, 0, 1, 35, 2, 224, 4, 152, 141, 232, 9, 0, 2, 147, ++ 32, 70, 57, 70, 106, 105, 75, 70, 23, 240, 14, 216, 32, 70, 65, 70, ++ 42, 70, 249, 247, 41, 251, 179, 105, 218, 106, 1, 50, 218, 98, 84, 224, ++ 1, 49, 185, 112, 35, 104, 147, 248, 213, 48, 35, 179, 7, 235, 9, 3, ++ 1, 34, 131, 248, 136, 32, 96, 104, 105, 105, 238, 247, 239, 248, 106, ++ 105, 9, 241, 4, 3, 17, 138, 32, 70, 39, 248, 19, 16, 211, 137, 57, 70, ++ 111, 234, 67, 67, 111, 234, 83, 67, 211, 129, 4, 155, 0, 147, 0, 35, ++ 1, 147, 2, 147, 75, 70, 22, 240, 223, 223, 32, 70, 65, 70, 42, 70, 249, ++ 247, 250, 250, 8, 224, 107, 105, 213, 248, 128, 32, 24, 136, 9, 241, ++ 4, 9, 39, 248, 25, 0, 90, 98, 150, 248, 41, 48, 59, 185, 1, 35, 134, ++ 248, 41, 48, 160, 104, 113, 105, 100, 34, 250, 243, 139, 243, 179, 105, ++ 26, 106, 1, 50, 26, 98, 16, 224, 96, 104, 105, 105, 0, 34, 236, 247, ++ 147, 251, 179, 105, 48, 70, 90, 108, 65, 70, 1, 50, 90, 100, 1, 35, ++ 0, 147, 82, 70, 0, 35, 23, 240, 141, 216, 9, 176, 189, 232, 240, 143, ++ 45, 233, 240, 67, 31, 70, 3, 104, 133, 176, 147, 248, 213, 64, 5, 70, ++ 14, 70, 145, 70, 157, 248, 48, 128, 36, 177, 64, 104, 180, 33, 236, ++ 247, 81, 251, 4, 70, 40, 70, 57, 70, 66, 70, 255, 247, 153, 253, 43, ++ 104, 147, 248, 213, 48, 0, 43, 46, 208, 12, 179, 0, 35, 0, 147, 1, 147, ++ 1, 35, 2, 147, 40, 70, 79, 246, 255, 115, 73, 70, 34, 70, 22, 240, 131, ++ 223, 163, 104, 180, 51, 163, 96, 163, 137, 180, 59, 163, 129, 51, 105, ++ 147, 248, 68, 48, 132, 248, 33, 48, 214, 248, 248, 48, 168, 104, 11, ++ 185, 51, 105, 219, 104, 153, 104, 34, 70, 1, 35, 237, 247, 25, 255, ++ 1, 35, 12, 147, 213, 248, 56, 1, 57, 104, 66, 70, 0, 35, 5, 176, 189, ++ 232, 240, 67, 23, 240, 63, 152, 5, 176, 189, 232, 240, 131, 45, 233, ++ 240, 71, 5, 104, 134, 176, 43, 104, 4, 70, 27, 126, 59, 185, 144, 248, ++ 41, 32, 1, 42, 89, 209, 128, 248, 41, 48, 168, 104, 82, 224, 213, 248, ++ 36, 1, 3, 169, 0, 34, 75, 240, 60, 222, 79, 240, 0, 10, 54, 224, 115, ++ 104, 90, 3, 51, 213, 99, 104, 0, 39, 86, 248, 3, 128, 193, 70, 89, 248, ++ 4, 47, 58, 179, 147, 120, 17, 121, 0, 43, 24, 191, 79, 240, 1, 10, 25, ++ 177, 0, 35, 19, 113, 211, 112, 28, 224, 219, 177, 209, 120, 1, 49, 201, ++ 178, 209, 112, 115, 104, 19, 244, 128, 127, 20, 191, 224, 137, 32, 138, ++ 79, 240, 100, 3, 176, 251, 243, 243, 153, 66, 9, 211, 163, 105, 40, ++ 70, 153, 106, 1, 49, 153, 98, 49, 70, 67, 70, 0, 151, 255, 247, 104, ++ 255, 79, 240, 1, 10, 1, 55, 255, 178, 8, 47, 208, 209, 213, 248, 36, ++ 1, 3, 169, 30, 240, 165, 250, 6, 70, 0, 40, 192, 209, 186, 241, 0, 15, ++ 10, 209, 148, 248, 41, 48, 1, 43, 6, 209, 35, 104, 132, 248, 41, 160, ++ 152, 104, 97, 105, 250, 243, 228, 242, 6, 176, 189, 232, 240, 135, 208, ++ 248, 56, 49, 155, 105, 216, 106, 112, 71, 248, 181, 194, 105, 0, 35, ++ 7, 70, 13, 70, 30, 70, 209, 88, 4, 51, 96, 43, 14, 68, 250, 209, 40, ++ 70, 17, 73, 229, 243, 225, 240, 198, 177, 0, 36, 251, 105, 40, 70, 83, ++ 248, 36, 32, 100, 35, 83, 67, 13, 73, 179, 251, 246, 243, 229, 243, ++ 212, 240, 4, 240, 7, 3, 7, 43, 5, 209, 23, 44, 3, 208, 40, 70, 8, 73, ++ 229, 243, 202, 240, 1, 52, 24, 44, 231, 209, 40, 70, 5, 73, 229, 243, ++ 195, 240, 0, 32, 248, 189, 0, 191, 177, 56, 4, 0, 101, 55, 4, 0, 112, ++ 55, 4, 0, 236, 252, 135, 0, 45, 233, 240, 79, 67, 104, 21, 70, 203, ++ 88, 135, 176, 14, 70, 3, 147, 11, 105, 233, 121, 47, 121, 4, 145, 41, ++ 122, 66, 107, 5, 145, 233, 120, 4, 70, 65, 234, 7, 39, 7, 240, 60, 10, ++ 79, 234, 154, 10, 186, 241, 7, 15, 154, 88, 104, 121, 149, 248, 6, 144, ++ 161, 122, 4, 217, 163, 105, 90, 108, 1, 50, 90, 100, 187, 224, 64, 234, ++ 9, 41, 137, 69, 40, 191, 137, 70, 146, 249, 8, 16, 33, 177, 82, 137, ++ 66, 250, 10, 242, 210, 7, 9, 212, 171, 120, 32, 104, 49, 70, 37, 34, ++ 205, 248, 0, 144, 1, 151, 22, 240, 242, 223, 164, 224, 32, 104, 2, 104, ++ 146, 248, 66, 16, 97, 177, 146, 248, 67, 32, 74, 177, 27, 124, 19, 177, ++ 115, 104, 219, 3, 4, 213, 4, 235, 10, 3, 147, 248, 32, 48, 51, 185, ++ 171, 120, 205, 248, 0, 144, 1, 151, 49, 70, 37, 34, 50, 224, 34, 122, ++ 199, 243, 64, 3, 154, 66, 6, 208, 171, 120, 205, 248, 0, 144, 1, 151, ++ 49, 70, 38, 34, 38, 224, 82, 70, 32, 70, 49, 70, 21, 240, 169, 220, ++ 216, 32, 236, 247, 242, 249, 34, 104, 128, 70, 19, 104, 147, 248, 213, ++ 48, 43, 177, 80, 104, 180, 33, 236, 247, 252, 249, 131, 70, 0, 224, ++ 155, 70, 184, 241, 0, 15, 7, 208, 35, 104, 27, 104, 147, 248, 213, 48, ++ 131, 177, 187, 241, 0, 15, 13, 209, 171, 120, 32, 104, 205, 248, 0, ++ 144, 1, 151, 49, 70, 1, 34, 22, 240, 163, 223, 163, 105, 154, 107, 1, ++ 50, 154, 99, 81, 224, 64, 70, 0, 33, 216, 34, 228, 243, 173, 245, 32, ++ 104, 3, 104, 147, 248, 213, 48, 11, 177, 200, 248, 204, 176, 187, 9, ++ 219, 178, 148, 248, 9, 176, 19, 177, 91, 69, 56, 191, 155, 70, 7, 240, ++ 113, 255, 32, 177, 88, 69, 56, 191, 131, 70, 95, 250, 139, 251, 3, 154, ++ 4, 153, 2, 235, 138, 3, 5, 154, 195, 248, 4, 128, 65, 234, 2, 35, 27, ++ 9, 168, 248, 6, 48, 1, 35, 136, 248, 1, 176, 136, 248, 0, 48, 35, 104, ++ 7, 240, 63, 7, 27, 104, 71, 234, 139, 23, 147, 248, 213, 48, 35, 177, ++ 32, 70, 22, 240, 9, 219, 168, 248, 200, 0, 163, 105, 32, 104, 90, 107, ++ 49, 70, 1, 50, 90, 99, 79, 246, 254, 114, 58, 64, 171, 120, 1, 146, ++ 0, 34, 205, 248, 0, 144, 22, 240, 83, 223, 163, 105, 154, 107, 1, 50, ++ 154, 99, 99, 138, 1, 51, 99, 130, 7, 176, 189, 232, 240, 143, 16, 181, ++ 0, 33, 4, 70, 80, 34, 128, 105, 228, 243, 86, 245, 224, 105, 120, 177, ++ 0, 33, 124, 34, 228, 243, 80, 245, 224, 105, 0, 33, 124, 34, 124, 48, ++ 228, 243, 74, 245, 224, 105, 0, 33, 248, 48, 124, 34, 228, 243, 68, ++ 245, 32, 104, 3, 104, 147, 248, 156, 48, 1, 43, 8, 209, 67, 126, 51, ++ 177, 79, 244, 170, 113, 0, 34, 189, 232, 16, 64, 17, 240, 61, 157, 16, ++ 189, 248, 181, 12, 38, 78, 67, 7, 110, 4, 70, 189, 25, 105, 104, 33, ++ 177, 67, 104, 0, 34, 88, 105, 236, 247, 119, 249, 0, 35, 187, 81, 171, ++ 96, 107, 96, 227, 110, 26, 109, 1, 50, 26, 101, 248, 189, 16, 181, 0, ++ 33, 4, 70, 255, 247, 229, 255, 32, 70, 1, 33, 255, 247, 225, 255, 0, ++ 32, 16, 189, 55, 181, 0, 35, 1, 147, 7, 155, 5, 70, 3, 43, 20, 70, 4, ++ 217, 1, 168, 6, 153, 4, 34, 227, 247, 134, 249, 24, 44, 43, 104, 11, ++ 209, 27, 104, 2, 169, 147, 248, 68, 48, 8, 152, 65, 248, 4, 61, 10, ++ 154, 227, 247, 121, 249, 0, 32, 1, 224, 111, 240, 22, 0, 62, 189, 147, ++ 137, 45, 233, 240, 65, 45, 43, 4, 70, 136, 70, 21, 70, 7, 110, 6, 216, ++ 67, 104, 211, 248, 136, 48, 90, 110, 1, 50, 90, 102, 34, 224, 150, 104, ++ 50, 70, 50, 248, 6, 31, 23, 240, 158, 217, 32, 185, 227, 110, 90, 107, ++ 1, 50, 90, 99, 22, 224, 6, 241, 16, 0, 234, 247, 144, 249, 16, 185, ++ 51, 124, 219, 7, 6, 213, 99, 104, 211, 248, 136, 48, 90, 111, 1, 50, ++ 90, 103, 7, 224, 12, 35, 3, 251, 8, 119, 1, 32, 125, 96, 189, 96, 189, ++ 232, 240, 129, 227, 110, 0, 32, 154, 108, 1, 50, 154, 100, 189, 232, ++ 240, 129, 0, 32, 112, 71, 3, 110, 16, 181, 27, 104, 4, 70, 19, 177, ++ 0, 33, 255, 247, 124, 255, 35, 110, 219, 104, 43, 177, 32, 70, 1, 33, ++ 189, 232, 16, 64, 255, 247, 115, 191, 16, 189, 45, 233, 247, 79, 215, ++ 137, 1, 147, 67, 104, 23, 244, 0, 87, 5, 70, 139, 70, 20, 70, 211, 248, ++ 20, 160, 44, 209, 3, 104, 145, 137, 27, 104, 219, 105, 155, 110, 153, ++ 66, 37, 218, 147, 104, 82, 104, 35, 240, 127, 67, 194, 243, 20, 8, 35, ++ 244, 96, 3, 200, 235, 3, 8, 80, 70, 65, 68, 236, 247, 178, 248, 6, 70, ++ 168, 177, 128, 104, 179, 137, 64, 68, 200, 235, 3, 3, 176, 96, 179, ++ 129, 161, 104, 162, 137, 200, 241, 0, 3, 201, 24, 192, 24, 66, 68, 227, ++ 247, 242, 248, 33, 70, 80, 70, 58, 70, 236, 247, 189, 248, 52, 70, 187, ++ 248, 2, 144, 187, 248, 18, 16, 12, 38, 235, 110, 6, 251, 9, 246, 218, ++ 106, 1, 240, 6, 1, 47, 110, 73, 16, 1, 50, 2, 41, 218, 98, 7, 235, 6, ++ 8, 186, 89, 23, 208, 3, 41, 46, 208, 1, 41, 9, 209, 50, 177, 154, 107, ++ 40, 70, 1, 50, 154, 99, 73, 70, 255, 247, 24, 255, 1, 35, 43, 224, 1, ++ 42, 9, 209, 163, 137, 14, 43, 15, 217, 216, 248, 8, 48, 33, 136, 153, ++ 130, 21, 224, 1, 42, 3, 208, 154, 107, 1, 50, 154, 99, 71, 224, 3, 35, ++ 187, 81, 163, 137, 17, 43, 6, 216, 107, 104, 211, 248, 136, 48, 90, ++ 110, 1, 50, 90, 102, 59, 224, 216, 248, 8, 48, 34, 136, 154, 130, 200, ++ 248, 8, 64, 15, 224, 50, 177, 154, 107, 40, 70, 1, 50, 154, 99, 73, ++ 70, 255, 247, 235, 254, 3, 35, 187, 81, 40, 70, 73, 70, 34, 70, 255, ++ 247, 36, 255, 32, 179, 187, 89, 79, 240, 0, 4, 3, 43, 42, 209, 216, ++ 248, 4, 48, 200, 248, 8, 64, 154, 105, 200, 248, 4, 64, 66, 240, 128, ++ 2, 188, 81, 154, 97, 106, 104, 210, 248, 136, 16, 209, 248, 204, 1, ++ 1, 48, 193, 248, 204, 1, 233, 110, 8, 107, 1, 48, 8, 99, 1, 153, 1, ++ 41, 17, 208, 81, 105, 40, 104, 90, 70, 249, 247, 111, 251, 10, 224, ++ 40, 70, 73, 70, 255, 247, 186, 254, 80, 70, 33, 70, 0, 34, 236, 247, ++ 57, 248, 0, 35, 0, 224, 35, 70, 24, 70, 189, 232, 254, 143, 0, 0, 45, ++ 233, 240, 79, 137, 176, 5, 147, 3, 104, 14, 104, 3, 147, 67, 104, 4, ++ 70, 95, 105, 2, 145, 56, 70, 49, 70, 6, 146, 233, 247, 228, 255, 4, ++ 56, 1, 144, 178, 70, 53, 70, 79, 240, 0, 8, 161, 70, 209, 224, 137, ++ 76, 170, 138, 35, 104, 83, 248, 34, 48, 35, 185, 56, 70, 41, 70, 4, ++ 34, 233, 243, 171, 241, 184, 241, 100, 15, 0, 240, 198, 128, 213, 248, ++ 8, 192, 232, 137, 188, 248, 12, 48, 16, 244, 0, 80, 12, 241, 14, 12, ++ 20, 191, 181, 248, 80, 32, 2, 70, 28, 240, 3, 15, 169, 137, 5, 208, ++ 76, 70, 227, 110, 26, 108, 1, 50, 26, 100, 195, 224, 82, 24, 79, 234, ++ 19, 44, 146, 178, 76, 234, 3, 35, 4, 146, 181, 248, 20, 192, 34, 104, ++ 14, 51, 82, 248, 44, 32, 155, 178, 42, 177, 112, 74, 3, 241, 3, 12, ++ 12, 234, 2, 2, 0, 224, 26, 70, 221, 248, 16, 192, 148, 69, 5, 208, 76, ++ 70, 227, 110, 218, 107, 1, 50, 218, 99, 163, 224, 48, 177, 181, 248, ++ 80, 32, 26, 177, 91, 26, 165, 248, 80, 48, 0, 224, 171, 129, 3, 152, ++ 57, 70, 42, 70, 239, 247, 24, 249, 171, 104, 25, 136, 88, 136, 179, ++ 248, 4, 176, 64, 234, 1, 2, 91, 234, 2, 2, 0, 145, 0, 240, 138, 128, ++ 18, 154, 17, 120, 0, 41, 56, 208, 3, 153, 209, 248, 96, 38, 210, 248, ++ 48, 192, 188, 241, 0, 15, 0, 209, 19, 99, 147, 248, 0, 192, 28, 240, ++ 1, 12, 205, 248, 28, 192, 29, 209, 18, 107, 0, 153, 178, 248, 2, 192, ++ 128, 234, 12, 12, 16, 136, 72, 64, 76, 234, 0, 0, 178, 248, 4, 192, ++ 139, 234, 12, 12, 64, 234, 12, 0, 128, 178, 112, 185, 155, 137, 8, 43, ++ 14, 208, 77, 246, 134, 92, 204, 235, 3, 1, 209, 241, 0, 12, 76, 235, ++ 1, 12, 7, 224, 79, 240, 0, 12, 4, 224, 221, 248, 28, 192, 1, 224, 79, ++ 240, 1, 12, 18, 155, 131, 248, 0, 192, 34, 104, 171, 138, 82, 248, 35, ++ 48, 184, 241, 0, 15, 30, 208, 11, 177, 25, 136, 0, 224, 25, 70, 177, ++ 130, 79, 240, 0, 12, 186, 248, 22, 16, 165, 248, 20, 192, 82, 248, 33, ++ 32, 2, 177, 18, 136, 41, 136, 234, 130, 170, 248, 22, 16, 234, 137, ++ 241, 137, 34, 240, 7, 2, 1, 240, 7, 1, 10, 67, 6, 153, 234, 129, 74, ++ 104, 170, 70, 170, 98, 2, 154, 1, 153, 21, 96, 221, 248, 16, 192, 234, ++ 137, 204, 235, 1, 1, 66, 244, 128, 82, 234, 129, 8, 241, 1, 8, 1, 145, ++ 29, 70, 0, 45, 127, 244, 43, 175, 1, 155, 76, 70, 35, 177, 227, 110, ++ 90, 108, 1, 50, 90, 100, 12, 224, 37, 177, 56, 70, 41, 70, 1, 154, 235, ++ 247, 55, 255, 5, 153, 0, 32, 11, 136, 152, 68, 161, 248, 0, 128, 38, ++ 224, 20, 77, 178, 138, 43, 104, 83, 248, 34, 16, 41, 177, 0, 34, 56, ++ 70, 235, 247, 38, 255, 0, 34, 178, 130, 86, 69, 16, 209, 21, 224, 226, ++ 138, 83, 248, 34, 48, 3, 177, 27, 136, 0, 34, 243, 130, 56, 70, 33, ++ 70, 235, 247, 22, 255, 84, 69, 2, 209, 2, 155, 30, 96, 5, 224, 43, 104, ++ 242, 138, 83, 248, 34, 64, 0, 44, 233, 209, 79, 240, 255, 48, 9, 176, ++ 189, 232, 240, 143, 32, 7, 0, 0, 252, 255, 1, 0, 16, 181, 11, 70, 9, ++ 105, 134, 176, 0, 106, 185, 177, 138, 121, 170, 177, 147, 248, 36, 32, ++ 146, 7, 17, 213, 208, 248, 124, 34, 114, 177, 209, 248, 204, 32, 18, ++ 244, 0, 82, 9, 209, 0, 146, 8, 36, 2, 146, 3, 146, 4, 146, 20, 51, 12, ++ 34, 1, 148, 5, 240, 34, 220, 6, 176, 16, 189, 45, 233, 240, 79, 177, ++ 176, 221, 248, 244, 128, 155, 70, 0, 35, 15, 146, 47, 147, 8, 241, 56, ++ 2, 58, 155, 10, 146, 91, 136, 209, 248, 244, 32, 14, 147, 187, 248, ++ 0, 48, 129, 70, 3, 240, 252, 3, 163, 241, 32, 7, 123, 66, 67, 235, 7, ++ 3, 12, 70, 60, 158, 5, 106, 11, 146, 7, 147, 43, 177, 58, 155, 79, 240, ++ 48, 10, 4, 51, 9, 147, 3, 224, 7, 154, 79, 240, 16, 10, 9, 146, 0, 33, ++ 40, 34, 17, 168, 228, 243, 98, 242, 27, 168, 0, 33, 40, 34, 228, 243, ++ 93, 242, 213, 248, 92, 51, 43, 177, 17, 168, 5, 245, 87, 113, 40, 34, ++ 226, 247, 212, 254, 11, 155, 13, 241, 68, 12, 3, 241, 56, 7, 27, 170, ++ 99, 70, 0, 146, 40, 70, 58, 70, 33, 70, 205, 248, 24, 192, 13, 240, ++ 181, 218, 213, 248, 116, 52, 57, 70, 155, 120, 37, 175, 0, 34, 10, 152, ++ 25, 240, 32, 250, 56, 70, 0, 33, 32, 34, 228, 243, 55, 242, 8, 241, ++ 77, 3, 38, 147, 184, 248, 104, 48, 221, 248, 24, 192, 41, 147, 27, 171, ++ 40, 147, 45, 171, 24, 70, 0, 33, 8, 34, 205, 248, 156, 192, 6, 147, ++ 37, 150, 228, 243, 35, 242, 114, 104, 6, 155, 194, 243, 0, 66, 0, 147, ++ 141, 248, 180, 32, 33, 70, 82, 70, 0, 35, 213, 248, 124, 6, 46, 151, ++ 52, 240, 100, 222, 130, 29, 12, 146, 11, 241, 10, 3, 8, 147, 12, 155, ++ 4, 241, 188, 2, 1, 147, 47, 171, 13, 146, 0, 146, 2, 147, 7, 70, 81, ++ 70, 40, 70, 8, 154, 4, 241, 194, 3, 10, 240, 45, 220, 132, 70, 24, 185, ++ 17, 34, 168, 248, 104, 32, 223, 224, 47, 155, 0, 34, 1, 33, 25, 112, ++ 90, 112, 42, 106, 18, 104, 2, 42, 4, 209, 148, 249, 24, 33, 10, 185, ++ 33, 34, 26, 112, 33, 109, 64, 242, 55, 18, 10, 64, 50, 177, 148, 248, ++ 88, 32, 26, 177, 26, 136, 66, 240, 16, 2, 26, 128, 149, 248, 98, 36, ++ 50, 177, 42, 106, 82, 125, 26, 177, 26, 136, 66, 244, 128, 98, 26, 128, ++ 184, 248, 104, 32, 33, 70, 90, 128, 184, 248, 32, 32, 154, 128, 47, ++ 155, 45, 170, 6, 51, 141, 232, 140, 0, 47, 147, 213, 248, 124, 6, 82, ++ 70, 0, 35, 205, 248, 24, 192, 52, 240, 126, 221, 221, 248, 24, 192, ++ 0, 40, 64, 240, 145, 128, 0, 148, 152, 248, 24, 32, 227, 104, 2, 144, ++ 3, 144, 1, 146, 218, 104, 40, 70, 51, 70, 97, 70, 245, 247, 94, 254, ++ 47, 155, 6, 59, 47, 147, 179, 104, 152, 5, 12, 213, 150, 248, 36, 48, ++ 3, 240, 3, 3, 3, 43, 6, 209, 213, 248, 100, 6, 33, 70, 50, 70, 62, 240, ++ 120, 223, 129, 224, 184, 248, 104, 48, 0, 43, 125, 209, 184, 248, 32, ++ 48, 49, 70, 166, 248, 220, 48, 40, 70, 75, 240, 197, 220, 11, 154, 2, ++ 33, 146, 248, 96, 48, 14, 154, 48, 70, 147, 66, 56, 191, 19, 70, 166, ++ 248, 10, 49, 75, 240, 16, 219, 212, 248, 204, 48, 25, 3, 9, 213, 40, ++ 70, 33, 70, 5, 240, 242, 217, 1, 40, 3, 209, 40, 70, 33, 70, 39, 240, ++ 212, 223, 43, 104, 155, 106, 243, 98, 7, 155, 83, 177, 13, 152, 9, 153, ++ 6, 34, 226, 247, 215, 253, 32, 177, 72, 70, 8, 153, 226, 104, 25, 240, ++ 2, 218, 8, 153, 226, 104, 72, 70, 24, 240, 53, 223, 42, 104, 212, 248, ++ 204, 16, 146, 248, 79, 32, 17, 244, 0, 83, 24, 191, 2, 35, 18, 240, ++ 3, 2, 5, 208, 202, 4, 90, 191, 114, 104, 194, 243, 0, 66, 0, 34, 127, ++ 33, 141, 232, 6, 0, 10, 152, 6, 241, 76, 1, 0, 34, 25, 240, 128, 250, ++ 40, 70, 49, 70, 29, 240, 98, 255, 96, 105, 32, 177, 6, 241, 20, 1, 1, ++ 34, 36, 240, 123, 216, 212, 248, 204, 48, 159, 4, 4, 213, 213, 248, ++ 80, 1, 33, 70, 66, 240, 198, 220, 40, 70, 33, 70, 1, 34, 7, 240, 77, ++ 251, 12, 159, 59, 155, 58, 154, 1, 147, 47, 155, 0, 146, 2, 147, 72, ++ 70, 33, 70, 15, 154, 91, 70, 3, 151, 4, 150, 205, 248, 20, 128, 24, ++ 240, 64, 218, 5, 224, 72, 70, 33, 70, 90, 70, 67, 70, 23, 240, 203, ++ 219, 49, 176, 189, 232, 240, 143, 247, 181, 30, 70, 83, 104, 20, 70, ++ 35, 244, 0, 83, 83, 96, 17, 240, 254, 2, 5, 70, 8, 209, 1, 104, 208, ++ 248, 248, 52, 143, 106, 161, 106, 121, 26, 153, 66, 0, 217, 75, 185, ++ 0, 35, 196, 248, 236, 48, 212, 248, 168, 49, 19, 179, 42, 104, 146, ++ 106, 154, 98, 30, 224, 212, 248, 236, 48, 208, 248, 0, 21, 1, 51, 139, ++ 66, 196, 248, 236, 48, 3, 210, 1, 35, 128, 248, 252, 52, 17, 224, 148, ++ 248, 36, 48, 219, 7, 7, 213, 4, 35, 0, 147, 33, 105, 4, 241, 20, 3, ++ 1, 146, 32, 240, 43, 222, 40, 70, 33, 70, 75, 240, 97, 220, 0, 35, 179, ++ 98, 254, 189, 45, 233, 240, 67, 4, 106, 137, 176, 0, 35, 32, 70, 21, ++ 153, 221, 248, 68, 128, 22, 70, 221, 248, 64, 144, 18, 159, 5, 147, ++ 6, 147, 7, 147, 6, 240, 174, 254, 184, 241, 3, 15, 5, 70, 13, 217, 4, ++ 34, 6, 168, 73, 70, 226, 247, 55, 253, 184, 241, 7, 15, 5, 217, 7, 168, ++ 9, 241, 4, 1, 4, 34, 226, 247, 46, 253, 78, 46, 6, 154, 14, 208, 5, ++ 216, 12, 46, 17, 208, 13, 46, 64, 240, 210, 128, 34, 224, 80, 46, 0, ++ 240, 167, 128, 6, 211, 81, 46, 64, 240, 202, 128, 174, 224, 212, 248, ++ 0, 53, 15, 224, 196, 248, 0, 37, 192, 224, 184, 241, 3, 15, 20, 217, ++ 0, 42, 5, 219, 17, 70, 32, 70, 5, 170, 6, 240, 101, 254, 5, 70, 21, ++ 177, 43, 121, 59, 96, 177, 224, 5, 155, 30, 51, 64, 240, 174, 128, 61, ++ 96, 171, 224, 19, 155, 7, 43, 2, 220, 111, 240, 13, 3, 164, 224, 7, ++ 158, 3, 46, 5, 208, 166, 241, 2, 1, 78, 66, 70, 235, 1, 6, 0, 224, 0, ++ 38, 0, 42, 57, 219, 17, 70, 32, 70, 5, 170, 6, 240, 67, 254, 7, 155, ++ 5, 70, 0, 43, 48, 221, 224, 185, 5, 155, 30, 51, 44, 209, 42, 70, 43, ++ 70, 134, 240, 1, 6, 32, 70, 6, 153, 0, 150, 39, 240, 43, 222, 5, 70, ++ 24, 185, 111, 240, 26, 3, 5, 147, 29, 224, 32, 70, 41, 70, 7, 240, 1, ++ 248, 5, 144, 184, 177, 32, 70, 41, 70, 40, 240, 29, 216, 114, 224, 3, ++ 43, 2, 209, 131, 121, 43, 177, 13, 224, 2, 43, 11, 209, 131, 121, 1, ++ 43, 8, 209, 170, 121, 32, 70, 210, 241, 1, 2, 41, 70, 56, 191, 0, 34, ++ 40, 240, 229, 216, 7, 155, 3, 43, 92, 208, 2, 43, 90, 208, 53, 185, ++ 5, 154, 30, 50, 86, 209, 0, 43, 84, 209, 5, 149, 82, 224, 0, 43, 36, ++ 221, 43, 121, 0, 43, 77, 209, 35, 104, 219, 110, 154, 7, 2, 208, 111, ++ 240, 8, 3, 69, 224, 171, 121, 43, 177, 32, 70, 41, 70, 6, 240, 188, ++ 253, 5, 144, 62, 224, 213, 248, 204, 32, 18, 244, 0, 82, 2, 208, 79, ++ 240, 255, 51, 53, 224, 43, 126, 32, 70, 0, 146, 1, 146, 2, 146, 41, ++ 70, 5, 241, 25, 2, 32, 240, 140, 223, 43, 224, 107, 121, 75, 179, 32, ++ 70, 41, 70, 39, 240, 105, 222, 36, 224, 171, 121, 251, 177, 5, 245, ++ 88, 112, 1, 48, 12, 33, 228, 243, 148, 246, 0, 48, 24, 191, 1, 32, 56, ++ 96, 23, 224, 171, 121, 147, 177, 12, 33, 0, 50, 40, 70, 24, 191, 1, ++ 34, 40, 240, 248, 216, 43, 121, 99, 177, 32, 70, 41, 70, 5, 240, 136, ++ 218, 32, 70, 41, 70, 1, 34, 5, 240, 203, 218, 2, 224, 111, 240, 5, 3, ++ 5, 147, 5, 152, 1, 224, 111, 240, 22, 0, 9, 176, 189, 232, 240, 131, ++ 45, 233, 240, 79, 5, 106, 229, 176, 146, 70, 152, 70, 157, 248, 188, ++ 33, 213, 248, 104, 49, 12, 70, 9, 146, 27, 177, 155, 121, 0, 43, 64, ++ 240, 96, 129, 43, 104, 147, 248, 47, 48, 171, 177, 35, 109, 153, 7, ++ 18, 213, 148, 248, 132, 48, 123, 177, 232, 243, 185, 241, 212, 248, ++ 144, 16, 32, 240, 243, 220, 0, 40, 0, 240, 77, 129, 0, 35, 196, 248, ++ 136, 48, 196, 248, 140, 48, 132, 248, 132, 48, 163, 121, 27, 177, 35, ++ 121, 0, 43, 0, 240, 64, 129, 186, 248, 0, 48, 19, 244, 128, 67, 8, 147, ++ 99, 208, 10, 241, 10, 11, 40, 70, 33, 70, 90, 70, 29, 240, 216, 251, ++ 7, 70, 0, 40, 0, 240, 47, 129, 208, 248, 224, 48, 0, 43, 0, 240, 42, ++ 129, 152, 248, 3, 144, 157, 248, 192, 49, 79, 234, 153, 25, 11, 179, ++ 213, 248, 128, 50, 83, 248, 41, 96, 230, 177, 51, 105, 211, 177, 51, ++ 122, 195, 177, 65, 70, 3, 34, 93, 168, 226, 247, 242, 251, 93, 168, ++ 6, 241, 20, 1, 50, 105, 3, 48, 226, 247, 235, 251, 49, 105, 93, 168, ++ 3, 49, 11, 170, 235, 243, 9, 242, 110, 155, 8, 241, 4, 0, 25, 31, 11, ++ 170, 235, 243, 36, 242, 4, 235, 137, 3, 219, 110, 147, 177, 26, 105, ++ 110, 152, 65, 70, 20, 51, 242, 243, 30, 243, 192, 185, 1, 35, 0, 144, ++ 1, 147, 2, 144, 3, 144, 4, 144, 33, 70, 40, 70, 23, 34, 91, 70, 5, 240, ++ 213, 216, 215, 248, 224, 0, 235, 247, 96, 251, 0, 35, 199, 248, 224, ++ 48, 15, 38, 79, 240, 3, 11, 79, 240, 1, 9, 196, 224, 110, 154, 8, 241, ++ 4, 8, 8, 58, 110, 146, 15, 38, 1, 224, 8, 158, 55, 70, 43, 104, 184, ++ 248, 0, 144, 147, 248, 102, 49, 184, 248, 2, 176, 115, 177, 185, 241, ++ 3, 15, 11, 209, 110, 155, 9, 154, 0, 147, 1, 146, 213, 248, 80, 8, 33, ++ 70, 82, 70, 67, 70, 28, 240, 237, 254, 188, 224, 187, 241, 3, 15, 0, ++ 242, 185, 128, 8, 155, 0, 43, 90, 209, 187, 241, 1, 15, 64, 240, 174, ++ 128, 181, 248, 174, 1, 243, 247, 9, 248, 3, 28, 10, 241, 10, 2, 33, ++ 70, 24, 191, 1, 35, 40, 70, 8, 146, 29, 240, 77, 251, 1, 70, 16, 177, ++ 40, 70, 75, 240, 136, 218, 40, 70, 33, 70, 8, 154, 29, 240, 248, 251, ++ 7, 70, 0, 40, 0, 240, 148, 128, 67, 104, 218, 4, 8, 213, 42, 104, 146, ++ 248, 48, 32, 0, 42, 64, 240, 139, 128, 35, 244, 128, 83, 67, 96, 40, ++ 70, 57, 70, 13, 240, 81, 220, 185, 241, 0, 15, 3, 208, 185, 241, 1, ++ 15, 19, 209, 33, 224, 180, 249, 84, 48, 148, 249, 68, 32, 56, 70, 1, ++ 33, 27, 185, 22, 185, 75, 240, 138, 216, 1, 224, 74, 240, 27, 222, 151, ++ 248, 36, 48, 19, 240, 1, 3, 15, 209, 0, 224, 0, 35, 1, 34, 0, 147, 1, ++ 146, 2, 147, 3, 147, 4, 147, 40, 70, 33, 70, 23, 34, 8, 155, 5, 240, ++ 74, 216, 13, 38, 68, 224, 0, 46, 66, 209, 0, 33, 12, 34, 97, 168, 227, ++ 243, 179, 246, 44, 75, 0, 33, 97, 147, 43, 75, 36, 34, 98, 147, 76, ++ 171, 24, 70, 7, 147, 99, 149, 227, 243, 167, 246, 173, 248, 64, 97, ++ 85, 174, 48, 70, 0, 33, 32, 34, 205, 248, 48, 145, 205, 248, 52, 177, ++ 78, 151, 227, 243, 154, 246, 7, 155, 110, 154, 92, 147, 8, 241, 6, 3, ++ 1, 147, 147, 31, 0, 150, 2, 147, 213, 248, 124, 6, 33, 70, 176, 34, ++ 97, 171, 52, 240, 2, 219, 189, 248, 64, 97, 142, 185, 135, 177, 151, ++ 248, 36, 48, 217, 7, 12, 213, 40, 70, 33, 70, 4, 34, 10, 241, 10, 3, ++ 0, 150, 1, 150, 205, 248, 8, 144, 3, 150, 4, 150, 5, 240, 3, 216, 11, ++ 241, 1, 3, 1, 147, 0, 35, 3, 147, 4, 147, 9, 155, 32, 70, 5, 147, 10, ++ 241, 10, 1, 4, 241, 188, 2, 59, 70, 205, 248, 0, 144, 2, 150, 245, 247, ++ 70, 253, 3, 224, 14, 38, 233, 231, 1, 38, 231, 231, 101, 176, 189, 232, ++ 240, 143, 177, 136, 131, 0, 181, 136, 131, 0, 56, 181, 4, 106, 10, 114, ++ 35, 104, 13, 70, 147, 248, 60, 48, 91, 177, 1, 42, 6, 209, 209, 248, ++ 244, 48, 32, 70, 90, 142, 11, 240, 166, 255, 2, 224, 32, 70, 60, 240, ++ 242, 216, 32, 70, 38, 240, 53, 222, 132, 248, 114, 2, 40, 70, 25, 240, ++ 236, 221, 32, 70, 241, 247, 182, 254, 148, 248, 114, 34, 1, 42, 3, 216, ++ 32, 105, 1, 33, 37, 240, 159, 219, 212, 248, 112, 34, 35, 104, 18, 240, ++ 255, 31, 12, 191, 0, 34, 1, 34, 131, 248, 63, 32, 212, 248, 112, 34, ++ 35, 104, 18, 240, 255, 31, 12, 191, 0, 34, 1, 34, 131, 248, 63, 32, ++ 212, 248, 120, 1, 85, 240, 135, 223, 1, 70, 212, 248, 92, 1, 189, 232, ++ 56, 64, 7, 240, 152, 189, 240, 181, 4, 106, 135, 176, 13, 70, 0, 34, ++ 6, 70, 212, 248, 72, 1, 12, 240, 255, 253, 212, 248, 36, 1, 3, 169, ++ 42, 70, 74, 240, 108, 221, 0, 39, 8, 224, 146, 248, 36, 48, 152, 7, ++ 4, 213, 32, 70, 17, 70, 75, 240, 130, 217, 1, 55, 212, 248, 36, 1, 3, ++ 169, 29, 240, 4, 250, 2, 70, 0, 40, 238, 209, 63, 177, 3, 35, 0, 147, ++ 1, 144, 41, 70, 32, 70, 16, 75, 32, 240, 54, 219, 0, 34, 48, 70, 41, ++ 70, 255, 247, 137, 255, 32, 70, 0, 33, 11, 240, 163, 217, 4, 35, 0, ++ 33, 5, 241, 194, 2, 0, 147, 32, 70, 43, 70, 240, 247, 3, 253, 48, 70, ++ 24, 240, 73, 223, 5, 241, 188, 0, 0, 33, 6, 34, 227, 243, 201, 245, ++ 0, 32, 7, 176, 240, 189, 236, 125, 135, 0, 45, 233, 255, 65, 4, 106, ++ 5, 70, 35, 104, 147, 248, 47, 48, 11, 185, 0, 38, 62, 224, 35, 106, ++ 24, 105, 13, 240, 210, 255, 6, 70, 40, 187, 43, 138, 27, 179, 32, 70, ++ 38, 240, 165, 221, 0, 40, 30, 221, 234, 33, 32, 70, 12, 240, 39, 223, ++ 181, 248, 110, 48, 131, 66, 18, 209, 181, 248, 108, 48, 42, 138, 1, ++ 51, 155, 178, 154, 66, 165, 248, 108, 48, 11, 216, 32, 70, 165, 248, ++ 108, 96, 165, 248, 110, 96, 9, 240, 55, 223, 79, 240, 255, 48, 182, ++ 224, 165, 248, 108, 96, 165, 248, 110, 0, 212, 248, 36, 1, 1, 169, 0, ++ 34, 74, 240, 244, 220, 3, 224, 67, 104, 35, 240, 32, 3, 67, 96, 212, ++ 248, 36, 1, 1, 169, 29, 240, 146, 249, 0, 40, 244, 209, 190, 231, 212, ++ 248, 104, 50, 159, 89, 0, 47, 46, 208, 187, 121, 99, 179, 59, 121, 83, ++ 179, 215, 248, 92, 51, 27, 120, 51, 179, 215, 248, 244, 48, 91, 142, ++ 3, 244, 96, 83, 179, 245, 128, 95, 30, 209, 212, 248, 112, 4, 57, 70, ++ 69, 240, 111, 221, 128, 70, 24, 177, 56, 70, 25, 240, 140, 223, 19, ++ 224, 215, 248, 92, 51, 34, 104, 145, 106, 154, 104, 138, 26, 153, 138, ++ 91, 139, 75, 67, 154, 66, 8, 217, 56, 70, 1, 33, 25, 240, 132, 223, ++ 56, 70, 65, 70, 66, 70, 25, 240, 249, 222, 4, 54, 32, 46, 200, 209, ++ 35, 104, 147, 248, 47, 32, 0, 42, 72, 208, 212, 248, 104, 33, 10, 177, ++ 146, 121, 138, 187, 32, 70, 27, 240, 79, 216, 34, 104, 212, 248, 244, ++ 52, 145, 106, 210, 248, 40, 1, 78, 30, 48, 26, 176, 251, 243, 246, 3, ++ 251, 22, 0, 177, 251, 243, 246, 3, 251, 22, 17, 136, 66, 2, 217, 1, ++ 33, 132, 248, 252, 20, 0, 33, 194, 248, 40, 17, 43, 177, 146, 106, 178, ++ 251, 243, 241, 3, 251, 17, 35, 67, 177, 212, 248, 80, 1, 16, 177, 66, ++ 240, 221, 216, 16, 185, 148, 248, 252, 52, 91, 177, 40, 70, 24, 240, ++ 50, 217, 0, 35, 132, 248, 252, 52, 4, 224, 211, 248, 40, 33, 1, 50, ++ 195, 248, 40, 33, 149, 248, 81, 48, 27, 177, 40, 70, 2, 33, 24, 240, ++ 230, 220, 149, 248, 80, 48, 19, 177, 171, 109, 1, 51, 171, 101, 0, 37, ++ 212, 248, 104, 50, 94, 89, 142, 177, 179, 121, 123, 177, 51, 121, 107, ++ 177, 32, 70, 49, 70, 4, 240, 153, 223, 64, 177, 32, 70, 49, 70, 4, 240, ++ 142, 223, 32, 70, 49, 70, 1, 34, 4, 240, 209, 223, 4, 53, 32, 45, 230, ++ 209, 0, 32, 4, 176, 189, 232, 240, 129, 45, 233, 240, 71, 3, 104, 14, ++ 70, 147, 248, 79, 48, 7, 70, 153, 7, 104, 208, 208, 248, 104, 49, 19, ++ 177, 155, 121, 0, 43, 98, 209, 244, 104, 0, 44, 95, 209, 51, 104, 219, ++ 105, 27, 121, 67, 244, 128, 85, 14, 43, 140, 191, 79, 244, 64, 67, 0, ++ 35, 29, 67, 215, 248, 104, 50, 83, 248, 4, 128, 184, 241, 0, 15, 74, ++ 208, 152, 248, 6, 48, 0, 43, 70, 208, 152, 248, 4, 48, 0, 43, 66, 208, ++ 216, 248, 244, 48, 179, 248, 50, 144, 216, 248, 92, 51, 27, 120, 0, ++ 43, 57, 208, 72, 70, 228, 243, 26, 247, 130, 70, 40, 70, 228, 243, 22, ++ 247, 192, 235, 10, 0, 0, 40, 5, 218, 40, 70, 228, 243, 15, 247, 130, ++ 70, 72, 70, 4, 224, 72, 70, 228, 243, 9, 247, 130, 70, 40, 70, 228, ++ 243, 5, 247, 192, 235, 10, 10, 186, 241, 3, 15, 212, 191, 79, 240, 0, ++ 10, 79, 240, 1, 10, 186, 241, 0, 15, 21, 209, 64, 70, 241, 104, 25, ++ 240, 173, 221, 128, 177, 64, 70, 81, 70, 25, 240, 174, 222, 9, 244, ++ 96, 89, 64, 70, 25, 240, 161, 222, 185, 245, 128, 95, 4, 208, 1, 33, ++ 64, 70, 10, 70, 25, 240, 27, 222, 4, 52, 32, 44, 170, 209, 0, 32, 189, ++ 232, 240, 135, 0, 0, 45, 233, 240, 79, 173, 245, 1, 125, 11, 147, 3, ++ 111, 128, 70, 203, 88, 13, 70, 10, 146, 6, 106, 108, 34, 44, 168, 0, ++ 33, 139, 156, 14, 147, 227, 243, 80, 244, 138, 155, 10, 152, 48, 147, ++ 157, 248, 48, 50, 11, 154, 141, 248, 200, 48, 180, 248, 220, 48, 46, ++ 144, 47, 146, 205, 248, 176, 128, 45, 149, 49, 148, 35, 185, 32, 105, ++ 39, 240, 178, 220, 164, 248, 220, 0, 180, 248, 220, 0, 213, 248, 244, ++ 32, 173, 248, 208, 0, 13, 146, 0, 33, 40, 34, 71, 168, 227, 243, 46, ++ 244, 10, 155, 11, 152, 31, 136, 0, 136, 7, 240, 252, 7, 167, 241, 32, ++ 14, 222, 241, 0, 7, 71, 235, 14, 7, 123, 1, 12, 147, 148, 248, 36, 48, ++ 173, 248, 36, 0, 3, 240, 3, 3, 3, 43, 31, 250, 128, 251, 3, 209, 163, ++ 104, 152, 5, 0, 241, 13, 130, 214, 248, 104, 49, 27, 177, 155, 121, ++ 0, 43, 64, 240, 35, 130, 51, 104, 147, 248, 47, 48, 171, 177, 43, 109, ++ 153, 7, 18, 213, 149, 248, 132, 48, 123, 177, 231, 243, 7, 246, 213, ++ 248, 144, 16, 32, 240, 65, 217, 0, 40, 0, 240, 22, 130, 0, 35, 197, ++ 248, 136, 48, 197, 248, 140, 48, 133, 248, 132, 48, 39, 177, 138, 152, ++ 9, 40, 64, 242, 4, 130, 9, 224, 138, 154, 3, 42, 64, 242, 255, 129, ++ 11, 155, 162, 241, 4, 10, 3, 241, 4, 9, 5, 224, 11, 152, 138, 154, 0, ++ 241, 10, 9, 162, 241, 10, 10, 0, 39, 186, 241, 1, 15, 164, 248, 68, ++ 112, 167, 100, 205, 248, 224, 144, 205, 248, 228, 160, 205, 248, 216, ++ 144, 64, 243, 229, 129, 153, 248, 1, 48, 2, 51, 154, 69, 192, 242, 223, ++ 129, 57, 70, 12, 34, 125, 168, 227, 243, 194, 243, 163, 75, 57, 70, ++ 125, 147, 163, 75, 36, 34, 126, 147, 101, 171, 24, 70, 8, 147, 127, ++ 150, 227, 243, 182, 243, 81, 170, 13, 245, 220, 124, 102, 146, 91, 170, ++ 103, 146, 96, 70, 57, 70, 32, 34, 205, 248, 28, 192, 101, 148, 173, ++ 248, 180, 113, 227, 243, 166, 243, 8, 155, 221, 248, 28, 192, 117, 147, ++ 51, 104, 41, 70, 147, 248, 79, 48, 205, 248, 0, 192, 3, 240, 3, 3, 205, ++ 248, 4, 144, 205, 248, 8, 160, 141, 248, 208, 49, 214, 248, 124, 6, ++ 12, 154, 125, 171, 52, 240, 6, 216, 0, 40, 64, 240, 163, 129, 189, 248, ++ 36, 0, 189, 248, 180, 49, 164, 248, 8, 1, 212, 248, 240, 0, 12, 147, ++ 56, 177, 65, 120, 2, 49, 228, 243, 49, 247, 194, 27, 80, 66, 64, 235, ++ 2, 0, 9, 144, 9, 154, 48, 70, 141, 248, 210, 32, 81, 169, 91, 170, 71, ++ 171, 5, 240, 95, 216, 0, 40, 64, 240, 107, 129, 150, 248, 12, 37, 157, ++ 248, 48, 49, 154, 66, 64, 240, 100, 129, 148, 248, 36, 48, 155, 7, 11, ++ 213, 148, 248, 231, 48, 35, 177, 48, 70, 33, 70, 1, 34, 0, 240, 24, ++ 251, 32, 70, 254, 33, 74, 240, 135, 218, 149, 249, 68, 16, 0, 41, 192, ++ 242, 87, 129, 148, 248, 36, 48, 223, 7, 64, 241, 82, 129, 4, 241, 32, ++ 0, 228, 243, 233, 241, 0, 40, 0, 240, 75, 129, 51, 104, 147, 248, 173, ++ 48, 75, 177, 214, 248, 116, 1, 17, 240, 188, 216, 2, 40, 3, 209, 27, ++ 244, 128, 127, 0, 240, 51, 129, 109, 34, 16, 168, 0, 33, 227, 243, 49, ++ 243, 0, 35, 221, 248, 28, 225, 26, 70, 18, 224, 128, 168, 193, 24, 17, ++ 248, 224, 28, 1, 240, 127, 1, 108, 41, 9, 216, 86, 72, 64, 92, 48, 177, ++ 16, 175, 64, 178, 121, 84, 50, 234, 32, 2, 40, 191, 1, 34, 1, 51, 115, ++ 69, 234, 209, 97, 104, 51, 106, 33, 240, 7, 1, 97, 96, 88, 125, 18, ++ 241, 0, 12, 24, 191, 79, 240, 1, 12, 24, 177, 18, 185, 65, 240, 1, 1, ++ 97, 96, 91, 125, 51, 177, 27, 244, 128, 111, 3, 209, 99, 104, 67, 240, ++ 2, 3, 99, 96, 27, 240, 32, 2, 15, 146, 3, 208, 99, 104, 67, 240, 4, ++ 3, 99, 96, 13, 155, 154, 107, 0, 35, 13, 224, 13, 152, 193, 24, 145, ++ 248, 60, 16, 8, 6, 6, 213, 1, 240, 127, 1, 16, 168, 65, 92, 0, 41, 0, ++ 240, 228, 128, 1, 51, 147, 66, 239, 209, 51, 104, 147, 248, 79, 48, ++ 159, 7, 42, 208, 104, 153, 65, 179, 74, 120, 48, 70, 2, 50, 205, 248, ++ 28, 192, 53, 240, 222, 220, 0, 34, 7, 70, 0, 146, 48, 70, 33, 70, 58, ++ 70, 0, 35, 240, 247, 173, 250, 221, 248, 28, 192, 175, 177, 76, 168, ++ 16, 34, 1, 48, 249, 28, 225, 247, 66, 255, 76, 170, 0, 35, 241, 24, ++ 145, 248, 229, 18, 18, 248, 1, 15, 8, 64, 136, 66, 64, 240, 182, 128, ++ 1, 51, 16, 43, 243, 209, 79, 240, 2, 12, 14, 155, 156, 69, 192, 240, ++ 173, 128, 181, 248, 90, 32, 34, 177, 41, 109, 64, 242, 55, 19, 11, 64, ++ 19, 185, 43, 109, 88, 6, 12, 213, 180, 248, 68, 48, 35, 177, 161, 108, ++ 64, 242, 55, 19, 11, 64, 35, 185, 43, 109, 19, 240, 65, 15, 0, 240, ++ 157, 128, 27, 240, 16, 15, 30, 208, 41, 109, 64, 242, 55, 19, 11, 64, ++ 203, 185, 73, 6, 1, 213, 9, 152, 168, 177, 48, 70, 10, 158, 0, 35, 1, ++ 34, 0, 147, 1, 146, 2, 147, 3, 147, 4, 147, 41, 70, 23, 34, 6, 241, ++ 10, 3, 4, 240, 9, 220, 128, 224, 189, 134, 131, 0, 109, 136, 131, 0, ++ 224, 248, 135, 0, 234, 177, 42, 109, 64, 242, 55, 19, 19, 64, 195, 177, ++ 211, 7, 22, 213, 148, 248, 230, 48, 1, 43, 18, 209, 180, 248, 68, 48, ++ 123, 177, 5, 241, 188, 3, 0, 147, 5, 241, 194, 3, 1, 147, 2, 39, 48, ++ 70, 41, 70, 34, 70, 4, 241, 20, 3, 2, 151, 13, 240, 20, 220, 92, 224, ++ 51, 104, 147, 248, 48, 48, 75, 185, 51, 106, 27, 104, 2, 43, 5, 209, ++ 149, 249, 24, 49, 19, 185, 15, 152, 0, 40, 71, 208, 51, 106, 27, 104, ++ 2, 43, 5, 209, 152, 248, 0, 48, 19, 177, 27, 244, 128, 111, 63, 208, ++ 48, 70, 3, 240, 92, 223, 216, 248, 48, 48, 152, 66, 58, 210, 48, 70, ++ 41, 70, 4, 240, 170, 218, 213, 248, 128, 48, 152, 66, 50, 210, 213, ++ 248, 204, 48, 159, 4, 7, 213, 214, 248, 80, 1, 33, 70, 74, 70, 83, 70, ++ 66, 240, 127, 216, 64, 187, 12, 154, 71, 169, 173, 248, 24, 33, 58, ++ 168, 40, 34, 225, 247, 154, 254, 1, 35, 141, 248, 216, 49, 4, 241, 20, ++ 1, 0, 35, 6, 34, 119, 168, 173, 248, 218, 49, 44, 175, 225, 247, 141, ++ 254, 48, 70, 41, 70, 118, 170, 35, 70, 0, 151, 23, 240, 84, 220, 34, ++ 224, 30, 39, 10, 224, 22, 39, 8, 224, 18, 39, 6, 224, 19, 39, 4, 224, ++ 25, 39, 2, 224, 17, 39, 0, 224, 12, 39, 11, 158, 44, 171, 0, 150, 138, ++ 158, 3, 147, 64, 70, 41, 70, 118, 170, 10, 155, 173, 248, 24, 113, 1, ++ 150, 2, 148, 254, 247, 87, 255, 5, 224, 64, 70, 41, 70, 10, 154, 44, ++ 171, 22, 240, 154, 220, 13, 245, 1, 125, 189, 232, 240, 143, 2, 75, ++ 0, 240, 15, 0, 83, 248, 32, 0, 112, 71, 240, 114, 4, 0, 56, 181, 208, ++ 248, 4, 53, 145, 248, 218, 0, 12, 70, 157, 105, 56, 177, 255, 247, 238, ++ 255, 1, 70, 96, 25, 189, 232, 56, 64, 228, 243, 52, 178, 56, 189, 56, ++ 181, 208, 248, 4, 53, 145, 248, 218, 0, 12, 70, 15, 40, 157, 105, 10, ++ 208, 192, 67, 0, 240, 15, 0, 255, 247, 217, 255, 1, 70, 96, 25, 189, ++ 232, 56, 64, 228, 243, 31, 178, 0, 32, 56, 189, 112, 181, 20, 70, 209, ++ 248, 248, 32, 5, 70, 10, 185, 10, 105, 210, 104, 9, 125, 210, 104, 201, ++ 7, 213, 248, 4, 5, 3, 212, 65, 104, 9, 177, 1, 57, 65, 96, 161, 105, ++ 40, 70, 33, 240, 1, 1, 161, 97, 17, 29, 34, 70, 237, 247, 10, 253, 6, ++ 70, 48, 185, 104, 104, 33, 70, 1, 34, 234, 247, 221, 253, 48, 70, 112, ++ 189, 1, 32, 112, 189, 45, 233, 240, 65, 208, 248, 4, 53, 10, 105, 159, ++ 105, 146, 249, 68, 32, 27, 104, 79, 244, 136, 116, 177, 248, 220, 80, ++ 4, 251, 2, 52, 145, 248, 218, 48, 173, 4, 128, 70, 14, 70, 207, 25, ++ 173, 12, 11, 177, 15, 43, 1, 209, 248, 136, 1, 224, 255, 247, 167, 255, ++ 0, 40, 151, 248, 203, 48, 20, 221, 0, 43, 84, 209, 32, 70, 41, 70, 228, ++ 243, 44, 243, 180, 248, 252, 48, 157, 66, 0, 211, 11, 185, 164, 248, ++ 252, 80, 180, 248, 254, 48, 171, 66, 56, 191, 164, 248, 254, 80, 1, ++ 35, 52, 224, 0, 43, 63, 208, 32, 70, 41, 70, 227, 243, 149, 247, 212, ++ 248, 4, 49, 35, 185, 164, 248, 254, 48, 164, 248, 252, 48, 37, 224, ++ 180, 248, 254, 48, 171, 66, 11, 209, 5, 224, 32, 70, 41, 70, 227, 243, ++ 222, 247, 0, 40, 37, 209, 1, 61, 173, 178, 0, 45, 245, 209, 30, 224, ++ 180, 248, 252, 48, 171, 66, 17, 209, 1, 53, 9, 224, 32, 70, 41, 70, ++ 227, 243, 205, 247, 16, 177, 164, 248, 252, 80, 7, 224, 1, 53, 173, ++ 178, 216, 248, 0, 48, 219, 105, 27, 105, 157, 66, 239, 219, 0, 35, 135, ++ 248, 203, 48, 49, 105, 64, 70, 189, 232, 240, 65, 4, 240, 192, 155, ++ 164, 248, 252, 80, 164, 248, 254, 80, 241, 231, 189, 232, 240, 129, ++ 56, 181, 208, 248, 4, 53, 5, 70, 155, 105, 12, 70, 203, 24, 147, 248, ++ 220, 48, 19, 185, 255, 247, 45, 255, 40, 185, 40, 70, 33, 70, 189, 232, ++ 56, 64, 25, 240, 208, 156, 148, 248, 218, 0, 255, 247, 26, 255, 33, ++ 70, 2, 70, 32, 35, 40, 70, 25, 240, 156, 222, 40, 185, 40, 70, 33, 70, ++ 189, 232, 56, 64, 25, 240, 23, 157, 56, 189, 11, 104, 10, 121, 25, 105, ++ 137, 121, 65, 177, 145, 7, 6, 213, 147, 248, 36, 32, 146, 7, 2, 212, ++ 25, 70, 255, 247, 83, 191, 112, 71, 45, 233, 240, 79, 208, 248, 4, 117, ++ 133, 176, 187, 105, 128, 70, 205, 24, 234, 136, 12, 70, 0, 42, 76, 208, ++ 49, 248, 3, 176, 79, 240, 0, 10, 11, 241, 255, 54, 60, 224, 49, 70, ++ 40, 70, 228, 243, 66, 241, 131, 105, 2, 70, 217, 7, 11, 212, 67, 240, ++ 1, 3, 131, 97, 185, 241, 0, 15, 8, 191, 129, 70, 49, 70, 40, 70, 228, ++ 243, 137, 241, 29, 224, 123, 104, 11, 177, 1, 59, 123, 96, 251, 104, ++ 1, 51, 251, 96, 4, 241, 20, 3, 147, 232, 3, 0, 35, 105, 2, 144, 173, ++ 248, 12, 16, 64, 70, 33, 70, 1, 147, 25, 240, 56, 222, 1, 155, 64, 70, ++ 25, 70, 2, 170, 28, 240, 226, 252, 16, 185, 21, 224, 79, 240, 0, 9, ++ 12, 35, 3, 251, 11, 83, 83, 68, 83, 248, 4, 60, 75, 69, 197, 209, 1, ++ 62, 170, 241, 12, 10, 114, 28, 240, 209, 149, 248, 203, 48, 27, 177, ++ 64, 70, 33, 70, 255, 247, 249, 254, 5, 176, 189, 232, 240, 143, 45, ++ 233, 243, 65, 5, 70, 213, 248, 4, 101, 12, 70, 183, 105, 1, 241, 20, ++ 3, 147, 232, 3, 0, 212, 248, 16, 128, 0, 144, 173, 248, 4, 16, 231, ++ 25, 24, 224, 35, 125, 219, 7, 3, 212, 115, 104, 11, 177, 1, 59, 115, ++ 96, 139, 105, 104, 104, 35, 240, 1, 3, 139, 97, 1, 34, 234, 247, 174, ++ 252, 157, 248, 0, 48, 216, 7, 5, 212, 40, 70, 65, 70, 106, 70, 28, 240, ++ 157, 252, 128, 177, 0, 33, 56, 70, 227, 243, 230, 247, 1, 70, 0, 40, ++ 223, 209, 180, 248, 220, 48, 51, 177, 151, 248, 203, 48, 27, 177, 40, ++ 70, 33, 70, 255, 247, 186, 254, 189, 232, 252, 129, 45, 233, 255, 71, ++ 208, 248, 4, 53, 146, 70, 158, 105, 15, 105, 142, 25, 150, 248, 221, ++ 32, 4, 70, 13, 70, 211, 248, 0, 192, 151, 248, 68, 144, 0, 42, 115, ++ 209, 79, 244, 136, 126, 79, 250, 137, 249, 14, 251, 9, 201, 79, 240, ++ 1, 8, 134, 248, 221, 128, 217, 248, 4, 225, 14, 241, 255, 62, 201, 248, ++ 4, 225, 211, 248, 28, 224, 14, 241, 255, 62, 195, 248, 28, 224, 129, ++ 248, 231, 32, 3, 34, 15, 240, 202, 220, 217, 248, 4, 49, 35, 187, 215, ++ 248, 204, 48, 19, 244, 128, 99, 31, 209, 215, 248, 244, 32, 82, 142, ++ 2, 244, 64, 66, 162, 245, 64, 64, 66, 66, 66, 235, 0, 2, 14, 50, 7, ++ 235, 130, 2, 82, 104, 130, 248, 231, 48, 227, 105, 179, 249, 36, 48, ++ 91, 177, 148, 248, 117, 50, 67, 185, 64, 34, 0, 147, 132, 248, 117, ++ 130, 32, 70, 65, 70, 19, 70, 10, 240, 118, 220, 79, 240, 0, 8, 32, 70, ++ 41, 70, 134, 248, 200, 128, 134, 248, 202, 128, 25, 240, 14, 220, 198, ++ 248, 208, 128, 5, 241, 20, 3, 147, 232, 3, 0, 2, 144, 173, 248, 12, ++ 16, 186, 241, 0, 15, 9, 209, 32, 70, 41, 70, 79, 246, 255, 114, 0, 35, ++ 25, 240, 121, 221, 0, 40, 246, 209, 3, 224, 32, 70, 41, 70, 255, 247, ++ 73, 255, 157, 248, 8, 48, 217, 7, 5, 212, 32, 70, 57, 70, 2, 170, 28, ++ 240, 7, 252, 16, 177, 0, 35, 134, 248, 221, 48, 189, 232, 255, 135, ++ 45, 233, 240, 65, 208, 248, 4, 117, 180, 176, 187, 105, 6, 70, 13, 70, ++ 1, 235, 3, 8, 1, 168, 16, 33, 128, 34, 227, 243, 190, 247, 36, 224, ++ 43, 125, 217, 7, 3, 212, 123, 104, 11, 177, 1, 59, 123, 96, 99, 107, ++ 26, 1, 5, 212, 1, 168, 51, 153, 34, 70, 228, 243, 110, 240, 20, 224, ++ 163, 105, 41, 70, 35, 240, 1, 3, 163, 97, 34, 70, 1, 35, 48, 70, 237, ++ 247, 39, 254, 48, 70, 2, 33, 34, 70, 0, 35, 237, 247, 161, 254, 48, ++ 70, 41, 70, 34, 70, 25, 240, 28, 221, 64, 70, 51, 169, 227, 243, 22, ++ 247, 4, 70, 0, 40, 211, 209, 14, 224, 53, 185, 51, 104, 17, 70, 88, ++ 105, 1, 34, 234, 247, 197, 251, 6, 224, 64, 70, 51, 153, 228, 243, 68, ++ 240, 123, 104, 1, 51, 123, 96, 1, 168, 51, 169, 227, 243, 255, 246, ++ 2, 70, 0, 40, 233, 209, 181, 248, 220, 48, 51, 177, 152, 248, 203, 48, ++ 27, 177, 48, 70, 41, 70, 255, 247, 211, 253, 52, 176, 189, 232, 240, ++ 129, 45, 233, 240, 65, 141, 106, 7, 70, 149, 248, 36, 0, 11, 70, 16, ++ 240, 2, 0, 148, 70, 3, 209, 42, 105, 18, 124, 0, 42, 46, 209, 215, 248, ++ 4, 69, 152, 105, 166, 105, 16, 244, 128, 96, 46, 68, 182, 248, 6, 128, ++ 6, 209, 34, 105, 144, 69, 3, 221, 97, 104, 98, 105, 145, 66, 29, 216, ++ 26, 70, 56, 70, 49, 70, 99, 70, 237, 247, 169, 250, 176, 177, 243, 136, ++ 200, 235, 3, 8, 184, 241, 1, 15, 2, 209, 99, 104, 1, 51, 99, 96, 181, ++ 248, 220, 48, 51, 177, 150, 248, 203, 48, 51, 185, 56, 70, 41, 70, 255, ++ 247, 150, 253, 1, 32, 189, 232, 240, 129, 1, 32, 189, 232, 240, 129, ++ 210, 248, 24, 192, 248, 181, 28, 240, 2, 15, 7, 70, 13, 70, 20, 70, ++ 208, 248, 4, 101, 5, 208, 209, 248, 52, 1, 68, 106, 128, 106, 160, 71, ++ 248, 189, 17, 70, 26, 70, 255, 247, 171, 255, 128, 185, 179, 104, 56, ++ 70, 1, 51, 179, 96, 179, 105, 41, 70, 235, 24, 211, 248, 216, 32, 1, ++ 50, 195, 248, 216, 32, 34, 70, 189, 232, 248, 64, 25, 240, 138, 156, ++ 248, 189, 45, 233, 248, 67, 12, 136, 12, 39, 1, 60, 7, 251, 4, 23, 129, ++ 70, 13, 70, 144, 70, 8, 55, 30, 224, 40, 70, 33, 70, 227, 243, 95, 247, ++ 131, 106, 2, 70, 152, 69, 2, 209, 131, 105, 155, 7, 7, 213, 40, 70, ++ 33, 70, 0, 46, 8, 191, 22, 70, 227, 243, 167, 247, 6, 224, 72, 70, 65, ++ 70, 35, 70, 255, 247, 180, 255, 0, 224, 0, 38, 59, 104, 179, 66, 226, ++ 209, 1, 60, 12, 63, 96, 28, 247, 209, 189, 232, 248, 131, 208, 248, ++ 4, 53, 112, 181, 158, 105, 5, 70, 12, 70, 3, 34, 142, 25, 15, 240, 74, ++ 219, 40, 70, 33, 70, 25, 240, 22, 223, 1, 35, 134, 248, 245, 48, 112, ++ 189, 195, 105, 48, 181, 179, 249, 30, 32, 179, 249, 28, 80, 133, 176, ++ 173, 24, 179, 249, 32, 32, 179, 249, 34, 48, 173, 24, 237, 24, 4, 70, ++ 90, 209, 144, 248, 116, 50, 41, 70, 35, 240, 8, 3, 128, 248, 116, 50, ++ 111, 240, 63, 2, 0, 105, 36, 240, 26, 222, 212, 248, 104, 50, 89, 89, ++ 193, 177, 209, 248, 204, 48, 91, 5, 20, 212, 209, 248, 244, 48, 91, ++ 142, 3, 244, 64, 67, 163, 245, 64, 64, 67, 66, 67, 235, 0, 3, 14, 51, ++ 1, 235, 131, 3, 91, 104, 43, 177, 147, 248, 231, 48, 19, 177, 32, 70, ++ 25, 240, 217, 218, 4, 53, 32, 45, 223, 209, 212, 248, 36, 1, 1, 169, ++ 0, 34, 73, 240, 218, 221, 23, 224, 149, 248, 231, 48, 163, 177, 43, ++ 125, 218, 7, 17, 212, 212, 248, 4, 53, 155, 105, 235, 24, 147, 248, ++ 245, 48, 27, 185, 32, 70, 41, 70, 255, 247, 154, 255, 149, 248, 232, ++ 32, 26, 185, 32, 70, 41, 70, 255, 247, 20, 254, 212, 248, 36, 1, 1, ++ 169, 28, 240, 100, 250, 5, 70, 0, 40, 223, 209, 212, 248, 164, 21, 33, ++ 177, 75, 137, 19, 177, 32, 70, 241, 247, 158, 255, 5, 176, 48, 189, ++ 115, 181, 10, 105, 4, 70, 147, 121, 13, 70, 19, 185, 19, 124, 0, 43, ++ 95, 209, 212, 248, 4, 53, 146, 249, 68, 16, 24, 104, 79, 244, 136, 118, ++ 6, 251, 1, 1, 209, 248, 4, 1, 1, 48, 193, 248, 4, 1, 216, 105, 1, 48, ++ 216, 97, 1, 32, 133, 248, 231, 0, 133, 248, 232, 0, 158, 105, 0, 32, ++ 174, 25, 165, 248, 228, 0, 134, 248, 202, 0, 209, 248, 4, 17, 1, 41, ++ 31, 209, 210, 248, 204, 48, 19, 244, 128, 99, 26, 209, 210, 248, 244, ++ 0, 64, 142, 0, 244, 64, 64, 160, 245, 64, 76, 220, 241, 0, 0, 64, 235, ++ 12, 0, 14, 48, 2, 235, 128, 2, 82, 104, 130, 248, 231, 16, 148, 248, ++ 117, 34, 50, 177, 132, 248, 117, 50, 32, 70, 64, 34, 0, 147, 10, 240, ++ 131, 218, 227, 105, 179, 249, 30, 32, 179, 249, 28, 16, 137, 24, 179, ++ 249, 32, 32, 137, 24, 179, 249, 34, 32, 139, 24, 0, 43, 9, 221, 148, ++ 248, 116, 50, 67, 240, 8, 3, 132, 248, 116, 50, 0, 35, 134, 248, 245, ++ 48, 6, 224, 32, 70, 41, 70, 2, 176, 189, 232, 112, 64, 255, 247, 24, ++ 191, 2, 176, 112, 189, 255, 247, 189, 190, 45, 233, 248, 67, 5, 70, ++ 137, 70, 22, 70, 79, 240, 0, 8, 213, 248, 104, 50, 83, 248, 8, 112, ++ 103, 177, 187, 121, 11, 177, 59, 121, 11, 185, 59, 124, 51, 185, 40, ++ 70, 57, 70, 74, 70, 28, 240, 7, 250, 4, 70, 40, 185, 8, 241, 4, 8, 184, ++ 241, 32, 15, 232, 209, 5, 224, 144, 248, 36, 48, 152, 7, 13, 212, 59, ++ 124, 91, 177, 149, 248, 116, 34, 40, 105, 2, 240, 8, 2, 0, 42, 20, 191, ++ 32, 34, 160, 34, 73, 70, 82, 178, 56, 224, 213, 248, 4, 53, 155, 105, ++ 227, 24, 182, 177, 147, 248, 244, 32, 22, 240, 2, 15, 20, 191, 66, 240, ++ 1, 2, 34, 240, 1, 2, 131, 248, 244, 32, 148, 248, 231, 48, 35, 185, ++ 40, 70, 33, 70, 255, 247, 75, 255, 22, 224, 1, 35, 132, 248, 232, 48, ++ 18, 224, 147, 248, 244, 48, 217, 7, 14, 212, 149, 248, 116, 50, 26, ++ 7, 2, 213, 132, 248, 232, 96, 7, 224, 148, 248, 231, 48, 35, 177, 40, ++ 70, 33, 70, 50, 70, 255, 247, 53, 253, 149, 248, 116, 50, 40, 105, 27, ++ 7, 88, 191, 102, 240, 127, 6, 4, 241, 20, 1, 50, 70, 36, 240, 240, 220, ++ 0, 32, 189, 232, 248, 131, 208, 248, 4, 53, 247, 181, 156, 105, 6, 70, ++ 12, 25, 212, 248, 212, 48, 13, 70, 23, 70, 0, 43, 84, 209, 148, 248, ++ 201, 48, 90, 7, 80, 212, 67, 240, 4, 3, 132, 248, 201, 48, 227, 136, ++ 19, 177, 255, 247, 138, 251, 216, 185, 2, 35, 0, 147, 48, 70, 0, 35, ++ 41, 105, 5, 241, 20, 2, 1, 147, 12, 240, 192, 223, 16, 185, 132, 248, ++ 200, 0, 8, 224, 131, 127, 35, 240, 48, 3, 67, 240, 32, 3, 131, 119, ++ 1, 35, 132, 248, 200, 48, 148, 248, 201, 48, 35, 240, 1, 3, 13, 224, ++ 148, 248, 200, 48, 107, 177, 43, 125, 216, 7, 10, 212, 148, 248, 201, ++ 48, 217, 7, 33, 213, 58, 5, 31, 212, 67, 240, 2, 3, 132, 248, 201, 48, ++ 26, 224, 48, 70, 41, 70, 255, 247, 71, 251, 0, 40, 10, 221, 149, 248, ++ 218, 0, 192, 67, 0, 240, 15, 0, 255, 247, 54, 251, 41, 70, 2, 70, 48, ++ 70, 3, 224, 48, 70, 41, 70, 79, 246, 255, 114, 0, 35, 3, 176, 189, 232, ++ 240, 64, 25, 240, 176, 154, 3, 176, 240, 189, 45, 233, 240, 79, 145, ++ 176, 1, 147, 178, 248, 2, 144, 178, 248, 32, 128, 142, 106, 79, 234, ++ 89, 25, 5, 70, 12, 70, 147, 70, 9, 240, 15, 9, 8, 244, 127, 72, 208, ++ 248, 4, 165, 22, 177, 150, 248, 231, 48, 43, 185, 40, 70, 6, 241, 20, ++ 1, 2, 34, 255, 247, 16, 255, 33, 70, 3, 170, 40, 70, 237, 247, 68, 252, ++ 213, 248, 4, 21, 10, 155, 143, 105, 26, 136, 247, 25, 151, 248, 202, ++ 16, 1, 187, 185, 241, 0, 15, 2, 209, 184, 241, 0, 15, 26, 208, 2, 240, ++ 12, 2, 4, 42, 22, 208, 189, 248, 18, 32, 2, 240, 16, 2, 146, 178, 18, ++ 177, 187, 248, 4, 32, 1, 224, 218, 138, 18, 9, 73, 234, 2, 18, 218, ++ 130, 9, 154, 19, 136, 162, 248, 78, 128, 35, 240, 16, 3, 27, 4, 27, ++ 12, 19, 128, 1, 155, 43, 185, 185, 241, 0, 15, 5, 209, 184, 241, 0, ++ 15, 2, 209, 1, 35, 135, 248, 202, 48, 34, 74, 22, 179, 150, 248, 231, ++ 48, 251, 177, 51, 125, 216, 7, 28, 212, 163, 105, 153, 7, 25, 212, 227, ++ 137, 3, 240, 7, 3, 210, 92, 13, 42, 1, 220, 1, 50, 0, 224, 15, 34, 40, ++ 70, 33, 70, 255, 247, 59, 253, 64, 187, 218, 248, 8, 48, 1, 32, 1, 51, ++ 202, 248, 8, 48, 215, 248, 216, 48, 1, 51, 199, 248, 216, 48, 29, 224, ++ 227, 127, 67, 240, 1, 3, 227, 119, 214, 248, 248, 48, 11, 185, 51, 105, ++ 219, 104, 217, 104, 227, 137, 4, 49, 3, 240, 7, 3, 211, 92, 13, 43, ++ 1, 220, 1, 51, 0, 224, 15, 35, 40, 70, 34, 70, 236, 247, 229, 255, 208, ++ 241, 1, 0, 56, 191, 0, 32, 0, 224, 0, 32, 17, 176, 189, 232, 240, 143, ++ 72, 194, 135, 0, 248, 181, 208, 248, 4, 53, 0, 36, 159, 105, 37, 70, ++ 207, 25, 1, 38, 166, 64, 240, 178, 255, 247, 122, 250, 1, 70, 56, 70, ++ 227, 243, 194, 244, 8, 177, 53, 67, 237, 178, 1, 52, 4, 44, 240, 209, ++ 40, 70, 248, 189, 3, 106, 211, 248, 16, 33, 154, 177, 209, 248, 252, ++ 48, 179, 249, 210, 0, 217, 106, 2, 235, 0, 18, 208, 137, 80, 177, 146, ++ 137, 66, 177, 74, 67, 130, 66, 40, 191, 2, 70, 88, 106, 218, 98, 65, ++ 26, 138, 24, 90, 98, 112, 71, 45, 233, 248, 67, 5, 70, 177, 248, 90, ++ 0, 12, 70, 145, 70, 232, 247, 230, 250, 0, 40, 108, 208, 153, 248, 131, ++ 96, 22, 240, 1, 6, 104, 208, 79, 240, 0, 8, 79, 70, 70, 70, 90, 224, ++ 151, 248, 139, 48, 180, 248, 90, 32, 1, 43, 2, 209, 81, 6, 76, 212, ++ 3, 224, 2, 43, 1, 209, 18, 6, 73, 212, 180, 248, 90, 32, 80, 4, 9, 213, ++ 3, 43, 2, 209, 18, 240, 64, 15, 3, 224, 4, 43, 2, 209, 18, 240, 128, ++ 15, 59, 209, 33, 104, 9, 104, 145, 248, 102, 17, 233, 177, 18, 240, ++ 160, 15, 26, 208, 8, 43, 14, 209, 213, 248, 80, 8, 33, 70, 26, 240, ++ 215, 254, 64, 177, 213, 248, 80, 8, 33, 70, 26, 240, 220, 254, 40, 179, ++ 35, 109, 153, 5, 34, 212, 151, 248, 139, 48, 2, 43, 5, 209, 213, 248, ++ 80, 8, 33, 70, 26, 240, 221, 254, 192, 185, 151, 248, 139, 48, 5, 43, ++ 7, 209, 180, 248, 90, 48, 19, 244, 130, 95, 12, 191, 0, 38, 1, 38, 13, ++ 224, 6, 43, 11, 209, 180, 248, 90, 48, 72, 242, 128, 6, 30, 64, 0, 54, ++ 24, 191, 1, 38, 2, 224, 30, 70, 0, 224, 1, 38, 8, 241, 1, 8, 1, 55, ++ 153, 248, 138, 48, 152, 69, 4, 218, 0, 46, 158, 208, 1, 38, 0, 224, ++ 6, 70, 48, 70, 189, 232, 248, 131, 45, 233, 247, 79, 76, 141, 156, 70, ++ 79, 246, 56, 115, 0, 44, 8, 191, 28, 70, 36, 178, 177, 248, 50, 144, ++ 111, 240, 199, 3, 4, 234, 228, 116, 156, 66, 184, 191, 28, 70, 9, 244, ++ 64, 73, 144, 248, 12, 49, 185, 245, 64, 79, 20, 191, 79, 240, 2, 9, ++ 79, 240, 1, 9, 75, 69, 5, 70, 14, 70, 208, 248, 8, 161, 164, 178, 14, ++ 209, 0, 42, 46, 208, 144, 248, 13, 49, 83, 177, 34, 178, 65, 50, 7, ++ 219, 91, 178, 228, 24, 36, 178, 4, 234, 228, 116, 164, 178, 0, 224, ++ 2, 179, 213, 248, 244, 48, 91, 142, 3, 244, 64, 67, 179, 245, 64, 79, ++ 20, 191, 2, 35, 1, 35, 75, 69, 20, 208, 213, 248, 252, 32, 146, 248, ++ 216, 48, 123, 177, 146, 249, 209, 16, 34, 178, 145, 66, 10, 220, 91, ++ 178, 228, 24, 36, 178, 4, 234, 228, 116, 111, 240, 199, 2, 148, 66, ++ 184, 191, 20, 70, 164, 178, 79, 240, 0, 8, 87, 70, 195, 70, 41, 224, ++ 59, 120, 2, 43, 14, 208, 3, 43, 15, 208, 1, 43, 22, 209, 99, 70, 40, ++ 70, 49, 70, 34, 178, 205, 248, 4, 192, 28, 240, 53, 216, 221, 248, 4, ++ 192, 12, 224, 150, 248, 186, 0, 9, 224, 154, 248, 224, 0, 48, 177, 192, ++ 235, 9, 3, 88, 66, 64, 235, 3, 0, 0, 224, 0, 32, 187, 120, 1, 34, 18, ++ 250, 3, 243, 1, 59, 24, 64, 123, 120, 147, 68, 152, 64, 4, 55, 128, ++ 68, 218, 248, 20, 48, 155, 69, 209, 219, 67, 185, 40, 70, 49, 70, 34, ++ 178, 99, 70, 3, 176, 189, 232, 240, 79, 28, 240, 12, 152, 64, 70, 3, ++ 176, 189, 232, 240, 143, 45, 233, 247, 79, 208, 248, 0, 160, 7, 70, ++ 1, 145, 208, 248, 252, 96, 21, 70, 218, 248, 204, 68, 79, 240, 0, 11, ++ 67, 224, 115, 107, 11, 43, 10, 209, 160, 104, 7, 241, 188, 1, 6, 34, ++ 224, 247, 118, 255, 24, 185, 40, 70, 29, 240, 201, 223, 6, 224, 56, ++ 70, 161, 104, 1, 34, 43, 29, 255, 247, 71, 255, 40, 96, 1, 155, 67, ++ 179, 150, 248, 61, 48, 43, 179, 243, 108, 27, 179, 177, 70, 79, 240, ++ 0, 8, 28, 224, 10, 33, 1, 251, 8, 97, 160, 104, 98, 49, 6, 34, 224, ++ 247, 87, 255, 120, 185, 162, 104, 185, 248, 96, 48, 80, 142, 0, 147, ++ 227, 243, 124, 245, 0, 155, 131, 66, 5, 209, 185, 248, 104, 48, 19, ++ 177, 40, 70, 29, 240, 157, 223, 8, 241, 1, 8, 9, 241, 10, 9, 243, 108, ++ 152, 69, 223, 219, 11, 241, 1, 11, 8, 53, 4, 52, 218, 248, 204, 52, ++ 27, 104, 155, 69, 182, 219, 189, 232, 254, 143, 45, 233, 248, 67, 4, ++ 70, 136, 70, 6, 104, 208, 248, 240, 112, 0, 37, 26, 224, 170, 28, 83, ++ 248, 34, 144, 184, 241, 0, 15, 11, 208, 153, 248, 8, 48, 58, 122, 154, ++ 66, 14, 209, 9, 241, 9, 0, 7, 241, 9, 1, 224, 247, 26, 255, 56, 185, ++ 74, 70, 214, 248, 200, 6, 33, 70, 146, 248, 131, 48, 66, 240, 172, 222, ++ 1, 53, 214, 248, 16, 51, 26, 104, 149, 66, 223, 211, 148, 248, 92, 48, ++ 27, 185, 180, 248, 90, 48, 154, 6, 6, 213, 214, 248, 200, 6, 33, 70, ++ 189, 232, 248, 67, 66, 240, 70, 158, 189, 232, 248, 131, 248, 181, 4, ++ 104, 7, 122, 1, 114, 35, 104, 5, 70, 147, 249, 82, 48, 14, 70, 51, 177, ++ 49, 185, 208, 248, 92, 3, 16, 48, 9, 240, 234, 216, 4, 224, 25, 177, ++ 32, 70, 0, 33, 5, 240, 15, 254, 35, 104, 147, 248, 60, 48, 187, 177, ++ 213, 248, 148, 51, 25, 7, 19, 212, 38, 185, 32, 70, 41, 70, 58, 240, ++ 27, 221, 13, 224, 213, 248, 40, 35, 213, 248, 244, 48, 32, 70, 41, 70, ++ 26, 185, 90, 142, 10, 240, 192, 251, 2, 224, 90, 142, 58, 240, 68, 223, ++ 47, 114, 40, 70, 22, 185, 11, 240, 135, 221, 3, 224, 148, 248, 38, 18, ++ 13, 240, 40, 219, 46, 114, 0, 33, 212, 248, 104, 34, 132, 248, 112, ++ 18, 132, 248, 115, 18, 83, 88, 123, 177, 152, 121, 104, 185, 24, 122, ++ 88, 177, 148, 248, 112, 2, 1, 48, 132, 248, 112, 2, 27, 124, 35, 185, ++ 148, 248, 115, 50, 1, 51, 132, 248, 115, 50, 4, 49, 32, 41, 234, 209, ++ 212, 248, 112, 34, 35, 104, 18, 240, 255, 31, 12, 191, 0, 34, 1, 34, ++ 131, 248, 63, 32, 34, 104, 35, 106, 146, 248, 63, 32, 24, 105, 210, ++ 241, 1, 2, 56, 191, 0, 34, 12, 240, 44, 252, 32, 70, 13, 240, 207, 223, ++ 132, 248, 113, 2, 40, 70, 24, 240, 202, 217, 40, 70, 240, 247, 74, 250, ++ 40, 70, 11, 240, 64, 216, 1, 70, 40, 70, 236, 247, 201, 251, 32, 70, ++ 41, 70, 50, 70, 5, 240, 43, 252, 35, 104, 147, 248, 173, 48, 83, 177, ++ 148, 248, 114, 50, 59, 177, 148, 248, 112, 50, 35, 185, 32, 70, 189, ++ 232, 248, 64, 29, 240, 64, 158, 248, 189, 16, 181, 208, 248, 252, 48, ++ 1, 104, 147, 248, 81, 32, 234, 185, 208, 248, 244, 0, 176, 249, 42, ++ 64, 88, 109, 36, 26, 147, 248, 92, 0, 0, 44, 184, 191, 100, 66, 132, ++ 66, 16, 219, 1, 32, 131, 248, 81, 0, 131, 248, 61, 32, 90, 98, 10, 106, ++ 210, 248, 240, 0, 10, 48, 194, 248, 240, 0, 210, 248, 244, 0, 5, 56, ++ 194, 248, 244, 0, 147, 248, 81, 32, 18, 179, 179, 248, 88, 32, 179, ++ 248, 90, 0, 1, 50, 146, 178, 144, 66, 163, 248, 88, 32, 24, 210, 0, ++ 34, 131, 248, 81, 32, 90, 101, 163, 248, 88, 32, 11, 106, 211, 248, ++ 240, 16, 211, 248, 252, 32, 145, 66, 11, 221, 211, 248, 244, 32, 211, ++ 248, 0, 1, 130, 66, 5, 210, 10, 57, 5, 50, 195, 248, 240, 16, 195, 248, ++ 244, 32, 16, 189, 45, 233, 240, 67, 135, 176, 14, 70, 7, 70, 21, 70, ++ 255, 247, 114, 253, 4, 70, 182, 248, 90, 0, 227, 243, 174, 246, 48, ++ 177, 149, 248, 111, 48, 219, 7, 2, 213, 5, 241, 111, 4, 41, 224, 182, ++ 248, 90, 0, 232, 247, 80, 248, 56, 177, 149, 248, 131, 48, 216, 7, 3, ++ 213, 20, 177, 5, 241, 131, 4, 28, 224, 182, 248, 90, 48, 179, 245, 128, ++ 111, 2, 208, 179, 245, 0, 111, 6, 209, 149, 248, 151, 48, 217, 7, 2, ++ 213, 5, 241, 151, 4, 13, 224, 0, 35, 8, 34, 0, 147, 1, 146, 2, 147, ++ 3, 147, 4, 147, 56, 70, 49, 70, 23, 34, 43, 70, 3, 240, 253, 218, 210, ++ 224, 51, 109, 90, 5, 4, 213, 149, 248, 131, 32, 16, 7, 64, 241, 203, ++ 128, 149, 248, 131, 32, 209, 6, 2, 213, 154, 5, 64, 241, 196, 128, 32, ++ 70, 31, 240, 176, 253, 51, 109, 0, 234, 3, 8, 214, 248, 140, 48, 83, ++ 177, 230, 243, 92, 243, 214, 248, 144, 16, 30, 240, 150, 222, 1, 40, ++ 2, 209, 0, 35, 198, 248, 140, 48, 24, 240, 4, 15, 29, 208, 163, 120, ++ 97, 120, 1, 43, 4, 209, 227, 120, 19, 185, 4, 41, 0, 240, 166, 128, ++ 4, 41, 5, 209, 32, 70, 84, 240, 210, 220, 0, 40, 64, 240, 162, 128, ++ 214, 248, 140, 144, 185, 241, 0, 15, 64, 240, 134, 128, 99, 120, 0, ++ 43, 0, 240, 130, 128, 32, 70, 4, 33, 92, 224, 24, 240, 2, 15, 21, 208, ++ 214, 248, 140, 48, 0, 43, 119, 209, 163, 120, 98, 120, 1, 43, 4, 209, ++ 227, 120, 19, 185, 2, 42, 0, 240, 129, 128, 0, 42, 108, 208, 32, 70, ++ 2, 33, 84, 240, 172, 220, 0, 40, 124, 209, 101, 224, 24, 240, 1, 9, ++ 69, 208, 214, 248, 140, 48, 0, 43, 94, 209, 182, 248, 90, 48, 8, 43, ++ 90, 209, 163, 120, 1, 43, 6, 209, 227, 120, 35, 185, 98, 120, 8, 58, ++ 210, 178, 2, 42, 98, 217, 99, 120, 155, 177, 32, 70, 9, 33, 84, 240, ++ 142, 220, 129, 70, 0, 40, 93, 209, 32, 70, 8, 33, 84, 240, 135, 220, ++ 128, 70, 0, 40, 88, 209, 32, 70, 10, 33, 84, 240, 128, 220, 0, 40, 78, ++ 209, 163, 120, 1, 43, 9, 209, 148, 248, 3, 144, 185, 241, 0, 15, 4, ++ 209, 99, 120, 1, 43, 71, 208, 5, 43, 69, 208, 99, 120, 0, 43, 42, 208, ++ 32, 70, 5, 33, 84, 240, 106, 220, 129, 70, 0, 40, 57, 209, 32, 70, 1, ++ 33, 84, 240, 99, 220, 0, 40, 53, 209, 28, 224, 24, 244, 128, 127, 9, ++ 208, 32, 70, 11, 33, 84, 240, 89, 220, 75, 70, 160, 177, 98, 120, 11, ++ 42, 17, 209, 39, 224, 214, 248, 140, 48, 99, 185, 163, 120, 1, 43, 9, ++ 209, 148, 248, 3, 144, 185, 241, 0, 15, 4, 209, 99, 120, 1, 43, 25, ++ 208, 5, 43, 23, 208, 0, 35, 149, 248, 50, 32, 0, 147, 1, 36, 2, 146, ++ 3, 147, 4, 147, 56, 70, 49, 70, 23, 34, 43, 70, 1, 148, 3, 240, 42, ++ 218, 8, 224, 1, 36, 6, 224, 28, 70, 4, 224, 68, 70, 2, 224, 0, 36, 0, ++ 224, 76, 70, 32, 70, 7, 176, 189, 232, 240, 131, 45, 233, 240, 79, 6, ++ 104, 4, 70, 214, 248, 204, 52, 208, 248, 252, 0, 135, 176, 3, 144, 24, ++ 104, 15, 70, 192, 0, 1, 146, 230, 243, 138, 246, 5, 70, 0, 40, 0, 240, ++ 232, 128, 32, 70, 57, 70, 42, 70, 214, 248, 204, 148, 255, 247, 83, ++ 253, 32, 70, 41, 70, 29, 240, 183, 219, 0, 47, 0, 240, 215, 128, 212, ++ 248, 244, 32, 32, 70, 2, 146, 3, 240, 12, 217, 40, 177, 32, 70, 2, 153, ++ 0, 34, 4, 171, 255, 247, 168, 252, 128, 70, 32, 70, 3, 240, 1, 217, ++ 56, 177, 3, 152, 67, 107, 1, 43, 3, 209, 51, 106, 211, 248, 244, 176, ++ 6, 224, 32, 70, 3, 240, 245, 216, 0, 35, 4, 147, 152, 70, 155, 70, 214, ++ 248, 204, 52, 27, 104, 3, 241, 1, 10, 9, 235, 138, 10, 95, 30, 35, 70, ++ 84, 70, 194, 70, 152, 70, 35, 224, 84, 248, 4, 9, 8, 241, 188, 1, 6, ++ 34, 224, 247, 164, 252, 208, 185, 99, 104, 88, 142, 227, 243, 172, 242, ++ 2, 154, 3, 70, 80, 142, 0, 147, 227, 243, 166, 242, 0, 155, 131, 66, ++ 13, 209, 5, 235, 199, 3, 91, 104, 68, 70, 85, 248, 55, 128, 2, 55, 4, ++ 147, 89, 248, 39, 48, 179, 249, 42, 48, 1, 147, 4, 224, 1, 63, 0, 47, ++ 217, 218, 68, 70, 208, 70, 3, 152, 67, 107, 154, 31, 1, 42, 1, 217, ++ 11, 43, 2, 209, 0, 35, 4, 147, 152, 70, 48, 70, 33, 70, 0, 34, 32, 240, ++ 33, 219, 120, 185, 51, 106, 1, 154, 211, 248, 240, 48, 154, 66, 9, 220, ++ 187, 241, 10, 15, 6, 217, 211, 26, 155, 68, 187, 241, 10, 15, 184, 191, ++ 79, 240, 10, 11, 214, 248, 204, 52, 0, 39, 27, 104, 17, 224, 85, 248, ++ 55, 16, 11, 235, 8, 2, 145, 66, 10, 217, 79, 240, 0, 8, 205, 248, 4, ++ 176, 194, 70, 179, 70, 38, 70, 76, 70, 169, 70, 61, 70, 65, 224, 1, ++ 55, 159, 66, 235, 219, 240, 231, 48, 70, 3, 240, 127, 216, 24, 179, ++ 4, 235, 133, 3, 67, 68, 153, 104, 2, 152, 74, 142, 67, 142, 2, 244, ++ 64, 66, 3, 244, 64, 67, 178, 245, 64, 79, 20, 191, 2, 34, 1, 34, 179, ++ 245, 64, 79, 20, 191, 2, 35, 1, 35, 154, 66, 12, 209, 0, 34, 6, 171, ++ 67, 248, 4, 45, 48, 70, 255, 247, 3, 252, 1, 154, 4, 155, 211, 24, 5, ++ 154, 154, 66, 18, 217, 9, 235, 197, 3, 83, 248, 24, 48, 10, 241, 2, ++ 2, 73, 248, 58, 48, 4, 235, 133, 3, 67, 68, 84, 248, 34, 16, 152, 104, ++ 10, 241, 1, 10, 68, 248, 34, 0, 153, 96, 1, 55, 8, 241, 4, 8, 219, 248, ++ 204, 52, 27, 104, 159, 66, 188, 219, 94, 70, 77, 70, 198, 248, 208, ++ 164, 40, 70, 233, 247, 175, 251, 7, 176, 189, 232, 240, 143, 240, 181, ++ 4, 106, 209, 248, 252, 48, 212, 248, 16, 81, 0, 45, 81, 208, 209, 248, ++ 0, 17, 179, 248, 210, 96, 209, 248, 16, 192, 194, 185, 144, 248, 8, ++ 118, 212, 248, 240, 16, 121, 24, 140, 69, 49, 178, 3, 219, 0, 41, 1, ++ 221, 113, 30, 13, 224, 5, 235, 1, 23, 151, 249, 2, 112, 23, 241, 128, ++ 15, 55, 208, 188, 69, 53, 218, 2, 41, 51, 220, 113, 28, 0, 224, 0, 33, ++ 163, 248, 210, 16, 9, 178, 14, 1, 169, 25, 173, 93, 94, 106, 21, 240, ++ 2, 15, 147, 248, 191, 80, 20, 191, 101, 240, 127, 5, 5, 240, 127, 5, ++ 131, 248, 191, 80, 145, 249, 1, 80, 196, 248, 240, 80, 145, 249, 3, ++ 80, 196, 248, 244, 80, 220, 106, 77, 137, 52, 27, 44, 25, 205, 136, ++ 131, 248, 140, 80, 13, 137, 73, 137, 29, 99, 217, 98, 36, 234, 228, ++ 113, 89, 98, 58, 177, 2, 104, 210, 105, 210, 248, 248, 32, 145, 66, ++ 44, 191, 89, 98, 90, 98, 240, 189, 112, 181, 146, 248, 131, 64, 157, ++ 248, 20, 80, 20, 240, 1, 0, 20, 208, 146, 248, 138, 0, 0, 33, 9, 224, ++ 86, 24, 150, 248, 139, 96, 158, 66, 3, 209, 61, 177, 20, 240, 8, 15, ++ 6, 209, 1, 49, 129, 66, 243, 219, 0, 32, 112, 189, 1, 32, 112, 189, ++ 1, 32, 112, 189, 45, 233, 240, 79, 203, 136, 141, 176, 155, 6, 5, 70, ++ 14, 70, 4, 104, 208, 248, 248, 112, 208, 248, 252, 176, 208, 248, 240, ++ 144, 68, 213, 3, 109, 154, 7, 18, 213, 91, 7, 11, 213, 1, 241, 111, ++ 0, 4, 33, 84, 240, 149, 218, 200, 185, 6, 241, 131, 0, 4, 33, 84, 240, ++ 143, 218, 152, 185, 148, 248, 49, 53, 19, 240, 2, 15, 13, 224, 216, ++ 7, 12, 213, 145, 248, 111, 48, 218, 7, 8, 212, 145, 248, 131, 48, 219, ++ 7, 4, 212, 148, 248, 49, 53, 19, 240, 1, 15, 2, 209, 149, 248, 37, 51, ++ 227, 177, 243, 136, 112, 142, 35, 244, 102, 99, 243, 128, 227, 243, ++ 82, 241, 64, 244, 128, 80, 31, 250, 128, 248, 112, 142, 227, 243, 75, ++ 241, 182, 248, 190, 48, 14, 40, 140, 191, 79, 244, 64, 64, 0, 32, 72, ++ 234, 0, 8, 35, 240, 10, 3, 166, 248, 50, 128, 166, 248, 190, 48, 32, ++ 70, 41, 70, 114, 142, 22, 35, 28, 240, 10, 219, 0, 40, 64, 240, 27, ++ 131, 115, 142, 32, 70, 19, 244, 64, 79, 12, 191, 0, 34, 1, 34, 10, 50, ++ 84, 248, 34, 32, 9, 146, 17, 70, 42, 70, 9, 240, 210, 218, 255, 40, ++ 128, 70, 0, 240, 8, 131, 148, 248, 116, 50, 67, 240, 4, 3, 132, 248, ++ 116, 50, 35, 104, 147, 248, 60, 48, 59, 177, 32, 70, 41, 70, 66, 70, ++ 9, 240, 247, 255, 0, 40, 64, 240, 246, 130, 35, 106, 24, 105, 12, 240, ++ 30, 249, 64, 69, 77, 208, 35, 106, 24, 105, 12, 240, 24, 249, 227, 243, ++ 2, 241, 130, 70, 64, 70, 227, 243, 254, 240, 130, 69, 9, 209, 35, 106, ++ 24, 105, 12, 240, 12, 249, 8, 244, 96, 83, 0, 244, 96, 80, 152, 66, ++ 55, 220, 123, 104, 2, 43, 10, 209, 185, 248, 190, 48, 216, 7, 6, 213, ++ 187, 104, 24, 43, 3, 208, 219, 248, 52, 48, 4, 43, 41, 209, 212, 248, ++ 92, 1, 65, 70, 45, 240, 203, 217, 32, 70, 13, 240, 156, 223, 123, 104, ++ 2, 43, 8, 209, 181, 249, 84, 48, 43, 185, 212, 248, 192, 6, 41, 70, ++ 50, 70, 48, 240, 142, 222, 32, 70, 65, 70, 12, 240, 94, 220, 35, 104, ++ 147, 248, 60, 48, 75, 177, 213, 248, 40, 51, 89, 104, 212, 248, 168, ++ 53, 153, 66, 2, 208, 32, 70, 10, 240, 144, 219, 32, 70, 7, 240, 49, ++ 223, 15, 224, 212, 248, 92, 1, 65, 70, 45, 240, 177, 222, 72, 177, 212, ++ 248, 92, 1, 65, 70, 45, 240, 155, 217, 0, 33, 32, 70, 10, 70, 9, 240, ++ 96, 219, 35, 104, 147, 248, 60, 48, 147, 177, 213, 248, 40, 51, 90, ++ 104, 212, 248, 168, 53, 154, 66, 11, 208, 32, 70, 13, 240, 92, 223, ++ 213, 248, 40, 51, 32, 70, 89, 104, 10, 240, 104, 219, 32, 70, 7, 240, ++ 9, 223, 9, 153, 79, 244, 146, 114, 80, 49, 11, 145, 72, 70, 49, 70, ++ 224, 247, 144, 250, 9, 154, 169, 248, 50, 128, 19, 104, 2, 43, 7, 209, ++ 146, 248, 21, 128, 216, 241, 1, 8, 56, 191, 79, 240, 0, 8, 1, 224, 79, ++ 240, 0, 8, 243, 136, 19, 240, 32, 3, 13, 208, 35, 104, 147, 248, 79, ++ 48, 19, 240, 3, 3, 7, 208, 213, 248, 204, 48, 3, 244, 128, 83, 211, ++ 241, 1, 3, 56, 191, 0, 35, 219, 178, 9, 241, 56, 10, 10, 147, 255, 34, ++ 184, 241, 0, 15, 24, 191, 0, 35, 141, 232, 12, 0, 80, 70, 81, 70, 0, ++ 34, 67, 70, 22, 240, 25, 255, 212, 248, 116, 52, 80, 70, 11, 153, 1, ++ 34, 155, 120, 22, 240, 185, 253, 0, 40, 48, 209, 9, 155, 26, 137, 27, ++ 104, 184, 241, 0, 15, 7, 209, 32, 70, 65, 70, 8, 146, 7, 147, 8, 240, ++ 69, 217, 8, 154, 7, 155, 185, 248, 50, 16, 1, 244, 96, 81, 177, 245, ++ 32, 95, 8, 208, 177, 245, 192, 95, 7, 208, 177, 245, 128, 95, 20, 191, ++ 10, 33, 20, 33, 2, 224, 160, 33, 0, 224, 40, 33, 79, 240, 255, 14, 2, ++ 144, 205, 248, 0, 128, 205, 248, 4, 224, 3, 145, 212, 248, 116, 20, ++ 80, 70, 9, 121, 4, 145, 11, 153, 22, 240, 92, 255, 213, 248, 204, 48, ++ 153, 4, 12, 213, 41, 70, 32, 70, 8, 240, 24, 217, 255, 35, 0, 147, 1, ++ 144, 81, 70, 80, 70, 0, 34, 2, 35, 22, 240, 205, 254, 32, 70, 81, 70, ++ 10, 240, 147, 221, 150, 249, 52, 32, 32, 70, 0, 50, 41, 70, 24, 191, ++ 1, 34, 4, 240, 60, 251, 150, 249, 52, 48, 227, 185, 213, 248, 244, 48, ++ 1, 34, 131, 248, 96, 32, 212, 248, 72, 1, 41, 70, 10, 240, 112, 253, ++ 40, 70, 49, 70, 27, 240, 113, 220, 40, 70, 14, 33, 0, 240, 53, 255, ++ 41, 70, 32, 70, 38, 240, 139, 216, 32, 70, 41, 70, 122, 104, 187, 104, ++ 36, 240, 109, 221, 194, 225, 213, 248, 204, 48, 154, 4, 5, 213, 212, ++ 248, 80, 1, 41, 70, 74, 70, 64, 240, 132, 216, 32, 70, 41, 70, 50, 70, ++ 27, 240, 86, 250, 128, 70, 56, 185, 32, 70, 41, 70, 58, 70, 13, 176, ++ 189, 232, 240, 79, 28, 240, 205, 153, 10, 153, 65, 179, 217, 248, 104, ++ 48, 185, 248, 108, 144, 12, 51, 169, 241, 12, 9, 25, 70, 74, 70, 32, ++ 70, 7, 147, 51, 240, 96, 223, 7, 155, 9, 144, 25, 70, 74, 70, 32, 70, ++ 51, 240, 47, 223, 34, 104, 132, 70, 146, 249, 82, 0, 7, 155, 64, 177, ++ 32, 70, 25, 70, 74, 70, 205, 248, 32, 192, 50, 240, 128, 223, 221, 248, ++ 32, 192, 0, 144, 65, 70, 32, 70, 9, 154, 99, 70, 10, 224, 67, 104, 219, ++ 3, 9, 213, 243, 136, 152, 6, 6, 212, 10, 154, 32, 70, 0, 146, 65, 70, ++ 19, 70, 238, 247, 245, 252, 216, 248, 4, 48, 213, 248, 204, 32, 67, ++ 244, 128, 83, 200, 248, 4, 48, 79, 240, 127, 3, 0, 147, 10, 155, 18, ++ 244, 0, 82, 8, 241, 76, 1, 1, 147, 80, 70, 2, 208, 0, 34, 2, 35, 0, ++ 224, 19, 70, 22, 240, 54, 254, 32, 70, 65, 70, 27, 240, 24, 251, 32, ++ 70, 41, 70, 26, 240, 184, 223, 152, 248, 36, 48, 19, 240, 12, 15, 64, ++ 240, 69, 129, 181, 249, 84, 160, 35, 104, 197, 248, 236, 160, 147, 248, ++ 102, 49, 0, 43, 91, 208, 181, 248, 90, 48, 25, 6, 5, 213, 212, 248, ++ 80, 8, 41, 70, 25, 240, 214, 255, 24, 185, 181, 248, 90, 48, 154, 6, ++ 60, 213, 0, 35, 41, 70, 197, 248, 236, 48, 212, 248, 80, 8, 25, 240, ++ 187, 255, 41, 70, 130, 70, 212, 248, 80, 8, 25, 240, 170, 255, 136, ++ 177, 79, 240, 32, 9, 32, 70, 41, 70, 50, 70, 8, 35, 141, 232, 0, 6, ++ 255, 247, 136, 253, 48, 177, 3, 35, 197, 248, 236, 48, 165, 248, 90, ++ 144, 154, 70, 27, 224, 212, 248, 80, 8, 41, 70, 25, 240, 171, 255, 160, ++ 177, 79, 240, 128, 10, 79, 240, 0, 9, 32, 70, 41, 70, 50, 70, 2, 35, ++ 205, 248, 0, 160, 205, 248, 4, 144, 255, 247, 108, 253, 40, 177, 165, ++ 248, 90, 160, 197, 248, 236, 144, 202, 70, 0, 224, 130, 70, 213, 248, ++ 236, 48, 3, 43, 12, 209, 212, 248, 200, 6, 41, 70, 50, 70, 181, 248, ++ 90, 48, 21, 240, 99, 252, 24, 177, 0, 35, 197, 248, 236, 48, 154, 70, ++ 215, 248, 4, 144, 185, 241, 2, 15, 29, 209, 186, 241, 0, 15, 26, 209, ++ 212, 248, 192, 6, 41, 70, 50, 70, 48, 240, 201, 220, 152, 177, 213, ++ 248, 244, 0, 231, 247, 48, 249, 112, 185, 212, 248, 188, 6, 41, 70, ++ 50, 70, 197, 248, 236, 144, 75, 240, 161, 222, 212, 248, 192, 6, 41, ++ 70, 50, 70, 48, 240, 247, 222, 202, 70, 12, 33, 64, 70, 72, 240, 238, ++ 221, 123, 104, 2, 43, 45, 209, 219, 248, 52, 48, 9, 59, 1, 43, 40, 216, ++ 91, 70, 212, 70, 163, 70, 186, 70, 79, 240, 0, 9, 31, 70, 28, 70, 23, ++ 224, 10, 32, 0, 251, 9, 64, 213, 248, 244, 16, 98, 48, 6, 34, 205, 248, ++ 32, 192, 224, 247, 177, 248, 221, 248, 32, 192, 48, 185, 79, 244, 150, ++ 113, 1, 34, 167, 248, 104, 16, 132, 248, 80, 32, 9, 241, 1, 9, 10, 55, ++ 226, 108, 145, 69, 228, 211, 35, 70, 87, 70, 92, 70, 226, 70, 155, 70, ++ 35, 104, 147, 248, 102, 49, 147, 177, 213, 248, 236, 48, 3, 43, 14, ++ 209, 212, 248, 80, 8, 41, 70, 66, 70, 51, 70, 26, 240, 189, 251, 48, ++ 177, 40, 70, 8, 33, 13, 176, 189, 232, 240, 79, 0, 240, 222, 189, 123, ++ 104, 2, 43, 51, 209, 43, 122, 0, 43, 48, 208, 186, 241, 2, 15, 45, 209, ++ 182, 248, 190, 48, 219, 7, 41, 213, 219, 248, 52, 48, 4, 43, 37, 208, ++ 187, 104, 24, 43, 34, 208, 40, 70, 10, 240, 47, 218, 24, 177, 40, 70, ++ 0, 33, 242, 247, 77, 249, 40, 70, 24, 33, 0, 240, 190, 253, 216, 248, ++ 12, 48, 212, 248, 192, 6, 213, 248, 244, 32, 27, 177, 25, 105, 0, 41, ++ 8, 191, 0, 35, 0, 147, 182, 248, 98, 48, 41, 70, 195, 243, 64, 19, 1, ++ 147, 67, 70, 48, 240, 211, 221, 6, 70, 41, 224, 40, 70, 8, 33, 0, 240, ++ 163, 253, 79, 240, 0, 9, 205, 248, 0, 160, 79, 240, 1, 10, 205, 248, ++ 4, 160, 205, 248, 8, 144, 205, 248, 12, 144, 205, 248, 16, 144, 182, ++ 248, 98, 48, 50, 70, 195, 243, 64, 19, 5, 147, 8, 241, 20, 1, 67, 70, ++ 40, 70, 243, 247, 167, 250, 81, 70, 6, 70, 32, 70, 4, 240, 85, 255, ++ 160, 104, 57, 104, 79, 244, 150, 114, 75, 70, 246, 243, 245, 247, 70, ++ 177, 212, 248, 120, 4, 12, 73, 181, 248, 26, 33, 51, 70, 64, 240, 98, ++ 223, 11, 224, 160, 104, 57, 104, 79, 244, 155, 114, 51, 70, 3, 224, ++ 0, 34, 160, 104, 57, 104, 19, 70, 246, 243, 223, 247, 187, 127, 1, 51, ++ 187, 119, 13, 176, 189, 232, 240, 143, 0, 191, 201, 66, 2, 0, 45, 233, ++ 240, 79, 137, 176, 154, 70, 18, 155, 6, 41, 4, 70, 136, 70, 6, 146, ++ 7, 147, 5, 104, 208, 248, 248, 112, 208, 248, 240, 144, 0, 240, 11, ++ 129, 187, 104, 24, 43, 0, 242, 7, 129, 132, 73, 153, 64, 64, 241, 3, ++ 129, 74, 177, 40, 70, 33, 70, 26, 240, 194, 255, 6, 70, 32, 177, 12, ++ 33, 72, 240, 167, 218, 0, 224, 6, 158, 184, 241, 2, 15, 0, 240, 46, ++ 129, 40, 70, 33, 70, 26, 240, 49, 222, 184, 241, 0, 15, 55, 209, 48, ++ 70, 9, 33, 135, 248, 73, 128, 72, 240, 240, 220, 115, 104, 185, 248, ++ 98, 32, 35, 240, 4, 3, 146, 6, 115, 96, 68, 191, 67, 240, 4, 3, 115, ++ 96, 115, 104, 32, 70, 67, 244, 128, 83, 115, 96, 11, 33, 0, 240, 21, ++ 253, 35, 122, 33, 70, 0, 147, 50, 70, 40, 70, 75, 70, 27, 240, 91, 219, ++ 33, 70, 6, 70, 40, 70, 26, 240, 8, 222, 70, 177, 213, 248, 120, 4, 99, ++ 73, 180, 248, 26, 33, 51, 70, 64, 240, 237, 222, 187, 224, 168, 104, ++ 57, 104, 79, 244, 155, 114, 51, 70, 246, 243, 111, 247, 188, 224, 184, ++ 241, 5, 15, 53, 209, 185, 248, 190, 48, 216, 7, 15, 213, 187, 104, 24, ++ 43, 12, 209, 213, 248, 208, 36, 213, 248, 204, 52, 2, 50, 83, 248, 34, ++ 16, 32, 70, 9, 176, 189, 232, 240, 79, 255, 247, 3, 188, 212, 248, 204, ++ 48, 153, 4, 64, 241, 211, 128, 151, 248, 73, 48, 90, 28, 3, 43, 135, ++ 248, 73, 32, 0, 242, 203, 128, 213, 248, 208, 36, 213, 248, 204, 52, ++ 2, 50, 65, 246, 88, 48, 83, 248, 34, 128, 229, 243, 111, 246, 32, 70, ++ 8, 33, 0, 240, 195, 252, 180, 249, 84, 48, 0, 147, 1, 35, 1, 147, 85, ++ 224, 184, 241, 1, 15, 119, 209, 163, 110, 48, 70, 90, 28, 26, 191, 4, ++ 235, 131, 3, 211, 248, 108, 176, 79, 240, 0, 11, 1, 33, 72, 240, 25, ++ 218, 0, 35, 135, 248, 73, 48, 180, 248, 90, 48, 88, 4, 16, 213, 186, ++ 241, 28, 15, 2, 208, 186, 241, 53, 15, 10, 209, 213, 248, 192, 6, 33, ++ 70, 7, 240, 144, 252, 186, 241, 28, 15, 2, 209, 32, 70, 28, 240, 151, ++ 223, 180, 249, 86, 48, 0, 43, 86, 208, 212, 248, 236, 48, 0, 43, 82, ++ 209, 186, 241, 13, 15, 79, 209, 185, 248, 98, 48, 217, 6, 75, 213, 35, ++ 109, 218, 7, 72, 213, 187, 241, 0, 15, 69, 208, 155, 248, 8, 48, 1, ++ 43, 1, 208, 3, 43, 63, 209, 213, 248, 208, 36, 213, 248, 204, 52, 2, ++ 50, 79, 240, 1, 9, 83, 248, 34, 128, 32, 70, 196, 248, 236, 144, 8, ++ 33, 0, 240, 107, 252, 212, 248, 236, 48, 141, 232, 8, 2, 0, 35, 2, 147, ++ 3, 147, 4, 147, 184, 248, 98, 48, 32, 70, 195, 243, 64, 19, 5, 147, ++ 6, 241, 20, 1, 51, 70, 66, 70, 243, 247, 117, 249, 3, 70, 72, 177, 213, ++ 248, 120, 4, 11, 73, 180, 248, 26, 33, 9, 176, 189, 232, 240, 79, 64, ++ 240, 57, 158, 168, 104, 57, 104, 79, 244, 155, 114, 9, 176, 189, 232, ++ 240, 79, 246, 243, 186, 182, 0, 38, 6, 224, 128, 0, 160, 0, 41, 250, ++ 131, 0, 201, 66, 2, 0, 1, 38, 212, 248, 252, 48, 147, 248, 60, 48, 59, ++ 177, 184, 241, 0, 15, 4, 209, 32, 70, 6, 153, 4, 240, 240, 250, 96, ++ 185, 7, 155, 40, 70, 2, 147, 0, 35, 3, 147, 4, 147, 33, 70, 3, 34, 6, ++ 155, 141, 232, 0, 5, 2, 240, 231, 219, 0, 46, 25, 208, 184, 241, 5, ++ 15, 2, 208, 184, 241, 2, 15, 9, 209, 186, 127, 59, 127, 154, 66, 5, ++ 210, 32, 70, 9, 176, 189, 232, 240, 79, 27, 240, 51, 158, 32, 70, 9, ++ 176, 189, 232, 240, 79, 0, 240, 165, 191, 0, 35, 135, 248, 73, 48, 200, ++ 231, 9, 176, 189, 232, 240, 143, 45, 233, 240, 79, 155, 70, 5, 104, ++ 208, 248, 240, 48, 137, 176, 4, 147, 43, 104, 4, 70, 147, 248, 63, 48, ++ 5, 145, 145, 70, 208, 248, 248, 96, 208, 248, 244, 112, 0, 43, 0, 240, ++ 89, 129, 3, 122, 0, 43, 0, 240, 85, 129, 3, 124, 6, 168, 19, 177, 4, ++ 241, 216, 1, 0, 224, 57, 70, 6, 34, 223, 247, 151, 254, 43, 104, 147, ++ 248, 69, 48, 27, 177, 213, 248, 100, 1, 41, 240, 253, 217, 34, 124, ++ 213, 248, 72, 1, 33, 70, 26, 177, 0, 34, 58, 240, 131, 221, 1, 224, ++ 10, 240, 253, 249, 40, 105, 49, 240, 171, 220, 160, 177, 32, 70, 0, ++ 33, 254, 247, 110, 255, 32, 70, 1, 33, 29, 240, 214, 222, 35, 124, 32, ++ 70, 211, 241, 1, 3, 56, 191, 0, 35, 0, 147, 0, 33, 6, 170, 8, 35, 30, ++ 240, 10, 216, 28, 225, 35, 124, 0, 43, 0, 240, 158, 128, 179, 104, 35, ++ 177, 16, 43, 2, 208, 32, 70, 28, 240, 168, 222, 6, 174, 50, 70, 33, ++ 70, 40, 70, 26, 240, 34, 254, 79, 240, 0, 10, 81, 70, 128, 70, 132, ++ 248, 148, 160, 32, 70, 13, 240, 133, 223, 81, 70, 32, 70, 10, 240, 77, ++ 216, 32, 70, 81, 70, 1, 240, 195, 221, 5, 155, 0, 43, 100, 208, 4, 241, ++ 188, 0, 230, 247, 126, 254, 0, 40, 94, 209, 213, 248, 92, 1, 121, 142, ++ 45, 240, 95, 218, 48, 185, 213, 248, 92, 1, 121, 142, 45, 240, 197, ++ 218, 0, 40, 41, 208, 185, 241, 0, 15, 78, 209, 213, 248, 92, 1, 121, ++ 142, 45, 240, 33, 218, 0, 40, 71, 209, 43, 106, 126, 142, 24, 105, 11, ++ 240, 50, 252, 134, 66, 64, 209, 4, 241, 194, 2, 1, 146, 8, 34, 6, 171, ++ 2, 146, 40, 70, 33, 70, 66, 70, 0, 147, 11, 240, 172, 219, 3, 70, 0, ++ 40, 49, 208, 213, 248, 120, 4, 101, 73, 74, 70, 64, 240, 65, 221, 6, ++ 28, 24, 191, 1, 38, 40, 224, 43, 106, 183, 248, 50, 160, 24, 105, 11, ++ 240, 17, 252, 130, 69, 31, 209, 4, 241, 194, 3, 1, 147, 8, 35, 2, 147, ++ 40, 70, 51, 70, 33, 70, 66, 70, 0, 150, 11, 240, 139, 219, 6, 70, 136, ++ 177, 185, 241, 0, 15, 14, 208, 213, 248, 120, 4, 73, 70, 90, 70, 51, ++ 70, 64, 240, 29, 221, 48, 185, 148, 248, 68, 48, 129, 70, 134, 248, ++ 33, 48, 1, 38, 0, 224, 1, 38, 184, 241, 0, 15, 24, 208, 64, 70, 14, ++ 33, 72, 240, 139, 216, 43, 104, 147, 248, 69, 48, 35, 177, 213, 248, ++ 100, 1, 65, 70, 41, 240, 76, 217, 65, 70, 40, 70, 10, 240, 186, 222, ++ 79, 240, 0, 8, 4, 224, 32, 70, 8, 240, 0, 216, 1, 38, 176, 70, 33, 70, ++ 1, 34, 40, 70, 3, 240, 247, 254, 32, 70, 0, 33, 254, 247, 173, 254, ++ 43, 104, 147, 248, 63, 48, 43, 185, 149, 249, 99, 36, 1, 50, 8, 191, ++ 133, 248, 98, 52, 213, 248, 108, 4, 33, 70, 66, 240, 132, 219, 43, 104, ++ 147, 248, 79, 48, 154, 7, 4, 208, 213, 248, 112, 4, 33, 70, 67, 240, ++ 162, 216, 4, 241, 188, 10, 80, 70, 230, 247, 217, 253, 1, 70, 48, 185, ++ 32, 70, 6, 170, 8, 35, 205, 248, 0, 128, 29, 240, 50, 223, 149, 248, ++ 114, 50, 32, 70, 59, 185, 213, 248, 108, 50, 156, 66, 3, 209, 49, 70, ++ 29, 240, 231, 221, 4, 224, 2, 240, 200, 221, 32, 70, 2, 240, 129, 217, ++ 184, 110, 40, 177, 232, 247, 28, 253, 0, 35, 187, 102, 167, 248, 108, ++ 48, 2, 35, 0, 38, 0, 147, 40, 70, 0, 33, 6, 170, 35, 70, 238, 247, 35, ++ 248, 33, 70, 50, 70, 51, 70, 40, 70, 0, 150, 54, 240, 151, 219, 32, ++ 70, 54, 240, 254, 218, 40, 70, 33, 70, 50, 70, 51, 70, 36, 240, 234, ++ 216, 40, 70, 10, 240, 105, 216, 185, 241, 0, 15, 3, 208, 40, 70, 49, ++ 70, 90, 70, 200, 71, 0, 33, 6, 34, 4, 152, 225, 243, 211, 240, 80, 70, ++ 0, 33, 6, 34, 225, 243, 206, 240, 0, 32, 1, 224, 79, 240, 255, 48, 9, ++ 176, 189, 232, 240, 143, 0, 191, 105, 216, 131, 0, 240, 181, 209, 176, ++ 12, 70, 79, 244, 146, 114, 209, 248, 240, 16, 5, 70, 7, 168, 223, 247, ++ 57, 253, 7, 168, 4, 241, 188, 1, 6, 34, 223, 247, 51, 253, 7, 168, 230, ++ 247, 108, 253, 96, 177, 40, 70, 7, 169, 6, 34, 7, 240, 84, 221, 157, ++ 248, 28, 48, 67, 240, 2, 3, 35, 240, 1, 3, 141, 248, 28, 48, 5, 245, ++ 82, 118, 48, 70, 230, 247, 89, 253, 32, 185, 7, 168, 49, 70, 6, 34, ++ 223, 247, 23, 253, 0, 33, 32, 34, 13, 241, 37, 0, 141, 248, 80, 16, ++ 225, 243, 143, 240, 34, 126, 13, 241, 37, 0, 141, 248, 36, 32, 4, 241, ++ 25, 1, 31, 42, 136, 191, 32, 34, 223, 247, 3, 253, 189, 248, 78, 48, ++ 19, 244, 64, 79, 12, 191, 0, 34, 1, 34, 3, 244, 96, 83, 10, 50, 179, ++ 245, 192, 95, 85, 248, 34, 96, 29, 209, 43, 104, 147, 248, 79, 48, 154, ++ 7, 10, 208, 213, 248, 92, 1, 113, 104, 44, 240, 10, 219, 3, 7, 3, 212, ++ 150, 248, 236, 48, 152, 7, 13, 212, 189, 248, 78, 0, 226, 243, 218, ++ 242, 64, 244, 128, 83, 14, 40, 140, 191, 79, 244, 64, 64, 0, 32, 24, ++ 67, 173, 248, 78, 0, 213, 248, 92, 1, 189, 248, 78, 16, 45, 240, 88, ++ 218, 48, 177, 213, 248, 92, 1, 189, 248, 78, 16, 45, 240, 191, 216, ++ 160, 177, 1, 34, 213, 248, 92, 1, 189, 248, 78, 16, 19, 70, 45, 240, ++ 70, 216, 255, 40, 8, 209, 32, 70, 3, 33, 7, 170, 1, 35, 28, 240, 118, ++ 218, 79, 240, 255, 48, 147, 224, 173, 248, 78, 0, 43, 106, 147, 248, ++ 236, 16, 17, 240, 2, 1, 18, 208, 189, 248, 78, 16, 1, 244, 96, 81, 177, ++ 245, 32, 95, 8, 208, 177, 245, 192, 95, 7, 208, 177, 245, 128, 95, 20, ++ 191, 10, 33, 20, 33, 2, 224, 160, 33, 0, 224, 40, 33, 21, 168, 22, 240, ++ 199, 249, 34, 109, 64, 242, 55, 19, 19, 64, 67, 177, 148, 248, 88, 48, ++ 43, 177, 189, 248, 126, 48, 67, 240, 16, 3, 173, 248, 126, 48, 189, ++ 248, 126, 48, 0, 34, 67, 240, 2, 3, 173, 248, 126, 48, 212, 248, 244, ++ 48, 173, 248, 76, 32, 26, 134, 212, 248, 240, 48, 40, 70, 26, 134, 13, ++ 240, 49, 217, 34, 70, 7, 169, 1, 35, 40, 70, 1, 240, 197, 216, 40, 70, ++ 7, 240, 222, 216, 212, 248, 252, 48, 1, 38, 158, 113, 212, 248, 252, ++ 48, 32, 70, 131, 248, 137, 96, 49, 70, 254, 247, 84, 253, 212, 248, ++ 244, 48, 33, 70, 131, 248, 96, 96, 213, 248, 72, 1, 50, 70, 9, 240, ++ 209, 255, 40, 70, 33, 70, 37, 240, 244, 218, 43, 104, 91, 107, 99, 177, ++ 212, 248, 204, 48, 153, 7, 8, 212, 67, 244, 128, 115, 196, 248, 204, ++ 48, 40, 70, 33, 70, 50, 70, 7, 240, 130, 216, 212, 248, 248, 48, 40, ++ 70, 90, 104, 33, 70, 155, 104, 35, 240, 196, 223, 0, 38, 1, 39, 40, ++ 70, 33, 70, 2, 34, 7, 171, 0, 150, 1, 150, 2, 151, 3, 150, 4, 150, 2, ++ 240, 61, 217, 40, 70, 57, 70, 7, 170, 35, 70, 0, 150, 237, 247, 217, ++ 254, 32, 70, 49, 70, 7, 170, 59, 70, 28, 240, 224, 217, 48, 70, 81, ++ 176, 240, 189, 0, 0, 45, 233, 247, 79, 137, 70, 208, 248, 104, 18, 5, ++ 70, 20, 70, 0, 35, 202, 88, 10, 177, 162, 66, 3, 208, 4, 51, 32, 43, ++ 248, 209, 80, 225, 212, 248, 248, 128, 212, 248, 252, 112, 216, 248, ++ 4, 96, 212, 248, 240, 48, 183, 248, 218, 32, 22, 241, 255, 54, 1, 147, ++ 24, 191, 1, 38, 50, 177, 138, 73, 40, 70, 8, 240, 60, 217, 0, 33, 167, ++ 248, 218, 16, 123, 106, 10, 43, 56, 191, 10, 35, 123, 98, 185, 241, ++ 0, 15, 7, 209, 215, 248, 204, 0, 208, 177, 232, 247, 135, 251, 199, ++ 248, 204, 144, 21, 224, 46, 177, 185, 241, 4, 15, 2, 209, 0, 35, 135, ++ 248, 189, 48, 1, 154, 146, 249, 52, 48, 1, 43, 2, 208, 185, 241, 12, ++ 15, 6, 208, 185, 241, 4, 15, 0, 240, 23, 129, 32, 70, 73, 70, 14, 225, ++ 180, 248, 90, 48, 154, 6, 3, 212, 88, 6, 5, 213, 89, 4, 3, 212, 32, ++ 70, 0, 33, 254, 247, 126, 252, 212, 248, 8, 49, 107, 177, 211, 248, ++ 220, 48, 83, 177, 32, 70, 213, 248, 16, 19, 213, 248, 204, 36, 26, 240, ++ 86, 218, 64, 177, 32, 70, 1, 33, 241, 224, 213, 248, 16, 3, 213, 248, ++ 204, 20, 2, 240, 164, 216, 213, 248, 204, 180, 219, 248, 0, 48, 197, ++ 248, 208, 52, 0, 43, 87, 208, 35, 122, 3, 177, 94, 185, 7, 241, 154, ++ 0, 0, 33, 28, 34, 224, 243, 29, 247, 0, 35, 135, 248, 182, 48, 135, ++ 248, 61, 48, 251, 100, 79, 240, 0, 9, 75, 70, 202, 70, 30, 224, 219, ++ 248, 8, 32, 80, 142, 0, 244, 64, 66, 178, 245, 64, 79, 2, 209, 1, 51, ++ 219, 178, 3, 224, 10, 241, 1, 10, 95, 250, 138, 250, 151, 248, 182, ++ 32, 66, 185, 0, 147, 226, 243, 119, 241, 1, 70, 7, 241, 154, 0, 226, ++ 243, 194, 240, 0, 155, 9, 241, 1, 9, 11, 241, 4, 11, 213, 248, 204, ++ 36, 18, 104, 145, 69, 219, 211, 186, 241, 1, 15, 1, 216, 1, 43, 1, 217, ++ 1, 35, 1, 224, 35, 122, 11, 185, 135, 248, 188, 48, 40, 70, 33, 70, ++ 31, 240, 113, 217, 78, 177, 216, 248, 12, 48, 26, 7, 5, 212, 212, 248, ++ 0, 49, 32, 70, 1, 33, 26, 105, 2, 224, 0, 33, 32, 70, 10, 70, 254, 247, ++ 65, 254, 10, 224, 78, 177, 151, 248, 61, 32, 50, 177, 250, 108, 34, ++ 177, 135, 248, 61, 48, 135, 248, 60, 48, 123, 98, 216, 248, 12, 48, ++ 213, 248, 208, 36, 35, 240, 8, 3, 200, 248, 12, 48, 210, 177, 40, 70, ++ 1, 33, 34, 70, 79, 240, 255, 51, 49, 240, 55, 217, 46, 177, 213, 248, ++ 204, 52, 32, 70, 25, 104, 28, 240, 156, 216, 32, 70, 0, 240, 13, 252, ++ 40, 70, 0, 33, 34, 70, 79, 240, 255, 51, 3, 176, 189, 232, 240, 79, ++ 49, 240, 35, 153, 1, 153, 145, 249, 52, 32, 1, 42, 27, 208, 149, 248, ++ 164, 148, 185, 241, 0, 15, 22, 209, 10, 122, 162, 177, 73, 70, 4, 241, ++ 188, 0, 6, 34, 224, 243, 141, 246, 40, 70, 33, 70, 255, 247, 197, 253, ++ 0, 40, 73, 208, 1, 33, 32, 70, 74, 70, 11, 70, 3, 176, 189, 232, 240, ++ 79, 28, 240, 188, 152, 70, 177, 151, 248, 60, 48, 155, 177, 251, 106, ++ 139, 177, 32, 70, 28, 240, 139, 216, 13, 224, 149, 248, 215, 33, 82, ++ 177, 155, 7, 8, 213, 32, 70, 3, 176, 189, 232, 240, 79, 25, 240, 181, ++ 152, 0, 191, 70, 108, 136, 0, 216, 248, 12, 48, 88, 7, 5, 213, 32, 70, ++ 3, 176, 189, 232, 240, 79, 28, 240, 208, 153, 212, 248, 204, 48, 153, ++ 4, 19, 213, 150, 177, 216, 248, 4, 48, 2, 43, 14, 209, 40, 70, 33, 70, ++ 241, 247, 245, 249, 32, 70, 3, 33, 25, 240, 231, 217, 40, 70, 33, 70, ++ 3, 176, 189, 232, 240, 79, 36, 240, 178, 156, 32, 70, 3, 33, 3, 176, ++ 189, 232, 240, 79, 25, 240, 217, 153, 3, 176, 189, 232, 240, 143, 45, ++ 233, 240, 71, 208, 248, 248, 96, 5, 70, 214, 248, 8, 128, 15, 70, 65, ++ 69, 4, 104, 82, 208, 3, 41, 10, 209, 212, 248, 28, 151, 229, 243, 49, ++ 240, 212, 248, 28, 55, 0, 34, 201, 248, 12, 0, 90, 96, 26, 114, 183, ++ 96, 184, 241, 0, 15, 4, 209, 40, 124, 57, 70, 25, 240, 126, 216, 40, ++ 185, 40, 124, 65, 70, 25, 240, 121, 216, 40, 177, 39, 185, 32, 70, 189, ++ 232, 240, 71, 12, 240, 240, 153, 184, 241, 0, 15, 4, 208, 40, 124, 65, ++ 70, 25, 240, 107, 216, 104, 177, 35, 106, 1, 33, 24, 105, 10, 70, 11, ++ 240, 12, 248, 114, 104, 32, 70, 41, 70, 1, 35, 189, 232, 240, 71, 25, ++ 240, 48, 154, 39, 177, 40, 124, 57, 70, 25, 240, 87, 216, 168, 177, ++ 41, 70, 32, 70, 25, 240, 146, 218, 5, 70, 120, 185, 32, 70, 212, 248, ++ 204, 20, 1, 240, 69, 223, 35, 106, 1, 33, 24, 105, 42, 70, 10, 240, ++ 237, 255, 32, 70, 189, 232, 240, 71, 25, 240, 110, 154, 189, 232, 240, ++ 135, 45, 233, 240, 79, 5, 70, 145, 176, 23, 70, 154, 70, 4, 104, 208, ++ 248, 248, 144, 208, 248, 252, 128, 14, 70, 97, 177, 1, 41, 10, 209, ++ 208, 248, 244, 48, 41, 70, 90, 142, 32, 70, 23, 35, 27, 240, 17, 218, ++ 0, 40, 64, 240, 210, 128, 32, 70, 212, 248, 204, 20, 1, 240, 25, 223, ++ 35, 104, 147, 248, 49, 48, 51, 177, 217, 248, 4, 48, 163, 241, 3, 2, ++ 83, 66, 67, 235, 2, 3, 0, 33, 201, 248, 4, 16, 40, 70, 6, 147, 255, ++ 247, 111, 255, 1, 46, 82, 209, 213, 248, 244, 48, 7, 147, 179, 248, ++ 50, 144, 35, 104, 147, 248, 60, 48, 51, 177, 32, 70, 41, 70, 74, 70, ++ 8, 240, 249, 254, 131, 70, 1, 224, 111, 240, 26, 11, 35, 106, 24, 105, ++ 11, 240, 31, 248, 72, 69, 26, 208, 32, 70, 12, 240, 198, 222, 32, 70, ++ 73, 70, 11, 240, 148, 219, 35, 104, 147, 248, 60, 48, 99, 177, 187, ++ 241, 0, 15, 9, 209, 213, 248, 40, 51, 89, 104, 212, 248, 168, 53, 153, ++ 66, 2, 208, 32, 70, 9, 240, 195, 218, 32, 70, 6, 240, 100, 222, 35, ++ 104, 147, 248, 60, 48, 171, 177, 187, 241, 0, 15, 18, 209, 213, 248, ++ 40, 51, 90, 104, 212, 248, 168, 53, 154, 66, 11, 208, 32, 70, 12, 240, ++ 157, 222, 213, 248, 40, 51, 32, 70, 89, 104, 9, 240, 169, 218, 32, 70, ++ 6, 240, 74, 222, 7, 155, 32, 70, 3, 241, 56, 1, 9, 240, 90, 221, 35, ++ 104, 147, 248, 47, 32, 50, 177, 147, 248, 48, 48, 27, 177, 212, 248, ++ 8, 5, 23, 240, 9, 216, 32, 70, 0, 33, 42, 70, 79, 240, 255, 51, 48, ++ 240, 198, 223, 94, 187, 40, 70, 57, 70, 3, 240, 198, 253, 48, 187, 181, ++ 248, 90, 48, 91, 4, 16, 213, 13, 241, 32, 9, 212, 248, 192, 6, 41, 70, ++ 74, 70, 47, 240, 60, 221, 32, 35, 0, 150, 1, 150, 205, 248, 8, 160, ++ 205, 248, 12, 144, 4, 147, 5, 224, 0, 150, 1, 150, 205, 248, 8, 160, ++ 3, 150, 4, 150, 32, 70, 41, 70, 125, 34, 59, 70, 1, 240, 169, 222, 5, ++ 245, 104, 112, 57, 70, 6, 34, 223, 247, 149, 249, 0, 150, 216, 248, ++ 52, 48, 79, 240, 0, 9, 1, 147, 32, 70, 59, 70, 41, 70, 19, 34, 205, ++ 248, 8, 160, 205, 248, 12, 144, 205, 248, 16, 144, 1, 240, 145, 222, ++ 35, 104, 147, 248, 49, 48, 131, 177, 6, 155, 115, 177, 110, 177, 3, ++ 35, 0, 147, 32, 70, 43, 70, 73, 70, 5, 241, 216, 2, 237, 247, 36, 252, ++ 1, 35, 136, 248, 137, 48, 136, 248, 6, 48, 17, 176, 189, 232, 240, 143, ++ 45, 233, 243, 65, 5, 104, 208, 248, 248, 48, 149, 248, 116, 34, 208, ++ 248, 252, 112, 34, 240, 4, 2, 208, 248, 240, 96, 133, 248, 116, 34, ++ 91, 104, 79, 240, 0, 8, 1, 43, 4, 70, 199, 248, 84, 128, 8, 209, 215, ++ 248, 204, 0, 199, 248, 52, 128, 24, 177, 232, 247, 234, 248, 199, 248, ++ 204, 128, 182, 249, 42, 48, 187, 100, 0, 35, 135, 248, 189, 48, 135, ++ 248, 182, 48, 35, 124, 67, 177, 3, 35, 0, 147, 40, 70, 1, 33, 34, 70, ++ 79, 240, 255, 51, 48, 240, 128, 223, 40, 70, 12, 240, 239, 221, 0, 35, ++ 49, 70, 34, 70, 40, 70, 0, 240, 131, 221, 40, 70, 6, 240, 156, 221, ++ 32, 70, 1, 33, 254, 247, 26, 250, 43, 104, 91, 107, 91, 177, 212, 248, ++ 204, 48, 3, 244, 129, 115, 179, 245, 128, 127, 4, 209, 40, 70, 33, 70, ++ 1, 34, 6, 240, 87, 221, 35, 124, 43, 177, 213, 248, 72, 1, 33, 70, 1, ++ 34, 58, 240, 13, 216, 43, 104, 147, 248, 79, 32, 145, 7, 5, 208, 147, ++ 249, 82, 48, 19, 177, 32, 70, 7, 240, 212, 218, 180, 248, 90, 0, 230, ++ 247, 62, 251, 40, 177, 212, 248, 236, 0, 2, 40, 12, 191, 11, 32, 0, ++ 32, 4, 241, 188, 2, 35, 70, 0, 144, 1, 33, 40, 70, 237, 247, 164, 251, ++ 32, 70, 13, 33, 255, 247, 53, 254, 212, 248, 248, 48, 40, 70, 90, 104, ++ 33, 70, 155, 104, 35, 240, 111, 220, 150, 249, 52, 48, 27, 177, 32, ++ 70, 14, 33, 255, 247, 38, 254, 32, 70, 27, 240, 69, 222, 50, 122, 32, ++ 70, 6, 241, 9, 1, 36, 240, 17, 218, 213, 248, 204, 52, 32, 70, 25, 104, ++ 27, 240, 65, 222, 40, 70, 33, 70, 1, 34, 2, 176, 189, 232, 240, 65, ++ 254, 247, 186, 188, 247, 181, 6, 104, 4, 70, 13, 70, 8, 70, 12, 33, ++ 71, 240, 115, 219, 48, 70, 33, 70, 25, 240, 3, 223, 35, 124, 107, 179, ++ 35, 122, 91, 179, 212, 248, 244, 48, 48, 70, 91, 142, 33, 70, 3, 244, ++ 64, 67, 163, 245, 64, 71, 123, 66, 67, 235, 7, 3, 4, 241, 216, 2, 26, ++ 240, 117, 248, 7, 70, 200, 177, 180, 248, 90, 48, 88, 4, 10, 213, 51, ++ 104, 147, 248, 69, 48, 51, 177, 214, 248, 100, 1, 24, 177, 57, 70, 42, ++ 70, 3, 240, 198, 255, 56, 70, 175, 66, 20, 191, 19, 33, 18, 33, 71, ++ 240, 67, 219, 48, 70, 57, 70, 10, 240, 123, 217, 171, 104, 34, 109, ++ 35, 244, 192, 99, 145, 5, 171, 96, 8, 213, 212, 248, 240, 32, 146, 248, ++ 131, 32, 18, 7, 68, 191, 67, 244, 0, 115, 171, 96, 35, 109, 155, 5, ++ 9, 213, 212, 248, 240, 48, 147, 248, 131, 48, 152, 6, 3, 213, 171, 104, ++ 67, 244, 128, 99, 171, 96, 180, 248, 90, 32, 73, 242, 32, 3, 19, 64, ++ 75, 177, 212, 248, 240, 48, 147, 248, 131, 48, 153, 6, 3, 213, 171, ++ 104, 67, 244, 128, 99, 171, 96, 0, 33, 32, 70, 11, 240, 224, 220, 0, ++ 33, 32, 70, 13, 240, 140, 217, 2, 33, 40, 70, 71, 240, 98, 221, 180, ++ 248, 90, 48, 32, 70, 165, 248, 68, 48, 255, 247, 226, 254, 107, 104, ++ 79, 240, 3, 1, 19, 244, 128, 63, 7, 209, 171, 108, 2, 43, 4, 209, 1, ++ 34, 0, 145, 48, 70, 19, 70, 4, 224, 0, 145, 48, 70, 3, 33, 1, 34, 0, ++ 35, 8, 240, 66, 216, 107, 104, 218, 3, 17, 212, 51, 104, 211, 248, 216, ++ 48, 155, 105, 155, 0, 3, 213, 214, 248, 180, 49, 152, 0, 7, 212, 2, ++ 33, 48, 70, 79, 244, 128, 114, 0, 35, 0, 145, 8, 240, 45, 216, 254, ++ 189, 139, 30, 1, 43, 45, 233, 240, 71, 7, 70, 137, 70, 5, 104, 208, ++ 248, 248, 128, 208, 248, 252, 64, 7, 216, 0, 33, 13, 240, 71, 217, 0, ++ 35, 99, 98, 56, 70, 1, 240, 12, 220, 227, 106, 0, 43, 0, 240, 197, 128, ++ 224, 108, 1, 40, 18, 217, 169, 241, 9, 3, 1, 43, 14, 216, 0, 34, 33, ++ 70, 19, 70, 177, 248, 104, 96, 6, 177, 1, 50, 1, 51, 10, 49, 131, 66, ++ 247, 209, 154, 66, 99, 209, 189, 232, 240, 135, 185, 241, 1, 15, 94, ++ 209, 215, 248, 0, 49, 30, 105, 43, 106, 211, 248, 16, 49, 35, 177, 40, ++ 70, 57, 70, 0, 34, 254, 247, 214, 251, 162, 108, 148, 248, 191, 48, ++ 145, 27, 153, 66, 8, 220, 148, 248, 61, 16, 0, 41, 0, 240, 177, 128, ++ 178, 26, 154, 66, 64, 243, 173, 128, 216, 248, 4, 48, 2, 43, 11, 209, ++ 213, 248, 104, 49, 27, 177, 155, 121, 0, 43, 64, 240, 172, 128, 216, ++ 248, 8, 48, 14, 43, 0, 240, 167, 128, 0, 35, 132, 248, 61, 48, 99, 98, ++ 166, 100, 150, 224, 148, 248, 60, 16, 0, 41, 0, 240, 156, 128, 97, 107, ++ 1, 41, 64, 240, 152, 128, 149, 248, 8, 22, 211, 26, 139, 66, 192, 242, ++ 146, 128, 216, 248, 4, 48, 2, 43, 11, 209, 213, 248, 104, 49, 67, 177, ++ 155, 121, 51, 177, 102, 106, 56, 70, 27, 240, 236, 223, 0, 35, 102, ++ 98, 99, 99, 0, 35, 132, 248, 60, 48, 43, 106, 211, 248, 16, 49, 0, 43, ++ 121, 208, 40, 70, 57, 70, 1, 34, 189, 232, 240, 71, 254, 247, 131, 187, ++ 99, 107, 9, 59, 1, 43, 25, 216, 98, 105, 163, 105, 154, 66, 21, 217, ++ 216, 248, 4, 48, 2, 43, 7, 209, 213, 248, 104, 49, 35, 177, 155, 121, ++ 19, 177, 56, 70, 27, 240, 198, 223, 0, 35, 132, 248, 61, 48, 132, 248, ++ 60, 48, 99, 98, 99, 97, 99, 99, 189, 232, 240, 135, 99, 106, 0, 43, ++ 81, 209, 33, 108, 34, 107, 148, 248, 61, 80, 145, 66, 166, 143, 4, 210, ++ 213, 241, 1, 5, 56, 191, 0, 37, 2, 224, 132, 248, 61, 48, 1, 37, 216, ++ 248, 4, 48, 2, 43, 3, 209, 216, 248, 8, 48, 14, 43, 58, 209, 0, 34, ++ 56, 70, 73, 70, 19, 70, 30, 240, 156, 221, 0, 40, 50, 209, 226, 106, ++ 1, 35, 132, 248, 60, 48, 98, 98, 13, 185, 0, 46, 42, 209, 99, 100, 0, ++ 35, 35, 100, 189, 232, 240, 135, 185, 241, 1, 15, 8, 191, 215, 248, ++ 0, 49, 42, 106, 8, 191, 27, 105, 210, 248, 240, 32, 24, 191, 111, 240, ++ 199, 3, 147, 66, 22, 218, 99, 106, 163, 185, 98, 121, 146, 185, 35, ++ 107, 56, 70, 99, 98, 1, 33, 19, 70, 189, 232, 240, 71, 30, 240, 113, ++ 157, 215, 248, 0, 49, 26, 105, 43, 106, 211, 248, 240, 48, 154, 66, ++ 191, 246, 96, 175, 140, 231, 189, 232, 240, 135, 0, 0, 45, 233, 240, ++ 79, 5, 104, 4, 70, 208, 248, 248, 160, 208, 248, 8, 129, 208, 248, 240, ++ 176, 149, 176, 40, 70, 11, 240, 112, 222, 40, 70, 33, 70, 25, 240, 80, ++ 221, 237, 225, 213, 248, 204, 36, 1, 51, 82, 248, 35, 96, 40, 70, 115, ++ 142, 3, 244, 64, 66, 162, 245, 64, 71, 122, 66, 66, 235, 7, 2, 10, 50, ++ 85, 248, 34, 112, 34, 70, 57, 70, 7, 240, 156, 222, 255, 40, 0, 240, ++ 209, 129, 112, 142, 225, 243, 232, 244, 64, 244, 128, 80, 31, 250, 128, ++ 249, 112, 142, 225, 243, 225, 244, 14, 40, 140, 191, 79, 244, 64, 65, ++ 0, 33, 73, 234, 1, 1, 32, 70, 26, 240, 141, 222, 0, 40, 0, 240, 186, ++ 129, 79, 240, 0, 9, 213, 248, 104, 50, 83, 248, 9, 16, 105, 177, 139, ++ 121, 91, 185, 11, 122, 75, 177, 161, 66, 7, 208, 48, 70, 188, 49, 6, ++ 34, 222, 247, 181, 254, 0, 40, 0, 240, 165, 129, 9, 241, 4, 9, 185, ++ 241, 32, 15, 231, 209, 59, 226, 211, 248, 220, 48, 0, 43, 127, 208, ++ 0, 35, 164, 248, 84, 48, 150, 248, 186, 0, 79, 240, 12, 9, 9, 251, 0, ++ 128, 242, 136, 28, 48, 2, 240, 128, 2, 210, 241, 1, 2, 56, 191, 0, 34, ++ 18, 169, 230, 247, 101, 248, 189, 248, 72, 48, 17, 169, 164, 248, 90, ++ 48, 150, 248, 186, 0, 9, 251, 0, 128, 32, 48, 225, 243, 205, 246, 17, ++ 155, 43, 187, 150, 248, 186, 48, 4, 34, 9, 251, 3, 137, 19, 168, 9, ++ 241, 36, 1, 222, 247, 143, 254, 19, 168, 150, 73, 4, 34, 222, 247, 119, ++ 254, 72, 185, 150, 248, 185, 48, 163, 241, 8, 2, 210, 178, 2, 42, 64, ++ 242, 97, 129, 141, 248, 79, 48, 19, 168, 17, 169, 225, 243, 173, 246, ++ 48, 185, 12, 35, 0, 144, 1, 147, 150, 248, 50, 48, 2, 147, 49, 225, ++ 213, 248, 188, 54, 27, 104, 227, 88, 171, 177, 27, 121, 155, 177, 17, ++ 155, 88, 7, 68, 191, 67, 240, 2, 3, 17, 147, 17, 155, 153, 7, 68, 191, ++ 67, 240, 1, 3, 17, 147, 35, 109, 17, 154, 35, 244, 130, 115, 35, 240, ++ 3, 3, 19, 67, 17, 147, 17, 171, 0, 147, 4, 35, 1, 147, 1, 35, 2, 147, ++ 227, 104, 0, 34, 3, 147, 120, 73, 19, 70, 40, 70, 234, 247, 20, 252, ++ 7, 35, 0, 147, 0, 35, 1, 147, 150, 248, 186, 32, 40, 70, 2, 146, 3, ++ 147, 4, 147, 33, 70, 24, 34, 51, 70, 1, 240, 73, 219, 182, 248, 98, ++ 48, 219, 6, 10, 213, 34, 109, 64, 242, 55, 19, 19, 64, 43, 185, 148, ++ 248, 124, 48, 19, 185, 0, 147, 1, 34, 73, 224, 48, 70, 229, 247, 89, ++ 254, 129, 70, 24, 177, 0, 35, 0, 147, 2, 34, 64, 224, 213, 248, 104, ++ 6, 33, 70, 50, 70, 53, 240, 199, 221, 1, 40, 3, 209, 205, 248, 0, 144, ++ 3, 35, 90, 224, 4, 40, 3, 209, 205, 248, 0, 144, 1, 144, 85, 224, 43, ++ 104, 147, 248, 173, 48, 195, 177, 213, 248, 116, 1, 13, 240, 9, 223, ++ 2, 40, 18, 209, 150, 249, 52, 48, 123, 177, 182, 248, 98, 144, 25, 244, ++ 128, 121, 10, 209, 213, 248, 92, 1, 121, 104, 43, 240, 26, 220, 128, ++ 7, 3, 213, 205, 248, 0, 144, 6, 35, 55, 224, 43, 104, 147, 248, 173, ++ 48, 147, 177, 150, 249, 52, 48, 123, 177, 213, 248, 124, 1, 177, 110, ++ 182, 248, 108, 32, 45, 240, 248, 220, 56, 177, 0, 35, 0, 147, 6, 34, ++ 1, 146, 150, 248, 50, 32, 2, 146, 180, 224, 43, 104, 147, 248, 173, ++ 48, 115, 177, 150, 249, 52, 144, 185, 241, 0, 15, 9, 209, 213, 248, ++ 92, 1, 113, 142, 44, 240, 243, 217, 24, 177, 205, 248, 0, 144, 7, 35, ++ 13, 224, 150, 249, 52, 144, 185, 241, 0, 15, 17, 209, 213, 248, 92, ++ 1, 113, 142, 44, 240, 80, 218, 88, 177, 205, 248, 0, 144, 5, 35, 1, ++ 147, 150, 248, 50, 48, 205, 248, 12, 144, 2, 147, 205, 248, 16, 144, ++ 140, 224, 180, 248, 90, 48, 99, 177, 34, 109, 64, 242, 55, 19, 19, 64, ++ 59, 177, 40, 70, 33, 70, 50, 70, 253, 247, 121, 255, 0, 40, 64, 240, ++ 131, 128, 59, 104, 2, 43, 9, 209, 122, 125, 58, 185, 255, 35, 0, 147, ++ 1, 146, 6, 241, 56, 0, 7, 169, 1, 35, 11, 224, 33, 70, 40, 70, 6, 240, ++ 144, 220, 255, 35, 0, 34, 0, 147, 1, 144, 7, 169, 6, 241, 56, 0, 19, ++ 70, 21, 240, 68, 250, 43, 106, 80, 55, 147, 248, 236, 16, 17, 240, 2, ++ 1, 17, 208, 113, 142, 1, 244, 96, 81, 177, 245, 32, 95, 8, 208, 177, ++ 245, 192, 95, 7, 208, 177, 245, 128, 95, 20, 191, 10, 33, 20, 33, 2, ++ 224, 160, 33, 0, 224, 40, 33, 56, 70, 21, 240, 156, 250, 213, 248, 116, ++ 52, 7, 168, 57, 70, 0, 34, 155, 120, 21, 240, 200, 248, 48, 185, 0, ++ 144, 9, 35, 28, 224, 59, 21, 4, 0, 32, 77, 136, 0, 157, 248, 48, 32, ++ 149, 248, 12, 53, 154, 66, 53, 209, 150, 249, 52, 48, 163, 185, 114, ++ 142, 40, 70, 2, 244, 64, 66, 6, 241, 56, 1, 178, 245, 64, 79, 20, 191, ++ 2, 34, 1, 34, 26, 240, 154, 220, 48, 185, 0, 144, 10, 35, 1, 147, 2, ++ 144, 3, 144, 4, 144, 23, 224, 43, 104, 147, 248, 48, 48, 27, 179, 40, ++ 70, 33, 70, 50, 70, 25, 240, 253, 252, 232, 177, 144, 248, 36, 48, 153, ++ 7, 25, 213, 67, 104, 19, 244, 128, 83, 21, 209, 13, 34, 0, 147, 1, 146, ++ 2, 147, 3, 147, 4, 147, 40, 70, 33, 70, 23, 34, 51, 70, 1, 240, 46, ++ 218, 213, 248, 208, 52, 1, 59, 197, 248, 208, 52, 213, 248, 208, 52, ++ 0, 43, 127, 244, 13, 174, 213, 248, 208, 52, 0, 43, 57, 208, 0, 35, ++ 138, 248, 30, 48, 213, 248, 208, 36, 213, 248, 204, 20, 80, 30, 1, 50, ++ 81, 248, 34, 96, 218, 248, 4, 32, 197, 248, 208, 4, 1, 42, 10, 208, ++ 0, 147, 1, 147, 2, 147, 3, 147, 4, 147, 40, 70, 33, 70, 32, 34, 51, ++ 70, 1, 240, 4, 218, 213, 248, 188, 6, 3, 104, 227, 88, 163, 177, 27, ++ 104, 2, 43, 17, 209, 33, 70, 6, 241, 9, 2, 51, 122, 74, 240, 128, 219, ++ 80, 177, 1, 40, 32, 70, 3, 209, 17, 33, 255, 247, 39, 250, 98, 224, ++ 1, 33, 24, 240, 249, 219, 94, 224, 32, 70, 29, 240, 189, 219, 90, 224, ++ 212, 248, 204, 48, 154, 4, 6, 213, 35, 122, 35, 185, 213, 248, 80, 1, ++ 33, 70, 63, 240, 147, 217, 43, 104, 147, 248, 60, 48, 67, 177, 212, ++ 248, 40, 51, 43, 177, 35, 122, 27, 185, 40, 70, 33, 70, 56, 240, 240, ++ 218, 35, 122, 147, 177, 148, 248, 118, 35, 34, 177, 32, 70, 1, 33, 24, ++ 240, 211, 219, 34, 224, 155, 249, 52, 48, 1, 33, 211, 241, 1, 3, 32, ++ 70, 56, 191, 0, 35, 255, 247, 82, 250, 23, 224, 149, 248, 215, 49, 59, ++ 177, 218, 248, 12, 48, 155, 7, 3, 208, 32, 70, 24, 240, 109, 218, 34, ++ 224, 155, 249, 52, 48, 0, 34, 194, 235, 3, 14, 1, 33, 222, 241, 0, 3, ++ 32, 70, 67, 235, 14, 3, 27, 240, 81, 218, 213, 248, 188, 6, 33, 70, ++ 0, 34, 74, 240, 95, 219, 149, 248, 116, 50, 32, 70, 35, 240, 4, 3, 133, ++ 248, 116, 50, 27, 240, 236, 217, 5, 224, 212, 248, 8, 49, 0, 43, 127, ++ 244, 191, 173, 65, 230, 21, 176, 189, 232, 240, 143, 45, 233, 240, 79, ++ 139, 176, 7, 147, 21, 155, 6, 41, 5, 70, 14, 70, 147, 70, 157, 248, ++ 80, 160, 9, 147, 4, 104, 208, 248, 248, 128, 0, 240, 169, 128, 0, 41, ++ 64, 240, 138, 128, 186, 241, 0, 15, 13, 209, 32, 70, 41, 70, 36, 240, ++ 255, 218, 187, 241, 0, 15, 9, 208, 5, 245, 104, 112, 89, 70, 6, 34, ++ 222, 247, 86, 252, 2, 224, 1, 35, 128, 248, 234, 51, 148, 248, 114, ++ 50, 0, 43, 98, 208, 35, 104, 147, 248, 60, 48, 59, 177, 212, 248, 84, ++ 1, 56, 240, 36, 220, 0, 48, 24, 191, 1, 32, 0, 224, 1, 32, 35, 104, ++ 192, 178, 147, 248, 60, 112, 8, 144, 31, 177, 79, 240, 0, 9, 47, 70, ++ 29, 224, 212, 248, 104, 50, 83, 248, 7, 144, 185, 241, 0, 15, 18, 208, ++ 153, 248, 6, 48, 123, 177, 153, 248, 4, 48, 99, 177, 35, 106, 24, 105, ++ 10, 240, 52, 250, 217, 248, 244, 48, 91, 142, 131, 66, 3, 208, 32, 70, ++ 73, 70, 21, 240, 69, 219, 4, 55, 32, 47, 226, 209, 221, 231, 212, 248, ++ 104, 50, 83, 248, 9, 80, 245, 177, 171, 121, 227, 177, 43, 121, 211, ++ 177, 35, 104, 147, 248, 60, 48, 43, 177, 213, 248, 204, 48, 154, 4, ++ 1, 213, 8, 155, 131, 177, 235, 104, 0, 34, 217, 104, 32, 70, 79, 244, ++ 128, 115, 238, 247, 254, 253, 35, 106, 24, 105, 10, 240, 8, 250, 41, ++ 70, 2, 70, 32, 70, 71, 240, 77, 218, 9, 241, 4, 9, 185, 241, 32, 15, ++ 214, 209, 212, 248, 8, 5, 61, 70, 22, 240, 43, 218, 181, 248, 90, 112, ++ 23, 244, 128, 71, 38, 208, 186, 241, 0, 15, 39, 208, 212, 248, 188, ++ 6, 41, 70, 28, 240, 140, 255, 0, 39, 35, 224, 216, 248, 8, 48, 11, 59, ++ 1, 43, 22, 216, 58, 177, 32, 70, 41, 70, 25, 240, 154, 251, 16, 177, ++ 12, 33, 70, 240, 128, 222, 2, 46, 9, 208, 32, 70, 41, 70, 25, 240, 14, ++ 218, 5, 46, 5, 216, 79, 240, 200, 67, 179, 64, 1, 213, 1, 39, 0, 224, ++ 0, 39, 186, 241, 0, 15, 3, 209, 0, 224, 87, 70, 7, 34, 0, 224, 9, 34, ++ 7, 155, 0, 150, 1, 147, 9, 155, 32, 70, 2, 147, 216, 248, 64, 48, 41, ++ 70, 3, 147, 216, 248, 68, 48, 4, 147, 91, 70, 1, 240, 181, 216, 0, 47, ++ 40, 208, 35, 104, 147, 248, 102, 49, 115, 177, 181, 248, 90, 48, 155, ++ 6, 10, 213, 7, 155, 67, 177, 213, 248, 236, 48, 43, 185, 212, 248, 200, ++ 6, 41, 70, 64, 240, 13, 219, 9, 224, 5, 46, 1, 208, 2, 46, 11, 209, ++ 152, 248, 30, 32, 152, 248, 28, 48, 154, 66, 5, 210, 40, 70, 11, 176, ++ 189, 232, 240, 79, 26, 240, 238, 154, 40, 70, 11, 176, 189, 232, 240, ++ 79, 255, 247, 96, 188, 11, 176, 189, 232, 240, 143, 0, 0, 45, 233, 240, ++ 79, 154, 70, 19, 136, 208, 248, 248, 96, 161, 176, 3, 240, 252, 3, 9, ++ 147, 179, 104, 148, 70, 11, 59, 186, 248, 2, 32, 1, 43, 4, 70, 139, ++ 70, 221, 248, 168, 144, 5, 104, 208, 248, 240, 128, 173, 248, 40, 32, ++ 151, 178, 11, 216, 12, 241, 16, 0, 65, 70, 6, 34, 205, 248, 24, 192, ++ 222, 247, 66, 251, 221, 248, 24, 192, 3, 70, 96, 177, 9, 154, 32, 70, ++ 178, 241, 16, 3, 24, 191, 1, 35, 0, 147, 0, 35, 1, 147, 6, 33, 12, 241, ++ 10, 2, 68, 224, 48, 108, 32, 177, 6, 147, 231, 247, 220, 250, 6, 155, ++ 115, 100, 72, 70, 231, 247, 212, 250, 48, 100, 40, 177, 198, 248, 68, ++ 144, 81, 70, 74, 70, 222, 247, 50, 251, 43, 104, 147, 248, 69, 48, 59, ++ 177, 213, 248, 100, 1, 186, 248, 2, 16, 39, 240, 142, 221, 170, 248, ++ 2, 0, 11, 47, 16, 209, 115, 104, 1, 43, 16, 208, 179, 104, 12, 43, 13, ++ 208, 0, 35, 0, 147, 33, 70, 40, 70, 90, 70, 67, 70, 25, 240, 170, 222, ++ 32, 70, 12, 33, 112, 224, 175, 177, 30, 47, 19, 208, 115, 104, 32, 70, ++ 19, 241, 255, 51, 24, 191, 1, 35, 0, 147, 152, 249, 52, 48, 66, 70, ++ 211, 241, 1, 3, 56, 191, 0, 35, 1, 147, 1, 33, 59, 70, 255, 247, 131, ++ 254, 171, 224, 43, 104, 0, 39, 155, 106, 169, 241, 6, 2, 203, 248, 44, ++ 48, 10, 241, 6, 3, 7, 147, 8, 146, 3, 147, 4, 146, 59, 70, 40, 70, 33, ++ 70, 88, 34, 0, 151, 1, 151, 2, 151, 0, 240, 244, 223, 57, 70, 12, 34, ++ 29, 168, 223, 243, 97, 246, 74, 75, 57, 70, 29, 147, 73, 75, 36, 34, ++ 30, 147, 12, 171, 24, 70, 6, 147, 31, 149, 223, 243, 85, 246, 189, 248, ++ 40, 32, 13, 241, 84, 9, 57, 70, 173, 248, 52, 32, 72, 70, 32, 34, 205, ++ 248, 48, 176, 223, 243, 72, 246, 6, 155, 8, 154, 28, 147, 7, 155, 2, ++ 146, 1, 147, 205, 248, 0, 144, 213, 248, 124, 6, 33, 70, 9, 154, 29, ++ 171, 48, 240, 177, 218, 7, 70, 0, 40, 101, 209, 189, 248, 52, 144, 185, ++ 241, 30, 15, 17, 209, 17, 155, 40, 70, 243, 100, 33, 70, 25, 240, 241, ++ 216, 242, 108, 168, 104, 49, 104, 30, 50, 59, 70, 245, 243, 98, 242, ++ 32, 70, 25, 33, 254, 247, 230, 255, 78, 224, 212, 248, 204, 48, 155, ++ 4, 6, 213, 213, 248, 80, 1, 89, 70, 7, 154, 8, 155, 62, 240, 208, 220, ++ 186, 248, 4, 48, 32, 70, 164, 248, 214, 48, 165, 248, 60, 51, 115, 104, ++ 66, 70, 19, 241, 255, 51, 24, 191, 1, 35, 0, 147, 152, 249, 52, 48, ++ 211, 241, 1, 3, 56, 191, 0, 35, 1, 147, 0, 33, 75, 70, 255, 247, 1, ++ 254, 32, 70, 89, 70, 255, 247, 174, 249, 213, 248, 108, 50, 156, 66, ++ 34, 208, 180, 248, 90, 48, 251, 185, 35, 109, 216, 7, 28, 213, 163, ++ 110, 89, 28, 25, 208, 4, 235, 131, 3, 218, 110, 170, 177, 17, 122, 1, ++ 41, 1, 208, 3, 41, 16, 209, 80, 137, 211, 121, 141, 232, 3, 0, 2, 241, ++ 20, 1, 2, 145, 0, 33, 4, 145, 5, 145, 205, 248, 12, 128, 40, 70, 33, ++ 70, 18, 105, 6, 240, 88, 254, 33, 176, 189, 232, 240, 143, 0, 191, 49, ++ 195, 131, 0, 185, 208, 131, 0, 45, 233, 240, 79, 208, 248, 248, 96, ++ 208, 248, 4, 113, 208, 248, 240, 160, 139, 176, 155, 70, 7, 150, 6, ++ 151, 4, 70, 5, 104, 208, 248, 244, 96, 11, 240, 194, 223, 154, 249, ++ 52, 144, 20, 154, 185, 241, 1, 15, 11, 241, 12, 7, 162, 241, 12, 8, ++ 24, 209, 56, 70, 65, 70, 5, 34, 229, 247, 17, 251, 104, 177, 195, 120, ++ 73, 70, 32, 70, 134, 248, 96, 48, 12, 240, 83, 219, 213, 248, 72, 1, ++ 33, 70, 74, 70, 57, 240, 211, 217, 26, 224, 32, 70, 73, 70, 10, 240, ++ 152, 222, 21, 224, 43, 104, 91, 107, 115, 177, 212, 248, 204, 48, 152, ++ 7, 10, 212, 56, 70, 65, 70, 5, 240, 116, 223, 40, 177, 212, 248, 204, ++ 48, 67, 244, 128, 115, 196, 248, 204, 48, 40, 70, 33, 70, 29, 240, 195, ++ 216, 20, 155, 182, 248, 108, 32, 0, 147, 8, 171, 1, 147, 9, 171, 2, ++ 147, 40, 70, 91, 70, 177, 110, 26, 240, 0, 222, 8, 155, 75, 177, 176, ++ 110, 8, 177, 231, 247, 135, 249, 8, 155, 189, 248, 36, 32, 179, 102, ++ 166, 248, 108, 32, 43, 104, 147, 248, 173, 32, 26, 177, 212, 248, 204, ++ 32, 81, 4, 2, 213, 147, 248, 175, 48, 83, 177, 154, 249, 52, 48, 1, ++ 43, 6, 209, 213, 248, 140, 1, 33, 70, 58, 70, 67, 70, 44, 240, 128, ++ 217, 163, 121, 19, 185, 1, 35, 133, 248, 160, 55, 212, 248, 4, 49, 219, ++ 139, 51, 177, 6, 158, 51, 120, 2, 43, 2, 209, 32, 70, 63, 240, 168, ++ 222, 32, 70, 8, 240, 105, 219, 32, 177, 32, 70, 1, 33, 240, 247, 135, ++ 250, 9, 224, 6, 159, 59, 120, 2, 43, 2, 209, 32, 70, 19, 240, 80, 252, ++ 32, 70, 237, 247, 96, 253, 7, 158, 179, 104, 179, 177, 0, 38, 0, 150, ++ 1, 150, 154, 249, 52, 48, 40, 70, 154, 27, 83, 66, 67, 235, 2, 3, 2, ++ 147, 33, 70, 1, 34, 4, 241, 188, 3, 3, 150, 4, 150, 0, 240, 163, 222, ++ 32, 70, 49, 70, 24, 240, 173, 216, 40, 70, 28, 240, 248, 255, 11, 176, ++ 189, 232, 240, 143, 0, 0, 45, 233, 240, 79, 163, 176, 146, 70, 12, 147, ++ 157, 248, 176, 32, 208, 248, 248, 48, 13, 146, 9, 147, 186, 248, 2, ++ 32, 208, 248, 240, 48, 1, 241, 10, 7, 186, 248, 4, 144, 4, 70, 11, 145, ++ 5, 104, 8, 146, 56, 70, 25, 70, 6, 34, 186, 248, 0, 176, 31, 250, 137, ++ 248, 10, 147, 222, 247, 86, 249, 0, 40, 46, 209, 40, 70, 33, 70, 58, ++ 70, 25, 240, 42, 249, 6, 70, 0, 40, 38, 208, 9, 154, 147, 104, 8, 43, ++ 1, 208, 10, 43, 32, 209, 114, 104, 66, 244, 128, 82, 114, 96, 42, 104, ++ 146, 248, 102, 33, 114, 177, 187, 241, 3, 15, 11, 209, 12, 155, 13, ++ 154, 0, 147, 1, 146, 213, 248, 80, 8, 33, 70, 11, 154, 83, 70, 24, 240, ++ 149, 252, 146, 224, 8, 43, 2, 209, 8, 155, 2, 43, 3, 224, 10, 43, 7, ++ 209, 8, 154, 4, 42, 4, 208, 0, 35, 0, 147, 32, 70, 6, 33, 128, 224, ++ 184, 241, 0, 15, 6, 208, 205, 248, 0, 176, 32, 70, 1, 33, 58, 70, 67, ++ 70, 119, 224, 65, 70, 12, 34, 31, 168, 223, 243, 164, 244, 59, 75, 65, ++ 70, 31, 147, 59, 75, 36, 34, 32, 147, 14, 171, 24, 70, 7, 147, 33, 149, ++ 223, 243, 152, 244, 8, 154, 173, 248, 72, 144, 13, 241, 92, 9, 15, 146, ++ 65, 70, 32, 34, 72, 70, 205, 248, 56, 176, 16, 150, 223, 243, 138, 244, ++ 7, 155, 12, 154, 30, 147, 10, 241, 6, 3, 1, 147, 147, 31, 2, 147, 205, ++ 248, 0, 144, 213, 248, 124, 6, 33, 70, 176, 34, 31, 171, 48, 240, 241, ++ 216, 0, 40, 71, 209, 189, 248, 72, 48, 0, 43, 58, 209, 187, 241, 1, ++ 15, 55, 209, 8, 154, 2, 42, 52, 209, 10, 33, 32, 70, 254, 247, 47, 254, ++ 243, 104, 17, 154, 6, 241, 20, 1, 27, 177, 24, 105, 0, 40, 8, 191, 0, ++ 35, 3, 147, 13, 155, 1, 32, 79, 240, 3, 12, 79, 240, 0, 14, 141, 232, ++ 1, 80, 4, 146, 5, 147, 32, 70, 51, 70, 10, 154, 241, 247, 52, 251, 33, ++ 70, 6, 70, 40, 70, 24, 240, 17, 223, 70, 177, 213, 248, 120, 4, 15, ++ 73, 180, 248, 26, 33, 51, 70, 62, 240, 246, 223, 17, 224, 9, 154, 168, ++ 104, 17, 104, 51, 70, 79, 244, 155, 114, 245, 243, 119, 240, 8, 224, ++ 25, 28, 205, 248, 0, 176, 32, 70, 24, 191, 1, 33, 58, 70, 254, 247, ++ 151, 248, 35, 176, 189, 232, 240, 143, 197, 208, 131, 0, 201, 208, 131, ++ 0, 201, 66, 2, 0, 247, 181, 13, 70, 145, 178, 4, 70, 2, 240, 178, 250, ++ 6, 70, 0, 40, 35, 208, 208, 248, 248, 112, 208, 248, 240, 32, 187, 104, ++ 24, 43, 28, 216, 15, 73, 153, 64, 25, 213, 21, 240, 2, 3, 4, 209, 5, ++ 33, 0, 147, 254, 247, 116, 248, 17, 224, 32, 70, 49, 70, 24, 240, 205, ++ 222, 214, 248, 236, 48, 3, 43, 9, 208, 160, 104, 57, 104, 79, 244, 155, ++ 114, 0, 35, 3, 176, 189, 232, 240, 64, 245, 243, 55, 176, 3, 176, 240, ++ 189, 0, 191, 128, 0, 160, 0, 45, 233, 240, 65, 5, 104, 142, 176, 43, ++ 104, 4, 70, 27, 126, 208, 248, 248, 128, 208, 248, 240, 96, 0, 43, 0, ++ 240, 154, 128, 0, 33, 40, 70, 2, 240, 121, 255, 40, 105, 47, 240, 137, ++ 222, 1, 70, 24, 177, 168, 104, 232, 247, 77, 253, 140, 224, 43, 104, ++ 147, 248, 49, 48, 139, 177, 216, 248, 4, 48, 3, 43, 13, 209, 216, 248, ++ 8, 48, 18, 43, 3, 209, 32, 70, 23, 240, 218, 223, 124, 224, 19, 43, ++ 3, 209, 200, 248, 4, 0, 32, 70, 116, 224, 216, 248, 8, 112, 24, 47, ++ 12, 216, 59, 75, 187, 64, 9, 213, 180, 249, 84, 48, 32, 70, 0, 147, ++ 2, 33, 50, 70, 0, 35, 254, 247, 27, 248, 101, 224, 167, 241, 11, 3, ++ 1, 43, 20, 216, 216, 248, 4, 48, 32, 70, 19, 241, 255, 51, 24, 191, ++ 1, 35, 0, 147, 150, 249, 52, 48, 50, 70, 211, 241, 1, 3, 56, 191, 0, ++ 35, 1, 147, 2, 33, 0, 35, 255, 247, 160, 251, 76, 224, 239, 185, 213, ++ 248, 200, 52, 0, 43, 71, 208, 163, 121, 0, 43, 68, 209, 99, 121, 0, ++ 43, 65, 208, 35, 122, 0, 43, 62, 209, 34, 126, 4, 241, 25, 1, 6, 168, ++ 5, 146, 222, 247, 4, 248, 40, 70, 33, 70, 6, 170, 5, 155, 0, 151, 1, ++ 151, 2, 151, 28, 240, 5, 219, 45, 224, 6, 47, 14, 209, 32, 70, 7, 33, ++ 254, 247, 58, 253, 213, 248, 208, 36, 213, 248, 204, 52, 2, 50, 32, ++ 70, 83, 248, 34, 16, 253, 247, 84, 252, 28, 224, 25, 47, 26, 209, 40, ++ 70, 33, 70, 50, 70, 24, 240, 170, 255, 7, 70, 152, 177, 168, 104, 216, ++ 248, 0, 16, 79, 244, 155, 114, 0, 35, 244, 243, 150, 247, 0, 35, 0, ++ 147, 33, 70, 40, 70, 58, 70, 51, 70, 25, 240, 100, 219, 32, 70, 11, ++ 33, 254, 247, 18, 253, 14, 176, 189, 232, 240, 129, 0, 191, 128, 0, ++ 160, 0, 45, 233, 240, 79, 5, 70, 155, 176, 15, 70, 208, 248, 0, 176, ++ 153, 70, 0, 43, 0, 240, 45, 130, 131, 104, 91, 104, 89, 248, 3, 48, ++ 94, 104, 155, 104, 3, 147, 6, 42, 0, 242, 37, 130, 223, 232, 18, 240, ++ 7, 0, 35, 2, 57, 0, 35, 2, 235, 0, 35, 2, 101, 1, 88, 70, 105, 104, ++ 9, 241, 20, 2, 113, 35, 82, 240, 43, 222, 128, 70, 0, 40, 0, 240, 21, ++ 130, 132, 104, 0, 35, 95, 34, 4, 241, 18, 10, 35, 116, 25, 70, 98, 116, ++ 80, 70, 2, 147, 223, 243, 17, 243, 71, 240, 136, 2, 17, 10, 225, 116, ++ 34, 117, 50, 139, 6, 241, 28, 9, 17, 10, 97, 117, 162, 117, 73, 70, ++ 88, 70, 32, 34, 5, 240, 171, 223, 73, 70, 32, 34, 4, 241, 31, 0, 221, ++ 247, 123, 255, 2, 155, 11, 34, 50, 96, 153, 70, 241, 225, 182, 248, ++ 206, 48, 128, 43, 4, 209, 65, 244, 158, 87, 71, 240, 8, 7, 3, 224, 4, ++ 43, 8, 191, 65, 244, 228, 119, 180, 136, 128, 43, 173, 248, 102, 64, ++ 37, 209, 23, 244, 128, 83, 35, 208, 181, 248, 16, 128, 24, 240, 1, 8, ++ 8, 209, 40, 70, 30, 240, 31, 219, 40, 70, 30, 240, 64, 219, 1, 48, 0, ++ 240, 203, 129, 43, 104, 105, 104, 211, 248, 100, 6, 57, 240, 127, 223, ++ 181, 248, 124, 48, 189, 248, 102, 32, 38, 51, 195, 24, 18, 240, 7, 2, ++ 155, 178, 5, 208, 194, 241, 8, 2, 155, 24, 155, 178, 0, 224, 0, 35, ++ 113, 52, 27, 25, 88, 70, 105, 104, 9, 241, 20, 2, 155, 178, 82, 240, ++ 190, 221, 128, 70, 0, 40, 0, 240, 168, 129, 132, 104, 0, 33, 95, 34, ++ 4, 241, 18, 10, 34, 116, 97, 116, 80, 70, 223, 243, 166, 242, 59, 10, ++ 227, 116, 39, 117, 51, 139, 6, 241, 28, 1, 26, 10, 163, 117, 98, 117, ++ 4, 241, 31, 0, 32, 34, 221, 247, 24, 255, 178, 136, 4, 241, 113, 0, ++ 177, 104, 221, 247, 18, 255, 189, 248, 102, 48, 26, 10, 66, 234, 3, ++ 35, 164, 248, 111, 48, 182, 248, 206, 48, 128, 43, 51, 209, 248, 4, ++ 49, 213, 33, 70, 13, 241, 102, 2, 40, 70, 30, 240, 117, 218, 189, 248, ++ 102, 48, 26, 10, 66, 234, 3, 35, 164, 248, 111, 48, 217, 248, 8, 48, ++ 153, 5, 15, 213, 43, 104, 34, 70, 211, 248, 100, 6, 105, 104, 13, 241, ++ 102, 3, 57, 240, 85, 223, 189, 248, 102, 48, 26, 10, 66, 234, 3, 35, ++ 164, 248, 111, 48, 163, 123, 40, 70, 0, 147, 49, 70, 82, 70, 59, 70, ++ 30, 240, 172, 216, 1, 48, 6, 209, 219, 248, 4, 0, 65, 70, 0, 34, 230, ++ 247, 164, 254, 70, 225, 148, 248, 111, 32, 148, 248, 112, 48, 67, 234, ++ 2, 35, 34, 138, 211, 24, 155, 178, 26, 10, 66, 234, 3, 35, 35, 130, ++ 12, 35, 15, 225, 144, 248, 122, 48, 176, 248, 124, 192, 27, 1, 3, 240, ++ 48, 3, 65, 234, 3, 7, 71, 244, 96, 119, 191, 178, 0, 35, 186, 7, 84, ++ 191, 12, 241, 113, 12, 12, 241, 121, 12, 31, 250, 140, 252, 173, 248, ++ 102, 48, 88, 70, 99, 70, 105, 104, 9, 241, 20, 2, 205, 248, 8, 192, ++ 82, 240, 46, 221, 221, 248, 8, 192, 128, 70, 0, 40, 0, 240, 22, 129, ++ 132, 104, 95, 35, 79, 240, 0, 9, 4, 241, 18, 10, 172, 241, 18, 2, 35, ++ 116, 73, 70, 132, 248, 17, 144, 80, 70, 223, 243, 15, 242, 59, 10, 227, ++ 116, 39, 117, 181, 248, 124, 48, 5, 241, 190, 1, 26, 10, 163, 117, 98, ++ 117, 4, 241, 31, 0, 32, 34, 221, 247, 128, 254, 16, 34, 5, 241, 142, ++ 1, 4, 241, 63, 0, 221, 247, 121, 254, 8, 34, 5, 241, 254, 1, 4, 241, ++ 79, 0, 221, 247, 114, 254, 181, 248, 124, 32, 5, 241, 90, 1, 4, 241, ++ 113, 0, 173, 248, 102, 32, 221, 247, 104, 254, 189, 248, 102, 48, 40, ++ 70, 26, 10, 66, 234, 3, 35, 164, 248, 111, 48, 163, 123, 49, 70, 0, ++ 147, 82, 70, 7, 240, 3, 3, 30, 240, 40, 216, 1, 48, 7, 209, 65, 70, ++ 219, 248, 4, 0, 74, 70, 230, 247, 32, 254, 200, 70, 197, 224, 34, 138, ++ 189, 248, 102, 48, 142, 224, 182, 248, 206, 48, 128, 43, 64, 240, 185, ++ 128, 180, 136, 219, 248, 100, 6, 105, 104, 173, 248, 102, 64, 57, 240, ++ 111, 222, 181, 248, 124, 48, 189, 248, 102, 32, 38, 51, 113, 52, 195, ++ 24, 18, 240, 7, 2, 164, 178, 155, 178, 3, 208, 194, 241, 8, 2, 155, ++ 24, 155, 178, 227, 24, 88, 70, 105, 104, 9, 241, 20, 2, 155, 178, 82, ++ 240, 175, 220, 128, 70, 0, 40, 0, 240, 153, 128, 132, 104, 79, 240, ++ 0, 12, 95, 34, 4, 241, 18, 10, 132, 248, 17, 192, 97, 70, 71, 244, 156, ++ 87, 34, 116, 80, 70, 205, 248, 8, 192, 223, 243, 144, 241, 59, 10, 227, ++ 116, 39, 117, 51, 139, 6, 241, 28, 1, 26, 10, 163, 117, 98, 117, 4, ++ 241, 31, 0, 32, 34, 221, 247, 2, 254, 13, 241, 104, 9, 177, 104, 178, ++ 136, 4, 241, 113, 0, 221, 247, 250, 253, 57, 248, 2, 61, 33, 70, 26, ++ 10, 66, 234, 3, 35, 164, 248, 111, 48, 74, 70, 40, 70, 30, 240, 100, ++ 217, 189, 248, 102, 48, 26, 10, 66, 234, 3, 35, 164, 248, 111, 48, 43, ++ 104, 105, 104, 211, 248, 100, 6, 34, 70, 75, 70, 57, 240, 73, 222, 189, ++ 248, 102, 48, 40, 70, 26, 10, 66, 234, 3, 35, 164, 248, 111, 48, 163, ++ 123, 49, 70, 0, 147, 82, 70, 59, 70, 29, 240, 160, 223, 1, 48, 221, ++ 248, 8, 192, 9, 209, 65, 70, 98, 70, 219, 248, 4, 0, 230, 247, 150, ++ 253, 221, 248, 8, 192, 224, 70, 57, 224, 148, 248, 111, 32, 148, 248, ++ 112, 48, 67, 234, 2, 35, 34, 138, 211, 24, 155, 178, 26, 10, 66, 234, ++ 3, 35, 35, 130, 13, 35, 51, 96, 79, 240, 1, 9, 43, 224, 32, 70, 7, 240, ++ 3, 1, 6, 241, 140, 2, 5, 171, 225, 243, 188, 242, 232, 177, 10, 241, ++ 77, 0, 5, 169, 16, 34, 221, 247, 161, 253, 107, 104, 65, 70, 218, 104, ++ 88, 70, 242, 247, 129, 254, 3, 155, 219, 248, 8, 0, 211, 248, 192, 16, ++ 79, 244, 122, 114, 0, 35, 244, 243, 79, 245, 79, 240, 1, 8, 5, 224, ++ 152, 70, 3, 224, 79, 240, 0, 8, 0, 224, 128, 70, 64, 70, 27, 176, 189, ++ 232, 240, 143, 3, 35, 227, 115, 182, 248, 206, 48, 80, 70, 128, 43, ++ 20, 191, 254, 35, 2, 35, 0, 248, 5, 59, 6, 241, 92, 1, 8, 34, 221, 247, ++ 116, 253, 185, 241, 0, 15, 207, 208, 191, 231, 45, 233, 240, 65, 4, ++ 70, 0, 40, 95, 208, 3, 105, 0, 43, 92, 208, 94, 105, 0, 46, 89, 208, ++ 179, 104, 0, 43, 86, 208, 91, 104, 195, 88, 0, 43, 82, 208, 93, 104, ++ 0, 45, 79, 208, 131, 104, 95, 5, 7, 212, 135, 108, 7, 240, 2, 7, 0, ++ 47, 20, 191, 1, 39, 2, 39, 0, 224, 3, 39, 43, 104, 12, 43, 19, 208, ++ 13, 43, 33, 208, 11, 43, 60, 209, 149, 248, 208, 48, 90, 28, 2, 43, ++ 133, 248, 208, 32, 31, 216, 5, 241, 92, 0, 8, 33, 225, 243, 70, 242, ++ 48, 70, 57, 70, 0, 34, 39, 224, 149, 248, 208, 48, 90, 28, 2, 43, 133, ++ 248, 208, 32, 15, 216, 5, 241, 92, 0, 8, 33, 225, 243, 54, 242, 48, ++ 70, 57, 70, 2, 34, 23, 224, 149, 248, 208, 48, 90, 28, 2, 43, 133, 248, ++ 208, 32, 4, 217, 48, 70, 189, 232, 240, 65, 29, 240, 70, 159, 8, 33, ++ 5, 241, 92, 0, 225, 243, 33, 242, 181, 248, 206, 32, 48, 70, 4, 42, ++ 57, 70, 24, 191, 6, 34, 35, 70, 189, 232, 240, 65, 255, 247, 69, 189, ++ 189, 232, 240, 129, 45, 233, 255, 65, 4, 70, 0, 33, 1, 168, 12, 34, ++ 223, 243, 129, 240, 0, 44, 81, 208, 35, 104, 0, 43, 78, 208, 98, 104, ++ 0, 42, 75, 208, 211, 248, 36, 1, 1, 169, 69, 240, 224, 223, 0, 37, 43, ++ 224, 150, 248, 36, 48, 218, 6, 39, 213, 163, 104, 91, 104, 243, 88, ++ 27, 179, 211, 248, 4, 128, 184, 241, 0, 15, 30, 208, 21, 185, 32, 70, ++ 30, 240, 167, 216, 13, 35, 200, 248, 0, 48, 179, 104, 91, 5, 7, 212, ++ 183, 108, 7, 240, 2, 7, 0, 47, 20, 191, 1, 39, 2, 39, 0, 224, 3, 39, ++ 8, 241, 92, 0, 8, 33, 225, 243, 215, 241, 32, 70, 57, 70, 6, 34, 51, ++ 70, 255, 247, 1, 253, 1, 53, 35, 104, 1, 169, 211, 248, 36, 1, 24, 240, ++ 84, 252, 6, 70, 0, 40, 202, 209, 85, 177, 212, 248, 12, 33, 90, 177, ++ 35, 104, 212, 248, 8, 17, 152, 104, 51, 70, 244, 243, 112, 244, 3, 224, ++ 35, 138, 35, 240, 1, 3, 35, 130, 189, 232, 255, 129, 45, 233, 240, 79, ++ 5, 70, 137, 176, 14, 70, 208, 248, 0, 160, 31, 70, 0, 43, 0, 240, 93, ++ 129, 131, 104, 91, 104, 251, 88, 92, 104, 211, 248, 8, 128, 0, 44, 0, ++ 240, 86, 129, 184, 241, 0, 15, 0, 240, 84, 129, 187, 104, 88, 5, 7, ++ 212, 187, 108, 3, 240, 2, 3, 0, 43, 20, 191, 1, 35, 2, 35, 0, 224, 3, ++ 35, 180, 248, 206, 0, 7, 147, 4, 40, 2, 208, 128, 40, 64, 240, 66, 129, ++ 51, 125, 150, 248, 19, 144, 67, 234, 9, 41, 25, 240, 3, 3, 6, 147, 2, ++ 209, 228, 247, 35, 254, 6, 144, 4, 241, 92, 11, 1, 32, 8, 35, 6, 241, ++ 23, 1, 90, 70, 224, 243, 180, 245, 131, 69, 0, 240, 44, 129, 35, 104, ++ 12, 43, 0, 240, 158, 128, 13, 43, 0, 240, 245, 128, 11, 43, 64, 240, ++ 34, 129, 9, 244, 220, 115, 179, 245, 132, 127, 64, 240, 28, 129, 4, ++ 241, 60, 12, 96, 70, 6, 241, 31, 1, 32, 34, 205, 248, 16, 192, 221, ++ 247, 77, 252, 187, 104, 105, 104, 19, 244, 128, 111, 221, 248, 16, 192, ++ 7, 241, 20, 3, 18, 208, 8, 241, 72, 2, 0, 146, 184, 248, 6, 32, 24, ++ 70, 1, 146, 4, 241, 140, 2, 2, 146, 162, 138, 194, 49, 3, 146, 99, 70, ++ 4, 241, 28, 2, 224, 243, 16, 245, 32, 224, 24, 70, 194, 49, 6, 34, 5, ++ 147, 205, 248, 16, 192, 221, 247, 22, 252, 5, 155, 221, 248, 16, 192, ++ 0, 40, 0, 240, 232, 128, 8, 241, 72, 2, 0, 146, 184, 248, 6, 32, 105, ++ 104, 1, 146, 4, 241, 140, 2, 2, 146, 162, 138, 24, 70, 3, 146, 194, ++ 49, 4, 241, 28, 2, 99, 70, 224, 243, 238, 246, 25, 244, 128, 127, 16, ++ 208, 51, 138, 26, 10, 66, 234, 3, 35, 155, 178, 92, 43, 64, 242, 164, ++ 128, 48, 70, 6, 153, 4, 241, 140, 2, 224, 243, 237, 247, 0, 40, 0, 240, ++ 193, 128, 51, 138, 26, 10, 66, 234, 3, 34, 146, 178, 94, 42, 64, 242, ++ 147, 128, 150, 248, 111, 16, 150, 248, 112, 48, 67, 234, 1, 35, 3, 241, ++ 95, 1, 138, 66, 192, 240, 136, 128, 67, 177, 226, 136, 154, 66, 5, 209, ++ 6, 241, 113, 0, 225, 104, 221, 247, 205, 251, 48, 177, 104, 104, 7, ++ 241, 20, 1, 17, 34, 82, 240, 247, 219, 156, 224, 132, 248, 208, 0, 43, ++ 104, 216, 248, 192, 16, 152, 104, 244, 243, 180, 243, 88, 70, 8, 33, ++ 225, 243, 214, 240, 40, 70, 7, 153, 2, 34, 59, 70, 255, 247, 0, 252, ++ 137, 224, 9, 244, 216, 115, 179, 245, 128, 127, 64, 240, 132, 128, 25, ++ 244, 128, 127, 7, 208, 48, 70, 6, 153, 4, 241, 140, 2, 224, 243, 164, ++ 247, 0, 40, 120, 208, 0, 35, 132, 248, 208, 48, 43, 104, 216, 248, 192, ++ 16, 152, 104, 244, 243, 143, 243, 34, 138, 7, 241, 20, 6, 35, 139, 80, ++ 70, 141, 232, 68, 0, 105, 104, 4, 241, 172, 2, 82, 240, 93, 219, 180, ++ 248, 206, 48, 128, 43, 2, 209, 16, 35, 35, 96, 24, 224, 4, 43, 22, 209, ++ 13, 35, 35, 96, 43, 138, 217, 7, 7, 212, 40, 70, 29, 240, 84, 223, 40, ++ 70, 29, 240, 117, 223, 1, 48, 77, 208, 88, 70, 8, 33, 225, 243, 143, ++ 240, 40, 70, 7, 153, 4, 34, 59, 70, 255, 247, 185, 251, 180, 248, 206, ++ 48, 128, 43, 1, 208, 4, 43, 8, 209, 107, 104, 80, 70, 219, 104, 121, ++ 33, 0, 147, 50, 70, 6, 35, 237, 247, 133, 249, 180, 248, 206, 48, 128, ++ 43, 48, 209, 35, 224, 25, 244, 128, 127, 21, 208, 51, 138, 26, 10, 66, ++ 234, 3, 35, 155, 178, 92, 43, 7, 216, 218, 248, 0, 48, 211, 248, 136, ++ 48, 90, 110, 1, 50, 90, 102, 29, 224, 48, 70, 6, 153, 4, 241, 140, 2, ++ 224, 243, 65, 247, 176, 177, 0, 35, 132, 248, 208, 48, 43, 104, 216, ++ 248, 192, 16, 152, 104, 244, 243, 45, 243, 16, 35, 35, 96, 40, 70, 29, ++ 240, 110, 221, 7, 224, 24, 70, 6, 224, 32, 70, 4, 224, 64, 70, 2, 224, ++ 0, 32, 0, 224, 1, 32, 9, 176, 189, 232, 240, 143, 45, 233, 243, 71, ++ 11, 158, 4, 70, 144, 70, 154, 70, 137, 70, 0, 41, 71, 208, 0, 46, 71, ++ 208, 131, 104, 0, 104, 91, 104, 243, 88, 93, 104, 159, 104, 41, 70, ++ 28, 240, 119, 251, 9, 35, 43, 96, 153, 248, 0, 48, 32, 104, 48, 43, ++ 99, 104, 41, 70, 179, 248, 90, 48, 74, 70, 12, 191, 3, 240, 128, 3, ++ 3, 240, 4, 3, 165, 248, 206, 48, 10, 155, 205, 248, 0, 160, 1, 147, ++ 67, 70, 82, 240, 126, 219, 40, 179, 99, 105, 1, 43, 1, 209, 248, 136, ++ 0, 179, 0, 35, 133, 248, 208, 48, 35, 104, 215, 248, 192, 16, 152, 104, ++ 244, 243, 223, 242, 10, 35, 43, 96, 179, 104, 91, 5, 7, 212, 177, 108, ++ 1, 240, 2, 1, 0, 41, 20, 191, 1, 33, 2, 33, 0, 224, 3, 33, 32, 70, 0, ++ 34, 51, 70, 255, 247, 34, 251, 1, 32, 2, 224, 8, 70, 0, 224, 48, 70, ++ 189, 232, 252, 135, 112, 71, 112, 181, 12, 70, 25, 179, 145, 248, 172, ++ 48, 3, 179, 145, 248, 55, 49, 235, 185, 209, 248, 64, 81, 173, 185, ++ 13, 78, 72, 105, 214, 248, 200, 48, 152, 71, 3, 40, 9, 217, 13, 224, ++ 212, 248, 64, 49, 19, 185, 196, 248, 64, 1, 1, 224, 3, 136, 235, 130, ++ 5, 70, 51, 111, 96, 105, 152, 71, 0, 40, 241, 209, 96, 105, 16, 177, ++ 1, 75, 91, 111, 152, 71, 112, 189, 208, 134, 135, 0, 208, 248, 148, ++ 48, 24, 106, 4, 75, 152, 66, 12, 191, 79, 244, 22, 96, 79, 244, 150, ++ 112, 112, 71, 0, 191, 80, 32, 8, 0, 11, 104, 210, 43, 7, 216, 130, 111, ++ 80, 139, 40, 177, 0, 235, 67, 0, 8, 96, 1, 32, 112, 71, 0, 32, 112, ++ 71, 0, 0, 45, 233, 248, 67, 12, 70, 208, 248, 136, 144, 6, 70, 1, 70, ++ 35, 70, 0, 34, 10, 224, 221, 7, 5, 213, 77, 105, 29, 185, 1, 37, 149, ++ 64, 36, 234, 5, 4, 1, 50, 91, 8, 4, 49, 0, 43, 242, 209, 7, 70, 37, ++ 70, 21, 224, 234, 7, 17, 213, 17, 75, 120, 105, 27, 106, 152, 71, 65, ++ 246, 65, 120, 2, 224, 10, 32, 227, 243, 98, 241, 217, 248, 80, 49, 19, ++ 244, 127, 79, 2, 208, 184, 241, 1, 8, 244, 209, 109, 8, 4, 55, 0, 45, ++ 231, 209, 7, 224, 227, 7, 3, 213, 5, 75, 112, 105, 91, 106, 152, 71, ++ 100, 8, 4, 54, 0, 44, 245, 209, 189, 232, 248, 131, 0, 191, 208, 134, ++ 135, 0, 16, 181, 4, 70, 192, 111, 10, 70, 1, 107, 65, 242, 107, 3, 153, ++ 66, 20, 209, 131, 106, 163, 245, 153, 115, 24, 43, 15, 216, 8, 73, 153, ++ 64, 12, 213, 90, 185, 4, 33, 2, 35, 233, 243, 66, 245, 4, 33, 224, 111, ++ 10, 70, 2, 35, 189, 232, 16, 64, 233, 243, 32, 181, 16, 189, 0, 191, ++ 128, 64, 0, 192, 79, 240, 255, 48, 112, 71, 3, 104, 45, 233, 240, 65, ++ 79, 244, 64, 65, 4, 70, 0, 34, 211, 248, 116, 100, 208, 248, 136, 112, ++ 32, 240, 22, 220, 163, 111, 27, 105, 19, 177, 32, 70, 31, 240, 4, 216, ++ 37, 109, 150, 248, 28, 49, 21, 240, 2, 5, 24, 191, 79, 244, 0, 117, ++ 59, 179, 214, 248, 32, 49, 35, 187, 150, 248, 232, 16, 1, 34, 224, 111, ++ 233, 243, 186, 244, 150, 248, 88, 17, 255, 41, 3, 208, 224, 111, 1, ++ 34, 233, 243, 178, 244, 150, 248, 232, 48, 150, 248, 88, 33, 1, 33, ++ 17, 250, 3, 243, 255, 42, 2, 208, 17, 250, 2, 242, 19, 67, 183, 248, ++ 158, 4, 67, 234, 5, 2, 3, 67, 66, 234, 5, 1, 167, 248, 158, 52, 21, ++ 70, 0, 224, 41, 70, 224, 111, 42, 70, 0, 35, 189, 232, 240, 65, 233, ++ 243, 171, 180, 56, 181, 208, 248, 68, 49, 4, 70, 208, 248, 136, 80, ++ 243, 185, 208, 248, 240, 48, 1, 59, 192, 248, 240, 48, 195, 185, 213, ++ 248, 32, 49, 3, 104, 147, 248, 42, 56, 11, 177, 3, 33, 0, 224, 1, 33, ++ 10, 70, 32, 240, 190, 219, 1, 35, 197, 248, 40, 49, 213, 248, 32, 49, ++ 213, 248, 40, 49, 32, 70, 4, 33, 189, 232, 56, 64, 33, 240, 19, 157, ++ 56, 189, 208, 248, 136, 48, 211, 248, 128, 1, 1, 177, 8, 96, 18, 177, ++ 211, 248, 132, 49, 19, 96, 112, 71, 0, 0, 45, 233, 240, 79, 153, 70, ++ 3, 104, 133, 176, 27, 104, 4, 70, 140, 70, 147, 248, 62, 160, 26, 177, ++ 219, 105, 211, 248, 64, 176, 1, 224, 79, 240, 255, 59, 79, 240, 0, 8, ++ 67, 70, 71, 70, 70, 70, 69, 70, 212, 248, 64, 33, 82, 177, 78, 73, 208, ++ 138, 9, 104, 2, 146, 81, 248, 32, 16, 196, 248, 64, 17, 0, 33, 209, ++ 130, 13, 224, 4, 235, 140, 2, 80, 105, 72, 74, 1, 147, 205, 248, 0, ++ 192, 18, 111, 144, 71, 1, 155, 2, 144, 221, 248, 0, 192, 40, 179, 2, ++ 154, 146, 104, 162, 248, 2, 192, 186, 241, 0, 15, 17, 208, 154, 178, ++ 32, 104, 2, 169, 1, 147, 205, 248, 0, 192, 8, 240, 222, 216, 1, 155, ++ 221, 248, 0, 192, 40, 185, 14, 185, 178, 70, 2, 224, 168, 70, 130, 70, ++ 6, 70, 2, 154, 58, 177, 1, 51, 30, 177, 17, 136, 241, 130, 22, 70, 1, ++ 224, 22, 70, 21, 70, 1, 55, 95, 69, 189, 211, 4, 235, 140, 3, 88, 105, ++ 46, 75, 91, 111, 152, 71, 184, 241, 0, 15, 4, 208, 32, 104, 65, 70, ++ 242, 247, 184, 253, 8, 224, 186, 241, 0, 15, 5, 208, 37, 177, 32, 104, ++ 41, 70, 242, 247, 175, 253, 58, 224, 32, 70, 3, 169, 0, 34, 255, 247, ++ 127, 255, 49, 224, 32, 75, 234, 138, 27, 104, 83, 248, 34, 96, 0, 35, ++ 235, 130, 35, 104, 173, 104, 27, 104, 41, 70, 211, 248, 136, 48, 211, ++ 248, 20, 35, 1, 50, 195, 248, 20, 35, 3, 155, 171, 97, 212, 248, 148, ++ 48, 88, 106, 9, 240, 222, 251, 235, 138, 19, 244, 0, 98, 3, 244, 255, ++ 97, 24, 191, 79, 244, 64, 66, 3, 244, 128, 83, 66, 234, 209, 2, 0, 43, ++ 12, 191, 79, 244, 128, 83, 79, 244, 192, 83, 19, 67, 235, 130, 32, 104, ++ 2, 153, 244, 247, 107, 248, 53, 70, 2, 149, 0, 45, 202, 209, 217, 248, ++ 0, 48, 95, 69, 59, 68, 201, 248, 0, 48, 52, 191, 0, 32, 1, 32, 5, 176, ++ 189, 232, 240, 143, 0, 191, 32, 7, 0, 0, 208, 134, 135, 0, 56, 181, ++ 3, 104, 4, 70, 27, 104, 147, 248, 32, 80, 0, 45, 36, 209, 192, 111, ++ 230, 247, 251, 254, 1, 33, 32, 70, 33, 240, 239, 218, 224, 111, 233, ++ 243, 198, 241, 41, 70, 32, 70, 31, 240, 80, 217, 224, 111, 233, 243, ++ 83, 244, 32, 70, 30, 240, 132, 222, 212, 248, 148, 48, 88, 106, 8, 240, ++ 20, 252, 35, 104, 132, 248, 118, 80, 27, 104, 1, 34, 131, 248, 32, 32, ++ 224, 111, 189, 232, 56, 64, 230, 247, 162, 190, 56, 189, 208, 248, 148, ++ 48, 112, 181, 4, 70, 0, 43, 45, 208, 40, 32, 226, 243, 175, 247, 0, ++ 37, 180, 248, 18, 97, 2, 224, 10, 32, 226, 243, 168, 247, 64, 33, 32, ++ 70, 32, 240, 222, 220, 4, 40, 5, 208, 64, 33, 32, 70, 32, 240, 216, ++ 220, 7, 40, 5, 209, 10, 61, 6, 241, 19, 3, 91, 25, 9, 43, 234, 216, ++ 64, 33, 32, 70, 32, 240, 204, 220, 4, 40, 1, 208, 7, 40, 3, 209, 3, ++ 35, 196, 248, 68, 49, 112, 189, 32, 70, 64, 33, 189, 232, 112, 64, 32, ++ 240, 190, 156, 112, 189, 144, 248, 172, 32, 160, 248, 160, 16, 58, 177, ++ 3, 104, 211, 248, 116, 52, 147, 248, 28, 49, 11, 185, 31, 240, 232, ++ 154, 112, 71, 45, 233, 240, 65, 4, 70, 0, 104, 13, 70, 208, 248, 116, ++ 100, 157, 248, 24, 16, 150, 248, 28, 1, 157, 248, 28, 112, 0, 40, 115, ++ 208, 10, 177, 134, 248, 172, 80, 9, 177, 134, 248, 69, 49, 148, 248, ++ 10, 49, 0, 43, 105, 208, 142, 33, 32, 70, 32, 240, 146, 220, 65, 0, ++ 137, 178, 1, 241, 78, 8, 76, 49, 1, 45, 148, 191, 0, 35, 1, 35, 1, 61, ++ 237, 178, 214, 248, 32, 33, 1, 45, 134, 248, 29, 49, 134, 248, 72, 49, ++ 150, 248, 172, 48, 140, 191, 0, 37, 1, 37, 1, 42, 31, 250, 136, 248, ++ 137, 178, 134, 248, 74, 81, 134, 248, 69, 49, 24, 208, 2, 211, 2, 42, ++ 41, 209, 31, 224, 1, 34, 32, 70, 33, 240, 24, 218, 150, 248, 232, 48, ++ 150, 248, 88, 33, 21, 250, 3, 243, 255, 42, 219, 178, 134, 248, 176, ++ 48, 25, 208, 133, 240, 1, 1, 17, 250, 2, 242, 19, 67, 17, 224, 32, 70, ++ 2, 34, 33, 240, 3, 218, 21, 177, 150, 248, 46, 49, 9, 224, 150, 248, ++ 44, 49, 6, 224, 32, 70, 33, 240, 249, 217, 150, 248, 232, 48, 21, 250, ++ 3, 243, 134, 248, 176, 48, 32, 70, 65, 70, 150, 248, 176, 32, 33, 240, ++ 237, 217, 143, 177, 212, 248, 136, 48, 211, 248, 88, 33, 208, 7, 11, ++ 212, 179, 248, 182, 54, 217, 7, 7, 212, 35, 104, 41, 70, 27, 106, 24, ++ 105, 189, 232, 240, 65, 9, 240, 14, 185, 189, 232, 240, 129, 112, 181, ++ 4, 70, 208, 248, 136, 0, 0, 34, 7, 33, 212, 248, 216, 48, 13, 10, 51, ++ 248, 18, 48, 206, 178, 203, 24, 155, 178, 1, 59, 70, 234, 3, 38, 5, ++ 240, 3, 5, 3, 244, 64, 115, 29, 67, 111, 234, 66, 99, 111, 234, 83, ++ 67, 160, 248, 64, 53, 160, 248, 32, 101, 160, 248, 44, 85, 160, 248, ++ 64, 53, 212, 248, 216, 48, 51, 248, 18, 80, 1, 50, 73, 25, 6, 42, 137, ++ 178, 218, 209, 32, 70, 152, 33, 90, 136, 33, 240, 168, 217, 212, 248, ++ 216, 48, 32, 70, 154, 33, 154, 136, 33, 240, 161, 217, 212, 248, 216, ++ 48, 32, 70, 218, 136, 27, 136, 156, 33, 67, 234, 2, 34, 146, 178, 33, ++ 240, 150, 217, 212, 248, 216, 48, 32, 70, 90, 137, 27, 137, 158, 33, ++ 67, 234, 2, 34, 146, 178, 33, 240, 139, 217, 32, 70, 189, 232, 112, ++ 64, 30, 240, 92, 159, 112, 181, 146, 33, 4, 70, 133, 111, 6, 104, 32, ++ 240, 209, 219, 163, 111, 64, 0, 104, 131, 90, 139, 0, 42, 69, 208, 26, ++ 106, 114, 177, 218, 127, 98, 177, 0, 37, 163, 111, 32, 70, 89, 139, ++ 27, 106, 73, 25, 90, 91, 2, 53, 33, 240, 107, 217, 236, 45, 244, 209, ++ 47, 224, 1, 34, 218, 119, 214, 248, 68, 54, 0, 43, 46, 208, 0, 37, 29, ++ 224, 3, 235, 133, 3, 218, 136, 178, 245, 122, 127, 11, 211, 161, 111, ++ 73, 106, 145, 177, 162, 245, 122, 114, 146, 178, 7, 42, 13, 216, 27, ++ 137, 33, 248, 18, 48, 9, 224, 210, 42, 7, 216, 161, 111, 32, 70, 73, ++ 139, 1, 235, 66, 1, 26, 137, 33, 240, 68, 217, 1, 53, 173, 178, 214, ++ 248, 68, 54, 154, 136, 170, 66, 220, 216, 26, 120, 18, 177, 162, 111, ++ 91, 136, 19, 129, 32, 70, 189, 232, 112, 64, 30, 240, 109, 156, 112, ++ 189, 3, 104, 112, 181, 142, 33, 211, 248, 116, 84, 4, 70, 32, 240, 124, ++ 219, 149, 248, 28, 33, 70, 0, 182, 178, 0, 42, 59, 208, 213, 248, 32, ++ 49, 6, 241, 80, 1, 148, 54, 1, 43, 137, 178, 182, 178, 28, 208, 2, 211, ++ 2, 43, 56, 209, 34, 224, 149, 248, 232, 32, 1, 32, 16, 250, 2, 242, ++ 149, 248, 88, 49, 146, 178, 255, 43, 3, 208, 16, 250, 3, 243, 26, 67, ++ 146, 178, 32, 70, 33, 240, 6, 217, 149, 248, 232, 48, 1, 34, 154, 64, ++ 32, 70, 49, 70, 146, 178, 26, 224, 32, 70, 181, 248, 42, 33, 33, 240, ++ 249, 216, 32, 70, 49, 70, 181, 248, 44, 33, 16, 224, 149, 248, 232, ++ 48, 1, 34, 154, 64, 32, 70, 146, 178, 33, 240, 236, 216, 32, 70, 49, ++ 70, 0, 34, 4, 224, 76, 54, 79, 246, 254, 113, 32, 70, 49, 64, 189, 232, ++ 112, 64, 33, 240, 223, 152, 112, 189, 208, 248, 148, 16, 16, 181, 8, ++ 49, 4, 70, 31, 240, 71, 218, 3, 73, 32, 70, 189, 232, 16, 64, 31, 240, ++ 41, 154, 0, 191, 244, 44, 4, 0, 208, 248, 240, 48, 112, 181, 1, 51, ++ 1, 43, 4, 70, 208, 248, 136, 80, 192, 248, 240, 48, 65, 216, 3, 104, ++ 147, 248, 42, 56, 91, 177, 2, 33, 0, 34, 32, 240, 213, 216, 32, 70, ++ 64, 242, 35, 17, 0, 34, 189, 232, 112, 64, 33, 240, 165, 152, 4, 33, ++ 33, 240, 58, 218, 213, 248, 32, 49, 1, 51, 36, 208, 213, 248, 40, 33, ++ 81, 28, 32, 208, 18, 240, 1, 2, 1, 208, 4, 35, 20, 224, 32, 70, 1, 33, ++ 32, 240, 185, 216, 66, 242, 109, 6, 2, 224, 10, 32, 226, 243, 177, 245, ++ 213, 248, 40, 49, 219, 7, 1, 212, 1, 62, 246, 209, 213, 248, 40, 49, ++ 216, 7, 3, 212, 5, 35, 196, 248, 68, 49, 112, 189, 213, 248, 32, 49, ++ 1, 51, 5, 209, 35, 104, 152, 104, 189, 232, 112, 64, 231, 247, 158, ++ 187, 112, 189, 112, 181, 4, 70, 13, 70, 22, 70, 255, 247, 172, 255, ++ 32, 70, 41, 70, 255, 247, 6, 252, 32, 70, 30, 240, 47, 222, 35, 104, ++ 26, 104, 146, 248, 156, 32, 1, 42, 4, 209, 211, 248, 52, 1, 41, 70, ++ 248, 247, 228, 249, 32, 70, 255, 247, 168, 252, 32, 104, 41, 70, 50, ++ 70, 237, 247, 228, 248, 32, 70, 41, 70, 189, 232, 112, 64, 30, 240, ++ 78, 157, 45, 233, 240, 65, 144, 248, 9, 113, 4, 70, 13, 70, 22, 70, ++ 152, 70, 23, 185, 57, 70, 30, 240, 230, 222, 212, 248, 148, 48, 214, ++ 241, 1, 1, 88, 106, 164, 248, 188, 80, 56, 191, 0, 33, 8, 240, 180, ++ 249, 148, 248, 172, 48, 131, 185, 148, 248, 10, 49, 51, 177, 212, 248, ++ 148, 48, 65, 70, 88, 106, 42, 70, 8, 240, 194, 254, 212, 248, 148, 48, ++ 41, 70, 88, 106, 8, 240, 101, 252, 86, 224, 180, 248, 70, 48, 68, 242, ++ 192, 50, 147, 66, 62, 208, 26, 216, 68, 242, 174, 50, 147, 66, 57, 208, ++ 10, 216, 68, 242, 163, 50, 147, 66, 52, 208, 68, 242, 171, 50, 147, ++ 66, 48, 208, 68, 242, 160, 50, 36, 224, 68, 242, 183, 50, 147, 66, 41, ++ 208, 68, 242, 186, 50, 147, 66, 37, 208, 68, 242, 177, 50, 25, 224, ++ 68, 242, 223, 50, 147, 66, 30, 208, 10, 216, 68, 242, 214, 50, 147, ++ 66, 25, 208, 68, 242, 217, 50, 147, 66, 21, 208, 68, 242, 211, 50, 9, ++ 224, 68, 242, 233, 50, 147, 66, 14, 208, 68, 242, 236, 50, 147, 66, ++ 10, 208, 68, 242, 227, 50, 147, 66, 6, 208, 212, 248, 148, 48, 88, 106, ++ 8, 240, 36, 252, 133, 66, 5, 208, 212, 248, 148, 48, 41, 70, 88, 106, ++ 9, 240, 79, 252, 212, 248, 148, 48, 65, 70, 88, 106, 42, 70, 8, 240, ++ 105, 254, 32, 70, 49, 70, 0, 34, 32, 240, 108, 216, 47, 185, 32, 70, ++ 2, 33, 189, 232, 240, 65, 30, 240, 105, 158, 189, 232, 240, 129, 56, ++ 181, 67, 124, 4, 70, 139, 66, 13, 70, 6, 208, 57, 177, 32, 240, 172, ++ 216, 56, 185, 79, 240, 255, 48, 56, 189, 0, 32, 56, 189, 79, 240, 255, ++ 48, 56, 189, 0, 32, 132, 248, 118, 0, 101, 116, 56, 189, 45, 233, 240, ++ 65, 138, 176, 16, 159, 152, 70, 0, 35, 3, 47, 4, 70, 13, 70, 17, 158, ++ 8, 147, 9, 147, 12, 217, 4, 34, 8, 168, 65, 70, 220, 247, 208, 253, ++ 7, 47, 5, 217, 9, 168, 8, 241, 4, 1, 4, 34, 220, 247, 200, 253, 93, ++ 45, 8, 153, 112, 208, 39, 216, 38, 45, 0, 240, 168, 128, 16, 216, 23, ++ 45, 8, 216, 20, 45, 128, 240, 81, 129, 12, 45, 74, 208, 14, 45, 64, ++ 240, 64, 129, 74, 224, 32, 45, 124, 208, 33, 45, 64, 240, 58, 129, 106, ++ 224, 82, 45, 0, 240, 224, 128, 6, 216, 39, 45, 0, 240, 129, 128, 68, ++ 45, 64, 240, 47, 129, 156, 224, 90, 45, 59, 208, 92, 45, 72, 208, 84, ++ 45, 64, 240, 39, 129, 210, 224, 112, 45, 0, 240, 47, 129, 20, 216, 102, ++ 45, 0, 240, 241, 128, 6, 216, 99, 45, 0, 240, 203, 128, 100, 45, 64, ++ 240, 24, 129, 228, 224, 105, 45, 0, 240, 238, 128, 106, 45, 0, 240, ++ 254, 128, 104, 45, 64, 240, 14, 129, 227, 224, 121, 45, 0, 240, 4, 129, ++ 6, 216, 113, 45, 0, 240, 247, 128, 120, 45, 64, 240, 3, 129, 254, 224, ++ 124, 45, 192, 240, 255, 128, 125, 45, 64, 242, 8, 129, 140, 45, 64, ++ 240, 249, 128, 31, 224, 224, 111, 233, 243, 73, 240, 64, 224, 212, 248, ++ 128, 0, 131, 73, 2, 224, 212, 248, 128, 0, 130, 73, 222, 243, 89, 247, ++ 32, 177, 0, 33, 10, 70, 227, 247, 42, 253, 49, 224, 79, 240, 255, 51, ++ 51, 96, 224, 224, 148, 248, 28, 49, 177, 224, 0, 49, 24, 191, 1, 33, ++ 132, 248, 28, 17, 172, 224, 9, 154, 18, 155, 154, 66, 0, 243, 214, 128, ++ 32, 70, 51, 70, 30, 240, 23, 218, 197, 224, 7, 47, 64, 242, 206, 128, ++ 0, 41, 192, 242, 206, 128, 2, 35, 0, 147, 224, 111, 1, 34, 9, 155, 233, ++ 243, 177, 240, 148, 224, 3, 47, 64, 242, 192, 128, 0, 41, 192, 242, ++ 192, 128, 2, 35, 0, 147, 0, 34, 224, 111, 19, 70, 233, 243, 163, 240, ++ 48, 96, 133, 224, 11, 47, 64, 242, 177, 128, 0, 41, 192, 242, 177, 128, ++ 9, 155, 0, 43, 172, 191, 111, 240, 22, 5, 111, 240, 1, 5, 179, 224, ++ 7, 47, 64, 242, 163, 128, 0, 41, 192, 242, 163, 128, 9, 154, 0, 42, ++ 192, 242, 159, 128, 0, 37, 0, 149, 224, 111, 43, 70, 233, 243, 143, ++ 240, 48, 96, 161, 224, 35, 104, 152, 104, 243, 243, 117, 245, 128, 70, ++ 224, 111, 233, 243, 53, 240, 16, 179, 224, 111, 233, 243, 77, 240, 7, ++ 70, 24, 185, 224, 111, 1, 33, 233, 243, 99, 241, 51, 104, 224, 111, ++ 0, 147, 115, 104, 8, 54, 1, 147, 0, 35, 2, 150, 3, 147, 65, 104, 212, ++ 248, 136, 32, 163, 104, 222, 243, 12, 240, 0, 40, 20, 191, 79, 240, ++ 255, 53, 0, 37, 111, 185, 224, 111, 57, 70, 233, 243, 74, 241, 8, 224, ++ 224, 111, 233, 243, 2, 240, 0, 40, 20, 191, 111, 240, 29, 5, 111, 240, ++ 22, 5, 35, 104, 65, 70, 152, 104, 243, 243, 71, 245, 102, 224, 212, ++ 248, 92, 49, 38, 224, 212, 248, 96, 49, 35, 224, 49, 70, 16, 34, 4, ++ 168, 220, 247, 193, 252, 5, 157, 12, 53, 40, 70, 229, 247, 86, 252, ++ 4, 70, 0, 40, 75, 208, 49, 70, 42, 70, 220, 247, 181, 252, 35, 136, ++ 32, 70, 27, 11, 1, 43, 4, 208, 229, 247, 75, 252, 79, 240, 255, 53, ++ 69, 224, 229, 247, 70, 252, 61, 224, 35, 104, 147, 248, 0, 54, 1, 224, ++ 79, 244, 176, 99, 51, 96, 0, 37, 57, 224, 180, 248, 30, 49, 249, 231, ++ 141, 178, 1, 45, 46, 216, 3, 35, 164, 248, 30, 81, 32, 70, 0, 147, 2, ++ 33, 32, 34, 29, 177, 19, 70, 31, 240, 142, 222, 235, 231, 43, 70, 31, ++ 240, 138, 222, 35, 224, 32, 70, 30, 240, 50, 219, 91, 231, 75, 28, 2, ++ 43, 26, 216, 32, 70, 73, 178, 32, 240, 206, 217, 5, 70, 22, 224, 196, ++ 248, 56, 17, 215, 231, 212, 248, 56, 49, 211, 231, 111, 240, 29, 5, ++ 13, 224, 111, 240, 13, 5, 10, 224, 111, 240, 1, 5, 7, 224, 111, 240, ++ 26, 5, 4, 224, 111, 240, 22, 5, 1, 224, 111, 240, 28, 5, 40, 70, 10, ++ 176, 189, 232, 240, 129, 0, 191, 173, 86, 136, 0, 181, 86, 136, 0, 56, ++ 181, 3, 104, 4, 70, 24, 105, 46, 240, 128, 218, 0, 40, 53, 209, 148, ++ 248, 8, 81, 0, 45, 49, 209, 16, 33, 10, 70, 43, 70, 224, 111, 230, 247, ++ 114, 250, 224, 111, 230, 247, 127, 250, 212, 248, 148, 48, 41, 70, 88, ++ 106, 8, 240, 29, 250, 212, 248, 148, 48, 41, 70, 88, 106, 7, 240, 107, ++ 255, 32, 70, 41, 70, 31, 240, 213, 219, 180, 248, 116, 48, 51, 177, ++ 224, 111, 79, 240, 255, 49, 42, 70, 43, 70, 232, 243, 241, 246, 0, 37, ++ 224, 111, 41, 70, 132, 248, 10, 81, 232, 243, 54, 245, 212, 248, 148, ++ 48, 41, 70, 88, 106, 189, 232, 56, 64, 7, 240, 102, 191, 56, 189, 45, ++ 233, 240, 71, 154, 70, 131, 111, 4, 70, 95, 139, 13, 70, 22, 70, 208, ++ 248, 136, 144, 15, 179, 7, 241, 8, 1, 32, 240, 54, 216, 128, 70, 216, ++ 177, 35, 109, 219, 7, 17, 213, 99, 109, 24, 6, 14, 212, 227, 111, 154, ++ 105, 145, 0, 2, 213, 218, 105, 210, 7, 4, 213, 219, 105, 216, 7, 1, ++ 212, 89, 7, 2, 213, 227, 110, 154, 0, 70, 212, 32, 70, 7, 241, 144, ++ 1, 32, 240, 26, 216, 4, 40, 63, 216, 163, 111, 154, 127, 1, 50, 154, ++ 119, 163, 111, 154, 127, 5, 42, 2, 216, 179, 248, 28, 128, 3, 224, 5, ++ 34, 154, 119, 79, 240, 0, 8, 163, 111, 32, 70, 163, 248, 28, 128, 7, ++ 241, 248, 1, 165, 248, 0, 128, 31, 240, 255, 223, 217, 248, 32, 49, ++ 170, 248, 0, 0, 155, 7, 26, 213, 163, 111, 185, 248, 194, 6, 154, 125, ++ 128, 178, 79, 246, 255, 113, 42, 177, 136, 66, 16, 209, 0, 34, 154, ++ 117, 163, 111, 1, 224, 136, 66, 1, 209, 218, 117, 8, 224, 218, 125, ++ 1, 50, 210, 178, 4, 42, 218, 117, 2, 217, 163, 111, 1, 34, 154, 117, ++ 163, 111, 0, 32, 155, 125, 51, 112, 189, 232, 240, 135, 163, 111, 0, ++ 34, 154, 119, 202, 231, 240, 181, 8, 41, 135, 176, 4, 70, 13, 70, 0, ++ 243, 238, 128, 25, 209, 3, 109, 221, 7, 17, 213, 67, 109, 25, 6, 14, ++ 212, 195, 111, 154, 105, 146, 0, 2, 213, 218, 105, 213, 7, 4, 213, 219, ++ 105, 216, 7, 1, 212, 89, 7, 2, 213, 227, 110, 154, 0, 6, 212, 101, 109, ++ 21, 240, 128, 5, 2, 209, 10, 224, 9, 185, 8, 224, 1, 37, 163, 111, 91, ++ 104, 2, 43, 3, 221, 35, 111, 155, 0, 64, 241, 203, 128, 0, 33, 3, 168, ++ 10, 34, 221, 243, 250, 246, 163, 111, 0, 33, 25, 129, 148, 248, 172, ++ 112, 47, 177, 212, 248, 136, 32, 210, 248, 32, 113, 7, 240, 1, 7, 189, ++ 248, 12, 32, 0, 45, 79, 208, 66, 240, 16, 2, 173, 248, 12, 32, 90, 104, ++ 2, 42, 34, 109, 18, 209, 18, 244, 128, 79, 189, 248, 14, 32, 8, 208, ++ 66, 244, 128, 114, 173, 248, 14, 32, 48, 34, 218, 96, 32, 34, 26, 97, ++ 61, 224, 34, 244, 128, 114, 173, 248, 14, 32, 56, 224, 5, 45, 1, 209, ++ 8, 33, 8, 224, 3, 45, 1, 209, 136, 33, 4, 224, 4, 45, 12, 191, 79, 244, ++ 132, 113, 20, 33, 214, 7, 25, 129, 21, 213, 98, 109, 16, 6, 18, 212, ++ 226, 111, 145, 105, 137, 0, 2, 213, 209, 105, 206, 7, 4, 213, 210, 105, ++ 208, 7, 1, 212, 81, 7, 6, 213, 226, 110, 146, 0, 3, 213, 26, 137, 66, ++ 240, 64, 2, 12, 224, 90, 104, 4, 42, 6, 209, 189, 248, 16, 48, 67, 244, ++ 0, 83, 173, 248, 16, 48, 8, 224, 26, 137, 66, 240, 1, 2, 26, 129, 3, ++ 224, 34, 240, 16, 2, 173, 248, 12, 32, 163, 111, 29, 96, 148, 248, 172, ++ 48, 27, 177, 23, 177, 32, 70, 255, 247, 21, 252, 2, 38, 189, 248, 12, ++ 48, 32, 70, 0, 33, 16, 34, 0, 150, 31, 240, 4, 221, 189, 248, 14, 48, ++ 32, 70, 1, 33, 79, 244, 128, 114, 0, 150, 31, 240, 251, 220, 189, 248, ++ 16, 48, 32, 70, 49, 70, 79, 244, 0, 82, 0, 150, 31, 240, 242, 220, 32, ++ 70, 29, 240, 255, 223, 148, 248, 172, 48, 27, 177, 23, 177, 32, 70, ++ 255, 247, 1, 249, 212, 248, 148, 48, 41, 70, 88, 106, 9, 240, 237, 251, ++ 32, 109, 16, 240, 1, 0, 45, 208, 101, 109, 21, 240, 128, 5, 40, 209, ++ 227, 111, 216, 105, 16, 240, 4, 0, 36, 208, 224, 110, 16, 240, 0, 80, ++ 32, 208, 35, 104, 79, 244, 112, 2, 27, 104, 64, 246, 116, 81, 211, 248, ++ 216, 0, 19, 70, 232, 243, 238, 244, 35, 104, 64, 246, 100, 81, 26, 104, ++ 163, 111, 210, 248, 216, 0, 27, 104, 79, 244, 112, 2, 27, 5, 232, 243, ++ 225, 244, 40, 70, 6, 224, 111, 240, 1, 0, 3, 224, 111, 240, 2, 0, 0, ++ 224, 0, 32, 7, 176, 240, 189, 45, 233, 240, 67, 135, 176, 4, 70, 208, ++ 248, 136, 80, 6, 104, 0, 33, 12, 34, 2, 168, 221, 243, 34, 246, 0, 39, ++ 79, 240, 255, 49, 111, 74, 13, 241, 24, 9, 32, 70, 73, 248, 4, 125, ++ 31, 240, 135, 220, 32, 70, 30, 240, 150, 216, 32, 70, 32, 240, 219, ++ 219, 79, 244, 0, 56, 32, 70, 255, 247, 89, 248, 205, 248, 0, 128, 4, ++ 35, 36, 33, 48, 105, 74, 70, 31, 240, 102, 217, 58, 70, 57, 70, 224, ++ 111, 232, 243, 147, 243, 96, 73, 32, 70, 30, 240, 169, 221, 32, 70, ++ 255, 247, 118, 250, 2, 169, 32, 70, 30, 240, 44, 219, 128, 33, 8, 34, ++ 32, 70, 32, 240, 69, 220, 10, 34, 92, 33, 32, 70, 32, 240, 64, 220, ++ 32, 70, 212, 248, 32, 17, 30, 240, 197, 217, 84, 74, 32, 70, 84, 73, ++ 31, 240, 80, 220, 79, 240, 0, 67, 197, 248, 136, 49, 79, 240, 0, 115, ++ 197, 248, 140, 49, 79, 244, 128, 67, 197, 248, 40, 49, 79, 244, 128, ++ 51, 107, 98, 1, 33, 32, 70, 31, 240, 51, 220, 224, 111, 232, 243, 2, ++ 243, 164, 248, 18, 1, 165, 248, 168, 6, 22, 33, 32, 70, 180, 248, 72, ++ 32, 32, 240, 22, 220, 192, 33, 32, 70, 180, 248, 108, 32, 32, 240, 16, ++ 220, 194, 33, 32, 70, 180, 248, 110, 32, 32, 240, 10, 220, 24, 33, 32, ++ 70, 2, 35, 4, 241, 164, 2, 205, 248, 0, 128, 31, 240, 89, 217, 2, 35, ++ 32, 70, 28, 33, 4, 241, 166, 2, 205, 248, 0, 128, 31, 240, 80, 217, ++ 150, 248, 64, 54, 19, 177, 134, 248, 64, 118, 7, 224, 205, 248, 0, 128, ++ 48, 105, 36, 33, 74, 70, 4, 35, 31, 240, 66, 217, 32, 70, 68, 33, 180, ++ 248, 168, 32, 32, 240, 228, 219, 32, 70, 70, 33, 180, 248, 170, 32, ++ 32, 240, 222, 219, 181, 248, 136, 54, 27, 5, 27, 13, 165, 248, 136, ++ 54, 1, 35, 165, 248, 156, 54, 0, 37, 181, 99, 99, 25, 88, 105, 16, 177, ++ 32, 75, 91, 104, 152, 71, 4, 53, 24, 45, 246, 209, 29, 77, 96, 105, ++ 171, 109, 152, 71, 107, 111, 96, 105, 152, 71, 0, 33, 32, 70, 32, 240, ++ 237, 216, 32, 70, 255, 247, 54, 250, 163, 111, 32, 70, 89, 139, 79, ++ 244, 128, 114, 204, 49, 32, 240, 180, 219, 99, 124, 3, 34, 0, 146, 16, ++ 34, 0, 43, 20, 191, 19, 70, 0, 35, 32, 70, 4, 33, 31, 240, 210, 219, ++ 32, 70, 174, 33, 31, 240, 246, 221, 79, 244, 216, 99, 64, 0, 196, 248, ++ 36, 1, 196, 248, 40, 49, 48, 70, 30, 240, 246, 219, 7, 176, 189, 232, ++ 240, 131, 0, 191, 4, 4, 0, 4, 44, 28, 4, 0, 0, 0, 2, 64, 0, 0, 6, 64, ++ 208, 134, 135, 0, 115, 181, 27, 74, 4, 70, 81, 104, 16, 104, 107, 70, ++ 3, 195, 0, 37, 29, 248, 5, 16, 32, 70, 30, 240, 221, 216, 0, 241, 18, ++ 6, 49, 70, 32, 70, 31, 240, 203, 221, 1, 53, 2, 70, 49, 70, 32, 70, ++ 32, 240, 115, 219, 8, 45, 236, 209, 32, 70, 30, 240, 80, 221, 168, 177, ++ 163, 111, 34, 33, 32, 70, 29, 126, 31, 240, 185, 221, 79, 246, 63, 67, ++ 3, 64, 1, 45, 20, 191, 128, 37, 64, 37, 32, 70, 34, 33, 67, 234, 5, ++ 2, 2, 176, 189, 232, 112, 64, 32, 240, 87, 155, 2, 176, 112, 189, 0, ++ 191, 90, 21, 4, 0, 45, 233, 248, 67, 144, 248, 9, 113, 4, 70, 14, 70, ++ 145, 70, 5, 104, 23, 185, 57, 70, 30, 240, 222, 217, 168, 104, 243, ++ 243, 223, 241, 6, 244, 64, 65, 161, 245, 64, 78, 222, 241, 0, 1, 65, ++ 235, 14, 1, 128, 70, 32, 70, 32, 240, 149, 220, 212, 248, 148, 48, 49, ++ 70, 88, 106, 7, 240, 102, 255, 212, 248, 148, 48, 164, 248, 188, 96, ++ 88, 106, 7, 240, 166, 252, 32, 70, 255, 247, 163, 254, 32, 70, 255, ++ 247, 242, 249, 1, 33, 196, 248, 240, 16, 185, 241, 0, 15, 3, 208, 32, ++ 70, 10, 70, 31, 240, 174, 219, 35, 109, 218, 7, 21, 213, 212, 248, 84, ++ 17, 40, 70, 17, 240, 1, 1, 24, 191, 1, 33, 79, 244, 0, 82, 1, 240, 27, ++ 248, 212, 248, 84, 17, 40, 70, 17, 240, 2, 1, 24, 191, 1, 33, 79, 244, ++ 0, 66, 1, 240, 16, 248, 35, 109, 219, 7, 7, 213, 148, 248, 88, 17, 40, ++ 70, 1, 177, 1, 33, 64, 34, 1, 240, 5, 248, 32, 70, 0, 33, 32, 240, 32, ++ 216, 32, 70, 49, 70, 0, 34, 29, 240, 161, 221, 168, 104, 65, 70, 243, ++ 243, 141, 241, 212, 248, 244, 48, 67, 240, 4, 3, 196, 248, 244, 48, ++ 31, 185, 32, 70, 2, 33, 30, 240, 118, 217, 0, 35, 132, 248, 55, 49, ++ 189, 232, 248, 131, 55, 181, 177, 245, 122, 127, 4, 70, 1, 145, 21, ++ 70, 9, 219, 131, 111, 91, 106, 243, 177, 161, 245, 122, 113, 6, 41, ++ 29, 220, 35, 248, 17, 32, 21, 224, 144, 248, 172, 48, 67, 185, 130, ++ 111, 18, 106, 138, 177, 117, 41, 18, 220, 34, 248, 17, 80, 24, 70, 19, ++ 224, 1, 169, 254, 247, 59, 254, 104, 177, 32, 70, 189, 248, 4, 16, 170, ++ 178, 32, 240, 178, 218, 0, 32, 7, 224, 79, 240, 255, 48, 4, 224, 111, ++ 240, 20, 0, 1, 224, 111, 240, 1, 0, 62, 189, 19, 181, 177, 245, 122, ++ 127, 4, 70, 1, 145, 6, 219, 131, 111, 91, 106, 195, 177, 161, 245, 122, ++ 113, 6, 41, 6, 224, 144, 248, 172, 48, 59, 185, 131, 111, 27, 106, 139, ++ 177, 117, 41, 15, 220, 51, 248, 17, 0, 14, 224, 1, 169, 254, 247, 14, ++ 254, 64, 177, 32, 70, 189, 248, 4, 16, 31, 240, 216, 220, 4, 224, 79, ++ 240, 255, 48, 1, 224, 64, 246, 173, 48, 28, 189, 56, 181, 4, 70, 144, ++ 248, 172, 0, 0, 40, 36, 208, 35, 104, 24, 105, 45, 240, 201, 222, 5, ++ 70, 16, 177, 0, 35, 227, 101, 13, 224, 35, 104, 152, 104, 243, 243, ++ 8, 241, 32, 70, 41, 70, 30, 240, 0, 217, 148, 248, 8, 49, 19, 185, 32, ++ 70, 29, 240, 52, 222, 32, 70, 0, 33, 254, 247, 48, 254, 32, 70, 30, ++ 240, 65, 221, 212, 248, 148, 48, 88, 106, 189, 232, 56, 64, 7, 240, ++ 71, 188, 56, 189, 0, 0, 45, 233, 240, 65, 196, 111, 23, 70, 8, 34, 6, ++ 70, 13, 70, 152, 70, 64, 246, 116, 81, 19, 70, 32, 70, 232, 243, 150, ++ 242, 32, 70, 64, 246, 100, 81, 8, 34, 37, 177, 21, 244, 64, 79, 1, 209, ++ 19, 70, 0, 224, 0, 35, 232, 243, 137, 242, 51, 109, 216, 7, 93, 213, ++ 115, 109, 25, 6, 90, 212, 243, 111, 154, 105, 146, 0, 2, 213, 218, 105, ++ 208, 7, 4, 213, 219, 105, 217, 7, 1, 212, 90, 7, 78, 213, 243, 110, ++ 155, 0, 75, 213, 0, 47, 73, 209, 184, 241, 0, 15, 70, 209, 0, 45, 55, ++ 208, 21, 244, 64, 66, 99, 105, 38, 209, 34, 43, 32, 73, 204, 191, 12, ++ 35, 0, 35, 234, 178, 216, 191, 15, 33, 32, 70, 154, 64, 5, 244, 96, ++ 85, 1, 35, 232, 243, 182, 241, 181, 245, 192, 95, 99, 105, 9, 209, 24, ++ 73, 34, 43, 32, 70, 216, 191, 112, 33, 204, 191, 79, 244, 32, 98, 80, ++ 34, 30, 224, 19, 73, 34, 43, 32, 70, 216, 191, 112, 33, 204, 191, 79, ++ 244, 0, 114, 16, 34, 20, 224, 178, 245, 64, 79, 9, 209, 34, 43, 2, 220, ++ 15, 33, 10, 70, 2, 224, 9, 73, 79, 244, 112, 66, 32, 70, 7, 224, 97, ++ 105, 6, 75, 32, 70, 34, 41, 204, 191, 25, 70, 15, 33, 0, 34, 1, 35, ++ 189, 232, 240, 65, 232, 243, 132, 177, 189, 232, 240, 129, 0, 240, 85, ++ 85, 0, 14, 85, 85, 56, 181, 3, 109, 4, 70, 218, 7, 116, 213, 67, 109, ++ 27, 6, 113, 212, 195, 111, 154, 105, 144, 0, 2, 213, 218, 105, 209, ++ 7, 4, 213, 219, 105, 218, 7, 1, 212, 88, 7, 101, 213, 227, 110, 153, ++ 0, 98, 213, 212, 248, 136, 48, 79, 244, 150, 117, 179, 248, 180, 38, ++ 146, 178, 66, 240, 3, 2, 163, 248, 180, 38, 212, 248, 136, 32, 178, ++ 248, 184, 54, 35, 240, 192, 3, 27, 4, 27, 12, 162, 248, 184, 54, 35, ++ 109, 218, 7, 25, 213, 99, 109, 27, 6, 22, 212, 227, 111, 219, 105, 88, ++ 7, 18, 213, 227, 110, 153, 0, 15, 213, 212, 248, 136, 48, 1, 33, 163, ++ 248, 240, 22, 212, 248, 136, 48, 179, 248, 242, 38, 146, 178, 19, 10, ++ 3, 240, 15, 3, 2, 240, 63, 2, 19, 224, 212, 248, 136, 48, 0, 34, 163, ++ 248, 240, 38, 212, 248, 136, 48, 1, 33, 179, 248, 242, 38, 163, 248, ++ 240, 22, 212, 248, 136, 48, 194, 243, 5, 18, 179, 248, 242, 54, 195, ++ 243, 3, 19, 4, 42, 5, 209, 35, 177, 100, 32, 225, 243, 133, 246, 1, ++ 61, 198, 209, 79, 244, 251, 117, 4, 224, 1, 61, 8, 208, 10, 32, 225, ++ 243, 123, 246, 212, 248, 136, 48, 179, 248, 182, 38, 210, 7, 244, 212, ++ 179, 248, 184, 38, 146, 178, 66, 240, 192, 2, 163, 248, 184, 38, 56, ++ 189, 48, 181, 135, 176, 4, 70, 13, 70, 3, 168, 0, 33, 10, 34, 221, 243, ++ 246, 242, 148, 248, 172, 48, 51, 177, 212, 248, 136, 32, 210, 248, 32, ++ 33, 2, 240, 1, 2, 0, 224, 26, 70, 189, 248, 12, 16, 1, 45, 12, 191, ++ 65, 240, 2, 1, 33, 240, 2, 1, 173, 248, 12, 16, 155, 177, 146, 177, ++ 32, 70, 255, 247, 100, 248, 2, 34, 32, 70, 189, 248, 12, 48, 0, 33, ++ 0, 146, 31, 240, 84, 217, 148, 248, 172, 0, 48, 177, 32, 70, 254, 247, ++ 103, 253, 0, 32, 1, 224, 79, 240, 255, 48, 7, 176, 48, 189, 208, 248, ++ 40, 49, 112, 181, 6, 70, 88, 104, 226, 243, 205, 240, 4, 70, 0, 40, ++ 92, 208, 192, 32, 226, 243, 199, 240, 224, 100, 0, 40, 86, 208, 80, ++ 32, 226, 243, 193, 240, 196, 248, 248, 0, 0, 40, 79, 208, 244, 32, 226, ++ 243, 186, 240, 196, 248, 252, 0, 0, 40, 72, 208, 4, 32, 226, 243, 179, ++ 240, 196, 248, 108, 3, 0, 40, 65, 208, 84, 32, 226, 243, 172, 240, 5, ++ 70, 196, 248, 0, 1, 208, 179, 32, 32, 226, 243, 165, 240, 40, 96, 168, ++ 179, 212, 248, 0, 81, 8, 35, 235, 129, 107, 135, 16, 32, 226, 243, 155, ++ 240, 232, 98, 88, 179, 79, 244, 146, 112, 226, 243, 149, 240, 196, 248, ++ 244, 0, 32, 179, 79, 244, 146, 112, 226, 243, 142, 240, 196, 248, 240, ++ 0, 232, 177, 120, 32, 226, 243, 136, 240, 196, 248, 4, 1, 184, 177, ++ 44, 32, 226, 243, 130, 240, 196, 248, 68, 3, 136, 177, 32, 32, 226, ++ 243, 124, 240, 196, 248, 88, 3, 88, 177, 32, 32, 226, 243, 118, 240, ++ 196, 248, 92, 3, 40, 177, 20, 32, 226, 243, 112, 240, 196, 248, 112, ++ 3, 32, 185, 33, 70, 48, 70, 32, 240, 171, 221, 0, 36, 32, 70, 112, 189, ++ 139, 121, 43, 177, 144, 248, 114, 34, 58, 185, 144, 248, 115, 34, 34, ++ 185, 1, 34, 74, 113, 35, 177, 33, 240, 109, 157, 79, 240, 255, 48, 112, ++ 71, 24, 70, 112, 71, 16, 181, 0, 50, 11, 124, 24, 191, 1, 34, 154, 66, ++ 12, 70, 10, 116, 3, 208, 3, 33, 226, 104, 233, 247, 98, 254, 163, 121, ++ 123, 185, 35, 124, 59, 185, 212, 248, 204, 48, 19, 240, 24, 15, 2, 209, ++ 67, 240, 96, 3, 3, 224, 212, 248, 204, 48, 35, 240, 96, 3, 196, 248, ++ 204, 48, 0, 32, 16, 189, 7, 41, 4, 217, 111, 240, 28, 3, 19, 96, 0, ++ 32, 112, 71, 208, 248, 104, 50, 83, 248, 33, 0, 0, 40, 12, 191, 111, ++ 240, 29, 3, 0, 35, 19, 96, 112, 71, 208, 248, 108, 2, 112, 71, 9, 185, ++ 255, 247, 250, 191, 11, 121, 1, 43, 2, 208, 2, 43, 5, 209, 1, 224, 8, ++ 105, 112, 71, 11, 105, 24, 105, 112, 71, 0, 32, 112, 71, 112, 181, 4, ++ 70, 8, 70, 13, 70, 226, 247, 184, 254, 0, 187, 43, 120, 19, 240, 1, ++ 3, 29, 209, 212, 248, 104, 34, 208, 88, 152, 177, 105, 136, 176, 248, ++ 196, 64, 176, 248, 194, 96, 76, 64, 41, 136, 113, 64, 12, 67, 176, 248, ++ 198, 96, 169, 136, 113, 64, 33, 67, 137, 178, 25, 185, 208, 248, 204, ++ 16, 9, 6, 5, 213, 4, 51, 32, 43, 230, 209, 0, 32, 112, 189, 0, 32, 112, ++ 189, 112, 181, 4, 70, 8, 70, 13, 70, 226, 247, 142, 254, 224, 185, 43, ++ 120, 19, 240, 1, 3, 25, 209, 212, 248, 104, 34, 208, 88, 120, 177, 105, ++ 136, 176, 248, 190, 64, 176, 248, 188, 96, 76, 64, 41, 136, 113, 64, ++ 12, 67, 176, 248, 192, 96, 169, 136, 113, 64, 33, 67, 137, 178, 41, ++ 177, 4, 51, 32, 43, 234, 209, 0, 32, 112, 189, 0, 32, 112, 189, 248, ++ 181, 4, 70, 8, 70, 13, 70, 226, 247, 104, 254, 232, 185, 43, 120, 19, ++ 240, 1, 3, 26, 209, 212, 248, 104, 18, 200, 88, 128, 177, 130, 121, ++ 114, 185, 208, 248, 240, 32, 110, 136, 84, 136, 47, 136, 102, 64, 20, ++ 136, 146, 136, 124, 64, 52, 67, 174, 136, 114, 64, 34, 67, 146, 178, ++ 42, 177, 4, 51, 32, 43, 233, 209, 0, 32, 248, 189, 0, 32, 248, 189, ++ 45, 233, 240, 65, 128, 70, 15, 70, 22, 70, 0, 37, 216, 248, 104, 50, ++ 92, 89, 92, 177, 0, 46, 9, 221, 35, 126, 158, 66, 6, 209, 56, 70, 4, ++ 241, 25, 1, 50, 70, 219, 247, 227, 253, 24, 177, 4, 53, 32, 45, 236, ++ 209, 0, 36, 32, 70, 189, 232, 240, 129, 16, 181, 208, 248, 104, 34, ++ 0, 35, 208, 88, 24, 177, 176, 248, 26, 65, 140, 66, 3, 208, 4, 51, 32, ++ 43, 246, 209, 0, 32, 16, 189, 209, 248, 204, 48, 112, 181, 67, 240, ++ 96, 3, 26, 3, 193, 248, 204, 48, 68, 191, 35, 240, 32, 3, 193, 248, ++ 204, 48, 3, 104, 5, 70, 219, 105, 12, 70, 27, 105, 209, 248, 68, 99, ++ 193, 248, 128, 48, 1, 35, 139, 113, 11, 116, 0, 35, 129, 248, 80, 51, ++ 209, 248, 204, 48, 91, 0, 4, 212, 29, 240, 159, 217, 96, 97, 0, 40, ++ 38, 208, 46, 177, 24, 32, 225, 243, 66, 247, 176, 97, 0, 40, 34, 208, ++ 40, 70, 33, 70, 32, 240, 205, 222, 212, 248, 32, 51, 107, 185, 212, ++ 248, 204, 48, 152, 0, 9, 213, 200, 32, 225, 243, 49, 247, 196, 248, ++ 32, 3, 160, 177, 16, 33, 128, 34, 222, 243, 50, 241, 32, 70, 2, 33, ++ 1, 34, 33, 240, 45, 218, 40, 70, 33, 70, 189, 232, 112, 64, 32, 240, ++ 191, 155, 79, 240, 255, 48, 112, 189, 111, 240, 26, 0, 112, 189, 111, ++ 240, 26, 0, 112, 189, 45, 233, 240, 71, 209, 248, 252, 96, 0, 36, 209, ++ 248, 248, 144, 128, 70, 209, 248, 4, 113, 13, 70, 140, 113, 244, 34, ++ 33, 70, 48, 70, 221, 243, 249, 240, 33, 70, 80, 34, 72, 70, 221, 243, ++ 244, 240, 33, 70, 120, 34, 56, 70, 221, 243, 239, 240, 8, 35, 51, 96, ++ 70, 35, 51, 99, 120, 35, 166, 248, 90, 48, 3, 35, 134, 248, 140, 48, ++ 7, 35, 134, 248, 191, 48, 6, 35, 134, 248, 136, 64, 134, 248, 183, 48, ++ 216, 248, 0, 48, 79, 240, 10, 10, 219, 105, 116, 98, 179, 248, 216, ++ 48, 198, 248, 44, 160, 166, 248, 152, 48, 191, 35, 134, 248, 209, 48, ++ 216, 248, 8, 0, 58, 73, 42, 70, 35, 70, 242, 243, 177, 245, 201, 248, ++ 0, 0, 0, 40, 99, 208, 79, 244, 122, 115, 137, 248, 28, 64, 201, 248, ++ 20, 160, 169, 248, 34, 160, 201, 248, 24, 48, 228, 32, 225, 243, 194, ++ 246, 197, 248, 8, 1, 0, 40, 78, 208, 128, 248, 224, 64, 216, 248, 8, ++ 0, 44, 73, 42, 70, 35, 70, 242, 243, 147, 245, 184, 97, 0, 40, 70, 208, ++ 216, 248, 8, 0, 40, 73, 42, 70, 35, 70, 242, 243, 137, 245, 56, 97, ++ 0, 40, 60, 208, 216, 248, 8, 0, 36, 73, 42, 70, 35, 70, 242, 243, 127, ++ 245, 198, 248, 196, 0, 0, 40, 49, 208, 216, 248, 208, 5, 44, 240, 209, ++ 223, 248, 99, 0, 40, 42, 208, 216, 248, 208, 5, 44, 240, 202, 223, 184, ++ 99, 0, 40, 39, 208, 200, 35, 187, 98, 251, 98, 1, 35, 135, 248, 111, ++ 48, 64, 70, 41, 70, 167, 248, 114, 64, 135, 248, 110, 64, 135, 248, ++ 112, 64, 32, 240, 17, 222, 213, 248, 68, 51, 15, 34, 131, 248, 36, 32, ++ 40, 70, 2, 33, 34, 70, 33, 240, 125, 217, 64, 70, 41, 70, 189, 232, ++ 240, 71, 32, 240, 15, 155, 111, 240, 26, 0, 189, 232, 240, 135, 111, ++ 240, 21, 0, 189, 232, 240, 135, 111, 240, 21, 0, 189, 232, 240, 135, ++ 0, 191, 45, 67, 2, 0, 145, 66, 130, 0, 17, 200, 130, 0, 165, 33, 132, ++ 0, 139, 121, 11, 177, 255, 247, 235, 190, 255, 247, 62, 191, 45, 233, ++ 240, 67, 4, 104, 137, 176, 0, 35, 32, 70, 21, 153, 221, 248, 68, 144, ++ 23, 70, 221, 248, 64, 128, 18, 157, 6, 147, 7, 147, 255, 247, 37, 254, ++ 185, 241, 3, 15, 6, 70, 13, 217, 4, 34, 6, 168, 65, 70, 219, 247, 174, ++ 252, 185, 241, 7, 15, 5, 217, 7, 168, 8, 241, 4, 1, 4, 34, 219, 247, ++ 165, 252, 23, 177, 3, 47, 78, 209, 62, 224, 19, 155, 15, 43, 77, 217, ++ 16, 34, 65, 70, 2, 168, 219, 247, 153, 252, 32, 70, 33, 240, 78, 216, ++ 6, 70, 1, 48, 69, 208, 3, 155, 32, 70, 3, 240, 1, 2, 153, 7, 84, 191, ++ 59, 70, 4, 171, 0, 146, 49, 70, 0, 34, 32, 240, 216, 221, 7, 70, 0, ++ 40, 57, 208, 32, 70, 57, 70, 255, 247, 177, 255, 128, 70, 16, 177, 32, ++ 70, 57, 70, 34, 224, 117, 179, 46, 118, 251, 104, 58, 104, 153, 104, ++ 144, 104, 242, 243, 210, 244, 15, 34, 1, 70, 5, 241, 8, 0, 221, 243, ++ 204, 240, 133, 248, 23, 128, 168, 28, 7, 241, 194, 1, 6, 34, 219, 247, ++ 100, 252, 64, 70, 24, 224, 150, 249, 68, 0, 168, 177, 115, 121, 27, ++ 177, 32, 70, 49, 70, 32, 240, 71, 222, 32, 70, 49, 70, 32, 240, 169, ++ 223, 0, 32, 9, 224, 111, 240, 22, 0, 6, 224, 111, 240, 13, 0, 3, 224, ++ 111, 240, 21, 0, 0, 224, 40, 70, 9, 176, 189, 232, 240, 131, 45, 233, ++ 248, 79, 21, 70, 0, 34, 42, 96, 12, 70, 155, 70, 26, 96, 128, 70, 79, ++ 240, 64, 10, 145, 70, 23, 70, 216, 248, 32, 97, 0, 46, 54, 208, 22, ++ 240, 64, 127, 243, 178, 31, 208, 163, 241, 87, 2, 1, 42, 3, 217, 163, ++ 241, 99, 1, 3, 41, 12, 216, 166, 50, 4, 235, 130, 2, 81, 104, 216, 248, ++ 36, 49, 203, 24, 187, 66, 83, 96, 24, 217, 46, 96, 31, 70, 21, 224, ++ 23, 43, 27, 216, 108, 51, 4, 235, 131, 3, 89, 104, 216, 248, 36, 33, ++ 138, 24, 90, 96, 6, 224, 84, 248, 35, 16, 216, 248, 36, 33, 138, 24, ++ 68, 248, 35, 32, 186, 66, 132, 191, 46, 96, 23, 70, 48, 70, 17, 240, ++ 205, 254, 72, 69, 132, 191, 203, 248, 0, 96, 129, 70, 186, 241, 1, 10, ++ 8, 241, 8, 8, 191, 209, 189, 232, 248, 143, 240, 181, 144, 248, 155, ++ 51, 35, 179, 208, 248, 156, 67, 12, 177, 32, 104, 200, 185, 19, 241, ++ 255, 48, 24, 191, 1, 32, 240, 189, 37, 29, 175, 90, 78, 136, 173, 24, ++ 126, 64, 111, 136, 141, 136, 6, 50, 125, 64, 46, 67, 6, 37, 5, 251, ++ 3, 69, 15, 136, 173, 136, 125, 64, 53, 67, 173, 178, 77, 177, 1, 51, ++ 1, 224, 2, 34, 0, 35, 131, 66, 230, 219, 0, 32, 240, 189, 24, 70, 240, ++ 189, 1, 32, 240, 189, 0, 35, 131, 135, 0, 32, 112, 71, 112, 71, 0, 32, ++ 112, 71, 0, 32, 112, 71, 0, 32, 112, 71, 0, 40, 12, 191, 79, 240, 255, ++ 48, 0, 32, 112, 71, 56, 181, 4, 108, 13, 70, 8, 89, 24, 177, 228, 247, ++ 79, 251, 0, 35, 43, 81, 56, 189, 112, 181, 145, 248, 111, 32, 3, 70, ++ 140, 143, 146, 177, 208, 248, 108, 82, 213, 248, 0, 97, 85, 178, 54, ++ 105, 174, 66, 10, 218, 145, 248, 112, 80, 61, 185, 1, 35, 128, 34, 129, ++ 248, 112, 48, 4, 241, 206, 1, 19, 70, 17, 224, 211, 248, 108, 2, 82, ++ 178, 208, 248, 0, 1, 0, 105, 144, 66, 13, 219, 145, 248, 112, 32, 82, ++ 177, 0, 34, 129, 248, 112, 32, 24, 70, 4, 241, 206, 1, 128, 35, 189, ++ 232, 112, 64, 9, 240, 144, 157, 112, 189, 45, 233, 240, 65, 4, 70, 22, ++ 70, 31, 70, 13, 70, 0, 41, 0, 240, 131, 128, 248, 247, 119, 248, 212, ++ 248, 164, 49, 128, 70, 147, 248, 102, 16, 147, 248, 108, 32, 0, 41, ++ 110, 209, 0, 42, 108, 209, 153, 136, 66, 242, 14, 114, 1, 57, 137, 178, ++ 145, 66, 45, 216, 32, 105, 64, 242, 234, 49, 255, 247, 140, 250, 144, ++ 177, 32, 105, 79, 244, 123, 113, 255, 247, 134, 250, 212, 248, 164, ++ 49, 154, 136, 65, 246, 75, 83, 154, 66, 4, 217, 32, 105, 64, 242, 237, ++ 49, 255, 247, 122, 250, 197, 178, 0, 224, 5, 70, 32, 105, 64, 242, 235, ++ 49, 255, 247, 114, 250, 1, 35, 48, 177, 59, 112, 212, 248, 164, 49, ++ 0, 34, 131, 248, 110, 32, 28, 224, 56, 112, 212, 248, 164, 33, 130, ++ 248, 110, 48, 22, 224, 91, 141, 19, 240, 2, 3, 6, 208, 32, 105, 64, ++ 242, 238, 49, 255, 247, 90, 250, 197, 178, 11, 224, 51, 112, 59, 112, ++ 212, 248, 164, 33, 1, 35, 130, 248, 108, 48, 212, 248, 164, 33, 130, ++ 248, 110, 48, 0, 224, 61, 185, 0, 35, 51, 112, 212, 248, 164, 49, 1, ++ 34, 131, 248, 108, 32, 26, 224, 212, 248, 164, 49, 147, 248, 109, 32, ++ 2, 42, 7, 217, 1, 34, 131, 248, 102, 32, 212, 248, 164, 49, 131, 248, ++ 103, 80, 1, 224, 0, 35, 51, 112, 212, 248, 164, 49, 147, 248, 109, 32, ++ 1, 50, 131, 248, 109, 32, 2, 224, 10, 177, 0, 35, 51, 112, 212, 248, ++ 164, 49, 195, 248, 104, 128, 189, 232, 240, 129, 208, 248, 164, 49, ++ 147, 248, 102, 32, 42, 185, 219, 110, 19, 240, 255, 31, 13, 209, 189, ++ 232, 240, 129, 2, 34, 19, 70, 13, 240, 100, 218, 212, 248, 164, 49, ++ 131, 248, 102, 80, 212, 248, 164, 49, 131, 248, 103, 80, 212, 248, 164, ++ 33, 0, 35, 130, 248, 108, 48, 212, 248, 164, 33, 130, 248, 110, 48, ++ 212, 248, 164, 33, 130, 248, 109, 48, 189, 232, 240, 129, 112, 181, ++ 4, 70, 0, 105, 29, 240, 82, 222, 5, 70, 32, 105, 212, 248, 164, 97, ++ 29, 240, 42, 222, 48, 102, 40, 70, 112, 189, 112, 181, 4, 70, 0, 105, ++ 254, 247, 14, 255, 5, 70, 32, 105, 212, 248, 164, 97, 29, 240, 108, ++ 222, 48, 97, 32, 105, 212, 248, 164, 97, 29, 240, 22, 222, 48, 102, ++ 40, 70, 112, 189, 208, 248, 164, 49, 147, 248, 102, 0, 8, 177, 147, ++ 248, 103, 0, 112, 71, 208, 248, 164, 49, 24, 110, 112, 71, 11, 70, 208, ++ 248, 164, 17, 16, 181, 0, 41, 49, 208, 82, 177, 90, 28, 1, 209, 0, 34, ++ 4, 224, 11, 177, 26, 7, 44, 208, 11, 131, 1, 34, 129, 248, 44, 32, 145, ++ 248, 44, 32, 194, 185, 179, 241, 255, 63, 20, 209, 4, 104, 212, 248, ++ 128, 48, 19, 244, 128, 3, 14, 208, 3, 105, 155, 111, 27, 126, 3, 43, ++ 8, 209, 212, 248, 132, 48, 3, 244, 0, 3, 0, 43, 12, 191, 1, 35, 2, 35, ++ 0, 224, 19, 70, 11, 131, 66, 126, 106, 177, 0, 105, 64, 242, 242, 97, ++ 154, 178, 31, 240, 63, 220, 0, 32, 16, 189, 79, 240, 255, 48, 16, 189, ++ 111, 240, 1, 0, 16, 189, 16, 70, 16, 189, 0, 0, 247, 181, 3, 104, 4, ++ 70, 147, 248, 61, 48, 0, 43, 64, 240, 161, 128, 33, 240, 96, 219, 2, ++ 40, 64, 243, 156, 128, 32, 70, 33, 240, 248, 218, 0, 40, 0, 240, 150, ++ 128, 32, 105, 29, 240, 176, 221, 35, 104, 6, 70, 218, 110, 212, 248, ++ 108, 114, 0, 42, 64, 240, 139, 128, 27, 126, 0, 43, 0, 240, 135, 128, ++ 148, 248, 216, 49, 35, 177, 32, 70, 3, 240, 226, 223, 0, 40, 126, 209, ++ 212, 248, 164, 49, 221, 121, 77, 177, 212, 248, 108, 50, 211, 248, 0, ++ 49, 27, 105, 91, 66, 171, 66, 204, 191, 8, 37, 0, 37, 6, 240, 4, 3, ++ 0, 43, 24, 191, 8, 37, 187, 121, 22, 240, 16, 6, 24, 191, 79, 244, 0, ++ 118, 43, 187, 215, 248, 244, 48, 147, 249, 52, 48, 3, 179, 59, 122, ++ 243, 177, 59, 124, 35, 177, 7, 241, 188, 0, 226, 247, 73, 250, 184, ++ 185, 148, 248, 113, 50, 1, 43, 19, 209, 148, 248, 114, 50, 35, 177, ++ 212, 248, 8, 5, 18, 240, 109, 221, 88, 185, 183, 248, 90, 48, 163, 177, ++ 58, 109, 64, 242, 55, 19, 19, 64, 123, 177, 151, 248, 92, 48, 211, 177, ++ 11, 224, 148, 248, 113, 50, 91, 177, 212, 248, 112, 34, 30, 75, 19, ++ 64, 179, 245, 128, 127, 16, 209, 59, 124, 115, 177, 53, 67, 173, 178, ++ 11, 224, 148, 248, 114, 50, 59, 177, 212, 248, 8, 5, 18, 240, 74, 221, ++ 0, 40, 8, 191, 0, 37, 0, 224, 29, 70, 2, 33, 32, 70, 79, 244, 2, 114, ++ 43, 70, 0, 145, 4, 240, 219, 217, 53, 66, 25, 208, 0, 35, 212, 248, ++ 104, 34, 209, 88, 137, 177, 138, 121, 122, 185, 10, 122, 106, 177, 10, ++ 124, 90, 177, 212, 248, 72, 1, 54, 240, 72, 216, 1, 70, 212, 248, 72, ++ 1, 3, 176, 189, 232, 240, 64, 54, 240, 78, 155, 4, 51, 32, 43, 230, ++ 209, 3, 176, 240, 189, 0, 191, 0, 255, 255, 0, 115, 181, 4, 104, 6, ++ 70, 32, 70, 33, 240, 84, 218, 212, 248, 164, 49, 5, 70, 147, 248, 62, ++ 32, 1, 50, 131, 248, 62, 32, 144, 177, 35, 106, 27, 104, 2, 43, 14, ++ 209, 1, 40, 3, 209, 32, 70, 49, 70, 255, 247, 232, 253, 32, 70, 33, ++ 240, 88, 219, 32, 70, 212, 248, 108, 18, 1, 34, 255, 247, 48, 255, 35, ++ 106, 27, 104, 2, 43, 80, 209, 1, 35, 141, 248, 6, 48, 141, 248, 7, 48, ++ 93, 179, 4, 45, 41, 208, 35, 104, 147, 248, 66, 32, 42, 179, 147, 248, ++ 67, 32, 18, 179, 212, 248, 104, 33, 10, 177, 146, 121, 234, 185, 147, ++ 248, 63, 48, 211, 177, 212, 248, 164, 49, 66, 242, 14, 114, 153, 136, ++ 1, 57, 137, 178, 145, 66, 4, 217, 91, 141, 19, 185, 150, 248, 93, 16, ++ 41, 177, 1, 61, 1, 45, 9, 216, 32, 70, 1, 33, 0, 224, 32, 70, 13, 241, ++ 7, 2, 13, 241, 6, 3, 255, 247, 217, 253, 157, 248, 7, 16, 157, 248, ++ 6, 48, 161, 241, 1, 0, 65, 66, 163, 241, 1, 14, 65, 235, 0, 1, 222, ++ 241, 0, 3, 67, 235, 14, 3, 2, 34, 141, 248, 6, 48, 32, 70, 19, 70, 141, ++ 248, 7, 16, 13, 240, 192, 216, 32, 70, 157, 248, 6, 16, 2, 34, 1, 35, ++ 13, 240, 185, 216, 0, 32, 124, 189, 56, 181, 67, 126, 208, 248, 164, ++ 65, 171, 177, 4, 241, 42, 3, 0, 105, 33, 29, 162, 29, 254, 247, 14, ++ 253, 163, 121, 99, 185, 148, 248, 56, 80, 77, 185, 4, 241, 45, 0, 41, ++ 70, 8, 34, 220, 243, 160, 244, 132, 248, 56, 80, 132, 248, 57, 80, 56, ++ 189, 248, 181, 67, 126, 4, 70, 13, 70, 23, 70, 187, 177, 146, 33, 0, ++ 105, 30, 240, 57, 221, 70, 0, 182, 178, 164, 54, 32, 105, 49, 70, 30, ++ 240, 50, 221, 21, 177, 64, 234, 7, 2, 1, 224, 32, 234, 7, 2, 32, 105, ++ 146, 178, 49, 70, 189, 232, 248, 64, 31, 240, 211, 154, 248, 189, 56, ++ 181, 131, 143, 4, 70, 5, 104, 43, 185, 40, 105, 146, 33, 30, 240, 27, ++ 221, 64, 0, 160, 135, 40, 70, 1, 33, 79, 244, 128, 114, 255, 247, 208, ++ 255, 0, 32, 56, 189, 1, 41, 0, 105, 24, 191, 0, 33, 255, 247, 100, 185, ++ 56, 181, 17, 70, 4, 70, 0, 104, 21, 70, 255, 247, 132, 250, 41, 70, ++ 196, 248, 44, 1, 6, 34, 4, 245, 146, 112, 189, 232, 56, 64, 219, 247, ++ 210, 184, 138, 66, 16, 181, 16, 208, 208, 248, 48, 1, 12, 24, 33, 70, ++ 16, 24, 79, 244, 138, 114, 219, 247, 198, 248, 32, 70, 0, 33, 79, 244, ++ 138, 114, 189, 232, 16, 64, 220, 243, 62, 180, 16, 189, 2, 104, 1, 70, ++ 210, 248, 112, 49, 210, 248, 196, 6, 3, 245, 198, 114, 3, 245, 206, ++ 115, 25, 240, 146, 188, 0, 0, 56, 181, 5, 70, 0, 36, 6, 72, 41, 70, ++ 0, 25, 220, 243, 180, 244, 32, 177, 4, 52, 40, 44, 246, 209, 0, 32, ++ 56, 189, 1, 32, 56, 189, 243, 57, 4, 0, 67, 104, 112, 181, 4, 70, 211, ++ 177, 131, 105, 75, 185, 18, 224, 163, 105, 91, 25, 88, 104, 8, 177, ++ 228, 247, 46, 248, 1, 54, 12, 53, 1, 224, 0, 37, 46, 70, 35, 106, 158, ++ 66, 241, 211, 160, 105, 228, 247, 35, 248, 0, 35, 163, 97, 96, 104, ++ 228, 247, 30, 248, 0, 35, 99, 96, 112, 189, 45, 233, 247, 79, 30, 70, ++ 3, 104, 4, 70, 1, 147, 139, 7, 139, 70, 21, 70, 102, 213, 255, 247, ++ 212, 255, 19, 46, 64, 242, 228, 128, 107, 104, 158, 66, 192, 240, 224, ++ 128, 40, 70, 114, 73, 4, 34, 219, 247, 83, 248, 7, 70, 0, 40, 64, 240, ++ 219, 128, 105, 104, 5, 241, 12, 0, 12, 57, 79, 240, 255, 50, 221, 243, ++ 94, 242, 171, 104, 192, 67, 131, 66, 64, 240, 198, 128, 104, 104, 160, ++ 96, 227, 247, 235, 255, 96, 96, 0, 40, 0, 240, 192, 128, 41, 70, 162, ++ 104, 219, 247, 73, 248, 99, 104, 12, 32, 27, 105, 88, 67, 224, 97, 227, ++ 247, 220, 255, 160, 97, 0, 40, 0, 240, 177, 128, 163, 104, 39, 98, 184, ++ 70, 170, 70, 50, 70, 30, 224, 20, 32, 0, 251, 8, 17, 209, 248, 24, 144, ++ 153, 69, 192, 240, 169, 128, 163, 105, 205, 105, 73, 105, 222, 25, 217, ++ 81, 181, 96, 40, 70, 0, 146, 227, 247, 192, 255, 12, 55, 112, 96, 0, ++ 154, 0, 40, 0, 240, 147, 128, 33, 106, 5, 235, 9, 3, 1, 49, 33, 98, ++ 8, 241, 1, 8, 97, 104, 8, 105, 128, 69, 220, 211, 0, 35, 227, 96, 35, ++ 97, 79, 240, 255, 51, 85, 70, 22, 70, 99, 97, 99, 104, 0, 43, 126, 208, ++ 227, 104, 243, 24, 152, 70, 69, 224, 33, 105, 35, 106, 153, 66, 59, ++ 210, 103, 104, 20, 35, 3, 251, 1, 119, 224, 104, 186, 105, 130, 66, ++ 4, 217, 23, 26, 190, 66, 56, 191, 55, 70, 47, 224, 212, 248, 24, 224, ++ 79, 240, 12, 12, 255, 105, 12, 251, 1, 225, 2, 235, 7, 10, 208, 69, ++ 52, 191, 193, 70, 209, 70, 192, 235, 9, 7, 130, 26, 72, 104, 41, 70, ++ 128, 24, 58, 70, 0, 147, 218, 247, 222, 255, 40, 70, 57, 70, 98, 105, ++ 221, 243, 221, 241, 209, 69, 96, 97, 0, 155, 15, 211, 34, 105, 97, 104, ++ 192, 67, 3, 251, 2, 19, 27, 106, 96, 97, 131, 66, 66, 209, 1, 50, 79, ++ 240, 255, 51, 34, 97, 99, 97, 0, 224, 55, 70, 227, 104, 237, 25, 219, ++ 25, 227, 96, 246, 27, 0, 46, 183, 209, 27, 240, 4, 15, 39, 208, 34, ++ 105, 35, 106, 154, 66, 47, 209, 96, 104, 227, 247, 81, 255, 1, 155, ++ 102, 96, 211, 248, 92, 1, 161, 105, 34, 106, 12, 155, 152, 71, 55, 70, ++ 5, 70, 7, 224, 163, 105, 155, 25, 88, 104, 8, 177, 227, 247, 64, 255, ++ 1, 55, 12, 54, 35, 106, 159, 66, 244, 211, 160, 105, 227, 247, 56, 255, ++ 0, 35, 1, 45, 163, 97, 4, 217, 32, 70, 255, 247, 246, 254, 0, 224, 1, ++ 37, 40, 70, 189, 232, 254, 143, 4, 37, 245, 231, 5, 37, 243, 231, 2, ++ 37, 241, 231, 6, 37, 239, 231, 3, 37, 237, 231, 0, 191, 212, 57, 4, ++ 0, 240, 181, 137, 176, 15, 158, 0, 35, 3, 46, 4, 70, 23, 70, 14, 157, ++ 7, 147, 4, 217, 7, 168, 41, 70, 4, 34, 218, 247, 115, 255, 5, 47, 2, ++ 208, 6, 47, 38, 209, 31, 224, 15, 46, 9, 217, 41, 70, 16, 34, 3, 168, ++ 218, 247, 103, 255, 189, 248, 12, 16, 11, 11, 1, 43, 3, 208, 2, 35, ++ 196, 248, 48, 49, 12, 224, 12, 75, 212, 248, 52, 1, 0, 147, 5, 241, ++ 12, 2, 4, 155, 255, 247, 215, 254, 1, 40, 196, 248, 48, 1, 6, 217, 79, ++ 240, 255, 48, 7, 224, 212, 248, 48, 33, 16, 155, 26, 96, 0, 32, 1, 224, ++ 111, 240, 22, 0, 9, 176, 240, 189, 37, 124, 2, 0, 1, 240, 0, 191, 247, ++ 181, 0, 35, 22, 70, 2, 170, 15, 120, 66, 248, 4, 61, 12, 75, 5, 70, ++ 0, 47, 20, 191, 15, 70, 31, 70, 56, 70, 49, 70, 255, 247, 237, 255, ++ 4, 70, 64, 185, 5, 241, 8, 0, 57, 70, 3, 34, 220, 243, 135, 243, 238, ++ 96, 32, 70, 1, 224, 111, 240, 1, 0, 254, 189, 0, 191, 162, 153, 136, ++ 0, 1, 240, 237, 190, 247, 181, 6, 70, 21, 70, 31, 70, 2, 170, 0, 35, ++ 12, 70, 66, 248, 4, 61, 241, 104, 8, 48, 255, 247, 205, 255, 6, 70, ++ 80, 185, 33, 70, 58, 70, 1, 152, 255, 247, 234, 255, 33, 70, 6, 70, ++ 4, 34, 40, 70, 220, 243, 98, 243, 214, 241, 1, 0, 56, 191, 0, 32, 254, ++ 189, 7, 181, 0, 35, 2, 170, 66, 248, 4, 61, 208, 248, 92, 49, 3, 241, ++ 8, 0, 217, 104, 255, 247, 175, 255, 208, 241, 1, 0, 56, 191, 0, 32, ++ 14, 189, 1, 240, 153, 190, 45, 233, 248, 67, 208, 248, 12, 144, 7, 70, ++ 8, 70, 14, 70, 21, 70, 28, 70, 221, 248, 32, 128, 220, 243, 17, 243, ++ 3, 40, 37, 216, 49, 70, 40, 70, 4, 34, 220, 243, 54, 243, 0, 35, 35, ++ 96, 7, 241, 8, 0, 49, 70, 220, 243, 219, 242, 16, 185, 196, 248, 0, ++ 144, 5, 224, 56, 70, 49, 70, 42, 70, 35, 70, 255, 247, 169, 255, 40, ++ 70, 33, 104, 66, 70, 255, 247, 212, 255, 80, 177, 35, 104, 67, 177, ++ 0, 33, 40, 70, 66, 70, 33, 96, 189, 232, 248, 67, 255, 247, 201, 191, ++ 1, 32, 189, 232, 248, 131, 240, 181, 75, 104, 159, 176, 6, 70, 12, 70, ++ 19, 185, 3, 106, 27, 104, 139, 96, 161, 104, 75, 30, 1, 43, 0, 242, ++ 138, 128, 51, 106, 26, 104, 145, 66, 2, 208, 0, 32, 224, 96, 132, 224, ++ 24, 105, 14, 170, 6, 240, 207, 252, 26, 168, 1, 240, 95, 248, 232, 177, ++ 0, 37, 35, 224, 26, 152, 21, 169, 39, 240, 177, 223, 3, 70, 176, 185, ++ 161, 104, 21, 168, 1, 41, 24, 191, 25, 70, 106, 70, 7, 171, 40, 240, ++ 242, 217, 0, 35, 14, 170, 29, 248, 3, 16, 154, 92, 17, 66, 1, 208, 1, ++ 53, 4, 224, 1, 51, 28, 43, 244, 209, 0, 224, 5, 70, 26, 168, 28, 169, ++ 27, 170, 1, 240, 19, 254, 0, 40, 219, 208, 5, 53, 35, 104, 173, 0, 157, ++ 66, 3, 217, 37, 96, 111, 240, 13, 0, 77, 224, 26, 168, 1, 240, 44, 248, ++ 0, 40, 66, 209, 173, 248, 116, 0, 5, 70, 54, 224, 26, 152, 21, 169, ++ 39, 240, 123, 223, 3, 70, 0, 40, 47, 209, 161, 104, 21, 168, 1, 41, ++ 24, 191, 25, 70, 106, 70, 7, 171, 40, 240, 187, 217, 0, 35, 14, 170, ++ 29, 248, 3, 16, 154, 92, 17, 66, 28, 208, 48, 70, 28, 169, 39, 240, ++ 56, 217, 208, 177, 28, 168, 29, 169, 2, 34, 218, 247, 41, 254, 160, ++ 177, 175, 0, 4, 241, 16, 0, 192, 25, 28, 169, 2, 34, 220, 243, 147, ++ 242, 231, 25, 0, 35, 187, 116, 29, 168, 28, 169, 2, 34, 218, 247, 43, ++ 254, 1, 53, 2, 224, 1, 51, 28, 43, 217, 209, 26, 168, 28, 169, 27, 170, ++ 1, 240, 195, 253, 0, 40, 193, 208, 0, 224, 0, 37, 229, 96, 0, 32, 1, ++ 224, 111, 240, 12, 0, 31, 176, 240, 189, 45, 233, 240, 71, 68, 104, ++ 234, 176, 129, 70, 16, 70, 15, 70, 21, 70, 16, 240, 50, 251, 100, 168, ++ 0, 240, 217, 255, 0, 40, 64, 240, 11, 129, 7, 244, 64, 67, 163, 245, ++ 64, 70, 115, 66, 67, 235, 6, 3, 10, 51, 72, 70, 57, 70, 84, 248, 35, ++ 96, 40, 240, 128, 219, 128, 185, 35, 104, 147, 248, 175, 48, 0, 43, ++ 0, 240, 246, 128, 212, 248, 136, 1, 9, 240, 53, 219, 104, 170, 1, 70, ++ 32, 70, 39, 240, 22, 221, 24, 177, 234, 224, 217, 248, 16, 48, 104, ++ 147, 127, 35, 101, 147, 150, 248, 6, 49, 150, 248, 4, 129, 134, 248, ++ 5, 49, 153, 248, 245, 32, 10, 177, 91, 178, 101, 147, 95, 169, 104, ++ 152, 39, 240, 244, 222, 1, 70, 0, 40, 64, 240, 211, 128, 105, 170, 95, ++ 168, 3, 50, 39, 240, 167, 222, 0, 40, 64, 240, 203, 128, 153, 248, 244, ++ 16, 254, 178, 113, 177, 157, 249, 167, 49, 0, 43, 7, 218, 1, 46, 7, ++ 208, 166, 241, 13, 0, 65, 66, 65, 235, 0, 1, 2, 224, 1, 70, 0, 224, ++ 49, 70, 32, 105, 29, 240, 48, 223, 35, 104, 147, 248, 47, 32, 138, 177, ++ 147, 248, 48, 48, 115, 185, 180, 248, 72, 4, 221, 243, 159, 243, 1, ++ 34, 1, 70, 212, 248, 92, 1, 39, 240, 195, 222, 193, 178, 212, 248, 120, ++ 1, 78, 240, 210, 218, 7, 244, 96, 83, 179, 245, 128, 95, 79, 250, 136, ++ 248, 37, 209, 100, 171, 0, 33, 1, 147, 50, 70, 5, 172, 95, 168, 67, ++ 70, 100, 145, 0, 145, 2, 148, 38, 240, 121, 222, 6, 70, 0, 40, 64, 240, ++ 136, 128, 35, 70, 49, 70, 1, 34, 40, 70, 16, 240, 94, 251, 35, 29, 0, ++ 147, 49, 70, 50, 70, 1, 35, 40, 70, 16, 240, 105, 251, 12, 52, 1, 34, ++ 0, 146, 1, 148, 40, 70, 49, 70, 51, 70, 111, 224, 179, 245, 192, 95, ++ 110, 209, 0, 33, 1, 36, 13, 245, 200, 122, 13, 241, 20, 9, 95, 168, ++ 50, 70, 67, 70, 0, 145, 100, 148, 205, 248, 4, 160, 205, 248, 8, 144, ++ 38, 240, 75, 222, 1, 70, 0, 40, 90, 209, 7, 244, 124, 87, 183, 245, ++ 200, 95, 20, 191, 39, 70, 2, 39, 141, 232, 128, 4, 67, 70, 13, 241, ++ 200, 10, 95, 168, 50, 70, 205, 248, 8, 160, 38, 240, 54, 222, 128, 70, ++ 0, 40, 69, 209, 9, 241, 4, 6, 33, 70, 66, 70, 35, 70, 40, 70, 0, 150, ++ 16, 240, 44, 251, 33, 70, 66, 70, 35, 70, 40, 70, 0, 150, 16, 240, 37, ++ 251, 9, 241, 12, 3, 1, 147, 33, 70, 34, 70, 67, 70, 40, 70, 0, 148, ++ 16, 240, 68, 251, 65, 70, 34, 70, 83, 70, 40, 70, 16, 240, 2, 251, 51, ++ 175, 65, 70, 66, 70, 35, 70, 40, 70, 53, 174, 0, 151, 16, 240, 12, 251, ++ 65, 70, 34, 70, 67, 70, 40, 70, 0, 148, 1, 150, 16, 240, 45, 251, 3, ++ 33, 34, 70, 83, 70, 40, 70, 16, 240, 235, 250, 3, 33, 66, 70, 35, 70, ++ 40, 70, 0, 151, 16, 240, 247, 250, 141, 232, 80, 0, 40, 70, 3, 33, 34, ++ 70, 67, 70, 16, 240, 24, 251, 106, 176, 189, 232, 240, 135, 248, 181, ++ 69, 104, 6, 70, 107, 126, 15, 70, 0, 43, 49, 208, 181, 248, 72, 20, ++ 3, 104, 1, 244, 96, 81, 161, 245, 192, 94, 222, 241, 0, 1, 88, 105, ++ 65, 235, 14, 1, 16, 240, 42, 250, 4, 70, 32, 179, 34, 70, 181, 248, ++ 72, 20, 48, 70, 255, 247, 197, 254, 43, 106, 24, 105, 7, 240, 219, 253, ++ 16, 240, 60, 253, 121, 178, 32, 70, 16, 240, 24, 251, 33, 70, 48, 70, ++ 38, 240, 119, 222, 43, 106, 33, 70, 24, 105, 181, 248, 72, 36, 6, 240, ++ 40, 253, 51, 104, 33, 70, 88, 105, 16, 240, 22, 250, 0, 32, 248, 189, ++ 111, 240, 10, 0, 248, 189, 79, 240, 255, 48, 248, 189, 0, 0, 45, 233, ++ 240, 71, 71, 104, 4, 70, 59, 106, 14, 70, 24, 105, 7, 240, 179, 253, ++ 49, 70, 5, 70, 16, 240, 247, 252, 1, 40, 223, 248, 212, 144, 22, 208, ++ 185, 248, 0, 16, 121, 177, 40, 70, 16, 240, 244, 252, 128, 70, 80, 177, ++ 65, 70, 1, 34, 40, 70, 16, 240, 77, 252, 35, 104, 41, 70, 88, 105, 66, ++ 70, 16, 240, 237, 252, 40, 70, 49, 70, 16, 240, 61, 253, 0, 34, 40, ++ 70, 49, 70, 169, 248, 0, 96, 16, 240, 203, 252, 128, 48, 18, 208, 0, ++ 33, 32, 70, 38, 240, 45, 222, 49, 70, 32, 70, 61, 105, 40, 240, 116, ++ 216, 2, 28, 24, 191, 1, 34, 40, 70, 49, 70, 0, 35, 189, 232, 240, 71, ++ 253, 247, 240, 189, 6, 244, 96, 81, 161, 245, 192, 92, 35, 104, 220, ++ 241, 0, 1, 88, 105, 65, 235, 12, 1, 16, 240, 175, 249, 5, 70, 0, 40, ++ 36, 208, 42, 70, 49, 70, 32, 70, 255, 247, 74, 254, 215, 248, 120, 1, ++ 78, 240, 76, 217, 65, 178, 40, 70, 16, 240, 159, 250, 41, 70, 32, 70, ++ 38, 240, 254, 221, 49, 70, 32, 70, 63, 105, 40, 240, 69, 216, 2, 28, ++ 49, 70, 56, 70, 43, 70, 24, 191, 1, 34, 253, 247, 195, 253, 35, 104, ++ 41, 70, 88, 105, 189, 232, 240, 71, 16, 240, 149, 185, 189, 232, 240, ++ 135, 120, 8, 0, 0, 45, 233, 243, 65, 69, 104, 6, 70, 23, 70, 40, 70, ++ 1, 170, 12, 70, 39, 240, 96, 219, 128, 70, 184, 177, 1, 63, 24, 73, ++ 58, 70, 32, 70, 220, 243, 138, 240, 40, 70, 33, 70, 1, 170, 39, 240, ++ 83, 219, 128, 70, 80, 177, 19, 73, 58, 70, 32, 70, 220, 243, 126, 240, ++ 40, 70, 33, 70, 1, 170, 39, 240, 71, 219, 128, 70, 213, 248, 140, 1, ++ 33, 70, 40, 240, 167, 220, 32, 70, 255, 247, 96, 251, 24, 177, 213, ++ 248, 136, 1, 33, 70, 2, 224, 213, 248, 136, 1, 7, 73, 9, 240, 200, 217, ++ 48, 70, 33, 70, 40, 240, 190, 216, 64, 70, 189, 232, 252, 129, 0, 191, ++ 146, 153, 136, 0, 154, 206, 135, 0, 41, 155, 136, 0, 1, 42, 247, 181, ++ 4, 70, 88, 217, 75, 105, 4, 43, 85, 209, 11, 105, 154, 120, 88, 120, ++ 18, 4, 66, 234, 0, 34, 24, 120, 219, 120, 2, 67, 66, 234, 3, 98, 74, ++ 246, 166, 19, 154, 66, 72, 209, 212, 248, 156, 48, 0, 38, 77, 104, 143, ++ 104, 78, 96, 99, 177, 48, 70, 0, 240, 158, 253, 212, 248, 156, 0, 227, ++ 247, 113, 251, 196, 248, 164, 96, 196, 248, 156, 96, 196, 248, 160, ++ 96, 212, 248, 148, 0, 8, 177, 227, 247, 102, 251, 69, 177, 40, 70, 0, ++ 240, 129, 253, 0, 40, 44, 208, 40, 70, 227, 247, 93, 251, 9, 37, 23, ++ 72, 0, 240, 120, 253, 0, 35, 196, 248, 152, 48, 196, 248, 148, 48, 4, ++ 241, 20, 0, 161, 105, 106, 70, 255, 247, 197, 252, 8, 185, 0, 155, 0, ++ 224, 0, 35, 35, 97, 0, 33, 4, 34, 1, 168, 219, 243, 39, 247, 4, 241, ++ 8, 1, 3, 34, 1, 168, 220, 243, 1, 240, 32, 70, 1, 169, 4, 34, 255, 247, ++ 96, 255, 2, 224, 7, 37, 0, 224, 8, 37, 40, 70, 254, 189, 196, 248, 148, ++ 80, 196, 248, 152, 112, 5, 70, 216, 231, 40, 60, 4, 0, 1, 244, 96, 83, ++ 179, 245, 0, 95, 112, 181, 6, 70, 0, 241, 196, 5, 204, 178, 27, 209, ++ 6, 44, 1, 217, 161, 31, 0, 224, 0, 33, 40, 70, 220, 243, 68, 245, 2, ++ 44, 1, 217, 161, 30, 0, 224, 0, 33, 40, 70, 220, 243, 60, 245, 221, ++ 44, 1, 216, 161, 28, 0, 224, 0, 33, 40, 70, 220, 243, 52, 245, 217, ++ 44, 16, 216, 161, 29, 15, 224, 179, 245, 192, 95, 14, 209, 2, 44, 1, ++ 217, 161, 30, 0, 224, 0, 33, 40, 70, 220, 243, 37, 245, 221, 44, 1, ++ 216, 161, 28, 0, 224, 0, 33, 40, 70, 1, 224, 40, 70, 33, 70, 220, 243, ++ 26, 245, 48, 70, 189, 232, 112, 64, 39, 240, 89, 152, 0, 0, 31, 181, ++ 12, 70, 22, 75, 208, 248, 148, 16, 0, 41, 8, 191, 25, 70, 1, 241, 14, ++ 0, 177, 249, 10, 32, 177, 249, 12, 48, 0, 144, 1, 241, 34, 0, 52, 49, ++ 1, 144, 2, 145, 32, 70, 14, 73, 220, 243, 44, 241, 1, 240, 130, 250, ++ 2, 70, 24, 177, 32, 70, 11, 73, 220, 243, 36, 241, 4, 32, 0, 33, 1, ++ 240, 124, 250, 2, 70, 48, 177, 7, 73, 32, 70, 4, 176, 189, 232, 16, ++ 64, 220, 243, 23, 177, 4, 176, 16, 189, 0, 191, 40, 60, 4, 0, 96, 156, ++ 136, 0, 133, 156, 136, 0, 152, 156, 136, 0, 16, 181, 16, 248, 1, 59, ++ 12, 70, 35, 177, 17, 248, 1, 43, 10, 177, 147, 66, 246, 208, 32, 120, ++ 24, 26, 16, 189, 11, 224, 75, 30, 75, 64, 33, 234, 3, 1, 91, 8, 3, 234, ++ 0, 2, 64, 8, 32, 234, 3, 0, 16, 67, 73, 8, 0, 41, 241, 209, 112, 71, ++ 1, 224, 0, 248, 1, 27, 18, 241, 255, 50, 250, 210, 112, 71, 2, 75, 84, ++ 34, 2, 251, 0, 48, 112, 71, 0, 191, 48, 115, 4, 0, 0, 72, 112, 71, 220, ++ 115, 4, 0, 16, 181, 12, 70, 255, 247, 240, 255, 3, 104, 35, 177, 27, ++ 89, 35, 177, 64, 104, 24, 24, 16, 189, 24, 70, 16, 189, 24, 70, 16, ++ 189, 16, 181, 12, 70, 33, 177, 255, 247, 224, 255, 64, 104, 32, 24, ++ 16, 189, 8, 70, 16, 189, 1, 56, 17, 177, 192, 243, 128, 115, 11, 96, ++ 18, 177, 32, 240, 64, 64, 16, 96, 112, 71, 72, 177, 1, 41, 12, 191, ++ 79, 240, 128, 65, 0, 33, 34, 240, 64, 66, 10, 67, 1, 50, 2, 96, 112, ++ 71, 2, 224, 3, 120, 1, 51, 192, 24, 17, 241, 255, 49, 249, 210, 112, ++ 71, 45, 233, 243, 65, 14, 70, 5, 70, 20, 70, 16, 70, 0, 33, 44, 34, ++ 255, 247, 172, 255, 3, 46, 116, 216, 223, 232, 6, 240, 2, 10, 17, 25, ++ 40, 104, 105, 70, 1, 170, 255, 247, 205, 255, 0, 37, 1, 39, 21, 224, ++ 104, 104, 105, 70, 1, 170, 255, 247, 197, 255, 1, 37, 5, 224, 168, 104, ++ 105, 70, 1, 170, 255, 247, 190, 255, 0, 37, 47, 70, 6, 224, 232, 104, ++ 105, 70, 1, 170, 255, 247, 182, 255, 1, 37, 0, 39, 1, 155, 64, 242, ++ 255, 50, 147, 66, 75, 208, 64, 242, 254, 50, 147, 66, 73, 208, 0, 152, ++ 255, 247, 131, 255, 3, 104, 6, 54, 128, 70, 83, 248, 38, 16, 0, 152, ++ 255, 247, 150, 255, 17, 224, 31, 177, 195, 120, 0, 235, 67, 0, 4, 48, ++ 3, 70, 19, 248, 1, 27, 64, 120, 1, 240, 48, 2, 18, 17, 3, 50, 0, 251, ++ 2, 48, 1, 48, 75, 7, 242, 212, 1, 155, 90, 30, 1, 146, 0, 43, 232, 209, ++ 8, 241, 60, 3, 99, 96, 5, 241, 8, 3, 8, 235, 195, 8, 8, 241, 4, 3, 163, ++ 96, 32, 96, 16, 33, 0, 152, 255, 247, 96, 255, 12, 33, 224, 96, 0, 152, ++ 255, 247, 91, 255, 32, 97, 0, 152, 255, 247, 75, 255, 8, 48, 110, 0, ++ 0, 235, 5, 21, 101, 97, 0, 152, 255, 247, 67, 255, 1, 54, 8, 48, 0, ++ 235, 198, 6, 166, 97, 1, 32, 0, 224, 0, 32, 189, 232, 252, 129, 0, 0, ++ 45, 233, 247, 67, 4, 70, 255, 247, 51, 255, 5, 104, 32, 70, 125, 185, ++ 255, 247, 46, 255, 133, 96, 32, 70, 255, 247, 42, 255, 5, 97, 32, 70, ++ 255, 247, 38, 255, 133, 97, 32, 70, 255, 247, 34, 255, 5, 98, 83, 224, ++ 0, 33, 255, 247, 41, 255, 4, 33, 5, 70, 0, 144, 32, 70, 255, 247, 35, ++ 255, 46, 104, 1, 144, 118, 185, 3, 104, 0, 43, 64, 208, 11, 224, 1, ++ 32, 255, 247, 13, 255, 8, 48, 0, 144, 1, 32, 255, 247, 8, 255, 24, 48, ++ 1, 144, 54, 224, 0, 38, 173, 241, 4, 8, 0, 37, 32, 70, 255, 247, 254, ++ 254, 88, 248, 4, 127, 0, 235, 5, 19, 8, 51, 151, 232, 3, 0, 131, 232, ++ 3, 0, 6, 177, 84, 177, 32, 70, 255, 247, 240, 254, 121, 104, 129, 70, ++ 32, 70, 255, 247, 6, 255, 9, 235, 5, 19, 216, 96, 1, 53, 2, 45, 227, ++ 209, 32, 70, 255, 247, 226, 254, 11, 74, 0, 241, 16, 3, 146, 232, 3, ++ 0, 131, 232, 3, 0, 32, 70, 255, 247, 216, 254, 7, 74, 0, 241, 32, 3, ++ 146, 232, 3, 0, 131, 232, 3, 0, 3, 224, 0, 44, 189, 208, 1, 38, 199, ++ 231, 189, 232, 254, 131, 156, 58, 4, 0, 40, 58, 4, 0, 10, 104, 3, 70, ++ 72, 104, 2, 235, 66, 2, 48, 181, 130, 24, 13, 224, 4, 120, 163, 66, ++ 9, 219, 65, 120, 139, 66, 6, 220, 129, 120, 28, 27, 148, 251, 241, 245, ++ 1, 251, 21, 65, 25, 177, 3, 48, 144, 66, 239, 209, 0, 32, 48, 189, 6, ++ 201, 1, 235, 65, 1, 3, 70, 48, 181, 81, 24, 0, 32, 10, 224, 20, 120, ++ 156, 66, 6, 221, 32, 177, 5, 120, 165, 66, 136, 191, 16, 70, 0, 224, ++ 16, 70, 3, 50, 138, 66, 242, 209, 48, 189, 45, 233, 248, 79, 10, 159, ++ 13, 70, 20, 70, 152, 70, 6, 70, 0, 40, 91, 208, 0, 33, 25, 34, 255, ++ 247, 130, 254, 0, 45, 85, 208, 255, 44, 83, 208, 33, 70, 40, 70, 255, ++ 247, 188, 254, 144, 248, 0, 176, 4, 70, 131, 68, 72, 224, 20, 248, 1, ++ 63, 255, 43, 31, 209, 120, 104, 57, 104, 0, 34, 23, 224, 131, 92, 15, ++ 224, 3, 240, 7, 9, 79, 240, 1, 10, 10, 250, 9, 250, 79, 234, 227, 12, ++ 22, 248, 12, 144, 74, 234, 9, 9, 6, 248, 12, 144, 173, 120, 91, 25, ++ 133, 24, 149, 248, 1, 192, 99, 69, 234, 221, 3, 50, 17, 241, 255, 49, ++ 228, 210, 36, 224, 24, 248, 19, 80, 8, 235, 67, 2, 40, 70, 57, 70, 146, ++ 248, 1, 144, 255, 247, 136, 255, 200, 177, 1, 33, 5, 240, 7, 2, 17, ++ 250, 2, 242, 235, 16, 241, 92, 77, 69, 66, 234, 1, 2, 242, 84, 13, 218, ++ 67, 120, 157, 66, 2, 218, 131, 120, 237, 24, 237, 231, 40, 70, 57, 70, ++ 255, 247, 139, 255, 16, 177, 5, 120, 77, 69, 229, 221, 92, 69, 180, ++ 209, 189, 232, 248, 143, 56, 181, 21, 70, 18, 104, 4, 70, 8, 120, 58, ++ 185, 132, 66, 34, 209, 74, 120, 154, 26, 80, 66, 64, 235, 2, 0, 56, ++ 189, 132, 66, 33, 219, 75, 120, 156, 66, 25, 220, 41, 70, 255, 247, ++ 83, 255, 3, 224, 24, 70, 41, 70, 255, 247, 104, 255, 136, 177, 67, 120, ++ 163, 66, 247, 219, 14, 224, 130, 120, 228, 26, 148, 251, 242, 240, 2, ++ 251, 16, 68, 212, 241, 1, 0, 56, 191, 0, 32, 56, 189, 16, 70, 56, 189, ++ 0, 32, 56, 189, 3, 120, 163, 66, 237, 221, 0, 32, 56, 189, 0, 0, 45, ++ 233, 240, 71, 18, 76, 4, 241, 108, 8, 84, 248, 8, 92, 84, 248, 4, 60, ++ 212, 248, 0, 144, 5, 235, 3, 10, 255, 247, 243, 253, 5, 240, 3, 7, 127, ++ 0, 3, 35, 187, 64, 174, 8, 130, 93, 9, 250, 7, 247, 34, 234, 3, 3, 131, ++ 85, 255, 247, 229, 253, 131, 93, 1, 53, 31, 67, 85, 69, 135, 85, 233, ++ 219, 12, 52, 68, 69, 222, 209, 189, 232, 240, 135, 56, 58, 4, 0, 248, ++ 181, 6, 70, 8, 70, 13, 70, 255, 247, 202, 253, 4, 70, 0, 46, 118, 208, ++ 48, 70, 67, 73, 255, 247, 159, 253, 0, 40, 126, 209, 115, 137, 5, 43, ++ 3, 209, 182, 249, 12, 32, 1, 42, 5, 208, 7, 59, 155, 178, 5, 43, 115, ++ 216, 1, 39, 0, 224, 7, 70, 243, 106, 40, 70, 243, 26, 99, 96, 49, 107, ++ 255, 247, 199, 253, 32, 96, 39, 177, 144, 248, 53, 48, 11, 177, 178, ++ 43, 100, 209, 102, 99, 31, 177, 67, 107, 3, 240, 1, 3, 0, 224, 59, 70, ++ 227, 98, 163, 98, 63, 177, 67, 107, 3, 240, 1, 3, 0, 43, 20, 191, 9, ++ 35, 7, 35, 0, 224, 7, 35, 35, 99, 31, 177, 67, 107, 195, 243, 192, 3, ++ 0, 224, 59, 70, 163, 99, 71, 179, 67, 107, 216, 6, 37, 213, 8, 33, 40, ++ 70, 255, 247, 142, 253, 64, 33, 224, 99, 40, 70, 255, 247, 137, 253, ++ 20, 33, 32, 100, 40, 70, 255, 247, 132, 253, 76, 33, 224, 100, 40, 70, ++ 255, 247, 127, 253, 35, 104, 32, 101, 91, 107, 153, 6, 9, 213, 88, 33, ++ 40, 70, 255, 247, 118, 253, 92, 33, 96, 100, 40, 70, 255, 247, 113, ++ 253, 1, 224, 227, 108, 99, 100, 160, 100, 17, 224, 8, 33, 40, 70, 255, ++ 247, 104, 253, 20, 33, 6, 70, 40, 70, 255, 247, 99, 253, 230, 99, 96, ++ 100, 224, 100, 38, 100, 160, 100, 32, 101, 1, 224, 70, 96, 6, 96, 40, ++ 70, 255, 247, 19, 254, 1, 45, 2, 209, 0, 32, 255, 247, 14, 254, 255, ++ 247, 74, 255, 0, 32, 248, 189, 1, 32, 248, 189, 1, 32, 248, 189, 164, ++ 203, 135, 0, 2, 120, 11, 120, 154, 66, 12, 209, 66, 120, 75, 120, 154, ++ 66, 10, 209, 128, 120, 139, 120, 195, 235, 0, 12, 220, 241, 0, 0, 64, ++ 235, 12, 0, 112, 71, 0, 32, 112, 71, 0, 32, 112, 71, 2, 120, 11, 120, ++ 154, 66, 6, 209, 64, 120, 75, 120, 195, 26, 88, 66, 64, 235, 3, 0, 112, ++ 71, 0, 32, 112, 71, 11, 120, 3, 112, 75, 120, 67, 112, 112, 71, 0, 0, ++ 3, 104, 26, 120, 26, 185, 91, 120, 11, 185, 1, 75, 3, 96, 112, 71, 164, ++ 58, 4, 0, 45, 233, 240, 65, 13, 70, 48, 33, 4, 70, 144, 70, 255, 247, ++ 14, 253, 6, 70, 8, 179, 65, 104, 9, 179, 32, 70, 255, 247, 22, 253, ++ 51, 104, 12, 38, 7, 70, 6, 251, 3, 6, 4, 70, 0, 224, 12, 52, 180, 66, ++ 5, 210, 32, 70, 41, 70, 255, 247, 177, 255, 0, 40, 246, 208, 184, 241, ++ 0, 15, 5, 208, 231, 27, 7, 75, 191, 16, 95, 67, 200, 248, 0, 112, 180, ++ 66, 40, 191, 0, 36, 2, 224, 4, 70, 0, 224, 12, 70, 32, 70, 189, 232, ++ 240, 129, 171, 170, 170, 170, 112, 181, 22, 70, 13, 70, 153, 177, 137, ++ 104, 255, 247, 234, 252, 4, 70, 136, 177, 109, 104, 5, 235, 69, 5, 69, ++ 25, 0, 224, 3, 52, 172, 66, 8, 210, 48, 70, 33, 70, 255, 247, 154, 255, ++ 0, 40, 246, 208, 2, 224, 12, 70, 0, 224, 0, 36, 32, 70, 112, 189, 112, ++ 181, 139, 24, 221, 120, 12, 70, 22, 70, 255, 247, 178, 252, 131, 106, ++ 75, 177, 227, 121, 198, 241, 4, 6, 118, 0, 19, 250, 6, 246, 6, 244, ++ 64, 118, 53, 67, 13, 224, 254, 45, 6, 208, 8, 216, 64, 242, 253, 51, ++ 253, 45, 8, 191, 29, 70, 4, 224, 64, 242, 254, 53, 1, 224, 64, 242, ++ 255, 53, 40, 70, 112, 189, 8, 181, 0, 34, 255, 247, 217, 255, 64, 242, ++ 253, 51, 194, 26, 80, 66, 64, 235, 2, 0, 8, 189, 112, 181, 13, 70, 40, ++ 33, 4, 70, 255, 247, 145, 252, 3, 70, 80, 177, 89, 104, 32, 70, 255, ++ 247, 154, 252, 6, 70, 32, 70, 255, 247, 123, 252, 0, 107, 0, 251, 5, ++ 96, 112, 189, 45, 233, 248, 67, 13, 70, 40, 33, 4, 70, 23, 70, 255, ++ 247, 123, 252, 0, 33, 128, 70, 32, 70, 255, 247, 223, 255, 6, 70, 32, ++ 70, 255, 247, 102, 252, 208, 248, 48, 144, 134, 177, 0, 36, 9, 224, ++ 48, 70, 41, 70, 255, 247, 33, 255, 16, 177, 71, 177, 60, 96, 6, 224, ++ 1, 52, 78, 68, 216, 248, 0, 48, 156, 66, 241, 219, 0, 38, 48, 70, 189, ++ 232, 248, 131, 45, 233, 240, 65, 68, 124, 7, 70, 4, 240, 1, 4, 32, 70, ++ 13, 70, 255, 247, 69, 252, 0, 33, 6, 70, 20, 34, 40, 70, 255, 247, 56, ++ 252, 6, 241, 60, 3, 43, 96, 56, 124, 16, 240, 71, 0, 53, 208, 56, 33, ++ 255, 247, 30, 252, 56, 33, 71, 30, 32, 70, 255, 247, 60, 252, 3, 70, ++ 136, 177, 2, 104, 151, 66, 14, 210, 89, 104, 32, 70, 255, 247, 66, 252, ++ 0, 235, 199, 3, 128, 70, 89, 104, 32, 70, 255, 247, 59, 252, 88, 248, ++ 55, 48, 168, 96, 107, 96, 179, 107, 187, 177, 32, 70, 60, 33, 255, 247, ++ 34, 252, 3, 70, 136, 177, 2, 104, 151, 66, 14, 210, 89, 104, 32, 70, ++ 255, 247, 40, 252, 0, 235, 199, 3, 6, 70, 89, 104, 32, 70, 255, 247, ++ 33, 252, 86, 248, 55, 48, 40, 97, 235, 96, 189, 232, 240, 129, 45, 233, ++ 248, 67, 20, 70, 21, 74, 4, 39, 18, 248, 3, 144, 79, 240, 1, 8, 79, ++ 234, 25, 19, 167, 64, 8, 250, 3, 248, 13, 70, 7, 235, 215, 119, 0, 33, ++ 2, 34, 6, 70, 95, 250, 136, 248, 127, 16, 255, 247, 224, 251, 95, 234, ++ 88, 8, 53, 85, 9, 208, 1, 60, 10, 212, 127, 16, 24, 234, 9, 15, 20, ++ 191, 237, 25, 199, 235, 5, 5, 241, 231, 1, 32, 189, 232, 248, 131, 0, ++ 32, 189, 232, 248, 131, 0, 191, 243, 58, 4, 0, 16, 181, 255, 247, 205, ++ 251, 3, 104, 92, 107, 20, 240, 2, 4, 8, 208, 68, 107, 5, 73, 82, 52, ++ 32, 70, 255, 247, 158, 251, 0, 40, 8, 191, 0, 36, 32, 70, 16, 189, 0, ++ 191, 246, 203, 135, 0, 16, 181, 4, 70, 255, 247, 182, 251, 0, 104, 32, ++ 177, 32, 70, 189, 232, 16, 64, 255, 247, 223, 191, 16, 189, 45, 233, ++ 248, 79, 5, 70, 12, 70, 22, 70, 154, 70, 0, 43, 78, 209, 152, 70, 64, ++ 70, 255, 247, 162, 251, 195, 106, 83, 177, 3, 104, 67, 177, 91, 107, ++ 153, 1, 5, 213, 64, 70, 180, 33, 255, 247, 163, 251, 129, 70, 40, 185, ++ 8, 241, 1, 8, 184, 241, 2, 15, 56, 208, 233, 231, 3, 104, 0, 43, 52, ++ 208, 64, 70, 217, 248, 4, 16, 255, 247, 162, 251, 217, 248, 0, 48, 7, ++ 70, 0, 235, 131, 11, 5, 224, 40, 70, 57, 70, 255, 247, 86, 254, 24, ++ 185, 4, 55, 95, 69, 247, 211, 32, 224, 217, 248, 8, 16, 64, 70, 255, ++ 247, 142, 251, 123, 136, 249, 136, 3, 235, 67, 2, 130, 24, 203, 26, ++ 15, 224, 17, 120, 80, 120, 9, 2, 9, 24, 37, 104, 14, 185, 144, 120, ++ 0, 224, 8, 70, 133, 66, 3, 209, 6, 177, 145, 120, 33, 96, 5, 224, 3, ++ 50, 19, 241, 255, 51, 236, 210, 79, 240, 1, 10, 80, 70, 189, 232, 248, ++ 143, 2, 74, 3, 75, 1, 33, 26, 96, 255, 247, 126, 189, 166, 58, 4, 0, ++ 216, 115, 4, 0, 0, 33, 255, 247, 119, 189, 24, 177, 0, 35, 3, 96, 24, ++ 70, 112, 71, 1, 32, 112, 71, 56, 177, 0, 35, 127, 34, 3, 96, 131, 96, ++ 66, 96, 195, 96, 24, 70, 112, 71, 1, 32, 112, 71, 45, 233, 247, 79, ++ 14, 70, 20, 70, 5, 70, 0, 40, 98, 208, 0, 41, 96, 208, 0, 42, 94, 208, ++ 0, 104, 16, 185, 0, 144, 1, 144, 6, 224, 105, 70, 1, 170, 255, 247, ++ 70, 251, 1, 155, 1, 51, 1, 147, 0, 152, 40, 33, 255, 247, 38, 251, 24, ++ 177, 1, 153, 3, 104, 153, 66, 10, 219, 0, 155, 19, 185, 1, 34, 0, 146, ++ 240, 231, 0, 177, 0, 104, 1, 144, 79, 240, 255, 52, 56, 224, 0, 152, ++ 255, 247, 124, 254, 128, 70, 65, 70, 0, 152, 255, 247, 108, 254, 7, ++ 70, 0, 40, 221, 209, 0, 155, 1, 43, 34, 209, 255, 247, 250, 250, 3, ++ 104, 243, 177, 40, 33, 56, 70, 255, 247, 0, 251, 57, 70, 130, 70, 56, ++ 70, 255, 247, 100, 254, 129, 70, 56, 70, 255, 247, 235, 250, 208, 248, ++ 48, 176, 6, 224, 64, 70, 73, 70, 255, 247, 168, 253, 40, 185, 1, 55, ++ 217, 68, 218, 248, 0, 48, 159, 66, 244, 219, 218, 248, 0, 48, 159, 66, ++ 183, 219, 48, 70, 65, 70, 255, 247, 187, 253, 152, 248, 2, 48, 35, 96, ++ 0, 36, 40, 70, 157, 232, 6, 0, 255, 247, 251, 250, 0, 224, 1, 36, 32, ++ 70, 189, 232, 254, 143, 127, 181, 12, 70, 1, 144, 21, 70, 48, 179, 42, ++ 179, 1, 168, 255, 247, 170, 253, 3, 168, 1, 153, 255, 247, 160, 253, ++ 3, 169, 0, 32, 2, 170, 141, 248, 14, 64, 255, 247, 60, 254, 1, 70, 64, ++ 185, 3, 169, 1, 32, 2, 170, 255, 247, 53, 254, 1, 70, 128, 177, 1, 38, ++ 0, 224, 0, 38, 48, 70, 255, 247, 14, 254, 4, 70, 64, 185, 40, 70, 49, ++ 70, 2, 154, 255, 247, 204, 250, 32, 70, 3, 224, 1, 32, 1, 224, 79, 240, ++ 255, 48, 4, 176, 112, 189, 0, 0, 45, 233, 243, 71, 14, 70, 0, 41, 75, ++ 208, 105, 70, 1, 170, 255, 247, 176, 250, 0, 152, 40, 33, 255, 247, ++ 147, 250, 0, 40, 67, 208, 1, 153, 3, 104, 153, 66, 63, 210, 0, 152, ++ 255, 247, 243, 253, 0, 36, 128, 70, 37, 70, 223, 248, 124, 160, 0, 159, ++ 10, 235, 4, 3, 211, 248, 4, 144, 56, 70, 74, 70, 65, 70, 255, 247, 182, ++ 253, 64, 242, 254, 51, 152, 66, 2, 70, 17, 209, 53, 185, 42, 70, 1, ++ 32, 65, 70, 255, 247, 237, 253, 5, 70, 48, 177, 74, 70, 1, 32, 41, 70, ++ 255, 247, 164, 253, 2, 70, 1, 224, 64, 242, 255, 50, 1, 39, 90, 248, ++ 4, 0, 57, 70, 48, 24, 8, 52, 255, 247, 128, 250, 32, 44, 211, 209, 0, ++ 152, 255, 247, 76, 250, 195, 106, 11, 177, 152, 248, 8, 48, 51, 116, ++ 0, 155, 0, 32, 115, 116, 3, 224, 1, 32, 1, 224, 79, 240, 255, 48, 189, ++ 232, 252, 135, 0, 191, 248, 58, 4, 0, 112, 181, 22, 70, 148, 176, 29, ++ 70, 0, 40, 61, 208, 1, 41, 59, 216, 11, 185, 18, 185, 54, 224, 2, 185, ++ 13, 174, 2, 170, 255, 247, 109, 250, 0, 40, 49, 208, 2, 156, 236, 177, ++ 7, 155, 34, 120, 0, 147, 3, 155, 48, 70, 5, 153, 27, 104, 255, 247, ++ 135, 251, 2, 155, 40, 70, 154, 120, 7, 155, 6, 153, 0, 147, 3, 155, ++ 27, 104, 255, 247, 125, 251, 237, 177, 0, 35, 241, 92, 234, 92, 10, ++ 64, 234, 84, 1, 51, 25, 43, 248, 209, 0, 32, 20, 224, 48, 70, 33, 70, ++ 34, 70, 35, 70, 0, 148, 255, 247, 107, 251, 40, 70, 33, 70, 34, 70, ++ 35, 70, 0, 148, 255, 247, 100, 251, 32, 70, 4, 224, 16, 70, 2, 224, ++ 1, 32, 0, 224, 40, 70, 20, 176, 112, 189, 0, 0, 45, 233, 240, 79, 14, ++ 70, 157, 176, 20, 70, 5, 70, 0, 40, 0, 240, 234, 128, 0, 42, 0, 240, ++ 231, 128, 1, 41, 0, 242, 228, 128, 79, 240, 102, 67, 19, 96, 6, 170, ++ 255, 247, 30, 250, 0, 40, 0, 240, 219, 128, 6, 155, 235, 177, 90, 120, ++ 2, 240, 3, 2, 1, 42, 2, 208, 2, 42, 8, 209, 3, 224, 34, 104, 66, 240, ++ 1, 2, 2, 224, 34, 104, 66, 240, 2, 2, 34, 96, 90, 120, 81, 7, 3, 213, ++ 34, 104, 66, 240, 4, 2, 34, 96, 218, 28, 6, 146, 219, 120, 2, 235, 67, ++ 2, 1, 50, 6, 146, 40, 70, 0, 46, 20, 191, 3, 33, 2, 33, 17, 170, 255, ++ 247, 243, 249, 0, 40, 0, 240, 176, 128, 0, 39, 171, 70, 7, 241, 24, ++ 1, 104, 70, 11, 88, 0, 43, 0, 240, 138, 128, 186, 70, 30, 120, 6, 240, ++ 73, 5, 1, 45, 9, 208, 8, 45, 10, 208, 72, 45, 11, 208, 9, 45, 12, 191, ++ 79, 240, 128, 101, 0, 37, 7, 224, 79, 240, 128, 69, 4, 224, 79, 240, ++ 0, 69, 1, 224, 79, 240, 0, 117, 6, 240, 48, 2, 18, 17, 208, 28, 2, 144, ++ 26, 177, 34, 104, 66, 240, 16, 2, 34, 96, 90, 120, 2, 51, 3, 146, 67, ++ 74, 4, 147, 18, 104, 6, 240, 73, 3, 211, 92, 198, 243, 64, 9, 155, 0, ++ 5, 147, 3, 155, 4, 159, 3, 241, 255, 56, 73, 224, 28, 168, 0, 235, 10, ++ 3, 83, 248, 80, 60, 5, 154, 185, 120, 152, 88, 255, 247, 161, 249, 59, ++ 120, 1, 120, 128, 43, 55, 208, 29, 177, 35, 104, 35, 234, 5, 5, 37, ++ 96, 65, 24, 90, 70, 5, 70, 179, 70, 14, 70, 39, 224, 21, 248, 1, 31, ++ 0, 146, 1, 145, 255, 247, 89, 249, 1, 153, 0, 154, 139, 8, 195, 92, ++ 1, 240, 3, 1, 73, 0, 83, 250, 1, 241, 1, 240, 3, 1, 1, 41, 9, 208, 2, ++ 41, 14, 208, 137, 185, 185, 241, 0, 15, 14, 208, 35, 104, 67, 240, 128, ++ 83, 9, 224, 185, 241, 0, 15, 7, 208, 35, 104, 67, 240, 0, 99, 2, 224, ++ 35, 104, 35, 240, 0, 83, 35, 96, 181, 66, 213, 209, 94, 70, 0, 37, 147, ++ 70, 2, 155, 8, 241, 255, 56, 255, 24, 184, 241, 255, 63, 178, 209, 2, ++ 154, 3, 152, 4, 153, 0, 251, 2, 19, 114, 7, 63, 245, 120, 175, 87, 70, ++ 44, 55, 88, 47, 127, 244, 107, 175, 93, 70, 43, 124, 27, 7, 3, 213, ++ 35, 104, 67, 240, 8, 3, 35, 96, 43, 124, 216, 6, 3, 213, 35, 104, 67, ++ 240, 32, 3, 35, 96, 40, 124, 16, 240, 32, 0, 6, 208, 35, 104, 0, 32, ++ 67, 240, 64, 3, 35, 96, 0, 224, 1, 32, 29, 176, 189, 232, 240, 143, ++ 0, 191, 216, 115, 4, 0, 45, 233, 240, 79, 12, 70, 133, 176, 0, 41, 75, ++ 208, 2, 169, 3, 170, 255, 247, 17, 249, 2, 152, 40, 33, 255, 247, 244, ++ 248, 0, 40, 65, 208, 3, 153, 3, 104, 153, 66, 61, 210, 2, 152, 255, ++ 247, 84, 252, 0, 37, 1, 144, 40, 70, 44, 33, 255, 247, 229, 248, 128, ++ 70, 72, 179, 40, 70, 216, 248, 4, 16, 255, 247, 237, 248, 24, 179, 6, ++ 70, 0, 39, 28, 224, 214, 248, 4, 176, 40, 70, 177, 104, 255, 247, 227, ++ 248, 187, 241, 255, 63, 17, 208, 130, 70, 79, 240, 0, 9, 11, 224, 80, ++ 70, 1, 153, 255, 247, 129, 251, 10, 241, 3, 10, 16, 177, 32, 70, 49, ++ 70, 14, 224, 9, 241, 1, 9, 217, 69, 241, 219, 1, 55, 12, 54, 216, 248, ++ 0, 48, 159, 66, 222, 219, 1, 53, 2, 45, 204, 209, 1, 153, 32, 70, 255, ++ 247, 140, 251, 0, 32, 0, 224, 1, 32, 5, 176, 189, 232, 240, 143, 45, ++ 233, 240, 79, 177, 176, 15, 70, 11, 146, 17, 147, 59, 157, 60, 158, ++ 4, 70, 0, 40, 0, 240, 119, 129, 0, 46, 0, 240, 116, 129, 1, 41, 0, 242, ++ 113, 129, 0, 45, 0, 240, 110, 129, 42, 104, 1, 42, 0, 242, 106, 129, ++ 58, 153, 2, 41, 0, 242, 102, 129, 171, 104, 2, 43, 0, 242, 98, 129, ++ 46, 168, 11, 153, 58, 155, 255, 247, 122, 252, 0, 40, 0, 240, 90, 129, ++ 47, 185, 43, 104, 51, 177, 157, 248, 184, 32, 3, 146, 4, 224, 0, 35, ++ 3, 147, 1, 224, 0, 33, 3, 145, 48, 70, 129, 33, 178, 34, 255, 247, 95, ++ 248, 32, 70, 57, 70, 19, 170, 255, 247, 164, 248, 0, 40, 0, 240, 65, ++ 129, 19, 155, 51, 177, 218, 28, 19, 146, 219, 120, 2, 235, 67, 2, 1, ++ 50, 19, 146, 32, 70, 0, 47, 20, 191, 3, 33, 2, 33, 30, 170, 255, 247, ++ 144, 248, 0, 40, 0, 240, 45, 129, 32, 70, 41, 169, 79, 240, 0, 10, 255, ++ 247, 245, 251, 205, 248, 24, 160, 6, 153, 44, 35, 75, 67, 19, 170, 212, ++ 88, 2, 235, 3, 9, 0, 44, 0, 240, 3, 129, 2, 34, 47, 168, 0, 33, 255, ++ 247, 44, 248, 58, 154, 43, 104, 42, 185, 48, 169, 11, 154, 203, 24, ++ 3, 248, 4, 44, 4, 224, 1, 43, 4, 191, 11, 155, 141, 248, 189, 48, 79, ++ 70, 176, 70, 134, 74, 33, 120, 18, 104, 1, 240, 73, 3, 18, 248, 3, 144, ++ 48, 170, 7, 235, 137, 3, 91, 105, 4, 145, 12, 147, 2, 235, 9, 3, 19, ++ 248, 4, 60, 5, 147, 1, 240, 48, 3, 27, 17, 217, 28, 9, 145, 35, 177, ++ 170, 104, 122, 75, 83, 248, 34, 32, 0, 224, 0, 34, 123, 104, 8, 146, ++ 83, 248, 41, 48, 16, 147, 187, 104, 83, 248, 41, 48, 13, 147, 99, 120, ++ 2, 52, 89, 30, 14, 147, 15, 148, 7, 145, 38, 70, 176, 224, 115, 120, ++ 16, 154, 9, 153, 2, 235, 67, 3, 10, 147, 8, 155, 139, 66, 24, 219, 186, ++ 241, 0, 15, 64, 240, 159, 128, 5, 154, 0, 42, 0, 240, 155, 128, 16, ++ 70, 10, 153, 12, 154, 235, 104, 255, 247, 174, 249, 0, 40, 0, 240, 146, ++ 128, 150, 248, 0, 160, 186, 241, 128, 10, 24, 191, 79, 240, 1, 10, 137, ++ 224, 8, 155, 244, 92, 128, 44, 9, 208, 4, 153, 139, 7, 2, 213, 17, 154, ++ 164, 26, 228, 178, 107, 104, 156, 66, 200, 191, 220, 178, 5, 155, 0, ++ 43, 59, 208, 24, 70, 10, 153, 12, 154, 235, 104, 255, 247, 140, 249, ++ 0, 40, 51, 208, 177, 120, 13, 152, 254, 247, 240, 255, 144, 248, 0, ++ 192, 41, 70, 132, 68, 131, 70, 82, 70, 101, 70, 31, 224, 3, 155, 27, ++ 248, 1, 175, 131, 177, 2, 145, 1, 146, 254, 247, 173, 255, 79, 234, ++ 154, 3, 192, 92, 10, 240, 3, 3, 91, 0, 80, 250, 3, 243, 19, 240, 3, ++ 15, 2, 153, 1, 154, 10, 208, 24, 249, 10, 48, 19, 241, 127, 15, 3, 208, ++ 163, 66, 3, 221, 128, 51, 1, 208, 8, 248, 10, 64, 171, 69, 221, 209, ++ 146, 70, 13, 70, 128, 44, 24, 191, 79, 240, 1, 10, 3, 153, 0, 41, 57, ++ 208, 185, 241, 0, 15, 54, 209, 8, 70, 122, 105, 10, 153, 75, 70, 255, ++ 247, 74, 249, 0, 40, 46, 208, 177, 120, 13, 152, 254, 247, 174, 255, ++ 1, 120, 172, 70, 9, 24, 131, 70, 82, 70, 13, 70, 31, 224, 27, 248, 1, ++ 175, 1, 146, 205, 248, 8, 192, 254, 247, 109, 255, 79, 234, 154, 3, ++ 192, 92, 10, 240, 3, 3, 91, 0, 80, 250, 3, 243, 19, 240, 3, 15, 1, 154, ++ 221, 248, 8, 192, 10, 209, 24, 249, 10, 48, 19, 241, 127, 15, 3, 208, ++ 163, 66, 3, 221, 128, 51, 1, 208, 8, 248, 10, 64, 171, 69, 221, 209, ++ 146, 70, 101, 70, 7, 155, 9, 154, 1, 59, 182, 24, 7, 147, 7, 153, 1, ++ 49, 127, 244, 75, 175, 9, 154, 14, 155, 15, 153, 3, 251, 2, 20, 4, 154, ++ 80, 7, 63, 245, 19, 175, 70, 70, 6, 155, 1, 51, 2, 43, 6, 147, 127, ++ 244, 237, 174, 186, 241, 0, 15, 16, 208, 6, 241, 178, 3, 22, 248, 1, ++ 43, 130, 240, 128, 2, 1, 42, 2, 216, 128, 34, 6, 248, 1, 44, 179, 66, ++ 244, 216, 0, 32, 3, 224, 1, 32, 1, 224, 79, 240, 255, 48, 49, 176, 189, ++ 232, 240, 143, 216, 115, 4, 0, 28, 58, 4, 0, 45, 233, 240, 79, 139, ++ 70, 161, 176, 146, 70, 4, 70, 0, 40, 0, 240, 168, 128, 0, 41, 0, 240, ++ 165, 128, 0, 42, 0, 240, 162, 128, 8, 70, 25, 34, 0, 33, 254, 247, 247, ++ 254, 80, 70, 0, 33, 25, 34, 254, 247, 242, 254, 32, 70, 1, 33, 10, 170, ++ 254, 247, 55, 255, 0, 40, 0, 240, 144, 128, 10, 155, 51, 177, 218, 28, ++ 10, 146, 219, 120, 2, 235, 67, 2, 1, 50, 10, 146, 32, 70, 3, 33, 21, ++ 170, 254, 247, 38, 255, 0, 40, 127, 208, 79, 240, 0, 9, 44, 35, 3, 251, ++ 9, 243, 10, 168, 0, 235, 3, 8, 195, 88, 0, 43, 109, 208, 71, 70, 205, ++ 248, 36, 144, 25, 120, 185, 70, 1, 240, 73, 2, 1, 145, 56, 73, 1, 152, ++ 9, 104, 142, 92, 90, 120, 2, 51, 4, 147, 0, 240, 48, 3, 27, 17, 3, 51, ++ 5, 147, 123, 104, 221, 248, 16, 128, 83, 248, 38, 48, 0, 46, 20, 191, ++ 81, 70, 89, 70, 7, 147, 7, 235, 134, 3, 91, 105, 2, 241, 255, 60, 6, ++ 147, 51, 70, 103, 70, 70, 70, 220, 70, 3, 146, 2, 145, 211, 70, 152, ++ 70, 50, 224, 115, 120, 7, 154, 2, 235, 67, 3, 8, 147, 9, 235, 136, 3, ++ 91, 105, 93, 104, 51, 120, 128, 43, 35, 208, 6, 155, 211, 248, 0, 160, ++ 28, 224, 44, 120, 22, 224, 156, 177, 32, 70, 8, 153, 6, 154, 0, 35, ++ 205, 248, 0, 192, 255, 247, 95, 248, 221, 248, 0, 192, 64, 177, 4, 240, ++ 7, 2, 1, 33, 145, 64, 2, 152, 227, 16, 194, 92, 10, 67, 194, 84, 171, ++ 120, 228, 24, 107, 120, 156, 66, 229, 221, 3, 53, 26, 241, 255, 58, ++ 223, 210, 5, 153, 1, 63, 118, 24, 121, 28, 202, 209, 3, 168, 7, 200, ++ 0, 251, 2, 19, 1, 154, 218, 70, 82, 7, 79, 70, 227, 70, 150, 212, 221, ++ 248, 36, 144, 9, 241, 1, 9, 185, 241, 2, 15, 131, 209, 0, 32, 0, 224, ++ 1, 32, 33, 176, 189, 232, 240, 143, 0, 191, 216, 115, 4, 0, 45, 233, ++ 240, 67, 23, 70, 141, 176, 30, 70, 32, 179, 1, 41, 34, 216, 11, 179, ++ 1, 170, 254, 247, 145, 254, 232, 177, 1, 155, 219, 177, 2, 154, 220, ++ 120, 210, 248, 0, 128, 221, 248, 24, 144, 29, 29, 1, 60, 14, 224, 105, ++ 120, 56, 70, 8, 235, 65, 1, 74, 70, 0, 35, 255, 247, 11, 248, 1, 60, ++ 24, 177, 43, 120, 0, 32, 51, 96, 5, 224, 2, 53, 96, 28, 238, 209, 32, ++ 70, 0, 224, 1, 32, 13, 176, 189, 232, 240, 131, 48, 181, 133, 176, 1, ++ 144, 13, 70, 20, 70, 8, 179, 2, 179, 1, 168, 255, 247, 13, 249, 3, 168, ++ 1, 153, 255, 247, 3, 249, 0, 32, 3, 169, 2, 170, 141, 248, 14, 80, 255, ++ 247, 12, 249, 56, 185, 1, 32, 3, 169, 2, 170, 255, 247, 6, 249, 104, ++ 177, 1, 33, 0, 224, 0, 33, 64, 104, 67, 28, 9, 208, 32, 70, 2, 154, ++ 254, 247, 52, 254, 0, 32, 3, 224, 1, 32, 1, 224, 79, 240, 255, 48, 5, ++ 176, 48, 189, 48, 181, 133, 176, 4, 70, 1, 145, 21, 70, 0, 41, 47, 208, ++ 0, 42, 45, 208, 1, 168, 255, 247, 221, 248, 32, 70, 3, 170, 2, 169, ++ 254, 247, 17, 254, 48, 33, 2, 152, 254, 247, 244, 253, 3, 70, 89, 104, ++ 2, 152, 254, 247, 254, 253, 3, 155, 12, 36, 4, 251, 3, 4, 1, 154, 2, ++ 152, 33, 70, 255, 247, 4, 249, 2, 70, 40, 177, 131, 120, 255, 43, 16, ++ 208, 43, 96, 0, 32, 15, 224, 2, 155, 1, 43, 10, 208, 1, 32, 33, 70, ++ 2, 144, 255, 247, 192, 248, 4, 70, 0, 40, 231, 209, 1, 224, 1, 32, 1, ++ 224, 79, 240, 255, 48, 5, 176, 48, 189, 1, 32, 255, 247, 3, 186, 0, ++ 0, 248, 181, 5, 70, 15, 70, 81, 177, 2, 41, 10, 209, 0, 32, 254, 247, ++ 179, 253, 6, 104, 214, 241, 1, 6, 56, 191, 0, 38, 2, 224, 1, 38, 0, ++ 224, 0, 38, 48, 70, 254, 247, 167, 253, 2, 47, 66, 107, 45, 216, 3, ++ 104, 75, 179, 4, 45, 41, 216, 223, 232, 5, 240, 3, 6, 9, 12, 20, 0, ++ 2, 241, 14, 4, 22, 224, 2, 241, 34, 4, 19, 224, 2, 241, 52, 4, 16, 224, ++ 92, 107, 20, 240, 2, 4, 24, 208, 2, 241, 82, 4, 12, 73, 9, 224, 92, ++ 107, 20, 240, 64, 4, 16, 208, 48, 70, 25, 110, 254, 247, 157, 253, 4, ++ 70, 8, 73, 76, 177, 32, 70, 254, 247, 88, 253, 0, 40, 8, 191, 0, 36, ++ 2, 224, 28, 70, 0, 224, 0, 36, 32, 70, 248, 189, 0, 191, 246, 203, 135, ++ 0, 60, 199, 136, 0, 112, 181, 13, 70, 20, 70, 255, 247, 52, 250, 33, ++ 70, 3, 70, 0, 34, 40, 70, 189, 232, 112, 64, 255, 247, 179, 185, 55, ++ 181, 2, 171, 67, 248, 4, 29, 5, 70, 20, 70, 25, 70, 1, 34, 0, 35, 255, ++ 247, 168, 249, 40, 70, 1, 153, 34, 70, 255, 247, 138, 250, 62, 189, ++ 55, 181, 2, 171, 67, 248, 4, 29, 5, 70, 20, 70, 25, 70, 1, 34, 0, 35, ++ 255, 247, 151, 249, 40, 70, 1, 153, 34, 70, 255, 247, 21, 255, 62, 189, ++ 112, 181, 13, 70, 20, 70, 255, 247, 61, 255, 33, 70, 3, 70, 0, 34, 40, ++ 70, 189, 232, 112, 64, 255, 247, 132, 185, 45, 233, 240, 79, 137, 176, ++ 221, 248, 76, 144, 0, 35, 20, 172, 185, 241, 3, 15, 130, 70, 144, 70, ++ 18, 158, 148, 232, 144, 8, 5, 104, 1, 147, 2, 147, 12, 217, 4, 34, 1, ++ 168, 49, 70, 217, 247, 11, 248, 185, 241, 7, 15, 4, 217, 2, 168, 49, ++ 29, 4, 34, 217, 247, 3, 248, 184, 241, 1, 15, 50, 208, 4, 211, 184, ++ 241, 6, 15, 64, 240, 203, 128, 159, 224, 213, 248, 92, 1, 37, 240, 218, ++ 221, 218, 243, 40, 244, 8, 63, 1, 48, 135, 66, 192, 240, 194, 128, 213, ++ 248, 92, 1, 37, 240, 209, 221, 0, 38, 1, 70, 3, 34, 32, 70, 218, 243, ++ 69, 244, 230, 112, 213, 248, 92, 1, 37, 240, 6, 222, 96, 96, 213, 248, ++ 92, 1, 37, 240, 191, 221, 7, 70, 213, 248, 92, 1, 37, 240, 186, 221, ++ 218, 243, 8, 244, 57, 70, 66, 28, 4, 241, 8, 0, 218, 243, 46, 244, 161, ++ 224, 32, 70, 82, 73, 218, 243, 213, 243, 176, 185, 4, 241, 8, 1, 4, ++ 34, 5, 168, 216, 247, 194, 255, 163, 121, 98, 121, 27, 4, 67, 234, 2, ++ 35, 34, 121, 213, 248, 92, 1, 19, 67, 226, 121, 5, 169, 67, 234, 2, ++ 98, 254, 247, 115, 248, 6, 70, 133, 224, 0, 33, 4, 34, 3, 168, 218, ++ 243, 44, 243, 33, 70, 3, 47, 180, 191, 58, 70, 3, 34, 3, 168, 218, 243, ++ 4, 244, 3, 169, 4, 34, 4, 168, 216, 247, 159, 255, 3, 168, 4, 33, 38, ++ 240, 181, 223, 6, 70, 0, 40, 108, 209, 11, 47, 16, 221, 167, 121, 99, ++ 121, 63, 4, 71, 234, 3, 39, 35, 121, 5, 168, 31, 67, 227, 121, 4, 241, ++ 8, 1, 4, 34, 71, 234, 3, 103, 216, 247, 134, 255, 3, 224, 141, 248, ++ 20, 0, 79, 240, 255, 55, 5, 168, 4, 33, 38, 240, 151, 223, 6, 70, 0, ++ 40, 78, 209, 157, 248, 20, 48, 213, 248, 92, 1, 27, 185, 3, 169, 38, ++ 240, 46, 220, 3, 224, 5, 169, 58, 70, 38, 240, 45, 220, 6, 70, 0, 40, ++ 62, 209, 40, 70, 3, 240, 203, 218, 10, 241, 4, 0, 4, 169, 4, 34, 216, ++ 247, 97, 255, 213, 248, 136, 1, 0, 40, 49, 208, 7, 240, 167, 220, 46, ++ 224, 0, 33, 4, 34, 5, 168, 218, 243, 213, 242, 5, 168, 49, 70, 3, 34, ++ 218, 243, 176, 243, 0, 35, 35, 96, 6, 168, 255, 247, 20, 249, 16, 224, ++ 4, 168, 5, 169, 2, 34, 218, 243, 129, 243, 80, 185, 35, 104, 11, 241, ++ 255, 50, 147, 66, 5, 210, 7, 153, 4, 235, 131, 2, 1, 51, 81, 96, 35, ++ 96, 6, 168, 4, 169, 7, 170, 255, 247, 214, 254, 0, 40, 231, 208, 0, ++ 38, 4, 224, 111, 240, 22, 6, 1, 224, 111, 240, 13, 6, 48, 70, 9, 176, ++ 189, 232, 240, 143, 0, 191, 105, 86, 136, 0, 45, 233, 240, 65, 4, 104, ++ 138, 176, 212, 248, 124, 129, 5, 70, 216, 248, 4, 48, 212, 248, 168, ++ 116, 198, 88, 35, 104, 27, 126, 0, 43, 0, 240, 229, 128, 32, 105, 42, ++ 240, 58, 221, 3, 70, 24, 177, 160, 104, 227, 247, 254, 251, 219, 224, ++ 143, 179, 215, 248, 248, 32, 146, 104, 22, 58, 1, 42, 43, 216, 2, 34, ++ 212, 248, 116, 1, 57, 70, 8, 240, 29, 216, 1, 33, 79, 240, 255, 51, ++ 32, 70, 58, 70, 42, 240, 250, 220, 215, 248, 248, 48, 155, 104, 22, ++ 43, 10, 209, 212, 248, 208, 36, 212, 248, 204, 52, 2, 50, 56, 70, 83, ++ 248, 34, 16, 248, 247, 81, 251, 183, 224, 215, 248, 240, 48, 1, 33, ++ 147, 249, 52, 48, 56, 70, 211, 241, 1, 3, 7, 241, 188, 2, 56, 191, 0, ++ 35, 249, 247, 126, 252, 168, 224, 171, 121, 3, 179, 115, 122, 1, 43, ++ 29, 209, 212, 248, 36, 1, 7, 169, 42, 70, 65, 240, 184, 217, 15, 224, ++ 2, 125, 216, 248, 8, 48, 210, 7, 195, 88, 9, 212, 144, 248, 36, 32, ++ 151, 7, 5, 213, 208, 248, 168, 113, 23, 185, 27, 120, 2, 43, 7, 209, ++ 212, 248, 36, 1, 7, 169, 19, 240, 74, 254, 0, 40, 232, 209, 1, 39, 171, ++ 121, 0, 43, 43, 208, 115, 122, 1, 43, 44, 209, 40, 70, 241, 136, 252, ++ 243, 181, 241, 212, 248, 116, 1, 41, 70, 2, 34, 0, 35, 7, 240, 194, ++ 223, 212, 248, 36, 1, 7, 169, 42, 70, 65, 240, 136, 217, 14, 224, 216, ++ 248, 8, 48, 194, 88, 3, 125, 217, 7, 8, 212, 144, 248, 36, 48, 155, ++ 7, 4, 213, 208, 248, 168, 49, 11, 185, 19, 112, 83, 112, 212, 248, 36, ++ 1, 7, 169, 19, 240, 27, 254, 0, 40, 233, 209, 24, 224, 115, 121, 11, ++ 177, 51, 105, 163, 177, 212, 248, 116, 1, 41, 70, 7, 240, 125, 223, ++ 128, 7, 13, 213, 171, 121, 3, 185, 51, 97, 40, 70, 241, 136, 252, 243, ++ 126, 241, 212, 248, 116, 1, 41, 70, 2, 34, 0, 35, 7, 240, 139, 223, ++ 171, 121, 59, 179, 115, 122, 1, 43, 36, 209, 31, 187, 212, 248, 116, ++ 1, 41, 70, 2, 34, 59, 70, 7, 240, 126, 223, 212, 248, 36, 1, 7, 169, ++ 42, 70, 65, 240, 68, 217, 14, 224, 216, 248, 8, 48, 194, 88, 3, 125, ++ 217, 7, 8, 212, 144, 248, 36, 48, 155, 7, 4, 213, 208, 248, 168, 49, ++ 11, 185, 19, 112, 83, 112, 212, 248, 36, 1, 7, 169, 19, 240, 215, 253, ++ 0, 40, 233, 209, 171, 121, 3, 177, 103, 177, 50, 29, 3, 146, 1, 34, ++ 0, 35, 4, 146, 32, 70, 41, 70, 80, 34, 0, 147, 1, 147, 2, 147, 251, ++ 243, 63, 243, 0, 35, 115, 113, 51, 113, 10, 176, 189, 232, 240, 129, ++ 0, 0, 45, 233, 240, 79, 135, 176, 31, 70, 16, 155, 7, 241, 2, 9, 163, ++ 241, 2, 8, 208, 248, 0, 160, 6, 70, 12, 70, 147, 70, 72, 70, 37, 34, ++ 65, 70, 3, 147, 223, 247, 0, 255, 218, 248, 0, 32, 5, 70, 3, 155, 16, ++ 177, 65, 120, 2, 41, 10, 216, 210, 248, 136, 32, 80, 70, 17, 111, 1, ++ 49, 17, 103, 89, 70, 58, 70, 3, 240, 72, 223, 70, 224, 146, 248, 79, ++ 112, 23, 240, 3, 7, 30, 208, 72, 70, 65, 70, 62, 34, 223, 247, 227, ++ 254, 32, 177, 67, 120, 1, 43, 1, 209, 135, 120, 19, 224, 53, 34, 6, ++ 171, 3, 248, 1, 45, 1, 34, 0, 146, 72, 70, 65, 70, 25, 74, 218, 243, ++ 110, 244, 32, 177, 67, 120, 5, 43, 3, 209, 135, 121, 2, 224, 7, 70, ++ 0, 224, 0, 39, 163, 121, 3, 187, 35, 122, 243, 177, 11, 241, 16, 0, ++ 4, 241, 188, 1, 6, 34, 216, 247, 193, 253, 129, 70, 168, 185, 115, 104, ++ 80, 70, 84, 248, 3, 128, 171, 120, 58, 70, 136, 248, 4, 48, 43, 121, ++ 136, 248, 5, 48, 233, 120, 0, 240, 126, 222, 136, 248, 8, 144, 168, ++ 248, 6, 0, 33, 70, 48, 70, 39, 240, 132, 216, 7, 176, 189, 232, 240, ++ 143, 0, 191, 98, 21, 4, 0, 45, 233, 240, 65, 67, 104, 6, 104, 205, 88, ++ 209, 248, 244, 112, 108, 121, 60, 185, 150, 248, 116, 50, 35, 240, 2, ++ 3, 134, 248, 116, 50, 189, 232, 240, 129, 1, 60, 228, 178, 108, 113, ++ 116, 185, 41, 104, 176, 104, 239, 243, 129, 245, 250, 141, 176, 104, ++ 41, 104, 9, 42, 136, 191, 10, 34, 35, 70, 189, 232, 240, 65, 239, 243, ++ 80, 181, 189, 232, 240, 129, 45, 233, 240, 65, 152, 70, 67, 104, 5, ++ 104, 7, 70, 203, 88, 16, 104, 22, 70, 88, 96, 146, 136, 56, 70, 26, ++ 129, 12, 70, 39, 240, 136, 221, 184, 241, 0, 15, 4, 208, 32, 70, 113, ++ 136, 252, 243, 133, 240, 12, 224, 3, 34, 19, 70, 213, 248, 116, 1, 33, ++ 70, 7, 240, 145, 222, 149, 248, 116, 50, 67, 240, 2, 3, 133, 248, 116, ++ 50, 40, 70, 33, 70, 251, 243, 145, 243, 40, 70, 33, 70, 1, 34, 189, ++ 232, 240, 65, 251, 243, 210, 179, 3, 104, 2, 70, 112, 181, 24, 70, 11, ++ 179, 1, 120, 16, 76, 3, 70, 101, 92, 1, 48, 173, 6, 1, 212, 33, 185, ++ 1, 224, 0, 41, 244, 209, 0, 32, 0, 224, 24, 70, 29, 70, 19, 248, 1, ++ 27, 102, 92, 22, 240, 32, 15, 1, 208, 25, 185, 7, 224, 0, 41, 244, 209, ++ 4, 224, 43, 70, 0, 33, 3, 248, 1, 27, 0, 224, 0, 35, 19, 96, 112, 189, ++ 112, 189, 22, 119, 135, 0, 248, 181, 12, 70, 23, 70, 208, 248, 180, ++ 98, 111, 240, 22, 5, 18, 224, 32, 70, 49, 104, 218, 243, 54, 241, 96, ++ 185, 115, 104, 176, 104, 57, 70, 152, 71, 123, 104, 21, 241, 23, 15, ++ 8, 191, 0, 37, 51, 177, 0, 40, 24, 191, 5, 70, 246, 104, 0, 46, 234, ++ 209, 1, 224, 111, 240, 13, 5, 40, 70, 248, 189, 240, 181, 135, 176, ++ 12, 70, 22, 70, 25, 70, 5, 70, 12, 154, 1, 168, 218, 243, 236, 242, ++ 166, 25, 35, 70, 179, 66, 26, 70, 65, 208, 17, 120, 1, 51, 0, 41, 248, ++ 209, 68, 224, 33, 70, 50, 70, 6, 174, 216, 247, 251, 252, 70, 248, 4, ++ 125, 48, 70, 255, 247, 150, 255, 4, 70, 48, 70, 255, 247, 146, 255, ++ 6, 70, 4, 179, 32, 177, 1, 168, 29, 73, 34, 70, 218, 243, 226, 242, ++ 33, 70, 40, 70, 1, 170, 255, 247, 175, 255, 4, 70, 152, 185, 14, 224, ++ 23, 73, 50, 70, 1, 168, 218, 243, 213, 242, 40, 70, 49, 70, 1, 170, ++ 255, 247, 162, 255, 48, 185, 5, 168, 255, 247, 116, 255, 6, 70, 0, 46, ++ 238, 209, 0, 224, 4, 70, 56, 70, 225, 247, 105, 252, 3, 155, 1, 154, ++ 147, 66, 9, 209, 2, 154, 58, 177, 0, 34, 26, 112, 4, 224, 111, 240, ++ 1, 4, 1, 224, 111, 240, 26, 4, 32, 70, 7, 176, 240, 189, 22, 27, 1, ++ 54, 48, 70, 225, 247, 80, 252, 7, 70, 0, 40, 178, 209, 241, 231, 204, ++ 60, 4, 0, 45, 233, 255, 65, 11, 158, 0, 35, 3, 46, 128, 70, 20, 70, ++ 10, 159, 12, 157, 3, 147, 4, 217, 3, 168, 57, 70, 4, 34, 216, 247, 160, ++ 252, 64, 70, 15, 153, 252, 247, 10, 254, 124, 185, 10, 75, 27, 104, ++ 219, 3, 2, 213, 44, 112, 32, 70, 10, 224, 13, 155, 64, 70, 0, 147, 57, ++ 70, 50, 70, 43, 70, 255, 247, 120, 255, 1, 224, 111, 240, 22, 0, 4, ++ 176, 189, 232, 240, 129, 8, 7, 0, 0, 56, 181, 139, 120, 28, 29, 162, ++ 66, 48, 211, 10, 120, 1, 42, 48, 209, 19, 43, 52, 191, 26, 70, 19, 34, ++ 75, 120, 2, 43, 4, 208, 3, 43, 30, 208, 1, 43, 40, 209, 1, 224, 0, 35, ++ 21, 224, 0, 35, 7, 224, 204, 24, 37, 121, 144, 248, 35, 64, 1, 51, 44, ++ 67, 128, 248, 35, 64, 1, 48, 147, 66, 244, 219, 15, 224, 204, 24, 37, ++ 121, 144, 248, 35, 64, 1, 51, 44, 64, 128, 248, 35, 64, 1, 48, 147, ++ 66, 244, 219, 3, 224, 36, 48, 4, 49, 216, 247, 80, 252, 0, 32, 56, 189, ++ 111, 240, 13, 0, 56, 189, 111, 240, 36, 0, 56, 189, 0, 32, 56, 189, ++ 56, 181, 4, 70, 16, 70, 138, 120, 21, 29, 171, 66, 15, 211, 11, 120, ++ 1, 43, 15, 209, 19, 42, 40, 191, 19, 34, 19, 35, 130, 112, 195, 112, ++ 4, 241, 36, 1, 4, 48, 216, 247, 49, 252, 0, 32, 56, 189, 111, 240, 13, ++ 0, 56, 189, 111, 240, 36, 0, 56, 189, 8, 181, 0, 241, 36, 3, 16, 34, ++ 8, 70, 25, 70, 216, 247, 33, 252, 0, 32, 8, 189, 56, 181, 16, 34, 4, ++ 70, 36, 48, 216, 247, 25, 252, 44, 33, 32, 70, 165, 104, 39, 240, 34, ++ 223, 2, 28, 24, 191, 1, 34, 40, 70, 1, 33, 232, 247, 144, 250, 0, 32, ++ 56, 189, 0, 0, 45, 233, 240, 79, 133, 176, 155, 70, 16, 157, 14, 155, ++ 4, 70, 14, 70, 145, 70, 3, 147, 15, 159, 208, 248, 8, 128, 245, 185, ++ 216, 248, 4, 16, 7, 245, 140, 114, 115, 104, 39, 240, 255, 221, 5, 70, ++ 56, 185, 32, 70, 49, 70, 42, 70, 5, 176, 189, 232, 240, 79, 39, 240, ++ 157, 157, 32, 70, 49, 70, 1, 34, 39, 240, 152, 221, 171, 104, 79, 240, ++ 1, 10, 206, 51, 171, 96, 171, 137, 206, 59, 171, 129, 1, 224, 79, 240, ++ 0, 10, 172, 104, 73, 70, 6, 34, 4, 241, 6, 9, 32, 70, 216, 247, 211, ++ 251, 89, 70, 6, 34, 72, 70, 216, 247, 206, 251, 72, 70, 33, 70, 6, 34, ++ 216, 247, 182, 251, 24, 185, 163, 121, 131, 240, 2, 3, 163, 113, 111, ++ 240, 119, 3, 35, 115, 108, 35, 79, 240, 0, 9, 99, 115, 79, 240, 1, 11, ++ 111, 240, 127, 3, 163, 115, 37, 73, 3, 34, 132, 248, 15, 176, 132, 248, ++ 18, 144, 4, 241, 19, 0, 216, 247, 174, 251, 7, 241, 56, 3, 155, 178, ++ 26, 10, 66, 234, 3, 35, 35, 130, 132, 248, 22, 144, 132, 248, 23, 176, ++ 4, 241, 24, 1, 186, 241, 0, 15, 5, 208, 141, 232, 128, 2, 64, 70, 50, ++ 70, 3, 155, 6, 224, 205, 248, 0, 160, 205, 248, 4, 160, 64, 70, 50, ++ 70, 83, 70, 39, 240, 247, 219, 79, 240, 0, 9, 7, 241, 74, 3, 72, 52, ++ 171, 129, 4, 248, 7, 144, 228, 25, 64, 70, 41, 70, 132, 248, 1, 144, ++ 39, 240, 50, 220, 113, 107, 64, 70, 252, 247, 234, 252, 115, 107, 1, ++ 70, 26, 121, 64, 70, 2, 42, 12, 191, 26, 105, 74, 70, 43, 70, 4, 240, ++ 231, 217, 0, 32, 5, 176, 189, 232, 240, 143, 0, 191, 102, 21, 4, 0, ++ 151, 41, 112, 181, 4, 70, 13, 70, 22, 70, 17, 216, 36, 48, 18, 177, ++ 219, 243, 170, 240, 1, 224, 218, 243, 37, 245, 44, 45, 11, 209, 1, 33, ++ 50, 28, 160, 104, 24, 191, 1, 34, 232, 247, 215, 249, 0, 32, 112, 189, ++ 79, 240, 255, 48, 112, 189, 0, 32, 112, 189, 3, 104, 16, 181, 203, 88, ++ 131, 177, 130, 138, 156, 24, 148, 248, 97, 16, 1, 41, 10, 209, 152, ++ 88, 161, 105, 23, 240, 147, 251, 225, 105, 0, 35, 203, 128, 163, 97, ++ 227, 97, 132, 248, 97, 48, 16, 189, 56, 181, 133, 105, 4, 70, 101, 177, ++ 232, 104, 8, 177, 225, 247, 204, 250, 168, 104, 8, 177, 225, 247, 200, ++ 250, 160, 105, 225, 247, 197, 250, 0, 35, 163, 97, 224, 105, 24, 177, ++ 225, 247, 191, 250, 0, 35, 227, 97, 56, 189, 112, 181, 5, 70, 12, 70, ++ 40, 240, 134, 217, 6, 70, 128, 177, 144, 248, 97, 48, 155, 185, 131, ++ 105, 35, 185, 212, 32, 222, 243, 156, 244, 176, 97, 48, 177, 243, 105, ++ 83, 185, 232, 32, 222, 243, 149, 244, 240, 97, 40, 185, 40, 70, 33, ++ 70, 189, 232, 112, 64, 39, 240, 93, 159, 112, 189, 240, 181, 3, 104, ++ 135, 176, 205, 88, 0, 45, 47, 208, 134, 138, 171, 25, 46, 208, 156, ++ 105, 3, 171, 0, 147, 5, 171, 1, 147, 0, 32, 2, 170, 4, 171, 66, 240, ++ 221, 221, 2, 152, 4, 153, 48, 34, 223, 247, 210, 251, 7, 70, 240, 177, ++ 224, 104, 8, 177, 225, 247, 127, 250, 120, 120, 2, 48, 224, 128, 225, ++ 247, 119, 250, 224, 96, 152, 177, 57, 70, 226, 136, 216, 247, 215, 250, ++ 168, 89, 4, 241, 60, 1, 32, 34, 0, 240, 251, 218, 48, 35, 163, 130, ++ 16, 35, 35, 131, 2, 35, 99, 131, 1, 224, 40, 70, 0, 224, 1, 32, 7, 176, ++ 240, 189, 2, 104, 112, 181, 140, 88, 100, 177, 134, 138, 40, 240, 142, ++ 216, 165, 25, 169, 105, 17, 177, 160, 89, 23, 240, 12, 251, 235, 105, ++ 11, 177, 0, 34, 218, 128, 112, 189, 11, 121, 19, 185, 9, 104, 255, 247, ++ 233, 191, 112, 71, 45, 233, 240, 71, 20, 70, 2, 104, 5, 70, 136, 88, ++ 14, 70, 0, 40, 64, 208, 175, 138, 83, 43, 7, 68, 215, 248, 24, 160, ++ 54, 217, 99, 120, 2, 51, 83, 43, 50, 217, 120, 107, 8, 177, 225, 247, ++ 51, 250, 96, 120, 2, 48, 56, 134, 225, 247, 43, 250, 120, 99, 16, 185, ++ 56, 134, 189, 232, 240, 135, 33, 70, 58, 142, 216, 247, 136, 250, 123, ++ 107, 183, 248, 48, 128, 3, 241, 84, 9, 168, 241, 84, 8, 65, 70, 1, 34, ++ 72, 70, 223, 247, 102, 251, 65, 70, 248, 99, 3, 34, 72, 70, 223, 247, ++ 96, 251, 184, 99, 96, 177, 251, 107, 107, 177, 4, 241, 20, 1, 10, 241, ++ 28, 0, 32, 34, 216, 247, 107, 250, 40, 70, 49, 70, 40, 240, 149, 221, ++ 1, 32, 189, 232, 240, 135, 1, 32, 189, 232, 240, 135, 3, 104, 45, 233, ++ 240, 65, 206, 88, 128, 70, 12, 70, 0, 46, 46, 208, 177, 248, 90, 48, ++ 135, 138, 91, 4, 41, 213, 209, 248, 236, 48, 2, 43, 3, 209, 189, 232, ++ 240, 65, 40, 240, 128, 154, 245, 25, 149, 248, 97, 48, 19, 185, 255, ++ 247, 129, 255, 1, 224, 40, 240, 19, 216, 33, 70, 64, 70, 255, 247, 63, ++ 255, 33, 70, 64, 70, 40, 240, 241, 216, 64, 70, 33, 70, 4, 241, 188, ++ 2, 41, 240, 71, 216, 149, 248, 97, 48, 59, 185, 171, 105, 180, 248, ++ 90, 64, 242, 89, 163, 248, 206, 64, 235, 105, 26, 96, 189, 232, 240, ++ 129, 3, 137, 32, 43, 9, 208, 3, 216, 59, 177, 16, 43, 15, 209, 4, 224, ++ 48, 43, 2, 208, 128, 43, 10, 209, 2, 224, 3, 104, 219, 105, 4, 224, ++ 66, 104, 3, 104, 146, 121, 219, 105, 26, 185, 24, 104, 112, 71, 0, 32, ++ 112, 71, 0, 32, 112, 71, 0, 0, 45, 233, 243, 65, 176, 248, 18, 128, ++ 135, 138, 198, 138, 132, 121, 128, 68, 199, 25, 134, 25, 244, 185, 37, ++ 70, 5, 240, 15, 3, 54, 248, 19, 16, 1, 51, 54, 248, 19, 32, 138, 66, ++ 14, 208, 12, 75, 82, 26, 24, 25, 128, 136, 79, 240, 12, 14, 0, 144, ++ 146, 178, 8, 235, 1, 0, 227, 88, 14, 251, 1, 113, 42, 240, 216, 222, ++ 1, 53, 8, 52, 13, 45, 227, 209, 0, 32, 1, 224, 111, 240, 22, 0, 189, ++ 232, 252, 129, 252, 60, 4, 0, 112, 181, 75, 120, 12, 70, 4, 43, 15, ++ 217, 0, 37, 29, 75, 6, 38, 6, 251, 5, 54, 160, 28, 49, 70, 5, 34, 216, ++ 247, 186, 249, 8, 185, 112, 121, 112, 189, 1, 53, 3, 45, 240, 209, 99, ++ 120, 3, 43, 15, 217, 0, 37, 21, 78, 5, 235, 133, 3, 246, 24, 160, 28, ++ 49, 70, 4, 34, 216, 247, 167, 249, 8, 185, 48, 121, 112, 189, 1, 53, ++ 15, 45, 240, 209, 99, 120, 2, 43, 18, 217, 2, 52, 32, 70, 12, 73, 3, ++ 34, 216, 247, 152, 249, 10, 77, 48, 177, 32, 70, 41, 29, 3, 34, 216, ++ 247, 145, 249, 48, 185, 1, 32, 5, 235, 128, 5, 232, 120, 112, 189, 250, ++ 32, 112, 189, 250, 32, 112, 189, 123, 233, 135, 0, 104, 61, 4, 0, 141, ++ 233, 135, 0, 248, 181, 6, 158, 7, 159, 0, 35, 51, 112, 5, 70, 59, 96, ++ 12, 70, 49, 177, 74, 120, 2, 42, 3, 217, 137, 120, 226, 120, 145, 66, ++ 4, 211, 40, 70, 1, 33, 4, 240, 4, 222, 42, 224, 208, 248, 4, 33, 82, ++ 120, 18, 177, 25, 70, 4, 240, 252, 221, 107, 124, 27, 185, 40, 70, 225, ++ 120, 17, 240, 90, 219, 163, 120, 59, 96, 35, 121, 3, 240, 1, 3, 51, ++ 112, 181, 248, 214, 16, 35, 121, 138, 4, 146, 12, 3, 240, 254, 3, 210, ++ 16, 154, 66, 96, 120, 12, 211, 3, 56, 192, 24, 130, 66, 10, 210, 164, ++ 24, 227, 26, 88, 121, 1, 240, 7, 1, 8, 65, 0, 240, 1, 0, 248, 189, 0, ++ 32, 248, 189, 0, 32, 248, 189, 45, 233, 240, 71, 77, 104, 7, 70, 8, ++ 70, 137, 70, 206, 104, 213, 248, 68, 131, 255, 247, 29, 255, 4, 70, ++ 238, 177, 115, 120, 24, 43, 26, 208, 7, 43, 24, 208, 59, 104, 91, 107, ++ 0, 43, 0, 240, 215, 128, 213, 248, 204, 48, 19, 240, 2, 1, 64, 240, ++ 209, 128, 66, 104, 35, 244, 128, 115, 34, 244, 0, 18, 34, 240, 64, 2, ++ 66, 96, 197, 248, 204, 48, 1, 34, 228, 247, 150, 252, 194, 224, 185, ++ 248, 8, 48, 32, 43, 11, 208, 4, 216, 75, 177, 16, 43, 64, 240, 186, ++ 128, 52, 224, 48, 43, 50, 208, 128, 43, 64, 240, 180, 128, 138, 224, ++ 99, 104, 35, 244, 0, 19, 35, 240, 64, 3, 99, 96, 59, 104, 91, 107, 0, ++ 43, 0, 240, 168, 128, 213, 248, 204, 16, 17, 240, 2, 1, 64, 240, 162, ++ 128, 32, 70, 1, 34, 228, 247, 112, 252, 0, 46, 0, 240, 155, 128, 99, ++ 104, 67, 240, 64, 3, 99, 96, 152, 248, 39, 48, 0, 43, 0, 240, 146, 128, ++ 32, 70, 1, 34, 49, 122, 228, 247, 95, 252, 148, 248, 217, 48, 24, 7, ++ 0, 240, 136, 128, 99, 104, 67, 244, 0, 19, 108, 224, 98, 104, 213, 248, ++ 4, 145, 34, 240, 64, 2, 98, 96, 213, 248, 204, 32, 34, 244, 128, 113, ++ 197, 248, 204, 16, 57, 104, 73, 107, 0, 41, 115, 208, 145, 7, 113, 212, ++ 48, 43, 10, 209, 6, 34, 5, 241, 216, 0, 213, 248, 240, 16, 216, 247, ++ 184, 248, 0, 48, 24, 191, 1, 32, 0, 224, 1, 32, 95, 250, 128, 250, 0, ++ 33, 32, 70, 82, 70, 228, 247, 47, 252, 0, 46, 90, 208, 99, 104, 177, ++ 28, 67, 240, 64, 3, 99, 96, 213, 248, 204, 48, 64, 70, 67, 244, 128, ++ 115, 197, 248, 204, 48, 114, 120, 216, 247, 174, 248, 152, 249, 6, 48, ++ 0, 43, 6, 218, 32, 70, 152, 248, 38, 16, 82, 70, 228, 247, 20, 252, ++ 16, 224, 59, 104, 91, 107, 1, 51, 60, 209, 97, 104, 202, 5, 57, 213, ++ 17, 240, 128, 97, 6, 209, 1, 35, 137, 248, 29, 48, 40, 70, 234, 247, ++ 100, 249, 47, 224, 153, 248, 0, 16, 0, 35, 1, 41, 137, 248, 29, 48, ++ 40, 209, 243, 231, 59, 104, 91, 107, 35, 179, 213, 248, 204, 48, 3, ++ 244, 129, 115, 179, 245, 128, 127, 29, 209, 60, 177, 43, 124, 43, 185, ++ 206, 177, 99, 104, 67, 240, 64, 3, 99, 96, 20, 224, 30, 185, 2, 35, ++ 136, 248, 8, 48, 10, 224, 152, 248, 6, 32, 51, 122, 83, 64, 27, 7, 9, ++ 208, 64, 70, 177, 28, 24, 34, 216, 247, 103, 248, 56, 70, 41, 70, 1, ++ 34, 255, 243, 160, 244, 0, 32, 189, 232, 240, 135, 83, 104, 112, 181, ++ 35, 240, 128, 83, 83, 96, 147, 104, 12, 70, 35, 240, 254, 99, 147, 96, ++ 75, 120, 21, 70, 67, 177, 136, 28, 0, 33, 218, 243, 112, 242, 24, 177, ++ 107, 104, 67, 240, 128, 83, 107, 96, 99, 120, 4, 43, 54, 217, 166, 28, ++ 48, 70, 38, 33, 218, 243, 99, 242, 24, 177, 171, 104, 67, 244, 128, ++ 19, 171, 96, 48, 70, 39, 33, 218, 243, 90, 242, 24, 177, 171, 104, 67, ++ 244, 0, 19, 171, 96, 48, 70, 37, 33, 218, 243, 81, 242, 24, 177, 171, ++ 104, 67, 244, 128, 3, 171, 96, 48, 70, 28, 33, 218, 243, 72, 242, 24, ++ 177, 171, 104, 67, 244, 0, 3, 171, 96, 48, 70, 20, 33, 218, 243, 63, ++ 242, 24, 177, 171, 104, 67, 240, 128, 115, 171, 96, 48, 70, 30, 33, ++ 218, 243, 54, 242, 24, 177, 171, 104, 67, 240, 0, 115, 171, 96, 99, ++ 120, 7, 43, 10, 217, 160, 28, 62, 33, 218, 243, 42, 242, 40, 177, 213, ++ 248, 164, 49, 67, 244, 128, 67, 197, 248, 164, 49, 99, 120, 8, 43, 10, ++ 217, 160, 28, 70, 33, 218, 243, 28, 242, 40, 177, 213, 248, 164, 49, ++ 67, 240, 32, 3, 197, 248, 164, 49, 99, 120, 8, 43, 10, 217, 160, 28, ++ 71, 33, 218, 243, 14, 242, 40, 177, 213, 248, 164, 49, 67, 240, 16, ++ 3, 197, 248, 164, 49, 99, 120, 8, 43, 10, 217, 160, 28, 70, 33, 218, ++ 243, 0, 242, 40, 177, 213, 248, 164, 49, 67, 240, 32, 3, 197, 248, 164, ++ 49, 99, 120, 8, 43, 10, 217, 160, 28, 71, 33, 218, 243, 242, 241, 40, ++ 177, 213, 248, 164, 49, 67, 240, 16, 3, 197, 248, 164, 49, 112, 189, ++ 248, 181, 208, 248, 240, 48, 4, 70, 13, 70, 152, 110, 179, 248, 108, ++ 16, 12, 48, 12, 57, 127, 34, 223, 247, 165, 248, 184, 177, 148, 248, ++ 96, 35, 170, 177, 70, 120, 0, 35, 150, 66, 40, 191, 22, 70, 26, 70, ++ 10, 224, 231, 24, 193, 24, 151, 248, 97, 115, 137, 120, 57, 64, 233, ++ 84, 1, 51, 0, 41, 24, 191, 26, 70, 179, 66, 242, 211, 0, 224, 2, 70, ++ 16, 70, 248, 189, 31, 181, 72, 104, 12, 70, 2, 169, 255, 247, 209, 255, ++ 2, 70, 96, 177, 227, 105, 127, 32, 0, 147, 2, 169, 163, 105, 218, 243, ++ 58, 240, 163, 105, 131, 66, 12, 191, 111, 240, 13, 0, 0, 32, 4, 176, ++ 16, 189, 19, 181, 12, 70, 73, 104, 145, 248, 96, 35, 218, 177, 35, 137, ++ 32, 43, 2, 208, 176, 43, 0, 208, 43, 185, 33, 70, 2, 176, 189, 232, ++ 16, 64, 255, 247, 215, 191, 227, 105, 1, 245, 88, 113, 0, 147, 127, ++ 32, 1, 49, 163, 105, 218, 243, 23, 240, 163, 105, 131, 66, 20, 191, ++ 0, 32, 111, 240, 13, 0, 0, 224, 16, 70, 2, 176, 16, 189, 7, 181, 72, ++ 104, 105, 70, 255, 247, 150, 255, 0, 40, 200, 191, 2, 48, 14, 189, 75, ++ 104, 147, 248, 96, 51, 75, 177, 10, 137, 32, 42, 2, 208, 176, 42, 0, ++ 208, 10, 185, 255, 247, 235, 191, 152, 28, 112, 71, 24, 70, 112, 71, ++ 16, 181, 8, 70, 12, 70, 0, 33, 234, 247, 21, 248, 212, 248, 4, 49, 0, ++ 34, 131, 248, 116, 32, 212, 248, 4, 49, 179, 248, 114, 32, 2, 177, 218, ++ 98, 32, 70, 13, 240, 216, 249, 212, 248, 4, 49, 219, 139, 35, 177, 32, ++ 70, 189, 232, 16, 64, 57, 240, 55, 156, 16, 189, 45, 233, 255, 65, 11, ++ 104, 76, 104, 10, 70, 217, 105, 6, 70, 15, 104, 161, 121, 212, 248, ++ 4, 81, 212, 248, 68, 131, 0, 41, 64, 240, 143, 128, 33, 124, 0, 41, ++ 0, 240, 139, 128, 13, 241, 15, 1, 0, 145, 2, 169, 1, 145, 209, 104, ++ 219, 104, 18, 105, 32, 70, 255, 247, 121, 253, 51, 104, 1, 70, 147, ++ 248, 60, 32, 26, 177, 189, 248, 8, 32, 164, 248, 44, 35, 106, 108, 0, ++ 42, 115, 209, 0, 41, 52, 208, 42, 120, 2, 42, 4, 209, 48, 70, 33, 70, ++ 255, 247, 174, 255, 64, 224, 91, 107, 59, 177, 152, 248, 39, 48, 35, ++ 177, 175, 177, 151, 248, 218, 48, 15, 43, 17, 208, 43, 122, 35, 177, ++ 48, 70, 33, 70, 3, 240, 233, 220, 47, 224, 79, 240, 255, 50, 1, 146, ++ 48, 70, 33, 70, 4, 241, 188, 2, 0, 147, 3, 240, 216, 220, 36, 224, 152, ++ 248, 37, 48, 11, 179, 43, 122, 59, 177, 31, 177, 123, 104, 35, 240, ++ 0, 99, 123, 96, 32, 70, 249, 243, 12, 246, 32, 70, 231, 247, 128, 250, ++ 19, 224, 43, 123, 35, 177, 235, 137, 19, 185, 32, 70, 4, 240, 111, 220, ++ 212, 248, 4, 49, 219, 139, 67, 177, 43, 120, 2, 43, 5, 209, 43, 106, ++ 1, 43, 2, 209, 32, 70, 57, 240, 160, 219, 214, 248, 104, 49, 43, 179, ++ 155, 121, 27, 179, 43, 120, 2, 43, 32, 209, 48, 70, 33, 70, 1, 34, 23, ++ 240, 67, 221, 208, 177, 212, 248, 244, 48, 181, 248, 114, 32, 219, 141, ++ 48, 70, 219, 8, 154, 66, 44, 191, 234, 98, 235, 98, 33, 70, 23, 240, ++ 158, 217, 64, 177, 2, 155, 1, 43, 5, 209, 212, 248, 244, 48, 234, 106, ++ 219, 141, 211, 24, 235, 98, 32, 70, 13, 240, 47, 249, 0, 32, 4, 176, ++ 189, 232, 240, 129, 0, 0, 45, 233, 247, 67, 5, 105, 4, 70, 208, 248, ++ 12, 128, 0, 38, 40, 70, 15, 70, 145, 70, 141, 248, 7, 96, 41, 240, 164, ++ 220, 32, 177, 160, 104, 226, 247, 105, 251, 48, 70, 250, 224, 174, 109, ++ 50, 1, 4, 213, 213, 248, 148, 48, 88, 106, 4, 240, 13, 249, 0, 35, 171, ++ 101, 51, 2, 2, 213, 40, 70, 26, 240, 17, 220, 119, 75, 51, 64, 67, 177, ++ 32, 70, 198, 243, 192, 65, 15, 240, 45, 220, 32, 70, 65, 70, 5, 240, ++ 73, 219, 176, 7, 12, 213, 35, 104, 147, 248, 47, 32, 66, 177, 147, 248, ++ 48, 48, 19, 177, 148, 248, 114, 50, 19, 177, 32, 70, 5, 240, 136, 223, ++ 113, 6, 8, 213, 40, 70, 57, 70, 27, 240, 90, 217, 24, 177, 171, 109, ++ 67, 240, 64, 3, 171, 101, 178, 0, 17, 213, 40, 70, 57, 70, 13, 241, ++ 7, 2, 27, 240, 7, 222, 24, 177, 171, 109, 67, 240, 0, 83, 171, 101, ++ 157, 248, 7, 48, 27, 177, 32, 70, 255, 243, 78, 243, 173, 224, 179, ++ 6, 6, 213, 212, 248, 28, 49, 200, 248, 36, 49, 0, 35, 196, 248, 28, ++ 49, 22, 244, 0, 99, 8, 208, 35, 104, 211, 248, 136, 48, 154, 107, 1, ++ 50, 154, 99, 213, 248, 180, 48, 1, 51, 48, 4, 197, 248, 180, 48, 10, ++ 213, 40, 70, 0, 33, 58, 70, 75, 70, 250, 247, 88, 252, 24, 177, 171, ++ 109, 67, 244, 0, 67, 171, 101, 241, 3, 7, 213, 40, 70, 1, 33, 27, 240, ++ 133, 221, 16, 177, 32, 70, 5, 240, 179, 222, 114, 3, 4, 213, 213, 248, ++ 148, 48, 88, 106, 4, 240, 152, 248, 179, 4, 4, 212, 43, 104, 147, 248, ++ 42, 56, 0, 43, 66, 208, 35, 104, 60, 72, 154, 106, 217, 104, 217, 243, ++ 143, 241, 43, 104, 147, 248, 42, 40, 74, 177, 179, 248, 40, 40, 32, ++ 70, 1, 50, 163, 248, 40, 40, 238, 247, 21, 254, 2, 39, 0, 224, 3, 39, ++ 32, 70, 57, 70, 231, 247, 104, 248, 35, 104, 211, 248, 136, 48, 211, ++ 248, 20, 34, 1, 50, 195, 248, 20, 34, 45, 75, 27, 104, 1, 43, 15, 209, ++ 132, 248, 213, 49, 132, 248, 95, 55, 32, 70, 0, 240, 119, 222, 40, 70, ++ 2, 33, 0, 34, 26, 240, 174, 223, 0, 35, 132, 248, 95, 55, 60, 224, 2, ++ 47, 3, 209, 43, 104, 0, 34, 131, 248, 42, 40, 32, 70, 255, 243, 211, ++ 242, 2, 47, 2, 209, 32, 70, 238, 247, 250, 253, 213, 248, 68, 49, 163, ++ 177, 35, 104, 32, 70, 211, 248, 136, 32, 35, 105, 211, 248, 68, 49, ++ 7, 43, 136, 191, 0, 35, 202, 51, 2, 235, 131, 3, 90, 104, 1, 50, 90, ++ 96, 0, 35, 197, 248, 68, 49, 255, 243, 182, 242, 0, 46, 3, 218, 212, ++ 248, 208, 5, 41, 240, 190, 216, 240, 0, 2, 213, 32, 70, 2, 240, 97, ++ 220, 177, 1, 2, 213, 40, 70, 28, 240, 2, 216, 212, 248, 164, 21, 75, ++ 137, 19, 177, 32, 70, 232, 247, 86, 250, 168, 109, 0, 48, 24, 191, 1, ++ 32, 189, 232, 254, 131, 0, 191, 4, 0, 8, 0, 135, 165, 136, 0, 108, 7, ++ 0, 0, 6, 32, 112, 71, 45, 233, 240, 79, 144, 248, 148, 66, 133, 176, ++ 5, 70, 136, 70, 22, 70, 180, 185, 19, 109, 19, 240, 8, 9, 19, 209, 208, ++ 248, 128, 50, 83, 248, 33, 64, 116, 177, 35, 105, 0, 43, 64, 240, 33, ++ 129, 28, 70, 153, 70, 8, 224, 32, 70, 222, 247, 142, 253, 32, 185, 148, ++ 248, 12, 144, 1, 224, 0, 36, 161, 70, 184, 241, 3, 15, 5, 221, 12, 185, ++ 71, 70, 12, 225, 103, 122, 4, 55, 9, 225, 43, 104, 194, 70, 211, 248, ++ 192, 112, 4, 55, 3, 47, 11, 217, 43, 104, 211, 248, 192, 48, 4, 51, ++ 159, 66, 5, 210, 40, 70, 57, 31, 7, 240, 246, 217, 3, 144, 1, 224, 0, ++ 35, 3, 147, 73, 234, 8, 25, 31, 250, 137, 249, 31, 250, 137, 251, 68, ++ 179, 213, 248, 108, 50, 158, 66, 0, 240, 240, 128, 179, 121, 0, 43, ++ 64, 240, 236, 128, 51, 124, 0, 43, 0, 240, 232, 128, 32, 70, 222, 247, ++ 83, 253, 0, 40, 64, 240, 226, 128, 51, 24, 219, 110, 83, 177, 26, 105, ++ 66, 177, 27, 123, 2, 43, 0, 240, 217, 128, 73, 234, 131, 41, 31, 250, ++ 137, 251, 211, 224, 4, 48, 16, 40, 238, 209, 207, 224, 227, 121, 11, ++ 177, 75, 240, 8, 11, 43, 104, 211, 248, 200, 48, 154, 69, 4, 210, 40, ++ 70, 81, 70, 90, 70, 6, 240, 116, 216, 0, 44, 0, 240, 158, 128, 35, 123, ++ 0, 43, 0, 240, 192, 128, 213, 248, 252, 18, 79, 234, 8, 27, 16, 35, ++ 40, 70, 89, 68, 4, 241, 20, 2, 250, 243, 78, 246, 213, 248, 180, 49, ++ 0, 43, 68, 218, 35, 122, 2, 43, 65, 209, 149, 248, 148, 50, 0, 43, 61, ++ 209, 51, 109, 26, 7, 58, 212, 42, 104, 163, 121, 210, 248, 188, 32, ++ 147, 66, 52, 210, 3, 43, 50, 217, 11, 43, 48, 216, 184, 241, 3, 15, ++ 10, 221, 32, 70, 222, 247, 0, 253, 48, 185, 40, 70, 49, 70, 34, 70, ++ 18, 240, 134, 252, 130, 70, 1, 224, 79, 240, 0, 10, 213, 248, 0, 51, ++ 49, 70, 82, 70, 40, 104, 11, 235, 3, 9, 65, 240, 141, 223, 34, 24, 73, ++ 70, 40, 70, 20, 50, 8, 35, 250, 243, 22, 246, 213, 248, 0, 51, 49, 70, ++ 8, 51, 82, 70, 40, 104, 155, 68, 65, 240, 93, 222, 34, 24, 89, 70, 40, ++ 70, 20, 50, 8, 35, 250, 243, 6, 246, 107, 224, 35, 122, 11, 43, 104, ++ 209, 43, 104, 147, 248, 177, 48, 0, 43, 99, 208, 163, 121, 7, 43, 96, ++ 216, 213, 248, 152, 1, 65, 70, 34, 70, 76, 240, 10, 219, 89, 224, 43, ++ 104, 211, 248, 192, 48, 4, 51, 159, 66, 45, 210, 35, 122, 2, 43, 36, ++ 209, 79, 240, 14, 10, 10, 251, 7, 250, 79, 240, 0, 9, 41, 240, 1, 3, ++ 227, 24, 10, 245, 56, 113, 73, 68, 40, 70, 179, 248, 100, 32, 9, 241, ++ 2, 9, 5, 240, 243, 223, 185, 241, 10, 15, 239, 209, 10, 245, 58, 113, ++ 40, 70, 2, 49, 180, 248, 136, 32, 5, 240, 232, 223, 40, 70, 10, 245, ++ 59, 113, 180, 248, 138, 32, 5, 240, 225, 223, 40, 70, 57, 70, 34, 70, ++ 3, 155, 44, 240, 67, 216, 184, 241, 3, 15, 37, 220, 40, 70, 44, 240, ++ 161, 216, 50, 124, 3, 70, 58, 185, 182, 248, 90, 32, 2, 240, 1, 2, 0, ++ 42, 24, 191, 79, 244, 128, 67, 3, 34, 0, 146, 40, 70, 0, 33, 79, 244, ++ 128, 66, 0, 240, 68, 220, 14, 224, 186, 70, 250, 230, 35, 122, 2, 43, ++ 127, 244, 226, 174, 220, 230, 35, 122, 11, 43, 127, 244, 48, 175, 42, ++ 231, 3, 47, 163, 216, 214, 231, 5, 176, 189, 232, 240, 143, 248, 181, ++ 12, 105, 208, 248, 108, 50, 5, 70, 156, 66, 14, 70, 6, 208, 163, 121, ++ 35, 185, 35, 124, 19, 177, 33, 70, 44, 240, 194, 216, 242, 104, 162, ++ 177, 40, 70, 33, 70, 151, 121, 44, 240, 227, 216, 43, 104, 211, 248, ++ 188, 48, 159, 66, 10, 218, 149, 248, 148, 50, 59, 185, 35, 109, 25, ++ 7, 4, 212, 40, 70, 57, 70, 34, 70, 44, 240, 153, 219, 213, 248, 152, ++ 1, 49, 70, 34, 70, 189, 232, 248, 64, 76, 240, 247, 153, 0, 0, 45, 233, ++ 240, 79, 155, 70, 83, 31, 27, 43, 135, 176, 6, 70, 13, 70, 146, 70, ++ 0, 242, 92, 130, 159, 74, 154, 64, 64, 241, 88, 130, 187, 241, 3, 15, ++ 0, 242, 87, 130, 19, 152, 222, 247, 30, 252, 7, 70, 0, 40, 64, 208, ++ 214, 248, 108, 50, 157, 66, 14, 209, 11, 241, 26, 3, 5, 235, 131, 3, ++ 90, 104, 34, 185, 6, 235, 139, 2, 210, 248, 132, 34, 90, 96, 95, 70, ++ 205, 248, 8, 176, 16, 224, 171, 121, 27, 185, 79, 234, 91, 2, 2, 146, ++ 1, 224, 205, 248, 8, 176, 2, 155, 3, 241, 26, 8, 5, 235, 136, 8, 216, ++ 248, 4, 64, 52, 177, 167, 121, 79, 240, 0, 9, 205, 248, 4, 144, 200, ++ 70, 139, 224, 42, 124, 4, 33, 0, 42, 12, 191, 16, 34, 128, 34, 1, 35, ++ 48, 70, 43, 240, 79, 222, 7, 30, 192, 242, 41, 130, 214, 248, 128, 50, ++ 161, 70, 83, 248, 39, 48, 1, 148, 200, 248, 4, 48, 160, 70, 116, 224, ++ 43, 122, 243, 177, 213, 248, 244, 48, 41, 70, 92, 142, 19, 154, 4, 244, ++ 64, 68, 164, 245, 64, 64, 68, 66, 68, 235, 0, 4, 35, 70, 48, 70, 18, ++ 240, 88, 251, 128, 70, 192, 185, 48, 70, 41, 70, 19, 154, 35, 70, 18, ++ 240, 3, 252, 128, 70, 0, 40, 0, 240, 245, 129, 1, 34, 1, 146, 12, 224, ++ 48, 70, 41, 70, 19, 154, 18, 240, 249, 251, 128, 70, 0, 40, 0, 240, ++ 233, 129, 1, 35, 1, 147, 0, 224, 1, 151, 216, 248, 12, 48, 83, 177, ++ 159, 121, 214, 248, 152, 1, 65, 70, 17, 154, 91, 70, 76, 240, 65, 217, ++ 129, 70, 56, 179, 1, 224, 79, 240, 1, 9, 48, 70, 41, 70, 16, 154, 19, ++ 155, 43, 240, 204, 221, 7, 30, 192, 242, 216, 129, 214, 248, 128, 50, ++ 214, 248, 72, 1, 83, 248, 39, 32, 41, 70, 200, 248, 12, 32, 83, 248, ++ 39, 64, 50, 240, 150, 220, 171, 121, 51, 185, 51, 104, 211, 248, 192, ++ 48, 152, 66, 1, 218, 96, 114, 5, 224, 163, 121, 3, 43, 64, 242, 181, ++ 129, 4, 59, 99, 114, 214, 248, 108, 50, 157, 66, 6, 208, 171, 121, 35, ++ 185, 48, 70, 41, 70, 58, 70, 43, 240, 54, 222, 214, 248, 160, 1, 65, ++ 70, 75, 240, 161, 217, 0, 34, 2, 146, 214, 248, 128, 50, 83, 248, 39, ++ 64, 185, 241, 0, 15, 14, 209, 227, 121, 155, 69, 11, 209, 35, 105, 154, ++ 69, 8, 209, 18, 152, 4, 241, 20, 1, 82, 70, 215, 247, 3, 251, 0, 40, ++ 0, 240, 142, 129, 99, 122, 96, 107, 3, 147, 8, 177, 224, 247, 170, 250, ++ 212, 248, 224, 144, 32, 70, 0, 33, 228, 34, 216, 243, 134, 246, 196, ++ 248, 224, 144, 185, 241, 0, 15, 8, 208, 51, 104, 72, 70, 219, 105, 0, ++ 33, 211, 248, 212, 32, 82, 1, 216, 243, 120, 246, 3, 155, 4, 241, 20, ++ 9, 99, 114, 18, 153, 82, 70, 167, 113, 72, 70, 215, 247, 238, 250, 95, ++ 250, 138, 243, 35, 97, 6, 34, 132, 248, 7, 176, 32, 70, 19, 153, 215, ++ 247, 228, 250, 0, 35, 186, 241, 13, 15, 99, 115, 32, 208, 4, 216, 186, ++ 241, 5, 15, 64, 240, 134, 128, 6, 224, 186, 241, 16, 15, 66, 208, 186, ++ 241, 32, 15, 126, 209, 37, 224, 1, 35, 35, 114, 35, 115, 4, 35, 163, ++ 115, 227, 115, 73, 70, 82, 70, 4, 241, 25, 0, 215, 247, 198, 250, 4, ++ 241, 30, 0, 73, 70, 82, 70, 215, 247, 192, 250, 35, 125, 12, 224, 3, ++ 35, 35, 114, 4, 35, 35, 115, 163, 115, 227, 115, 35, 125, 132, 248, ++ 33, 48, 99, 125, 132, 248, 34, 48, 163, 125, 132, 248, 35, 48, 89, 224, ++ 16, 0, 144, 128, 17, 154, 11, 42, 14, 209, 34, 114, 48, 70, 255, 247, ++ 53, 253, 18, 35, 163, 115, 16, 35, 32, 115, 227, 115, 72, 70, 18, 153, ++ 82, 70, 215, 247, 155, 250, 69, 224, 2, 35, 35, 114, 35, 115, 8, 35, ++ 163, 115, 4, 35, 17, 224, 17, 154, 83, 31, 3, 43, 29, 216, 223, 232, ++ 3, 240, 14, 14, 2, 2, 181, 248, 90, 48, 8, 43, 64, 240, 3, 129, 3, 35, ++ 35, 114, 4, 35, 35, 115, 163, 115, 227, 115, 42, 224, 17, 154, 211, ++ 178, 4, 34, 34, 115, 162, 115, 8, 34, 5, 43, 35, 114, 226, 115, 1, 209, ++ 2, 35, 29, 224, 3, 35, 27, 224, 4, 35, 35, 114, 3, 35, 35, 115, 184, ++ 241, 0, 15, 2, 208, 216, 248, 4, 48, 9, 224, 171, 121, 91, 185, 48, ++ 70, 41, 70, 213, 248, 244, 32, 18, 240, 39, 250, 32, 177, 67, 104, 89, ++ 5, 1, 213, 5, 35, 35, 115, 8, 35, 163, 115, 227, 115, 1, 35, 99, 115, ++ 1, 155, 171, 177, 35, 122, 1, 59, 10, 43, 17, 216, 223, 232, 3, 240, ++ 6, 8, 6, 10, 16, 16, 16, 16, 16, 16, 12, 0, 1, 35, 5, 224, 2, 35, 3, ++ 224, 4, 35, 1, 224, 79, 244, 128, 115, 200, 248, 72, 48, 19, 152, 222, ++ 247, 117, 250, 216, 177, 16, 155, 19, 240, 2, 15, 171, 110, 16, 208, ++ 90, 28, 7, 208, 5, 235, 131, 3, 219, 110, 27, 177, 90, 137, 34, 240, ++ 2, 2, 90, 129, 99, 137, 2, 154, 67, 240, 2, 3, 170, 102, 99, 129, 5, ++ 224, 2, 154, 147, 66, 4, 191, 79, 240, 255, 51, 171, 102, 48, 70, 41, ++ 70, 34, 70, 20, 155, 44, 240, 74, 221, 128, 70, 40, 177, 48, 70, 33, ++ 70, 43, 240, 238, 221, 71, 70, 142, 224, 35, 122, 2, 43, 43, 209, 181, ++ 248, 90, 48, 219, 7, 7, 213, 32, 70, 222, 247, 64, 250, 24, 177, 4, ++ 168, 5, 241, 96, 1, 2, 224, 4, 168, 4, 241, 56, 1, 8, 34, 215, 247, ++ 249, 249, 4, 155, 4, 241, 64, 0, 73, 70, 5, 241, 194, 2, 230, 243, 43, ++ 246, 32, 70, 222, 247, 42, 250, 4, 241, 100, 3, 24, 185, 24, 70, 73, ++ 70, 34, 70, 3, 224, 24, 70, 73, 70, 5, 241, 188, 2, 212, 248, 136, 48, ++ 230, 243, 25, 246, 48, 70, 57, 70, 42, 70, 44, 240, 98, 223, 214, 248, ++ 108, 50, 157, 66, 31, 208, 171, 121, 235, 185, 43, 124, 219, 177, 32, ++ 70, 222, 247, 11, 250, 184, 177, 213, 248, 244, 48, 48, 70, 91, 142, ++ 41, 70, 3, 244, 64, 67, 163, 245, 64, 71, 123, 66, 67, 235, 7, 3, 5, ++ 241, 188, 2, 18, 240, 138, 249, 48, 177, 195, 104, 35, 177, 48, 70, ++ 153, 121, 42, 70, 44, 240, 62, 223, 171, 121, 235, 185, 213, 248, 204, ++ 48, 91, 5, 3, 212, 32, 70, 222, 247, 233, 249, 168, 177, 40, 70, 1, ++ 240, 87, 219, 1, 34, 7, 70, 133, 248, 92, 32, 48, 70, 41, 70, 251, 247, ++ 67, 255, 79, 185, 40, 70, 1, 240, 75, 219, 40, 177, 213, 248, 4, 49, ++ 40, 70, 25, 122, 233, 247, 103, 250, 21, 155, 155, 177, 28, 96, 0, 39, ++ 17, 224, 111, 240, 23, 7, 14, 224, 111, 240, 7, 7, 11, 224, 111, 240, ++ 29, 7, 8, 224, 79, 240, 255, 55, 5, 224, 79, 70, 3, 224, 111, 240, 28, ++ 7, 0, 224, 21, 159, 56, 70, 7, 176, 189, 232, 240, 143, 0, 191, 240, ++ 181, 208, 248, 116, 52, 144, 248, 68, 68, 91, 121, 16, 37, 3, 240, 1, ++ 7, 91, 16, 3, 240, 1, 6, 0, 35, 26, 70, 39, 177, 0, 235, 68, 12, 188, ++ 249, 196, 195, 98, 68, 38, 177, 0, 235, 68, 12, 188, 249, 228, 195, ++ 99, 68, 1, 52, 1, 61, 4, 240, 15, 4, 238, 209, 0, 42, 184, 191, 15, ++ 50, 18, 17, 0, 43, 184, 191, 15, 51, 27, 17, 10, 112, 75, 112, 240, ++ 189, 112, 181, 0, 35, 138, 176, 193, 88, 1, 170, 153, 80, 4, 51, 36, ++ 43, 249, 209, 0, 35, 25, 70, 1, 49, 201, 178, 10, 70, 10, 168, 0, 235, ++ 130, 6, 1, 168, 86, 248, 36, 92, 28, 88, 1, 50, 210, 178, 165, 66, 212, ++ 191, 70, 248, 36, 92, 70, 248, 36, 76, 165, 66, 172, 191, 29, 80, 28, ++ 80, 8, 42, 234, 217, 4, 51, 5, 41, 228, 209, 5, 152, 10, 176, 112, 189, ++ 112, 181, 134, 176, 0, 35, 15, 153, 4, 147, 5, 70, 20, 70, 12, 158, ++ 251, 247, 139, 250, 11, 155, 3, 43, 4, 217, 4, 168, 10, 153, 4, 34, ++ 215, 247, 21, 249, 20, 177, 6, 44, 43, 209, 37, 224, 12, 34, 33, 70, ++ 1, 168, 216, 243, 140, 244, 6, 169, 1, 35, 65, 248, 4, 77, 40, 70, 1, ++ 147, 255, 247, 138, 255, 2, 35, 2, 147, 213, 248, 116, 52, 48, 70, 90, ++ 121, 1, 169, 210, 7, 68, 191, 157, 248, 20, 32, 141, 248, 12, 32, 91, ++ 121, 155, 7, 68, 191, 157, 248, 21, 48, 141, 248, 13, 48, 12, 34, 215, ++ 247, 237, 248, 0, 32, 6, 224, 0, 32, 197, 248, 36, 7, 48, 96, 1, 224, ++ 111, 240, 22, 0, 6, 176, 112, 189, 56, 181, 4, 70, 13, 70, 241, 177, ++ 144, 248, 32, 56, 0, 235, 131, 2, 1, 51, 219, 178, 8, 43, 194, 248, ++ 252, 23, 128, 248, 32, 56, 2, 217, 0, 35, 128, 248, 32, 56, 4, 245, ++ 254, 96, 12, 48, 255, 247, 122, 255, 0, 40, 8, 191, 40, 70, 196, 248, ++ 36, 7, 95, 48, 188, 191, 111, 240, 94, 3, 196, 248, 36, 55, 212, 248, ++ 36, 7, 56, 189, 144, 248, 174, 32, 176, 248, 122, 48, 42, 177, 0, 34, ++ 128, 248, 174, 32, 3, 245, 122, 115, 0, 224, 200, 59, 160, 248, 122, ++ 48, 176, 248, 122, 48, 66, 242, 40, 50, 147, 66, 2, 217, 160, 248, 122, ++ 32, 112, 71, 65, 242, 111, 114, 147, 66, 156, 191, 65, 242, 112, 115, ++ 160, 248, 122, 48, 112, 71, 112, 181, 144, 249, 32, 48, 2, 104, 88, ++ 28, 23, 208, 210, 248, 104, 2, 0, 34, 0, 235, 131, 5, 131, 88, 107, ++ 177, 46, 104, 211, 248, 40, 67, 214, 248, 40, 99, 180, 66, 6, 208, 9, ++ 177, 139, 66, 3, 208, 20, 177, 147, 248, 68, 0, 3, 224, 4, 50, 32, 42, ++ 236, 209, 255, 32, 64, 178, 112, 189, 144, 248, 32, 48, 48, 181, 89, ++ 178, 74, 28, 4, 104, 39, 208, 144, 248, 33, 32, 85, 178, 181, 241, 255, ++ 63, 33, 208, 7, 43, 154, 191, 212, 248, 104, 82, 85, 248, 33, 16, 0, ++ 33, 7, 42, 158, 191, 212, 248, 104, 66, 85, 178, 84, 248, 37, 64, 141, ++ 121, 136, 191, 0, 36, 125, 185, 212, 248, 204, 64, 20, 244, 0, 95, 10, ++ 208, 209, 248, 204, 16, 137, 4, 6, 212, 90, 64, 83, 64, 90, 64, 128, ++ 248, 32, 48, 128, 248, 33, 32, 48, 189, 45, 233, 248, 67, 177, 248, ++ 46, 83, 4, 70, 14, 70, 79, 240, 0, 8, 212, 248, 104, 50, 83, 248, 8, ++ 112, 143, 177, 183, 66, 15, 208, 183, 248, 46, 3, 217, 243, 50, 246, ++ 129, 70, 182, 248, 46, 3, 217, 243, 45, 246, 129, 69, 4, 209, 215, 248, ++ 244, 48, 93, 142, 0, 39, 5, 224, 8, 241, 4, 8, 184, 241, 32, 15, 227, ++ 209, 247, 231, 212, 248, 104, 50, 83, 248, 7, 128, 184, 241, 0, 15, ++ 22, 208, 176, 69, 20, 208, 184, 248, 46, 3, 217, 243, 19, 246, 129, ++ 70, 182, 248, 46, 3, 217, 243, 14, 246, 129, 69, 9, 209, 216, 248, 244, ++ 48, 5, 244, 96, 82, 91, 142, 3, 244, 96, 81, 145, 66, 200, 191, 29, ++ 70, 4, 55, 32, 47, 222, 209, 40, 70, 189, 232, 248, 131, 248, 181, 5, ++ 104, 6, 70, 15, 70, 0, 36, 213, 248, 104, 50, 25, 89, 0, 41, 52, 208, ++ 139, 121, 0, 43, 49, 209, 11, 122, 0, 43, 46, 208, 209, 248, 40, 51, ++ 187, 66, 42, 209, 209, 248, 4, 49, 90, 108, 80, 7, 37, 212, 34, 240, ++ 2, 2, 90, 100, 26, 120, 50, 177, 2, 42, 4, 208, 88, 127, 16, 185, 150, ++ 248, 74, 0, 200, 177, 24, 122, 184, 177, 40, 104, 144, 248, 61, 0, 48, ++ 177, 209, 248, 204, 0, 128, 4, 2, 213, 145, 248, 57, 3, 96, 185, 2, ++ 42, 6, 209, 91, 104, 216, 7, 7, 213, 40, 70, 255, 247, 126, 248, 3, ++ 224, 8, 70, 0, 33, 233, 247, 148, 248, 4, 52, 32, 44, 194, 209, 248, ++ 189, 115, 181, 0, 35, 6, 70, 214, 248, 104, 34, 213, 88, 0, 45, 58, ++ 208, 213, 248, 40, 35, 138, 66, 54, 209, 48, 70, 251, 247, 13, 253, ++ 170, 121, 16, 240, 4, 3, 24, 191, 8, 35, 16, 240, 16, 0, 24, 191, 79, ++ 244, 0, 112, 34, 185, 44, 124, 60, 177, 64, 234, 3, 4, 4, 224, 44, 121, ++ 0, 44, 20, 191, 28, 70, 0, 36, 41, 70, 214, 248, 72, 1, 49, 240, 30, ++ 222, 1, 70, 214, 248, 72, 1, 50, 240, 39, 217, 51, 104, 147, 248, 61, ++ 48, 67, 177, 2, 33, 48, 70, 79, 244, 2, 114, 35, 70, 0, 145, 255, 243, ++ 143, 247, 10, 224, 48, 70, 41, 70, 1, 34, 2, 176, 189, 232, 112, 64, ++ 251, 247, 30, 189, 4, 51, 32, 43, 188, 209, 2, 176, 112, 189, 56, 181, ++ 5, 104, 42, 104, 146, 248, 60, 48, 27, 179, 146, 248, 61, 48, 3, 179, ++ 144, 248, 32, 48, 7, 43, 157, 191, 213, 248, 104, 34, 91, 178, 82, 248, ++ 35, 48, 0, 35, 156, 121, 180, 185, 213, 248, 104, 50, 25, 89, 97, 177, ++ 139, 121, 83, 185, 11, 122, 67, 177, 209, 248, 204, 48, 155, 4, 4, 213, ++ 213, 248, 80, 1, 55, 240, 114, 216, 56, 185, 4, 52, 32, 44, 235, 209, ++ 1, 224, 24, 70, 56, 189, 0, 32, 56, 189, 1, 32, 56, 189, 8, 181, 3, ++ 104, 27, 104, 147, 248, 61, 48, 51, 177, 255, 247, 200, 255, 208, 241, ++ 1, 0, 56, 191, 0, 32, 8, 189, 1, 32, 8, 189, 56, 181, 3, 104, 4, 70, ++ 27, 104, 147, 248, 61, 80, 101, 185, 209, 248, 4, 49, 88, 108, 32, 234, ++ 2, 2, 90, 100, 8, 70, 41, 70, 5, 240, 139, 216, 132, 248, 48, 80, 165, ++ 98, 56, 189, 115, 181, 0, 35, 1, 147, 7, 155, 4, 70, 3, 43, 21, 70, ++ 6, 104, 4, 217, 1, 168, 6, 153, 4, 34, 214, 247, 21, 255, 1, 45, 3, ++ 217, 51, 104, 147, 248, 60, 48, 243, 177, 28, 45, 2, 208, 29, 45, 29, ++ 209, 3, 224, 226, 109, 8, 155, 26, 96, 33, 224, 1, 155, 3, 43, 24, 216, ++ 32, 70, 255, 247, 185, 255, 184, 177, 227, 109, 1, 154, 154, 66, 22, ++ 208, 3, 43, 2, 209, 32, 70, 47, 240, 76, 216, 1, 155, 227, 101, 1, 35, ++ 132, 248, 104, 48, 11, 224, 79, 240, 255, 48, 9, 224, 111, 240, 22, ++ 0, 6, 224, 111, 240, 28, 0, 3, 224, 111, 240, 15, 0, 0, 224, 0, 32, ++ 124, 189, 0, 35, 65, 242, 112, 114, 128, 248, 173, 48, 128, 248, 172, ++ 48, 160, 248, 122, 32, 128, 248, 174, 48, 112, 71, 248, 181, 2, 104, ++ 203, 105, 4, 70, 13, 70, 146, 248, 61, 112, 27, 177, 27, 104, 0, 51, ++ 24, 191, 1, 35, 130, 248, 61, 48, 0, 35, 197, 248, 164, 48, 35, 104, ++ 147, 248, 61, 48, 67, 185, 40, 70, 255, 247, 220, 255, 235, 109, 3, ++ 43, 2, 209, 40, 70, 47, 240, 14, 216, 0, 38, 212, 248, 104, 50, 153, ++ 89, 41, 177, 11, 122, 27, 177, 212, 248, 76, 1, 68, 240, 7, 218, 4, ++ 54, 32, 46, 242, 209, 35, 104, 147, 248, 61, 48, 187, 66, 48, 208, 0, ++ 33, 10, 70, 212, 248, 72, 1, 50, 240, 155, 216, 35, 104, 4, 33, 147, ++ 248, 61, 32, 32, 105, 0, 42, 20, 191, 10, 70, 0, 34, 25, 240, 132, 223, ++ 149, 248, 74, 48, 227, 177, 35, 104, 147, 248, 61, 80, 197, 185, 212, ++ 248, 104, 50, 88, 89, 136, 177, 131, 121, 123, 185, 3, 122, 107, 177, ++ 208, 248, 4, 49, 26, 122, 74, 185, 25, 120, 2, 41, 2, 209, 12, 240, ++ 30, 249, 3, 224, 1, 41, 1, 209, 232, 247, 72, 255, 4, 53, 32, 45, 230, ++ 209, 248, 189, 0, 0, 45, 233, 240, 65, 4, 70, 13, 70, 6, 104, 3, 42, ++ 39, 216, 223, 232, 2, 240, 17, 2, 7, 12, 208, 248, 24, 128, 2, 36, 26, ++ 79, 34, 224, 208, 248, 16, 128, 4, 36, 25, 79, 29, 224, 208, 248, 124, ++ 128, 64, 36, 23, 79, 24, 224, 144, 248, 120, 48, 115, 177, 199, 111, ++ 56, 70, 40, 240, 41, 217, 180, 248, 122, 16, 56, 70, 141, 66, 56, 191, ++ 13, 70, 105, 26, 15, 74, 51, 70, 40, 240, 208, 216, 212, 248, 20, 128, ++ 1, 224, 208, 248, 20, 128, 12, 79, 1, 36, 64, 70, 40, 240, 20, 217, ++ 41, 70, 58, 70, 64, 70, 51, 70, 40, 240, 192, 216, 48, 70, 33, 70, 1, ++ 34, 189, 232, 240, 65, 254, 243, 109, 182, 0, 191, 113, 188, 133, 0, ++ 173, 187, 133, 0, 65, 196, 2, 0, 91, 195, 2, 0, 2, 41, 112, 181, 5, ++ 104, 13, 208, 3, 41, 17, 208, 1, 41, 18, 209, 255, 34, 128, 248, 35, ++ 32, 2, 33, 0, 34, 132, 105, 2, 38, 47, 240, 107, 217, 10, 224, 255, ++ 34, 4, 105, 128, 248, 36, 32, 4, 38, 4, 224, 196, 111, 64, 38, 1, 224, ++ 68, 105, 1, 38, 32, 70, 40, 240, 222, 216, 40, 70, 49, 70, 0, 34, 189, ++ 232, 112, 64, 254, 243, 61, 182, 240, 181, 4, 70, 133, 176, 21, 70, ++ 31, 70, 14, 70, 0, 41, 49, 208, 138, 121, 226, 177, 208, 248, 36, 1, ++ 1, 169, 0, 34, 63, 240, 219, 216, 13, 224, 3, 105, 179, 66, 10, 209, ++ 144, 248, 36, 48, 154, 7, 6, 213, 9, 45, 4, 209, 214, 248, 204, 48, ++ 155, 4, 0, 213, 215, 177, 212, 248, 36, 1, 1, 169, 17, 240, 111, 253, ++ 0, 40, 234, 209, 15, 224, 1, 61, 237, 178, 1, 45, 11, 216, 208, 248, ++ 36, 1, 1, 169, 63, 240, 187, 216, 212, 248, 36, 1, 1, 169, 17, 240, ++ 94, 253, 0, 40, 248, 209, 160, 104, 225, 247, 105, 248, 0, 32, 5, 176, ++ 240, 189, 45, 233, 240, 71, 4, 70, 13, 70, 106, 177, 144, 248, 116, ++ 50, 89, 7, 2, 212, 46, 240, 47, 218, 48, 177, 212, 248, 84, 49, 147, ++ 248, 48, 48, 0, 43, 0, 240, 148, 128, 111, 104, 32, 70, 57, 70, 181, ++ 248, 8, 128, 180, 248, 72, 148, 48, 240, 46, 220, 148, 248, 176, 53, ++ 6, 70, 164, 248, 70, 132, 43, 177, 32, 70, 57, 70, 189, 232, 240, 71, ++ 0, 240, 102, 158, 212, 248, 168, 53, 187, 66, 8, 209, 72, 70, 217, 243, ++ 141, 243, 130, 70, 64, 70, 217, 243, 137, 243, 130, 69, 113, 208, 212, ++ 248, 168, 53, 187, 66, 5, 209, 72, 70, 217, 243, 128, 243, 64, 70, 217, ++ 243, 125, 243, 32, 70, 4, 240, 58, 218, 212, 248, 168, 53, 187, 66, ++ 3, 208, 32, 70, 57, 70, 0, 240, 68, 222, 193, 69, 67, 208, 35, 106, ++ 1, 34, 24, 105, 79, 244, 128, 81, 2, 240, 251, 250, 32, 70, 65, 70, ++ 2, 240, 247, 222, 35, 106, 0, 34, 24, 105, 79, 244, 128, 81, 2, 240, ++ 240, 250, 212, 248, 84, 49, 219, 109, 3, 43, 13, 209, 32, 70, 57, 70, ++ 48, 240, 227, 219, 64, 177, 208, 248, 204, 16, 32, 70, 193, 243, 64, ++ 49, 129, 240, 1, 1, 46, 240, 229, 222, 148, 248, 114, 50, 179, 177, ++ 32, 70, 57, 70, 48, 240, 210, 219, 2, 70, 32, 177, 131, 121, 19, 177, ++ 32, 70, 0, 33, 7, 224, 32, 70, 57, 70, 48, 240, 239, 219, 2, 70, 40, ++ 177, 32, 70, 1, 33, 79, 240, 255, 51, 40, 240, 59, 219, 212, 248, 84, ++ 1, 41, 70, 255, 247, 48, 253, 32, 70, 28, 240, 217, 221, 24, 177, 32, ++ 70, 41, 70, 255, 247, 107, 253, 32, 70, 254, 243, 151, 241, 150, 248, ++ 57, 51, 67, 185, 212, 248, 164, 21, 75, 137, 35, 177, 32, 70, 189, 232, ++ 240, 71, 231, 247, 244, 185, 189, 232, 240, 135, 45, 233, 248, 67, 5, ++ 104, 4, 70, 149, 248, 116, 50, 14, 70, 88, 7, 3, 212, 40, 70, 46, 240, ++ 133, 217, 56, 177, 35, 104, 211, 248, 84, 49, 147, 248, 48, 48, 0, 43, ++ 0, 240, 154, 128, 148, 248, 48, 112, 0, 47, 64, 240, 149, 128, 214, ++ 248, 40, 51, 24, 137, 217, 243, 244, 242, 128, 70, 181, 248, 70, 4, ++ 217, 243, 239, 242, 128, 69, 10, 208, 181, 248, 70, 4, 217, 243, 233, ++ 242, 128, 70, 181, 248, 72, 4, 217, 243, 228, 242, 128, 69, 4, 208, ++ 32, 104, 214, 248, 40, 19, 0, 34, 116, 224, 32, 70, 181, 248, 72, 20, ++ 46, 240, 72, 222, 128, 70, 0, 40, 112, 208, 99, 108, 99, 177, 179, 66, ++ 11, 208, 148, 248, 144, 48, 1, 59, 219, 178, 132, 248, 144, 48, 0, 43, ++ 100, 209, 99, 100, 189, 232, 248, 131, 31, 70, 213, 248, 104, 50, 83, ++ 248, 7, 144, 185, 241, 0, 15, 59, 208, 153, 248, 6, 48, 0, 43, 55, 209, ++ 153, 248, 8, 48, 0, 43, 51, 208, 217, 248, 40, 51, 67, 69, 47, 209, ++ 213, 248, 80, 1, 73, 70, 54, 240, 211, 221, 217, 248, 4, 49, 90, 108, ++ 16, 177, 66, 240, 4, 2, 1, 224, 66, 240, 2, 2, 90, 100, 26, 122, 18, ++ 177, 155, 122, 227, 177, 13, 224, 153, 248, 57, 35, 194, 185, 27, 120, ++ 2, 43, 2, 209, 72, 70, 56, 240, 43, 218, 1, 33, 72, 70, 10, 70, 255, ++ 243, 50, 245, 196, 248, 44, 128, 152, 248, 10, 48, 132, 248, 48, 48, ++ 51, 177, 214, 248, 40, 51, 163, 98, 150, 248, 68, 48, 132, 248, 37, ++ 48, 4, 55, 32, 47, 185, 209, 148, 248, 48, 48, 35, 177, 32, 104, 189, ++ 232, 248, 67, 255, 243, 91, 183, 148, 248, 73, 32, 66, 177, 150, 248, ++ 68, 48, 32, 70, 132, 248, 37, 48, 189, 232, 248, 67, 46, 240, 33, 154, ++ 32, 104, 214, 248, 40, 19, 189, 232, 248, 67, 255, 247, 168, 190, 189, ++ 232, 248, 131, 45, 233, 255, 65, 6, 70, 80, 248, 28, 75, 15, 70, 177, ++ 248, 8, 128, 77, 104, 46, 240, 59, 222, 243, 106, 187, 66, 1, 209, 0, ++ 35, 243, 98, 56, 70, 223, 247, 242, 251, 35, 106, 65, 70, 24, 105, 3, ++ 240, 30, 250, 243, 105, 51, 185, 0, 147, 96, 104, 41, 29, 1, 34, 216, ++ 243, 194, 247, 41, 224, 212, 248, 168, 37, 149, 66, 4, 209, 32, 70, ++ 25, 70, 0, 34, 255, 247, 124, 254, 212, 248, 104, 18, 0, 35, 202, 88, ++ 50, 177, 210, 104, 208, 104, 168, 66, 4, 191, 212, 248, 168, 5, 208, ++ 96, 4, 51, 32, 43, 243, 209, 4, 224, 35, 104, 1, 34, 88, 105, 223, 247, ++ 249, 251, 3, 169, 40, 29, 216, 243, 59, 247, 1, 70, 0, 40, 243, 209, ++ 32, 70, 97, 104, 42, 70, 4, 240, 175, 220, 189, 232, 255, 129, 45, 233, ++ 240, 79, 209, 248, 40, 115, 11, 122, 135, 176, 5, 70, 14, 70, 146, 70, ++ 208, 248, 84, 65, 5, 147, 0, 47, 0, 240, 232, 128, 203, 104, 217, 104, ++ 48, 240, 184, 218, 0, 35, 51, 114, 198, 248, 40, 51, 123, 104, 128, ++ 70, 211, 248, 204, 48, 67, 179, 186, 241, 0, 15, 2, 208, 202, 248, 0, ++ 48, 34, 224, 105, 104, 40, 70, 4, 240, 103, 220, 122, 104, 243, 104, ++ 210, 248, 204, 32, 129, 70, 211, 248, 12, 176, 73, 70, 192, 248, 204, ++ 32, 216, 96, 40, 70, 230, 247, 20, 254, 83, 70, 104, 104, 9, 241, 4, ++ 1, 1, 34, 205, 248, 0, 160, 216, 243, 88, 247, 40, 70, 105, 104, 74, ++ 70, 4, 240, 107, 220, 243, 104, 195, 248, 12, 176, 32, 70, 57, 70, 50, ++ 70, 48, 240, 239, 216, 64, 185, 32, 70, 57, 70, 46, 240, 154, 216, 32, ++ 70, 57, 70, 255, 247, 96, 255, 16, 224, 49, 70, 40, 70, 255, 247, 120, ++ 251, 129, 70, 1, 35, 32, 70, 57, 70, 74, 70, 46, 240, 88, 217, 43, 104, ++ 147, 248, 61, 48, 11, 185, 165, 248, 70, 148, 5, 155, 40, 70, 51, 114, ++ 33, 70, 255, 247, 218, 252, 0, 35, 99, 103, 148, 249, 32, 32, 213, 248, ++ 104, 50, 83, 248, 34, 144, 185, 241, 0, 15, 27, 208, 153, 248, 6, 48, ++ 195, 177, 217, 248, 204, 48, 153, 4, 20, 213, 43, 104, 147, 248, 61, ++ 112, 135, 185, 73, 70, 58, 70, 59, 70, 40, 70, 0, 151, 1, 151, 2, 151, ++ 3, 151, 46, 240, 244, 221, 40, 70, 57, 70, 74, 70, 79, 240, 255, 51, ++ 40, 240, 141, 217, 184, 241, 0, 15, 26, 208, 152, 248, 6, 48, 123, 185, ++ 216, 248, 204, 48, 154, 4, 11, 213, 216, 3, 9, 212, 213, 248, 80, 1, ++ 65, 70, 54, 240, 152, 220, 64, 177, 32, 70, 65, 70, 4, 34, 2, 224, 32, ++ 70, 65, 70, 2, 34, 255, 247, 54, 252, 64, 70, 28, 240, 231, 216, 148, ++ 249, 32, 32, 150, 249, 68, 48, 154, 66, 47, 209, 213, 248, 104, 194, ++ 0, 33, 79, 246, 255, 112, 255, 34, 92, 248, 1, 48, 195, 177, 211, 248, ++ 40, 115, 175, 177, 179, 66, 19, 208, 147, 248, 6, 128, 184, 241, 0, ++ 15, 3, 209, 214, 248, 40, 131, 71, 69, 2, 209, 147, 248, 68, 32, 10, ++ 224, 211, 248, 244, 112, 255, 141, 135, 66, 60, 191, 147, 248, 68, 32, ++ 56, 70, 4, 49, 32, 41, 224, 209, 83, 178, 89, 28, 9, 191, 148, 248, ++ 33, 32, 132, 248, 32, 32, 132, 248, 32, 32, 132, 248, 33, 48, 43, 104, ++ 147, 248, 61, 48, 75, 177, 32, 70, 49, 70, 255, 247, 145, 250, 132, ++ 248, 33, 0, 32, 70, 255, 247, 173, 250, 2, 224, 255, 35, 132, 248, 33, ++ 48, 0, 32, 7, 176, 189, 232, 240, 143, 45, 233, 240, 79, 203, 104, 208, ++ 248, 84, 65, 133, 176, 13, 70, 209, 248, 40, 147, 211, 248, 12, 160, ++ 6, 70, 0, 35, 32, 70, 17, 70, 23, 70, 3, 147, 46, 240, 119, 220, 165, ++ 248, 46, 115, 128, 70, 185, 241, 0, 15, 67, 208, 235, 104, 79, 244, ++ 128, 114, 217, 104, 48, 70, 230, 247, 128, 252, 16, 241, 0, 11, 185, ++ 248, 8, 0, 24, 191, 79, 240, 1, 11, 217, 243, 241, 240, 3, 70, 56, 70, ++ 1, 147, 217, 243, 236, 240, 1, 155, 131, 66, 31, 209, 185, 248, 8, 48, ++ 187, 66, 0, 240, 136, 128, 32, 70, 73, 70, 42, 70, 48, 240, 3, 216, ++ 56, 177, 32, 70, 73, 70, 58, 70, 45, 240, 209, 223, 0, 40, 0, 240, 130, ++ 128, 48, 70, 41, 70, 254, 243, 44, 241, 135, 66, 115, 209, 32, 70, 73, ++ 70, 58, 70, 1, 35, 46, 240, 108, 216, 108, 224, 32, 70, 73, 70, 42, ++ 70, 47, 240, 232, 223, 48, 185, 48, 70, 41, 70, 3, 170, 255, 247, 169, ++ 254, 0, 224, 203, 70, 184, 241, 0, 15, 6, 209, 32, 70, 57, 70, 45, 240, ++ 207, 223, 128, 70, 0, 40, 91, 208, 216, 248, 4, 16, 235, 104, 138, 69, ++ 217, 96, 197, 248, 40, 131, 24, 208, 95, 250, 139, 242, 114, 177, 48, ++ 70, 1, 34, 79, 244, 128, 115, 230, 247, 167, 252, 48, 70, 81, 70, 46, ++ 240, 51, 223, 80, 177, 48, 70, 81, 70, 0, 34, 2, 224, 3, 155, 35, 177, ++ 48, 70, 79, 244, 128, 115, 230, 247, 151, 252, 184, 248, 8, 48, 7, 244, ++ 96, 82, 3, 244, 96, 83, 154, 66, 5, 221, 32, 70, 65, 70, 58, 70, 1, ++ 35, 46, 240, 37, 216, 48, 70, 33, 70, 255, 247, 175, 251, 171, 121, ++ 123, 185, 148, 249, 32, 48, 88, 28, 11, 208, 214, 248, 104, 18, 213, ++ 248, 244, 32, 81, 248, 35, 48, 210, 141, 211, 248, 244, 48, 219, 141, ++ 154, 66, 3, 210, 149, 248, 68, 48, 132, 248, 32, 48, 51, 104, 147, 248, ++ 61, 0, 80, 177, 32, 70, 0, 33, 255, 247, 203, 249, 132, 248, 33, 0, ++ 32, 70, 255, 247, 231, 249, 0, 32, 5, 224, 255, 35, 132, 248, 33, 48, ++ 1, 224, 111, 240, 26, 0, 5, 176, 189, 232, 240, 143, 112, 181, 144, ++ 248, 48, 48, 4, 70, 6, 104, 0, 43, 32, 208, 195, 106, 19, 177, 155, ++ 122, 0, 43, 27, 209, 32, 70, 255, 247, 140, 249, 148, 248, 73, 80, 0, ++ 35, 161, 106, 132, 248, 48, 48, 163, 98, 227, 98, 37, 177, 32, 70, 189, ++ 232, 112, 64, 45, 240, 234, 159, 48, 70, 1, 34, 255, 247, 116, 252, ++ 32, 70, 2, 33, 42, 70, 189, 232, 112, 64, 46, 240, 133, 157, 112, 189, ++ 45, 233, 240, 79, 145, 176, 10, 147, 11, 121, 128, 70, 13, 70, 9, 146, ++ 208, 248, 84, 65, 0, 43, 0, 240, 150, 129, 148, 248, 49, 112, 31, 177, ++ 1, 63, 132, 248, 49, 112, 127, 225, 148, 248, 33, 48, 7, 43, 0, 242, ++ 141, 129, 208, 248, 104, 34, 91, 178, 82, 248, 35, 96, 0, 46, 0, 240, ++ 133, 129, 51, 122, 0, 43, 0, 240, 132, 129, 208, 248, 72, 1, 49, 70, ++ 49, 240, 60, 221, 2, 70, 168, 185, 212, 248, 164, 48, 64, 70, 9, 43, ++ 9, 220, 214, 248, 40, 19, 255, 247, 55, 252, 212, 248, 164, 48, 1, 51, ++ 196, 248, 164, 48, 3, 224, 213, 248, 40, 19, 255, 247, 45, 252, 0, 35, ++ 99, 99, 81, 225, 148, 249, 35, 48, 196, 248, 164, 112, 1, 51, 5, 209, ++ 216, 248, 84, 1, 41, 70, 9, 154, 255, 247, 199, 252, 214, 248, 244, ++ 48, 12, 175, 219, 141, 13, 241, 52, 10, 49, 70, 11, 147, 216, 248, 72, ++ 1, 10, 154, 9, 155, 0, 151, 205, 248, 4, 160, 49, 240, 7, 218, 214, ++ 248, 244, 48, 57, 70, 216, 141, 82, 70, 74, 240, 0, 217, 49, 70, 13, ++ 154, 216, 248, 72, 1, 49, 240, 142, 218, 213, 248, 244, 48, 6, 70, 179, ++ 248, 46, 144, 216, 248, 72, 1, 41, 70, 10, 154, 9, 155, 141, 232, 128, ++ 4, 49, 240, 236, 217, 213, 248, 244, 48, 57, 70, 216, 141, 82, 70, 74, ++ 240, 229, 216, 13, 154, 41, 70, 216, 248, 72, 1, 49, 240, 115, 218, ++ 79, 234, 137, 41, 7, 70, 0, 235, 9, 10, 32, 70, 46, 240, 255, 221, 59, ++ 26, 32, 70, 7, 147, 46, 240, 250, 221, 32, 70, 46, 240, 247, 221, 192, ++ 235, 10, 10, 32, 70, 46, 240, 242, 221, 7, 155, 55, 26, 199, 235, 10, ++ 12, 195, 235, 7, 11, 139, 234, 235, 114, 162, 235, 235, 114, 140, 234, ++ 236, 118, 166, 235, 236, 118, 150, 66, 168, 191, 22, 70, 71, 242, 48, ++ 82, 150, 66, 68, 216, 226, 109, 2, 42, 65, 208, 179, 69, 4, 208, 27, ++ 235, 6, 15, 24, 191, 202, 235, 7, 11, 10, 153, 9, 154, 187, 241, 0, ++ 15, 79, 234, 89, 3, 204, 191, 198, 235, 3, 3, 243, 24, 14, 145, 15, ++ 146, 14, 168, 15, 169, 0, 34, 74, 240, 176, 216, 12, 175, 13, 174, 216, ++ 248, 72, 1, 41, 70, 14, 154, 15, 155, 0, 151, 1, 150, 49, 240, 143, ++ 217, 213, 248, 244, 48, 57, 70, 216, 141, 50, 70, 74, 240, 136, 216, ++ 216, 248, 72, 1, 41, 70, 12, 154, 13, 155, 0, 151, 1, 150, 49, 240, ++ 25, 218, 10, 155, 9, 153, 0, 147, 13, 155, 1, 145, 2, 147, 0, 35, 4, ++ 147, 205, 248, 12, 144, 64, 70, 41, 70, 14, 154, 15, 155, 152, 224, ++ 213, 248, 204, 0, 16, 244, 0, 80, 0, 240, 175, 128, 216, 248, 80, 1, ++ 41, 70, 7, 147, 205, 248, 32, 192, 54, 240, 74, 218, 7, 155, 221, 248, ++ 32, 192, 104, 177, 98, 107, 90, 177, 146, 27, 18, 245, 122, 127, 7, ++ 219, 178, 245, 122, 127, 4, 220, 148, 248, 104, 0, 0, 40, 0, 240, 149, ++ 128, 0, 34, 132, 248, 104, 32, 226, 109, 1, 42, 1, 208, 3, 42, 44, 209, ++ 35, 110, 195, 241, 100, 3, 75, 43, 3, 216, 24, 43, 152, 191, 25, 35, ++ 0, 224, 75, 35, 11, 153, 195, 241, 100, 3, 138, 2, 83, 67, 100, 33, ++ 227, 69, 179, 251, 241, 243, 7, 216, 218, 25, 82, 69, 12, 217, 178, ++ 235, 10, 3, 9, 208, 251, 26, 9, 224, 195, 235, 10, 3, 187, 66, 5, 217, ++ 218, 27, 3, 208, 194, 235, 10, 2, 59, 70, 0, 224, 82, 70, 210, 26, 141, ++ 232, 12, 0, 2, 35, 2, 147, 106, 224, 2, 42, 73, 209, 79, 244, 200, 66, ++ 187, 245, 224, 79, 162, 101, 2, 218, 203, 245, 24, 67, 6, 224, 187, ++ 245, 60, 79, 84, 221, 9, 245, 24, 67, 203, 235, 3, 3, 10, 154, 9, 153, ++ 15, 146, 14, 145, 15, 168, 14, 169, 0, 34, 74, 240, 22, 216, 12, 175, ++ 13, 174, 216, 248, 72, 1, 41, 70, 15, 154, 14, 155, 0, 151, 1, 150, ++ 49, 240, 245, 216, 213, 248, 244, 48, 57, 70, 216, 141, 50, 70, 73, ++ 240, 238, 223, 216, 248, 72, 1, 41, 70, 12, 154, 13, 155, 0, 151, 1, ++ 150, 49, 240, 127, 217, 9, 155, 10, 154, 1, 147, 13, 155, 0, 146, 2, ++ 147, 0, 35, 4, 147, 15, 154, 14, 155, 205, 248, 12, 144, 64, 70, 41, ++ 70, 230, 247, 27, 248, 2, 35, 132, 248, 49, 48, 111, 240, 24, 0, 19, ++ 224, 1, 34, 3, 146, 64, 70, 41, 70, 74, 70, 205, 248, 0, 160, 1, 151, ++ 2, 150, 46, 240, 240, 218, 7, 224, 111, 240, 3, 0, 4, 224, 79, 240, ++ 255, 48, 1, 224, 111, 240, 16, 0, 17, 176, 189, 232, 240, 143, 0, 146, ++ 185, 251, 242, 242, 3, 245, 200, 67, 210, 178, 1, 147, 2, 146, 64, 70, ++ 41, 70, 74, 70, 51, 70, 46, 240, 110, 219, 237, 231, 8, 181, 208, 248, ++ 84, 49, 147, 248, 48, 32, 98, 177, 1, 34, 131, 248, 174, 32, 219, 106, ++ 59, 177, 89, 104, 47, 240, 235, 222, 130, 33, 189, 232, 8, 64, 4, 240, ++ 194, 153, 8, 189, 45, 233, 248, 67, 3, 104, 5, 70, 27, 126, 0, 43, 105, ++ 208, 0, 105, 39, 240, 125, 222, 128, 70, 32, 177, 168, 104, 189, 232, ++ 248, 67, 224, 247, 63, 189, 213, 248, 84, 65, 32, 70, 46, 240, 251, ++ 220, 6, 70, 40, 185, 32, 70, 49, 70, 189, 232, 248, 67, 255, 247, 25, ++ 186, 132, 248, 172, 128, 2, 121, 7, 42, 67, 216, 213, 248, 104, 50, ++ 82, 178, 83, 248, 34, 112, 0, 47, 60, 208, 215, 248, 40, 147, 185, 241, ++ 0, 15, 55, 208, 148, 248, 32, 32, 7, 42, 154, 191, 82, 178, 83, 248, ++ 34, 48, 67, 70, 155, 121, 35, 185, 32, 70, 255, 247, 170, 248, 2, 70, ++ 104, 177, 40, 70, 255, 247, 171, 255, 40, 70, 73, 70, 0, 34, 255, 247, ++ 85, 250, 32, 70, 2, 33, 0, 34, 46, 240, 104, 219, 4, 224, 213, 248, ++ 84, 1, 57, 70, 255, 247, 243, 250, 179, 104, 155, 177, 234, 104, 32, ++ 70, 210, 248, 128, 17, 242, 104, 145, 66, 140, 191, 194, 235, 1, 1, ++ 0, 33, 200, 49, 139, 66, 140, 191, 193, 235, 3, 1, 1, 33, 0, 34, 255, ++ 247, 133, 249, 3, 224, 32, 70, 0, 33, 255, 247, 204, 249, 32, 70, 49, ++ 70, 189, 232, 248, 67, 46, 240, 144, 156, 189, 232, 248, 131, 56, 181, ++ 208, 248, 168, 21, 4, 70, 47, 240, 108, 222, 3, 33, 5, 70, 212, 248, ++ 84, 1, 255, 247, 184, 249, 32, 70, 41, 70, 10, 34, 0, 35, 255, 247, ++ 217, 249, 117, 177, 173, 121, 101, 185, 212, 248, 168, 21, 32, 70, 47, ++ 240, 128, 222, 1, 70, 212, 248, 84, 1, 42, 70, 189, 232, 56, 64, 255, ++ 247, 175, 186, 56, 189, 45, 233, 240, 65, 3, 104, 7, 70, 147, 248, 60, ++ 32, 208, 248, 84, 81, 14, 104, 140, 104, 209, 248, 12, 128, 0, 42, 84, ++ 208, 147, 248, 61, 48, 0, 43, 80, 208, 208, 248, 72, 1, 49, 70, 49, ++ 240, 232, 218, 0, 40, 73, 208, 151, 248, 114, 50, 91, 185, 150, 248, ++ 48, 35, 149, 248, 67, 48, 154, 66, 5, 217, 107, 108, 27, 185, 3, 35, ++ 110, 100, 133, 248, 144, 48, 179, 121, 75, 185, 51, 124, 59, 177, 149, ++ 248, 72, 48, 35, 177, 150, 248, 48, 51, 1, 51, 134, 248, 48, 51, 40, ++ 70, 255, 247, 25, 248, 149, 248, 173, 16, 120, 177, 0, 41, 38, 209, ++ 1, 35, 40, 70, 133, 248, 173, 48, 133, 248, 172, 16, 233, 101, 255, ++ 247, 92, 249, 40, 70, 189, 232, 240, 65, 47, 240, 81, 159, 17, 177, ++ 40, 70, 255, 247, 151, 248, 149, 249, 32, 32, 150, 249, 68, 48, 154, ++ 66, 14, 209, 179, 121, 56, 70, 49, 70, 66, 70, 35, 177, 35, 70, 189, ++ 232, 240, 65, 255, 247, 59, 189, 35, 70, 189, 232, 240, 65, 46, 240, ++ 132, 156, 189, 232, 240, 129, 45, 233, 240, 71, 145, 248, 6, 144, 5, ++ 70, 136, 70, 23, 70, 208, 248, 84, 65, 185, 241, 0, 15, 4, 209, 1, 35, ++ 129, 248, 56, 147, 129, 248, 57, 51, 43, 104, 147, 248, 60, 32, 0, 42, ++ 0, 240, 131, 128, 147, 248, 61, 48, 0, 43, 126, 208, 213, 248, 84, 1, ++ 152, 248, 68, 32, 144, 248, 32, 48, 147, 66, 89, 178, 8, 191, 144, 249, ++ 33, 16, 7, 41, 13, 220, 0, 41, 11, 219, 147, 66, 213, 248, 104, 18, ++ 94, 178, 3, 209, 144, 249, 33, 48, 155, 0, 0, 224, 179, 0, 206, 88, ++ 0, 224, 0, 38, 185, 241, 0, 15, 26, 208, 163, 107, 163, 177, 99, 104, ++ 51, 177, 32, 70, 0, 33, 255, 247, 250, 248, 32, 70, 47, 240, 241, 222, ++ 32, 70, 161, 107, 0, 34, 255, 247, 166, 248, 0, 34, 32, 70, 152, 248, ++ 68, 16, 19, 70, 47, 240, 201, 222, 213, 248, 84, 1, 49, 70, 63, 224, ++ 216, 248, 244, 48, 179, 248, 46, 160, 148, 248, 172, 48, 0, 43, 60, ++ 209, 99, 108, 67, 69, 51, 208, 58, 70, 49, 70, 255, 247, 229, 249, 235, ++ 104, 73, 70, 32, 70, 211, 248, 128, 97, 255, 247, 209, 248, 32, 70, ++ 47, 240, 200, 222, 213, 248, 72, 81, 65, 70, 40, 70, 48, 240, 118, 221, ++ 24, 33, 65, 67, 40, 70, 74, 49, 49, 240, 60, 216, 227, 143, 79, 234, ++ 138, 42, 246, 24, 198, 235, 10, 6, 192, 1, 247, 25, 63, 24, 57, 70, ++ 32, 70, 74, 70, 255, 247, 104, 248, 59, 70, 32, 70, 152, 248, 68, 16, ++ 74, 70, 47, 240, 139, 222, 1, 35, 132, 248, 172, 48, 189, 232, 240, ++ 135, 65, 70, 58, 70, 189, 232, 240, 71, 255, 247, 175, 185, 189, 232, ++ 240, 135, 45, 233, 247, 79, 139, 121, 6, 70, 12, 70, 145, 70, 67, 185, ++ 2, 104, 146, 106, 129, 248, 57, 51, 193, 248, 52, 35, 1, 34, 129, 248, ++ 56, 35, 51, 104, 147, 248, 60, 32, 0, 42, 0, 240, 163, 128, 147, 248, ++ 61, 48, 0, 43, 0, 240, 158, 128, 214, 248, 84, 33, 148, 248, 68, 16, ++ 146, 248, 32, 48, 139, 66, 88, 178, 8, 191, 146, 249, 33, 0, 7, 40, ++ 13, 220, 0, 40, 11, 219, 139, 66, 214, 248, 104, 2, 93, 178, 3, 209, ++ 146, 249, 33, 48, 155, 0, 0, 224, 171, 0, 199, 88, 0, 224, 0, 39, 212, ++ 248, 244, 48, 88, 142, 216, 243, 132, 244, 182, 248, 72, 4, 216, 243, ++ 128, 244, 163, 121, 214, 248, 84, 81, 75, 177, 149, 249, 35, 48, 1, ++ 51, 87, 209, 40, 70, 33, 70, 74, 70, 255, 247, 96, 249, 81, 224, 149, ++ 248, 172, 128, 181, 248, 62, 160, 184, 241, 0, 15, 99, 209, 107, 108, ++ 187, 66, 65, 208, 66, 70, 48, 70, 212, 248, 40, 19, 255, 247, 166, 248, ++ 214, 248, 84, 1, 33, 70, 46, 240, 207, 218, 214, 248, 72, 177, 33, 70, ++ 88, 70, 48, 240, 229, 220, 24, 33, 65, 67, 88, 70, 72, 49, 48, 240, ++ 171, 223, 2, 169, 192, 1, 65, 248, 4, 13, 72, 70, 49, 240, 224, 217, ++ 148, 248, 68, 48, 65, 70, 133, 248, 36, 48, 243, 104, 40, 70, 211, 248, ++ 128, 145, 255, 247, 31, 248, 40, 70, 47, 240, 22, 222, 1, 155, 40, 70, ++ 200, 59, 201, 235, 3, 9, 202, 235, 9, 10, 81, 70, 66, 70, 254, 247, ++ 197, 255, 83, 70, 40, 70, 151, 248, 68, 16, 66, 70, 47, 240, 232, 221, ++ 1, 35, 133, 248, 172, 48, 5, 224, 40, 70, 57, 70, 74, 70, 255, 247, ++ 14, 249, 24, 224, 163, 121, 179, 177, 214, 248, 84, 1, 195, 143, 176, ++ 248, 122, 32, 210, 24, 111, 240, 199, 3, 155, 26, 212, 248, 244, 32, ++ 209, 141, 208, 248, 140, 32, 137, 2, 177, 251, 242, 241, 130, 107, 137, ++ 26, 89, 24, 3, 34, 254, 247, 155, 255, 189, 232, 254, 143, 248, 181, ++ 22, 70, 66, 126, 4, 70, 15, 70, 194, 177, 72, 242, 2, 2, 72, 242, 14, ++ 5, 48, 70, 0, 43, 8, 191, 21, 70, 220, 247, 55, 254, 0, 40, 24, 191, ++ 0, 37, 122, 28, 20, 191, 57, 70, 111, 240, 1, 1, 32, 70, 50, 70, 43, ++ 70, 5, 240, 184, 218, 0, 32, 248, 189, 111, 240, 10, 0, 248, 189, 45, ++ 233, 240, 65, 12, 70, 7, 104, 5, 70, 48, 240, 50, 223, 6, 70, 4, 241, ++ 194, 2, 56, 70, 49, 70, 48, 240, 53, 220, 212, 248, 204, 48, 218, 3, ++ 13, 212, 162, 121, 114, 185, 3, 244, 0, 83, 0, 43, 12, 191, 17, 39, ++ 129, 39, 12, 191, 79, 240, 25, 8, 79, 240, 193, 8, 5, 224, 33, 39, 184, ++ 70, 2, 224, 65, 39, 79, 240, 193, 8, 33, 70, 40, 70, 48, 240, 71, 220, ++ 128, 178, 71, 234, 0, 36, 79, 246, 241, 115, 40, 70, 49, 70, 72, 244, ++ 64, 114, 35, 64, 48, 240, 245, 218, 0, 32, 189, 232, 240, 129, 45, 233, ++ 240, 79, 155, 70, 67, 104, 139, 176, 203, 88, 4, 70, 13, 70, 147, 248, ++ 6, 160, 22, 70, 79, 240, 24, 9, 0, 42, 110, 208, 9, 251, 10, 249, 31, ++ 139, 9, 241, 62, 3, 25, 70, 3, 147, 48, 240, 236, 222, 79, 246, 254, ++ 118, 5, 171, 41, 70, 4, 170, 6, 64, 32, 70, 48, 240, 233, 222, 4, 153, ++ 5, 154, 56, 70, 73, 240, 86, 220, 4, 155, 128, 70, 6, 147, 5, 155, 6, ++ 168, 7, 147, 7, 169, 67, 70, 0, 34, 73, 240, 229, 220, 43, 122, 27, ++ 185, 171, 121, 11, 185, 43, 124, 67, 185, 191, 2, 6, 168, 7, 169, 0, ++ 34, 59, 70, 73, 240, 192, 220, 200, 235, 7, 8, 8, 171, 0, 147, 9, 171, ++ 1, 147, 32, 70, 7, 155, 41, 70, 6, 154, 48, 240, 56, 222, 43, 122, 51, ++ 187, 79, 234, 219, 19, 179, 235, 216, 31, 32, 70, 16, 217, 9, 241, 66, ++ 1, 48, 240, 174, 222, 64, 185, 9, 154, 32, 70, 90, 68, 210, 9, 9, 241, ++ 68, 1, 146, 178, 49, 240, 142, 216, 70, 240, 1, 6, 15, 224, 41, 70, ++ 48, 240, 52, 221, 1, 35, 10, 241, 4, 2, 19, 250, 2, 242, 3, 250, 10, ++ 250, 66, 234, 10, 3, 152, 66, 8, 191, 70, 240, 2, 6, 79, 234, 219, 18, ++ 32, 70, 9, 241, 66, 1, 146, 178, 49, 240, 115, 216, 32, 70, 3, 153, ++ 8, 224, 9, 251, 10, 250, 10, 241, 66, 1, 49, 240, 106, 216, 32, 70, ++ 10, 241, 68, 1, 50, 70, 49, 240, 100, 216, 11, 176, 189, 232, 240, 143, ++ 45, 233, 240, 71, 136, 176, 4, 70, 13, 70, 23, 70, 208, 248, 0, 160, ++ 48, 240, 161, 219, 6, 70, 0, 47, 106, 208, 99, 104, 85, 248, 3, 128, ++ 43, 122, 19, 177, 213, 248, 244, 48, 1, 224, 213, 248, 240, 48, 223, ++ 141, 32, 70, 3, 171, 168, 248, 24, 112, 41, 70, 2, 170, 48, 240, 93, ++ 222, 56, 70, 2, 153, 3, 154, 73, 240, 202, 219, 2, 155, 129, 70, 4, ++ 147, 3, 155, 4, 168, 5, 147, 5, 169, 75, 70, 0, 34, 73, 240, 89, 220, ++ 43, 122, 191, 2, 27, 185, 171, 121, 11, 185, 43, 124, 155, 185, 216, ++ 248, 36, 48, 4, 168, 5, 169, 83, 177, 0, 34, 73, 240, 50, 220, 216, ++ 248, 36, 48, 75, 69, 7, 210, 4, 168, 5, 169, 0, 34, 0, 224, 26, 70, ++ 59, 70, 73, 240, 38, 220, 6, 171, 0, 147, 7, 171, 41, 70, 4, 154, 1, ++ 147, 32, 70, 5, 155, 48, 240, 160, 221, 40, 70, 225, 247, 77, 250, 218, ++ 248, 28, 55, 7, 157, 25, 104, 2, 70, 45, 26, 9, 177, 91, 104, 237, 26, ++ 6, 241, 95, 1, 32, 70, 73, 0, 48, 240, 250, 223, 24, 35, 94, 67, 234, ++ 9, 32, 70, 6, 241, 64, 1, 146, 178, 48, 240, 241, 223, 255, 9, 79, 246, ++ 248, 114, 32, 70, 6, 241, 58, 1, 58, 64, 30, 224, 218, 248, 16, 0, 39, ++ 240, 209, 218, 5, 70, 208, 185, 24, 39, 119, 67, 32, 70, 7, 241, 58, ++ 1, 42, 70, 48, 240, 219, 223, 32, 70, 7, 241, 64, 1, 42, 70, 48, 240, ++ 213, 223, 6, 241, 95, 1, 32, 70, 73, 0, 42, 70, 48, 240, 206, 223, 32, ++ 70, 7, 241, 62, 1, 42, 70, 48, 240, 200, 223, 8, 176, 189, 232, 240, ++ 135, 240, 181, 22, 70, 133, 176, 5, 70, 12, 70, 7, 104, 48, 240, 41, ++ 222, 38, 185, 40, 70, 33, 70, 48, 240, 230, 221, 39, 224, 107, 104, ++ 212, 248, 244, 32, 227, 88, 210, 141, 56, 70, 26, 131, 2, 169, 3, 170, ++ 229, 247, 233, 251, 163, 121, 11, 185, 34, 124, 90, 185, 40, 70, 33, ++ 70, 3, 154, 2, 155, 48, 240, 198, 217, 40, 70, 33, 70, 1, 34, 48, 240, ++ 129, 223, 7, 224, 0, 147, 1, 147, 40, 70, 33, 70, 3, 154, 2, 155, 48, ++ 240, 82, 223, 40, 70, 33, 70, 1, 34, 48, 240, 11, 220, 40, 70, 33, 70, ++ 50, 70, 48, 240, 68, 216, 5, 176, 240, 189, 11, 104, 16, 181, 72, 105, ++ 56, 34, 137, 105, 220, 105, 220, 247, 44, 253, 64, 177, 67, 120, 5, ++ 43, 5, 209, 131, 120, 3, 43, 4, 191, 208, 248, 3, 48, 99, 97, 0, 32, ++ 16, 189, 45, 233, 240, 79, 5, 70, 0, 137, 135, 176, 147, 70, 153, 70, ++ 221, 248, 64, 160, 0, 40, 65, 208, 24, 70, 81, 70, 76, 34, 220, 247, ++ 16, 253, 4, 70, 0, 40, 57, 208, 67, 120, 16, 43, 51, 209, 66, 136, 43, ++ 136, 154, 66, 47, 209, 70, 122, 2, 121, 65, 121, 144, 248, 6, 128, 195, ++ 121, 0, 122, 64, 234, 6, 38, 104, 136, 176, 66, 35, 216, 79, 234, 8, ++ 72, 72, 234, 1, 40, 72, 234, 2, 8, 72, 234, 3, 104, 2, 209, 107, 104, ++ 67, 69, 23, 216, 2, 175, 88, 70, 73, 70, 82, 70, 5, 241, 10, 3, 0, 151, ++ 48, 240, 159, 223, 56, 70, 4, 241, 10, 1, 8, 34, 213, 247, 226, 251, ++ 56, 185, 8, 241, 1, 3, 110, 128, 107, 96, 35, 185, 1, 54, 110, 128, ++ 1, 224, 0, 32, 0, 224, 1, 32, 7, 176, 189, 232, 240, 143, 16, 181, 0, ++ 104, 20, 70, 7, 153, 249, 247, 78, 253, 3, 44, 9, 209, 4, 34, 6, 72, ++ 4, 153, 213, 247, 198, 251, 0, 40, 24, 191, 111, 240, 1, 0, 16, 189, ++ 111, 240, 22, 0, 16, 189, 0, 191, 106, 21, 4, 0, 248, 181, 70, 104, ++ 146, 248, 112, 48, 15, 70, 141, 25, 146, 248, 111, 16, 2, 241, 113, ++ 0, 67, 234, 1, 33, 9, 34, 217, 243, 173, 240, 4, 70, 8, 185, 40, 129, ++ 248, 189, 66, 120, 12, 58, 146, 178, 15, 42, 42, 129, 3, 216, 0, 35, ++ 43, 129, 0, 32, 248, 189, 193, 136, 187, 91, 153, 66, 7, 209, 16, 42, ++ 5, 209, 14, 48, 5, 241, 10, 1, 213, 247, 147, 251, 152, 177, 226, 121, ++ 163, 121, 5, 241, 10, 0, 67, 234, 2, 35, 187, 83, 163, 104, 4, 241, ++ 14, 1, 107, 96, 163, 137, 16, 34, 107, 128, 16, 35, 43, 129, 213, 247, ++ 147, 251, 1, 32, 248, 189, 1, 32, 248, 189, 45, 233, 240, 65, 71, 104, ++ 86, 104, 20, 70, 35, 136, 202, 91, 16, 46, 148, 191, 182, 178, 16, 38, ++ 154, 66, 136, 70, 1, 235, 7, 5, 10, 209, 43, 137, 179, 66, 7, 209, 4, ++ 241, 8, 0, 5, 241, 10, 1, 50, 70, 213, 247, 98, 251, 80, 177, 46, 129, ++ 5, 241, 10, 0, 4, 241, 8, 1, 50, 70, 213, 247, 108, 251, 35, 136, 40, ++ 248, 7, 48, 212, 248, 140, 48, 180, 248, 144, 64, 107, 96, 108, 128, ++ 189, 232, 240, 129, 0, 32, 24, 112, 17, 244, 0, 112, 5, 208, 18, 240, ++ 128, 15, 2, 208, 1, 32, 24, 112, 112, 71, 73, 5, 1, 213, 19, 6, 7, 213, ++ 64, 185, 2, 240, 64, 2, 210, 241, 1, 0, 56, 191, 0, 32, 112, 71, 0, ++ 32, 112, 71, 1, 32, 112, 71, 240, 181, 5, 104, 135, 176, 14, 70, 0, ++ 147, 64, 242, 238, 81, 4, 171, 5, 145, 1, 145, 2, 147, 7, 70, 80, 33, ++ 40, 70, 6, 241, 194, 3, 253, 243, 226, 240, 4, 70, 0, 40, 52, 208, 5, ++ 171, 0, 147, 0, 35, 1, 147, 40, 70, 4, 155, 80, 33, 50, 70, 247, 243, ++ 15, 244, 5, 155, 24, 51, 163, 129, 43, 104, 147, 248, 60, 48, 67, 177, ++ 123, 104, 158, 66, 5, 209, 251, 123, 1, 43, 2, 209, 213, 248, 164, 117, ++ 1, 224, 243, 104, 223, 104, 40, 70, 33, 70, 79, 244, 122, 34, 225, 247, ++ 251, 249, 163, 105, 0, 34, 67, 240, 2, 3, 163, 97, 12, 155, 1, 146, ++ 2, 146, 12, 34, 3, 146, 6, 235, 131, 3, 0, 150, 40, 70, 33, 70, 58, ++ 70, 219, 107, 232, 247, 44, 251, 7, 176, 240, 189, 248, 181, 2, 105, ++ 13, 104, 6, 70, 172, 88, 42, 121, 3, 104, 0, 42, 47, 208, 170, 121, ++ 50, 177, 213, 248, 204, 32, 144, 4, 2, 213, 98, 120, 74, 185, 248, 189, ++ 42, 122, 0, 42, 35, 208, 98, 136, 145, 7, 32, 213, 34, 127, 0, 42, 29, ++ 208, 211, 248, 72, 113, 41, 70, 56, 70, 48, 240, 97, 217, 171, 121, ++ 115, 177, 213, 248, 204, 48, 154, 4, 10, 213, 1, 34, 130, 64, 0, 35, ++ 56, 70, 41, 70, 210, 178, 48, 240, 229, 218, 0, 35, 99, 112, 248, 189, ++ 48, 70, 33, 70, 1, 34, 189, 232, 248, 64, 50, 240, 189, 153, 248, 189, ++ 45, 233, 240, 65, 6, 104, 134, 176, 13, 159, 0, 35, 5, 70, 17, 153, ++ 48, 70, 144, 70, 12, 156, 5, 147, 249, 247, 32, 252, 3, 47, 4, 217, ++ 5, 168, 33, 70, 4, 34, 213, 247, 171, 250, 184, 241, 9, 15, 34, 209, ++ 107, 104, 27, 179, 170, 123, 34, 240, 2, 2, 170, 115, 34, 120, 69, 42, ++ 10, 208, 83, 42, 29, 209, 219, 104, 48, 70, 0, 147, 50, 33, 34, 29, ++ 59, 31, 229, 247, 170, 248, 22, 224, 1, 34, 4, 52, 4, 63, 2, 146, 0, ++ 148, 1, 151, 219, 104, 0, 34, 3, 147, 48, 70, 7, 73, 19, 70, 225, 247, ++ 80, 248, 7, 224, 111, 240, 22, 0, 4, 224, 79, 240, 255, 48, 1, 224, ++ 111, 240, 1, 0, 6, 176, 189, 232, 240, 129, 9, 80, 136, 0, 45, 233, ++ 243, 65, 144, 232, 160, 0, 59, 28, 4, 70, 24, 191, 1, 35, 213, 248, ++ 72, 97, 136, 70, 0, 41, 45, 208, 0, 43, 69, 209, 0, 241, 8, 7, 57, 70, ++ 40, 70, 249, 247, 225, 251, 128, 70, 0, 40, 63, 209, 40, 70, 26, 240, ++ 21, 222, 1, 70, 1, 48, 60, 208, 59, 70, 40, 70, 79, 244, 148, 50, 205, ++ 248, 0, 128, 26, 240, 164, 219, 7, 70, 0, 40, 52, 208, 32, 70, 57, 70, ++ 50, 240, 135, 219, 128, 70, 192, 185, 56, 70, 4, 241, 32, 1, 103, 96, ++ 226, 105, 26, 240, 124, 219, 48, 70, 57, 70, 255, 247, 85, 252, 22, ++ 224, 35, 179, 213, 248, 104, 1, 57, 70, 4, 34, 60, 240, 134, 222, 48, ++ 70, 57, 70, 48, 240, 104, 219, 23, 185, 6, 224, 79, 240, 255, 56, 40, ++ 70, 57, 70, 26, 240, 126, 221, 0, 224, 184, 70, 0, 35, 99, 96, 0, 35, ++ 227, 115, 12, 224, 79, 240, 0, 8, 9, 224, 111, 240, 15, 8, 6, 224, 111, ++ 240, 21, 8, 3, 224, 111, 240, 26, 8, 0, 224, 152, 70, 64, 70, 189, 232, ++ 252, 129, 45, 233, 240, 65, 136, 70, 180, 176, 5, 70, 9, 136, 1, 168, ++ 184, 248, 4, 32, 215, 243, 156, 245, 41, 224, 99, 107, 166, 106, 27, ++ 1, 4, 213, 30, 177, 55, 125, 23, 240, 1, 7, 5, 208, 1, 168, 51, 153, ++ 34, 70, 215, 243, 77, 246, 26, 224, 1, 35, 49, 70, 34, 70, 40, 70, 225, ++ 247, 10, 252, 40, 70, 2, 33, 59, 70, 34, 70, 225, 247, 132, 252, 163, ++ 105, 88, 5, 5, 213, 213, 248, 52, 1, 49, 70, 34, 70, 241, 247, 131, ++ 249, 43, 104, 33, 70, 88, 105, 1, 34, 222, 247, 173, 249, 64, 70, 51, ++ 169, 215, 243, 239, 244, 4, 70, 0, 40, 206, 209, 12, 224, 147, 106, ++ 51, 185, 43, 104, 17, 70, 88, 105, 1, 34, 222, 247, 157, 249, 3, 224, ++ 64, 70, 51, 153, 215, 243, 28, 246, 1, 168, 51, 169, 215, 243, 218, ++ 244, 2, 70, 0, 40, 235, 209, 52, 176, 189, 232, 240, 129, 45, 233, 248, ++ 67, 5, 104, 140, 107, 213, 248, 72, 129, 6, 70, 15, 70, 64, 70, 33, ++ 70, 48, 240, 58, 216, 57, 70, 129, 70, 0, 34, 48, 70, 50, 240, 168, ++ 216, 163, 121, 3, 179, 212, 248, 204, 48, 154, 4, 28, 213, 251, 127, ++ 1, 43, 2, 208, 2, 43, 17, 209, 9, 224, 9, 241, 4, 9, 3, 250, 9, 242, ++ 64, 70, 33, 70, 210, 178, 48, 240, 177, 217, 6, 224, 40, 70, 1, 33, ++ 34, 70, 79, 240, 255, 51, 38, 240, 147, 223, 48, 70, 33, 70, 1, 34, ++ 52, 240, 144, 221, 26, 224, 212, 248, 4, 49, 155, 122, 27, 177, 32, ++ 70, 0, 33, 3, 240, 229, 218, 43, 104, 91, 107, 59, 177, 212, 248, 4, ++ 49, 27, 127, 27, 177, 32, 70, 0, 33, 1, 240, 172, 218, 212, 248, 4, ++ 49, 27, 123, 27, 177, 32, 70, 0, 33, 1, 240, 26, 223, 40, 70, 33, 70, ++ 189, 232, 248, 67, 53, 240, 254, 158, 16, 181, 68, 104, 3, 70, 140, ++ 177, 161, 66, 15, 209, 193, 123, 2, 41, 7, 209, 16, 70, 3, 241, 28, ++ 1, 36, 34, 189, 232, 16, 64, 213, 247, 87, 185, 25, 185, 130, 123, 66, ++ 240, 2, 2, 130, 115, 16, 189, 240, 181, 0, 36, 133, 176, 141, 248, 15, ++ 64, 4, 105, 5, 70, 12, 89, 6, 104, 97, 136, 17, 240, 8, 1, 31, 208, ++ 13, 241, 15, 1, 0, 145, 33, 70, 50, 240, 94, 217, 7, 70, 192, 185, 157, ++ 248, 15, 48, 171, 177, 51, 104, 147, 248, 60, 48, 27, 177, 214, 248, ++ 84, 1, 254, 247, 79, 250, 33, 70, 40, 70, 52, 240, 131, 216, 33, 70, ++ 40, 70, 52, 240, 113, 217, 40, 70, 33, 70, 51, 240, 177, 217, 0, 224, ++ 15, 70, 56, 70, 5, 176, 240, 189, 112, 71, 112, 181, 3, 125, 4, 70, ++ 13, 70, 22, 70, 19, 177, 0, 104, 225, 247, 65, 252, 32, 70, 41, 70, ++ 50, 70, 189, 232, 112, 64, 53, 240, 139, 159, 0, 0, 45, 233, 240, 65, ++ 208, 248, 4, 128, 12, 36, 0, 38, 1, 39, 20, 224, 208, 248, 8, 192, 12, ++ 235, 4, 5, 92, 248, 4, 192, 140, 69, 10, 209, 213, 248, 4, 192, 148, ++ 69, 6, 209, 1, 54, 35, 177, 223, 248, 20, 192, 109, 96, 197, 248, 0, ++ 192, 1, 55, 12, 52, 71, 69, 232, 221, 48, 70, 189, 232, 240, 129, 213, ++ 209, 2, 0, 1, 117, 112, 71, 1, 41, 3, 70, 10, 208, 208, 248, 232, 32, ++ 162, 248, 216, 19, 178, 248, 218, 3, 0, 34, 128, 178, 163, 248, 44, ++ 33, 112, 71, 79, 246, 255, 112, 112, 71, 208, 248, 232, 48, 163, 248, ++ 216, 19, 163, 248, 218, 35, 112, 71, 208, 248, 232, 32, 0, 35, 162, ++ 248, 216, 51, 178, 248, 218, 35, 160, 248, 44, 49, 16, 4, 64, 244, 118, ++ 112, 64, 240, 2, 0, 112, 71, 208, 248, 232, 48, 0, 34, 163, 248, 252, ++ 19, 160, 248, 44, 33, 179, 248, 254, 3, 128, 178, 112, 71, 208, 248, ++ 232, 48, 65, 234, 2, 66, 195, 248, 252, 35, 112, 71, 0, 35, 128, 248, ++ 255, 48, 255, 35, 128, 248, 138, 49, 128, 248, 44, 50, 112, 71, 112, ++ 71, 176, 248, 246, 48, 19, 244, 64, 79, 3, 191, 219, 178, 192, 24, 144, ++ 248, 250, 3, 0, 32, 64, 178, 112, 71, 112, 71, 111, 240, 22, 0, 112, ++ 71, 111, 240, 22, 0, 112, 71, 111, 240, 22, 0, 112, 71, 111, 240, 22, ++ 0, 112, 71, 111, 240, 22, 0, 112, 71, 111, 240, 22, 0, 112, 71, 112, ++ 71, 112, 71, 144, 248, 125, 50, 112, 181, 139, 66, 4, 70, 13, 70, 22, ++ 70, 3, 208, 208, 248, 164, 48, 3, 177, 152, 71, 164, 248, 128, 98, 132, ++ 248, 125, 82, 112, 189, 112, 181, 0, 36, 78, 66, 0, 240, 15, 5, 117, ++ 27, 2, 235, 69, 5, 29, 85, 1, 52, 0, 9, 10, 44, 244, 209, 89, 122, 157, ++ 249, 16, 32, 138, 26, 90, 114, 112, 189, 7, 181, 0, 34, 1, 146, 4, 154, ++ 3, 42, 4, 217, 1, 168, 25, 70, 4, 34, 213, 247, 85, 248, 111, 240, 22, ++ 0, 14, 189, 16, 181, 189, 232, 16, 64, 255, 247, 237, 191, 7, 181, 0, ++ 34, 1, 146, 4, 154, 3, 42, 4, 217, 1, 168, 25, 70, 4, 34, 213, 247, ++ 66, 248, 111, 240, 22, 0, 14, 189, 7, 181, 0, 34, 1, 146, 4, 154, 3, ++ 42, 4, 217, 1, 168, 25, 70, 4, 34, 213, 247, 52, 248, 111, 240, 22, ++ 0, 14, 189, 7, 181, 0, 34, 1, 146, 4, 154, 3, 42, 4, 217, 1, 168, 25, ++ 70, 4, 34, 213, 247, 38, 248, 111, 240, 22, 0, 14, 189, 16, 181, 144, ++ 248, 7, 49, 138, 176, 67, 240, 1, 3, 128, 248, 7, 49, 4, 70, 0, 33, ++ 12, 34, 1, 168, 214, 243, 149, 243, 0, 33, 4, 34, 4, 168, 214, 243, ++ 144, 243, 0, 33, 1, 34, 9, 168, 214, 243, 139, 243, 0, 33, 2, 34, 8, ++ 168, 214, 243, 134, 243, 0, 33, 2, 34, 7, 168, 214, 243, 129, 243, 0, ++ 33, 2, 34, 5, 168, 214, 243, 124, 243, 6, 168, 0, 33, 2, 34, 214, 243, ++ 119, 243, 148, 248, 7, 49, 0, 32, 35, 240, 1, 3, 132, 248, 7, 49, 10, ++ 176, 16, 189, 55, 181, 0, 36, 13, 70, 12, 96, 1, 33, 9, 240, 105, 255, ++ 2, 169, 65, 248, 4, 13, 4, 34, 40, 70, 212, 247, 224, 255, 32, 70, 62, ++ 189, 115, 181, 0, 34, 1, 146, 6, 154, 5, 70, 3, 42, 12, 70, 7, 158, ++ 4, 217, 1, 168, 25, 70, 4, 34, 212, 247, 208, 255, 64, 242, 21, 51, ++ 156, 66, 94, 208, 49, 216, 64, 242, 214, 35, 156, 66, 84, 208, 21, 216, ++ 64, 242, 181, 35, 156, 66, 0, 240, 150, 128, 4, 216, 180, 245, 45, 127, ++ 64, 240, 174, 128, 138, 224, 64, 242, 182, 35, 156, 66, 0, 240, 146, ++ 128, 64, 242, 183, 35, 156, 66, 64, 240, 163, 128, 143, 224, 180, 245, ++ 66, 127, 0, 240, 148, 128, 8, 216, 180, 245, 64, 127, 62, 208, 64, 242, ++ 6, 51, 156, 66, 64, 240, 149, 128, 137, 224, 64, 242, 9, 51, 156, 66, ++ 52, 208, 180, 245, 69, 127, 64, 240, 140, 128, 49, 224, 64, 242, 26, ++ 51, 156, 66, 84, 208, 12, 216, 64, 242, 23, 51, 156, 66, 43, 208, 48, ++ 211, 180, 245, 70, 127, 64, 208, 64, 242, 25, 51, 156, 66, 121, 209, ++ 53, 224, 64, 242, 29, 51, 156, 66, 41, 208, 7, 216, 64, 242, 27, 51, ++ 156, 66, 55, 208, 180, 245, 71, 127, 108, 209, 37, 224, 180, 245, 72, ++ 127, 65, 208, 64, 242, 33, 51, 156, 66, 100, 209, 54, 224, 40, 70, 49, ++ 70, 255, 247, 128, 255, 99, 224, 189, 248, 4, 48, 165, 248, 48, 51, ++ 0, 32, 93, 224, 181, 249, 48, 51, 65, 224, 213, 248, 228, 48, 1, 154, ++ 131, 248, 130, 40, 244, 231, 213, 248, 228, 48, 147, 248, 130, 56, 54, ++ 224, 189, 248, 4, 48, 165, 248, 50, 51, 234, 231, 181, 249, 50, 51, ++ 46, 224, 213, 248, 228, 48, 1, 154, 131, 248, 131, 40, 225, 231, 213, ++ 248, 228, 48, 147, 248, 131, 56, 35, 224, 213, 248, 228, 48, 1, 154, ++ 131, 248, 132, 40, 214, 231, 213, 248, 228, 48, 147, 248, 132, 56, 24, ++ 224, 213, 248, 228, 48, 1, 154, 131, 248, 134, 40, 203, 231, 213, 248, ++ 228, 48, 147, 248, 134, 56, 13, 224, 40, 70, 1, 153, 50, 70, 0, 35, ++ 3, 224, 1, 153, 40, 70, 50, 70, 1, 35, 255, 247, 141, 254, 186, 231, ++ 181, 248, 102, 50, 51, 96, 182, 231, 1, 155, 90, 30, 178, 245, 250, ++ 111, 15, 210, 165, 248, 102, 50, 174, 231, 0, 36, 2, 169, 65, 248, 4, ++ 77, 48, 70, 4, 34, 212, 247, 16, 255, 32, 70, 4, 224, 111, 240, 22, ++ 0, 1, 224, 111, 240, 28, 0, 124, 189, 56, 181, 208, 248, 148, 52, 4, ++ 70, 147, 248, 154, 33, 18, 177, 211, 248, 172, 33, 106, 185, 163, 107, ++ 79, 244, 135, 113, 24, 105, 9, 240, 192, 255, 212, 248, 148, 52, 211, ++ 248, 112, 34, 195, 248, 112, 2, 130, 26, 13, 224, 0, 34, 131, 248, 154, ++ 33, 208, 248, 148, 52, 79, 244, 122, 113, 211, 248, 156, 33, 211, 248, ++ 172, 49, 74, 67, 178, 251, 243, 242, 0, 42, 31, 219, 212, 248, 148, ++ 52, 211, 248, 136, 18, 179, 248, 116, 82, 1, 245, 156, 112, 3, 235, ++ 64, 0, 196, 136, 194, 128, 44, 27, 164, 24, 164, 178, 179, 248, 108, ++ 82, 74, 28, 163, 248, 116, 66, 228, 8, 7, 42, 163, 248, 110, 82, 163, ++ 248, 108, 66, 195, 248, 136, 34, 2, 221, 0, 34, 195, 248, 136, 34, 56, ++ 189, 16, 181, 4, 70, 255, 247, 179, 255, 163, 107, 218, 110, 4, 42, ++ 7, 209, 147, 248, 44, 49, 35, 177, 32, 70, 189, 232, 16, 64, 7, 240, ++ 23, 185, 16, 189, 16, 181, 144, 248, 38, 49, 4, 70, 83, 177, 176, 249, ++ 60, 49, 1, 51, 6, 209, 131, 107, 50, 33, 24, 105, 9, 240, 104, 255, ++ 164, 248, 62, 1, 1, 32, 16, 189, 56, 181, 4, 70, 13, 70, 82, 177, 0, ++ 35, 192, 248, 84, 49, 160, 248, 88, 49, 6, 240, 208, 251, 16, 177, 32, ++ 70, 6, 240, 18, 252, 32, 70, 41, 70, 6, 240, 200, 251, 48, 177, 32, ++ 70, 41, 70, 6, 240, 221, 251, 196, 248, 144, 81, 1, 32, 56, 189, 8, ++ 181, 9, 240, 97, 254, 0, 32, 8, 189, 16, 181, 4, 70, 180, 248, 246, ++ 16, 0, 34, 208, 248, 156, 4, 10, 240, 126, 254, 180, 248, 246, 16, 132, ++ 248, 34, 1, 0, 34, 212, 248, 156, 4, 10, 240, 144, 254, 0, 35, 132, ++ 248, 58, 49, 163, 108, 132, 248, 35, 1, 132, 248, 53, 1, 11, 177, 32, ++ 70, 152, 71, 16, 189, 112, 181, 8, 70, 134, 176, 25, 70, 29, 70, 1, ++ 36, 10, 240, 234, 252, 0, 33, 11, 70, 3, 174, 40, 70, 34, 70, 0, 148, ++ 1, 150, 10, 240, 245, 251, 157, 249, 20, 48, 128, 51, 13, 209, 157, ++ 248, 19, 48, 0, 33, 141, 248, 20, 48, 141, 248, 21, 48, 40, 70, 34, ++ 70, 11, 70, 141, 232, 80, 0, 10, 240, 66, 252, 6, 176, 112, 189, 4, ++ 75, 27, 120, 1, 43, 2, 209, 0, 32, 0, 112, 112, 71, 39, 240, 119, 191, ++ 0, 191, 52, 7, 0, 0, 16, 181, 20, 70, 255, 247, 240, 255, 40, 177, 0, ++ 33, 10, 70, 189, 232, 16, 64, 219, 247, 239, 189, 32, 70, 16, 189, 0, ++ 34, 255, 247, 240, 191, 45, 233, 240, 65, 5, 70, 12, 70, 23, 70, 30, ++ 70, 255, 247, 220, 255, 56, 177, 40, 70, 33, 70, 58, 70, 51, 70, 189, ++ 232, 240, 65, 39, 240, 139, 191, 48, 70, 189, 232, 240, 129, 0, 35, ++ 255, 247, 233, 191, 144, 248, 116, 51, 1, 51, 219, 178, 1, 43, 128, ++ 248, 116, 51, 3, 216, 131, 107, 24, 105, 9, 240, 221, 190, 112, 71, ++ 144, 248, 116, 51, 1, 59, 219, 178, 128, 248, 116, 51, 27, 185, 131, ++ 107, 24, 105, 9, 240, 213, 190, 112, 71, 240, 181, 31, 70, 147, 176, ++ 0, 35, 17, 147, 24, 155, 4, 70, 3, 43, 13, 70, 25, 158, 4, 217, 17, ++ 168, 57, 70, 4, 34, 212, 247, 220, 253, 64, 242, 238, 35, 157, 66, 24, ++ 208, 3, 216, 181, 245, 28, 127, 57, 209, 8, 224, 64, 242, 234, 51, 157, ++ 66, 45, 208, 64, 242, 2, 67, 157, 66, 48, 209, 43, 224, 32, 70, 255, ++ 247, 194, 255, 32, 70, 49, 70, 255, 247, 42, 253, 32, 70, 255, 247, ++ 200, 255, 39, 224, 64, 34, 1, 168, 57, 70, 212, 247, 186, 253, 189, ++ 248, 4, 48, 189, 248, 6, 0, 189, 248, 8, 32, 12, 43, 51, 128, 112, 128, ++ 178, 128, 2, 208, 15, 35, 51, 128, 20, 224, 152, 185, 180, 248, 38, ++ 36, 242, 128, 180, 248, 34, 52, 51, 129, 180, 248, 36, 68, 116, 129, ++ 10, 224, 0, 32, 48, 96, 7, 224, 163, 107, 91, 107, 51, 96, 2, 224, 111, ++ 240, 22, 0, 0, 224, 0, 32, 19, 176, 240, 189, 112, 181, 5, 70, 12, 70, ++ 22, 70, 255, 247, 166, 252, 33, 70, 0, 234, 6, 2, 40, 70, 189, 232, ++ 112, 64, 255, 247, 175, 188, 112, 181, 5, 70, 12, 70, 22, 70, 255, 247, ++ 152, 252, 64, 234, 6, 2, 33, 70, 40, 70, 146, 178, 189, 232, 112, 64, ++ 255, 247, 160, 188, 248, 181, 5, 70, 12, 70, 22, 70, 31, 70, 255, 247, ++ 136, 252, 32, 234, 6, 2, 62, 64, 50, 67, 40, 70, 33, 70, 146, 178, 189, ++ 232, 248, 64, 255, 247, 142, 188, 0, 35, 160, 248, 44, 49, 208, 248, ++ 232, 48, 179, 248, 254, 3, 128, 178, 112, 71, 208, 248, 232, 48, 163, ++ 248, 254, 19, 112, 71, 208, 248, 232, 48, 163, 248, 252, 19, 179, 248, ++ 254, 19, 10, 64, 163, 248, 254, 35, 0, 35, 160, 248, 44, 49, 112, 71, ++ 208, 248, 232, 48, 163, 248, 252, 19, 179, 248, 254, 19, 137, 178, 10, ++ 67, 163, 248, 254, 35, 0, 35, 160, 248, 44, 49, 112, 71, 16, 181, 208, ++ 248, 232, 64, 19, 64, 164, 248, 252, 19, 180, 248, 254, 19, 137, 178, ++ 33, 234, 2, 2, 26, 67, 0, 35, 164, 248, 254, 35, 160, 248, 44, 49, 16, ++ 189, 112, 181, 11, 70, 5, 70, 82, 224, 28, 70, 86, 30, 52, 248, 2, 43, ++ 209, 4, 2, 244, 96, 66, 201, 12, 178, 245, 192, 79, 60, 208, 7, 216, ++ 178, 245, 0, 95, 46, 208, 178, 245, 128, 79, 33, 208, 122, 177, 60, ++ 224, 178, 245, 32, 79, 43, 208, 3, 216, 178, 245, 0, 79, 53, 209, 14, ++ 224, 178, 245, 64, 79, 25, 208, 178, 245, 96, 79, 46, 209, 41, 224, ++ 28, 70, 90, 136, 40, 70, 52, 248, 4, 63, 255, 247, 192, 255, 6, 224, ++ 28, 70, 90, 136, 40, 70, 52, 248, 4, 63, 255, 247, 125, 255, 1, 62, ++ 28, 224, 40, 70, 90, 136, 255, 247, 56, 252, 23, 224, 40, 70, 90, 136, ++ 255, 247, 18, 252, 18, 224, 40, 70, 90, 136, 255, 247, 141, 255, 13, ++ 224, 40, 70, 90, 136, 255, 247, 75, 255, 8, 224, 40, 70, 90, 136, 255, ++ 247, 144, 255, 3, 224, 40, 70, 90, 136, 255, 247, 79, 255, 163, 28, ++ 114, 30, 0, 42, 170, 220, 112, 189, 208, 248, 180, 48, 16, 181, 11, ++ 177, 152, 71, 16, 189, 208, 248, 232, 32, 1, 185, 244, 35, 162, 248, ++ 230, 51, 16, 189, 1, 35, 128, 248, 253, 48, 112, 71, 128, 248, 48, 17, ++ 112, 71, 144, 249, 48, 1, 112, 71, 112, 71, 16, 177, 131, 107, 3, 177, ++ 89, 119, 112, 71, 16, 177, 131, 107, 3, 177, 25, 119, 112, 71, 144, ++ 248, 255, 32, 16, 181, 4, 70, 0, 42, 111, 209, 208, 248, 148, 52, 100, ++ 33, 163, 248, 108, 18, 163, 248, 110, 18, 79, 244, 72, 113, 163, 248, ++ 116, 18, 100, 33, 163, 248, 118, 18, 163, 248, 120, 18, 163, 248, 122, ++ 18, 163, 248, 124, 18, 163, 248, 126, 18, 163, 248, 128, 18, 163, 248, ++ 130, 18, 163, 248, 132, 18, 10, 33, 163, 248, 210, 17, 163, 248, 240, ++ 17, 163, 248, 214, 17, 163, 248, 248, 17, 163, 248, 212, 17, 163, 248, ++ 242, 17, 163, 248, 216, 17, 163, 248, 250, 17, 163, 248, 198, 17, 163, ++ 248, 196, 17, 163, 248, 200, 17, 163, 248, 202, 17, 20, 33, 163, 248, ++ 206, 17, 163, 248, 208, 17, 10, 33, 163, 248, 202, 16, 163, 248, 204, ++ 16, 80, 33, 163, 248, 206, 16, 10, 33, 195, 248, 112, 34, 163, 248, ++ 204, 33, 163, 248, 228, 32, 163, 248, 230, 32, 163, 248, 230, 17, 163, ++ 248, 228, 17, 163, 248, 232, 17, 163, 248, 234, 17, 131, 248, 154, 33, ++ 20, 33, 163, 248, 236, 17, 163, 248, 238, 17, 195, 248, 244, 33, 195, ++ 248, 252, 33, 208, 248, 148, 52, 195, 248, 156, 33, 195, 248, 160, 33, ++ 195, 248, 164, 33, 195, 248, 168, 33, 195, 248, 172, 33, 3, 108, 3, ++ 177, 152, 71, 1, 35, 132, 248, 255, 48, 16, 189, 208, 248, 36, 19, 8, ++ 181, 65, 177, 131, 107, 24, 105, 9, 240, 241, 252, 208, 241, 1, 0, 56, ++ 191, 0, 32, 8, 189, 8, 70, 8, 189, 45, 233, 240, 79, 133, 176, 30, 70, ++ 189, 248, 56, 48, 13, 70, 2, 147, 189, 248, 60, 48, 209, 248, 12, 144, ++ 3, 147, 189, 248, 64, 48, 15, 104, 4, 70, 209, 248, 16, 128, 17, 70, ++ 42, 137, 1, 147, 255, 247, 90, 251, 49, 70, 32, 70, 31, 250, 137, 242, ++ 255, 247, 84, 251, 43, 70, 186, 70, 0, 38, 61, 70, 155, 70, 93, 224, ++ 184, 241, 32, 15, 64, 208, 6, 216, 184, 241, 8, 15, 77, 208, 184, 241, ++ 16, 15, 79, 209, 68, 224, 184, 241, 60, 15, 6, 208, 184, 241, 64, 15, ++ 3, 208, 184, 241, 48, 15, 69, 209, 25, 224, 218, 248, 0, 144, 32, 70, ++ 31, 250, 137, 242, 2, 153, 255, 247, 49, 251, 32, 70, 79, 234, 25, 65, ++ 255, 247, 134, 254, 218, 248, 4, 144, 32, 70, 31, 250, 137, 241, 255, ++ 247, 127, 254, 32, 70, 79, 234, 25, 65, 255, 247, 122, 254, 42, 224, ++ 79, 240, 0, 9, 32, 70, 185, 241, 0, 15, 4, 209, 2, 153, 42, 136, 255, ++ 247, 21, 251, 3, 224, 53, 248, 25, 16, 255, 247, 106, 254, 9, 241, 1, ++ 9, 185, 241, 3, 15, 237, 209, 21, 224, 87, 248, 38, 32, 32, 70, 3, 153, ++ 18, 12, 255, 247, 3, 251, 32, 70, 1, 153, 55, 248, 38, 32, 7, 224, 32, ++ 70, 1, 153, 55, 248, 22, 32, 2, 224, 1, 153, 186, 93, 32, 70, 255, 247, ++ 244, 250, 1, 54, 10, 241, 8, 10, 6, 53, 219, 248, 4, 48, 158, 66, 157, ++ 211, 5, 176, 189, 232, 240, 143, 45, 233, 240, 79, 133, 176, 152, 70, ++ 189, 248, 56, 48, 209, 248, 12, 144, 2, 147, 189, 248, 60, 48, 13, 70, ++ 3, 147, 189, 248, 64, 48, 14, 104, 4, 70, 15, 105, 17, 70, 42, 137, ++ 1, 147, 255, 247, 210, 250, 65, 70, 32, 70, 31, 250, 137, 242, 255, ++ 247, 204, 250, 179, 70, 178, 70, 79, 240, 0, 8, 95, 224, 32, 47, 58, ++ 208, 4, 216, 8, 47, 78, 208, 16, 47, 82, 209, 68, 224, 60, 47, 4, 208, ++ 64, 47, 2, 208, 48, 47, 75, 209, 23, 224, 2, 153, 32, 70, 255, 247, ++ 169, 250, 129, 70, 32, 70, 255, 247, 1, 254, 73, 234, 0, 64, 203, 248, ++ 0, 0, 32, 70, 255, 247, 250, 253, 129, 70, 32, 70, 255, 247, 246, 253, ++ 73, 234, 0, 64, 203, 248, 4, 0, 50, 224, 79, 240, 0, 9, 32, 70, 185, ++ 241, 0, 15, 5, 209, 2, 153, 255, 247, 140, 250, 170, 248, 0, 0, 3, 224, ++ 255, 247, 227, 253, 42, 248, 25, 0, 9, 241, 1, 9, 185, 241, 3, 15, 236, ++ 209, 28, 224, 1, 153, 32, 70, 255, 247, 123, 250, 3, 153, 129, 70, 70, ++ 248, 40, 0, 32, 70, 255, 247, 116, 250, 73, 234, 0, 64, 70, 248, 40, ++ 0, 12, 224, 32, 70, 1, 153, 255, 247, 107, 250, 38, 248, 24, 0, 5, 224, ++ 32, 70, 1, 153, 255, 247, 100, 250, 6, 248, 8, 0, 8, 241, 1, 8, 11, ++ 241, 8, 11, 10, 241, 6, 10, 107, 104, 152, 69, 156, 211, 5, 176, 189, ++ 232, 240, 143, 127, 181, 2, 147, 8, 155, 3, 145, 5, 147, 9, 155, 1, ++ 146, 4, 147, 1, 169, 10, 155, 152, 71, 7, 176, 0, 189, 127, 181, 2, ++ 147, 8, 155, 3, 145, 5, 147, 9, 155, 1, 146, 4, 147, 1, 169, 10, 155, ++ 152, 71, 7, 176, 0, 189, 0, 0, 240, 181, 65, 75, 139, 176, 208, 248, ++ 232, 64, 7, 70, 13, 70, 106, 70, 3, 241, 16, 14, 24, 104, 89, 104, 22, ++ 70, 3, 198, 8, 51, 115, 69, 50, 70, 247, 209, 24, 104, 57, 75, 48, 96, ++ 5, 170, 3, 241, 16, 14, 24, 104, 89, 104, 22, 70, 3, 198, 8, 51, 115, ++ 69, 50, 70, 247, 209, 24, 104, 0, 35, 48, 96, 164, 248, 112, 53, 13, ++ 177, 107, 70, 0, 224, 5, 171, 186, 107, 0, 33, 16, 105, 20, 34, 9, 240, ++ 185, 251, 0, 35, 164, 248, 104, 53, 0, 45, 79, 244, 128, 115, 164, 248, ++ 192, 55, 12, 191, 64, 35, 65, 35, 164, 248, 12, 53, 65, 246, 2, 35, ++ 164, 248, 20, 53, 79, 240, 0, 3, 164, 248, 8, 53, 164, 248, 10, 53, ++ 164, 248, 76, 53, 79, 240, 20, 3, 164, 248, 106, 53, 64, 246, 38, 3, ++ 164, 248, 104, 53, 79, 240, 0, 3, 164, 248, 0, 53, 79, 240, 208, 3, ++ 164, 248, 2, 53, 12, 191, 250, 38, 30, 38, 180, 248, 2, 53, 0, 37, 2, ++ 224, 10, 32, 218, 243, 136, 241, 181, 66, 9, 218, 180, 248, 14, 53, ++ 1, 53, 24, 6, 245, 212, 3, 224, 10, 32, 218, 243, 125, 241, 0, 224, ++ 11, 37, 1, 61, 8, 208, 180, 248, 14, 53, 89, 5, 244, 213, 3, 224, 10, ++ 32, 218, 243, 113, 241, 1, 224, 64, 242, 245, 21, 1, 61, 3, 208, 180, ++ 248, 144, 54, 218, 5, 243, 212, 11, 176, 240, 189, 116, 21, 4, 0, 136, ++ 21, 4, 0, 11, 70, 208, 248, 20, 17, 10, 177, 25, 67, 1, 224, 33, 234, ++ 3, 1, 155, 7, 192, 248, 20, 17, 2, 213, 17, 70, 255, 247, 191, 185, ++ 112, 71, 208, 248, 20, 1, 192, 243, 0, 16, 112, 71, 16, 181, 208, 248, ++ 20, 49, 33, 177, 67, 240, 16, 3, 192, 248, 20, 49, 16, 189, 35, 240, ++ 16, 3, 210, 7, 192, 248, 20, 49, 10, 213, 131, 107, 208, 248, 48, 66, ++ 26, 106, 155, 110, 154, 66, 136, 191, 195, 235, 2, 1, 196, 248, 128, ++ 16, 16, 189, 131, 107, 16, 181, 88, 33, 4, 70, 71, 246, 127, 114, 24, ++ 105, 9, 240, 0, 251, 163, 107, 90, 33, 24, 105, 71, 246, 127, 114, 9, ++ 240, 249, 250, 163, 107, 112, 33, 24, 105, 71, 246, 127, 114, 9, 240, ++ 242, 250, 163, 107, 114, 33, 24, 105, 71, 246, 127, 114, 9, 240, 235, ++ 250, 0, 32, 16, 189, 56, 181, 208, 248, 232, 48, 4, 70, 211, 248, 32, ++ 49, 208, 248, 20, 49, 128, 107, 64, 246, 2, 2, 13, 70, 26, 64, 0, 105, ++ 9, 177, 180, 248, 246, 16, 0, 50, 195, 243, 128, 3, 24, 191, 1, 34, ++ 9, 240, 1, 251, 212, 248, 176, 48, 19, 177, 32, 70, 41, 70, 152, 71, ++ 56, 189, 160, 248, 250, 16, 112, 71, 131, 107, 202, 178, 1, 244, 96, ++ 81, 177, 245, 192, 95, 24, 105, 8, 191, 66, 244, 0, 114, 160, 33, 9, ++ 240, 186, 186, 160, 248, 246, 16, 112, 71, 176, 248, 246, 0, 112, 71, ++ 112, 71, 64, 246, 195, 19, 152, 66, 140, 191, 79, 240, 255, 48, 0, 32, ++ 112, 71, 112, 71, 0, 0, 16, 181, 0, 35, 6, 74, 153, 0, 50, 248, 35, ++ 64, 132, 66, 2, 209, 82, 24, 80, 136, 16, 189, 1, 51, 14, 43, 243, 209, ++ 0, 32, 16, 189, 176, 62, 4, 0, 8, 181, 200, 178, 255, 247, 234, 255, ++ 189, 232, 8, 64, 255, 247, 220, 191, 248, 181, 6, 70, 13, 70, 16, 70, ++ 20, 70, 0, 33, 28, 34, 213, 243, 65, 245, 0, 39, 13, 75, 249, 90, 150, ++ 248, 136, 50, 35, 177, 148, 41, 2, 217, 165, 41, 14, 217, 1, 224, 144, ++ 41, 11, 208, 2, 45, 2, 209, 14, 41, 4, 217, 6, 224, 1, 45, 4, 209, 14, ++ 41, 2, 217, 32, 70, 214, 243, 242, 246, 4, 55, 56, 47, 228, 209, 248, ++ 189, 176, 62, 4, 0, 48, 181, 144, 248, 136, 66, 0, 34, 14, 75, 211, ++ 90, 67, 244, 128, 80, 14, 43, 140, 191, 79, 244, 64, 69, 0, 37, 40, ++ 67, 28, 177, 148, 43, 1, 217, 165, 43, 8, 217, 2, 41, 2, 209, 14, 43, ++ 4, 216, 48, 189, 1, 41, 1, 209, 14, 43, 3, 216, 4, 50, 56, 42, 228, ++ 209, 255, 32, 48, 189, 0, 191, 176, 62, 4, 0, 16, 181, 144, 248, 31, ++ 49, 11, 112, 144, 248, 54, 49, 51, 177, 144, 248, 58, 65, 144, 248, ++ 53, 49, 4, 177, 91, 66, 11, 112, 18, 177, 144, 248, 56, 49, 19, 112, ++ 0, 32, 16, 189, 48, 181, 20, 70, 26, 70, 157, 248, 12, 48, 80, 177, ++ 28, 177, 144, 248, 11, 84, 173, 0, 37, 112, 34, 177, 201, 178, 189, ++ 232, 48, 64, 8, 240, 230, 188, 48, 189, 45, 233, 240, 79, 146, 70, 130, ++ 107, 13, 70, 82, 108, 64, 242, 57, 81, 0, 35, 135, 176, 138, 66, 4, ++ 70, 141, 248, 23, 48, 3, 208, 64, 242, 139, 81, 138, 66, 8, 209, 180, ++ 248, 246, 48, 3, 244, 64, 67, 163, 245, 64, 65, 75, 66, 67, 235, 1, ++ 3, 212, 248, 136, 36, 3, 147, 90, 177, 212, 248, 156, 4, 1, 33, 10, ++ 240, 32, 249, 40, 185, 163, 107, 212, 248, 136, 20, 152, 104, 9, 240, ++ 129, 254, 148, 248, 56, 49, 131, 185, 212, 248, 156, 4, 180, 248, 246, ++ 16, 1, 34, 10, 240, 194, 248, 196, 248, 136, 4, 48, 177, 186, 241, 0, ++ 15, 3, 209, 32, 70, 255, 247, 158, 250, 59, 225, 180, 248, 246, 16, ++ 0, 35, 196, 248, 136, 52, 1, 244, 96, 81, 163, 107, 177, 245, 0, 95, ++ 152, 104, 5, 208, 161, 245, 192, 82, 81, 66, 65, 235, 2, 1, 0, 224, ++ 2, 33, 9, 240, 74, 254, 6, 70, 0, 40, 0, 240, 35, 129, 53, 177, 32, ++ 70, 41, 70, 180, 248, 246, 32, 51, 70, 255, 247, 154, 250, 180, 248, ++ 246, 144, 72, 70, 214, 243, 236, 246, 9, 244, 96, 87, 163, 107, 183, ++ 245, 0, 95, 152, 104, 5, 208, 167, 245, 192, 83, 89, 66, 65, 235, 3, ++ 1, 0, 224, 2, 33, 9, 240, 41, 254, 163, 107, 5, 70, 16, 185, 152, 104, ++ 49, 70, 23, 224, 183, 245, 0, 95, 152, 104, 6, 208, 167, 245, 192, 88, ++ 216, 241, 0, 1, 65, 235, 8, 1, 0, 224, 2, 33, 9, 240, 21, 254, 128, ++ 70, 80, 185, 163, 107, 49, 70, 152, 104, 9, 240, 28, 254, 163, 107, ++ 41, 70, 152, 104, 9, 240, 23, 254, 228, 224, 212, 248, 136, 4, 184, ++ 177, 9, 240, 45, 254, 183, 245, 0, 95, 6, 208, 167, 245, 192, 92, 220, ++ 241, 0, 3, 67, 235, 12, 3, 0, 224, 2, 35, 152, 66, 8, 208, 163, 107, ++ 212, 248, 136, 20, 152, 104, 9, 240, 254, 253, 0, 35, 196, 248, 136, ++ 52, 212, 248, 136, 52, 251, 185, 163, 107, 183, 245, 0, 95, 152, 104, ++ 6, 208, 167, 245, 192, 94, 222, 241, 0, 1, 65, 235, 14, 1, 0, 224, 2, ++ 33, 9, 240, 219, 253, 196, 248, 136, 4, 104, 185, 163, 107, 49, 70, ++ 152, 104, 9, 240, 225, 253, 163, 107, 41, 70, 152, 104, 9, 240, 220, ++ 253, 163, 107, 65, 70, 152, 104, 190, 231, 212, 248, 136, 4, 9, 240, ++ 165, 253, 32, 70, 254, 247, 215, 255, 40, 70, 148, 249, 31, 17, 9, 240, ++ 254, 254, 0, 35, 13, 241, 23, 2, 0, 147, 32, 70, 67, 70, 73, 70, 255, ++ 247, 4, 255, 64, 70, 49, 70, 9, 240, 167, 255, 64, 70, 148, 249, 9, ++ 20, 9, 240, 120, 255, 65, 70, 40, 70, 9, 240, 158, 255, 148, 248, 252, ++ 16, 99, 41, 2, 216, 40, 70, 9, 240, 129, 255, 40, 70, 9, 240, 156, 254, ++ 40, 70, 9, 240, 157, 254, 148, 248, 11, 52, 7, 70, 155, 0, 152, 66, ++ 111, 240, 127, 1, 40, 70, 184, 191, 223, 178, 9, 240, 164, 254, 255, ++ 178, 95, 250, 128, 249, 131, 70, 132, 248, 34, 113, 132, 248, 35, 145, ++ 212, 248, 156, 4, 180, 248, 246, 16, 10, 240, 134, 248, 1, 40, 15, 209, ++ 180, 248, 246, 16, 0, 34, 75, 70, 212, 248, 156, 4, 10, 240, 98, 248, ++ 212, 248, 156, 4, 180, 248, 246, 16, 0, 34, 59, 70, 10, 240, 63, 248, ++ 0, 35, 132, 248, 53, 177, 132, 248, 58, 49, 132, 248, 36, 49, 186, 241, ++ 0, 15, 3, 208, 40, 70, 81, 70, 9, 240, 175, 254, 148, 248, 38, 49, 40, ++ 70, 11, 177, 3, 155, 35, 177, 148, 249, 34, 17, 9, 240, 15, 255, 3, ++ 224, 148, 249, 35, 17, 9, 240, 30, 255, 212, 248, 136, 4, 41, 70, 9, ++ 240, 93, 255, 212, 248, 156, 4, 180, 248, 246, 16, 10, 240, 76, 248, ++ 1, 40, 3, 70, 10, 209, 212, 248, 136, 4, 161, 107, 0, 144, 136, 104, ++ 180, 248, 246, 32, 212, 248, 156, 20, 9, 240, 178, 255, 163, 107, 49, ++ 70, 152, 104, 9, 240, 66, 253, 163, 107, 41, 70, 152, 104, 9, 240, 61, ++ 253, 163, 107, 65, 70, 152, 104, 9, 240, 56, 253, 186, 241, 0, 15, 3, ++ 209, 163, 108, 11, 177, 32, 70, 152, 71, 7, 176, 189, 232, 240, 143, ++ 112, 181, 130, 107, 30, 70, 0, 35, 128, 248, 31, 17, 128, 248, 56, 49, ++ 19, 127, 4, 70, 243, 177, 208, 248, 20, 17, 64, 246, 2, 3, 11, 64, 195, ++ 185, 208, 248, 232, 48, 211, 248, 32, 49, 3, 240, 1, 3, 131, 240, 1, ++ 5, 19, 177, 16, 105, 9, 240, 141, 248, 32, 70, 49, 70, 0, 34, 255, 247, ++ 95, 254, 32, 70, 255, 247, 6, 249, 29, 185, 163, 107, 24, 105, 9, 240, ++ 131, 248, 0, 32, 112, 189, 144, 248, 35, 1, 127, 40, 40, 191, 127, 32, ++ 112, 71, 144, 248, 34, 1, 0, 40, 56, 191, 0, 32, 112, 71, 128, 248, ++ 252, 16, 112, 71, 56, 181, 131, 107, 4, 70, 13, 70, 24, 105, 9, 240, ++ 104, 248, 32, 70, 41, 70, 0, 34, 255, 247, 58, 254, 32, 70, 255, 247, ++ 225, 248, 163, 107, 24, 105, 189, 232, 56, 64, 9, 240, 93, 184, 128, ++ 248, 245, 16, 112, 71, 112, 71, 248, 181, 31, 70, 0, 35, 59, 112, 144, ++ 248, 38, 49, 4, 70, 13, 70, 22, 70, 131, 177, 131, 107, 27, 127, 107, ++ 177, 255, 247, 113, 249, 32, 70, 41, 70, 58, 70, 8, 240, 207, 250, 43, ++ 120, 32, 70, 51, 112, 189, 232, 248, 64, 255, 247, 114, 185, 248, 189, ++ 1, 35, 240, 181, 19, 114, 19, 104, 21, 70, 67, 240, 8, 2, 42, 96, 176, ++ 249, 60, 33, 133, 176, 1, 50, 4, 191, 67, 240, 9, 3, 43, 96, 144, 248, ++ 38, 49, 4, 70, 15, 70, 27, 177, 43, 104, 67, 240, 2, 3, 43, 96, 180, ++ 248, 246, 16, 163, 107, 1, 244, 96, 81, 177, 245, 0, 95, 152, 104, 5, ++ 208, 161, 245, 192, 86, 113, 66, 65, 235, 6, 1, 0, 224, 2, 33, 9, 240, ++ 133, 252, 6, 70, 144, 177, 0, 35, 180, 248, 246, 16, 0, 147, 32, 70, ++ 51, 70, 13, 241, 15, 2, 255, 247, 200, 253, 48, 70, 169, 106, 9, 240, ++ 195, 253, 163, 107, 49, 70, 152, 104, 9, 240, 126, 252, 32, 70, 57, ++ 70, 234, 106, 255, 247, 204, 253, 148, 248, 36, 49, 32, 70, 107, 114, ++ 5, 241, 10, 1, 5, 241, 18, 3, 5, 241, 14, 2, 255, 247, 147, 255, 148, ++ 248, 38, 49, 227, 177, 163, 107, 27, 127, 203, 177, 32, 70, 255, 247, ++ 10, 249, 148, 248, 34, 49, 235, 116, 148, 248, 34, 49, 43, 117, 212, ++ 248, 156, 48, 51, 177, 32, 70, 152, 71, 24, 177, 43, 104, 67, 240, 3, ++ 3, 2, 224, 43, 104, 35, 240, 3, 3, 43, 96, 32, 70, 255, 247, 0, 249, ++ 5, 176, 240, 189, 131, 107, 91, 127, 11, 177, 8, 240, 143, 190, 24, ++ 70, 112, 71, 131, 107, 91, 127, 11, 177, 8, 240, 184, 190, 24, 70, 112, ++ 71, 131, 107, 1, 32, 147, 248, 134, 48, 11, 112, 112, 71, 131, 107, ++ 131, 248, 134, 16, 112, 71, 112, 181, 144, 248, 254, 80, 4, 70, 14, ++ 70, 0, 45, 116, 209, 1, 35, 128, 248, 254, 48, 255, 247, 221, 252, 132, ++ 248, 7, 81, 32, 70, 49, 70, 255, 247, 202, 252, 212, 248, 232, 48, 211, ++ 248, 32, 49, 212, 248, 20, 49, 196, 248, 144, 81, 154, 7, 11, 212, 212, ++ 248, 148, 36, 210, 248, 40, 40, 50, 177, 146, 248, 74, 32, 26, 185, ++ 67, 240, 32, 3, 196, 248, 20, 49, 229, 107, 0, 45, 80, 208, 1, 33, 32, ++ 70, 255, 247, 223, 249, 180, 248, 246, 16, 180, 248, 250, 48, 1, 244, ++ 96, 81, 153, 66, 3, 208, 163, 107, 24, 105, 8, 240, 122, 255, 1, 33, ++ 132, 248, 41, 19, 32, 70, 255, 247, 121, 252, 163, 107, 147, 248, 132, ++ 32, 1, 42, 180, 248, 246, 32, 10, 209, 18, 244, 64, 79, 1, 209, 218, ++ 111, 10, 224, 211, 248, 128, 32, 1, 42, 136, 191, 0, 34, 4, 224, 18, ++ 244, 64, 79, 12, 191, 26, 111, 154, 111, 218, 102, 217, 110, 0, 34, ++ 32, 70, 254, 247, 228, 255, 32, 70, 168, 71, 0, 37, 163, 107, 132, 248, ++ 253, 80, 147, 248, 134, 16, 32, 70, 255, 247, 147, 255, 163, 107, 132, ++ 248, 254, 80, 24, 105, 146, 33, 8, 240, 54, 255, 148, 248, 160, 58, ++ 64, 0, 1, 43, 164, 248, 130, 2, 4, 209, 60, 35, 164, 248, 102, 50, 196, ++ 248, 204, 83, 112, 189, 16, 181, 208, 248, 148, 52, 201, 178, 28, 120, ++ 140, 66, 5, 209, 208, 248, 228, 16, 161, 248, 118, 34, 131, 248, 180, ++ 32, 16, 189, 0, 0, 240, 181, 30, 70, 50, 75, 139, 176, 13, 70, 20, 70, ++ 1, 175, 3, 241, 16, 14, 24, 104, 89, 104, 58, 70, 3, 194, 8, 51, 115, ++ 69, 23, 70, 247, 209, 44, 75, 5, 175, 3, 241, 16, 14, 24, 104, 89, 104, ++ 58, 70, 3, 194, 8, 51, 115, 69, 23, 70, 247, 209, 0, 33, 2, 34, 9, 168, ++ 213, 243, 176, 241, 41, 104, 0, 35, 10, 70, 24, 70, 7, 224, 82, 8, 1, ++ 48, 192, 178, 2, 240, 1, 5, 0, 45, 24, 191, 3, 70, 0, 42, 245, 209, ++ 4, 43, 3, 216, 195, 241, 4, 2, 145, 64, 11, 224, 1, 32, 90, 31, 16, ++ 250, 2, 242, 81, 24, 26, 24, 144, 64, 1, 66, 24, 191, 211, 178, 26, ++ 31, 209, 64, 10, 170, 1, 240, 15, 1, 81, 24, 17, 248, 36, 44, 3, 235, ++ 67, 0, 17, 248, 20, 28, 2, 235, 128, 2, 153, 66, 140, 191, 19, 70, 83, ++ 28, 155, 178, 26, 178, 64, 246, 161, 33, 74, 67, 18, 19, 32, 50, 34, ++ 128, 17, 154, 18, 136, 194, 241, 127, 66, 2, 245, 126, 2, 2, 245, 255, ++ 50, 242, 50, 155, 24, 51, 128, 11, 176, 240, 189, 164, 21, 4, 0, 180, ++ 21, 4, 0, 128, 248, 216, 26, 112, 71, 16, 181, 144, 248, 7, 49, 0, 43, ++ 55, 208, 219, 7, 201, 178, 39, 213, 208, 248, 12, 49, 139, 66, 29, 209, ++ 144, 248, 201, 58, 83, 177, 0, 35, 132, 107, 228, 24, 1, 51, 8, 43, ++ 132, 248, 32, 33, 248, 209, 0, 35, 128, 248, 201, 58, 131, 107, 211, ++ 248, 40, 65, 27, 25, 131, 248, 32, 33, 131, 107, 211, 248, 40, 65, 7, ++ 44, 1, 208, 1, 52, 0, 224, 0, 36, 195, 248, 40, 65, 144, 248, 7, 49, ++ 35, 240, 1, 3, 128, 248, 7, 49, 144, 248, 7, 49, 19, 240, 2, 15, 7, ++ 208, 35, 240, 2, 3, 128, 248, 7, 49, 131, 107, 24, 105, 8, 240, 152, ++ 254, 0, 32, 16, 189, 56, 181, 144, 248, 7, 49, 4, 70, 0, 43, 45, 209, ++ 1, 41, 2, 208, 2, 41, 44, 209, 1, 224, 192, 248, 12, 33, 163, 107, 128, ++ 248, 7, 17, 26, 106, 148, 248, 125, 1, 196, 248, 8, 33, 160, 185, 148, ++ 248, 16, 81, 0, 45, 30, 209, 24, 105, 142, 33, 8, 240, 78, 254, 163, ++ 107, 65, 0, 137, 178, 24, 105, 116, 49, 1, 34, 8, 240, 67, 254, 32, ++ 70, 8, 240, 131, 252, 40, 70, 56, 189, 180, 248, 246, 16, 32, 70, 111, ++ 240, 94, 2, 189, 232, 56, 64, 255, 247, 141, 191, 111, 240, 24, 0, 56, ++ 189, 111, 240, 2, 0, 56, 189, 16, 181, 4, 70, 255, 247, 116, 251, 2, ++ 33, 194, 178, 32, 70, 189, 232, 16, 64, 255, 247, 187, 191, 112, 71, ++ 0, 33, 111, 240, 91, 2, 255, 247, 118, 191, 0, 35, 129, 107, 26, 70, ++ 200, 24, 144, 249, 32, 1, 1, 51, 8, 43, 2, 68, 248, 209, 0, 42, 184, ++ 191, 7, 50, 210, 8, 80, 178, 112, 71, 0, 32, 112, 71, 48, 181, 208, ++ 248, 228, 32, 205, 136, 146, 248, 41, 54, 75, 185, 131, 107, 91, 105, ++ 10, 43, 5, 217, 76, 138, 20, 244, 128, 115, 1, 209, 1, 34, 28, 224, ++ 140, 136, 235, 178, 20, 240, 3, 15, 1, 208, 157, 43, 7, 208, 133, 107, ++ 109, 105, 35, 45, 7, 209, 77, 138, 21, 240, 32, 15, 3, 208, 1, 35, 139, ++ 119, 0, 35, 10, 224, 144, 249, 208, 3, 27, 24, 224, 4, 68, 191, 146, ++ 249, 30, 38, 155, 24, 203, 119, 0, 34, 138, 119, 11, 119, 0, 35, 75, ++ 119, 48, 189, 45, 233, 240, 79, 35, 79, 143, 176, 28, 70, 5, 173, 0, ++ 35, 6, 70, 136, 70, 147, 70, 13, 147, 15, 207, 15, 197, 151, 232, 15, ++ 0, 221, 248, 96, 144, 133, 232, 15, 0, 185, 241, 3, 15, 4, 217, 13, ++ 168, 33, 70, 4, 34, 211, 247, 249, 252, 221, 248, 52, 160, 5, 173, 55, ++ 70, 25, 155, 205, 248, 0, 144, 1, 147, 26, 155, 56, 70, 2, 147, 27, ++ 155, 65, 70, 3, 147, 46, 104, 35, 70, 90, 70, 176, 71, 85, 248, 4, 63, ++ 27, 177, 16, 241, 23, 15, 235, 208, 17, 224, 16, 241, 23, 15, 14, 209, ++ 27, 155, 56, 70, 0, 147, 13, 155, 65, 70, 1, 147, 26, 241, 0, 3, 24, ++ 191, 1, 35, 2, 147, 34, 70, 25, 155, 254, 247, 69, 252, 15, 176, 189, ++ 232, 240, 143, 0, 191, 196, 21, 4, 0, 195, 105, 4, 59, 8, 43, 6, 216, ++ 223, 232, 3, 240, 24, 5, 9, 7, 9, 5, 11, 5, 13, 0, 0, 32, 112, 71, 23, ++ 32, 112, 71, 4, 32, 112, 71, 7, 32, 112, 71, 144, 248, 226, 3, 1, 40, ++ 8, 208, 3, 40, 20, 191, 79, 244, 131, 112, 79, 244, 139, 112, 112, 71, ++ 1, 32, 112, 71, 79, 244, 139, 112, 112, 71, 247, 181, 4, 70, 13, 70, ++ 22, 70, 31, 70, 59, 177, 3, 42, 5, 217, 1, 168, 25, 70, 4, 34, 211, ++ 247, 152, 252, 1, 224, 0, 35, 1, 147, 27, 45, 3, 208, 0, 47, 85, 208, ++ 0, 46, 83, 221, 211, 45, 26, 208, 4, 220, 27, 45, 15, 208, 135, 45, ++ 79, 209, 7, 224, 212, 45, 35, 208, 165, 245, 154, 117, 3, 61, 1, 45, ++ 71, 216, 79, 224, 32, 70, 255, 247, 35, 255, 56, 96, 74, 224, 163, 107, ++ 29, 127, 0, 45, 64, 209, 32, 70, 254, 247, 196, 251, 67, 224, 163, 107, ++ 219, 110, 59, 96, 212, 248, 104, 81, 21, 240, 1, 5, 59, 208, 67, 240, ++ 128, 3, 59, 96, 212, 248, 108, 33, 67, 234, 2, 19, 59, 96, 49, 224, ++ 1, 154, 0, 42, 43, 219, 4, 42, 41, 220, 163, 107, 217, 110, 145, 66, ++ 40, 208, 29, 127, 61, 179, 218, 102, 24, 105, 8, 240, 35, 253, 1, 155, ++ 35, 177, 32, 70, 0, 33, 1, 34, 254, 247, 175, 253, 163, 107, 1, 34, ++ 217, 110, 32, 70, 254, 247, 169, 253, 163, 107, 0, 40, 24, 105, 12, ++ 191, 111, 240, 2, 5, 0, 37, 8, 240, 16, 253, 12, 224, 111, 240, 1, 5, ++ 9, 224, 111, 240, 22, 5, 6, 224, 111, 240, 4, 5, 3, 224, 111, 240, 28, ++ 5, 0, 224, 0, 37, 40, 70, 254, 189, 131, 107, 19, 181, 26, 106, 4, 70, ++ 1, 50, 26, 98, 144, 248, 4, 33, 0, 42, 0, 240, 178, 128, 176, 248, 108, ++ 35, 42, 177, 208, 248, 148, 20, 161, 248, 54, 34, 161, 248, 58, 34, ++ 180, 248, 112, 35, 42, 177, 212, 248, 148, 20, 161, 248, 40, 34, 161, ++ 248, 36, 34, 180, 248, 110, 35, 42, 177, 212, 248, 148, 20, 161, 248, ++ 34, 34, 161, 248, 38, 34, 212, 248, 20, 17, 64, 246, 6, 34, 10, 64, ++ 42, 185, 147, 248, 44, 49, 19, 177, 32, 70, 254, 247, 59, 253, 163, ++ 107, 26, 106, 27, 110, 178, 251, 243, 241, 3, 251, 17, 35, 171, 185, ++ 32, 70, 254, 247, 234, 253, 212, 248, 20, 49, 64, 246, 2, 2, 161, 107, ++ 26, 64, 0, 50, 8, 105, 24, 191, 1, 34, 180, 248, 246, 16, 195, 243, ++ 128, 3, 8, 240, 212, 252, 32, 70, 254, 247, 228, 253, 212, 248, 20, ++ 33, 64, 246, 14, 35, 19, 64, 179, 185, 163, 107, 212, 248, 48, 34, 25, ++ 106, 210, 248, 144, 32, 211, 248, 24, 49, 138, 26, 154, 66, 11, 211, ++ 148, 248, 246, 32, 32, 70, 1, 33, 255, 247, 33, 254, 162, 107, 212, ++ 248, 48, 50, 18, 106, 195, 248, 144, 32, 148, 248, 7, 49, 75, 177, 163, ++ 107, 26, 106, 212, 248, 8, 49, 211, 26, 5, 43, 2, 217, 0, 35, 132, 248, ++ 7, 49, 212, 248, 152, 33, 42, 177, 163, 107, 25, 106, 27, 110, 138, ++ 26, 154, 66, 13, 211, 212, 248, 20, 33, 64, 246, 2, 3, 19, 64, 59, 185, ++ 32, 70, 254, 247, 242, 252, 24, 177, 163, 107, 27, 106, 196, 248, 152, ++ 49, 212, 248, 20, 33, 64, 246, 15, 35, 19, 64, 43, 187, 32, 70, 254, ++ 247, 13, 251, 32, 70, 254, 247, 9, 251, 212, 248, 48, 50, 211, 248, ++ 136, 32, 18, 177, 1, 58, 195, 248, 136, 32, 212, 248, 168, 48, 11, 177, ++ 32, 70, 152, 71, 163, 107, 24, 105, 8, 240, 88, 252, 104, 177, 163, ++ 107, 1, 169, 24, 105, 13, 241, 7, 2, 8, 240, 83, 252, 32, 70, 157, 248, ++ 7, 16, 189, 248, 4, 32, 254, 247, 235, 250, 0, 32, 28, 189, 3, 70, 0, ++ 33, 152, 107, 64, 24, 1, 49, 8, 41, 128, 248, 32, 33, 248, 209, 154, ++ 107, 0, 33, 194, 248, 40, 17, 209, 110, 3, 41, 7, 209, 211, 248, 104, ++ 17, 201, 7, 3, 213, 18, 106, 8, 50, 195, 248, 92, 33, 0, 34, 153, 24, ++ 2, 50, 79, 246, 164, 112, 32, 42, 161, 248, 168, 10, 247, 209, 0, 32, ++ 131, 248, 200, 10, 112, 71, 67, 11, 179, 245, 128, 95, 19, 96, 164, ++ 191, 163, 245, 0, 83, 19, 96, 192, 4, 192, 12, 176, 245, 128, 95, 8, ++ 96, 164, 191, 160, 245, 0, 80, 8, 96, 112, 71, 73, 246, 117, 51, 75, ++ 96, 0, 35, 11, 96, 79, 244, 52, 2, 152, 66, 172, 191, 1, 35, 79, 240, ++ 255, 51, 2, 251, 3, 2, 45, 233, 240, 65, 79, 240, 180, 116, 146, 251, ++ 244, 240, 4, 251, 16, 34, 33, 72, 0, 251, 3, 35, 0, 43, 5, 219, 218, ++ 19, 1, 50, 181, 42, 13, 221, 27, 24, 8, 224, 90, 66, 210, 19, 1, 50, ++ 82, 16, 82, 66, 90, 50, 4, 218, 3, 245, 52, 3, 79, 240, 255, 52, 0, ++ 224, 1, 36, 0, 32, 2, 70, 5, 70, 78, 104, 171, 66, 15, 104, 223, 248, ++ 76, 192, 70, 250, 2, 248, 9, 221, 184, 68, 23, 65, 246, 27, 78, 96, ++ 92, 248, 0, 96, 193, 248, 0, 128, 173, 25, 9, 224, 200, 235, 7, 8, 23, ++ 65, 246, 25, 78, 96, 92, 248, 0, 96, 193, 248, 0, 128, 173, 27, 1, 50, ++ 4, 48, 18, 42, 223, 209, 75, 104, 99, 67, 75, 96, 11, 104, 92, 67, 12, ++ 96, 189, 232, 240, 129, 0, 191, 0, 0, 76, 255, 104, 62, 4, 0, 247, 181, ++ 2, 171, 3, 233, 3, 0, 1, 156, 0, 155, 0, 32, 16, 96, 36, 1, 27, 1, 1, ++ 70, 0, 43, 67, 250, 1, 245, 68, 250, 1, 247, 9, 78, 6, 218, 219, 25, ++ 54, 88, 23, 104, 100, 27, 190, 27, 22, 96, 5, 224, 219, 27, 54, 88, ++ 23, 104, 100, 25, 190, 25, 22, 96, 1, 49, 4, 48, 18, 41, 231, 209, 254, ++ 189, 104, 62, 4, 0, 16, 181, 4, 70, 208, 248, 52, 2, 6, 224, 3, 104, ++ 196, 248, 52, 50, 220, 247, 69, 250, 212, 248, 52, 2, 0, 40, 246, 209, ++ 4, 245, 36, 115, 196, 248, 48, 50, 79, 246, 206, 115, 196, 248, 52, ++ 2, 164, 248, 28, 51, 196, 248, 16, 3, 196, 248, 20, 3, 16, 189, 112, ++ 71, 128, 234, 224, 115, 163, 235, 224, 115, 0, 32, 1, 224, 1, 48, 192, ++ 178, 83, 250, 0, 242, 0, 42, 249, 220, 112, 71, 16, 181, 0, 35, 2, 70, ++ 24, 70, 79, 240, 128, 65, 25, 65, 12, 24, 148, 66, 79, 234, 80, 0, 156, ++ 191, 196, 235, 2, 2, 8, 67, 2, 51, 32, 43, 241, 209, 144, 66, 56, 191, ++ 1, 48, 16, 189, 131, 107, 131, 248, 135, 16, 131, 107, 131, 248, 136, ++ 32, 131, 107, 131, 248, 137, 16, 131, 107, 131, 248, 138, 32, 112, 71, ++ 131, 107, 131, 248, 137, 16, 112, 71, 0, 72, 112, 71, 232, 62, 4, 0, ++ 16, 181, 12, 70, 1, 33, 8, 240, 217, 249, 32, 128, 1, 32, 16, 189, 6, ++ 240, 76, 189, 112, 71, 0, 32, 112, 71, 0, 35, 11, 113, 202, 128, 130, ++ 107, 24, 70, 18, 106, 193, 248, 244, 50, 138, 96, 79, 246, 206, 114, ++ 161, 248, 0, 35, 1, 34, 193, 248, 240, 50, 129, 248, 8, 35, 112, 71, ++ 208, 248, 52, 2, 3, 224, 195, 136, 139, 66, 2, 208, 0, 104, 0, 40, 249, ++ 209, 112, 71, 8, 181, 255, 247, 243, 255, 24, 177, 0, 35, 3, 113, 128, ++ 248, 8, 51, 8, 189, 112, 181, 5, 70, 14, 70, 208, 248, 52, 66, 255, ++ 247, 230, 255, 136, 185, 12, 224, 35, 121, 75, 185, 148, 248, 8, 51, ++ 51, 185, 40, 70, 33, 70, 50, 70, 255, 247, 199, 255, 2, 32, 112, 189, ++ 36, 104, 0, 44, 240, 209, 32, 70, 112, 189, 1, 32, 112, 189, 248, 181, ++ 4, 70, 14, 70, 255, 247, 223, 255, 7, 70, 96, 187, 79, 244, 67, 112, ++ 220, 247, 156, 249, 5, 70, 64, 179, 57, 70, 79, 244, 67, 114, 212, 243, ++ 123, 245, 163, 107, 238, 128, 27, 106, 171, 96, 79, 246, 206, 115, 165, ++ 248, 0, 51, 148, 248, 147, 50, 133, 248, 119, 50, 1, 35, 133, 248, 8, ++ 51, 212, 248, 52, 50, 43, 96, 59, 185, 180, 248, 246, 48, 179, 66, 4, ++ 191, 5, 245, 29, 115, 196, 248, 48, 50, 148, 248, 56, 50, 196, 248, ++ 52, 82, 1, 51, 132, 248, 56, 50, 0, 32, 248, 189, 111, 240, 26, 0, 248, ++ 189, 16, 181, 176, 248, 246, 16, 4, 70, 255, 247, 146, 255, 212, 248, ++ 48, 34, 0, 35, 194, 248, 136, 48, 1, 34, 132, 248, 5, 33, 132, 248, ++ 6, 49, 111, 240, 22, 0, 16, 189, 0, 32, 112, 71, 112, 181, 4, 70, 13, ++ 70, 255, 247, 126, 255, 41, 70, 6, 70, 32, 70, 254, 247, 179, 255, 99, ++ 108, 22, 177, 6, 245, 29, 114, 1, 224, 4, 245, 36, 114, 196, 248, 48, ++ 34, 19, 177, 32, 70, 41, 70, 152, 71, 54, 179, 32, 70, 255, 247, 227, ++ 255, 212, 248, 48, 34, 83, 120, 115, 177, 163, 107, 212, 248, 36, 19, ++ 24, 105, 8, 240, 92, 250, 163, 107, 0, 34, 24, 105, 212, 248, 36, 19, ++ 19, 70, 8, 240, 81, 250, 16, 224, 148, 248, 101, 50, 107, 177, 3, 43, ++ 11, 208, 163, 107, 210, 248, 128, 32, 25, 106, 155, 110, 138, 26, 154, ++ 66, 3, 211, 32, 70, 2, 33, 255, 247, 172, 255, 1, 35, 132, 248, 201, ++ 58, 212, 248, 20, 49, 161, 107, 64, 246, 2, 2, 26, 64, 8, 105, 0, 50, ++ 41, 70, 24, 191, 1, 34, 195, 243, 128, 3, 189, 232, 112, 64, 8, 240, ++ 97, 186, 8, 181, 208, 248, 144, 48, 11, 177, 152, 71, 8, 189, 111, 240, ++ 22, 0, 8, 189, 45, 233, 247, 67, 134, 70, 79, 240, 0, 8, 2, 168, 12, ++ 70, 21, 70, 64, 248, 4, 141, 113, 70, 4, 34, 30, 70, 10, 159, 221, 248, ++ 44, 144, 211, 247, 81, 249, 1, 155, 19, 224, 184, 241, 0, 15, 1, 208, ++ 184, 69, 7, 217, 3, 240, 15, 2, 82, 0, 170, 26, 6, 248, 8, 32, 27, 9, ++ 2, 224, 50, 120, 6, 248, 8, 32, 8, 241, 1, 8, 95, 250, 136, 248, 200, ++ 69, 233, 211, 47, 177, 123, 30, 242, 92, 100, 0, 20, 27, 244, 84, 244, ++ 85, 189, 232, 254, 131, 0, 32, 112, 71, 19, 181, 12, 70, 19, 70, 0, ++ 33, 34, 70, 0, 145, 254, 247, 179, 248, 28, 189, 131, 107, 16, 181, ++ 154, 105, 4, 70, 146, 0, 25, 213, 176, 248, 246, 32, 18, 244, 64, 79, ++ 20, 209, 24, 105, 8, 240, 15, 250, 212, 248, 232, 48, 179, 248, 180, ++ 38, 146, 178, 66, 240, 3, 2, 163, 248, 180, 38, 212, 248, 232, 48, 179, ++ 248, 184, 38, 146, 178, 66, 240, 192, 2, 163, 248, 184, 38, 16, 189, ++ 131, 107, 155, 105, 153, 0, 23, 213, 176, 248, 246, 48, 19, 244, 64, ++ 79, 18, 209, 208, 248, 232, 48, 179, 248, 180, 38, 146, 178, 66, 240, ++ 3, 2, 163, 248, 180, 38, 208, 248, 232, 32, 178, 248, 184, 54, 35, 240, ++ 192, 3, 27, 4, 27, 12, 162, 248, 184, 54, 112, 71, 3, 70, 1, 224, 11, ++ 70, 17, 70, 179, 251, 241, 242, 1, 251, 18, 50, 0, 42, 247, 209, 8, ++ 70, 112, 71, 248, 181, 13, 70, 176, 248, 246, 16, 4, 70, 22, 70, 31, ++ 70, 254, 247, 0, 255, 64, 185, 180, 249, 34, 52, 51, 96, 180, 249, 36, ++ 52, 59, 96, 180, 249, 38, 52, 43, 96, 248, 189, 208, 248, 228, 0, 112, ++ 71, 208, 248, 196, 0, 8, 181, 0, 177, 128, 71, 8, 189, 8, 181, 208, ++ 248, 200, 48, 19, 177, 8, 70, 152, 71, 8, 189, 24, 70, 8, 189, 8, 181, ++ 208, 248, 204, 48, 19, 177, 8, 70, 152, 71, 8, 189, 24, 70, 8, 189, ++ 8, 181, 208, 248, 208, 48, 19, 177, 8, 70, 17, 70, 152, 71, 8, 189, ++ 8, 181, 208, 248, 212, 48, 128, 248, 114, 19, 3, 177, 152, 71, 8, 189, ++ 0, 49, 24, 191, 1, 33, 128, 248, 117, 19, 112, 71, 0, 35, 192, 248, ++ 136, 52, 112, 71, 7, 181, 131, 107, 2, 34, 0, 146, 24, 105, 0, 33, 19, ++ 70, 8, 240, 84, 249, 14, 189, 7, 181, 131, 107, 2, 34, 0, 146, 0, 33, ++ 24, 105, 11, 70, 8, 240, 74, 249, 14, 189, 240, 181, 0, 34, 137, 176, ++ 7, 146, 14, 154, 4, 70, 3, 42, 13, 70, 15, 158, 17, 159, 4, 217, 7, ++ 168, 25, 70, 4, 34, 211, 247, 110, 248, 64, 242, 126, 51, 157, 66, 0, ++ 240, 54, 129, 40, 216, 181, 245, 33, 127, 0, 240, 2, 129, 12, 216, 181, ++ 245, 32, 127, 74, 208, 2, 216, 82, 61, 1, 45, 67, 224, 64, 242, 129, ++ 35, 157, 66, 64, 240, 78, 129, 187, 224, 64, 242, 138, 35, 157, 66, ++ 0, 240, 6, 129, 5, 216, 64, 242, 134, 35, 157, 66, 64, 240, 66, 129, ++ 237, 224, 64, 242, 139, 35, 157, 66, 0, 240, 246, 128, 64, 242, 142, ++ 35, 157, 66, 64, 240, 55, 129, 251, 224, 64, 242, 131, 51, 157, 66, ++ 0, 240, 253, 128, 16, 216, 181, 245, 96, 127, 0, 240, 12, 129, 192, ++ 240, 5, 129, 64, 242, 129, 51, 157, 66, 0, 240, 10, 129, 64, 242, 130, ++ 51, 157, 66, 64, 240, 32, 129, 238, 224, 64, 242, 219, 51, 157, 66, ++ 0, 240, 11, 129, 5, 216, 64, 242, 218, 51, 157, 66, 64, 240, 20, 129, ++ 252, 224, 165, 245, 120, 117, 2, 61, 3, 45, 64, 242, 8, 129, 11, 225, ++ 163, 107, 27, 127, 0, 43, 0, 240, 4, 129, 32, 70, 255, 247, 123, 255, ++ 212, 248, 232, 48, 211, 248, 32, 49, 3, 240, 1, 3, 131, 240, 1, 7, 27, ++ 177, 163, 107, 24, 105, 8, 240, 209, 248, 32, 70, 254, 247, 248, 249, ++ 212, 248, 228, 48, 147, 248, 132, 56, 1, 43, 7, 209, 148, 248, 72, 34, ++ 34, 185, 148, 248, 95, 34, 10, 185, 132, 248, 72, 50, 148, 248, 69, ++ 2, 148, 248, 68, 50, 0, 144, 148, 248, 70, 2, 0, 37, 1, 144, 148, 248, ++ 71, 2, 148, 248, 66, 18, 2, 144, 148, 248, 95, 2, 148, 248, 67, 34, ++ 3, 144, 148, 248, 72, 2, 4, 149, 5, 144, 32, 70, 253, 247, 178, 255, ++ 48, 96, 212, 248, 228, 48, 147, 248, 132, 56, 1, 43, 39, 209, 148, 248, ++ 72, 50, 1, 43, 35, 209, 148, 248, 68, 50, 1, 43, 31, 209, 194, 224, ++ 148, 248, 69, 226, 9, 32, 205, 248, 0, 224, 148, 248, 70, 226, 132, ++ 248, 72, 2, 205, 248, 4, 224, 148, 248, 71, 226, 5, 144, 205, 248, 8, ++ 224, 148, 248, 95, 226, 148, 248, 66, 18, 148, 248, 67, 34, 32, 70, ++ 205, 248, 12, 224, 4, 149, 253, 247, 134, 255, 128, 5, 128, 13, 48, ++ 96, 32, 70, 254, 247, 171, 249, 31, 185, 163, 107, 24, 105, 8, 240, ++ 114, 248, 32, 70, 255, 247, 19, 255, 139, 224, 7, 155, 26, 22, 2, 240, ++ 15, 2, 4, 42, 0, 242, 141, 128, 24, 21, 0, 240, 3, 0, 1, 40, 0, 242, ++ 135, 128, 153, 21, 1, 240, 3, 1, 3, 41, 0, 240, 129, 128, 29, 20, 5, ++ 240, 15, 5, 1, 45, 123, 216, 31, 18, 255, 178, 167, 241, 10, 6, 246, ++ 178, 5, 46, 116, 216, 3, 240, 15, 6, 3, 46, 112, 216, 132, 248, 71, ++ 34, 26, 15, 27, 17, 3, 240, 15, 3, 132, 248, 66, 114, 132, 248, 67, ++ 98, 132, 248, 68, 82, 132, 248, 69, 2, 132, 248, 70, 18, 132, 248, 95, ++ 34, 132, 248, 72, 50, 83, 224, 8, 169, 79, 240, 255, 51, 65, 248, 4, ++ 61, 7, 224, 180, 248, 246, 16, 32, 70, 254, 247, 133, 253, 8, 169, 65, ++ 248, 4, 13, 48, 70, 58, 70, 210, 247, 80, 255, 64, 224, 7, 155, 132, ++ 248, 11, 52, 60, 224, 148, 248, 11, 52, 8, 169, 65, 248, 4, 61, 48, ++ 70, 4, 34, 240, 231, 212, 248, 20, 49, 195, 243, 0, 19, 51, 96, 46, ++ 224, 32, 70, 7, 169, 1, 34, 2, 224, 32, 70, 49, 70, 0, 34, 254, 247, ++ 180, 248, 46, 224, 32, 70, 49, 70, 253, 247, 157, 254, 41, 224, 32, ++ 70, 7, 153, 253, 247, 149, 254, 36, 224, 32, 70, 49, 70, 253, 247, 153, ++ 254, 31, 224, 32, 70, 7, 153, 253, 247, 145, 254, 26, 224, 212, 248, ++ 220, 48, 147, 177, 32, 70, 152, 71, 48, 96, 9, 224, 212, 248, 216, 48, ++ 91, 177, 7, 153, 74, 28, 2, 42, 10, 216, 32, 70, 73, 178, 152, 71, 0, ++ 32, 7, 224, 111, 240, 3, 0, 4, 224, 111, 240, 22, 0, 1, 224, 111, 240, ++ 28, 0, 9, 176, 240, 189, 64, 243, 135, 0, 82, 48, 255, 246, 56, 175, ++ 85, 231, 208, 248, 156, 4, 112, 71, 144, 248, 9, 4, 112, 71, 112, 71, ++ 112, 71, 128, 248, 160, 26, 112, 71, 0, 0, 2, 75, 24, 96, 2, 75, 25, ++ 96, 112, 71, 0, 191, 16, 116, 4, 0, 12, 116, 4, 0, 67, 177, 26, 177, ++ 208, 248, 148, 20, 145, 248, 180, 16, 33, 177, 128, 248, 230, 26, 1, ++ 224, 128, 248, 230, 58, 211, 241, 1, 3, 56, 191, 0, 35, 128, 248, 228, ++ 42, 128, 248, 229, 58, 112, 71, 16, 181, 12, 137, 3, 153, 2, 155, 2, ++ 145, 4, 153, 3, 145, 5, 153, 4, 145, 6, 153, 5, 145, 0, 105, 17, 70, ++ 34, 70, 189, 232, 16, 64, 22, 240, 129, 153, 3, 120, 51, 185, 177, 245, ++ 128, 111, 5, 216, 1, 35, 0, 248, 1, 59, 112, 71, 0, 32, 112, 71, 24, ++ 70, 112, 71, 3, 120, 11, 177, 0, 35, 3, 112, 112, 71, 112, 71, 112, ++ 71, 130, 107, 208, 248, 120, 1, 19, 106, 131, 66, 1, 211, 27, 26, 1, ++ 224, 192, 67, 195, 24, 144, 110, 131, 66, 52, 191, 0, 32, 1, 32, 112, ++ 71, 112, 71, 112, 71, 112, 71, 19, 32, 112, 71, 112, 71, 112, 71, 128, ++ 10, 112, 71, 3, 136, 155, 5, 155, 13, 67, 234, 129, 35, 3, 128, 112, ++ 71, 65, 67, 146, 2, 155, 1, 0, 251, 3, 32, 1, 245, 0, 65, 1, 235, 64, ++ 0, 73, 0, 144, 251, 241, 240, 112, 71, 208, 248, 228, 48, 1, 34, 163, ++ 248, 52, 36, 112, 71, 112, 71, 0, 0, 48, 181, 137, 177, 9, 75, 90, 67, ++ 1, 35, 2, 251, 3, 244, 129, 234, 225, 117, 165, 235, 225, 117, 180, ++ 251, 245, 240, 128, 178, 69, 67, 1, 51, 165, 66, 155, 178, 241, 209, ++ 48, 189, 2, 32, 48, 189, 64, 66, 15, 0, 129, 66, 184, 191, 8, 70, 112, ++ 71, 45, 233, 240, 71, 1, 41, 184, 191, 1, 33, 79, 240, 128, 116, 148, ++ 251, 241, 244, 36, 240, 127, 68, 36, 244, 112, 4, 0, 44, 8, 191, 1, ++ 36, 4, 251, 4, 243, 79, 72, 27, 19, 1, 43, 184, 191, 1, 35, 144, 251, ++ 243, 243, 77, 72, 1, 51, 144, 251, 243, 240, 127, 33, 1, 48, 21, 70, ++ 255, 247, 218, 255, 130, 70, 73, 72, 73, 78, 144, 251, 244, 240, 1, ++ 48, 150, 251, 240, 240, 127, 33, 1, 48, 255, 247, 206, 255, 129, 70, ++ 69, 72, 127, 33, 144, 251, 244, 240, 1, 48, 150, 251, 240, 240, 1, 48, ++ 255, 247, 195, 255, 127, 33, 128, 70, 16, 32, 255, 247, 190, 255, 40, ++ 128, 62, 72, 127, 33, 144, 251, 244, 240, 32, 240, 127, 64, 32, 244, ++ 112, 0, 160, 245, 248, 80, 63, 56, 1, 40, 184, 191, 1, 32, 150, 251, ++ 240, 240, 1, 48, 255, 247, 170, 255, 168, 129, 53, 72, 127, 33, 144, ++ 251, 244, 240, 32, 240, 127, 64, 32, 244, 112, 0, 160, 245, 120, 96, ++ 31, 56, 1, 40, 184, 191, 1, 32, 150, 251, 240, 240, 1, 48, 255, 247, ++ 150, 255, 232, 129, 44, 72, 127, 33, 144, 251, 244, 240, 32, 240, 127, ++ 64, 32, 244, 112, 0, 160, 245, 248, 64, 255, 56, 1, 40, 184, 191, 1, ++ 32, 150, 251, 240, 240, 1, 48, 255, 247, 130, 255, 255, 33, 40, 130, ++ 10, 32, 255, 247, 125, 255, 127, 33, 104, 130, 42, 32, 255, 247, 120, ++ 255, 7, 70, 30, 72, 79, 244, 122, 99, 144, 251, 244, 240, 160, 245, ++ 250, 48, 144, 251, 243, 240, 1, 48, 127, 33, 1, 40, 184, 191, 1, 32, ++ 255, 247, 103, 255, 23, 75, 6, 70, 147, 251, 244, 244, 164, 245, 248, ++ 100, 21, 75, 15, 60, 1, 44, 184, 191, 1, 36, 147, 251, 244, 244, 96, ++ 28, 127, 33, 255, 247, 86, 255, 165, 248, 2, 160, 165, 248, 4, 144, ++ 165, 248, 6, 128, 47, 129, 110, 129, 168, 130, 189, 232, 240, 135, 0, ++ 191, 255, 95, 16, 4, 255, 207, 7, 0, 255, 191, 30, 3, 255, 231, 3, 0, ++ 255, 95, 85, 3, 255, 255, 166, 9, 255, 127, 66, 8, 255, 31, 55, 14, ++ 255, 63, 233, 118, 255, 255, 243, 1, 255, 243, 1, 0, 112, 181, 128, ++ 34, 4, 70, 208, 248, 228, 80, 19, 70, 79, 244, 241, 97, 254, 247, 76, ++ 248, 32, 70, 2, 34, 0, 35, 79, 244, 241, 97, 254, 247, 69, 248, 181, ++ 248, 2, 54, 79, 244, 127, 66, 27, 2, 32, 70, 19, 64, 64, 242, 135, 113, ++ 254, 247, 58, 248, 181, 248, 4, 54, 79, 244, 127, 66, 27, 2, 32, 70, ++ 64, 242, 50, 65, 19, 64, 189, 232, 112, 64, 254, 247, 45, 184, 112, ++ 181, 12, 28, 24, 191, 1, 36, 227, 1, 128, 34, 79, 244, 150, 97, 5, 70, ++ 254, 247, 34, 248, 40, 70, 64, 242, 58, 65, 64, 34, 163, 1, 189, 232, ++ 112, 64, 254, 247, 25, 184, 11, 2, 79, 244, 127, 66, 64, 242, 251, 65, ++ 19, 64, 254, 247, 17, 184, 203, 67, 3, 240, 7, 3, 91, 0, 112, 181, 64, ++ 246, 117, 17, 21, 70, 67, 240, 1, 3, 79, 34, 4, 70, 254, 247, 3, 248, ++ 235, 2, 32, 70, 64, 246, 105, 17, 79, 244, 96, 82, 3, 244, 120, 67, ++ 189, 232, 112, 64, 253, 247, 247, 191, 1, 34, 16, 181, 19, 70, 4, 70, ++ 64, 246, 172, 17, 253, 247, 239, 255, 32, 70, 192, 35, 64, 246, 172, ++ 17, 79, 244, 112, 114, 253, 247, 231, 255, 32, 70, 0, 35, 64, 242, 164, ++ 65, 79, 244, 128, 82, 253, 247, 223, 255, 79, 244, 0, 82, 32, 70, 19, ++ 70, 64, 242, 116, 81, 253, 247, 215, 255, 79, 244, 0, 114, 32, 70, 19, ++ 70, 64, 242, 117, 81, 253, 247, 207, 255, 32, 70, 1, 34, 0, 35, 64, ++ 246, 7, 1, 253, 247, 200, 255, 79, 244, 128, 66, 32, 70, 19, 70, 64, ++ 242, 76, 65, 253, 247, 192, 255, 79, 244, 128, 66, 32, 70, 19, 70, 64, ++ 242, 77, 65, 253, 247, 184, 255, 79, 244, 128, 98, 32, 70, 19, 70, 64, ++ 246, 56, 17, 253, 247, 176, 255, 79, 244, 128, 98, 32, 70, 19, 70, 64, ++ 246, 57, 17, 253, 247, 168, 255, 79, 244, 128, 98, 32, 70, 19, 70, 64, ++ 242, 117, 81, 253, 247, 160, 255, 79, 244, 128, 66, 32, 70, 19, 70, ++ 64, 242, 116, 81, 253, 247, 152, 255, 79, 244, 0, 98, 32, 70, 19, 70, ++ 64, 246, 56, 17, 253, 247, 144, 255, 79, 244, 0, 98, 32, 70, 64, 246, ++ 57, 17, 19, 70, 189, 232, 16, 64, 253, 247, 134, 191, 45, 233, 240, ++ 71, 23, 70, 30, 70, 79, 244, 0, 66, 203, 3, 19, 64, 64, 242, 177, 65, ++ 4, 70, 189, 248, 32, 80, 189, 248, 36, 128, 189, 248, 40, 144, 189, ++ 248, 44, 160, 253, 247, 113, 255, 59, 2, 32, 70, 64, 242, 250, 65, 79, ++ 244, 112, 98, 3, 244, 127, 67, 253, 247, 103, 255, 243, 2, 32, 70, 64, ++ 242, 177, 65, 79, 244, 96, 82, 3, 244, 120, 67, 253, 247, 93, 255, 32, ++ 70, 15, 34, 43, 70, 64, 242, 60, 81, 253, 247, 86, 255, 79, 234, 72, ++ 35, 32, 70, 64, 242, 60, 81, 79, 244, 240, 82, 3, 244, 126, 67, 253, ++ 247, 75, 255, 79, 234, 137, 25, 79, 246, 192, 115, 32, 70, 9, 234, 3, ++ 3, 64, 246, 172, 17, 79, 244, 112, 114, 253, 247, 62, 255, 79, 234, ++ 74, 10, 79, 246, 254, 115, 32, 70, 64, 246, 121, 17, 79, 244, 255, 114, ++ 10, 234, 3, 3, 189, 232, 240, 71, 253, 247, 47, 191, 112, 181, 12, 28, ++ 24, 191, 1, 36, 5, 70, 35, 3, 79, 244, 150, 97, 79, 244, 128, 82, 253, ++ 247, 35, 255, 40, 70, 128, 34, 227, 1, 64, 242, 249, 65, 253, 247, 28, ++ 255, 40, 70, 163, 2, 79, 244, 150, 97, 79, 244, 128, 98, 253, 247, 20, ++ 255, 40, 70, 1, 34, 35, 70, 64, 242, 61, 81, 253, 247, 13, 255, 40, ++ 70, 8, 34, 227, 0, 64, 242, 61, 81, 253, 247, 6, 255, 40, 70, 1, 34, ++ 35, 70, 64, 246, 172, 17, 253, 247, 255, 254, 40, 70, 64, 246, 121, ++ 17, 1, 34, 35, 70, 189, 232, 112, 64, 253, 247, 246, 190, 45, 233, 240, ++ 71, 142, 70, 157, 248, 40, 112, 4, 70, 22, 70, 29, 70, 7, 34, 115, 70, ++ 64, 246, 207, 17, 157, 248, 32, 128, 157, 248, 36, 144, 253, 247, 228, ++ 254, 32, 70, 8, 34, 251, 0, 64, 246, 207, 17, 253, 247, 221, 254, 243, ++ 2, 32, 70, 64, 246, 211, 17, 79, 244, 0, 98, 3, 244, 120, 67, 253, 247, ++ 211, 254, 43, 3, 32, 70, 64, 246, 211, 17, 79, 244, 128, 82, 3, 244, ++ 112, 67, 253, 247, 201, 254, 32, 70, 24, 34, 79, 234, 200, 3, 64, 246, ++ 211, 17, 253, 247, 193, 254, 32, 70, 64, 246, 211, 17, 96, 34, 79, 234, ++ 73, 19, 189, 232, 240, 71, 253, 247, 183, 190, 79, 244, 0, 66, 16, 181, ++ 19, 70, 79, 244, 137, 97, 4, 70, 253, 247, 174, 254, 32, 70, 79, 244, ++ 129, 97, 79, 244, 128, 114, 0, 35, 189, 232, 16, 64, 253, 247, 164, ++ 190, 112, 181, 208, 248, 228, 48, 66, 34, 211, 248, 32, 54, 1, 57, 2, ++ 251, 1, 49, 77, 136, 5, 35, 170, 0, 146, 251, 243, 243, 1, 51, 91, 16, ++ 64, 242, 87, 97, 64, 246, 255, 114, 155, 178, 4, 70, 253, 247, 140, ++ 254, 79, 244, 160, 3, 147, 251, 245, 243, 1, 51, 91, 16, 32, 70, 79, ++ 244, 203, 97, 64, 246, 255, 114, 155, 178, 189, 232, 112, 64, 253, 247, ++ 124, 190, 112, 181, 11, 2, 20, 70, 79, 244, 127, 66, 19, 64, 64, 246, ++ 87, 33, 5, 70, 253, 247, 113, 254, 40, 70, 64, 246, 87, 33, 255, 34, ++ 163, 178, 189, 232, 112, 64, 253, 247, 104, 190, 248, 181, 64, 242, ++ 118, 65, 7, 70, 253, 247, 221, 250, 64, 242, 119, 65, 198, 5, 56, 70, ++ 253, 247, 215, 250, 64, 242, 121, 65, 197, 5, 56, 70, 253, 247, 209, ++ 250, 64, 242, 122, 65, 196, 5, 56, 70, 253, 247, 203, 250, 246, 13, ++ 192, 5, 237, 13, 228, 13, 192, 13, 255, 46, 136, 191, 166, 245, 0, 118, ++ 255, 45, 136, 191, 165, 245, 0, 117, 255, 44, 136, 191, 164, 245, 0, ++ 116, 255, 40, 136, 191, 160, 245, 0, 112, 54, 178, 36, 178, 45, 178, ++ 0, 178, 173, 27, 0, 27, 40, 24, 64, 8, 0, 178, 248, 189, 112, 181, 12, ++ 70, 64, 242, 57, 65, 6, 70, 253, 247, 165, 250, 0, 244, 240, 96, 192, ++ 17, 224, 128, 64, 242, 181, 65, 48, 70, 253, 247, 156, 250, 64, 242, ++ 251, 65, 5, 70, 48, 70, 253, 247, 150, 250, 5, 240, 31, 3, 192, 178, ++ 45, 10, 35, 128, 101, 128, 160, 128, 112, 189, 8, 181, 64, 242, 251, ++ 65, 253, 247, 137, 250, 0, 10, 128, 178, 8, 189, 112, 181, 13, 70, 64, ++ 242, 57, 65, 4, 70, 253, 247, 127, 250, 32, 244, 240, 99, 67, 234, 197, ++ 19, 32, 70, 64, 242, 57, 65, 64, 246, 255, 114, 155, 178, 189, 232, ++ 112, 64, 253, 247, 246, 189, 112, 181, 13, 70, 4, 70, 255, 247, 222, ++ 255, 106, 136, 43, 136, 6, 70, 67, 234, 2, 35, 32, 70, 64, 242, 181, ++ 65, 79, 246, 255, 114, 155, 178, 253, 247, 228, 253, 171, 136, 32, 70, ++ 67, 234, 6, 38, 79, 246, 255, 114, 179, 178, 64, 242, 251, 65, 253, ++ 247, 217, 253, 32, 70, 233, 136, 255, 247, 202, 255, 32, 70, 1, 33, ++ 189, 232, 112, 64, 255, 247, 162, 189, 0, 0, 1, 73, 14, 34, 253, 247, ++ 220, 189, 0, 69, 4, 0, 3, 41, 248, 181, 4, 70, 23, 70, 4, 216, 25, 75, ++ 94, 92, 25, 75, 93, 92, 1, 224, 0, 37, 46, 70, 79, 244, 0, 114, 19, ++ 70, 32, 70, 64, 246, 56, 17, 253, 247, 180, 253, 115, 2, 32, 70, 64, ++ 246, 57, 17, 79, 244, 0, 114, 3, 244, 126, 67, 253, 247, 170, 253, 79, ++ 244, 128, 98, 19, 70, 32, 70, 64, 246, 56, 17, 253, 247, 162, 253, 171, ++ 2, 32, 70, 64, 246, 57, 17, 79, 244, 128, 98, 3, 244, 124, 67, 253, ++ 247, 152, 253, 39, 177, 32, 70, 189, 232, 248, 64, 255, 247, 196, 191, ++ 248, 189, 0, 191, 74, 71, 4, 0, 138, 72, 4, 0, 112, 181, 4, 70, 22, ++ 70, 13, 70, 0, 41, 61, 209, 64, 246, 56, 17, 79, 244, 0, 98, 43, 70, ++ 253, 247, 127, 253, 32, 70, 64, 242, 76, 65, 79, 244, 128, 66, 43, 70, ++ 253, 247, 119, 253, 32, 70, 64, 246, 56, 17, 79, 244, 128, 98, 43, 70, ++ 253, 247, 111, 253, 32, 70, 64, 242, 117, 81, 79, 244, 128, 98, 43, ++ 70, 253, 247, 103, 253, 32, 70, 64, 242, 76, 65, 79, 244, 0, 82, 43, ++ 70, 253, 247, 95, 253, 32, 70, 79, 244, 150, 97, 79, 244, 0, 98, 43, ++ 70, 253, 247, 87, 253, 32, 70, 64, 246, 56, 17, 79, 244, 0, 114, 43, ++ 70, 253, 247, 79, 253, 32, 70, 64, 246, 56, 17, 79, 244, 128, 98, 43, ++ 70, 108, 224, 79, 244, 0, 82, 64, 242, 76, 65, 19, 70, 253, 247, 65, ++ 253, 32, 70, 64, 242, 77, 65, 79, 244, 0, 82, 14, 185, 51, 70, 0, 224, ++ 19, 70, 253, 247, 54, 253, 79, 244, 0, 98, 19, 70, 32, 70, 79, 244, ++ 150, 97, 253, 247, 46, 253, 0, 35, 32, 70, 64, 242, 177, 65, 79, 244, ++ 128, 66, 253, 247, 38, 253, 0, 33, 10, 70, 32, 70, 255, 247, 89, 255, ++ 79, 244, 128, 66, 19, 70, 32, 70, 64, 242, 77, 65, 253, 247, 25, 253, ++ 79, 244, 128, 66, 19, 70, 32, 70, 64, 242, 76, 65, 253, 247, 17, 253, ++ 79, 244, 128, 98, 19, 70, 32, 70, 64, 246, 56, 17, 253, 247, 9, 253, ++ 79, 244, 128, 98, 19, 70, 32, 70, 64, 246, 57, 17, 253, 247, 1, 253, ++ 32, 70, 64, 242, 116, 81, 79, 244, 128, 66, 0, 35, 253, 247, 249, 252, ++ 79, 244, 128, 98, 19, 70, 32, 70, 64, 242, 117, 81, 253, 247, 241, 252, ++ 79, 244, 128, 66, 19, 70, 32, 70, 64, 242, 116, 81, 253, 247, 233, 252, ++ 79, 244, 0, 98, 19, 70, 32, 70, 64, 246, 57, 17, 253, 247, 225, 252, ++ 79, 244, 0, 98, 32, 70, 64, 246, 56, 17, 19, 70, 189, 232, 112, 64, ++ 253, 247, 215, 188, 112, 181, 4, 70, 13, 70, 0, 41, 47, 209, 1, 34, ++ 43, 70, 64, 242, 117, 81, 253, 247, 204, 252, 32, 70, 43, 70, 64, 242, ++ 76, 65, 79, 244, 0, 82, 253, 247, 196, 252, 32, 70, 43, 70, 79, 244, ++ 150, 97, 79, 244, 0, 98, 253, 247, 188, 252, 32, 70, 43, 70, 64, 246, ++ 56, 17, 79, 244, 0, 114, 253, 247, 180, 252, 32, 70, 43, 70, 64, 246, ++ 56, 17, 79, 244, 128, 98, 253, 247, 172, 252, 32, 70, 64, 246, 56, 17, ++ 79, 244, 0, 98, 43, 70, 189, 232, 112, 64, 253, 247, 162, 188, 0, 35, ++ 64, 246, 57, 17, 79, 244, 0, 98, 253, 247, 155, 252, 79, 244, 0, 98, ++ 32, 70, 19, 70, 64, 246, 56, 17, 253, 247, 147, 252, 31, 34, 32, 70, ++ 19, 70, 64, 242, 116, 81, 253, 247, 140, 252, 1, 34, 32, 70, 19, 70, ++ 64, 242, 117, 81, 253, 247, 133, 252, 79, 244, 0, 82, 32, 70, 19, 70, ++ 64, 242, 77, 65, 253, 247, 125, 252, 79, 244, 0, 82, 32, 70, 19, 70, ++ 64, 242, 76, 65, 253, 247, 117, 252, 79, 244, 128, 66, 32, 70, 19, 70, ++ 64, 242, 177, 65, 253, 247, 109, 252, 79, 244, 0, 98, 32, 70, 19, 70, ++ 79, 244, 150, 97, 253, 247, 101, 252, 32, 70, 1, 33, 0, 34, 189, 232, ++ 112, 64, 255, 247, 150, 190, 1, 41, 112, 181, 5, 70, 12, 70, 2, 209, ++ 17, 73, 6, 34, 3, 224, 3, 41, 4, 209, 15, 73, 15, 34, 253, 247, 98, ++ 252, 13, 224, 97, 185, 4, 34, 19, 70, 64, 242, 217, 65, 253, 247, 72, ++ 252, 40, 70, 64, 242, 217, 65, 8, 34, 35, 70, 253, 247, 65, 252, 40, ++ 70, 64, 242, 55, 97, 79, 244, 64, 66, 0, 35, 189, 232, 112, 64, 253, ++ 247, 55, 188, 0, 191, 4, 71, 4, 0, 142, 71, 4, 0, 112, 181, 208, 248, ++ 228, 48, 4, 70, 147, 248, 188, 100, 147, 248, 189, 84, 9, 34, 69, 234, ++ 6, 53, 173, 178, 23, 73, 253, 247, 53, 252, 32, 70, 43, 70, 64, 242, ++ 219, 65, 71, 242, 255, 50, 253, 247, 27, 252, 32, 70, 43, 70, 64, 242, ++ 220, 65, 71, 242, 255, 50, 253, 247, 19, 252, 32, 70, 43, 70, 64, 242, ++ 10, 65, 71, 242, 255, 50, 253, 247, 11, 252, 32, 70, 64, 242, 11, 65, ++ 71, 242, 255, 50, 67, 242, 164, 3, 253, 247, 2, 252, 32, 70, 64, 242, ++ 12, 65, 71, 242, 255, 50, 67, 242, 164, 3, 189, 232, 112, 64, 253, 247, ++ 247, 187, 0, 191, 254, 72, 4, 0, 1, 73, 12, 34, 253, 247, 2, 188, 236, ++ 70, 4, 0, 112, 181, 21, 70, 4, 34, 19, 70, 14, 70, 64, 246, 101, 17, ++ 4, 70, 253, 247, 228, 251, 8, 34, 19, 70, 32, 70, 64, 246, 101, 17, ++ 253, 247, 221, 251, 32, 70, 49, 70, 0, 34, 255, 247, 199, 251, 4, 34, ++ 32, 70, 79, 244, 136, 97, 19, 70, 253, 247, 209, 251, 1, 34, 19, 70, ++ 32, 70, 64, 242, 74, 65, 253, 247, 202, 251, 32, 70, 64, 242, 74, 65, ++ 1, 34, 0, 35, 253, 247, 195, 251, 32, 32, 215, 243, 234, 247, 181, 177, ++ 32, 70, 64, 246, 120, 17, 253, 247, 53, 248, 192, 178, 255, 40, 10, ++ 209, 32, 70, 64, 246, 111, 17, 253, 247, 45, 248, 0, 5, 0, 13, 64, 246, ++ 255, 115, 152, 66, 3, 208, 1, 61, 109, 178, 0, 45, 214, 209, 0, 33, ++ 32, 70, 10, 70, 255, 247, 146, 251, 32, 70, 79, 244, 136, 97, 4, 34, ++ 0, 35, 189, 232, 112, 64, 253, 247, 154, 187, 248, 181, 23, 70, 4, 70, ++ 30, 70, 79, 246, 255, 114, 59, 70, 13, 70, 64, 242, 131, 65, 253, 247, ++ 142, 251, 51, 70, 32, 70, 64, 242, 130, 65, 255, 34, 253, 247, 135, ++ 251, 157, 248, 24, 48, 32, 70, 64, 242, 129, 65, 2, 34, 91, 0, 253, ++ 247, 126, 251, 1, 34, 32, 70, 64, 242, 129, 65, 19, 70, 253, 247, 119, ++ 251, 66, 242, 17, 118, 2, 224, 10, 32, 215, 243, 155, 247, 32, 70, 64, ++ 242, 129, 65, 252, 247, 231, 255, 194, 7, 1, 213, 1, 62, 243, 209, 32, ++ 70, 64, 242, 129, 65, 252, 247, 222, 255, 195, 7, 41, 212, 64, 242, ++ 135, 65, 32, 70, 252, 247, 215, 255, 64, 242, 134, 65, 6, 70, 32, 70, ++ 252, 247, 209, 255, 64, 234, 6, 64, 104, 96, 64, 246, 154, 33, 32, 70, ++ 252, 247, 201, 255, 79, 244, 145, 97, 6, 70, 32, 70, 252, 247, 195, ++ 255, 64, 234, 6, 64, 168, 96, 64, 242, 133, 65, 32, 70, 252, 247, 187, ++ 255, 64, 242, 132, 65, 6, 70, 32, 70, 252, 247, 181, 255, 64, 234, 6, ++ 64, 40, 96, 248, 189, 112, 181, 29, 70, 4, 70, 22, 70, 11, 70, 25, 185, ++ 79, 244, 150, 97, 7, 34, 10, 224, 1, 34, 19, 70, 64, 242, 177, 65, 253, ++ 247, 38, 251, 7, 34, 32, 70, 79, 244, 150, 97, 19, 70, 253, 247, 31, ++ 251, 134, 177, 234, 5, 32, 70, 210, 13, 64, 242, 188, 65, 252, 247, ++ 157, 255, 106, 10, 210, 5, 32, 70, 64, 242, 187, 65, 210, 13, 189, 232, ++ 112, 64, 252, 247, 147, 191, 112, 189, 1, 41, 56, 181, 5, 70, 20, 70, ++ 15, 208, 2, 211, 2, 41, 35, 209, 21, 224, 64, 246, 222, 17, 252, 247, ++ 122, 255, 64, 246, 223, 17, 32, 128, 40, 70, 252, 247, 116, 255, 96, ++ 128, 56, 189, 64, 246, 222, 17, 18, 136, 252, 247, 120, 255, 40, 70, ++ 64, 246, 223, 17, 98, 136, 8, 224, 64, 246, 222, 17, 0, 34, 252, 247, ++ 110, 255, 40, 70, 64, 246, 223, 17, 0, 34, 189, 232, 56, 64, 252, 247, ++ 102, 191, 56, 189, 1, 41, 56, 181, 5, 70, 20, 70, 32, 209, 64, 246, ++ 216, 17, 18, 120, 252, 247, 91, 255, 40, 70, 64, 246, 217, 17, 98, 120, ++ 252, 247, 85, 255, 40, 70, 64, 246, 218, 17, 162, 120, 252, 247, 79, ++ 255, 40, 70, 64, 246, 186, 33, 226, 120, 252, 247, 73, 255, 40, 70, ++ 64, 246, 187, 33, 34, 121, 252, 247, 67, 255, 40, 70, 64, 246, 188, ++ 33, 33, 224, 2, 41, 36, 209, 64, 246, 219, 17, 18, 120, 252, 247, 56, ++ 255, 40, 70, 64, 246, 220, 17, 98, 120, 252, 247, 50, 255, 40, 70, 64, ++ 246, 221, 17, 162, 120, 252, 247, 44, 255, 40, 70, 64, 246, 189, 33, ++ 226, 120, 252, 247, 38, 255, 40, 70, 64, 246, 190, 33, 34, 121, 252, ++ 247, 32, 255, 40, 70, 64, 246, 245, 33, 98, 121, 189, 232, 56, 64, 252, ++ 247, 24, 191, 56, 189, 0, 0, 45, 233, 240, 65, 208, 248, 228, 48, 4, ++ 70, 147, 249, 112, 53, 0, 43, 51, 221, 27, 74, 79, 244, 19, 97, 7, 43, ++ 212, 191, 211, 24, 211, 29, 19, 248, 1, 92, 252, 247, 247, 254, 64, ++ 246, 49, 17, 128, 70, 32, 70, 252, 247, 241, 254, 64, 246, 50, 17, 7, ++ 70, 32, 70, 252, 247, 235, 254, 5, 251, 8, 248, 111, 67, 79, 234, 168, ++ 18, 6, 70, 79, 244, 19, 97, 32, 70, 146, 178, 252, 247, 234, 254, 186, ++ 17, 32, 70, 64, 246, 49, 17, 146, 178, 252, 247, 227, 254, 117, 67, ++ 170, 17, 32, 70, 64, 246, 50, 17, 146, 178, 189, 232, 240, 65, 252, ++ 247, 217, 190, 189, 232, 240, 129, 0, 191, 92, 101, 4, 0, 45, 233, 240, ++ 67, 44, 75, 147, 176, 6, 70, 15, 70, 108, 70, 3, 241, 32, 14, 24, 104, ++ 89, 104, 37, 70, 3, 197, 8, 51, 115, 69, 44, 70, 247, 209, 27, 136, ++ 9, 172, 43, 128, 36, 75, 3, 241, 32, 14, 24, 104, 89, 104, 37, 70, 3, ++ 197, 8, 51, 115, 69, 44, 70, 247, 209, 27, 136, 43, 128, 79, 177, 1, ++ 47, 3, 209, 9, 172, 18, 32, 28, 73, 6, 224, 0, 36, 32, 70, 33, 70, 2, ++ 224, 26, 73, 108, 70, 17, 32, 0, 35, 6, 224, 13, 70, 181, 248, 0, 224, ++ 1, 51, 36, 49, 114, 69, 6, 208, 131, 66, 31, 250, 131, 248, 244, 219, ++ 79, 246, 255, 120, 14, 224, 169, 70, 0, 37, 97, 91, 48, 70, 57, 248, ++ 2, 47, 2, 53, 252, 247, 140, 254, 34, 45, 246, 209, 23, 185, 48, 70, ++ 255, 247, 112, 255, 48, 70, 15, 250, 136, 248, 255, 247, 7, 254, 184, ++ 241, 255, 63, 12, 191, 79, 240, 255, 48, 0, 32, 19, 176, 189, 232, 240, ++ 131, 228, 21, 4, 0, 6, 22, 4, 0, 100, 101, 4, 0, 2, 106, 4, 0, 45, 233, ++ 240, 65, 208, 248, 228, 112, 1, 37, 14, 70, 135, 248, 216, 85, 161, ++ 33, 4, 70, 252, 247, 50, 254, 103, 33, 167, 248, 218, 5, 32, 70, 252, ++ 247, 44, 254, 153, 33, 167, 248, 220, 5, 32, 70, 252, 247, 38, 254, ++ 9, 33, 167, 248, 222, 5, 32, 70, 252, 247, 32, 254, 150, 33, 167, 248, ++ 224, 5, 32, 70, 252, 247, 26, 254, 2, 33, 167, 248, 226, 5, 32, 70, ++ 252, 247, 20, 254, 3, 33, 167, 248, 228, 5, 32, 70, 252, 247, 14, 254, ++ 156, 33, 167, 248, 230, 5, 32, 70, 252, 247, 8, 254, 39, 33, 167, 248, ++ 232, 5, 32, 70, 252, 247, 2, 254, 111, 33, 167, 248, 234, 5, 32, 70, ++ 252, 247, 252, 253, 157, 33, 167, 248, 236, 5, 32, 70, 252, 247, 246, ++ 253, 49, 33, 167, 248, 238, 5, 32, 70, 252, 247, 240, 253, 50, 33, 167, ++ 248, 240, 5, 32, 70, 252, 247, 234, 253, 155, 33, 167, 248, 242, 5, ++ 32, 70, 252, 247, 228, 253, 166, 33, 167, 248, 244, 5, 32, 70, 252, ++ 247, 222, 253, 47, 33, 167, 248, 246, 5, 32, 70, 252, 247, 216, 253, ++ 48, 33, 167, 248, 248, 5, 32, 70, 252, 247, 210, 253, 43, 33, 167, 248, ++ 250, 5, 32, 70, 252, 247, 204, 253, 25, 33, 167, 248, 252, 5, 32, 70, ++ 252, 247, 198, 253, 136, 33, 167, 248, 254, 5, 32, 70, 252, 247, 192, ++ 253, 153, 33, 167, 248, 0, 6, 42, 70, 32, 70, 43, 70, 253, 247, 41, ++ 249, 9, 33, 32, 70, 42, 70, 43, 70, 253, 247, 35, 249, 9, 33, 2, 34, ++ 0, 35, 32, 70, 253, 247, 29, 249, 174, 66, 34, 209, 32, 70, 161, 33, ++ 50, 70, 51, 70, 253, 247, 21, 249, 32, 70, 103, 33, 50, 70, 51, 70, ++ 253, 247, 15, 249, 32, 70, 166, 33, 50, 70, 51, 70, 253, 247, 9, 249, ++ 32, 70, 136, 33, 50, 70, 0, 35, 253, 247, 3, 249, 2, 34, 19, 70, 32, ++ 70, 153, 33, 253, 247, 253, 248, 32, 70, 9, 33, 112, 34, 16, 35, 35, ++ 224, 2, 46, 35, 209, 32, 70, 166, 33, 42, 70, 43, 70, 253, 247, 240, ++ 248, 32, 70, 136, 33, 42, 70, 43, 70, 253, 247, 234, 248, 32, 70, 161, ++ 33, 42, 70, 43, 70, 253, 247, 228, 248, 32, 70, 103, 33, 42, 70, 0, ++ 35, 253, 247, 222, 248, 32, 70, 153, 33, 50, 70, 51, 70, 253, 247, 216, ++ 248, 32, 70, 9, 33, 112, 34, 48, 35, 253, 247, 210, 248, 2, 34, 32, ++ 70, 150, 33, 19, 70, 253, 247, 204, 248, 1, 34, 32, 70, 2, 33, 19, 70, ++ 253, 247, 198, 248, 8, 34, 32, 70, 150, 33, 19, 70, 253, 247, 192, 248, ++ 32, 70, 2, 33, 79, 244, 224, 98, 79, 244, 64, 115, 253, 247, 184, 248, ++ 1, 34, 32, 70, 150, 33, 19, 70, 253, 247, 178, 248, 32, 70, 3, 33, 164, ++ 35, 64, 242, 255, 50, 253, 247, 171, 248, 4, 34, 32, 70, 150, 33, 19, ++ 70, 253, 247, 165, 248, 2, 33, 32, 70, 14, 34, 11, 70, 253, 247, 159, ++ 248, 32, 70, 2, 33, 48, 34, 0, 35, 253, 247, 153, 248, 32, 70, 111, ++ 33, 0, 35, 79, 244, 0, 82, 253, 247, 146, 248, 32, 70, 0, 35, 47, 33, ++ 79, 244, 112, 82, 253, 247, 139, 248, 156, 33, 2, 34, 32, 70, 19, 70, ++ 253, 247, 133, 248, 79, 244, 112, 98, 32, 70, 39, 33, 19, 70, 253, 247, ++ 126, 248, 64, 34, 32, 70, 157, 33, 19, 70, 253, 247, 120, 248, 32, 70, ++ 45, 33, 0, 35, 79, 244, 0, 114, 253, 247, 113, 248, 128, 34, 32, 70, ++ 157, 33, 19, 70, 253, 247, 107, 248, 32, 70, 45, 33, 0, 35, 79, 244, ++ 128, 98, 253, 247, 100, 248, 79, 244, 128, 82, 32, 70, 157, 33, 19, ++ 70, 253, 247, 93, 248, 32, 70, 43, 33, 1, 34, 0, 35, 253, 247, 87, 248, ++ 2, 34, 32, 70, 155, 33, 19, 70, 253, 247, 81, 248, 1, 34, 32, 70, 25, ++ 33, 19, 70, 253, 247, 75, 248, 4, 34, 32, 70, 156, 33, 19, 70, 253, ++ 247, 69, 248, 79, 244, 128, 82, 32, 70, 19, 70, 38, 33, 253, 247, 62, ++ 248, 8, 34, 32, 70, 156, 33, 19, 70, 253, 247, 56, 248, 1, 34, 32, 70, ++ 31, 33, 19, 70, 253, 247, 50, 248, 32, 34, 32, 70, 156, 33, 19, 70, ++ 253, 247, 44, 248, 8, 34, 32, 70, 31, 33, 19, 70, 189, 232, 240, 65, ++ 253, 247, 36, 184, 112, 181, 208, 248, 228, 96, 1, 37, 104, 33, 134, ++ 248, 144, 85, 4, 70, 252, 247, 169, 252, 162, 33, 166, 248, 146, 5, ++ 32, 70, 252, 247, 163, 252, 2, 33, 166, 248, 148, 5, 32, 70, 252, 247, ++ 157, 252, 106, 33, 166, 248, 150, 5, 32, 70, 252, 247, 151, 252, 39, ++ 33, 166, 248, 152, 5, 32, 70, 252, 247, 145, 252, 150, 33, 166, 248, ++ 154, 5, 32, 70, 252, 247, 139, 252, 153, 33, 166, 248, 156, 5, 32, 70, ++ 252, 247, 133, 252, 121, 33, 166, 248, 158, 5, 32, 70, 252, 247, 127, ++ 252, 156, 33, 166, 248, 160, 5, 32, 70, 252, 247, 121, 252, 159, 33, ++ 166, 248, 162, 5, 32, 70, 252, 247, 115, 252, 165, 33, 166, 248, 164, ++ 5, 32, 70, 252, 247, 109, 252, 157, 33, 166, 248, 166, 5, 32, 70, 252, ++ 247, 103, 252, 158, 33, 166, 248, 168, 5, 32, 70, 252, 247, 97, 252, ++ 155, 33, 166, 248, 170, 5, 32, 70, 252, 247, 91, 252, 240, 34, 166, ++ 248, 172, 5, 128, 35, 32, 70, 104, 33, 252, 247, 196, 255, 121, 33, ++ 32, 70, 32, 34, 0, 35, 252, 247, 190, 255, 32, 70, 104, 33, 0, 35, 79, ++ 244, 64, 114, 252, 247, 183, 255, 2, 34, 32, 70, 162, 33, 19, 70, 252, ++ 247, 177, 255, 2, 34, 32, 70, 104, 33, 19, 70, 252, 247, 171, 255, 32, ++ 70, 162, 33, 42, 70, 43, 70, 252, 247, 165, 255, 32, 70, 104, 33, 42, ++ 70, 0, 35, 252, 247, 159, 255, 64, 34, 32, 70, 165, 33, 19, 70, 252, ++ 247, 153, 255, 16, 34, 32, 70, 129, 33, 19, 70, 252, 247, 147, 255, ++ 32, 34, 32, 70, 165, 33, 19, 70, 252, 247, 141, 255, 32, 70, 129, 33, ++ 8, 34, 0, 35, 252, 247, 135, 255, 32, 70, 129, 33, 79, 244, 240, 114, ++ 96, 35, 252, 247, 128, 255, 32, 70, 153, 33, 42, 70, 43, 70, 252, 247, ++ 122, 255, 32, 70, 9, 33, 42, 70, 43, 70, 252, 247, 116, 255, 2, 34, ++ 32, 70, 153, 33, 19, 70, 252, 247, 110, 255, 32, 70, 9, 33, 112, 34, ++ 0, 35, 252, 247, 104, 255, 2, 34, 32, 70, 150, 33, 19, 70, 252, 247, ++ 98, 255, 32, 70, 2, 33, 42, 70, 43, 70, 252, 247, 92, 255, 4, 34, 32, ++ 70, 150, 33, 19, 70, 252, 247, 86, 255, 32, 70, 2, 33, 14, 34, 0, 35, ++ 252, 247, 80, 255, 8, 34, 32, 70, 150, 33, 19, 70, 252, 247, 74, 255, ++ 150, 248, 190, 52, 32, 70, 2, 33, 27, 2, 79, 244, 224, 98, 252, 247, ++ 65, 255, 32, 70, 150, 33, 42, 70, 43, 70, 252, 247, 59, 255, 32, 70, ++ 150, 248, 191, 52, 3, 33, 64, 242, 255, 50, 252, 247, 51, 255, 2, 34, ++ 32, 70, 156, 33, 19, 70, 252, 247, 45, 255, 79, 244, 112, 98, 32, 70, ++ 39, 33, 19, 70, 252, 247, 38, 255, 32, 70, 47, 33, 0, 35, 79, 244, 112, ++ 82, 252, 247, 31, 255, 32, 70, 111, 33, 0, 35, 79, 244, 0, 82, 252, ++ 247, 24, 255, 8, 34, 32, 70, 156, 33, 19, 70, 252, 247, 18, 255, 32, ++ 70, 31, 33, 42, 70, 43, 70, 252, 247, 12, 255, 32, 34, 32, 70, 156, ++ 33, 19, 70, 252, 247, 6, 255, 8, 34, 32, 70, 31, 33, 19, 70, 252, 247, ++ 0, 255, 128, 34, 32, 70, 159, 33, 19, 70, 252, 247, 250, 254, 32, 70, ++ 56, 33, 42, 70, 0, 35, 252, 247, 244, 254, 16, 34, 32, 70, 159, 33, ++ 19, 70, 252, 247, 238, 254, 32, 70, 61, 33, 79, 244, 0, 82, 0, 35, 252, ++ 247, 231, 254, 32, 70, 61, 33, 0, 35, 79, 244, 128, 82, 252, 247, 224, ++ 254, 79, 244, 128, 114, 32, 70, 157, 33, 19, 70, 252, 247, 217, 254, ++ 32, 70, 45, 33, 0, 35, 79, 244, 0, 98, 252, 247, 210, 254, 64, 34, 32, ++ 70, 157, 33, 19, 70, 252, 247, 204, 254, 32, 70, 45, 33, 0, 35, 79, ++ 244, 0, 114, 252, 247, 197, 254, 128, 34, 32, 70, 157, 33, 19, 70, 252, ++ 247, 191, 254, 32, 70, 45, 33, 0, 35, 79, 244, 128, 98, 252, 247, 184, ++ 254, 79, 244, 128, 82, 32, 70, 157, 33, 19, 70, 252, 247, 177, 254, ++ 32, 70, 43, 33, 42, 70, 0, 35, 252, 247, 171, 254, 64, 34, 32, 70, 159, ++ 33, 19, 70, 252, 247, 165, 254, 32, 70, 58, 33, 32, 34, 0, 35, 252, ++ 247, 159, 254, 32, 70, 158, 33, 42, 70, 43, 70, 252, 247, 153, 254, ++ 32, 70, 53, 33, 42, 70, 0, 35, 189, 232, 112, 64, 252, 247, 145, 190, ++ 112, 181, 0, 35, 4, 70, 13, 70, 79, 244, 0, 98, 157, 33, 252, 247, 136, ++ 254, 32, 70, 157, 33, 16, 34, 0, 35, 252, 247, 130, 254, 32, 70, 157, ++ 33, 8, 34, 0, 35, 252, 247, 124, 254, 32, 70, 157, 33, 4, 34, 0, 35, ++ 252, 247, 118, 254, 32, 70, 157, 33, 2, 34, 0, 35, 252, 247, 112, 254, ++ 32, 70, 157, 33, 1, 34, 0, 35, 252, 247, 106, 254, 32, 70, 157, 33, ++ 0, 35, 79, 244, 128, 66, 252, 247, 99, 254, 32, 70, 157, 33, 0, 35, ++ 79, 244, 0, 114, 252, 247, 92, 254, 32, 70, 128, 34, 0, 35, 157, 33, ++ 252, 247, 86, 254, 157, 33, 32, 70, 0, 35, 79, 244, 128, 82, 252, 247, ++ 79, 254, 32, 70, 157, 33, 0, 35, 79, 244, 0, 82, 252, 247, 72, 254, ++ 8, 34, 32, 70, 19, 70, 64, 242, 61, 81, 252, 247, 124, 254, 107, 2, ++ 32, 70, 64, 242, 60, 81, 79, 244, 240, 82, 3, 244, 126, 67, 189, 232, ++ 112, 64, 252, 247, 112, 190, 112, 181, 208, 248, 228, 96, 1, 37, 156, ++ 33, 134, 248, 254, 84, 4, 70, 252, 247, 186, 250, 164, 33, 166, 248, ++ 0, 5, 32, 70, 252, 247, 180, 250, 165, 33, 166, 248, 2, 5, 32, 70, 252, ++ 247, 174, 250, 159, 33, 166, 248, 4, 5, 32, 70, 252, 247, 168, 250, ++ 157, 33, 166, 248, 6, 5, 32, 70, 252, 247, 162, 250, 155, 33, 166, 248, ++ 8, 5, 32, 70, 252, 247, 156, 250, 2, 34, 166, 248, 10, 5, 156, 33, 32, ++ 70, 19, 70, 252, 247, 5, 254, 32, 70, 39, 33, 0, 35, 79, 244, 112, 98, ++ 252, 247, 254, 253, 32, 70, 50, 33, 0, 35, 79, 244, 0, 98, 252, 247, ++ 247, 253, 32, 70, 50, 33, 0, 35, 79, 244, 128, 98, 252, 247, 240, 253, ++ 32, 70, 164, 33, 42, 70, 43, 70, 252, 247, 234, 253, 79, 244, 128, 114, ++ 32, 70, 126, 33, 19, 70, 252, 247, 227, 253, 2, 34, 32, 70, 164, 33, ++ 19, 70, 252, 247, 221, 253, 79, 244, 128, 66, 32, 70, 19, 70, 126, 33, ++ 252, 247, 214, 253, 79, 244, 0, 114, 32, 70, 159, 33, 19, 70, 252, 247, ++ 207, 253, 32, 70, 56, 33, 4, 34, 0, 35, 252, 247, 201, 253, 79, 244, ++ 128, 98, 32, 70, 165, 33, 19, 70, 252, 247, 194, 253, 64, 34, 32, 70, ++ 128, 33, 19, 70, 252, 247, 188, 253, 79, 244, 0, 114, 32, 70, 165, 33, ++ 19, 70, 252, 247, 181, 253, 32, 34, 32, 70, 128, 33, 19, 70, 252, 247, ++ 175, 253, 32, 70, 129, 33, 42, 70, 43, 70, 252, 247, 169, 253, 4, 34, ++ 32, 70, 62, 33, 19, 70, 252, 247, 163, 253, 6, 34, 32, 70, 129, 33, ++ 19, 70, 252, 247, 157, 253, 3, 34, 32, 70, 62, 33, 19, 70, 252, 247, ++ 151, 253, 128, 34, 32, 70, 159, 33, 19, 70, 252, 247, 145, 253, 32, ++ 70, 42, 70, 56, 33, 0, 35, 252, 247, 139, 253, 79, 244, 128, 114, 32, ++ 70, 159, 33, 19, 70, 252, 247, 132, 253, 2, 34, 32, 70, 56, 33, 19, ++ 70, 252, 247, 126, 253, 16, 34, 32, 70, 159, 33, 19, 70, 252, 247, 120, ++ 253, 32, 70, 61, 33, 0, 35, 79, 244, 0, 82, 252, 247, 113, 253, 79, ++ 244, 128, 82, 32, 70, 61, 33, 19, 70, 252, 247, 106, 253, 32, 34, 32, ++ 70, 159, 33, 19, 70, 252, 247, 100, 253, 79, 244, 128, 66, 32, 70, 61, ++ 33, 19, 70, 252, 247, 93, 253, 4, 34, 32, 70, 159, 33, 19, 70, 252, ++ 247, 87, 253, 32, 34, 32, 70, 62, 33, 19, 70, 252, 247, 81, 253, 79, ++ 244, 128, 114, 32, 70, 157, 33, 19, 70, 252, 247, 74, 253, 79, 244, ++ 0, 98, 32, 70, 45, 33, 19, 70, 252, 247, 67, 253, 64, 34, 32, 70, 157, ++ 33, 19, 70, 252, 247, 61, 253, 79, 244, 0, 114, 32, 70, 19, 70, 45, ++ 33, 252, 247, 54, 253, 128, 34, 32, 70, 157, 33, 19, 70, 252, 247, 48, ++ 253, 79, 244, 128, 98, 19, 70, 32, 70, 45, 33, 252, 247, 41, 253, 32, ++ 70, 3, 33, 255, 247, 148, 254, 2, 34, 32, 70, 155, 33, 19, 70, 252, ++ 247, 31, 253, 32, 70, 25, 33, 42, 70, 43, 70, 252, 247, 25, 253, 4, ++ 34, 32, 70, 156, 33, 19, 70, 252, 247, 19, 253, 79, 244, 128, 82, 32, ++ 70, 38, 33, 19, 70, 252, 247, 12, 253, 8, 34, 32, 70, 156, 33, 19, 70, ++ 252, 247, 6, 253, 32, 70, 31, 33, 42, 70, 43, 70, 252, 247, 0, 253, ++ 32, 34, 32, 70, 156, 33, 19, 70, 252, 247, 250, 252, 8, 34, 32, 70, ++ 31, 33, 19, 70, 189, 232, 112, 64, 252, 247, 242, 188, 1, 34, 16, 181, ++ 12, 33, 4, 70, 19, 70, 252, 247, 235, 252, 32, 70, 29, 33, 32, 34, 0, ++ 35, 252, 247, 229, 252, 32, 70, 10, 33, 0, 35, 79, 246, 255, 114, 252, ++ 247, 222, 252, 32, 70, 11, 33, 0, 35, 79, 246, 255, 114, 252, 247, 215, ++ 252, 32, 70, 10, 33, 0, 35, 79, 246, 255, 114, 252, 247, 208, 252, 32, ++ 70, 11, 33, 0, 35, 79, 246, 255, 114, 252, 247, 201, 252, 32, 70, 104, ++ 33, 240, 34, 0, 35, 252, 247, 195, 252, 32, 70, 121, 33, 32, 34, 0, ++ 35, 252, 247, 189, 252, 32, 70, 104, 33, 4, 34, 0, 35, 189, 232, 16, ++ 64, 252, 247, 181, 188, 45, 233, 240, 71, 4, 70, 208, 248, 228, 0, 176, ++ 248, 174, 85, 176, 248, 176, 197, 0, 32, 73, 78, 134, 87, 150, 66, 4, ++ 208, 1, 48, 15, 40, 248, 209, 189, 232, 240, 135, 0, 235, 1, 16, 69, ++ 74, 64, 26, 50, 248, 16, 112, 68, 74, 111, 67, 50, 248, 17, 96, 67, ++ 74, 110, 67, 50, 248, 16, 128, 66, 74, 5, 251, 8, 248, 50, 248, 16, ++ 144, 64, 74, 32, 70, 50, 248, 19, 160, 63, 75, 16, 34, 5, 251, 9, 249, ++ 51, 248, 17, 80, 163, 33, 19, 70, 12, 251, 10, 250, 252, 247, 127, 252, ++ 8, 34, 32, 70, 163, 33, 19, 70, 252, 247, 121, 252, 4, 34, 32, 70, 163, ++ 33, 19, 70, 252, 247, 115, 252, 1, 34, 32, 70, 163, 33, 19, 70, 252, ++ 247, 109, 252, 2, 34, 32, 70, 163, 33, 19, 70, 252, 247, 103, 252, 255, ++ 19, 79, 244, 0, 82, 32, 70, 163, 33, 19, 70, 191, 178, 246, 19, 252, ++ 247, 93, 252, 182, 178, 32, 70, 114, 33, 59, 70, 65, 246, 255, 114, ++ 79, 234, 232, 56, 252, 247, 83, 252, 31, 250, 136, 248, 32, 70, 118, ++ 33, 51, 70, 65, 246, 255, 114, 79, 234, 233, 57, 252, 247, 72, 252, ++ 31, 250, 137, 249, 32, 70, 115, 33, 67, 70, 65, 246, 255, 114, 79, 234, ++ 234, 58, 252, 247, 61, 252, 31, 250, 138, 250, 32, 70, 116, 33, 75, ++ 70, 65, 246, 255, 114, 252, 247, 52, 252, 32, 70, 117, 33, 83, 70, 64, ++ 242, 255, 18, 252, 247, 45, 252, 32, 70, 43, 70, 119, 33, 255, 34, 252, ++ 247, 39, 252, 32, 70, 113, 33, 0, 35, 79, 244, 128, 82, 252, 247, 32, ++ 252, 32, 70, 114, 33, 79, 244, 0, 82, 0, 35, 189, 232, 240, 71, 252, ++ 247, 23, 188, 220, 69, 4, 0, 88, 67, 4, 0, 12, 68, 4, 0, 24, 68, 4, ++ 0, 40, 69, 4, 0, 236, 69, 4, 0, 28, 69, 4, 0, 112, 181, 8, 34, 4, 70, ++ 13, 70, 0, 35, 156, 33, 252, 247, 1, 252, 32, 70, 156, 33, 4, 34, 0, ++ 35, 252, 247, 251, 251, 32, 70, 31, 33, 224, 34, 128, 35, 252, 247, ++ 245, 251, 32, 70, 38, 33, 0, 35, 79, 244, 0, 98, 252, 247, 238, 251, ++ 32, 70, 36, 33, 255, 34, 16, 35, 252, 247, 232, 251, 32, 70, 36, 33, ++ 79, 244, 127, 66, 79, 244, 0, 99, 252, 247, 224, 251, 32, 70, 37, 33, ++ 255, 34, 8, 35, 252, 247, 218, 251, 32, 70, 37, 33, 79, 244, 127, 66, ++ 79, 244, 0, 99, 252, 247, 210, 251, 32, 70, 38, 33, 79, 244, 64, 114, ++ 79, 244, 128, 115, 252, 247, 202, 251, 32, 70, 255, 34, 64, 35, 38, ++ 33, 252, 247, 196, 251, 32, 33, 32, 70, 127, 34, 43, 136, 252, 247, ++ 190, 251, 32, 70, 33, 33, 127, 34, 107, 136, 252, 247, 184, 251, 171, ++ 136, 32, 70, 27, 2, 33, 33, 79, 244, 254, 66, 3, 244, 127, 67, 252, ++ 247, 174, 251, 32, 70, 34, 33, 127, 34, 235, 136, 252, 247, 168, 251, ++ 32, 70, 40, 33, 127, 34, 171, 137, 252, 247, 162, 251, 235, 137, 32, ++ 70, 27, 2, 40, 33, 79, 244, 254, 66, 3, 244, 127, 67, 252, 247, 152, ++ 251, 32, 70, 41, 33, 127, 34, 43, 138, 252, 247, 146, 251, 107, 138, ++ 79, 244, 127, 66, 27, 2, 32, 70, 41, 33, 19, 64, 252, 247, 137, 251, ++ 43, 137, 32, 70, 27, 2, 35, 33, 79, 244, 254, 66, 3, 244, 127, 67, 252, ++ 247, 127, 251, 32, 70, 35, 33, 127, 34, 107, 137, 252, 247, 121, 251, ++ 171, 138, 32, 70, 27, 2, 34, 33, 79, 244, 254, 66, 3, 244, 127, 67, ++ 252, 247, 111, 251, 42, 33, 32, 70, 79, 244, 248, 82, 79, 244, 0, 115, ++ 252, 247, 103, 251, 32, 70, 42, 33, 79, 244, 192, 66, 79, 244, 0, 83, ++ 252, 247, 95, 251, 16, 34, 32, 70, 156, 33, 19, 70, 252, 247, 89, 251, ++ 4, 34, 32, 70, 31, 33, 19, 70, 252, 247, 83, 251, 32, 70, 31, 33, 4, ++ 34, 0, 35, 252, 247, 77, 251, 32, 70, 156, 33, 16, 34, 0, 35, 189, 232, ++ 112, 64, 252, 247, 69, 187, 16, 181, 208, 248, 228, 48, 134, 176, 4, ++ 70, 179, 248, 180, 21, 106, 70, 254, 247, 88, 250, 32, 70, 105, 70, ++ 255, 247, 46, 255, 6, 176, 16, 189, 56, 181, 208, 248, 228, 64, 0, 35, ++ 5, 70, 132, 248, 216, 53, 161, 33, 180, 248, 218, 37, 251, 247, 201, ++ 255, 40, 70, 103, 33, 180, 248, 220, 37, 251, 247, 195, 255, 40, 70, ++ 153, 33, 180, 248, 222, 37, 251, 247, 189, 255, 40, 70, 9, 33, 180, ++ 248, 224, 37, 251, 247, 183, 255, 40, 70, 150, 33, 180, 248, 226, 37, ++ 251, 247, 177, 255, 40, 70, 2, 33, 180, 248, 228, 37, 251, 247, 171, ++ 255, 40, 70, 3, 33, 180, 248, 230, 37, 251, 247, 165, 255, 40, 70, 156, ++ 33, 180, 248, 232, 37, 251, 247, 159, 255, 40, 70, 39, 33, 180, 248, ++ 234, 37, 251, 247, 153, 255, 40, 70, 111, 33, 180, 248, 236, 37, 251, ++ 247, 147, 255, 40, 70, 157, 33, 180, 248, 238, 37, 251, 247, 141, 255, ++ 40, 70, 49, 33, 180, 248, 240, 37, 251, 247, 135, 255, 40, 70, 50, 33, ++ 180, 248, 242, 37, 251, 247, 129, 255, 40, 70, 155, 33, 180, 248, 244, ++ 37, 251, 247, 123, 255, 40, 70, 166, 33, 180, 248, 246, 37, 251, 247, ++ 117, 255, 40, 70, 180, 248, 248, 37, 47, 33, 251, 247, 111, 255, 48, ++ 33, 40, 70, 180, 248, 250, 37, 251, 247, 105, 255, 40, 70, 43, 33, 180, ++ 248, 252, 37, 251, 247, 99, 255, 40, 70, 25, 33, 180, 248, 254, 37, ++ 251, 247, 93, 255, 180, 248, 0, 38, 40, 70, 136, 33, 189, 232, 56, 64, ++ 251, 247, 85, 191, 56, 181, 208, 248, 228, 64, 0, 35, 5, 70, 132, 248, ++ 144, 53, 104, 33, 180, 248, 146, 37, 251, 247, 73, 255, 40, 70, 162, ++ 33, 180, 248, 148, 37, 251, 247, 67, 255, 40, 70, 2, 33, 180, 248, 150, ++ 37, 251, 247, 61, 255, 40, 70, 106, 33, 180, 248, 152, 37, 251, 247, ++ 55, 255, 40, 70, 39, 33, 180, 248, 154, 37, 251, 247, 49, 255, 40, 70, ++ 150, 33, 180, 248, 156, 37, 251, 247, 43, 255, 40, 70, 153, 33, 180, ++ 248, 158, 37, 251, 247, 37, 255, 40, 70, 121, 33, 180, 248, 160, 37, ++ 251, 247, 31, 255, 40, 70, 156, 33, 180, 248, 162, 37, 251, 247, 25, ++ 255, 40, 70, 159, 33, 180, 248, 164, 37, 251, 247, 19, 255, 40, 70, ++ 165, 33, 180, 248, 166, 37, 251, 247, 13, 255, 40, 70, 157, 33, 180, ++ 248, 168, 37, 251, 247, 7, 255, 40, 70, 158, 33, 180, 248, 170, 37, ++ 251, 247, 1, 255, 180, 248, 172, 37, 40, 70, 155, 33, 189, 232, 56, ++ 64, 251, 247, 249, 190, 112, 181, 208, 248, 228, 96, 0, 37, 4, 70, 156, ++ 33, 182, 248, 0, 37, 134, 248, 254, 84, 251, 247, 237, 254, 32, 70, ++ 164, 33, 182, 248, 2, 37, 251, 247, 231, 254, 32, 70, 165, 33, 182, ++ 248, 4, 37, 251, 247, 225, 254, 32, 70, 159, 33, 182, 248, 6, 37, 251, ++ 247, 219, 254, 32, 70, 157, 33, 182, 248, 8, 37, 251, 247, 213, 254, ++ 32, 70, 155, 33, 182, 248, 10, 37, 251, 247, 207, 254, 32, 70, 129, ++ 33, 1, 34, 43, 70, 252, 247, 41, 250, 32, 70, 62, 33, 4, 34, 43, 70, ++ 252, 247, 35, 250, 32, 70, 61, 33, 79, 244, 128, 82, 43, 70, 189, 232, ++ 112, 64, 252, 247, 26, 186, 16, 181, 138, 33, 4, 70, 251, 247, 164, ++ 254, 64, 244, 128, 114, 138, 33, 32, 70, 146, 178, 251, 247, 174, 254, ++ 32, 70, 27, 33, 0, 35, 79, 244, 224, 98, 252, 247, 7, 250, 81, 33, 1, ++ 34, 0, 35, 32, 70, 252, 247, 1, 250, 1, 32, 214, 243, 99, 246, 1, 34, ++ 32, 70, 81, 33, 19, 70, 252, 247, 248, 249, 79, 244, 128, 114, 32, 70, ++ 160, 33, 19, 70, 252, 247, 241, 249, 32, 70, 66, 33, 16, 34, 0, 35, ++ 252, 247, 235, 249, 79, 244, 0, 114, 32, 70, 160, 33, 19, 70, 252, 247, ++ 228, 249, 66, 33, 32, 34, 0, 35, 32, 70, 252, 247, 222, 249, 1, 32, ++ 214, 243, 64, 246, 16, 34, 32, 70, 19, 70, 66, 33, 252, 247, 213, 249, ++ 66, 33, 32, 34, 19, 70, 32, 70, 252, 247, 207, 249, 1, 32, 214, 243, ++ 49, 246, 128, 34, 32, 70, 66, 33, 19, 70, 252, 247, 198, 249, 64, 34, ++ 66, 33, 19, 70, 32, 70, 252, 247, 192, 249, 1, 32, 214, 243, 34, 246, ++ 32, 70, 66, 33, 128, 34, 0, 35, 252, 247, 183, 249, 32, 70, 66, 33, ++ 64, 34, 0, 35, 252, 247, 177, 249, 50, 32, 189, 232, 16, 64, 214, 243, ++ 17, 182, 112, 181, 4, 70, 14, 70, 100, 37, 10, 32, 214, 243, 10, 246, ++ 101, 33, 32, 70, 251, 247, 48, 254, 193, 7, 3, 212, 1, 61, 237, 178, ++ 0, 45, 242, 209, 1, 46, 2, 209, 100, 32, 214, 243, 251, 245, 138, 33, ++ 32, 70, 251, 247, 33, 254, 79, 246, 255, 98, 2, 64, 138, 33, 32, 70, ++ 189, 232, 112, 64, 251, 247, 41, 190, 56, 181, 208, 248, 228, 48, 1, ++ 57, 211, 248, 32, 54, 66, 37, 5, 251, 1, 53, 4, 70, 98, 33, 170, 136, ++ 251, 247, 27, 254, 32, 70, 83, 33, 234, 136, 251, 247, 22, 254, 32, ++ 70, 84, 33, 42, 137, 251, 247, 17, 254, 32, 70, 87, 33, 106, 137, 251, ++ 247, 12, 254, 32, 70, 88, 33, 170, 137, 251, 247, 7, 254, 32, 70, 100, ++ 33, 234, 137, 251, 247, 2, 254, 32, 70, 81, 33, 42, 138, 251, 247, 253, ++ 253, 32, 70, 92, 33, 106, 138, 251, 247, 248, 253, 32, 70, 93, 33, 170, ++ 138, 251, 247, 243, 253, 32, 70, 90, 33, 234, 138, 251, 247, 238, 253, ++ 32, 70, 91, 33, 42, 139, 251, 247, 233, 253, 32, 70, 99, 33, 106, 139, ++ 251, 247, 228, 253, 32, 70, 86, 33, 170, 139, 251, 247, 223, 253, 32, ++ 70, 89, 33, 234, 139, 251, 247, 218, 253, 32, 70, 97, 33, 42, 140, 251, ++ 247, 213, 253, 32, 70, 106, 140, 85, 33, 251, 247, 208, 253, 32, 70, ++ 95, 33, 170, 140, 251, 247, 203, 253, 32, 70, 82, 33, 234, 140, 251, ++ 247, 198, 253, 32, 70, 78, 33, 42, 141, 251, 247, 193, 253, 32, 70, ++ 79, 33, 106, 141, 251, 247, 188, 253, 32, 70, 77, 33, 170, 141, 251, ++ 247, 183, 253, 32, 70, 76, 33, 234, 141, 251, 247, 178, 253, 32, 70, ++ 74, 33, 42, 142, 251, 247, 173, 253, 32, 70, 75, 33, 106, 142, 251, ++ 247, 168, 253, 32, 70, 72, 33, 170, 142, 251, 247, 163, 253, 32, 70, ++ 73, 33, 234, 142, 251, 247, 158, 253, 32, 70, 69, 33, 42, 143, 251, ++ 247, 153, 253, 32, 70, 70, 33, 106, 143, 251, 247, 148, 253, 32, 70, ++ 24, 33, 170, 143, 251, 247, 143, 253, 32, 70, 60, 33, 234, 143, 251, ++ 247, 138, 253, 32, 70, 134, 33, 181, 248, 64, 32, 251, 247, 132, 253, ++ 32, 70, 61, 33, 79, 244, 128, 82, 0, 35, 252, 247, 221, 248, 32, 70, ++ 113, 33, 0, 35, 79, 244, 128, 82, 252, 247, 214, 248, 114, 33, 32, 70, ++ 79, 244, 0, 82, 0, 35, 252, 247, 207, 248, 32, 70, 255, 247, 178, 254, ++ 32, 70, 1, 33, 189, 232, 56, 64, 255, 247, 26, 191, 0, 0, 45, 233, 240, ++ 65, 105, 75, 134, 176, 25, 136, 154, 120, 173, 248, 12, 16, 141, 248, ++ 14, 32, 26, 70, 50, 248, 3, 31, 4, 70, 146, 120, 173, 248, 16, 16, 141, ++ 248, 18, 32, 26, 70, 50, 248, 6, 31, 212, 248, 228, 96, 146, 120, 173, ++ 248, 20, 16, 141, 248, 22, 32, 83, 248, 10, 15, 138, 33, 155, 136, 1, ++ 144, 32, 70, 173, 248, 8, 48, 251, 247, 45, 253, 0, 244, 254, 99, 138, ++ 33, 32, 70, 79, 244, 254, 98, 67, 244, 136, 67, 252, 247, 148, 248, ++ 13, 241, 2, 7, 0, 37, 3, 171, 235, 92, 32, 70, 30, 33, 64, 34, 155, ++ 1, 252, 247, 137, 248, 4, 171, 235, 92, 32, 70, 30, 33, 48, 34, 27, ++ 1, 252, 247, 129, 248, 5, 171, 235, 92, 32, 70, 143, 33, 79, 244, 127, ++ 66, 27, 2, 252, 247, 120, 248, 32, 70, 144, 33, 65, 246, 255, 114, 55, ++ 248, 2, 63, 252, 247, 112, 248, 30, 33, 1, 34, 0, 35, 32, 70, 252, 247, ++ 106, 248, 1, 32, 214, 243, 204, 244, 1, 34, 19, 70, 30, 33, 32, 70, ++ 252, 247, 97, 248, 35, 32, 214, 243, 195, 244, 1, 34, 32, 70, 143, 33, ++ 19, 70, 252, 247, 88, 248, 79, 240, 100, 8, 100, 32, 8, 241, 255, 56, ++ 214, 243, 182, 244, 31, 250, 136, 248, 32, 70, 145, 33, 251, 247, 218, ++ 252, 184, 241, 0, 15, 1, 208, 192, 7, 239, 213, 0, 35, 1, 34, 143, 33, ++ 32, 70, 252, 247, 64, 248, 146, 33, 32, 70, 251, 247, 203, 252, 147, ++ 33, 128, 70, 32, 70, 251, 247, 198, 252, 79, 234, 200, 72, 192, 4, 192, ++ 12, 79, 234, 216, 72, 21, 240, 255, 15, 200, 235, 0, 8, 212, 248, 128, ++ 49, 10, 209, 30, 72, 27, 11, 0, 251, 8, 248, 184, 251, 243, 248, 166, ++ 248, 174, 133, 166, 248, 176, 133, 7, 224, 25, 72, 27, 11, 0, 251, 8, ++ 248, 184, 251, 243, 248, 166, 248, 180, 133, 30, 33, 1, 34, 0, 35, 32, ++ 70, 1, 53, 252, 247, 16, 248, 2, 45, 127, 244, 124, 175, 148, 33, 32, ++ 70, 251, 247, 152, 252, 0, 244, 120, 112, 64, 17, 134, 248, 178, 5, ++ 163, 33, 32, 70, 79, 244, 128, 114, 0, 35, 251, 247, 253, 255, 138, ++ 33, 32, 70, 251, 247, 136, 252, 79, 246, 255, 50, 2, 64, 138, 33, 32, ++ 70, 6, 176, 189, 232, 240, 65, 251, 247, 143, 188, 40, 22, 4, 0, 165, ++ 140, 1, 0, 163, 142, 1, 0, 248, 181, 169, 33, 6, 70, 14, 77, 0, 224, ++ 33, 70, 76, 28, 164, 178, 48, 70, 21, 248, 1, 43, 251, 247, 124, 252, ++ 221, 44, 245, 209, 9, 77, 0, 224, 60, 70, 103, 28, 48, 70, 33, 70, 53, ++ 248, 2, 43, 251, 247, 112, 252, 191, 178, 64, 242, 21, 19, 159, 66, ++ 242, 209, 248, 189, 0, 191, 204, 68, 4, 0, 142, 72, 4, 0, 203, 75, 208, ++ 248, 128, 33, 140, 33, 154, 66, 79, 240, 1, 2, 16, 181, 12, 191, 19, ++ 70, 0, 35, 4, 70, 251, 247, 183, 255, 64, 34, 32, 70, 155, 33, 19, 70, ++ 251, 247, 177, 255, 128, 34, 32, 70, 25, 33, 19, 70, 251, 247, 171, ++ 255, 16, 34, 32, 70, 155, 33, 19, 70, 251, 247, 165, 255, 8, 34, 25, ++ 33, 19, 70, 32, 70, 251, 247, 159, 255, 100, 32, 214, 243, 1, 244, 1, ++ 34, 32, 70, 167, 33, 19, 70, 251, 247, 150, 255, 1, 34, 32, 70, 137, ++ 33, 19, 70, 251, 247, 144, 255, 1, 34, 32, 70, 151, 33, 19, 70, 251, ++ 247, 138, 255, 1, 34, 4, 33, 19, 70, 32, 70, 251, 247, 132, 255, 20, ++ 32, 214, 243, 230, 243, 32, 34, 32, 70, 19, 70, 155, 33, 251, 247, 123, ++ 255, 155, 33, 8, 34, 32, 70, 19, 70, 251, 247, 117, 255, 4, 34, 32, ++ 70, 155, 33, 19, 70, 251, 247, 111, 255, 2, 34, 32, 70, 155, 33, 19, ++ 70, 251, 247, 105, 255, 16, 34, 32, 70, 25, 33, 19, 70, 251, 247, 99, ++ 255, 4, 34, 32, 70, 25, 33, 19, 70, 251, 247, 93, 255, 2, 34, 32, 70, ++ 25, 33, 19, 70, 251, 247, 87, 255, 1, 34, 25, 33, 19, 70, 32, 70, 251, ++ 247, 81, 255, 200, 32, 214, 243, 179, 243, 1, 34, 32, 70, 67, 33, 19, ++ 70, 251, 247, 72, 255, 32, 70, 81, 33, 1, 34, 0, 35, 251, 247, 66, 255, ++ 32, 34, 32, 70, 19, 70, 160, 33, 251, 247, 60, 255, 66, 33, 2, 34, 32, ++ 70, 19, 70, 251, 247, 54, 255, 64, 34, 32, 70, 160, 33, 19, 70, 251, ++ 247, 48, 255, 4, 34, 32, 70, 66, 33, 19, 70, 251, 247, 42, 255, 16, ++ 34, 32, 70, 160, 33, 19, 70, 251, 247, 36, 255, 1, 34, 32, 70, 66, 33, ++ 19, 70, 251, 247, 30, 255, 128, 34, 32, 70, 160, 33, 19, 70, 251, 247, ++ 24, 255, 8, 34, 32, 70, 66, 33, 19, 70, 251, 247, 18, 255, 4, 34, 32, ++ 70, 151, 33, 19, 70, 251, 247, 12, 255, 32, 70, 4, 33, 240, 34, 112, ++ 35, 251, 247, 6, 255, 0, 35, 32, 70, 151, 33, 2, 34, 251, 247, 0, 255, ++ 32, 70, 138, 33, 251, 247, 139, 251, 79, 246, 255, 82, 2, 64, 138, 33, ++ 32, 70, 251, 247, 149, 251, 32, 70, 255, 247, 45, 254, 32, 70, 255, ++ 247, 170, 251, 32, 70, 8, 33, 240, 34, 64, 35, 251, 247, 233, 254, 8, ++ 33, 32, 70, 14, 34, 11, 70, 251, 247, 227, 254, 79, 244, 0, 114, 32, ++ 70, 111, 33, 19, 70, 251, 247, 220, 254, 32, 70, 111, 33, 0, 35, 79, ++ 244, 64, 98, 251, 247, 213, 254, 2, 34, 32, 70, 4, 33, 19, 70, 251, ++ 247, 207, 254, 108, 33, 48, 34, 16, 35, 32, 70, 251, 247, 201, 254, ++ 32, 70, 255, 247, 221, 254, 79, 244, 64, 114, 32, 70, 137, 33, 19, 70, ++ 251, 247, 191, 254, 32, 70, 24, 33, 7, 34, 0, 35, 251, 247, 185, 254, ++ 32, 70, 24, 33, 112, 34, 0, 35, 251, 247, 179, 254, 32, 70, 23, 33, ++ 224, 34, 64, 35, 251, 247, 173, 254, 79, 244, 224, 98, 32, 70, 23, 33, ++ 19, 70, 251, 247, 166, 254, 32, 70, 141, 33, 240, 34, 16, 35, 251, 247, ++ 160, 254, 32, 70, 121, 33, 32, 34, 0, 35, 251, 247, 154, 254, 32, 70, ++ 121, 33, 16, 34, 0, 35, 251, 247, 148, 254, 32, 70, 121, 33, 8, 34, ++ 0, 35, 251, 247, 142, 254, 32, 70, 122, 33, 79, 244, 127, 66, 79, 244, ++ 64, 83, 251, 247, 134, 254, 240, 34, 32, 70, 122, 33, 19, 70, 251, 247, ++ 128, 254, 32, 70, 15, 34, 0, 35, 122, 33, 251, 247, 122, 254, 124, 33, ++ 32, 70, 63, 34, 25, 35, 251, 247, 116, 254, 32, 70, 124, 33, 79, 244, ++ 124, 82, 79, 244, 200, 83, 251, 247, 108, 254, 32, 70, 125, 33, 0, 35, ++ 79, 244, 240, 98, 251, 247, 101, 254, 32, 70, 125, 33, 63, 34, 33, 35, ++ 251, 247, 95, 254, 32, 70, 131, 33, 62, 34, 42, 35, 251, 247, 89, 254, ++ 32, 70, 135, 33, 0, 35, 79, 244, 112, 66, 251, 247, 82, 254, 32, 70, ++ 135, 33, 79, 244, 124, 98, 79, 244, 32, 99, 251, 247, 74, 254, 32, 70, ++ 135, 33, 63, 34, 22, 35, 251, 247, 68, 254, 32, 70, 123, 33, 79, 244, ++ 224, 98, 79, 244, 128, 99, 251, 247, 60, 254, 32, 70, 123, 33, 64, 35, ++ 112, 34, 251, 247, 54, 254, 32, 70, 123, 33, 3, 34, 1, 35, 251, 247, ++ 48, 254, 32, 70, 30, 33, 1, 224, 192, 173, 58, 2, 128, 34, 0, 35, 189, ++ 232, 16, 64, 251, 247, 37, 190, 45, 233, 240, 79, 151, 176, 3, 146, ++ 144, 34, 0, 37, 26, 128, 14, 70, 64, 242, 218, 97, 4, 70, 152, 70, 14, ++ 149, 15, 149, 16, 149, 251, 247, 202, 250, 64, 246, 172, 17, 131, 70, ++ 32, 70, 251, 247, 196, 250, 64, 246, 121, 17, 130, 70, 32, 70, 251, ++ 247, 190, 250, 41, 70, 18, 170, 129, 70, 32, 70, 254, 247, 49, 251, ++ 32, 34, 19, 70, 32, 70, 64, 242, 218, 97, 251, 247, 54, 254, 79, 244, ++ 128, 114, 19, 70, 32, 70, 64, 242, 218, 97, 251, 247, 46, 254, 32, 70, ++ 64, 246, 121, 17, 79, 244, 255, 114, 43, 70, 251, 247, 38, 254, 1, 34, ++ 19, 70, 32, 70, 64, 246, 121, 17, 251, 247, 31, 254, 32, 70, 64, 246, ++ 172, 17, 79, 244, 112, 114, 179, 1, 251, 247, 23, 254, 1, 34, 19, 70, ++ 32, 70, 64, 246, 172, 17, 251, 247, 16, 254, 32, 70, 2, 33, 42, 70, ++ 254, 247, 255, 250, 10, 39, 0, 35, 0, 147, 1, 147, 79, 244, 0, 114, ++ 32, 35, 32, 70, 14, 169, 254, 247, 102, 250, 16, 154, 15, 155, 211, ++ 24, 8, 208, 22, 170, 2, 235, 133, 1, 1, 53, 173, 178, 10, 45, 65, 248, ++ 72, 60, 3, 208, 1, 63, 191, 178, 0, 47, 228, 209, 1, 33, 32, 70, 18, ++ 170, 254, 247, 222, 250, 32, 70, 64, 246, 121, 17, 74, 70, 251, 247, ++ 106, 250, 32, 70, 64, 246, 172, 17, 82, 70, 251, 247, 100, 250, 32, ++ 70, 64, 242, 218, 97, 90, 70, 251, 247, 94, 250, 9, 45, 75, 217, 4, ++ 171, 24, 70, 1, 34, 65, 104, 4, 175, 0, 37, 87, 248, 4, 235, 113, 69, ++ 156, 191, 71, 248, 4, 28, 113, 70, 1, 53, 173, 178, 15, 250, 133, 252, ++ 15, 250, 130, 254, 244, 69, 240, 219, 1, 50, 146, 178, 10, 42, 64, 248, ++ 4, 31, 231, 209, 3, 241, 32, 1, 0, 34, 83, 248, 4, 15, 139, 66, 2, 68, ++ 250, 209, 3, 155, 6, 235, 70, 6, 15, 62, 2, 245, 0, 98, 18, 11, 3, 235, ++ 134, 6, 0, 35, 18, 2, 0, 147, 20, 171, 17, 146, 1, 147, 32, 70, 21, ++ 170, 19, 171, 17, 169, 173, 248, 80, 96, 252, 247, 134, 252, 189, 248, ++ 76, 0, 10, 75, 2, 178, 155, 26, 0, 43, 184, 191, 91, 66, 24, 43, 7, ++ 216, 189, 248, 80, 48, 195, 24, 3, 245, 135, 115, 168, 248, 0, 48, 1, ++ 224, 79, 246, 120, 96, 0, 178, 23, 176, 189, 232, 240, 143, 120, 254, ++ 255, 255, 45, 233, 255, 65, 14, 70, 64, 246, 165, 17, 4, 70, 251, 247, ++ 245, 249, 2, 34, 19, 70, 128, 70, 64, 246, 165, 17, 32, 70, 251, 247, ++ 114, 253, 179, 104, 33, 43, 28, 209, 32, 70, 64, 242, 116, 81, 251, ++ 247, 229, 249, 64, 242, 117, 81, 7, 70, 32, 70, 251, 247, 223, 249, ++ 79, 244, 128, 66, 19, 70, 5, 70, 64, 242, 116, 81, 32, 70, 251, 247, ++ 91, 253, 79, 244, 128, 98, 32, 70, 64, 242, 117, 81, 19, 70, 251, 247, ++ 83, 253, 1, 224, 0, 37, 47, 70, 64, 242, 87, 66, 1, 146, 64, 242, 86, ++ 66, 14, 35, 2, 146, 32, 70, 13, 34, 49, 70, 0, 147, 251, 247, 224, 254, ++ 179, 104, 33, 43, 11, 209, 32, 70, 64, 242, 116, 81, 58, 70, 251, 247, ++ 192, 249, 32, 70, 64, 242, 117, 81, 42, 70, 251, 247, 186, 249, 32, ++ 70, 64, 246, 165, 17, 66, 70, 4, 176, 189, 232, 240, 65, 251, 247, 177, ++ 185, 127, 181, 0, 35, 173, 248, 22, 48, 2, 147, 16, 35, 4, 147, 13, ++ 241, 22, 3, 0, 147, 1, 35, 1, 147, 105, 70, 98, 35, 3, 147, 255, 247, ++ 152, 255, 189, 248, 22, 0, 7, 176, 0, 189, 127, 181, 13, 241, 22, 3, ++ 0, 147, 1, 35, 1, 147, 0, 35, 2, 147, 99, 35, 3, 147, 105, 70, 8, 35, ++ 4, 147, 255, 247, 133, 255, 157, 248, 22, 0, 7, 176, 0, 189, 56, 181, ++ 208, 248, 228, 64, 1, 35, 132, 248, 114, 53, 5, 70, 255, 247, 228, 255, ++ 64, 246, 165, 17, 132, 248, 115, 5, 40, 70, 251, 247, 110, 249, 64, ++ 242, 164, 65, 164, 248, 116, 5, 40, 70, 251, 247, 103, 249, 64, 246, ++ 172, 17, 164, 248, 118, 5, 40, 70, 251, 247, 96, 249, 64, 242, 218, ++ 97, 164, 248, 120, 5, 40, 70, 251, 247, 89, 249, 64, 242, 116, 81, 164, ++ 248, 122, 5, 40, 70, 251, 247, 82, 249, 64, 242, 117, 81, 164, 248, ++ 124, 5, 40, 70, 251, 247, 75, 249, 64, 242, 75, 65, 164, 248, 126, 5, ++ 40, 70, 251, 247, 68, 249, 64, 242, 76, 65, 164, 248, 128, 5, 40, 70, ++ 251, 247, 61, 249, 64, 242, 77, 65, 164, 248, 132, 5, 40, 70, 251, 247, ++ 54, 249, 64, 246, 56, 17, 164, 248, 134, 5, 40, 70, 251, 247, 47, 249, ++ 64, 246, 57, 17, 164, 248, 136, 5, 40, 70, 251, 247, 40, 249, 64, 246, ++ 7, 1, 164, 248, 138, 5, 40, 70, 251, 247, 33, 249, 164, 248, 142, 5, ++ 56, 189, 112, 181, 208, 248, 228, 80, 1, 38, 121, 33, 133, 248, 254, ++ 100, 133, 248, 12, 101, 4, 70, 251, 247, 235, 248, 122, 33, 165, 248, ++ 14, 5, 32, 70, 251, 247, 229, 248, 61, 33, 165, 248, 16, 5, 32, 70, ++ 251, 247, 223, 248, 165, 33, 165, 248, 22, 5, 32, 70, 251, 247, 217, ++ 248, 111, 33, 165, 248, 24, 5, 32, 70, 251, 247, 211, 248, 47, 33, 165, ++ 248, 26, 5, 32, 70, 251, 247, 205, 248, 39, 33, 165, 248, 28, 5, 32, ++ 70, 251, 247, 199, 248, 50, 33, 165, 248, 30, 5, 32, 70, 251, 247, 193, ++ 248, 126, 33, 165, 248, 32, 5, 32, 70, 251, 247, 187, 248, 56, 33, 165, ++ 248, 34, 5, 32, 70, 251, 247, 181, 248, 128, 33, 165, 248, 36, 5, 32, ++ 70, 251, 247, 175, 248, 129, 33, 165, 248, 38, 5, 32, 70, 251, 247, ++ 169, 248, 62, 33, 165, 248, 40, 5, 32, 70, 251, 247, 163, 248, 45, 33, ++ 165, 248, 42, 5, 32, 70, 251, 247, 157, 248, 25, 33, 165, 248, 44, 5, ++ 32, 70, 251, 247, 151, 248, 38, 33, 165, 248, 46, 5, 32, 70, 251, 247, ++ 145, 248, 31, 33, 165, 248, 48, 5, 32, 70, 251, 247, 139, 248, 124, ++ 33, 165, 248, 50, 5, 32, 70, 251, 247, 133, 248, 125, 33, 165, 248, ++ 18, 5, 32, 70, 251, 247, 127, 248, 5, 245, 166, 97, 4, 49, 165, 248, ++ 20, 5, 32, 70, 253, 247, 242, 253, 32, 70, 255, 247, 10, 255, 165, 248, ++ 62, 5, 32, 70, 253, 247, 8, 254, 111, 33, 165, 248, 60, 5, 0, 35, 32, ++ 70, 79, 244, 0, 82, 251, 247, 215, 251, 0, 35, 79, 244, 112, 82, 32, ++ 70, 47, 33, 251, 247, 208, 251, 156, 33, 32, 70, 251, 247, 91, 248, ++ 164, 33, 165, 248, 0, 5, 32, 70, 251, 247, 85, 248, 159, 33, 165, 248, ++ 2, 5, 32, 70, 251, 247, 79, 248, 157, 33, 165, 248, 6, 5, 32, 70, 251, ++ 247, 73, 248, 155, 33, 165, 248, 8, 5, 32, 70, 251, 247, 67, 248, 2, ++ 34, 165, 248, 10, 5, 156, 33, 32, 70, 19, 70, 251, 247, 172, 251, 32, ++ 70, 39, 33, 79, 244, 112, 98, 0, 35, 251, 247, 165, 251, 32, 70, 50, ++ 33, 79, 244, 0, 98, 0, 35, 251, 247, 158, 251, 32, 70, 50, 33, 0, 35, ++ 79, 244, 128, 98, 251, 247, 151, 251, 32, 70, 164, 33, 50, 70, 51, 70, ++ 251, 247, 145, 251, 79, 244, 128, 114, 32, 70, 126, 33, 19, 70, 251, ++ 247, 138, 251, 2, 34, 32, 70, 164, 33, 19, 70, 251, 247, 132, 251, 79, ++ 244, 128, 66, 32, 70, 126, 33, 19, 70, 251, 247, 125, 251, 79, 244, ++ 0, 114, 32, 70, 159, 33, 19, 70, 251, 247, 118, 251, 32, 70, 56, 33, ++ 4, 34, 0, 35, 251, 247, 112, 251, 79, 244, 128, 98, 32, 70, 165, 33, ++ 19, 70, 251, 247, 105, 251, 64, 34, 32, 70, 128, 33, 19, 70, 251, 247, ++ 99, 251, 79, 244, 0, 114, 32, 70, 165, 33, 19, 70, 251, 247, 92, 251, ++ 32, 34, 32, 70, 128, 33, 19, 70, 251, 247, 86, 251, 32, 70, 129, 33, ++ 50, 70, 51, 70, 251, 247, 80, 251, 62, 33, 4, 34, 32, 70, 19, 70, 251, ++ 247, 74, 251, 128, 34, 32, 70, 159, 33, 19, 70, 251, 247, 68, 251, 32, ++ 70, 56, 33, 50, 70, 0, 35, 251, 247, 62, 251, 79, 244, 128, 114, 32, ++ 70, 159, 33, 19, 70, 251, 247, 55, 251, 2, 34, 32, 70, 56, 33, 19, 70, ++ 251, 247, 49, 251, 16, 34, 32, 70, 159, 33, 19, 70, 251, 247, 43, 251, ++ 32, 70, 61, 33, 0, 35, 79, 244, 0, 82, 251, 247, 36, 251, 79, 244, 128, ++ 82, 32, 70, 61, 33, 19, 70, 251, 247, 29, 251, 32, 34, 32, 70, 159, ++ 33, 19, 70, 251, 247, 23, 251, 79, 244, 128, 66, 32, 70, 61, 33, 19, ++ 70, 251, 247, 16, 251, 4, 34, 32, 70, 159, 33, 19, 70, 251, 247, 10, ++ 251, 32, 34, 32, 70, 62, 33, 19, 70, 251, 247, 4, 251, 79, 244, 128, ++ 114, 32, 70, 19, 70, 157, 33, 251, 247, 253, 250, 79, 244, 0, 98, 32, ++ 70, 45, 33, 19, 70, 251, 247, 246, 250, 64, 34, 32, 70, 157, 33, 19, ++ 70, 251, 247, 240, 250, 79, 244, 0, 114, 32, 70, 45, 33, 19, 70, 251, ++ 247, 233, 250, 128, 34, 32, 70, 157, 33, 19, 70, 251, 247, 227, 250, ++ 79, 244, 128, 98, 19, 70, 32, 70, 45, 33, 251, 247, 220, 250, 32, 70, ++ 3, 33, 254, 247, 71, 252, 2, 34, 32, 70, 155, 33, 19, 70, 251, 247, ++ 210, 250, 32, 70, 25, 33, 50, 70, 51, 70, 251, 247, 204, 250, 4, 34, ++ 32, 70, 156, 33, 19, 70, 251, 247, 198, 250, 79, 244, 128, 82, 32, 70, ++ 38, 33, 19, 70, 251, 247, 191, 250, 8, 34, 32, 70, 156, 33, 19, 70, ++ 251, 247, 185, 250, 32, 70, 31, 33, 50, 70, 51, 70, 251, 247, 179, 250, ++ 32, 34, 32, 70, 19, 70, 156, 33, 251, 247, 173, 250, 31, 33, 8, 34, ++ 32, 70, 19, 70, 189, 232, 112, 64, 251, 247, 165, 186, 48, 181, 135, ++ 176, 5, 171, 0, 147, 2, 35, 1, 147, 0, 35, 2, 147, 96, 35, 12, 70, 3, ++ 147, 105, 70, 16, 35, 21, 70, 4, 147, 255, 247, 77, 253, 189, 248, 20, ++ 48, 35, 128, 189, 248, 22, 48, 43, 128, 7, 176, 48, 189, 45, 233, 255, ++ 65, 14, 70, 64, 246, 165, 17, 4, 70, 250, 247, 58, 255, 2, 34, 19, 70, ++ 128, 70, 64, 246, 165, 17, 32, 70, 251, 247, 183, 250, 179, 104, 33, ++ 43, 28, 209, 32, 70, 64, 242, 116, 81, 250, 247, 42, 255, 64, 242, 117, ++ 81, 7, 70, 32, 70, 250, 247, 36, 255, 79, 244, 128, 66, 19, 70, 5, 70, ++ 64, 242, 116, 81, 32, 70, 251, 247, 160, 250, 79, 244, 128, 98, 32, ++ 70, 64, 242, 117, 81, 19, 70, 251, 247, 152, 250, 1, 224, 0, 37, 47, ++ 70, 64, 242, 87, 66, 1, 146, 64, 242, 86, 66, 14, 35, 2, 146, 32, 70, ++ 13, 34, 49, 70, 0, 147, 251, 247, 156, 251, 179, 104, 33, 43, 11, 209, ++ 32, 70, 64, 242, 116, 81, 58, 70, 250, 247, 5, 255, 32, 70, 64, 242, ++ 117, 81, 42, 70, 250, 247, 255, 254, 32, 70, 64, 246, 165, 17, 66, 70, ++ 4, 176, 189, 232, 240, 65, 250, 247, 246, 190, 112, 181, 198, 176, 1, ++ 173, 208, 248, 228, 96, 4, 70, 0, 33, 40, 70, 79, 244, 128, 114, 209, ++ 243, 32, 243, 7, 35, 67, 147, 32, 35, 69, 147, 150, 248, 200, 52, 65, ++ 149, 67, 185, 20, 35, 66, 147, 32, 70, 79, 244, 80, 115, 65, 169, 68, ++ 147, 255, 247, 140, 255, 64, 35, 66, 147, 32, 70, 128, 35, 65, 169, ++ 68, 147, 255, 247, 132, 255, 70, 176, 112, 189, 0, 0, 127, 181, 144, ++ 248, 114, 51, 99, 177, 7, 75, 1, 169, 1, 147, 20, 35, 2, 147, 7, 35, ++ 3, 147, 8, 35, 5, 147, 128, 35, 4, 147, 255, 247, 112, 255, 7, 176, ++ 0, 189, 0, 191, 14, 109, 4, 0, 16, 181, 134, 176, 6, 171, 35, 248, 2, ++ 29, 0, 147, 1, 35, 1, 147, 0, 35, 2, 147, 99, 35, 4, 70, 3, 147, 105, ++ 70, 16, 35, 4, 147, 255, 247, 89, 255, 115, 35, 32, 70, 105, 70, 3, ++ 147, 255, 247, 83, 255, 6, 176, 16, 189, 56, 181, 208, 248, 228, 64, ++ 0, 35, 5, 70, 132, 248, 114, 53, 148, 248, 115, 21, 255, 247, 219, 255, ++ 40, 70, 180, 248, 116, 37, 64, 246, 165, 17, 250, 247, 140, 254, 40, ++ 70, 180, 248, 118, 37, 64, 242, 164, 65, 250, 247, 133, 254, 40, 70, ++ 180, 248, 120, 37, 64, 246, 172, 17, 250, 247, 126, 254, 40, 70, 180, ++ 248, 122, 37, 64, 242, 218, 97, 250, 247, 119, 254, 40, 70, 180, 248, ++ 124, 37, 64, 242, 116, 81, 250, 247, 112, 254, 40, 70, 180, 248, 126, ++ 37, 64, 242, 117, 81, 250, 247, 105, 254, 40, 70, 180, 248, 128, 37, ++ 64, 242, 75, 65, 250, 247, 98, 254, 40, 70, 180, 248, 132, 37, 64, 242, ++ 76, 65, 250, 247, 91, 254, 40, 70, 180, 248, 134, 37, 64, 242, 77, 65, ++ 250, 247, 84, 254, 40, 70, 180, 248, 136, 37, 64, 246, 56, 17, 250, ++ 247, 77, 254, 40, 70, 180, 248, 138, 37, 64, 246, 57, 17, 250, 247, ++ 70, 254, 180, 248, 142, 37, 40, 70, 64, 246, 7, 1, 189, 232, 56, 64, ++ 250, 247, 61, 190, 56, 181, 208, 248, 228, 64, 0, 35, 5, 70, 132, 248, ++ 254, 52, 132, 248, 12, 53, 156, 33, 180, 248, 0, 37, 250, 247, 14, 254, ++ 40, 70, 164, 33, 180, 248, 2, 37, 250, 247, 8, 254, 40, 70, 159, 33, ++ 180, 248, 6, 37, 250, 247, 2, 254, 40, 70, 157, 33, 180, 248, 8, 37, ++ 250, 247, 252, 253, 40, 70, 155, 33, 180, 248, 10, 37, 250, 247, 246, ++ 253, 40, 70, 121, 33, 180, 248, 14, 37, 250, 247, 240, 253, 40, 70, ++ 122, 33, 180, 248, 16, 37, 250, 247, 234, 253, 40, 70, 61, 33, 180, ++ 248, 22, 37, 250, 247, 228, 253, 40, 70, 165, 33, 180, 248, 24, 37, ++ 250, 247, 222, 253, 40, 70, 111, 33, 180, 248, 26, 37, 250, 247, 216, ++ 253, 40, 70, 47, 33, 180, 248, 28, 37, 250, 247, 210, 253, 40, 70, 39, ++ 33, 180, 248, 30, 37, 250, 247, 204, 253, 40, 70, 50, 33, 180, 248, ++ 32, 37, 250, 247, 198, 253, 40, 70, 126, 33, 180, 248, 34, 37, 250, ++ 247, 192, 253, 40, 70, 125, 33, 180, 248, 20, 37, 250, 247, 186, 253, ++ 40, 70, 180, 248, 36, 37, 56, 33, 250, 247, 180, 253, 128, 33, 40, 70, ++ 180, 248, 38, 37, 250, 247, 174, 253, 40, 70, 129, 33, 180, 248, 40, ++ 37, 250, 247, 168, 253, 40, 70, 62, 33, 180, 248, 42, 37, 250, 247, ++ 162, 253, 40, 70, 45, 33, 180, 248, 44, 37, 250, 247, 156, 253, 40, ++ 70, 25, 33, 180, 248, 46, 37, 250, 247, 150, 253, 40, 70, 38, 33, 180, ++ 248, 48, 37, 250, 247, 144, 253, 40, 70, 31, 33, 180, 248, 50, 37, 250, ++ 247, 138, 253, 40, 70, 124, 33, 180, 248, 18, 37, 250, 247, 132, 253, ++ 180, 248, 20, 37, 40, 70, 125, 33, 250, 247, 126, 253, 4, 245, 166, ++ 97, 40, 70, 4, 49, 253, 247, 29, 251, 40, 70, 148, 248, 62, 21, 255, ++ 247, 220, 254, 180, 248, 60, 21, 40, 70, 189, 232, 56, 64, 253, 247, ++ 238, 184, 127, 181, 0, 35, 2, 147, 16, 35, 4, 147, 5, 171, 0, 147, 2, ++ 35, 173, 248, 20, 16, 1, 147, 105, 70, 96, 35, 173, 248, 22, 32, 3, ++ 147, 255, 247, 46, 254, 7, 176, 0, 189, 0, 181, 0, 35, 137, 176, 5, ++ 147, 16, 35, 7, 147, 13, 241, 6, 3, 3, 147, 1, 35, 173, 248, 6, 16, ++ 4, 147, 3, 169, 98, 35, 6, 147, 255, 247, 26, 254, 9, 176, 0, 189, 45, ++ 233, 240, 67, 208, 248, 228, 48, 141, 176, 32, 39, 131, 248, 68, 20, ++ 131, 248, 69, 20, 1, 245, 16, 115, 12, 173, 4, 147, 13, 235, 7, 3, 69, ++ 248, 44, 61, 79, 240, 1, 8, 14, 70, 79, 240, 7, 9, 41, 70, 4, 70, 205, ++ 248, 12, 144, 5, 151, 205, 248, 8, 128, 255, 247, 61, 251, 6, 241, 192, ++ 3, 4, 147, 32, 70, 9, 171, 41, 70, 1, 147, 5, 151, 255, 247, 51, 251, ++ 9, 155, 32, 70, 3, 240, 31, 2, 173, 248, 24, 32, 90, 9, 91, 11, 219, ++ 178, 173, 248, 28, 48, 8, 155, 210, 178, 91, 12, 3, 240, 15, 3, 6, 169, ++ 173, 248, 26, 32, 173, 248, 30, 48, 253, 247, 168, 250, 9, 153, 32, ++ 70, 73, 13, 201, 178, 253, 247, 127, 248, 8, 153, 32, 70, 73, 10, 201, ++ 178, 255, 247, 96, 254, 4, 34, 32, 70, 19, 70, 64, 246, 7, 1, 251, 247, ++ 139, 248, 8, 155, 65, 246, 240, 114, 219, 5, 219, 13, 27, 1, 32, 70, ++ 64, 246, 7, 1, 251, 247, 128, 248, 32, 70, 65, 70, 253, 247, 79, 248, ++ 79, 244, 160, 115, 4, 147, 32, 70, 11, 171, 41, 70, 1, 147, 205, 248, ++ 12, 144, 5, 151, 205, 248, 8, 128, 255, 247, 236, 250, 11, 154, 32, ++ 70, 145, 10, 137, 5, 146, 5, 146, 13, 137, 13, 255, 247, 94, 255, 16, ++ 35, 5, 147, 32, 70, 10, 171, 41, 70, 6, 245, 224, 118, 1, 147, 4, 150, ++ 255, 247, 216, 250, 32, 70, 189, 248, 40, 16, 255, 247, 98, 255, 32, ++ 70, 64, 242, 166, 97, 65, 246, 255, 114, 0, 35, 251, 247, 77, 248, 13, ++ 176, 189, 232, 240, 131, 45, 233, 240, 67, 64, 246, 117, 17, 135, 176, ++ 4, 70, 250, 247, 189, 252, 64, 246, 105, 17, 7, 70, 32, 70, 250, 247, ++ 183, 252, 64, 246, 120, 17, 6, 70, 32, 70, 250, 247, 177, 252, 0, 33, ++ 10, 70, 95, 250, 128, 248, 32, 70, 253, 247, 30, 248, 32, 70, 64, 246, ++ 113, 17, 255, 34, 254, 35, 251, 247, 40, 248, 8, 34, 19, 70, 32, 70, ++ 64, 246, 101, 17, 251, 247, 33, 248, 32, 70, 2, 33, 0, 34, 253, 247, ++ 11, 248, 4, 34, 19, 70, 32, 70, 79, 244, 136, 97, 251, 247, 21, 248, ++ 1, 34, 19, 70, 32, 70, 64, 242, 74, 65, 251, 247, 14, 248, 32, 70, 64, ++ 242, 74, 65, 1, 34, 0, 35, 251, 247, 7, 248, 5, 37, 1, 34, 19, 70, 32, ++ 70, 64, 242, 74, 65, 250, 247, 255, 255, 32, 70, 64, 242, 74, 65, 1, ++ 34, 0, 35, 250, 247, 248, 255, 79, 240, 11, 9, 2, 224, 10, 32, 213, ++ 243, 28, 244, 32, 70, 64, 246, 116, 17, 250, 247, 104, 252, 131, 7, ++ 2, 213, 185, 241, 1, 9, 242, 209, 32, 70, 64, 246, 120, 17, 250, 247, ++ 94, 252, 192, 178, 255, 40, 3, 208, 1, 61, 237, 178, 0, 45, 213, 209, ++ 4, 34, 32, 70, 0, 35, 79, 244, 136, 97, 250, 247, 213, 255, 5, 171, ++ 0, 147, 1, 35, 1, 147, 35, 35, 2, 147, 0, 37, 32, 35, 32, 70, 105, 70, ++ 4, 147, 3, 149, 255, 247, 69, 250, 5, 154, 32, 70, 210, 5, 210, 13, ++ 64, 242, 188, 65, 250, 247, 69, 252, 5, 154, 32, 70, 82, 10, 210, 5, ++ 210, 13, 64, 242, 187, 65, 250, 247, 60, 252, 32, 70, 105, 70, 5, 149, ++ 255, 247, 234, 252, 32, 70, 58, 70, 64, 246, 117, 17, 250, 247, 49, ++ 252, 32, 70, 50, 70, 64, 246, 105, 17, 250, 247, 43, 252, 32, 70, 255, ++ 34, 67, 70, 64, 246, 113, 17, 250, 247, 158, 255, 8, 34, 32, 70, 64, ++ 246, 101, 17, 19, 70, 250, 247, 151, 255, 7, 176, 189, 232, 240, 131, ++ 48, 181, 208, 248, 228, 80, 4, 70, 135, 176, 40, 70, 79, 244, 0, 113, ++ 65, 242, 111, 2, 252, 247, 5, 254, 0, 40, 0, 240, 158, 128, 7, 35, 3, ++ 147, 32, 35, 5, 147, 128, 35, 2, 147, 0, 35, 1, 144, 4, 147, 64, 248, ++ 4, 59, 1, 51, 128, 43, 250, 209, 32, 70, 1, 169, 255, 247, 172, 252, ++ 79, 244, 48, 115, 32, 70, 1, 169, 4, 147, 255, 247, 165, 252, 212, 248, ++ 228, 0, 65, 242, 130, 1, 252, 247, 240, 253, 32, 70, 1, 33, 253, 247, ++ 4, 251, 32, 70, 62, 73, 54, 34, 250, 247, 111, 255, 213, 248, 196, 52, ++ 32, 70, 64, 246, 244, 17, 79, 244, 128, 66, 107, 177, 19, 70, 250, 247, ++ 82, 255, 181, 248, 88, 36, 181, 248, 86, 52, 32, 70, 211, 24, 64, 242, ++ 12, 81, 64, 242, 255, 18, 155, 178, 250, 247, 69, 255, 30, 34, 48, 73, ++ 32, 70, 250, 247, 82, 255, 32, 70, 255, 247, 205, 252, 32, 70, 254, ++ 247, 13, 250, 153, 33, 1, 34, 0, 35, 32, 70, 250, 247, 249, 254, 150, ++ 33, 2, 34, 0, 35, 32, 70, 250, 247, 243, 254, 162, 33, 1, 34, 0, 35, ++ 32, 70, 250, 247, 237, 254, 165, 33, 64, 34, 0, 35, 32, 70, 250, 247, ++ 231, 254, 166, 33, 1, 34, 0, 35, 32, 70, 250, 247, 225, 254, 161, 33, ++ 1, 34, 0, 35, 32, 70, 250, 247, 219, 254, 48, 34, 0, 35, 32, 70, 2, ++ 33, 250, 247, 213, 254, 111, 33, 32, 70, 79, 244, 0, 82, 0, 35, 250, ++ 247, 206, 254, 79, 244, 128, 82, 19, 70, 32, 70, 111, 33, 250, 247, ++ 199, 254, 4, 34, 19, 70, 32, 70, 64, 242, 215, 65, 250, 247, 251, 254, ++ 64, 242, 215, 65, 79, 244, 112, 98, 79, 244, 128, 115, 32, 70, 250, ++ 247, 242, 254, 32, 70, 253, 247, 189, 250, 32, 70, 64, 242, 117, 81, ++ 79, 244, 0, 114, 0, 35, 250, 247, 231, 254, 7, 176, 48, 189, 0, 191, ++ 46, 70, 4, 0, 154, 70, 4, 0, 45, 233, 240, 67, 155, 176, 4, 70, 13, ++ 70, 22, 70, 0, 33, 48, 34, 104, 70, 31, 70, 208, 243, 144, 247, 32, ++ 70, 32, 35, 64, 246, 118, 17, 64, 246, 255, 114, 250, 247, 204, 254, ++ 232, 7, 45, 213, 32, 70, 64, 246, 102, 17, 79, 246, 247, 114, 72, 246, ++ 133, 19, 250, 247, 193, 254, 32, 70, 64, 246, 103, 17, 255, 34, 25, ++ 35, 250, 247, 186, 254, 110, 177, 0, 171, 17, 147, 12, 35, 18, 147, ++ 34, 35, 19, 147, 32, 35, 21, 147, 32, 70, 0, 35, 17, 169, 20, 147, 255, ++ 247, 228, 251, 32, 70, 64, 246, 110, 17, 64, 246, 255, 114, 0, 35, 250, ++ 247, 163, 254, 4, 34, 32, 70, 64, 246, 101, 17, 19, 70, 250, 247, 156, ++ 254, 169, 7, 105, 213, 63, 75, 13, 241, 88, 14, 3, 241, 16, 12, 24, ++ 104, 89, 104, 114, 70, 3, 194, 8, 51, 99, 69, 150, 70, 247, 209, 32, ++ 70, 64, 246, 104, 17, 79, 246, 247, 114, 69, 246, 134, 83, 250, 247, ++ 132, 254, 32, 70, 64, 246, 103, 17, 79, 244, 127, 66, 79, 244, 32, 83, ++ 250, 247, 123, 254, 32, 70, 64, 246, 105, 17, 1, 35, 255, 34, 250, 247, ++ 116, 254, 22, 171, 12, 147, 36, 35, 79, 240, 8, 9, 14, 147, 79, 240, ++ 0, 8, 16, 35, 32, 70, 12, 169, 205, 248, 52, 144, 16, 147, 205, 248, ++ 60, 128, 255, 247, 155, 251, 118, 177, 13, 235, 8, 3, 12, 147, 35, 35, ++ 14, 147, 32, 70, 32, 35, 12, 169, 205, 248, 52, 144, 16, 147, 205, 248, ++ 60, 128, 255, 247, 139, 251, 32, 70, 64, 246, 113, 17, 255, 34, 1, 35, ++ 250, 247, 75, 254, 8, 34, 19, 70, 32, 70, 64, 246, 101, 17, 250, 247, ++ 68, 254, 32, 70, 64, 242, 177, 65, 1, 34, 0, 35, 250, 247, 61, 254, ++ 32, 70, 79, 244, 150, 97, 7, 34, 0, 35, 250, 247, 54, 254, 32, 70, 50, ++ 33, 126, 34, 123, 0, 250, 247, 245, 253, 106, 7, 15, 213, 32, 70, 64, ++ 246, 107, 17, 79, 244, 127, 66, 79, 244, 32, 83, 250, 247, 37, 254, ++ 32, 70, 64, 246, 109, 17, 63, 34, 24, 35, 250, 247, 30, 254, 27, 176, ++ 189, 232, 240, 131, 0, 191, 56, 22, 4, 0, 240, 181, 7, 35, 135, 176, ++ 208, 248, 228, 96, 2, 147, 32, 35, 4, 147, 1, 35, 4, 70, 13, 70, 1, ++ 147, 48, 70, 5, 171, 79, 244, 0, 113, 65, 242, 198, 34, 0, 147, 252, ++ 247, 128, 252, 0, 40, 75, 208, 214, 248, 184, 101, 7, 70, 1, 70, 0, ++ 35, 179, 66, 44, 191, 158, 70, 182, 70, 5, 235, 206, 2, 146, 248, 3, ++ 192, 21, 248, 62, 224, 1, 51, 78, 234, 76, 94, 146, 248, 2, 192, 82, ++ 120, 78, 234, 76, 62, 78, 234, 66, 18, 128, 43, 5, 146, 65, 248, 4, ++ 43, 230, 209, 141, 232, 9, 0, 105, 70, 192, 35, 32, 70, 3, 147, 255, ++ 247, 20, 251, 0, 35, 179, 66, 44, 191, 26, 70, 50, 70, 5, 235, 194, ++ 2, 16, 121, 81, 121, 64, 2, 64, 234, 65, 64, 209, 121, 1, 51, 64, 234, ++ 1, 2, 128, 43, 5, 146, 71, 248, 4, 43, 235, 209, 79, 244, 16, 115, 32, ++ 70, 105, 70, 3, 147, 255, 247, 248, 250, 212, 248, 228, 48, 65, 242, ++ 242, 33, 195, 248, 188, 85, 212, 248, 228, 0, 252, 247, 63, 252, 7, ++ 176, 240, 189, 112, 181, 208, 248, 228, 80, 164, 176, 149, 249, 84, ++ 100, 4, 70, 110, 177, 251, 247, 56, 251, 149, 249, 84, 52, 64, 242, ++ 167, 65, 160, 235, 131, 3, 255, 34, 32, 70, 155, 178, 250, 247, 158, ++ 253, 139, 224, 208, 248, 136, 4, 0, 40, 0, 240, 135, 128, 49, 70, 1, ++ 34, 35, 171, 5, 240, 68, 248, 33, 171, 0, 147, 49, 70, 50, 70, 1, 35, ++ 212, 248, 136, 4, 5, 240, 84, 248, 30, 171, 1, 34, 1, 147, 49, 70, 51, ++ 70, 212, 248, 136, 4, 0, 146, 5, 240, 101, 248, 2, 169, 42, 70, 43, ++ 70, 35, 168, 48, 86, 1, 54, 64, 66, 65, 248, 4, 15, 195, 248, 92, 4, ++ 4, 51, 4, 46, 244, 209, 6, 168, 41, 70, 0, 35, 33, 174, 158, 87, 1, ++ 51, 118, 66, 64, 248, 4, 111, 193, 248, 108, 100, 4, 49, 8, 43, 244, ++ 209, 14, 169, 0, 35, 30, 168, 24, 86, 1, 51, 64, 66, 65, 248, 4, 15, ++ 194, 248, 140, 4, 4, 50, 10, 43, 244, 209, 149, 248, 200, 52, 115, 185, ++ 7, 35, 27, 147, 32, 35, 29, 147, 22, 35, 26, 147, 3, 171, 25, 147, 32, ++ 70, 79, 244, 80, 115, 25, 169, 28, 147, 255, 247, 126, 250, 148, 248, ++ 114, 51, 19, 177, 32, 70, 255, 247, 247, 250, 32, 70, 251, 247, 203, ++ 250, 64, 242, 167, 65, 3, 70, 255, 34, 32, 70, 250, 247, 53, 253, 149, ++ 248, 51, 54, 235, 177, 64, 242, 167, 65, 32, 70, 250, 247, 168, 249, ++ 149, 248, 49, 38, 67, 0, 149, 248, 50, 102, 219, 178, 158, 27, 155, ++ 26, 27, 2, 79, 244, 127, 66, 19, 64, 32, 70, 64, 242, 209, 65, 250, ++ 247, 28, 253, 115, 178, 32, 70, 64, 242, 209, 65, 255, 34, 155, 178, ++ 250, 247, 20, 253, 32, 70, 252, 247, 207, 251, 36, 176, 112, 189, 45, ++ 233, 240, 65, 13, 70, 64, 242, 164, 65, 4, 70, 208, 248, 228, 96, 250, ++ 247, 128, 249, 0, 244, 96, 71, 175, 66, 0, 240, 158, 128, 64, 34, 0, ++ 35, 32, 70, 64, 242, 218, 97, 250, 247, 249, 252, 16, 34, 181, 245, ++ 96, 79, 20, 191, 19, 70, 0, 35, 32, 70, 64, 242, 163, 97, 250, 247, ++ 238, 252, 79, 244, 0, 82, 181, 245, 96, 79, 12, 191, 19, 70, 0, 35, ++ 32, 70, 64, 242, 55, 97, 250, 247, 226, 252, 79, 244, 128, 82, 181, ++ 245, 96, 79, 12, 191, 19, 70, 0, 35, 32, 70, 64, 242, 55, 97, 250, 247, ++ 214, 252, 4, 34, 181, 245, 96, 79, 8, 191, 19, 70, 32, 70, 24, 191, ++ 0, 35, 79, 244, 154, 97, 250, 247, 202, 252, 3, 34, 0, 35, 32, 70, 79, ++ 244, 143, 97, 250, 247, 195, 252, 183, 245, 96, 79, 8, 209, 32, 70, ++ 255, 247, 77, 250, 32, 70, 64, 242, 110, 65, 0, 34, 250, 247, 61, 249, ++ 181, 245, 96, 79, 32, 70, 67, 209, 255, 247, 254, 254, 182, 248, 2, ++ 116, 79, 246, 254, 115, 127, 0, 32, 70, 59, 64, 64, 242, 164, 65, 64, ++ 242, 255, 18, 250, 247, 164, 252, 182, 248, 4, 116, 79, 246, 254, 115, ++ 127, 0, 32, 70, 59, 64, 79, 244, 144, 97, 64, 242, 255, 18, 250, 247, ++ 151, 252, 182, 248, 52, 52, 32, 70, 155, 2, 3, 244, 124, 67, 64, 242, ++ 165, 65, 79, 244, 224, 82, 250, 247, 139, 252, 1, 34, 32, 70, 64, 242, ++ 110, 65, 250, 247, 11, 249, 163, 107, 224, 33, 24, 105, 4, 240, 132, ++ 250, 0, 33, 166, 248, 54, 4, 32, 70, 252, 247, 77, 252, 255, 35, 134, ++ 248, 68, 52, 32, 70, 64, 246, 7, 1, 4, 34, 0, 35, 250, 247, 112, 252, ++ 2, 224, 1, 33, 252, 247, 63, 252, 32, 70, 64, 242, 164, 65, 79, 244, ++ 96, 66, 43, 70, 189, 232, 240, 65, 250, 247, 98, 188, 189, 232, 240, ++ 129, 56, 181, 64, 242, 164, 65, 4, 70, 250, 247, 213, 248, 0, 33, 5, ++ 70, 32, 70, 255, 247, 70, 255, 32, 70, 255, 247, 159, 254, 32, 70, 5, ++ 244, 96, 65, 189, 232, 56, 64, 255, 247, 60, 191, 240, 181, 208, 248, ++ 228, 112, 137, 176, 0, 35, 4, 70, 13, 70, 56, 70, 79, 244, 0, 113, 65, ++ 242, 19, 34, 5, 147, 6, 147, 7, 147, 252, 247, 183, 250, 6, 70, 0, 40, ++ 53, 208, 77, 185, 32, 70, 5, 169, 6, 170, 7, 171, 252, 247, 145, 248, ++ 3, 149, 55, 70, 0, 37, 16, 224, 151, 248, 51, 54, 0, 43, 248, 208, 180, ++ 249, 204, 58, 6, 147, 180, 249, 206, 58, 7, 147, 180, 249, 208, 58, ++ 5, 147, 79, 244, 48, 115, 3, 147, 235, 231, 5, 169, 40, 70, 14, 201, ++ 252, 247, 199, 250, 1, 53, 128, 45, 71, 248, 4, 11, 245, 209, 7, 35, ++ 2, 147, 32, 70, 32, 35, 105, 70, 4, 147, 0, 150, 1, 149, 255, 247, 64, ++ 249, 212, 248, 228, 0, 65, 242, 50, 33, 252, 247, 139, 250, 9, 176, ++ 240, 189, 45, 233, 240, 67, 144, 248, 13, 84, 137, 176, 0, 36, 0, 245, ++ 208, 121, 4, 35, 144, 70, 6, 70, 1, 147, 72, 70, 33, 70, 42, 70, 7, ++ 171, 0, 148, 251, 247, 197, 255, 33, 70, 1, 34, 7, 171, 64, 70, 4, 240, ++ 3, 255, 3, 33, 1, 34, 7, 171, 64, 70, 4, 240, 253, 254, 5, 175, 8, 35, ++ 1, 147, 9, 241, 4, 0, 33, 70, 42, 70, 59, 70, 0, 148, 251, 247, 174, ++ 255, 1, 35, 0, 151, 33, 70, 34, 70, 2, 175, 64, 70, 4, 240, 253, 254, ++ 214, 248, 168, 1, 41, 70, 58, 70, 251, 247, 213, 255, 150, 248, 172, ++ 33, 111, 240, 1, 3, 2, 240, 15, 1, 3, 251, 1, 81, 18, 9, 3, 251, 2, ++ 85, 141, 248, 16, 16, 1, 34, 64, 70, 33, 70, 35, 70, 141, 248, 17, 80, ++ 141, 232, 132, 0, 4, 240, 244, 254, 9, 176, 189, 232, 240, 131, 45, ++ 233, 243, 71, 21, 70, 36, 38, 129, 234, 225, 114, 162, 235, 225, 114, ++ 86, 67, 10, 154, 12, 70, 79, 244, 122, 113, 74, 67, 182, 251, 242, 246, ++ 54, 4, 100, 34, 79, 240, 0, 9, 189, 248, 44, 112, 150, 251, 242, 246, ++ 154, 70, 200, 70, 44, 224, 64, 70, 105, 70, 251, 247, 148, 253, 1, 154, ++ 0, 44, 204, 191, 176, 68, 198, 235, 8, 8, 106, 67, 3, 212, 210, 19, ++ 1, 50, 82, 16, 4, 224, 82, 66, 210, 19, 1, 50, 82, 16, 82, 66, 0, 155, ++ 146, 5, 146, 13, 107, 67, 3, 212, 219, 19, 1, 51, 91, 16, 4, 224, 91, ++ 66, 219, 19, 1, 51, 91, 16, 91, 66, 155, 5, 155, 13, 67, 234, 130, 35, ++ 9, 241, 1, 9, 74, 248, 4, 59, 31, 250, 137, 249, 185, 69, 208, 209, ++ 189, 232, 252, 135, 0, 0, 127, 181, 0, 35, 4, 70, 29, 70, 30, 70, 6, ++ 224, 81, 248, 8, 12, 1, 51, 54, 24, 81, 248, 4, 12, 45, 24, 12, 49, ++ 147, 66, 245, 219, 83, 8, 0, 46, 180, 191, 79, 240, 255, 49, 1, 33, ++ 3, 251, 1, 102, 237, 24, 150, 251, 242, 240, 1, 169, 149, 251, 242, ++ 245, 251, 247, 70, 253, 2, 153, 1, 154, 105, 67, 106, 67, 201, 19, 1, ++ 49, 210, 19, 73, 16, 1, 50, 161, 245, 128, 97, 82, 16, 64, 242, 255, ++ 19, 154, 66, 168, 191, 26, 70, 153, 66, 184, 191, 11, 70, 10, 73, 32, ++ 70, 138, 66, 184, 191, 10, 70, 139, 66, 184, 191, 11, 70, 146, 5, 146, ++ 13, 155, 5, 173, 248, 12, 32, 155, 13, 1, 33, 3, 170, 173, 248, 14, ++ 48, 253, 247, 12, 248, 127, 189, 0, 191, 0, 254, 255, 255, 115, 181, ++ 130, 234, 226, 115, 163, 235, 226, 115, 5, 70, 36, 32, 88, 67, 68, 246, ++ 32, 99, 144, 251, 243, 240, 0, 4, 100, 35, 144, 251, 243, 240, 0, 42, ++ 216, 191, 64, 66, 14, 70, 105, 70, 251, 247, 3, 253, 1, 155, 0, 43, ++ 5, 219, 26, 3, 210, 26, 210, 19, 1, 50, 82, 16, 5, 224, 24, 74, 90, ++ 67, 210, 19, 1, 50, 82, 16, 82, 66, 0, 155, 210, 4, 210, 12, 0, 43, ++ 5, 219, 28, 3, 228, 26, 228, 19, 1, 52, 100, 16, 5, 224, 16, 76, 92, ++ 67, 228, 19, 1, 52, 100, 16, 100, 66, 228, 4, 228, 12, 1, 46, 8, 209, ++ 40, 70, 64, 246, 212, 17, 249, 247, 90, 255, 40, 70, 64, 246, 214, 17, ++ 9, 224, 2, 46, 10, 209, 40, 70, 64, 246, 213, 17, 249, 247, 79, 255, ++ 40, 70, 64, 246, 215, 17, 34, 70, 249, 247, 73, 255, 124, 189, 1, 240, ++ 255, 255, 45, 233, 248, 67, 15, 70, 21, 70, 64, 242, 218, 97, 72, 242, ++ 128, 2, 4, 70, 152, 70, 157, 248, 32, 96, 157, 248, 36, 144, 250, 247, ++ 162, 250, 123, 30, 255, 34, 155, 178, 32, 70, 64, 242, 66, 97, 250, ++ 247, 168, 250, 79, 246, 255, 115, 157, 66, 1, 208, 1, 61, 173, 178, ++ 43, 70, 32, 70, 79, 244, 200, 97, 79, 246, 255, 114, 250, 247, 154, ++ 250, 32, 70, 64, 242, 65, 97, 79, 246, 255, 114, 67, 70, 250, 247, 146, ++ 250, 0, 46, 12, 191, 1, 39, 2, 39, 10, 37, 32, 70, 38, 177, 64, 242, ++ 83, 65, 79, 244, 0, 66, 2, 224, 64, 242, 63, 97, 1, 34, 19, 70, 250, ++ 247, 128, 250, 1, 32, 212, 243, 167, 246, 32, 70, 64, 242, 68, 97, 249, ++ 247, 243, 254, 1, 61, 1, 208, 56, 66, 230, 208, 54, 185, 32, 70, 1, ++ 33, 74, 70, 189, 232, 248, 67, 252, 247, 224, 188, 189, 232, 248, 131, ++ 56, 181, 39, 73, 4, 70, 250, 247, 130, 249, 192, 178, 40, 40, 140, 191, ++ 0, 35, 1, 35, 132, 248, 13, 4, 132, 248, 110, 4, 132, 248, 17, 52, 32, ++ 70, 32, 73, 250, 247, 115, 249, 8, 40, 32, 70, 28, 216, 30, 73, 0, 34, ++ 250, 247, 131, 249, 128, 178, 0, 34, 196, 248, 160, 1, 27, 73, 32, 70, ++ 250, 247, 123, 249, 26, 73, 196, 248, 164, 1, 32, 70, 250, 247, 94, ++ 249, 24, 73, 5, 70, 32, 70, 250, 247, 89, 249, 128, 178, 64, 234, 5, ++ 69, 196, 248, 168, 81, 19, 224, 19, 73, 0, 34, 250, 247, 102, 249, 128, ++ 178, 196, 248, 160, 1, 17, 73, 0, 34, 32, 70, 250, 247, 94, 249, 15, ++ 73, 196, 248, 164, 1, 32, 70, 250, 247, 65, 249, 196, 248, 168, 1, 32, ++ 70, 12, 73, 250, 247, 59, 249, 132, 248, 172, 1, 56, 189, 0, 191, 14, ++ 165, 5, 0, 237, 173, 5, 0, 255, 168, 5, 0, 60, 169, 5, 0, 196, 173, ++ 5, 0, 40, 169, 5, 0, 241, 169, 5, 0, 16, 174, 5, 0, 124, 169, 5, 0, ++ 180, 168, 5, 0, 208, 248, 228, 48, 211, 248, 36, 6, 8, 177, 215, 247, ++ 216, 190, 112, 71, 248, 181, 144, 248, 160, 42, 208, 248, 232, 48, 1, ++ 42, 4, 70, 211, 248, 32, 49, 50, 209, 3, 240, 1, 3, 131, 240, 1, 7, ++ 27, 177, 131, 107, 24, 105, 3, 240, 248, 255, 32, 70, 250, 247, 31, ++ 249, 32, 70, 251, 247, 252, 253, 50, 38, 0, 37, 32, 70, 64, 242, 177, ++ 81, 249, 247, 89, 254, 0, 240, 16, 0, 128, 178, 0, 177, 1, 53, 1, 62, ++ 246, 178, 0, 46, 241, 209, 100, 35, 93, 67, 64, 246, 196, 19, 157, 66, ++ 32, 70, 148, 191, 0, 37, 1, 37, 251, 247, 2, 254, 32, 70, 250, 247, ++ 11, 249, 47, 185, 163, 107, 24, 105, 3, 240, 210, 255, 0, 224, 0, 37, ++ 40, 70, 248, 189, 45, 233, 240, 71, 87, 26, 126, 28, 31, 250, 134, 249, ++ 79, 234, 137, 3, 79, 246, 252, 113, 134, 176, 4, 70, 25, 64, 208, 248, ++ 228, 0, 65, 246, 13, 50, 252, 247, 40, 248, 5, 70, 0, 40, 116, 208, ++ 16, 35, 79, 240, 96, 10, 223, 248, 232, 128, 141, 232, 8, 4, 4, 170, ++ 2, 35, 32, 70, 0, 33, 205, 248, 8, 128, 250, 247, 190, 251, 189, 248, ++ 16, 32, 189, 248, 18, 48, 146, 5, 155, 5, 155, 13, 146, 13, 67, 234, ++ 130, 34, 194, 70, 0, 35, 8, 224, 85, 248, 35, 16, 1, 240, 127, 97, 17, ++ 67, 69, 248, 35, 16, 1, 51, 155, 178, 187, 66, 244, 221, 32, 35, 79, ++ 244, 160, 120, 141, 232, 8, 1, 223, 248, 152, 128, 42, 70, 51, 70, 32, ++ 70, 7, 33, 205, 248, 8, 128, 250, 247, 164, 251, 212, 248, 228, 0, 65, ++ 246, 33, 49, 251, 247, 246, 255, 79, 234, 73, 9, 79, 246, 254, 113, ++ 212, 248, 228, 0, 9, 234, 1, 1, 65, 246, 36, 50, 251, 247, 221, 255, ++ 5, 70, 80, 179, 16, 35, 79, 240, 98, 12, 141, 232, 8, 16, 32, 70, 1, ++ 35, 0, 33, 13, 241, 22, 2, 205, 248, 8, 160, 250, 247, 117, 251, 0, ++ 35, 5, 224, 189, 248, 22, 32, 37, 248, 19, 32, 1, 51, 155, 178, 187, ++ 66, 247, 221, 16, 35, 79, 244, 224, 126, 141, 232, 8, 64, 32, 70, 7, ++ 33, 42, 70, 51, 70, 205, 248, 8, 128, 250, 247, 107, 251, 212, 248, ++ 228, 0, 65, 246, 49, 49, 251, 247, 189, 255, 6, 176, 189, 232, 240, ++ 135, 153, 30, 3, 0, 15, 36, 3, 0, 240, 181, 0, 36, 135, 176, 5, 70, ++ 5, 148, 21, 78, 32, 39, 1, 148, 33, 33, 1, 35, 40, 70, 5, 170, 1, 52, ++ 0, 151, 2, 150, 250, 247, 77, 251, 64, 44, 241, 209, 0, 151, 35, 70, ++ 0, 39, 40, 70, 28, 33, 12, 74, 1, 151, 2, 150, 250, 247, 65, 251, 60, ++ 70, 32, 35, 0, 147, 4, 245, 128, 99, 1, 52, 1, 147, 7, 33, 1, 35, 40, ++ 70, 5, 170, 228, 178, 2, 150, 250, 247, 50, 251, 128, 44, 239, 209, ++ 7, 176, 240, 189, 15, 36, 3, 0, 236, 103, 4, 0, 20, 75, 112, 181, 4, ++ 70, 30, 104, 0, 37, 7, 224, 18, 75, 20, 33, 1, 251, 5, 49, 32, 70, 254, ++ 247, 36, 254, 1, 53, 181, 66, 245, 209, 0, 37, 6, 224, 13, 75, 20, 33, ++ 1, 251, 5, 49, 254, 247, 25, 254, 1, 53, 11, 75, 32, 70, 27, 104, 157, ++ 66, 243, 211, 255, 247, 172, 255, 212, 248, 228, 48, 32, 70, 211, 248, ++ 36, 22, 189, 232, 112, 64, 255, 247, 183, 186, 0, 191, 80, 77, 4, 0, ++ 236, 76, 4, 0, 96, 73, 4, 0, 84, 77, 4, 0, 45, 233, 240, 79, 15, 104, ++ 133, 176, 56, 70, 76, 104, 142, 104, 21, 70, 251, 247, 100, 251, 130, ++ 70, 48, 70, 251, 247, 96, 251, 129, 70, 32, 70, 251, 247, 92, 251, 15, ++ 250, 137, 249, 15, 250, 128, 248, 200, 69, 184, 191, 200, 70, 15, 250, ++ 136, 249, 185, 241, 30, 15, 9, 220, 201, 241, 30, 9, 4, 250, 9, 240, ++ 251, 247, 87, 251, 131, 70, 6, 250, 9, 240, 8, 224, 169, 241, 30, 9, ++ 68, 250, 9, 240, 251, 247, 77, 251, 131, 70, 70, 250, 9, 240, 251, 247, ++ 72, 251, 15, 250, 138, 250, 0, 251, 11, 251, 15, 250, 136, 248, 10, ++ 241, 16, 0, 128, 69, 4, 220, 200, 235, 0, 0, 75, 250, 0, 240, 6, 224, ++ 111, 240, 15, 3, 202, 235, 3, 3, 152, 68, 11, 250, 8, 240, 127, 66, ++ 202, 241, 30, 10, 7, 250, 10, 247, 79, 234, 96, 11, 0, 47, 204, 191, ++ 95, 68, 203, 235, 7, 7, 8, 177, 151, 251, 240, 240, 168, 96, 64, 16, ++ 64, 67, 192, 241, 128, 64, 251, 247, 28, 251, 171, 104, 64, 0, 1, 147, ++ 2, 144, 1, 171, 147, 232, 3, 0, 3, 170, 251, 247, 193, 250, 3, 155, ++ 54, 27, 43, 96, 48, 70, 251, 247, 255, 250, 195, 7, 1, 213, 1, 48, 128, ++ 178, 0, 178, 192, 241, 30, 3, 158, 64, 10, 40, 2, 221, 10, 56, 4, 65, ++ 2, 224, 192, 241, 10, 0, 132, 64, 0, 46, 79, 234, 100, 3, 204, 191, ++ 246, 24, 195, 235, 6, 6, 28, 185, 79, 244, 128, 99, 107, 96, 6, 224, ++ 150, 251, 244, 244, 4, 245, 128, 16, 251, 247, 234, 250, 104, 96, 5, ++ 176, 189, 232, 240, 143, 48, 181, 133, 176, 20, 70, 1, 170, 29, 70, ++ 255, 247, 100, 255, 1, 155, 35, 96, 2, 155, 43, 96, 5, 176, 48, 189, ++ 56, 181, 13, 70, 176, 248, 246, 16, 208, 248, 228, 64, 250, 247, 134, ++ 251, 8, 185, 164, 248, 180, 84, 56, 189, 56, 181, 12, 70, 176, 248, ++ 246, 16, 208, 248, 228, 80, 250, 247, 122, 251, 16, 185, 149, 248, 56, ++ 52, 35, 128, 56, 189, 240, 181, 0, 35, 161, 176, 208, 248, 228, 80, ++ 173, 248, 126, 48, 28, 147, 29, 147, 30, 147, 181, 248, 70, 52, 4, 70, ++ 83, 177, 111, 240, 0, 67, 197, 248, 80, 52, 197, 248, 76, 52, 149, 248, ++ 201, 52, 0, 43, 69, 209, 140, 224, 13, 241, 126, 1, 255, 247, 214, 255, ++ 29, 170, 30, 171, 32, 70, 28, 169, 251, 247, 73, 252, 64, 246, 244, ++ 17, 32, 70, 249, 247, 94, 252, 16, 244, 128, 79, 20, 191, 64, 242, 123, ++ 65, 64, 242, 166, 65, 32, 70, 249, 247, 84, 252, 192, 5, 192, 13, 255, ++ 40, 134, 191, 160, 245, 128, 112, 128, 178, 0, 245, 128, 112, 128, 8, ++ 189, 248, 126, 48, 192, 241, 131, 0, 128, 178, 28, 169, 152, 66, 56, ++ 191, 24, 70, 14, 201, 251, 247, 116, 254, 148, 249, 24, 113, 149, 248, ++ 201, 52, 199, 25, 135, 66, 168, 191, 7, 70, 70, 16, 127, 16, 197, 248, ++ 80, 100, 197, 248, 76, 116, 67, 177, 20, 47, 168, 191, 20, 39, 20, 46, ++ 168, 191, 20, 38, 1, 224, 20, 38, 55, 70, 148, 248, 56, 49, 83, 177, ++ 148, 248, 35, 49, 183, 66, 184, 191, 62, 70, 158, 66, 168, 191, 30, ++ 70, 132, 248, 35, 97, 55, 224, 234, 24, 210, 248, 92, 20, 1, 170, 153, ++ 80, 4, 51, 88, 43, 247, 209, 32, 70, 64, 242, 167, 65, 249, 247, 11, ++ 252, 0, 35, 192, 178, 1, 170, 153, 88, 69, 26, 173, 178, 189, 66, 2, ++ 221, 237, 27, 105, 24, 153, 80, 4, 51, 16, 43, 243, 209, 5, 171, 23, ++ 173, 83, 248, 4, 43, 129, 26, 137, 178, 177, 66, 3, 221, 137, 27, 138, ++ 24, 67, 248, 4, 44, 171, 66, 243, 209, 7, 35, 25, 147, 32, 35, 27, 147, ++ 22, 35, 24, 147, 1, 171, 23, 147, 32, 70, 79, 244, 80, 115, 23, 169, ++ 26, 147, 254, 247, 158, 252, 33, 176, 240, 189, 0, 0, 112, 181, 208, ++ 248, 228, 48, 1, 57, 211, 248, 32, 54, 66, 34, 2, 251, 1, 51, 94, 136, ++ 24, 75, 2, 34, 83, 248, 33, 80, 64, 246, 135, 17, 4, 70, 249, 247, 213, ++ 251, 48, 70, 79, 244, 240, 97, 251, 247, 159, 251, 182, 251, 240, 242, ++ 46, 12, 32, 70, 246, 178, 64, 246, 134, 17, 249, 247, 199, 251, 173, ++ 178, 32, 70, 50, 70, 79, 244, 24, 97, 249, 247, 192, 251, 32, 70, 42, ++ 70, 64, 246, 129, 17, 249, 247, 186, 251, 32, 70, 50, 70, 64, 246, 132, ++ 17, 249, 247, 180, 251, 32, 70, 64, 246, 133, 17, 42, 70, 189, 232, ++ 112, 64, 249, 247, 172, 187, 172, 71, 4, 0, 112, 181, 0, 35, 4, 70, ++ 14, 70, 79, 244, 128, 98, 64, 242, 49, 97, 208, 248, 228, 80, 249, 247, ++ 24, 255, 0, 35, 32, 70, 64, 242, 49, 97, 79, 244, 0, 114, 249, 247, ++ 16, 255, 79, 244, 128, 114, 19, 70, 32, 70, 64, 242, 49, 97, 249, 247, ++ 8, 255, 32, 70, 49, 70, 255, 247, 162, 255, 255, 34, 90, 35, 32, 70, ++ 64, 242, 42, 97, 249, 247, 253, 254, 0, 34, 32, 70, 64, 246, 72, 1, ++ 249, 247, 125, 251, 181, 249, 104, 37, 1, 46, 34, 234, 226, 114, 1, ++ 208, 11, 46, 3, 209, 181, 248, 110, 53, 24, 4, 4, 213, 181, 248, 106, ++ 53, 25, 4, 72, 191, 0, 35, 165, 248, 108, 53, 0, 33, 32, 70, 18, 178, ++ 252, 247, 145, 252, 1, 33, 181, 249, 108, 37, 32, 70, 252, 247, 139, ++ 252, 32, 70, 79, 244, 137, 97, 79, 244, 64, 114, 79, 244, 0, 115, 189, ++ 232, 112, 64, 249, 247, 206, 190, 240, 181, 40, 78, 143, 176, 109, 70, ++ 4, 70, 15, 70, 15, 206, 15, 197, 15, 206, 15, 197, 15, 206, 15, 197, ++ 150, 232, 3, 0, 212, 248, 228, 48, 1, 63, 211, 248, 32, 54, 66, 34, ++ 2, 251, 7, 51, 133, 232, 3, 0, 94, 136, 14, 171, 3, 235, 135, 7, 87, ++ 248, 56, 92, 32, 70, 171, 178, 64, 246, 173, 17, 79, 246, 255, 114, ++ 249, 247, 168, 254, 32, 70, 43, 12, 64, 246, 174, 17, 64, 242, 255, ++ 50, 249, 247, 160, 254, 0, 35, 32, 70, 79, 244, 128, 66, 64, 246, 174, ++ 17, 249, 247, 152, 254, 49, 70, 79, 244, 160, 96, 251, 247, 232, 250, ++ 79, 244, 160, 99, 179, 251, 240, 243, 64, 246, 177, 17, 32, 70, 65, ++ 246, 255, 114, 249, 247, 136, 254, 79, 244, 128, 98, 32, 70, 64, 246, ++ 172, 17, 19, 70, 15, 176, 189, 232, 240, 64, 249, 247, 125, 190, 0, ++ 191, 72, 22, 4, 0, 240, 181, 4, 70, 145, 176, 13, 70, 255, 247, 166, ++ 255, 32, 70, 41, 70, 251, 247, 204, 255, 0, 34, 32, 70, 64, 246, 207, ++ 17, 249, 247, 240, 250, 104, 75, 1, 170, 3, 241, 32, 6, 24, 104, 89, ++ 104, 21, 70, 3, 197, 8, 51, 179, 66, 42, 70, 247, 209, 24, 104, 155, ++ 136, 40, 96, 171, 128, 1, 171, 8, 38, 16, 37, 3, 39, 11, 147, 32, 70, ++ 19, 35, 11, 169, 12, 147, 13, 150, 15, 149, 14, 151, 254, 247, 133, ++ 251, 60, 35, 173, 248, 4, 48, 1, 35, 173, 248, 6, 48, 32, 70, 29, 35, ++ 11, 169, 14, 147, 173, 248, 8, 96, 12, 151, 254, 247, 118, 251, 79, ++ 244, 128, 114, 32, 70, 19, 70, 64, 242, 59, 81, 249, 247, 53, 254, 79, ++ 244, 0, 114, 32, 70, 19, 70, 64, 242, 59, 81, 249, 247, 45, 254, 79, ++ 244, 128, 98, 32, 70, 19, 70, 64, 242, 59, 81, 249, 247, 37, 254, 4, ++ 34, 32, 70, 19, 70, 64, 242, 177, 65, 249, 247, 30, 254, 1, 34, 32, ++ 70, 25, 33, 19, 70, 249, 247, 221, 253, 2, 34, 32, 70, 155, 33, 19, ++ 70, 249, 247, 215, 253, 1, 34, 32, 70, 28, 33, 19, 70, 249, 247, 209, ++ 253, 79, 244, 128, 66, 32, 70, 23, 33, 19, 70, 249, 247, 202, 253, 1, ++ 34, 32, 70, 154, 33, 19, 70, 249, 247, 196, 253, 79, 244, 128, 66, 32, ++ 70, 61, 33, 19, 70, 249, 247, 189, 253, 32, 34, 32, 70, 19, 70, 159, ++ 33, 249, 247, 183, 253, 62, 33, 32, 70, 42, 70, 0, 35, 249, 247, 177, ++ 253, 2, 34, 32, 70, 159, 33, 19, 70, 249, 247, 171, 253, 32, 34, 32, ++ 70, 62, 33, 19, 70, 249, 247, 165, 253, 4, 34, 32, 70, 159, 33, 19, ++ 70, 249, 247, 159, 253, 79, 244, 128, 82, 32, 70, 38, 33, 19, 70, 249, ++ 247, 152, 253, 4, 34, 32, 70, 156, 33, 19, 70, 249, 247, 146, 253, 4, ++ 34, 32, 70, 19, 70, 64, 242, 177, 65, 249, 247, 198, 253, 64, 34, 32, ++ 70, 19, 70, 64, 246, 165, 17, 249, 247, 191, 253, 32, 70, 64, 242, 99, ++ 65, 79, 244, 127, 66, 79, 244, 228, 67, 249, 247, 182, 253, 7, 33, 1, ++ 34, 2, 35, 32, 70, 254, 247, 208, 254, 32, 70, 251, 247, 223, 255, 32, ++ 70, 48, 33, 63, 34, 51, 70, 249, 247, 108, 253, 32, 70, 126, 34, 43, ++ 70, 49, 33, 249, 247, 102, 253, 57, 33, 32, 70, 15, 34, 0, 35, 249, ++ 247, 96, 253, 17, 176, 240, 189, 0, 191, 128, 22, 4, 0, 16, 181, 64, ++ 242, 74, 65, 79, 244, 128, 114, 4, 70, 249, 247, 128, 253, 32, 70, 64, ++ 242, 74, 65, 79, 246, 255, 98, 189, 232, 16, 64, 249, 247, 106, 189, ++ 131, 107, 147, 248, 44, 33, 139, 30, 74, 177, 1, 43, 14, 217, 105, 177, ++ 161, 241, 4, 12, 220, 241, 0, 0, 64, 235, 12, 0, 112, 71, 1, 43, 6, ++ 217, 209, 241, 1, 0, 56, 191, 0, 32, 112, 71, 1, 32, 112, 71, 1, 32, ++ 112, 71, 16, 181, 4, 70, 4, 41, 36, 216, 223, 232, 1, 240, 30, 35, 15, ++ 3, 3, 0, 79, 244, 48, 97, 2, 34, 0, 35, 249, 247, 92, 253, 32, 70, 64, ++ 246, 7, 49, 1, 34, 0, 35, 10, 224, 2, 34, 79, 244, 48, 97, 19, 70, 249, ++ 247, 80, 253, 1, 34, 32, 70, 64, 246, 7, 49, 19, 70, 249, 247, 73, 253, ++ 0, 32, 16, 189, 79, 244, 48, 97, 2, 34, 0, 35, 239, 231, 111, 240, 2, ++ 0, 16, 189, 112, 181, 4, 70, 251, 247, 176, 249, 163, 107, 5, 70, 147, ++ 248, 44, 49, 155, 179, 0, 35, 196, 248, 104, 49, 128, 248, 127, 51, ++ 79, 244, 122, 115, 192, 248, 84, 51, 100, 35, 192, 248, 92, 51, 3, 35, ++ 192, 248, 88, 51, 20, 35, 192, 248, 96, 51, 55, 35, 128, 248, 120, 51, ++ 128, 248, 121, 51, 97, 35, 128, 248, 118, 51, 128, 248, 119, 51, 128, ++ 248, 116, 51, 128, 248, 117, 51, 64, 246, 87, 33, 32, 70, 255, 34, 249, ++ 247, 16, 253, 149, 248, 119, 51, 32, 70, 27, 2, 64, 246, 87, 33, 79, ++ 244, 127, 66, 249, 247, 6, 253, 163, 107, 27, 106, 197, 248, 104, 51, ++ 32, 70, 1, 34, 0, 35, 79, 244, 48, 97, 249, 247, 251, 252, 32, 70, 2, ++ 34, 0, 35, 79, 244, 48, 97, 249, 247, 244, 252, 32, 70, 4, 34, 0, 35, ++ 79, 244, 48, 97, 249, 247, 237, 252, 32, 70, 8, 34, 0, 35, 79, 244, ++ 48, 97, 249, 247, 230, 252, 240, 34, 32, 70, 19, 70, 79, 244, 48, 97, ++ 249, 247, 223, 252, 79, 244, 112, 98, 32, 70, 19, 70, 79, 244, 48, 97, ++ 249, 247, 215, 252, 32, 70, 0, 35, 79, 244, 48, 97, 79, 244, 128, 82, ++ 249, 247, 207, 252, 32, 70, 1, 34, 0, 35, 64, 246, 7, 49, 249, 247, ++ 200, 252, 32, 70, 6, 34, 4, 35, 64, 246, 7, 49, 249, 247, 193, 252, ++ 32, 70, 56, 34, 8, 35, 64, 246, 7, 49, 249, 247, 186, 252, 32, 70, 0, ++ 35, 64, 246, 7, 49, 79, 244, 224, 114, 249, 247, 178, 252, 32, 70, 48, ++ 34, 16, 35, 64, 246, 11, 49, 249, 247, 171, 252, 64, 34, 32, 70, 19, ++ 70, 64, 246, 11, 49, 249, 247, 164, 252, 32, 70, 64, 246, 11, 49, 79, ++ 244, 240, 98, 79, 244, 128, 99, 249, 247, 155, 252, 32, 70, 64, 246, ++ 11, 49, 79, 244, 240, 66, 79, 244, 0, 83, 249, 247, 146, 252, 32, 70, ++ 64, 246, 12, 49, 79, 246, 255, 114, 79, 244, 128, 83, 249, 247, 137, ++ 252, 32, 70, 64, 246, 13, 49, 79, 246, 255, 114, 79, 244, 80, 67, 249, ++ 247, 128, 252, 32, 70, 64, 246, 14, 49, 79, 246, 255, 114, 79, 244, ++ 120, 67, 249, 247, 119, 252, 32, 70, 16, 35, 64, 246, 15, 49, 79, 246, ++ 255, 114, 249, 247, 111, 252, 32, 70, 79, 244, 49, 97, 79, 246, 255, ++ 114, 79, 244, 120, 67, 249, 247, 102, 252, 32, 70, 64, 246, 17, 49, ++ 79, 246, 255, 114, 79, 244, 125, 67, 249, 247, 93, 252, 32, 70, 15, ++ 34, 0, 35, 64, 246, 18, 49, 249, 247, 86, 252, 32, 70, 240, 34, 0, 35, ++ 64, 246, 18, 49, 249, 247, 79, 252, 32, 70, 0, 35, 64, 246, 18, 49, ++ 79, 244, 112, 98, 249, 247, 71, 252, 32, 70, 15, 34, 0, 35, 64, 246, ++ 19, 49, 249, 247, 64, 252, 32, 70, 240, 34, 0, 35, 64, 246, 19, 49, ++ 249, 247, 57, 252, 32, 70, 0, 35, 64, 246, 19, 49, 79, 244, 112, 98, ++ 249, 247, 49, 252, 32, 70, 15, 34, 0, 35, 64, 246, 20, 49, 249, 247, ++ 42, 252, 32, 70, 240, 34, 0, 35, 64, 246, 20, 49, 249, 247, 35, 252, ++ 32, 70, 0, 35, 64, 246, 20, 49, 79, 244, 112, 98, 249, 247, 27, 252, ++ 15, 34, 32, 70, 0, 35, 64, 246, 21, 49, 249, 247, 20, 252, 32, 70, 240, ++ 34, 0, 35, 64, 246, 21, 49, 249, 247, 13, 252, 32, 70, 0, 35, 64, 246, ++ 21, 49, 79, 244, 112, 98, 249, 247, 5, 252, 32, 70, 3, 34, 1, 35, 64, ++ 246, 22, 49, 249, 247, 254, 251, 32, 70, 12, 34, 0, 35, 64, 246, 22, ++ 49, 249, 247, 247, 251, 32, 70, 48, 34, 16, 35, 64, 246, 22, 49, 249, ++ 247, 240, 251, 32, 70, 192, 34, 64, 35, 64, 246, 22, 49, 249, 247, 233, ++ 251, 32, 70, 0, 35, 64, 246, 22, 49, 79, 244, 64, 114, 249, 247, 225, ++ 251, 32, 70, 64, 246, 22, 49, 79, 244, 64, 98, 79, 244, 128, 99, 249, ++ 247, 216, 251, 32, 70, 3, 34, 0, 35, 64, 246, 23, 49, 249, 247, 209, ++ 251, 32, 70, 12, 34, 64, 246, 23, 49, 79, 246, 252, 115, 249, 247, 201, ++ 251, 32, 70, 48, 34, 64, 246, 23, 49, 79, 246, 240, 115, 249, 247, 193, ++ 251, 32, 70, 192, 34, 0, 35, 64, 246, 23, 49, 249, 247, 186, 251, 32, ++ 70, 64, 246, 23, 49, 79, 244, 64, 114, 79, 244, 127, 67, 249, 247, 177, ++ 251, 32, 70, 64, 246, 23, 49, 79, 244, 64, 98, 79, 244, 124, 67, 249, ++ 247, 168, 251, 32, 70, 1, 34, 0, 35, 64, 246, 6, 49, 249, 247, 161, ++ 251, 31, 34, 32, 70, 19, 70, 64, 246, 5, 49, 249, 247, 154, 251, 79, ++ 246, 255, 114, 32, 70, 19, 70, 64, 246, 4, 49, 249, 247, 146, 251, 79, ++ 246, 255, 114, 32, 70, 19, 70, 64, 246, 8, 49, 249, 247, 138, 251, 32, ++ 70, 64, 246, 9, 49, 79, 246, 255, 114, 71, 246, 255, 115, 249, 247, ++ 129, 251, 32, 70, 8, 35, 64, 246, 10, 49, 79, 246, 255, 114, 249, 247, ++ 121, 251, 32, 70, 63, 35, 64, 246, 2, 49, 79, 246, 255, 114, 249, 247, ++ 113, 251, 32, 70, 255, 35, 64, 246, 3, 49, 79, 246, 255, 114, 249, 247, ++ 105, 251, 15, 34, 32, 70, 19, 70, 64, 246, 1, 49, 249, 247, 98, 251, ++ 240, 34, 32, 70, 19, 70, 64, 246, 1, 49, 249, 247, 91, 251, 1, 34, 32, ++ 70, 79, 244, 48, 97, 19, 70, 189, 232, 112, 64, 249, 247, 82, 187, 56, ++ 181, 54, 33, 4, 70, 0, 35, 79, 244, 224, 66, 208, 248, 228, 80, 249, ++ 247, 13, 251, 54, 33, 32, 70, 79, 244, 224, 98, 79, 244, 128, 99, 249, ++ 247, 5, 251, 54, 33, 112, 34, 64, 35, 32, 70, 249, 247, 255, 250, 54, ++ 33, 7, 34, 0, 35, 32, 70, 249, 247, 249, 250, 53, 33, 0, 35, 32, 70, ++ 79, 244, 224, 66, 249, 247, 242, 250, 79, 244, 224, 98, 53, 33, 19, ++ 70, 32, 70, 249, 247, 235, 250, 53, 33, 0, 35, 32, 70, 79, 244, 0, 66, ++ 249, 247, 228, 250, 53, 33, 126, 34, 32, 35, 32, 70, 249, 247, 222, ++ 250, 58, 33, 30, 34, 16, 35, 32, 70, 249, 247, 216, 250, 58, 33, 0, ++ 35, 32, 70, 1, 34, 249, 247, 210, 250, 1, 34, 32, 70, 0, 35, 64, 242, ++ 10, 81, 249, 247, 6, 251, 15, 34, 4, 35, 32, 70, 64, 242, 113, 65, 249, ++ 247, 255, 250, 240, 34, 0, 35, 32, 70, 64, 242, 113, 65, 249, 247, 248, ++ 250, 127, 34, 65, 35, 32, 70, 64, 242, 31, 65, 249, 247, 241, 250, 255, ++ 34, 12, 35, 32, 70, 79, 244, 132, 97, 249, 247, 234, 250, 255, 34, 0, ++ 35, 32, 70, 79, 244, 188, 97, 249, 247, 227, 250, 32, 70, 79, 244, 188, ++ 97, 79, 244, 127, 66, 79, 244, 64, 83, 249, 247, 218, 250, 255, 34, ++ 39, 35, 32, 70, 64, 242, 225, 81, 249, 247, 211, 250, 32, 70, 64, 242, ++ 225, 81, 79, 244, 127, 66, 79, 244, 28, 83, 249, 247, 202, 250, 255, ++ 34, 39, 35, 32, 70, 64, 242, 226, 81, 249, 247, 195, 250, 32, 70, 64, ++ 242, 226, 81, 79, 244, 127, 66, 79, 244, 240, 83, 249, 247, 186, 250, ++ 255, 34, 30, 35, 32, 70, 64, 242, 227, 81, 249, 247, 179, 250, 32, 70, ++ 64, 242, 227, 81, 79, 244, 127, 66, 79, 244, 240, 83, 249, 247, 170, ++ 250, 32, 70, 64, 242, 228, 81, 255, 34, 30, 35, 249, 247, 163, 250, ++ 255, 34, 21, 35, 32, 70, 64, 246, 150, 33, 249, 247, 156, 250, 32, 70, ++ 64, 246, 150, 33, 79, 244, 127, 66, 79, 244, 64, 99, 249, 247, 147, ++ 250, 255, 34, 0, 35, 32, 70, 64, 246, 151, 33, 249, 247, 140, 250, 127, ++ 34, 0, 35, 32, 70, 64, 242, 229, 81, 249, 247, 133, 250, 32, 70, 64, ++ 242, 229, 81, 79, 244, 126, 82, 79, 244, 240, 99, 249, 247, 124, 250, ++ 127, 34, 21, 35, 32, 70, 64, 242, 230, 81, 249, 247, 117, 250, 0, 35, ++ 32, 70, 64, 242, 230, 81, 79, 244, 126, 82, 249, 247, 109, 250, 127, ++ 34, 0, 35, 32, 70, 64, 242, 231, 81, 249, 247, 102, 250, 32, 70, 64, ++ 242, 231, 81, 79, 244, 126, 82, 79, 244, 24, 99, 249, 247, 93, 250, ++ 127, 34, 0, 35, 32, 70, 79, 244, 189, 97, 249, 247, 86, 250, 0, 35, ++ 32, 70, 79, 244, 189, 97, 79, 244, 126, 82, 249, 247, 78, 250, 127, ++ 34, 0, 35, 32, 70, 64, 242, 233, 81, 249, 247, 71, 250, 32, 70, 64, ++ 242, 233, 81, 79, 244, 126, 82, 79, 244, 16, 99, 249, 247, 62, 250, ++ 127, 34, 22, 35, 32, 70, 64, 246, 145, 33, 249, 247, 55, 250, 32, 70, ++ 64, 246, 145, 33, 79, 244, 126, 82, 79, 244, 72, 99, 249, 247, 46, 250, ++ 255, 34, 54, 35, 32, 70, 64, 242, 250, 81, 249, 247, 39, 250, 255, 34, ++ 0, 35, 32, 70, 64, 242, 245, 81, 249, 247, 32, 250, 32, 70, 64, 242, ++ 245, 81, 79, 244, 127, 66, 79, 244, 52, 83, 249, 247, 23, 250, 255, ++ 34, 36, 35, 32, 70, 64, 242, 246, 81, 249, 247, 16, 250, 32, 70, 64, ++ 242, 246, 81, 79, 244, 127, 66, 79, 244, 16, 83, 249, 247, 7, 250, 255, ++ 34, 36, 35, 32, 70, 64, 242, 247, 81, 249, 247, 0, 250, 32, 70, 64, ++ 242, 247, 81, 79, 244, 127, 66, 79, 244, 16, 83, 249, 247, 247, 249, ++ 255, 34, 36, 35, 32, 70, 79, 244, 191, 97, 249, 247, 240, 249, 32, 70, ++ 79, 244, 191, 97, 79, 244, 127, 66, 79, 244, 16, 83, 249, 247, 231, ++ 249, 255, 34, 36, 35, 32, 70, 64, 242, 249, 81, 249, 247, 224, 249, ++ 255, 34, 27, 35, 32, 70, 64, 246, 143, 33, 249, 247, 217, 249, 32, 70, ++ 64, 246, 143, 33, 79, 244, 127, 66, 79, 244, 144, 83, 249, 247, 208, ++ 249, 255, 34, 6, 35, 32, 70, 79, 244, 41, 97, 249, 247, 201, 249, 32, ++ 70, 64, 242, 255, 81, 79, 244, 126, 82, 0, 35, 249, 247, 193, 249, 127, ++ 34, 32, 70, 40, 35, 64, 242, 209, 81, 249, 247, 186, 249, 32, 70, 64, ++ 242, 209, 81, 79, 244, 126, 82, 79, 244, 136, 83, 249, 247, 177, 249, ++ 127, 34, 0, 35, 32, 70, 64, 242, 210, 81, 249, 247, 170, 249, 0, 35, ++ 32, 70, 64, 242, 210, 81, 79, 244, 126, 82, 249, 247, 162, 249, 127, ++ 34, 0, 35, 32, 70, 64, 242, 211, 81, 249, 247, 155, 249, 0, 35, 32, ++ 70, 64, 242, 211, 81, 79, 244, 126, 82, 249, 247, 147, 249, 127, 34, ++ 0, 35, 32, 70, 64, 242, 212, 81, 249, 247, 140, 249, 0, 35, 32, 70, ++ 64, 242, 212, 81, 79, 244, 126, 82, 249, 247, 132, 249, 127, 34, 5, ++ 35, 32, 70, 64, 246, 148, 33, 249, 247, 125, 249, 32, 70, 64, 246, 148, ++ 33, 79, 244, 126, 82, 79, 244, 160, 99, 249, 247, 116, 249, 127, 34, ++ 18, 35, 32, 70, 64, 246, 149, 33, 249, 247, 109, 249, 32, 70, 64, 242, ++ 249, 81, 79, 244, 127, 66, 79, 244, 64, 83, 249, 247, 100, 249, 32, ++ 70, 64, 242, 237, 81, 79, 244, 127, 66, 79, 244, 122, 67, 249, 247, ++ 91, 249, 32, 70, 64, 242, 228, 81, 79, 244, 112, 98, 79, 244, 128, 115, ++ 249, 247, 82, 249, 24, 34, 16, 35, 32, 70, 64, 242, 101, 81, 249, 247, ++ 75, 249, 7, 34, 19, 70, 32, 70, 48, 33, 249, 247, 69, 249, 32, 70, 64, ++ 242, 113, 65, 79, 244, 127, 66, 79, 244, 150, 67, 249, 247, 60, 249, ++ 63, 34, 32, 70, 64, 242, 234, 81, 79, 246, 250, 115, 249, 247, 52, 249, ++ 32, 70, 64, 242, 234, 81, 79, 244, 127, 66, 79, 244, 119, 67, 249, 247, ++ 43, 249, 255, 34, 0, 35, 32, 70, 64, 242, 55, 65, 249, 247, 36, 249, ++ 32, 70, 64, 242, 41, 65, 79, 244, 248, 66, 79, 244, 144, 67, 249, 247, ++ 27, 249, 255, 34, 81, 35, 32, 70, 64, 242, 114, 65, 249, 247, 20, 249, ++ 32, 70, 64, 242, 66, 81, 79, 244, 127, 66, 79, 244, 168, 67, 249, 247, ++ 11, 249, 255, 34, 23, 35, 32, 70, 64, 242, 52, 81, 249, 247, 4, 249, ++ 255, 34, 0, 35, 32, 70, 64, 242, 213, 81, 249, 247, 253, 248, 32, 70, ++ 79, 244, 170, 97, 64, 242, 255, 50, 64, 242, 105, 19, 249, 247, 244, ++ 248, 64, 35, 32, 70, 64, 246, 82, 33, 79, 244, 255, 82, 249, 247, 236, ++ 248, 255, 34, 2, 35, 32, 70, 64, 246, 83, 33, 249, 247, 229, 248, 15, ++ 34, 1, 35, 32, 70, 64, 246, 88, 33, 249, 247, 222, 248, 255, 34, 46, ++ 35, 32, 70, 64, 242, 66, 81, 249, 247, 215, 248, 0, 35, 32, 70, 64, ++ 242, 65, 65, 79, 244, 127, 66, 249, 247, 207, 248, 255, 34, 32, 70, ++ 64, 242, 66, 65, 98, 35, 249, 247, 200, 248, 32, 70, 64, 242, 213, 81, ++ 79, 244, 127, 66, 79, 244, 190, 67, 249, 247, 191, 248, 32, 70, 64, ++ 246, 40, 33, 79, 244, 127, 66, 79, 244, 190, 67, 249, 247, 182, 248, ++ 32, 70, 64, 246, 40, 33, 255, 34, 95, 35, 249, 247, 175, 248, 32, 70, ++ 64, 246, 41, 33, 79, 244, 127, 66, 79, 244, 190, 67, 249, 247, 166, ++ 248, 32, 70, 64, 246, 41, 33, 255, 34, 95, 35, 249, 247, 159, 248, 32, ++ 70, 64, 246, 85, 33, 255, 34, 94, 35, 249, 247, 152, 248, 149, 248, ++ 40, 54, 32, 70, 64, 246, 79, 33, 255, 34, 211, 177, 97, 35, 249, 247, ++ 142, 248, 79, 244, 128, 114, 19, 70, 32, 70, 64, 246, 179, 17, 249, ++ 247, 134, 248, 32, 70, 64, 242, 85, 97, 79, 244, 112, 66, 79, 244, 160, ++ 67, 249, 247, 125, 248, 32, 70, 64, 242, 85, 97, 64, 246, 255, 114, ++ 0, 35, 0, 224, 91, 35, 249, 247, 115, 248, 212, 248, 228, 48, 32, 70, ++ 147, 248, 0, 60, 11, 177, 104, 33, 0, 224, 97, 33, 10, 70, 251, 247, ++ 235, 249, 32, 70, 251, 247, 14, 248, 32, 70, 255, 247, 34, 251, 32, ++ 70, 189, 232, 56, 64, 251, 247, 142, 186, 112, 181, 5, 70, 250, 247, ++ 205, 252, 171, 107, 4, 70, 79, 244, 135, 113, 24, 105, 2, 240, 85, 254, ++ 212, 248, 100, 35, 196, 248, 100, 3, 149, 248, 229, 26, 213, 248, 104, ++ 49, 41, 179, 170, 107, 17, 106, 196, 248, 104, 19, 217, 7, 64, 241, ++ 251, 128, 35, 240, 1, 3, 16, 105, 0, 33, 197, 248, 104, 49, 2, 240, ++ 100, 254, 148, 248, 118, 51, 132, 248, 116, 51, 148, 248, 119, 51, 132, ++ 248, 117, 51, 171, 107, 24, 105, 2, 240, 58, 254, 148, 248, 118, 51, ++ 40, 70, 64, 246, 87, 33, 255, 34, 249, 247, 37, 248, 148, 248, 119, ++ 51, 202, 224, 130, 26, 219, 7, 146, 178, 4, 212, 212, 248, 84, 51, 154, ++ 66, 4, 219, 7, 224, 212, 248, 92, 51, 154, 66, 3, 221, 171, 107, 27, ++ 106, 196, 248, 104, 51, 213, 248, 104, 49, 222, 7, 8, 213, 212, 248, ++ 92, 51, 154, 66, 1, 221, 1, 35, 0, 224, 0, 35, 132, 248, 127, 51, 148, ++ 249, 127, 51, 83, 177, 148, 248, 116, 51, 3, 59, 132, 248, 116, 51, ++ 148, 248, 117, 51, 3, 59, 132, 248, 117, 51, 3, 224, 213, 248, 104, ++ 49, 216, 7, 42, 213, 149, 248, 230, 58, 187, 177, 148, 248, 116, 35, ++ 195, 241, 10, 3, 219, 178, 154, 66, 56, 191, 132, 248, 116, 51, 132, ++ 248, 125, 51, 149, 248, 230, 58, 148, 248, 117, 35, 195, 241, 10, 3, ++ 219, 178, 154, 66, 132, 248, 126, 51, 56, 191, 132, 248, 117, 51, 148, ++ 248, 120, 51, 148, 248, 116, 35, 154, 66, 152, 191, 132, 248, 116, 51, ++ 148, 248, 117, 35, 148, 248, 121, 51, 154, 66, 152, 191, 132, 248, 117, ++ 51, 171, 107, 26, 106, 212, 248, 104, 51, 211, 26, 213, 248, 104, 33, ++ 209, 7, 13, 212, 212, 248, 88, 19, 139, 66, 63, 219, 66, 240, 1, 2, ++ 1, 33, 197, 248, 104, 33, 132, 248, 127, 19, 171, 107, 24, 105, 47, ++ 224, 212, 248, 96, 35, 147, 66, 49, 219, 0, 35, 132, 248, 127, 51, 148, ++ 248, 116, 51, 148, 248, 118, 35, 3, 51, 219, 178, 148, 248, 117, 19, ++ 147, 66, 132, 248, 116, 51, 40, 191, 132, 248, 116, 35, 148, 248, 119, ++ 51, 3, 49, 201, 178, 153, 66, 132, 248, 117, 19, 148, 248, 116, 19, ++ 40, 191, 132, 248, 117, 51, 145, 66, 3, 210, 148, 248, 117, 35, 154, ++ 66, 10, 211, 213, 248, 104, 49, 0, 33, 35, 240, 1, 3, 197, 248, 104, ++ 49, 171, 107, 24, 105, 2, 240, 169, 253, 171, 107, 27, 106, 196, 248, ++ 104, 51, 40, 70, 64, 246, 87, 33, 148, 248, 116, 99, 248, 247, 238, ++ 251, 192, 178, 134, 66, 10, 209, 40, 70, 64, 246, 87, 33, 148, 248, ++ 117, 99, 248, 247, 228, 251, 0, 10, 128, 178, 134, 66, 30, 208, 171, ++ 107, 24, 105, 2, 240, 110, 253, 148, 248, 116, 51, 40, 70, 64, 246, ++ 87, 33, 255, 34, 248, 247, 89, 255, 148, 248, 117, 51, 27, 2, 40, 70, ++ 64, 246, 87, 33, 79, 244, 127, 66, 248, 247, 79, 255, 40, 70, 251, 247, ++ 126, 249, 171, 107, 24, 105, 189, 232, 112, 64, 2, 240, 86, 189, 112, ++ 189, 56, 181, 12, 70, 0, 33, 5, 70, 254, 247, 48, 250, 40, 70, 33, 70, ++ 189, 232, 56, 64, 253, 247, 90, 190, 112, 181, 208, 248, 228, 80, 0, ++ 38, 4, 70, 149, 248, 233, 20, 133, 248, 202, 100, 255, 247, 233, 255, ++ 32, 70, 181, 248, 234, 20, 254, 247, 26, 250, 32, 70, 181, 248, 238, ++ 36, 64, 246, 130, 1, 248, 247, 168, 251, 32, 70, 181, 248, 236, 36, ++ 64, 246, 7, 1, 248, 247, 161, 251, 181, 248, 246, 36, 32, 70, 64, 242, ++ 49, 97, 248, 247, 154, 251, 32, 70, 149, 248, 232, 20, 253, 247, 221, ++ 252, 32, 70, 181, 248, 204, 36, 64, 242, 76, 65, 248, 247, 142, 251, ++ 32, 70, 181, 248, 206, 36, 64, 242, 77, 65, 248, 247, 135, 251, 32, ++ 70, 181, 248, 208, 36, 79, 244, 150, 97, 248, 247, 128, 251, 32, 70, ++ 181, 248, 210, 36, 64, 242, 177, 65, 248, 247, 121, 251, 32, 70, 181, ++ 248, 212, 36, 64, 242, 249, 65, 248, 247, 114, 251, 32, 70, 181, 248, ++ 214, 36, 64, 242, 250, 65, 248, 247, 107, 251, 32, 70, 181, 248, 216, ++ 36, 64, 246, 56, 17, 248, 247, 100, 251, 32, 70, 181, 248, 218, 36, ++ 64, 246, 57, 17, 248, 247, 93, 251, 32, 70, 181, 248, 220, 36, 64, 242, ++ 61, 81, 248, 247, 86, 251, 32, 70, 181, 248, 222, 36, 64, 242, 60, 81, ++ 248, 247, 79, 251, 32, 70, 181, 248, 224, 36, 64, 242, 113, 81, 248, ++ 247, 72, 251, 32, 70, 181, 248, 226, 36, 79, 244, 174, 97, 248, 247, ++ 65, 251, 32, 70, 181, 248, 228, 36, 64, 242, 115, 81, 248, 247, 58, ++ 251, 32, 70, 181, 248, 230, 36, 64, 242, 114, 81, 248, 247, 51, 251, ++ 32, 70, 181, 248, 250, 36, 64, 246, 211, 17, 248, 247, 44, 251, 32, ++ 70, 181, 248, 248, 36, 64, 242, 218, 97, 248, 247, 37, 251, 32, 70, ++ 181, 248, 240, 36, 64, 246, 172, 17, 248, 247, 30, 251, 32, 70, 181, ++ 248, 242, 36, 64, 246, 177, 17, 248, 247, 23, 251, 32, 70, 181, 248, ++ 244, 36, 64, 246, 121, 17, 248, 247, 16, 251, 32, 70, 181, 248, 252, ++ 36, 64, 246, 165, 17, 248, 247, 9, 251, 32, 70, 49, 70, 50, 70, 51, ++ 70, 189, 232, 112, 64, 251, 247, 69, 187, 48, 181, 6, 34, 133, 176, ++ 19, 70, 129, 33, 4, 70, 208, 248, 228, 80, 248, 247, 54, 254, 3, 34, ++ 19, 70, 32, 70, 62, 33, 248, 247, 48, 254, 213, 248, 84, 21, 32, 70, ++ 255, 247, 33, 255, 148, 248, 17, 20, 3, 35, 25, 177, 0, 33, 141, 232, ++ 10, 0, 2, 224, 4, 34, 0, 145, 1, 146, 2, 147, 32, 70, 10, 70, 11, 70, ++ 3, 145, 250, 247, 206, 254, 32, 70, 1, 33, 5, 176, 189, 232, 48, 64, ++ 250, 247, 30, 191, 56, 181, 208, 248, 228, 64, 1, 33, 180, 249, 108, ++ 37, 5, 70, 251, 247, 246, 251, 0, 35, 132, 248, 202, 52, 40, 70, 180, ++ 248, 66, 37, 64, 242, 116, 81, 248, 247, 192, 250, 40, 70, 180, 248, ++ 68, 37, 64, 242, 117, 81, 248, 247, 185, 250, 40, 70, 180, 248, 70, ++ 37, 64, 246, 165, 17, 248, 247, 178, 250, 40, 70, 180, 248, 204, 36, ++ 64, 242, 76, 65, 248, 247, 171, 250, 40, 70, 180, 248, 206, 36, 64, ++ 242, 77, 65, 248, 247, 164, 250, 40, 70, 180, 248, 208, 36, 79, 244, ++ 150, 97, 248, 247, 157, 250, 40, 70, 180, 248, 210, 36, 64, 242, 177, ++ 65, 248, 247, 150, 250, 40, 70, 180, 248, 212, 36, 64, 242, 249, 65, ++ 248, 247, 143, 250, 40, 70, 180, 248, 214, 36, 64, 242, 250, 65, 248, ++ 247, 136, 250, 40, 70, 180, 248, 216, 36, 64, 246, 56, 17, 248, 247, ++ 129, 250, 40, 70, 180, 248, 218, 36, 64, 246, 57, 17, 248, 247, 122, ++ 250, 40, 70, 180, 248, 220, 36, 64, 242, 61, 81, 248, 247, 115, 250, ++ 40, 70, 180, 248, 222, 36, 64, 242, 60, 81, 248, 247, 108, 250, 40, ++ 70, 180, 248, 224, 36, 64, 242, 113, 81, 248, 247, 101, 250, 40, 70, ++ 180, 248, 226, 36, 79, 244, 174, 97, 248, 247, 94, 250, 40, 70, 180, ++ 248, 228, 36, 64, 242, 115, 81, 248, 247, 87, 250, 180, 248, 230, 36, ++ 40, 70, 64, 242, 114, 81, 248, 247, 80, 250, 40, 70, 148, 248, 232, ++ 20, 253, 247, 147, 251, 40, 70, 148, 248, 233, 20, 255, 247, 123, 254, ++ 40, 70, 180, 248, 234, 20, 254, 247, 172, 248, 40, 70, 180, 248, 238, ++ 36, 64, 246, 130, 1, 248, 247, 58, 250, 40, 70, 180, 248, 236, 36, 64, ++ 246, 7, 1, 248, 247, 51, 250, 40, 70, 180, 248, 240, 36, 64, 246, 172, ++ 17, 248, 247, 44, 250, 40, 70, 180, 248, 242, 36, 64, 246, 177, 17, ++ 248, 247, 37, 250, 40, 70, 180, 248, 244, 36, 64, 246, 121, 17, 248, ++ 247, 30, 250, 40, 70, 180, 248, 246, 36, 64, 242, 49, 97, 248, 247, ++ 23, 250, 40, 70, 180, 248, 248, 36, 64, 242, 218, 97, 248, 247, 16, ++ 250, 180, 248, 250, 36, 40, 70, 64, 246, 211, 17, 189, 232, 56, 64, ++ 248, 247, 7, 186, 0, 0, 16, 181, 40, 34, 4, 70, 9, 73, 248, 247, 140, ++ 253, 32, 70, 5, 34, 7, 73, 248, 247, 135, 253, 32, 70, 6, 73, 6, 34, ++ 248, 247, 130, 253, 32, 70, 40, 33, 189, 232, 16, 64, 255, 247, 37, ++ 190, 16, 73, 4, 0, 52, 71, 4, 0, 62, 71, 4, 0, 255, 247, 226, 191, 16, ++ 181, 4, 70, 254, 247, 102, 252, 32, 70, 189, 232, 16, 64, 255, 247, ++ 245, 191, 56, 181, 64, 242, 164, 65, 4, 70, 208, 248, 228, 80, 248, ++ 247, 204, 249, 64, 11, 128, 178, 7, 40, 2, 208, 149, 248, 69, 4, 7, ++ 224, 32, 70, 64, 242, 115, 65, 248, 247, 192, 249, 192, 5, 192, 13, ++ 64, 8, 64, 178, 56, 189, 45, 233, 240, 79, 208, 248, 232, 48, 135, 176, ++ 211, 248, 32, 49, 4, 70, 3, 240, 1, 3, 131, 240, 1, 2, 15, 70, 208, ++ 248, 228, 96, 1, 146, 27, 177, 131, 107, 24, 105, 2, 240, 56, 251, 32, ++ 70, 255, 247, 207, 255, 64, 242, 127, 65, 128, 70, 32, 70, 248, 247, ++ 157, 249, 64, 242, 117, 81, 129, 70, 32, 70, 248, 247, 151, 249, 64, ++ 242, 116, 81, 2, 144, 32, 70, 248, 247, 145, 249, 64, 242, 218, 97, ++ 3, 144, 32, 70, 248, 247, 139, 249, 64, 246, 248, 17, 4, 144, 32, 70, ++ 248, 247, 133, 249, 64, 242, 12, 81, 5, 144, 32, 70, 248, 247, 127, ++ 249, 64, 246, 172, 17, 197, 5, 32, 70, 248, 247, 121, 249, 79, 244, ++ 136, 97, 130, 70, 32, 70, 248, 247, 115, 249, 64, 246, 172, 17, 79, ++ 244, 112, 114, 79, 244, 128, 115, 131, 70, 32, 70, 248, 247, 238, 252, ++ 1, 34, 19, 70, 32, 70, 64, 246, 172, 17, 248, 247, 231, 252, 0, 35, ++ 1, 34, 32, 70, 79, 244, 136, 97, 248, 247, 224, 252, 27, 34, 32, 70, ++ 69, 73, 248, 247, 237, 252, 95, 250, 136, 243, 91, 0, 32, 70, 64, 242, ++ 164, 65, 64, 242, 255, 18, 248, 247, 209, 252, 64, 242, 255, 18, 9, ++ 244, 255, 115, 32, 70, 79, 244, 144, 97, 248, 247, 200, 252, 57, 70, ++ 32, 70, 251, 247, 218, 250, 10, 32, 211, 243, 235, 240, 32, 34, 32, ++ 70, 79, 244, 154, 97, 19, 70, 248, 247, 186, 252, 10, 32, 211, 243, ++ 225, 240, 237, 13, 1, 47, 32, 70, 3, 209, 250, 247, 73, 254, 7, 70, ++ 9, 224, 64, 242, 117, 65, 248, 247, 38, 249, 199, 5, 255, 13, 255, 47, ++ 136, 191, 167, 245, 0, 119, 32, 70, 252, 247, 50, 249, 32, 70, 64, 246, ++ 172, 17, 82, 70, 248, 247, 34, 249, 32, 70, 79, 244, 136, 97, 90, 70, ++ 248, 247, 28, 249, 32, 70, 64, 242, 117, 81, 2, 154, 248, 247, 22, 249, ++ 32, 70, 64, 242, 116, 81, 3, 154, 248, 247, 16, 249, 32, 70, 64, 242, ++ 218, 97, 4, 154, 248, 247, 10, 249, 32, 70, 64, 246, 248, 17, 5, 154, ++ 248, 247, 4, 249, 43, 70, 32, 70, 64, 242, 12, 81, 64, 242, 255, 18, ++ 248, 247, 118, 252, 182, 248, 2, 84, 79, 246, 254, 115, 109, 0, 43, ++ 64, 32, 70, 64, 242, 164, 65, 64, 242, 255, 18, 248, 247, 105, 252, ++ 182, 248, 4, 84, 79, 246, 254, 115, 109, 0, 43, 64, 32, 70, 79, 244, ++ 144, 97, 64, 242, 255, 18, 248, 247, 92, 252, 1, 155, 27, 185, 163, ++ 107, 24, 105, 2, 240, 102, 250, 56, 178, 7, 176, 189, 232, 240, 143, ++ 248, 69, 4, 0, 112, 181, 208, 248, 228, 80, 1, 38, 133, 248, 202, 100, ++ 64, 242, 76, 65, 4, 70, 248, 247, 192, 248, 64, 242, 77, 65, 165, 248, ++ 204, 4, 32, 70, 248, 247, 185, 248, 79, 244, 150, 97, 165, 248, 206, ++ 4, 32, 70, 248, 247, 178, 248, 64, 242, 177, 65, 165, 248, 208, 4, 32, ++ 70, 248, 247, 171, 248, 64, 242, 249, 65, 165, 248, 210, 4, 32, 70, ++ 248, 247, 164, 248, 64, 242, 250, 65, 165, 248, 212, 4, 32, 70, 248, ++ 247, 157, 248, 64, 246, 56, 17, 165, 248, 214, 4, 32, 70, 248, 247, ++ 150, 248, 64, 246, 57, 17, 165, 248, 216, 4, 32, 70, 248, 247, 143, ++ 248, 64, 242, 61, 81, 165, 248, 218, 4, 32, 70, 248, 247, 136, 248, ++ 64, 242, 60, 81, 165, 248, 220, 4, 32, 70, 248, 247, 129, 248, 64, 242, ++ 113, 81, 165, 248, 222, 4, 32, 70, 248, 247, 122, 248, 79, 244, 174, ++ 97, 165, 248, 224, 4, 32, 70, 248, 247, 115, 248, 64, 242, 115, 81, ++ 165, 248, 226, 4, 32, 70, 248, 247, 108, 248, 64, 242, 114, 81, 165, ++ 248, 228, 4, 32, 70, 248, 247, 101, 248, 64, 242, 218, 97, 165, 248, ++ 230, 4, 32, 70, 248, 247, 94, 248, 165, 248, 248, 4, 32, 70, 252, 247, ++ 200, 254, 133, 248, 232, 4, 32, 70, 255, 247, 128, 254, 64, 242, 164, ++ 65, 133, 248, 233, 4, 32, 70, 248, 247, 77, 248, 32, 244, 254, 80, 32, ++ 240, 63, 0, 165, 248, 234, 4, 0, 33, 32, 70, 253, 247, 185, 254, 32, ++ 70, 64, 246, 7, 1, 248, 247, 62, 248, 64, 246, 130, 1, 165, 248, 236, ++ 4, 32, 70, 248, 247, 55, 248, 50, 70, 165, 248, 238, 4, 0, 35, 32, 70, ++ 64, 246, 7, 1, 248, 247, 179, 251, 32, 70, 8, 34, 0, 35, 64, 246, 130, ++ 1, 248, 247, 172, 251, 79, 244, 0, 82, 32, 70, 19, 70, 64, 242, 76, ++ 65, 248, 247, 164, 251, 79, 244, 0, 82, 19, 70, 32, 70, 64, 242, 77, ++ 65, 248, 247, 156, 251, 32, 70, 64, 246, 172, 17, 248, 247, 18, 248, ++ 64, 246, 177, 17, 165, 248, 240, 4, 32, 70, 248, 247, 11, 248, 64, 246, ++ 121, 17, 165, 248, 242, 4, 32, 70, 248, 247, 4, 248, 50, 70, 165, 248, ++ 244, 4, 51, 70, 32, 70, 64, 246, 172, 17, 248, 247, 128, 251, 50, 70, ++ 51, 70, 32, 70, 64, 246, 121, 17, 248, 247, 121, 251, 32, 70, 64, 242, ++ 49, 97, 247, 247, 239, 255, 4, 34, 165, 248, 246, 4, 19, 70, 32, 70, ++ 64, 242, 49, 97, 248, 247, 107, 251, 16, 34, 19, 70, 32, 70, 64, 242, ++ 49, 97, 248, 247, 100, 251, 32, 70, 0, 34, 64, 242, 218, 97, 247, 247, ++ 228, 255, 8, 34, 32, 70, 19, 70, 64, 242, 218, 97, 248, 247, 87, 251, ++ 32, 34, 32, 70, 19, 70, 64, 242, 218, 97, 248, 247, 80, 251, 79, 244, ++ 128, 114, 19, 70, 32, 70, 64, 242, 218, 97, 248, 247, 72, 251, 32, 70, ++ 64, 246, 211, 17, 247, 247, 190, 255, 0, 35, 165, 248, 250, 4, 64, 246, ++ 211, 17, 32, 70, 79, 244, 0, 98, 248, 247, 57, 251, 0, 35, 32, 70, 79, ++ 244, 128, 82, 64, 246, 211, 17, 248, 247, 49, 251, 32, 70, 64, 246, ++ 165, 17, 247, 247, 167, 255, 79, 244, 128, 82, 165, 248, 252, 4, 19, ++ 70, 32, 70, 64, 246, 165, 17, 248, 247, 34, 251, 32, 70, 49, 70, 50, ++ 70, 0, 35, 189, 232, 112, 64, 250, 247, 228, 191, 45, 233, 240, 79, ++ 208, 248, 232, 48, 133, 176, 211, 248, 32, 49, 4, 70, 3, 240, 1, 3, ++ 131, 240, 1, 2, 208, 248, 228, 112, 0, 146, 27, 177, 131, 107, 24, 105, ++ 2, 240, 19, 249, 64, 242, 171, 65, 32, 70, 247, 247, 124, 255, 64, 242, ++ 164, 65, 32, 70, 247, 247, 119, 255, 0, 244, 96, 64, 1, 144, 32, 70, ++ 255, 247, 157, 253, 95, 250, 128, 251, 32, 70, 252, 247, 219, 253, 64, ++ 242, 12, 81, 128, 70, 32, 70, 247, 247, 102, 255, 79, 244, 149, 97, ++ 198, 5, 32, 70, 247, 247, 96, 255, 64, 242, 58, 65, 130, 70, 32, 70, ++ 247, 247, 90, 255, 2, 169, 192, 243, 128, 25, 32, 70, 250, 247, 168, ++ 252, 32, 70, 0, 33, 253, 247, 198, 253, 32, 70, 1, 33, 250, 247, 164, ++ 250, 32, 70, 127, 33, 255, 247, 136, 251, 1, 34, 19, 70, 32, 70, 64, ++ 242, 215, 65, 248, 247, 198, 250, 64, 34, 19, 70, 64, 242, 215, 65, ++ 32, 70, 248, 247, 191, 250, 32, 70, 253, 247, 40, 251, 0, 33, 32, 70, ++ 253, 247, 134, 248, 32, 70, 249, 247, 204, 254, 0, 34, 1, 33, 32, 70, ++ 248, 247, 240, 252, 32, 70, 249, 247, 229, 254, 64, 242, 171, 65, 32, ++ 70, 247, 247, 35, 255, 32, 70, 64, 242, 62, 97, 247, 247, 30, 255, 151, ++ 248, 51, 54, 197, 5, 246, 13, 237, 13, 147, 179, 1, 34, 19, 70, 32, ++ 70, 64, 242, 215, 65, 248, 247, 150, 250, 0, 35, 64, 242, 215, 65, 64, ++ 34, 32, 70, 248, 247, 143, 250, 32, 70, 249, 247, 163, 254, 0, 34, 1, ++ 33, 32, 70, 248, 247, 199, 252, 32, 70, 249, 247, 188, 254, 64, 242, ++ 171, 65, 32, 70, 247, 247, 250, 254, 64, 242, 62, 97, 32, 70, 247, 247, ++ 245, 254, 195, 5, 219, 13, 32, 70, 64, 242, 154, 65, 64, 242, 255, 18, ++ 248, 247, 113, 250, 32, 70, 64, 242, 215, 65, 1, 34, 0, 35, 248, 247, ++ 106, 250, 43, 70, 64, 242, 255, 18, 32, 70, 64, 242, 166, 65, 248, 247, ++ 98, 250, 41, 70, 32, 70, 254, 247, 58, 250, 0, 35, 79, 244, 128, 66, ++ 32, 70, 64, 242, 76, 65, 248, 247, 86, 250, 32, 70, 65, 70, 253, 247, ++ 32, 248, 32, 70, 73, 70, 250, 247, 33, 250, 32, 70, 2, 169, 250, 247, ++ 84, 252, 32, 70, 79, 244, 149, 97, 82, 70, 247, 247, 202, 254, 64, 242, ++ 255, 18, 51, 70, 32, 70, 64, 242, 12, 81, 248, 247, 60, 250, 32, 70, ++ 89, 70, 255, 247, 243, 250, 32, 70, 1, 153, 253, 247, 37, 253, 148, ++ 249, 24, 81, 79, 246, 192, 115, 173, 1, 43, 64, 32, 70, 79, 244, 154, ++ 97, 71, 246, 192, 114, 248, 247, 39, 250, 0, 155, 27, 185, 163, 107, ++ 24, 105, 2, 240, 49, 248, 5, 176, 189, 232, 240, 143, 112, 181, 208, ++ 248, 228, 80, 4, 70, 18, 34, 1, 38, 1, 33, 250, 247, 199, 255, 133, ++ 248, 202, 100, 32, 70, 64, 242, 116, 81, 247, 247, 137, 254, 64, 242, ++ 117, 81, 165, 248, 66, 5, 32, 70, 247, 247, 130, 254, 79, 244, 128, ++ 66, 165, 248, 68, 5, 19, 70, 32, 70, 64, 242, 116, 81, 248, 247, 253, ++ 249, 79, 244, 128, 98, 19, 70, 32, 70, 64, 242, 117, 81, 248, 247, 245, ++ 249, 32, 70, 64, 242, 76, 65, 247, 247, 107, 254, 64, 242, 77, 65, 165, ++ 248, 204, 4, 32, 70, 247, 247, 100, 254, 79, 244, 150, 97, 165, 248, ++ 206, 4, 32, 70, 247, 247, 93, 254, 64, 242, 177, 65, 165, 248, 208, ++ 4, 32, 70, 247, 247, 86, 254, 64, 242, 249, 65, 165, 248, 210, 4, 32, ++ 70, 247, 247, 79, 254, 64, 242, 250, 65, 165, 248, 212, 4, 32, 70, 247, ++ 247, 72, 254, 64, 246, 56, 17, 165, 248, 214, 4, 32, 70, 247, 247, 65, ++ 254, 64, 246, 57, 17, 165, 248, 216, 4, 32, 70, 247, 247, 58, 254, 64, ++ 242, 61, 81, 165, 248, 218, 4, 32, 70, 247, 247, 51, 254, 64, 242, 60, ++ 81, 165, 248, 220, 4, 32, 70, 247, 247, 44, 254, 64, 242, 113, 81, 165, ++ 248, 222, 4, 32, 70, 247, 247, 37, 254, 79, 244, 174, 97, 165, 248, ++ 224, 4, 32, 70, 247, 247, 30, 254, 64, 242, 115, 81, 165, 248, 226, ++ 4, 32, 70, 247, 247, 23, 254, 64, 242, 114, 81, 165, 248, 228, 4, 32, ++ 70, 247, 247, 16, 254, 64, 242, 218, 97, 165, 248, 230, 4, 32, 70, 247, ++ 247, 9, 254, 165, 248, 248, 4, 32, 70, 252, 247, 115, 252, 133, 248, ++ 232, 4, 32, 70, 255, 247, 43, 252, 64, 242, 164, 65, 133, 248, 233, ++ 4, 32, 70, 247, 247, 248, 253, 32, 244, 254, 80, 32, 240, 63, 0, 165, ++ 248, 234, 4, 0, 33, 32, 70, 253, 247, 100, 252, 32, 70, 64, 246, 7, ++ 1, 247, 247, 233, 253, 64, 246, 130, 1, 165, 248, 236, 4, 32, 70, 247, ++ 247, 226, 253, 8, 34, 0, 35, 165, 248, 238, 4, 64, 246, 130, 1, 32, ++ 70, 248, 247, 94, 249, 32, 70, 64, 246, 165, 17, 247, 247, 212, 253, ++ 64, 246, 172, 17, 165, 248, 70, 5, 32, 70, 247, 247, 205, 253, 64, 246, ++ 177, 17, 165, 248, 240, 4, 32, 70, 247, 247, 198, 253, 64, 246, 121, ++ 17, 165, 248, 242, 4, 32, 70, 247, 247, 191, 253, 79, 244, 128, 82, ++ 165, 248, 244, 4, 19, 70, 32, 70, 64, 246, 165, 17, 248, 247, 58, 249, ++ 32, 70, 50, 70, 51, 70, 64, 246, 172, 17, 248, 247, 51, 249, 64, 35, ++ 32, 70, 79, 244, 112, 114, 64, 246, 172, 17, 248, 247, 43, 249, 32, ++ 70, 64, 242, 49, 97, 247, 247, 161, 253, 4, 34, 165, 248, 246, 4, 19, ++ 70, 32, 70, 64, 242, 49, 97, 248, 247, 29, 249, 16, 34, 19, 70, 32, ++ 70, 64, 242, 49, 97, 248, 247, 22, 249, 32, 70, 71, 246, 15, 2, 64, ++ 242, 218, 97, 247, 247, 149, 253, 32, 70, 64, 246, 211, 17, 247, 247, ++ 133, 253, 0, 35, 165, 248, 250, 4, 64, 246, 211, 17, 32, 70, 79, 244, ++ 0, 98, 248, 247, 0, 249, 32, 70, 0, 35, 64, 246, 211, 17, 79, 244, 128, ++ 82, 248, 247, 248, 248, 79, 244, 0, 82, 32, 70, 19, 70, 64, 242, 76, ++ 65, 248, 247, 240, 248, 79, 244, 0, 82, 32, 70, 64, 242, 77, 65, 19, ++ 70, 189, 232, 112, 64, 248, 247, 230, 184, 248, 181, 208, 248, 232, ++ 48, 4, 70, 211, 248, 32, 49, 3, 240, 1, 3, 131, 240, 1, 5, 27, 177, ++ 131, 107, 24, 105, 1, 240, 228, 254, 64, 242, 164, 65, 32, 70, 247, ++ 247, 77, 253, 6, 70, 32, 70, 255, 247, 117, 251, 0, 33, 7, 70, 32, 70, ++ 253, 247, 186, 251, 32, 70, 253, 247, 50, 249, 64, 242, 55, 97, 79, ++ 244, 64, 66, 0, 35, 32, 70, 248, 247, 190, 248, 32, 70, 254, 247, 176, ++ 248, 79, 244, 128, 66, 0, 35, 32, 70, 64, 242, 76, 65, 248, 247, 179, ++ 248, 32, 70, 249, 178, 255, 247, 106, 249, 6, 244, 96, 65, 32, 70, 253, ++ 247, 155, 251, 148, 249, 24, 97, 79, 246, 192, 115, 182, 1, 32, 70, ++ 79, 244, 154, 97, 71, 246, 192, 114, 51, 64, 248, 247, 157, 248, 45, ++ 185, 163, 107, 24, 105, 189, 232, 248, 64, 1, 240, 166, 190, 248, 189, ++ 0, 0, 248, 181, 208, 248, 232, 48, 4, 70, 211, 248, 32, 49, 208, 248, ++ 228, 80, 3, 240, 1, 3, 176, 248, 246, 96, 131, 240, 1, 7, 27, 177, 131, ++ 107, 24, 105, 1, 240, 142, 254, 148, 248, 148, 17, 32, 70, 0, 41, 0, ++ 240, 162, 128, 252, 247, 9, 254, 213, 248, 196, 52, 32, 70, 19, 177, ++ 255, 247, 141, 255, 1, 224, 255, 247, 86, 253, 32, 70, 0, 33, 253, 247, ++ 33, 252, 32, 70, 78, 73, 15, 34, 248, 247, 121, 248, 149, 248, 51, 54, ++ 35, 179, 79, 244, 64, 66, 79, 244, 0, 67, 32, 70, 64, 242, 55, 97, 248, ++ 247, 91, 248, 32, 70, 1, 33, 253, 247, 12, 252, 149, 249, 49, 54, 32, ++ 70, 64, 242, 209, 65, 255, 34, 155, 178, 248, 247, 78, 248, 149, 248, ++ 50, 54, 32, 70, 64, 242, 209, 65, 79, 244, 127, 66, 27, 2, 248, 247, ++ 68, 248, 32, 70, 59, 73, 18, 34, 248, 247, 81, 248, 32, 70, 79, 244, ++ 149, 97, 8, 34, 247, 247, 191, 252, 148, 249, 24, 225, 79, 246, 192, ++ 115, 79, 234, 142, 30, 14, 234, 3, 3, 32, 70, 79, 244, 154, 97, 71, ++ 246, 192, 114, 248, 247, 42, 248, 79, 244, 0, 66, 19, 70, 32, 70, 79, ++ 244, 144, 97, 246, 178, 248, 247, 33, 248, 1, 62, 32, 70, 79, 244, 144, ++ 97, 64, 242, 255, 18, 180, 35, 248, 247, 24, 248, 171, 25, 147, 249, ++ 6, 54, 32, 70, 91, 0, 155, 178, 165, 248, 86, 52, 64, 242, 12, 81, 64, ++ 242, 255, 18, 248, 247, 10, 248, 213, 248, 196, 52, 99, 177, 181, 248, ++ 88, 36, 181, 248, 86, 52, 32, 70, 211, 24, 64, 242, 12, 81, 64, 242, ++ 255, 18, 155, 178, 247, 247, 250, 255, 60, 35, 32, 70, 64, 242, 167, ++ 65, 255, 34, 247, 247, 243, 255, 149, 248, 51, 52, 91, 177, 171, 25, ++ 5, 235, 70, 6, 147, 248, 38, 52, 182, 248, 12, 100, 165, 248, 2, 52, ++ 165, 248, 4, 100, 7, 224, 149, 248, 8, 52, 165, 248, 2, 52, 181, 248, ++ 6, 52, 165, 248, 4, 52, 32, 70, 79, 244, 96, 65, 253, 247, 200, 250, ++ 47, 185, 163, 107, 24, 105, 189, 232, 248, 64, 1, 240, 224, 189, 248, ++ 189, 0, 191, 72, 72, 4, 0, 102, 72, 4, 0, 112, 181, 208, 248, 228, 48, ++ 5, 70, 147, 248, 192, 36, 12, 70, 138, 66, 11, 208, 79, 244, 0, 98, ++ 131, 248, 192, 20, 64, 246, 218, 33, 0, 44, 20, 191, 19, 70, 0, 35, ++ 247, 247, 181, 255, 40, 70, 79, 244, 193, 97, 255, 34, 0, 44, 12, 191, ++ 20, 35, 24, 35, 189, 232, 112, 64, 247, 247, 169, 191, 209, 241, 1, ++ 3, 56, 191, 0, 35, 79, 244, 136, 97, 1, 34, 247, 247, 160, 191, 112, ++ 181, 4, 70, 208, 248, 228, 80, 251, 247, 6, 253, 32, 70, 255, 247, 94, ++ 248, 32, 70, 0, 33, 255, 247, 234, 255, 149, 248, 101, 53, 59, 177, ++ 0, 33, 32, 70, 10, 70, 11, 70, 189, 232, 112, 64, 250, 247, 82, 188, ++ 112, 189, 0, 0, 0, 35, 112, 181, 64, 242, 68, 97, 192, 248, 116, 49, ++ 4, 70, 247, 247, 248, 251, 10, 37, 32, 70, 64, 242, 68, 97, 247, 247, ++ 242, 251, 16, 240, 1, 3, 10, 208, 0, 33, 10, 70, 32, 70, 250, 247, 227, ++ 249, 2, 34, 32, 70, 64, 242, 63, 97, 19, 70, 6, 224, 130, 7, 6, 213, ++ 32, 70, 64, 242, 83, 65, 79, 244, 0, 66, 247, 247, 96, 255, 1, 32, 210, ++ 243, 135, 243, 32, 70, 64, 242, 68, 97, 247, 247, 211, 251, 1, 61, 1, ++ 208, 128, 7, 215, 209, 11, 34, 32, 70, 7, 73, 247, 247, 97, 255, 32, ++ 70, 0, 33, 255, 247, 162, 255, 32, 70, 64, 242, 156, 65, 1, 34, 0, 35, ++ 189, 232, 112, 64, 247, 247, 66, 191, 214, 70, 4, 0, 45, 233, 240, 67, ++ 4, 70, 137, 176, 15, 70, 144, 70, 208, 248, 228, 0, 79, 244, 128, 97, ++ 65, 242, 126, 82, 153, 70, 249, 247, 174, 253, 6, 70, 0, 40, 80, 208, ++ 1, 34, 19, 70, 32, 70, 64, 242, 156, 65, 196, 248, 116, 113, 247, 247, ++ 37, 255, 32, 70, 157, 248, 64, 16, 255, 247, 119, 255, 40, 34, 32, 70, ++ 57, 70, 249, 247, 225, 253, 176, 245, 128, 127, 5, 70, 4, 217, 212, ++ 248, 228, 0, 65, 242, 154, 81, 50, 224, 32, 70, 64, 242, 214, 97, 3, ++ 34, 0, 35, 247, 247, 11, 255, 8, 34, 19, 70, 32, 70, 64, 242, 218, 97, ++ 247, 247, 4, 255, 40, 35, 66, 70, 141, 232, 40, 0, 32, 70, 51, 70, 57, ++ 70, 253, 247, 78, 251, 21, 35, 3, 150, 5, 147, 0, 38, 32, 35, 32, 70, ++ 3, 169, 7, 147, 4, 149, 6, 150, 252, 247, 40, 252, 157, 248, 68, 48, ++ 32, 70, 1, 147, 41, 70, 79, 246, 255, 114, 51, 70, 205, 248, 0, 144, ++ 253, 247, 35, 252, 212, 248, 228, 0, 65, 242, 174, 81, 249, 247, 103, ++ 253, 9, 176, 189, 232, 240, 131, 45, 233, 240, 79, 169, 77, 151, 176, ++ 4, 70, 15, 70, 40, 104, 105, 104, 13, 171, 3, 195, 42, 137, 16, 38, ++ 26, 128, 16, 170, 3, 194, 27, 136, 213, 248, 10, 0, 19, 128, 0, 33, ++ 50, 70, 19, 144, 9, 168, 205, 243, 125, 247, 32, 70, 252, 247, 187, ++ 249, 32, 70, 250, 247, 92, 254, 32, 70, 249, 247, 193, 254, 1, 33, 32, ++ 70, 255, 247, 11, 255, 32, 70, 64, 242, 218, 97, 64, 246, 8, 2, 247, ++ 247, 51, 251, 79, 244, 128, 82, 19, 70, 32, 70, 64, 242, 164, 65, 247, ++ 247, 165, 254, 0, 34, 32, 70, 64, 242, 154, 81, 247, 247, 37, 251, 0, ++ 34, 32, 70, 64, 242, 155, 81, 247, 247, 31, 251, 0, 34, 32, 70, 64, ++ 242, 156, 81, 247, 247, 25, 251, 0, 34, 32, 70, 64, 242, 157, 81, 247, ++ 247, 19, 251, 0, 34, 64, 242, 158, 81, 32, 70, 247, 247, 13, 251, 32, ++ 70, 252, 247, 110, 249, 7, 144, 32, 70, 255, 247, 250, 254, 5, 32, 210, ++ 243, 167, 242, 0, 37, 1, 35, 250, 34, 32, 70, 123, 73, 141, 232, 40, ++ 0, 255, 247, 52, 255, 32, 70, 64, 242, 83, 65, 72, 246, 9, 34, 247, ++ 247, 243, 250, 32, 70, 64, 242, 82, 65, 71, 246, 118, 18, 247, 247, ++ 236, 250, 1, 47, 20, 208, 3, 211, 2, 47, 64, 240, 70, 129, 68, 224, ++ 64, 35, 1, 147, 110, 75, 41, 70, 2, 147, 32, 70, 9, 170, 8, 35, 0, 150, ++ 248, 247, 134, 248, 5, 33, 13, 241, 52, 10, 6, 145, 66, 224, 96, 35, ++ 223, 248, 164, 129, 1, 147, 32, 70, 41, 70, 20, 170, 2, 35, 223, 248, ++ 140, 145, 0, 150, 205, 248, 8, 128, 248, 247, 101, 248, 64, 35, 1, 147, ++ 32, 70, 41, 70, 20, 170, 2, 35, 0, 150, 205, 248, 8, 144, 248, 247, ++ 103, 248, 98, 35, 1, 147, 32, 70, 41, 70, 20, 170, 59, 70, 0, 150, 205, ++ 248, 8, 128, 248, 247, 79, 248, 67, 35, 1, 147, 20, 170, 32, 70, 41, ++ 70, 59, 70, 0, 150, 205, 248, 8, 144, 248, 247, 81, 248, 5, 34, 13, ++ 241, 64, 10, 6, 146, 13, 224, 67, 35, 1, 147, 75, 75, 32, 70, 2, 147, ++ 41, 70, 9, 170, 8, 35, 0, 150, 13, 241, 76, 10, 248, 247, 63, 248, 6, ++ 151, 0, 37, 168, 70, 185, 70, 69, 75, 7, 154, 233, 92, 91, 25, 81, 67, ++ 79, 240, 100, 11, 90, 120, 177, 251, 251, 241, 66, 234, 1, 35, 22, 174, ++ 38, 248, 2, 61, 60, 79, 79, 240, 16, 12, 0, 33, 50, 70, 1, 35, 32, 70, ++ 205, 248, 0, 192, 205, 248, 4, 128, 205, 248, 20, 192, 2, 151, 248, ++ 247, 28, 248, 54, 75, 7, 153, 234, 92, 91, 25, 74, 67, 91, 120, 178, ++ 251, 251, 251, 67, 234, 11, 43, 221, 248, 20, 192, 8, 241, 32, 3, 1, ++ 147, 0, 33, 50, 70, 1, 35, 32, 70, 8, 241, 1, 8, 173, 248, 86, 176, ++ 205, 248, 0, 192, 2, 151, 2, 53, 247, 247, 255, 255, 184, 241, 18, 15, ++ 62, 70, 191, 209, 79, 70, 85, 70, 79, 240, 0, 9, 186, 70, 32, 70, 3, ++ 33, 61, 34, 247, 247, 69, 250, 53, 248, 2, 43, 32, 70, 64, 242, 81, ++ 65, 66, 244, 0, 66, 247, 247, 60, 250, 66, 242, 17, 119, 2, 224, 10, ++ 32, 210, 243, 218, 241, 32, 70, 64, 242, 81, 65, 247, 247, 38, 250, ++ 16, 244, 64, 79, 1, 208, 1, 63, 242, 209, 32, 70, 64, 242, 81, 65, 247, ++ 247, 28, 250, 16, 39, 0, 244, 112, 96, 79, 234, 16, 43, 223, 248, 64, ++ 128, 0, 151, 248, 185, 128, 35, 1, 147, 32, 70, 89, 70, 20, 170, 2, ++ 35, 205, 248, 8, 128, 247, 247, 179, 255, 64, 35, 1, 147, 0, 151, 2, ++ 150, 32, 70, 89, 70, 20, 170, 2, 35, 30, 224, 0, 191, 166, 22, 4, 0, ++ 128, 132, 30, 0, 15, 36, 3, 0, 16, 71, 4, 0, 228, 71, 4, 0, 153, 30, ++ 3, 0, 131, 35, 1, 147, 32, 70, 0, 33, 20, 170, 1, 35, 205, 248, 8, 128, ++ 247, 247, 147, 255, 67, 35, 1, 147, 0, 151, 2, 150, 32, 70, 0, 33, 20, ++ 170, 1, 35, 247, 247, 150, 255, 9, 241, 1, 9, 6, 154, 95, 250, 137, ++ 249, 145, 69, 152, 211, 186, 241, 2, 15, 31, 208, 128, 35, 16, 37, 1, ++ 147, 32, 70, 0, 33, 20, 170, 2, 35, 0, 149, 205, 248, 8, 128, 247, 247, ++ 115, 255, 96, 35, 1, 147, 32, 70, 0, 33, 20, 170, 2, 35, 0, 149, 2, ++ 150, 247, 247, 118, 255, 112, 35, 1, 147, 32, 70, 0, 33, 20, 170, 2, ++ 35, 0, 149, 2, 150, 247, 247, 108, 255, 131, 35, 16, 37, 1, 147, 32, ++ 70, 0, 33, 20, 170, 1, 35, 0, 149, 205, 248, 8, 128, 247, 247, 83, 255, ++ 98, 35, 1, 147, 32, 70, 0, 33, 20, 170, 1, 35, 0, 149, 2, 150, 247, ++ 247, 86, 255, 114, 35, 1, 147, 32, 70, 0, 33, 20, 170, 1, 35, 0, 149, ++ 2, 150, 247, 247, 76, 255, 32, 70, 255, 247, 145, 253, 32, 70, 252, ++ 247, 252, 250, 32, 70, 251, 247, 33, 250, 32, 70, 0, 33, 255, 247, 100, ++ 253, 23, 176, 189, 232, 240, 143, 112, 181, 64, 242, 164, 65, 4, 70, ++ 247, 247, 127, 249, 5, 70, 32, 70, 254, 247, 167, 255, 0, 35, 79, 244, ++ 96, 98, 6, 70, 64, 242, 121, 81, 32, 70, 247, 247, 247, 252, 32, 70, ++ 70, 33, 254, 247, 174, 253, 32, 70, 0, 33, 255, 247, 21, 254, 32, 70, ++ 0, 33, 127, 34, 253, 247, 44, 251, 32, 70, 241, 178, 254, 247, 161, ++ 253, 32, 70, 5, 244, 96, 65, 189, 232, 112, 64, 252, 247, 208, 191, ++ 0, 0, 45, 233, 240, 79, 208, 248, 228, 32, 141, 176, 146, 248, 102, ++ 21, 7, 146, 78, 75, 79, 74, 0, 39, 2, 41, 8, 191, 26, 70, 1, 35, 6, ++ 146, 0, 147, 1, 147, 75, 73, 181, 34, 59, 70, 4, 70, 9, 151, 10, 151, ++ 11, 151, 62, 70, 255, 247, 130, 253, 184, 70, 5, 151, 79, 240, 56, 9, ++ 8, 37, 7, 154, 146, 248, 102, 53, 6, 154, 2, 43, 79, 234, 133, 3, 19, ++ 68, 88, 120, 154, 120, 8, 191, 223, 120, 0, 33, 1, 144, 2, 146, 32, ++ 70, 10, 70, 11, 70, 0, 145, 3, 151, 249, 247, 33, 253, 32, 70, 1, 33, ++ 249, 247, 116, 253, 30, 185, 32, 70, 73, 70, 254, 247, 89, 253, 79, ++ 240, 8, 10, 55, 33, 32, 70, 247, 247, 236, 248, 55, 33, 131, 70, 32, ++ 70, 247, 247, 231, 248, 0, 244, 0, 96, 192, 18, 5, 155, 11, 244, 128, ++ 123, 0, 235, 27, 43, 155, 68, 95, 250, 139, 242, 186, 241, 1, 10, 5, ++ 146, 231, 209, 9, 169, 32, 35, 32, 70, 79, 244, 128, 98, 205, 248, 0, ++ 160, 205, 248, 4, 160, 250, 247, 223, 248, 10, 153, 11, 155, 1, 245, ++ 0, 113, 3, 245, 0, 115, 137, 10, 155, 10, 110, 185, 185, 241, 55, 15, ++ 10, 217, 5, 154, 66, 185, 64, 242, 87, 70, 177, 66, 4, 216, 179, 66, ++ 148, 191, 0, 38, 1, 38, 0, 224, 1, 38, 246, 178, 38, 185, 169, 241, ++ 12, 9, 95, 250, 137, 249, 20, 224, 65, 246, 88, 50, 145, 66, 1, 216, ++ 147, 66, 1, 217, 1, 61, 6, 224, 145, 66, 16, 208, 64, 242, 86, 66, 147, ++ 66, 12, 216, 1, 53, 8, 241, 1, 8, 237, 178, 95, 250, 136, 248, 1, 38, ++ 184, 241, 8, 15, 2, 208, 13, 177, 16, 45, 129, 209, 32, 70, 255, 247, ++ 182, 252, 13, 176, 189, 232, 240, 143, 0, 191, 8, 72, 4, 0, 78, 71, ++ 4, 0, 128, 132, 30, 0, 55, 181, 4, 70, 1, 33, 208, 248, 228, 80, 255, ++ 247, 130, 252, 32, 70, 254, 247, 216, 255, 32, 70, 250, 247, 181, 253, ++ 149, 248, 101, 53, 195, 177, 181, 34, 0, 35, 1, 37, 32, 70, 13, 73, ++ 0, 149, 1, 149, 255, 247, 217, 252, 0, 33, 32, 70, 252, 247, 227, 249, ++ 32, 70, 252, 247, 200, 251, 0, 34, 32, 70, 41, 70, 19, 70, 250, 247, ++ 214, 248, 32, 70, 255, 247, 131, 252, 32, 70, 3, 176, 189, 232, 48, ++ 64, 255, 247, 37, 191, 0, 191, 128, 132, 30, 0, 240, 181, 208, 248, ++ 228, 48, 2, 37, 0, 39, 149, 176, 131, 248, 102, 85, 131, 248, 101, 117, ++ 4, 70, 255, 247, 193, 255, 41, 70, 32, 70, 18, 170, 250, 247, 226, 248, ++ 254, 35, 141, 248, 77, 48, 6, 35, 141, 248, 78, 48, 250, 35, 141, 248, ++ 76, 80, 141, 248, 79, 48, 61, 70, 19, 171, 235, 92, 3, 174, 187, 85, ++ 89, 178, 1, 35, 0, 147, 1, 147, 21, 75, 181, 34, 89, 67, 32, 70, 0, ++ 35, 255, 247, 147, 252, 0, 35, 15, 169, 79, 244, 250, 82, 0, 147, 1, ++ 147, 32, 70, 32, 35, 250, 247, 47, 248, 32, 70, 255, 247, 64, 252, 12, ++ 35, 107, 67, 242, 24, 8, 51, 4, 50, 32, 70, 15, 169, 243, 24, 1, 53, ++ 253, 247, 138, 251, 12, 55, 4, 45, 213, 209, 32, 70, 49, 70, 42, 70, ++ 253, 247, 83, 248, 32, 70, 255, 247, 16, 252, 21, 176, 240, 189, 64, ++ 66, 15, 0, 45, 233, 240, 79, 157, 176, 157, 248, 152, 160, 1, 37, 10, ++ 241, 255, 59, 5, 250, 11, 251, 137, 70, 19, 146, 79, 244, 136, 97, 95, ++ 250, 139, 242, 4, 70, 5, 146, 4, 147, 247, 247, 18, 248, 4, 34, 40, ++ 64, 19, 70, 6, 144, 79, 244, 136, 97, 32, 70, 247, 247, 142, 251, 42, ++ 70, 0, 35, 79, 244, 136, 97, 32, 70, 247, 247, 135, 251, 40, 70, 209, ++ 243, 174, 247, 42, 70, 43, 70, 79, 244, 136, 97, 32, 70, 247, 247, 125, ++ 251, 40, 70, 209, 243, 164, 247, 223, 248, 180, 132, 7, 35, 32, 38, ++ 35, 33, 1, 147, 32, 70, 43, 70, 21, 170, 0, 150, 205, 248, 8, 128, 247, ++ 247, 145, 253, 42, 70, 21, 155, 41, 70, 32, 70, 250, 247, 48, 248, 64, ++ 242, 164, 65, 32, 70, 246, 247, 220, 255, 0, 244, 96, 64, 0, 33, 7, ++ 144, 32, 70, 252, 247, 75, 254, 64, 242, 81, 65, 32, 70, 246, 247, 208, ++ 255, 64, 242, 82, 65, 8, 144, 32, 70, 246, 247, 202, 255, 64, 242, 164, ++ 65, 9, 144, 32, 70, 246, 247, 196, 255, 129, 33, 10, 144, 32, 70, 246, ++ 247, 152, 255, 104, 33, 11, 144, 32, 70, 246, 247, 147, 255, 9, 33, ++ 12, 144, 32, 70, 246, 247, 142, 255, 2, 33, 13, 144, 32, 70, 246, 247, ++ 137, 255, 165, 33, 14, 144, 32, 70, 246, 247, 132, 255, 162, 33, 15, ++ 144, 32, 70, 246, 247, 127, 255, 153, 33, 16, 144, 32, 70, 246, 247, ++ 122, 255, 150, 33, 17, 144, 32, 70, 246, 247, 117, 255, 41, 70, 18, ++ 144, 32, 70, 249, 247, 69, 254, 0, 35, 32, 70, 64, 242, 77, 65, 79, ++ 244, 128, 66, 247, 247, 20, 251, 79, 244, 128, 66, 19, 70, 32, 70, 64, ++ 242, 76, 65, 247, 247, 12, 251, 129, 33, 16, 34, 0, 35, 32, 70, 247, ++ 247, 203, 250, 64, 34, 165, 33, 19, 70, 32, 70, 247, 247, 197, 250, ++ 104, 33, 2, 34, 0, 35, 32, 70, 247, 247, 191, 250, 2, 34, 162, 33, 19, ++ 70, 32, 70, 247, 247, 185, 250, 104, 33, 42, 70, 0, 35, 32, 70, 247, ++ 247, 179, 250, 162, 33, 42, 70, 43, 70, 32, 70, 247, 247, 173, 250, ++ 9, 33, 42, 70, 0, 35, 32, 70, 247, 247, 167, 250, 153, 33, 42, 70, 43, ++ 70, 32, 70, 247, 247, 161, 250, 42, 70, 32, 70, 2, 33, 0, 35, 247, 247, ++ 155, 250, 2, 34, 19, 70, 32, 70, 150, 33, 247, 247, 149, 250, 34, 35, ++ 1, 147, 32, 70, 43, 70, 13, 33, 22, 170, 0, 150, 205, 248, 8, 128, 247, ++ 247, 234, 252, 22, 159, 32, 70, 7, 244, 126, 83, 219, 9, 1, 147, 18, ++ 33, 43, 70, 22, 170, 0, 150, 205, 248, 8, 128, 247, 247, 220, 252, 22, ++ 153, 7, 244, 240, 18, 1, 240, 15, 0, 1, 244, 240, 97, 201, 9, 1, 145, ++ 157, 248, 156, 16, 7, 244, 224, 51, 0, 38, 82, 12, 155, 11, 0, 144, ++ 2, 145, 32, 70, 199, 243, 64, 81, 3, 150, 249, 247, 25, 251, 41, 70, ++ 32, 70, 249, 247, 108, 251, 79, 244, 0, 82, 19, 70, 32, 70, 64, 242, ++ 116, 81, 247, 247, 147, 250, 79, 244, 0, 114, 19, 70, 32, 70, 64, 242, ++ 117, 81, 247, 247, 139, 250, 221, 248, 16, 192, 79, 244, 122, 113, 98, ++ 70, 1, 251, 9, 241, 43, 70, 32, 70, 0, 150, 1, 150, 255, 247, 62, 251, ++ 32, 70, 64, 242, 81, 65, 79, 244, 0, 66, 51, 70, 247, 247, 118, 250, ++ 32, 70, 64, 242, 81, 65, 79, 244, 128, 66, 51, 70, 247, 247, 110, 250, ++ 32, 70, 64, 242, 81, 65, 79, 244, 112, 98, 79, 244, 0, 115, 247, 247, ++ 101, 250, 79, 244, 0, 66, 19, 70, 32, 70, 64, 242, 83, 65, 247, 247, ++ 93, 250, 32, 70, 64, 242, 82, 65, 66, 246, 34, 18, 246, 247, 220, 254, ++ 79, 244, 134, 115, 173, 248, 104, 48, 23, 150, 177, 70, 69, 70, 158, ++ 224, 79, 244, 128, 82, 19, 70, 32, 70, 64, 242, 164, 65, 247, 247, 70, ++ 250, 79, 244, 128, 66, 32, 70, 64, 242, 81, 65, 19, 70, 247, 247, 62, ++ 250, 66, 242, 17, 119, 2, 224, 10, 32, 209, 243, 98, 246, 32, 70, 64, ++ 242, 81, 65, 246, 247, 174, 254, 16, 244, 64, 79, 1, 208, 1, 63, 242, ++ 209, 156, 35, 16, 39, 1, 147, 32, 70, 0, 33, 13, 241, 106, 2, 1, 35, ++ 0, 151, 2, 149, 247, 247, 71, 252, 157, 35, 1, 147, 32, 70, 0, 33, 27, ++ 170, 1, 35, 0, 151, 189, 248, 106, 128, 2, 149, 247, 247, 59, 252, 158, ++ 35, 1, 147, 32, 70, 0, 33, 13, 241, 110, 2, 1, 35, 0, 151, 2, 149, 247, ++ 247, 48, 252, 189, 249, 110, 32, 189, 249, 108, 48, 82, 67, 3, 251, ++ 3, 35, 23, 154, 32, 70, 211, 24, 23, 147, 64, 242, 164, 65, 79, 244, ++ 128, 82, 0, 35, 247, 247, 249, 249, 79, 244, 128, 66, 32, 70, 64, 242, ++ 81, 65, 19, 70, 247, 247, 241, 249, 66, 242, 17, 119, 2, 224, 10, 32, ++ 209, 243, 21, 246, 32, 70, 64, 242, 81, 65, 246, 247, 97, 254, 16, 244, ++ 64, 79, 1, 208, 1, 63, 242, 209, 156, 35, 16, 39, 1, 147, 32, 70, 0, ++ 33, 13, 241, 106, 2, 1, 35, 0, 151, 2, 149, 247, 247, 250, 251, 189, ++ 248, 106, 48, 32, 70, 152, 68, 157, 35, 1, 147, 0, 33, 27, 170, 1, 35, ++ 0, 151, 2, 149, 247, 247, 237, 251, 158, 35, 1, 147, 13, 241, 110, 2, ++ 1, 35, 32, 70, 0, 33, 0, 151, 2, 149, 247, 247, 226, 251, 189, 249, ++ 110, 32, 189, 249, 108, 48, 82, 67, 3, 251, 3, 35, 23, 154, 193, 68, ++ 211, 24, 31, 250, 137, 249, 23, 147, 1, 54, 5, 154, 150, 66, 255, 246, ++ 93, 175, 23, 155, 73, 250, 10, 249, 91, 68, 35, 250, 10, 243, 28, 169, ++ 65, 248, 20, 61, 26, 171, 0, 37, 1, 147, 32, 70, 24, 170, 25, 171, 0, ++ 149, 248, 247, 131, 248, 189, 248, 100, 32, 189, 248, 104, 48, 32, 70, ++ 211, 24, 19, 154, 3, 245, 135, 115, 19, 128, 255, 247, 7, 250, 42, 70, ++ 43, 70, 32, 70, 41, 70, 249, 247, 81, 254, 32, 70, 41, 70, 249, 247, ++ 84, 250, 32, 70, 43, 70, 64, 242, 117, 81, 79, 244, 0, 114, 247, 247, ++ 123, 249, 43, 70, 32, 70, 79, 244, 128, 66, 64, 242, 76, 65, 247, 247, ++ 115, 249, 32, 70, 41, 70, 249, 247, 152, 252, 32, 70, 129, 33, 11, 154, ++ 246, 247, 207, 253, 32, 70, 104, 33, 12, 154, 246, 247, 202, 253, 32, ++ 70, 9, 33, 13, 154, 246, 247, 197, 253, 32, 70, 2, 33, 14, 154, 246, ++ 247, 192, 253, 32, 70, 165, 33, 15, 154, 246, 247, 187, 253, 32, 70, ++ 162, 33, 16, 154, 246, 247, 182, 253, 32, 70, 153, 33, 17, 154, 246, ++ 247, 177, 253, 32, 70, 150, 33, 18, 154, 246, 247, 172, 253, 32, 70, ++ 10, 154, 64, 242, 164, 65, 246, 247, 199, 253, 32, 70, 8, 154, 64, 242, ++ 81, 65, 246, 247, 193, 253, 9, 154, 32, 70, 64, 242, 82, 65, 246, 247, ++ 187, 253, 32, 70, 7, 153, 252, 247, 34, 252, 32, 70, 4, 34, 43, 70, ++ 79, 244, 136, 97, 247, 247, 42, 249, 32, 70, 79, 244, 136, 97, 1, 34, ++ 6, 155, 247, 247, 35, 249, 31, 250, 137, 240, 29, 176, 189, 232, 240, ++ 143, 153, 30, 3, 0, 45, 233, 240, 71, 0, 33, 142, 176, 208, 248, 228, ++ 128, 144, 248, 246, 80, 173, 248, 50, 16, 173, 248, 52, 16, 4, 70, 0, ++ 33, 9, 168, 12, 34, 205, 243, 198, 241, 0, 35, 173, 248, 54, 48, 152, ++ 248, 21, 54, 19, 177, 152, 248, 22, 54, 1, 224, 152, 248, 20, 54, 212, ++ 248, 128, 33, 153, 73, 138, 66, 10, 209, 1, 43, 5, 241, 255, 53, 1, ++ 209, 150, 75, 32, 224, 3, 43, 12, 191, 149, 75, 150, 75, 27, 224, 150, ++ 73, 138, 66, 10, 209, 1, 43, 5, 241, 255, 53, 1, 209, 147, 75, 18, 224, ++ 3, 43, 12, 191, 146, 75, 147, 75, 13, 224, 147, 73, 138, 66, 64, 240, ++ 115, 129, 1, 43, 5, 241, 255, 53, 1, 209, 144, 75, 3, 224, 3, 43, 12, ++ 191, 143, 75, 143, 75, 3, 235, 133, 5, 0, 45, 0, 240, 100, 129, 32, ++ 70, 1, 33, 255, 247, 33, 249, 46, 136, 70, 177, 54, 178, 79, 244, 122, ++ 114, 114, 67, 32, 70, 1, 33, 252, 247, 172, 253, 1, 38, 107, 136, 99, ++ 177, 1, 54, 246, 178, 27, 178, 79, 244, 122, 114, 90, 67, 32, 70, 49, ++ 70, 252, 247, 159, 253, 1, 46, 10, 209, 0, 224, 222, 177, 2, 35, 0, ++ 147, 1, 33, 0, 35, 1, 147, 2, 147, 32, 70, 10, 70, 8, 224, 2, 35, 1, ++ 33, 0, 147, 1, 147, 0, 35, 2, 147, 32, 70, 10, 70, 11, 70, 249, 247, ++ 165, 249, 32, 70, 5, 33, 79, 244, 134, 114, 13, 241, 50, 3, 251, 247, ++ 51, 250, 0, 38, 55, 70, 177, 70, 169, 91, 33, 179, 4, 32, 11, 35, 141, ++ 232, 9, 0, 9, 178, 13, 170, 79, 244, 250, 115, 32, 70, 255, 247, 215, ++ 252, 189, 248, 52, 32, 189, 248, 50, 48, 28, 58, 210, 26, 184, 249, ++ 24, 22, 19, 178, 153, 66, 14, 220, 14, 169, 6, 35, 3, 251, 7, 19, 169, ++ 91, 1, 55, 35, 248, 20, 28, 35, 248, 18, 44, 35, 248, 16, 12, 191, 178, ++ 79, 240, 1, 9, 2, 54, 4, 46, 213, 209, 2, 35, 6, 147, 16, 35, 8, 147, ++ 13, 241, 54, 3, 4, 147, 0, 37, 1, 35, 32, 70, 4, 169, 5, 147, 7, 149, ++ 251, 247, 213, 250, 16, 35, 141, 232, 40, 0, 80, 75, 2, 33, 2, 147, ++ 32, 70, 1, 35, 13, 241, 54, 2, 1, 53, 247, 247, 124, 250, 64, 45, 240, ++ 209, 0, 37, 32, 70, 41, 70, 42, 70, 43, 70, 0, 149, 1, 149, 2, 149, ++ 249, 247, 72, 249, 185, 241, 0, 15, 64, 240, 185, 128, 202, 224, 14, ++ 171, 79, 240, 6, 9, 9, 251, 5, 57, 57, 248, 20, 108, 1, 53, 237, 178, ++ 15, 250, 134, 250, 79, 244, 122, 114, 2, 251, 10, 242, 32, 70, 41, 70, ++ 252, 247, 18, 253, 184, 249, 26, 38, 57, 249, 18, 60, 154, 66, 3, 221, ++ 32, 70, 41, 70, 54, 74, 7, 224, 184, 249, 28, 38, 32, 70, 154, 66, 204, ++ 191, 52, 74, 52, 74, 41, 70, 186, 241, 0, 15, 184, 191, 202, 241, 0, ++ 10, 249, 247, 46, 253, 79, 234, 138, 10, 0, 35, 64, 242, 113, 34, 146, ++ 69, 7, 221, 1, 51, 219, 178, 170, 245, 156, 106, 32, 43, 170, 241, 2, ++ 10, 243, 209, 50, 178, 0, 42, 216, 191, 91, 66, 219, 178, 90, 178, 118, ++ 0, 111, 244, 28, 126, 14, 251, 2, 110, 0, 42, 184, 191, 82, 66, 2, 42, ++ 108, 221, 0, 33, 10, 70, 32, 78, 15, 250, 142, 240, 49, 248, 6, 144, ++ 128, 234, 224, 124, 172, 235, 224, 124, 225, 69, 91, 209, 6, 33, 1, ++ 251, 2, 98, 0, 40, 178, 248, 2, 160, 178, 248, 4, 144, 90, 178, 8, 218, ++ 0, 42, 1, 221, 94, 30, 46, 224, 222, 178, 6, 241, 64, 3, 63, 54, 41, ++ 224, 0, 42, 35, 221, 94, 28, 37, 224, 192, 173, 58, 2, 54, 105, 4, 0, ++ 36, 101, 4, 0, 236, 100, 4, 0, 128, 186, 140, 1, 102, 108, 4, 0, 202, ++ 105, 4, 0, 236, 104, 4, 0, 0, 248, 36, 1, 110, 105, 4, 0, 158, 108, ++ 4, 0, 214, 108, 4, 0, 15, 36, 3, 0, 36, 105, 4, 0, 42, 105, 4, 0, 48, ++ 105, 4, 0, 166, 105, 4, 0, 222, 178, 6, 241, 64, 3, 65, 54, 91, 178, ++ 32, 70, 4, 169, 7, 147, 251, 247, 28, 250, 189, 248, 54, 48, 32, 70, ++ 154, 68, 4, 169, 173, 248, 54, 160, 118, 178, 251, 247, 205, 252, 32, ++ 70, 4, 169, 7, 150, 251, 247, 13, 250, 189, 248, 54, 48, 32, 70, 153, ++ 68, 4, 169, 173, 248, 54, 144, 251, 247, 191, 252, 3, 224, 1, 50, 6, ++ 49, 6, 42, 148, 209, 189, 66, 255, 244, 69, 175, 79, 240, 0, 3, 1, 47, ++ 0, 147, 1, 147, 2, 147, 32, 70, 79, 240, 5, 1, 1, 209, 58, 70, 1, 224, ++ 1, 34, 19, 70, 249, 247, 120, 248, 32, 70, 0, 33, 254, 247, 193, 255, ++ 14, 176, 189, 232, 240, 135, 0, 191, 115, 181, 0, 35, 19, 112, 11, 112, ++ 144, 248, 148, 49, 6, 70, 12, 70, 21, 70, 27, 179, 64, 242, 171, 65, ++ 246, 247, 211, 251, 16, 244, 0, 79, 48, 70, 2, 208, 64, 242, 171, 65, ++ 8, 224, 64, 242, 60, 97, 246, 247, 200, 251, 3, 4, 6, 213, 48, 70, 64, ++ 242, 60, 97, 246, 247, 193, 251, 64, 8, 32, 112, 1, 34, 1, 171, 214, ++ 248, 136, 4, 0, 33, 1, 240, 238, 249, 34, 120, 157, 248, 4, 48, 211, ++ 24, 43, 112, 124, 189, 248, 181, 20, 70, 31, 70, 5, 70, 248, 247, 61, ++ 251, 6, 70, 49, 70, 40, 70, 34, 70, 252, 247, 44, 251, 7, 235, 135, ++ 7, 237, 25, 174, 25, 150, 249, 110, 20, 32, 70, 189, 232, 248, 64, 1, ++ 240, 142, 186, 56, 181, 208, 248, 228, 80, 64, 246, 7, 1, 4, 70, 246, ++ 247, 147, 251, 149, 248, 74, 53, 27, 177, 64, 240, 1, 3, 155, 178, 2, ++ 224, 79, 246, 254, 115, 3, 64, 149, 248, 75, 37, 18, 177, 67, 240, 2, ++ 2, 2, 224, 79, 246, 253, 114, 26, 64, 32, 70, 64, 246, 7, 1, 189, 232, ++ 56, 64, 246, 247, 132, 187, 127, 181, 0, 35, 64, 242, 62, 97, 6, 70, ++ 1, 147, 2, 147, 3, 147, 246, 247, 111, 251, 64, 242, 166, 65, 197, 5, ++ 48, 70, 246, 247, 105, 251, 237, 13, 196, 5, 133, 244, 128, 117, 228, ++ 13, 5, 245, 254, 117, 3, 53, 132, 244, 128, 116, 48, 70, 1, 169, 2, ++ 170, 3, 171, 45, 27, 248, 247, 62, 251, 168, 178, 1, 169, 128, 8, 14, ++ 201, 248, 247, 136, 253, 4, 176, 112, 189, 45, 233, 240, 79, 64, 242, ++ 164, 65, 133, 176, 4, 70, 208, 248, 228, 112, 246, 247, 70, 251, 0, ++ 244, 96, 75, 32, 70, 254, 247, 109, 249, 64, 246, 7, 1, 95, 250, 128, ++ 250, 32, 70, 246, 247, 58, 251, 0, 240, 1, 0, 1, 144, 64, 242, 58, 65, ++ 32, 70, 246, 247, 50, 251, 2, 169, 192, 243, 128, 24, 32, 70, 249, 247, ++ 128, 248, 32, 70, 0, 33, 252, 247, 158, 249, 1, 34, 0, 35, 32, 70, 64, ++ 246, 7, 1, 246, 247, 166, 254, 32, 70, 1, 33, 248, 247, 117, 254, 32, ++ 70, 63, 33, 253, 247, 89, 255, 5, 38, 63, 37, 79, 244, 0, 66, 19, 70, ++ 32, 70, 64, 242, 164, 65, 246, 247, 148, 254, 1, 33, 0, 34, 32, 70, ++ 247, 247, 207, 248, 100, 32, 209, 243, 182, 242, 32, 70, 255, 247, 139, ++ 255, 1, 33, 0, 34, 129, 70, 32, 70, 247, 247, 195, 248, 100, 32, 209, ++ 243, 170, 242, 32, 70, 255, 247, 127, 255, 215, 248, 92, 53, 129, 68, ++ 79, 234, 105, 9, 195, 235, 9, 3, 0, 43, 1, 221, 90, 16, 1, 224, 90, ++ 28, 82, 16, 2, 51, 4, 43, 15, 217, 173, 24, 127, 45, 168, 191, 127, ++ 37, 1, 33, 32, 70, 37, 234, 229, 117, 248, 247, 54, 254, 32, 70, 41, ++ 70, 253, 247, 26, 255, 1, 62, 192, 209, 215, 248, 96, 53, 32, 70, 65, ++ 70, 195, 235, 9, 9, 248, 247, 40, 254, 32, 70, 2, 169, 249, 247, 91, ++ 248, 9, 241, 1, 9, 32, 70, 81, 70, 253, 247, 6, 255, 5, 235, 105, 5, ++ 32, 70, 89, 70, 252, 247, 54, 249, 127, 45, 168, 191, 127, 37, 32, 70, ++ 64, 246, 7, 1, 1, 34, 1, 155, 246, 247, 59, 254, 37, 234, 229, 112, ++ 5, 176, 189, 232, 240, 143, 45, 233, 247, 67, 21, 70, 8, 34, 15, 70, ++ 30, 70, 64, 246, 7, 1, 19, 70, 4, 70, 208, 248, 228, 144, 189, 248, ++ 40, 128, 246, 247, 38, 254, 1, 34, 19, 70, 32, 70, 64, 246, 7, 1, 246, ++ 247, 31, 254, 79, 244, 0, 82, 19, 70, 32, 70, 64, 246, 70, 1, 246, 247, ++ 23, 254, 32, 70, 64, 246, 57, 1, 58, 70, 246, 247, 151, 250, 148, 248, ++ 17, 52, 32, 70, 64, 246, 53, 1, 11, 177, 128, 34, 0, 224, 32, 34, 246, ++ 247, 140, 250, 32, 70, 79, 244, 4, 97, 0, 34, 246, 247, 134, 250, 32, ++ 70, 64, 246, 52, 1, 127, 34, 51, 70, 246, 247, 249, 253, 32, 70, 79, ++ 244, 1, 97, 79, 244, 128, 67, 79, 244, 64, 66, 246, 247, 240, 253, 148, ++ 248, 17, 52, 32, 70, 64, 246, 54, 1, 19, 177, 79, 244, 128, 114, 0, ++ 224, 128, 34, 246, 247, 106, 250, 32, 70, 64, 246, 70, 1, 15, 34, 7, ++ 35, 246, 247, 221, 253, 148, 248, 17, 100, 32, 70, 64, 246, 70, 1, 240, ++ 34, 86, 177, 144, 35, 246, 247, 211, 253, 32, 70, 64, 246, 70, 1, 79, ++ 244, 112, 98, 79, 244, 16, 99, 8, 224, 51, 70, 246, 247, 200, 253, 32, ++ 70, 64, 246, 70, 1, 79, 244, 112, 98, 51, 70, 246, 247, 192, 253, 43, ++ 70, 32, 70, 64, 246, 51, 1, 127, 34, 246, 247, 185, 253, 79, 234, 8, ++ 35, 32, 70, 64, 246, 51, 1, 79, 244, 254, 66, 3, 244, 127, 67, 246, ++ 247, 174, 253, 1, 37, 32, 70, 53, 73, 100, 34, 0, 35, 0, 149, 1, 149, ++ 254, 247, 101, 254, 79, 244, 128, 82, 19, 70, 32, 70, 64, 246, 165, ++ 17, 246, 247, 157, 253, 42, 70, 43, 70, 64, 246, 136, 17, 32, 70, 246, ++ 247, 150, 253, 79, 244, 150, 112, 209, 243, 188, 241, 42, 70, 32, 70, ++ 64, 246, 55, 1, 246, 247, 18, 250, 68, 246, 33, 101, 2, 224, 10, 32, ++ 209, 243, 176, 241, 32, 70, 64, 246, 55, 1, 246, 247, 252, 249, 48, ++ 177, 1, 61, 244, 209, 3, 224, 10, 32, 209, 243, 164, 241, 1, 224, 68, ++ 246, 33, 101, 32, 70, 64, 246, 55, 1, 246, 247, 237, 249, 8, 177, 1, ++ 61, 241, 209, 32, 70, 64, 246, 55, 1, 246, 247, 229, 249, 194, 7, 5, ++ 213, 148, 248, 185, 51, 67, 240, 1, 3, 132, 248, 185, 51, 0, 35, 32, ++ 70, 64, 246, 165, 17, 79, 244, 128, 82, 246, 247, 90, 253, 32, 70, 254, ++ 247, 209, 253, 32, 70, 0, 35, 64, 242, 166, 97, 65, 246, 255, 114, 246, ++ 247, 79, 253, 185, 248, 72, 85, 79, 246, 128, 114, 237, 1, 32, 70, 64, ++ 246, 9, 1, 5, 234, 2, 3, 3, 176, 189, 232, 240, 67, 246, 247, 64, 189, ++ 160, 37, 38, 0, 45, 233, 240, 65, 208, 248, 228, 48, 144, 248, 17, 132, ++ 147, 248, 76, 85, 147, 248, 74, 53, 0, 38, 200, 176, 4, 70, 68, 150, ++ 176, 69, 20, 191, 79, 240, 64, 8, 79, 240, 16, 8, 43, 185, 64, 246, ++ 7, 1, 1, 34, 246, 247, 36, 253, 156, 224, 254, 247, 3, 251, 32, 70, ++ 251, 247, 123, 248, 32, 70, 253, 247, 160, 254, 32, 35, 75, 79, 141, ++ 232, 72, 0, 33, 33, 1, 35, 32, 70, 68, 170, 1, 54, 2, 151, 246, 247, ++ 65, 255, 64, 46, 241, 209, 5, 34, 32, 70, 65, 70, 19, 70, 0, 149, 255, ++ 247, 208, 254, 0, 38, 1, 150, 33, 33, 1, 35, 79, 240, 32, 8, 32, 70, ++ 68, 170, 1, 54, 205, 248, 0, 128, 2, 151, 246, 247, 42, 255, 5, 46, ++ 240, 209, 62, 45, 58, 78, 24, 216, 32, 70, 33, 33, 69, 170, 1, 35, 1, ++ 149, 205, 248, 0, 128, 2, 150, 246, 247, 14, 255, 1, 53, 237, 178, 32, ++ 35, 141, 232, 168, 0, 1, 53, 33, 33, 1, 35, 32, 70, 69, 170, 237, 178, ++ 246, 247, 14, 255, 64, 45, 242, 209, 64, 246, 9, 1, 127, 34, 8, 35, ++ 32, 70, 246, 247, 211, 252, 32, 70, 251, 247, 25, 251, 32, 70, 253, ++ 247, 128, 254, 8, 34, 19, 70, 64, 246, 7, 1, 32, 70, 246, 247, 198, ++ 252, 32, 70, 255, 247, 163, 253, 64, 242, 116, 81, 32, 70, 246, 247, ++ 57, 249, 64, 242, 117, 81, 7, 70, 32, 70, 246, 247, 51, 249, 79, 244, ++ 128, 66, 19, 70, 128, 70, 64, 242, 116, 81, 32, 70, 246, 247, 175, 252, ++ 79, 244, 128, 98, 19, 70, 32, 70, 64, 242, 117, 81, 246, 247, 167, 252, ++ 0, 37, 32, 35, 141, 232, 40, 0, 32, 70, 33, 33, 4, 170, 64, 35, 2, 150, ++ 246, 247, 193, 254, 32, 70, 64, 242, 116, 81, 58, 70, 246, 247, 28, ++ 249, 32, 70, 64, 242, 117, 81, 66, 70, 246, 247, 22, 249, 4, 171, 232, ++ 88, 70, 169, 71, 170, 4, 53, 247, 247, 125, 254, 181, 245, 128, 127, ++ 245, 209, 72, 176, 189, 232, 240, 129, 0, 191, 15, 36, 3, 0, 153, 30, ++ 3, 0, 208, 248, 232, 48, 45, 233, 240, 65, 211, 248, 32, 49, 4, 70, ++ 3, 240, 1, 3, 13, 70, 131, 240, 1, 6, 27, 185, 131, 107, 24, 105, 0, ++ 240, 125, 250, 32, 70, 212, 248, 228, 112, 253, 247, 15, 255, 64, 242, ++ 127, 65, 167, 248, 2, 4, 32, 70, 212, 248, 228, 112, 246, 247, 218, ++ 248, 192, 5, 192, 13, 64, 16, 167, 248, 4, 4, 212, 248, 20, 33, 65, ++ 246, 6, 35, 19, 64, 43, 185, 68, 246, 32, 98, 16, 45, 8, 191, 250, 34, ++ 0, 224, 250, 34, 163, 107, 184, 33, 24, 105, 0, 240, 73, 250, 163, 107, ++ 24, 105, 0, 240, 81, 250, 32, 70, 248, 247, 88, 248, 212, 248, 20, 33, ++ 65, 246, 6, 35, 19, 64, 27, 185, 163, 107, 27, 106, 196, 248, 120, 49, ++ 8, 45, 1, 208, 233, 6, 6, 213, 3, 33, 10, 34, 32, 70, 249, 247, 64, ++ 248, 8, 45, 1, 208, 170, 6, 4, 213, 32, 70, 254, 247, 29, 255, 8, 45, ++ 1, 208, 107, 6, 4, 213, 32, 70, 255, 247, 32, 248, 8, 45, 1, 208, 232, ++ 5, 7, 213, 212, 248, 228, 48, 147, 248, 23, 54, 19, 177, 32, 70, 255, ++ 247, 248, 250, 32, 70, 254, 247, 247, 248, 32, 70, 248, 247, 37, 248, ++ 8, 45, 1, 208, 41, 6, 12, 213, 212, 248, 228, 80, 149, 248, 100, 53, ++ 35, 177, 32, 70, 255, 247, 45, 253, 197, 248, 84, 5, 32, 70, 255, 247, ++ 191, 254, 32, 70, 248, 247, 50, 248, 30, 185, 163, 107, 24, 105, 0, ++ 240, 5, 250, 32, 70, 0, 33, 251, 247, 166, 255, 212, 248, 228, 48, 147, ++ 248, 51, 54, 115, 177, 32, 70, 1, 33, 251, 247, 157, 255, 32, 70, 64, ++ 242, 55, 97, 79, 244, 64, 66, 79, 244, 0, 67, 189, 232, 240, 65, 246, ++ 247, 221, 187, 189, 232, 240, 129, 16, 181, 4, 70, 248, 247, 104, 250, ++ 192, 177, 212, 248, 20, 33, 64, 246, 15, 35, 19, 64, 147, 185, 148, ++ 249, 132, 49, 123, 185, 16, 6, 13, 212, 148, 248, 17, 49, 83, 185, 32, ++ 70, 252, 247, 199, 249, 48, 185, 32, 70, 79, 244, 248, 113, 189, 232, ++ 16, 64, 255, 247, 63, 191, 16, 189, 240, 181, 131, 107, 135, 176, 4, ++ 70, 79, 244, 66, 113, 24, 105, 0, 240, 183, 249, 163, 107, 7, 70, 64, ++ 242, 10, 49, 24, 105, 0, 240, 176, 249, 163, 107, 5, 70, 79, 244, 67, ++ 113, 24, 105, 0, 240, 169, 249, 163, 107, 6, 70, 64, 242, 14, 49, 24, ++ 105, 0, 240, 162, 249, 190, 25, 54, 4, 45, 24, 117, 25, 27, 208, 79, ++ 244, 134, 115, 173, 248, 20, 48, 5, 245, 128, 117, 0, 35, 109, 10, 0, ++ 147, 5, 171, 45, 2, 1, 147, 3, 170, 4, 171, 32, 70, 2, 169, 2, 149, ++ 247, 247, 112, 250, 189, 249, 16, 32, 31, 75, 155, 26, 0, 43, 184, 191, ++ 91, 66, 112, 43, 10, 217, 148, 248, 201, 42, 79, 246, 120, 99, 210, ++ 241, 1, 2, 173, 248, 16, 48, 56, 191, 0, 34, 0, 224, 1, 34, 189, 249, ++ 16, 0, 148, 248, 201, 58, 128, 8, 1, 70, 91, 177, 0, 35, 165, 107, 237, ++ 24, 1, 51, 8, 43, 133, 248, 32, 17, 248, 209, 18, 177, 0, 35, 132, 248, ++ 201, 58, 163, 107, 211, 248, 40, 33, 155, 24, 131, 248, 32, 1, 163, ++ 107, 211, 248, 40, 33, 7, 42, 1, 208, 1, 50, 0, 224, 0, 34, 195, 248, ++ 40, 33, 148, 248, 7, 49, 1, 43, 2, 209, 0, 35, 132, 248, 7, 49, 64, ++ 178, 7, 176, 240, 189, 120, 254, 255, 255, 112, 181, 208, 248, 228, ++ 48, 1, 41, 211, 248, 196, 85, 211, 248, 192, 101, 211, 248, 200, 69, ++ 2, 209, 253, 247, 245, 253, 1, 224, 248, 247, 202, 252, 0, 178, 6, 251, ++ 0, 85, 99, 30, 1, 38, 22, 250, 3, 243, 237, 24, 85, 250, 4, 244, 32, ++ 178, 112, 189, 48, 181, 208, 248, 228, 32, 210, 248, 44, 54, 243, 185, ++ 146, 248, 42, 54, 146, 248, 48, 38, 1, 36, 20, 250, 3, 243, 148, 64, ++ 208, 248, 232, 0, 1, 41, 176, 248, 156, 84, 155, 178, 164, 178, 173, ++ 178, 6, 209, 255, 42, 67, 234, 5, 3, 7, 208, 35, 234, 4, 3, 4, 224, ++ 37, 234, 3, 3, 255, 42, 24, 191, 35, 67, 160, 248, 156, 52, 1, 32, 48, ++ 189, 208, 248, 228, 48, 147, 248, 41, 54, 19, 177, 0, 33, 255, 247, ++ 209, 191, 112, 71, 208, 248, 228, 48, 211, 248, 44, 38, 114, 185, 147, ++ 248, 42, 54, 208, 248, 232, 32, 1, 32, 16, 250, 3, 243, 178, 248, 156, ++ 36, 146, 178, 26, 66, 12, 191, 0, 35, 1, 35, 11, 112, 1, 32, 112, 71, ++ 1, 42, 208, 248, 228, 48, 12, 209, 10, 120, 81, 178, 17, 241, 121, 15, ++ 10, 219, 6, 58, 82, 178, 163, 248, 2, 22, 163, 248, 4, 38, 248, 247, ++ 121, 186, 179, 249, 2, 54, 11, 96, 112, 71, 176, 248, 246, 48, 7, 181, ++ 19, 244, 64, 79, 12, 191, 144, 249, 52, 51, 144, 249, 53, 51, 1, 147, ++ 10, 51, 3, 218, 1, 169, 1, 34, 255, 247, 218, 255, 14, 189, 247, 181, ++ 208, 248, 20, 33, 64, 246, 6, 35, 19, 64, 4, 70, 15, 70, 206, 178, 35, ++ 185, 208, 248, 148, 52, 176, 248, 246, 32, 26, 112, 32, 70, 248, 247, ++ 240, 251, 32, 70, 1, 33, 254, 247, 250, 250, 212, 248, 232, 48, 211, ++ 248, 32, 49, 3, 240, 1, 3, 131, 240, 1, 5, 27, 177, 163, 107, 24, 105, ++ 0, 240, 163, 248, 32, 70, 49, 70, 250, 247, 206, 248, 32, 70, 57, 70, ++ 246, 247, 213, 253, 32, 70, 49, 70, 252, 247, 102, 251, 32, 70, 49, ++ 70, 252, 247, 12, 252, 2, 33, 1, 35, 0, 147, 32, 70, 10, 70, 11, 70, ++ 249, 247, 142, 253, 212, 248, 20, 33, 65, 246, 6, 35, 19, 64, 32, 70, ++ 19, 185, 79, 244, 248, 113, 0, 224, 16, 33, 255, 247, 243, 253, 32, ++ 70, 252, 247, 28, 255, 29, 185, 163, 107, 24, 105, 0, 240, 121, 248, ++ 0, 33, 32, 70, 254, 247, 188, 250, 32, 70, 254, 247, 206, 249, 79, 244, ++ 0, 114, 19, 70, 32, 70, 79, 244, 136, 97, 246, 247, 90, 250, 16, 34, ++ 19, 70, 32, 70, 64, 246, 5, 1, 246, 247, 83, 250, 1, 34, 19, 70, 32, ++ 70, 79, 244, 65, 113, 246, 247, 76, 250, 15, 34, 10, 35, 32, 70, 64, ++ 242, 21, 49, 246, 247, 69, 250, 64, 246, 255, 114, 19, 70, 32, 70, 64, ++ 242, 39, 49, 246, 247, 61, 250, 148, 248, 160, 58, 1, 43, 2, 209, 32, ++ 70, 255, 247, 107, 255, 1, 35, 132, 248, 201, 58, 254, 189, 208, 248, ++ 148, 52, 176, 248, 246, 32, 16, 181, 4, 70, 26, 112, 252, 247, 147, ++ 252, 32, 70, 248, 247, 111, 251, 32, 70, 253, 247, 193, 252, 148, 248, ++ 114, 51, 19, 177, 32, 70, 250, 247, 213, 255, 32, 70, 248, 247, 222, ++ 248, 32, 70, 250, 247, 23, 250, 32, 70, 180, 248, 246, 16, 255, 247, ++ 89, 255, 32, 70, 255, 247, 16, 255, 148, 248, 160, 58, 1, 43, 4, 209, ++ 32, 70, 189, 232, 16, 64, 255, 247, 59, 191, 16, 189, 128, 104, 225, ++ 243, 252, 182, 128, 104, 225, 243, 31, 183, 0, 104, 15, 240, 14, 153, ++ 0, 104, 14, 240, 93, 155, 0, 104, 14, 240, 50, 153, 0, 104, 13, 240, ++ 1, 159, 0, 104, 238, 247, 52, 184, 0, 104, 237, 247, 66, 189, 0, 104, ++ 13, 240, 70, 157, 0, 104, 13, 240, 219, 154, 3, 104, 155, 111, 152, ++ 139, 8, 128, 155, 125, 19, 112, 112, 71, 0, 104, 2, 33, 15, 240, 120, ++ 154, 0, 104, 2, 33, 15, 240, 102, 154, 0, 104, 15, 240, 235, 152, 64, ++ 104, 218, 247, 244, 190, 64, 104, 33, 240, 23, 156, 0, 104, 238, 247, ++ 140, 190, 0, 104, 238, 247, 11, 191, 45, 233, 248, 67, 139, 104, 76, ++ 105, 3, 43, 129, 70, 13, 70, 210, 248, 8, 128, 150, 137, 103, 104, 81, ++ 208, 35, 104, 0, 43, 24, 70, 11, 218, 8, 224, 3, 104, 17, 70, 64, 104, ++ 0, 34, 152, 71, 0, 40, 58, 208, 4, 35, 6, 224, 240, 24, 53, 212, 195, ++ 25, 179, 66, 50, 216, 64, 68, 0, 35, 3, 241, 8, 2, 217, 25, 171, 104, ++ 8, 49, 162, 24, 97, 24, 107, 177, 3, 43, 14, 209, 9, 224, 16, 248, 3, ++ 192, 212, 92, 206, 92, 12, 234, 4, 4, 166, 66, 29, 209, 1, 51, 0, 224, ++ 0, 35, 187, 66, 242, 219, 18, 224, 1, 43, 21, 209, 99, 104, 246, 26, ++ 176, 68, 15, 224, 16, 248, 3, 192, 212, 92, 206, 92, 12, 234, 4, 4, ++ 166, 66, 6, 209, 1, 51, 0, 224, 0, 35, 187, 66, 242, 219, 1, 32, 3, ++ 224, 1, 48, 64, 69, 247, 217, 0, 32, 43, 123, 19, 177, 128, 240, 1, ++ 0, 192, 178, 16, 177, 107, 123, 137, 248, 102, 48, 189, 232, 248, 131, ++ 160, 104, 0, 40, 175, 209, 240, 231, 45, 233, 247, 79, 3, 70, 72, 105, ++ 151, 137, 4, 29, 0, 120, 210, 248, 8, 176, 1, 144, 0, 38, 66, 224, 96, ++ 136, 180, 248, 0, 160, 0, 241, 32, 2, 51, 248, 18, 32, 165, 136, 15, ++ 250, 130, 252, 188, 241, 255, 63, 4, 209, 224, 136, 16, 240, 1, 0, 55, ++ 208, 43, 224, 1, 40, 4, 209, 186, 69, 2, 220, 202, 235, 7, 10, 0, 224, ++ 146, 68, 31, 250, 138, 250, 10, 235, 5, 2, 186, 66, 39, 220, 5, 241, ++ 8, 0, 32, 24, 218, 68, 0, 34, 12, 224, 4, 235, 2, 12, 156, 248, 8, 128, ++ 26, 248, 2, 192, 16, 248, 2, 144, 8, 234, 12, 12, 225, 69, 4, 209, 1, ++ 50, 170, 66, 240, 219, 1, 32, 0, 224, 0, 32, 226, 136, 210, 7, 72, 191, ++ 128, 240, 1, 0, 80, 177, 4, 53, 1, 54, 4, 235, 69, 4, 246, 178, 1, 154, ++ 150, 66, 185, 209, 1, 32, 0, 224, 0, 32, 10, 123, 10, 177, 128, 240, ++ 1, 0, 16, 177, 74, 123, 131, 248, 102, 32, 189, 232, 254, 143, 45, 233, ++ 240, 71, 163, 241, 12, 7, 5, 70, 56, 70, 12, 70, 145, 70, 152, 70, 211, ++ 247, 211, 253, 6, 70, 0, 40, 92, 208, 9, 241, 12, 1, 58, 70, 202, 247, ++ 49, 254, 163, 104, 102, 97, 2, 43, 46, 209, 3, 47, 87, 217, 115, 136, ++ 159, 66, 81, 209, 168, 241, 16, 8, 51, 29, 150, 248, 0, 192, 0, 33, ++ 27, 224, 159, 136, 120, 0, 8, 48, 128, 69, 72, 211, 8, 55, 223, 25, ++ 0, 34, 10, 224, 3, 235, 2, 9, 153, 248, 8, 160, 23, 248, 2, 144, 10, ++ 234, 9, 9, 7, 248, 2, 144, 1, 50, 179, 248, 4, 144, 74, 69, 240, 211, ++ 192, 235, 8, 8, 27, 24, 1, 49, 140, 69, 225, 209, 51, 120, 1, 43, 51, ++ 209, 243, 136, 29, 224, 114, 104, 3, 43, 12, 191, 4, 35, 0, 35, 3, 235, ++ 66, 1, 8, 49, 143, 66, 32, 209, 154, 24, 3, 241, 8, 1, 8, 50, 113, 24, ++ 178, 24, 0, 35, 4, 224, 205, 92, 208, 92, 40, 64, 208, 84, 1, 51, 112, ++ 104, 131, 66, 247, 211, 51, 104, 0, 43, 2, 219, 163, 104, 1, 43, 17, ++ 209, 99, 123, 67, 240, 1, 3, 99, 115, 12, 224, 111, 240, 26, 4, 4, 224, ++ 111, 240, 1, 4, 1, 224, 111, 240, 13, 4, 40, 70, 49, 70, 43, 240, 145, ++ 222, 0, 224, 0, 36, 32, 70, 189, 232, 240, 135, 112, 181, 2, 121, 4, ++ 70, 18, 240, 2, 0, 14, 70, 96, 209, 35, 106, 203, 177, 139, 104, 137, ++ 137, 22, 41, 21, 217, 25, 123, 93, 123, 9, 2, 73, 25, 137, 178, 177, ++ 245, 0, 111, 13, 209, 153, 123, 9, 9, 4, 41, 9, 209, 219, 125, 1, 43, ++ 6, 209, 99, 106, 1, 51, 99, 98, 227, 104, 1, 51, 227, 96, 112, 189, ++ 99, 105, 67, 185, 163, 141, 51, 185, 2, 240, 8, 0, 208, 241, 1, 0, 56, ++ 191, 0, 32, 112, 189, 32, 70, 49, 70, 44, 240, 210, 216, 0, 35, 132, ++ 248, 102, 48, 101, 105, 1, 32, 19, 224, 171, 104, 32, 70, 2, 43, 41, ++ 70, 50, 70, 2, 209, 255, 247, 229, 254, 1, 224, 255, 247, 128, 254, ++ 48, 177, 107, 123, 132, 248, 102, 48, 43, 105, 1, 51, 43, 97, 2, 224, ++ 45, 104, 0, 45, 233, 209, 35, 121, 3, 240, 1, 3, 152, 66, 15, 209, 163, ++ 141, 67, 177, 148, 248, 102, 48, 217, 7, 4, 212, 32, 70, 49, 70, 44, ++ 240, 107, 217, 32, 185, 163, 104, 1, 32, 1, 51, 163, 96, 112, 189, 227, ++ 104, 0, 32, 1, 51, 227, 96, 112, 189, 1, 32, 112, 189, 112, 181, 208, ++ 248, 4, 81, 6, 104, 4, 70, 232, 107, 28, 240, 46, 216, 214, 248, 108, ++ 50, 156, 66, 1, 209, 35, 122, 67, 177, 233, 106, 232, 107, 3, 74, 137, ++ 2, 35, 70, 189, 232, 112, 64, 27, 240, 209, 159, 112, 189, 1, 63, 134, ++ 0, 112, 181, 6, 104, 4, 70, 208, 248, 4, 81, 48, 70, 248, 243, 134, ++ 245, 212, 248, 4, 49, 219, 139, 3, 185, 24, 187, 43, 120, 2, 43, 32, ++ 209, 35, 122, 243, 177, 107, 120, 227, 185, 107, 104, 211, 185, 214, ++ 248, 168, 52, 35, 185, 214, 248, 104, 49, 107, 177, 155, 121, 91, 177, ++ 48, 70, 33, 70, 1, 34, 10, 240, 187, 219, 96, 177, 214, 248, 104, 1, ++ 0, 33, 50, 240, 63, 220, 6, 224, 32, 70, 1, 33, 220, 247, 231, 253, ++ 32, 70, 44, 240, 159, 217, 171, 122, 11, 185, 107, 104, 139, 177, 212, ++ 248, 4, 49, 219, 139, 67, 177, 107, 104, 32, 70, 0, 43, 12, 191, 3, ++ 35, 1, 35, 43, 98, 44, 240, 38, 218, 32, 70, 189, 232, 112, 64, 44, ++ 240, 141, 154, 35, 121, 35, 177, 32, 70, 189, 232, 112, 64, 255, 247, ++ 152, 191, 112, 189, 247, 181, 208, 248, 4, 81, 4, 70, 43, 120, 6, 104, ++ 2, 43, 239, 106, 53, 209, 51, 104, 27, 126, 0, 43, 49, 208, 43, 107, ++ 2, 169, 65, 248, 4, 61, 214, 248, 208, 5, 27, 240, 220, 223, 167, 235, ++ 144, 32, 5, 40, 1, 217, 184, 66, 5, 217, 171, 106, 32, 70, 235, 98, ++ 255, 247, 145, 255, 29, 224, 232, 98, 32, 70, 255, 247, 114, 255, 214, ++ 248, 104, 49, 179, 177, 155, 121, 163, 177, 48, 70, 33, 70, 1, 34, 10, ++ 240, 96, 219, 112, 177, 48, 70, 33, 70, 9, 240, 185, 223, 48, 177, 169, ++ 106, 214, 248, 104, 1, 73, 0, 50, 240, 222, 219, 2, 224, 32, 70, 7, ++ 240, 254, 220, 254, 189, 16, 181, 208, 248, 4, 49, 28, 122, 28, 185, ++ 255, 247, 185, 255, 32, 70, 16, 189, 79, 240, 255, 48, 16, 189, 112, ++ 181, 21, 70, 194, 104, 19, 240, 32, 0, 140, 88, 11, 209, 112, 189, 22, ++ 33, 1, 251, 6, 65, 40, 70, 116, 49, 6, 34, 202, 247, 134, 252, 64, 177, ++ 1, 54, 0, 224, 0, 38, 212, 248, 212, 49, 158, 66, 239, 211, 0, 32, 112, ++ 189, 1, 32, 112, 189, 45, 233, 240, 79, 147, 176, 30, 70, 28, 156, 195, ++ 104, 13, 70, 146, 70, 189, 248, 116, 176, 207, 88, 12, 177, 1, 148, ++ 79, 224, 27, 240, 96, 3, 25, 209, 28, 70, 108, 224, 79, 240, 22, 9, ++ 9, 251, 8, 121, 80, 70, 9, 241, 116, 1, 6, 34, 9, 241, 112, 9, 202, ++ 247, 91, 252, 56, 185, 18, 170, 2, 235, 132, 3, 9, 241, 10, 2, 67, 248, ++ 68, 44, 1, 52, 8, 241, 1, 8, 0, 224, 160, 70, 215, 248, 212, 49, 152, ++ 69, 226, 211, 43, 104, 211, 248, 188, 6, 3, 104, 235, 88, 83, 177, 27, ++ 121, 67, 177, 60, 177, 27, 240, 32, 15, 4, 209, 41, 70, 82, 70, 1, 155, ++ 8, 240, 19, 254, 43, 122, 227, 177, 228, 185, 40, 104, 3, 104, 147, ++ 248, 242, 48, 0, 43, 53, 208, 208, 248, 208, 54, 219, 136, 0, 43, 48, ++ 208, 18, 171, 67, 248, 4, 77, 82, 70, 41, 70, 39, 240, 217, 216, 17, ++ 155, 90, 28, 38, 208, 22, 34, 2, 251, 3, 115, 122, 51, 1, 147, 1, 36, ++ 0, 224, 244, 177, 115, 120, 111, 70, 243, 24, 156, 112, 3, 241, 2, 8, ++ 35, 10, 136, 248, 1, 48, 115, 120, 0, 37, 2, 51, 115, 112, 10, 224, ++ 64, 68, 2, 48, 87, 248, 4, 31, 16, 34, 202, 247, 23, 252, 115, 120, ++ 1, 53, 16, 51, 115, 112, 165, 66, 79, 234, 5, 16, 240, 209, 132, 28, ++ 228, 178, 32, 70, 19, 176, 189, 232, 240, 143, 1, 32, 112, 71, 22, 32, ++ 112, 71, 0, 0, 11, 40, 154, 191, 1, 75, 24, 92, 0, 32, 112, 71, 227, ++ 81, 4, 0, 56, 181, 13, 70, 255, 247, 241, 255, 4, 70, 40, 70, 255, 247, ++ 240, 255, 96, 67, 56, 189, 9, 185, 4, 48, 112, 71, 0, 32, 112, 71, 1, ++ 41, 3, 208, 4, 211, 3, 41, 4, 209, 1, 224, 4, 48, 112, 71, 26, 48, 112, ++ 71, 0, 32, 112, 71, 5, 41, 17, 216, 79, 240, 136, 67, 139, 64, 11, 212, ++ 79, 240, 24, 67, 139, 64, 5, 212, 79, 240, 0, 83, 139, 64, 5, 213, 4, ++ 48, 112, 71, 26, 48, 112, 71, 48, 48, 112, 71, 0, 32, 112, 71, 9, 41, ++ 14, 216, 223, 232, 1, 240, 7, 9, 11, 7, 7, 9, 5, 7, 9, 11, 4, 48, 112, ++ 71, 26, 48, 112, 71, 48, 48, 112, 71, 70, 48, 112, 71, 0, 32, 112, 71, ++ 15, 41, 19, 216, 223, 232, 1, 240, 12, 14, 16, 12, 12, 14, 18, 18, 18, ++ 18, 18, 8, 10, 12, 14, 16, 4, 48, 112, 71, 26, 48, 112, 71, 70, 48, ++ 112, 71, 92, 48, 112, 71, 48, 48, 112, 71, 0, 32, 112, 71, 112, 181, ++ 120, 177, 5, 104, 0, 35, 7, 74, 220, 0, 82, 248, 51, 96, 174, 66, 3, ++ 209, 18, 25, 83, 104, 152, 71, 112, 189, 1, 51, 5, 43, 242, 209, 0, ++ 32, 112, 189, 0, 191, 168, 81, 4, 0, 1, 41, 24, 191, 0, 32, 112, 71, ++ 1, 42, 1, 209, 4, 48, 112, 71, 0, 32, 112, 71, 1, 41, 11, 209, 1, 43, ++ 9, 216, 1, 59, 6, 73, 2, 235, 131, 2, 81, 248, 34, 48, 90, 28, 3, 208, ++ 192, 24, 112, 71, 0, 32, 112, 71, 0, 32, 112, 71, 208, 81, 4, 0, 2, ++ 40, 154, 191, 1, 75, 24, 92, 0, 32, 112, 71, 224, 81, 4, 0, 20, 35, ++ 3, 251, 1, 0, 112, 71, 56, 181, 12, 70, 0, 33, 5, 70, 255, 247, 246, ++ 255, 3, 136, 163, 66, 7, 208, 40, 70, 1, 33, 255, 247, 239, 255, 3, ++ 136, 156, 66, 24, 191, 0, 32, 56, 189, 112, 181, 14, 70, 0, 33, 5, 70, ++ 255, 247, 228, 255, 3, 136, 179, 66, 6, 208, 40, 70, 0, 33, 255, 247, ++ 221, 255, 4, 70, 8, 177, 13, 224, 0, 36, 1, 33, 40, 70, 255, 247, 213, ++ 255, 3, 136, 179, 66, 5, 208, 40, 70, 1, 33, 189, 232, 112, 64, 255, ++ 247, 204, 191, 32, 70, 112, 189, 3, 70, 16, 181, 8, 104, 12, 70, 22, ++ 34, 25, 70, 202, 247, 38, 251, 35, 104, 22, 32, 22, 51, 35, 96, 16, ++ 189, 45, 233, 247, 67, 2, 35, 1, 145, 4, 70, 11, 112, 84, 248, 4, 59, ++ 13, 70, 75, 112, 23, 70, 255, 247, 11, 255, 129, 70, 255, 247, 8, 255, ++ 128, 70, 255, 247, 5, 255, 6, 70, 255, 247, 2, 255, 79, 234, 9, 105, ++ 73, 234, 16, 105, 8, 244, 127, 72, 73, 234, 8, 41, 6, 244, 127, 6, 73, ++ 234, 22, 38, 110, 96, 56, 70, 255, 247, 244, 254, 6, 70, 56, 70, 255, ++ 247, 240, 254, 0, 10, 64, 234, 6, 38, 110, 128, 0, 38, 46, 114, 110, ++ 114, 1, 155, 10, 51, 1, 147, 104, 120, 255, 247, 230, 254, 10, 37, 128, ++ 70, 7, 224, 32, 70, 1, 169, 58, 70, 255, 247, 180, 255, 22, 52, 45, ++ 24, 1, 54, 70, 69, 245, 209, 40, 70, 189, 232, 254, 131, 16, 181, 4, ++ 70, 84, 248, 4, 11, 255, 247, 104, 255, 111, 240, 127, 1, 2, 70, 32, ++ 70, 189, 232, 16, 64, 203, 243, 76, 182, 8, 181, 255, 247, 93, 255, ++ 4, 48, 8, 189, 56, 181, 4, 70, 8, 70, 13, 70, 255, 247, 245, 255, 111, ++ 240, 127, 1, 2, 70, 32, 70, 203, 243, 59, 246, 37, 96, 56, 189, 56, ++ 181, 8, 70, 13, 70, 255, 247, 232, 255, 211, 247, 76, 250, 4, 70, 16, ++ 177, 41, 70, 255, 247, 230, 255, 32, 70, 56, 189, 16, 181, 8, 104, 12, ++ 70, 255, 247, 218, 255, 32, 70, 189, 232, 16, 64, 211, 247, 62, 186, ++ 112, 181, 0, 37, 12, 70, 13, 128, 73, 104, 6, 70, 17, 177, 255, 247, ++ 237, 255, 101, 96, 161, 104, 33, 177, 48, 70, 255, 247, 231, 255, 0, ++ 35, 163, 96, 112, 189, 0, 104, 112, 71, 2, 32, 112, 71, 56, 181, 20, ++ 70, 29, 70, 255, 247, 230, 254, 80, 177, 33, 70, 255, 247, 248, 254, ++ 1, 70, 40, 177, 40, 70, 4, 34, 202, 247, 124, 250, 4, 32, 56, 189, 40, ++ 70, 111, 240, 127, 1, 4, 34, 203, 243, 244, 245, 0, 32, 56, 189, 112, ++ 181, 4, 156, 21, 70, 30, 70, 255, 247, 204, 254, 88, 177, 41, 70, 50, ++ 70, 255, 247, 225, 254, 1, 70, 40, 177, 32, 70, 8, 34, 202, 247, 97, ++ 250, 8, 32, 112, 189, 32, 70, 111, 240, 127, 1, 8, 34, 203, 243, 217, ++ 245, 0, 32, 112, 189, 112, 181, 5, 156, 21, 70, 30, 70, 255, 247, 177, ++ 254, 96, 177, 41, 70, 50, 70, 4, 155, 255, 247, 203, 254, 1, 70, 40, ++ 177, 32, 70, 10, 34, 202, 247, 69, 250, 10, 32, 112, 189, 32, 70, 111, ++ 240, 127, 1, 10, 34, 203, 243, 189, 245, 0, 32, 112, 189, 112, 181, ++ 5, 156, 21, 70, 30, 70, 255, 247, 149, 254, 96, 177, 41, 70, 50, 70, ++ 4, 155, 255, 247, 175, 254, 1, 70, 40, 177, 32, 70, 10, 34, 202, 247, ++ 41, 250, 10, 32, 112, 189, 32, 70, 111, 240, 127, 1, 10, 34, 203, 243, ++ 161, 245, 0, 32, 112, 189, 56, 181, 29, 70, 20, 70, 255, 247, 122, 254, ++ 3, 70, 72, 177, 33, 70, 255, 247, 139, 254, 3, 70, 32, 177, 41, 70, ++ 4, 34, 202, 247, 15, 250, 4, 35, 24, 70, 56, 189, 56, 181, 29, 70, 20, ++ 70, 255, 247, 103, 254, 3, 70, 80, 177, 33, 70, 42, 70, 255, 247, 123, ++ 254, 3, 70, 32, 177, 4, 153, 8, 34, 202, 247, 251, 249, 8, 35, 24, 70, ++ 56, 189, 56, 181, 29, 70, 20, 70, 255, 247, 83, 254, 3, 70, 88, 177, ++ 4, 155, 33, 70, 42, 70, 255, 247, 108, 254, 3, 70, 32, 177, 5, 153, ++ 10, 34, 202, 247, 230, 249, 10, 35, 24, 70, 56, 189, 56, 181, 29, 70, ++ 20, 70, 255, 247, 62, 254, 3, 70, 88, 177, 4, 155, 33, 70, 42, 70, 255, ++ 247, 87, 254, 3, 70, 32, 177, 5, 153, 10, 34, 202, 247, 209, 249, 10, ++ 35, 24, 70, 56, 189, 248, 181, 4, 70, 15, 70, 6, 29, 0, 37, 5, 224, ++ 115, 87, 187, 66, 168, 191, 59, 70, 115, 85, 1, 53, 32, 104, 255, 247, ++ 83, 254, 133, 66, 244, 211, 40, 70, 248, 189, 0, 32, 112, 71, 255, 247, ++ 233, 191, 248, 181, 5, 70, 7, 121, 70, 29, 1, 36, 5, 224, 22, 249, 1, ++ 123, 1, 52, 135, 66, 184, 191, 7, 70, 40, 104, 255, 247, 60, 254, 132, ++ 66, 120, 178, 243, 211, 248, 189, 45, 233, 240, 65, 4, 70, 136, 70, ++ 7, 29, 128, 38, 0, 37, 2, 224, 23, 248, 1, 107, 1, 53, 32, 104, 255, ++ 247, 42, 254, 133, 66, 18, 210, 115, 178, 19, 241, 128, 15, 243, 208, ++ 67, 69, 241, 208, 11, 224, 23, 249, 1, 59, 19, 241, 128, 15, 5, 208, ++ 67, 69, 3, 208, 118, 178, 179, 66, 184, 191, 30, 70, 1, 53, 32, 104, ++ 255, 247, 18, 254, 133, 66, 238, 211, 112, 178, 189, 232, 240, 129, ++ 56, 181, 4, 70, 84, 248, 4, 11, 13, 70, 255, 247, 6, 254, 41, 70, 2, ++ 70, 32, 70, 189, 232, 56, 64, 203, 243, 235, 180, 112, 181, 3, 104, ++ 10, 104, 5, 70, 147, 66, 12, 70, 6, 209, 24, 70, 255, 247, 245, 253, ++ 41, 29, 2, 70, 32, 29, 86, 224, 0, 33, 255, 247, 186, 253, 0, 33, 6, ++ 70, 32, 70, 255, 247, 181, 253, 38, 177, 24, 177, 49, 70, 22, 34, 202, ++ 247, 79, 249, 1, 33, 40, 70, 255, 247, 171, 253, 1, 33, 6, 70, 32, 70, ++ 255, 247, 166, 253, 38, 177, 24, 177, 49, 70, 22, 34, 202, 247, 64, ++ 249, 3, 33, 40, 70, 255, 247, 156, 253, 3, 33, 6, 70, 32, 70, 255, 247, ++ 151, 253, 38, 177, 24, 177, 49, 70, 22, 34, 202, 247, 49, 249, 2, 33, ++ 40, 70, 255, 247, 141, 253, 2, 33, 6, 70, 32, 70, 255, 247, 136, 253, ++ 38, 177, 24, 177, 49, 70, 22, 34, 202, 247, 34, 249, 4, 33, 40, 70, ++ 255, 247, 126, 253, 4, 33, 6, 70, 32, 70, 255, 247, 121, 253, 38, 177, ++ 24, 177, 49, 70, 22, 34, 202, 247, 19, 249, 40, 70, 5, 33, 255, 247, ++ 111, 253, 5, 33, 5, 70, 32, 70, 255, 247, 106, 253, 53, 177, 40, 177, ++ 41, 70, 22, 34, 189, 232, 112, 64, 202, 247, 2, 185, 112, 189, 248, ++ 181, 4, 70, 15, 70, 6, 29, 0, 37, 7, 224, 115, 93, 90, 178, 128, 50, ++ 28, 191, 195, 235, 7, 3, 115, 85, 1, 53, 32, 104, 255, 247, 132, 253, ++ 133, 66, 242, 211, 248, 189, 248, 181, 4, 70, 15, 70, 6, 29, 0, 37, ++ 7, 224, 115, 93, 90, 178, 128, 50, 28, 191, 199, 235, 3, 3, 115, 85, ++ 1, 53, 32, 104, 255, 247, 112, 253, 133, 66, 242, 211, 248, 189, 248, ++ 181, 4, 70, 15, 70, 6, 29, 0, 37, 9, 224, 115, 87, 19, 241, 128, 15, ++ 4, 208, 123, 67, 100, 34, 147, 251, 242, 243, 115, 85, 1, 53, 32, 104, ++ 255, 247, 90, 253, 133, 66, 240, 211, 248, 189, 56, 181, 4, 70, 11, ++ 104, 0, 104, 152, 66, 4, 209, 4, 52, 13, 29, 255, 247, 77, 253, 2, 224, ++ 0, 32, 5, 70, 4, 70, 0, 35, 6, 224, 225, 86, 234, 86, 145, 66, 184, ++ 191, 10, 70, 226, 84, 1, 51, 131, 66, 246, 209, 56, 189, 56, 181, 4, ++ 70, 11, 104, 0, 104, 152, 66, 4, 209, 4, 52, 13, 29, 255, 247, 51, 253, ++ 2, 224, 0, 32, 5, 70, 4, 70, 0, 35, 6, 224, 225, 86, 234, 86, 145, 66, ++ 168, 191, 10, 70, 226, 84, 1, 51, 131, 66, 246, 209, 56, 189, 0, 0, ++ 8, 42, 45, 233, 240, 65, 5, 70, 12, 70, 22, 70, 31, 70, 26, 217, 10, ++ 104, 17, 75, 209, 248, 4, 128, 18, 186, 154, 66, 152, 250, 136, 248, ++ 2, 208, 255, 247, 114, 252, 128, 70, 64, 70, 41, 104, 255, 247, 122, ++ 252, 134, 66, 12, 211, 40, 70, 33, 70, 66, 70, 255, 247, 78, 253, 56, ++ 96, 0, 32, 189, 232, 240, 129, 111, 240, 13, 0, 189, 232, 240, 129, ++ 111, 240, 13, 0, 189, 232, 240, 129, 0, 191, 255, 192, 239, 190, 1, ++ 42, 16, 181, 20, 70, 10, 216, 255, 247, 250, 252, 80, 177, 195, 123, ++ 35, 65, 217, 7, 5, 212, 0, 235, 132, 0, 64, 104, 16, 189, 0, 32, 16, ++ 189, 0, 32, 16, 189, 1, 42, 16, 181, 20, 70, 6, 216, 255, 247, 231, ++ 252, 32, 177, 0, 235, 132, 0, 64, 104, 16, 189, 0, 32, 16, 189, 45, ++ 233, 240, 65, 1, 43, 4, 70, 30, 70, 6, 159, 29, 216, 8, 70, 17, 70, ++ 255, 247, 213, 252, 5, 70, 216, 177, 79, 234, 134, 8, 0, 235, 8, 3, ++ 89, 104, 33, 177, 185, 66, 2, 208, 32, 70, 255, 247, 125, 253, 5, 235, ++ 8, 3, 95, 96, 1, 35, 19, 250, 6, 246, 235, 123, 0, 32, 35, 234, 6, 6, ++ 238, 115, 189, 232, 240, 129, 111, 240, 29, 0, 189, 232, 240, 129, 111, ++ 240, 29, 0, 189, 232, 240, 129, 1, 41, 112, 181, 5, 70, 12, 70, 22, ++ 70, 20, 216, 0, 33, 255, 247, 166, 252, 164, 0, 0, 25, 67, 104, 179, ++ 66, 14, 208, 1, 33, 40, 70, 255, 247, 157, 252, 4, 25, 96, 104, 198, ++ 235, 0, 14, 222, 241, 0, 0, 64, 235, 14, 0, 112, 189, 0, 32, 112, 189, ++ 1, 32, 112, 189, 8, 181, 34, 185, 255, 247, 144, 252, 24, 177, 0, 123, ++ 8, 189, 128, 32, 8, 189, 128, 32, 8, 189, 56, 181, 28, 70, 21, 70, 42, ++ 185, 255, 247, 131, 252, 40, 177, 4, 115, 40, 70, 56, 189, 111, 240, ++ 29, 0, 56, 189, 111, 240, 29, 0, 56, 189, 8, 181, 34, 185, 255, 247, ++ 117, 252, 24, 177, 64, 123, 8, 189, 128, 32, 8, 189, 128, 32, 8, 189, ++ 56, 181, 28, 70, 21, 70, 42, 185, 255, 247, 104, 252, 40, 177, 68, 115, ++ 40, 70, 56, 189, 111, 240, 29, 0, 56, 189, 111, 240, 29, 0, 56, 189, ++ 8, 181, 34, 185, 255, 247, 90, 252, 8, 177, 128, 123, 0, 224, 128, 32, ++ 64, 178, 8, 189, 8, 181, 255, 247, 81, 252, 0, 48, 24, 191, 1, 32, 8, ++ 189, 8, 181, 255, 247, 92, 252, 0, 177, 0, 136, 8, 189, 16, 181, 4, ++ 70, 8, 70, 17, 70, 255, 247, 65, 252, 1, 70, 32, 177, 32, 70, 189, 232, ++ 16, 64, 255, 247, 249, 188, 16, 189, 16, 181, 0, 33, 4, 70, 255, 247, ++ 48, 252, 3, 136, 59, 177, 255, 35, 128, 34, 195, 115, 127, 35, 67, 115, ++ 2, 115, 130, 115, 3, 116, 32, 70, 1, 33, 255, 247, 34, 252, 3, 136, ++ 59, 177, 255, 35, 128, 34, 195, 115, 127, 35, 67, 115, 2, 115, 130, ++ 115, 3, 116, 16, 189, 56, 181, 5, 70, 12, 70, 8, 70, 0, 33, 255, 247, ++ 16, 252, 3, 136, 1, 70, 19, 177, 40, 70, 255, 247, 205, 252, 1, 33, ++ 32, 70, 255, 247, 6, 252, 3, 136, 1, 70, 19, 177, 40, 70, 255, 247, ++ 195, 252, 32, 70, 189, 232, 56, 64, 210, 247, 252, 190, 16, 181, 40, ++ 32, 210, 247, 245, 254, 4, 70, 24, 177, 0, 33, 40, 34, 203, 243, 213, ++ 242, 32, 70, 16, 189, 16, 181, 12, 70, 0, 33, 255, 247, 238, 251, 64, ++ 177, 127, 35, 128, 34, 4, 128, 67, 115, 2, 115, 130, 115, 3, 116, 0, ++ 32, 16, 189, 111, 240, 29, 0, 16, 189, 56, 181, 2, 34, 12, 70, 0, 35, ++ 5, 70, 44, 240, 116, 217, 212, 248, 204, 48, 1, 34, 155, 4, 72, 191, ++ 19, 70, 40, 70, 88, 191, 2, 35, 33, 70, 44, 240, 104, 217, 0, 32, 56, ++ 189, 2, 104, 75, 104, 18, 104, 146, 248, 173, 32, 106, 177, 211, 248, ++ 204, 32, 82, 4, 11, 212, 154, 121, 90, 177, 66, 104, 155, 88, 24, 125, ++ 0, 40, 20, 191, 8, 32, 0, 32, 112, 71, 16, 70, 112, 71, 0, 32, 112, ++ 71, 16, 70, 112, 71, 2, 104, 75, 104, 18, 104, 146, 248, 173, 32, 178, ++ 177, 211, 248, 204, 32, 82, 4, 18, 212, 154, 121, 130, 177, 66, 104, ++ 154, 88, 19, 125, 99, 177, 139, 105, 40, 33, 25, 112, 6, 33, 89, 112, ++ 17, 125, 153, 112, 81, 125, 217, 112, 209, 138, 153, 128, 18, 139, 218, ++ 128, 0, 32, 112, 71, 67, 104, 240, 181, 206, 88, 135, 176, 115, 104, ++ 7, 104, 35, 240, 8, 3, 115, 96, 8, 70, 13, 70, 246, 243, 104, 242, 0, ++ 33, 0, 36, 10, 70, 56, 70, 242, 243, 144, 247, 35, 70, 56, 70, 41, 70, ++ 14, 34, 0, 148, 1, 148, 2, 148, 3, 148, 4, 148, 236, 243, 227, 243, ++ 59, 104, 52, 96, 116, 96, 147, 248, 60, 48, 107, 177, 171, 121, 91, ++ 185, 213, 248, 204, 48, 152, 4, 1, 213, 217, 3, 5, 213, 40, 70, 7, 176, ++ 189, 232, 240, 64, 15, 240, 61, 156, 7, 176, 240, 189, 247, 181, 67, ++ 104, 7, 104, 204, 88, 13, 70, 6, 70, 8, 70, 236, 243, 18, 247, 1, 170, ++ 107, 70, 56, 70, 41, 70, 45, 240, 116, 221, 35, 104, 35, 240, 2, 3, ++ 35, 96, 99, 104, 67, 240, 8, 3, 99, 96, 1, 155, 90, 28, 2, 209, 0, 154, ++ 1, 50, 2, 208, 226, 104, 147, 66, 4, 217, 48, 70, 41, 70, 255, 247, ++ 168, 255, 9, 224, 210, 26, 79, 244, 122, 115, 178, 251, 243, 242, 184, ++ 104, 33, 105, 0, 35, 224, 243, 78, 246, 254, 189, 67, 104, 240, 181, ++ 204, 88, 6, 104, 99, 104, 135, 176, 35, 240, 4, 3, 99, 96, 7, 70, 4, ++ 34, 48, 70, 13, 70, 9, 240, 144, 217, 3, 70, 16, 177, 0, 35, 35, 96, ++ 57, 224, 34, 104, 41, 70, 66, 240, 1, 2, 34, 96, 0, 144, 1, 144, 2, ++ 144, 3, 144, 4, 144, 13, 34, 48, 70, 236, 243, 123, 243, 51, 104, 147, ++ 248, 60, 48, 227, 177, 171, 121, 211, 185, 213, 248, 204, 48, 152, 4, ++ 1, 213, 217, 3, 20, 213, 40, 70, 15, 240, 48, 220, 235, 104, 48, 70, ++ 217, 104, 218, 247, 109, 249, 32, 185, 35, 104, 67, 240, 2, 3, 35, 96, ++ 14, 224, 56, 70, 41, 70, 7, 176, 189, 232, 240, 64, 255, 247, 141, 191, ++ 48, 105, 1, 33, 13, 240, 152, 221, 48, 105, 3, 33, 13, 240, 148, 221, ++ 99, 104, 67, 240, 1, 3, 99, 96, 7, 176, 240, 189, 67, 104, 45, 233, ++ 247, 67, 204, 88, 4, 35, 208, 248, 0, 128, 6, 70, 99, 96, 8, 70, 13, ++ 70, 215, 247, 107, 253, 0, 240, 249, 248, 79, 244, 122, 119, 144, 251, ++ 247, 247, 39, 177, 32, 35, 179, 251, 247, 247, 1, 55, 0, 224, 1, 39, ++ 1, 170, 107, 70, 64, 70, 41, 70, 212, 248, 8, 144, 45, 240, 224, 220, ++ 1, 154, 83, 28, 2, 209, 0, 155, 1, 51, 8, 208, 227, 104, 154, 66, 5, ++ 216, 79, 244, 122, 115, 3, 251, 23, 151, 186, 66, 4, 211, 48, 70, 41, ++ 70, 255, 247, 122, 255, 8, 224, 186, 26, 178, 251, 243, 242, 216, 248, ++ 8, 0, 33, 105, 0, 35, 224, 243, 189, 245, 189, 232, 254, 131, 248, 181, ++ 6, 104, 4, 70, 214, 248, 128, 81, 107, 104, 199, 88, 51, 104, 27, 126, ++ 0, 43, 33, 208, 48, 105, 27, 240, 25, 220, 32, 177, 176, 104, 189, 232, ++ 248, 64, 212, 247, 220, 186, 123, 104, 152, 7, 5, 213, 40, 70, 33, 70, ++ 189, 232, 248, 64, 255, 247, 162, 191, 89, 7, 5, 213, 40, 70, 33, 70, ++ 189, 232, 248, 64, 255, 247, 73, 191, 26, 7, 5, 213, 40, 70, 33, 70, ++ 189, 232, 248, 64, 255, 247, 221, 190, 248, 189, 2, 104, 90, 177, 97, ++ 177, 0, 35, 193, 24, 145, 249, 4, 16, 0, 41, 8, 219, 1, 51, 147, 66, ++ 247, 209, 0, 32, 112, 71, 16, 70, 112, 71, 1, 32, 112, 71, 1, 32, 112, ++ 71, 0, 240, 64, 115, 179, 241, 128, 127, 3, 209, 0, 240, 127, 0, 45, ++ 240, 10, 158, 255, 32, 112, 71, 0, 240, 64, 115, 179, 241, 128, 127, ++ 8, 209, 192, 178, 31, 40, 2, 217, 32, 40, 5, 208, 85, 56, 192, 8, 1, ++ 48, 112, 71, 1, 32, 112, 71, 1, 32, 112, 71, 0, 240, 64, 115, 179, 241, ++ 128, 127, 11, 209, 195, 178, 32, 43, 8, 208, 31, 43, 136, 191, 85, 59, ++ 219, 8, 1, 51, 194, 2, 3, 213, 88, 28, 112, 71, 1, 32, 112, 71, 24, ++ 70, 112, 71, 16, 181, 4, 70, 255, 247, 231, 255, 4, 244, 64, 115, 0, ++ 235, 19, 32, 16, 189, 32, 40, 112, 181, 7, 209, 65, 242, 112, 114, 65, ++ 246, 122, 32, 0, 43, 8, 191, 16, 70, 112, 189, 9, 40, 3, 217, 160, 241, ++ 87, 4, 1, 44, 51, 216, 87, 40, 3, 208, 88, 40, 8, 191, 9, 32, 0, 224, ++ 8, 32, 2, 244, 224, 36, 180, 245, 128, 63, 12, 208, 180, 245, 0, 63, ++ 11, 208, 178, 245, 64, 63, 10, 208, 178, 245, 128, 47, 12, 191, 79, ++ 244, 234, 114, 0, 34, 4, 224, 52, 34, 2, 224, 108, 34, 0, 224, 234, ++ 34, 12, 77, 0, 235, 64, 0, 44, 24, 102, 120, 40, 92, 164, 120, 112, ++ 67, 65, 67, 74, 67, 250, 32, 178, 251, 244, 242, 80, 67, 59, 177, 10, ++ 35, 88, 67, 9, 35, 4, 48, 176, 251, 243, 240, 112, 189, 0, 32, 112, ++ 189, 0, 191, 40, 82, 4, 0, 16, 240, 64, 115, 112, 181, 5, 70, 4, 209, ++ 197, 178, 79, 244, 250, 112, 104, 67, 29, 224, 179, 241, 128, 127, 31, ++ 209, 192, 178, 32, 40, 5, 244, 0, 4, 3, 209, 1, 33, 79, 244, 0, 50, ++ 12, 224, 31, 40, 1, 216, 198, 8, 2, 224, 160, 241, 85, 6, 246, 8, 1, ++ 54, 45, 240, 110, 221, 49, 70, 5, 244, 224, 34, 35, 28, 24, 191, 1, ++ 35, 255, 247, 142, 255, 0, 40, 8, 191, 79, 240, 255, 48, 112, 189, 79, ++ 240, 255, 48, 112, 189, 160, 241, 87, 3, 1, 43, 12, 217, 99, 40, 10, ++ 208, 100, 40, 8, 208, 101, 40, 6, 208, 102, 40, 4, 208, 31, 40, 4, 216, ++ 0, 240, 7, 0, 2, 224, 9, 32, 0, 224, 0, 32, 1, 75, 83, 248, 32, 0, 112, ++ 71, 0, 82, 4, 0, 0, 240, 64, 115, 179, 241, 128, 127, 192, 178, 1, 209, ++ 255, 247, 222, 191, 112, 71, 112, 181, 0, 35, 6, 70, 13, 70, 4, 224, ++ 114, 25, 210, 24, 0, 33, 81, 117, 1, 51, 90, 25, 3, 42, 247, 221, 87, ++ 36, 164, 241, 85, 3, 181, 235, 227, 15, 4, 220, 6, 241, 21, 0, 33, 70, ++ 203, 243, 147, 246, 1, 52, 103, 44, 242, 209, 112, 189, 240, 181, 4, ++ 70, 0, 104, 139, 176, 24, 179, 0, 33, 40, 34, 104, 70, 203, 243, 61, ++ 240, 0, 33, 37, 104, 0, 155, 10, 70, 14, 224, 160, 24, 0, 121, 0, 240, ++ 127, 6, 127, 46, 1, 209, 32, 117, 5, 224, 10, 175, 126, 24, 6, 248, ++ 36, 12, 1, 49, 1, 51, 1, 50, 170, 66, 238, 209, 32, 70, 64, 248, 4, ++ 59, 1, 169, 16, 34, 0, 147, 201, 247, 159, 252, 1, 32, 11, 176, 240, ++ 189, 240, 181, 157, 176, 4, 70, 13, 70, 22, 70, 104, 70, 0, 33, 109, ++ 34, 203, 243, 18, 240, 32, 104, 0, 35, 13, 224, 226, 24, 17, 121, 1, ++ 240, 127, 2, 108, 42, 6, 216, 25, 79, 191, 92, 31, 177, 28, 175, 186, ++ 24, 2, 248, 112, 28, 1, 51, 131, 66, 239, 209, 0, 35, 40, 104, 26, 70, ++ 12, 224, 233, 24, 9, 121, 28, 175, 1, 240, 127, 1, 121, 24, 17, 248, ++ 112, 28, 17, 177, 167, 24, 57, 113, 1, 50, 1, 51, 131, 66, 240, 209, ++ 34, 96, 0, 35, 34, 70, 233, 24, 72, 125, 81, 125, 1, 51, 1, 64, 81, ++ 117, 1, 50, 16, 43, 246, 209, 32, 70, 49, 70, 255, 247, 141, 254, 0, ++ 48, 24, 191, 1, 32, 29, 176, 240, 189, 0, 191, 224, 248, 135, 0, 66, ++ 120, 3, 120, 18, 2, 154, 24, 192, 120, 2, 244, 224, 83, 155, 10, 1, ++ 51, 0, 9, 17, 7, 72, 191, 91, 8, 64, 240, 128, 0, 64, 234, 3, 16, 112, ++ 71, 16, 181, 4, 70, 255, 247, 234, 255, 35, 120, 98, 120, 33, 121, 67, ++ 234, 2, 34, 227, 120, 0, 240, 127, 0, 67, 234, 1, 35, 64, 240, 0, 113, ++ 2, 240, 3, 0, 1, 48, 65, 234, 0, 64, 17, 7, 72, 191, 64, 244, 128, 16, ++ 218, 7, 72, 191, 64, 244, 0, 0, 91, 7, 72, 191, 64, 244, 128, 0, 16, ++ 189, 16, 181, 131, 136, 12, 70, 3, 240, 3, 3, 2, 43, 17, 208, 3, 43, ++ 45, 208, 1, 43, 4, 208, 8, 120, 5, 35, 176, 251, 243, 240, 5, 224, 246, ++ 247, 174, 249, 35, 120, 3, 240, 7, 3, 192, 92, 64, 244, 128, 48, 16, ++ 189, 10, 120, 227, 120, 9, 121, 2, 240, 127, 0, 18, 6, 88, 191, 64, ++ 240, 128, 112, 67, 234, 1, 35, 76, 191, 64, 240, 129, 112, 64, 244, ++ 128, 48, 25, 6, 72, 191, 64, 244, 0, 0, 90, 6, 72, 191, 64, 244, 128, ++ 0, 19, 240, 48, 15, 7, 208, 64, 244, 128, 16, 16, 189, 8, 70, 189, 232, ++ 16, 64, 255, 247, 162, 191, 16, 189, 3, 70, 40, 34, 8, 70, 25, 70, 201, ++ 247, 221, 187, 0, 0, 17, 74, 45, 233, 240, 65, 208, 248, 0, 192, 23, ++ 104, 0, 35, 22, 70, 21, 224, 193, 24, 181, 24, 12, 121, 45, 121, 133, ++ 234, 4, 8, 24, 240, 127, 15, 2, 209, 42, 6, 9, 213, 5, 224, 1, 50, 0, ++ 224, 0, 34, 186, 66, 238, 209, 2, 224, 100, 240, 127, 4, 12, 113, 1, ++ 51, 99, 69, 245, 209, 189, 232, 240, 129, 0, 191, 184, 248, 135, 0, ++ 16, 181, 0, 35, 7, 74, 217, 0, 82, 248, 51, 64, 160, 66, 2, 209, 82, ++ 24, 16, 121, 4, 224, 1, 51, 12, 43, 243, 209, 79, 246, 255, 112, 0, ++ 178, 16, 189, 72, 82, 4, 0, 45, 233, 247, 79, 3, 104, 79, 244, 250, ++ 121, 195, 24, 147, 248, 3, 128, 157, 248, 52, 160, 8, 240, 127, 8, 9, ++ 251, 8, 249, 4, 70, 1, 145, 147, 70, 0, 38, 163, 25, 91, 125, 0, 43, ++ 56, 208, 245, 0, 237, 178, 0, 39, 102, 45, 51, 216, 4, 241, 21, 0, 41, ++ 70, 203, 243, 154, 245, 56, 187, 31, 45, 1, 216, 235, 8, 7, 224, 32, ++ 45, 7, 208, 181, 241, 85, 3, 72, 191, 165, 241, 78, 3, 219, 16, 1, 51, ++ 0, 224, 1, 35, 83, 69, 22, 220, 1, 155, 1, 43, 6, 191, 69, 240, 128, ++ 115, 67, 244, 128, 51, 69, 240, 129, 115, 187, 241, 0, 15, 1, 208, 67, ++ 244, 0, 3, 24, 70, 0, 147, 255, 247, 40, 254, 0, 155, 72, 69, 132, 191, ++ 129, 70, 152, 70, 1, 55, 255, 178, 1, 53, 8, 47, 237, 178, 201, 209, ++ 1, 54, 16, 46, 191, 209, 64, 70, 189, 232, 254, 143, 0, 35, 194, 24, ++ 1, 51, 0, 33, 16, 43, 81, 117, 249, 209, 112, 71, 0, 0, 45, 233, 240, ++ 71, 31, 70, 0, 35, 12, 70, 5, 70, 221, 248, 32, 128, 157, 248, 36, 96, ++ 208, 248, 0, 144, 25, 70, 41, 224, 104, 24, 0, 121, 18, 177, 16, 240, ++ 128, 15, 34, 208, 1, 47, 9, 209, 223, 248, 148, 160, 0, 240, 127, 12, ++ 26, 249, 12, 192, 188, 241, 0, 15, 16, 218, 22, 224, 2, 47, 13, 209, ++ 0, 240, 127, 12, 188, 241, 2, 15, 15, 208, 188, 241, 4, 15, 12, 208, ++ 188, 241, 11, 15, 9, 208, 188, 241, 22, 15, 6, 208, 4, 235, 3, 12, 0, ++ 234, 8, 0, 140, 248, 4, 0, 1, 51, 1, 49, 73, 69, 211, 209, 2, 47, 35, ++ 96, 5, 209, 184, 241, 255, 15, 2, 209, 32, 70, 255, 247, 37, 255, 43, ++ 125, 240, 7, 35, 117, 18, 213, 1, 47, 16, 208, 165, 66, 6, 208, 4, 241, ++ 21, 0, 5, 241, 21, 1, 16, 34, 201, 247, 242, 250, 113, 7, 11, 212, 4, ++ 241, 21, 0, 189, 232, 240, 71, 45, 240, 60, 155, 32, 70, 255, 247, 154, ++ 255, 79, 240, 255, 51, 227, 132, 189, 232, 240, 135, 224, 248, 135, ++ 0, 56, 181, 16, 34, 4, 70, 13, 70, 21, 48, 4, 73, 201, 247, 216, 250, ++ 32, 70, 41, 70, 189, 232, 56, 64, 255, 247, 239, 189, 33, 240, 135, ++ 0, 40, 41, 0, 241, 21, 0, 79, 240, 32, 1, 1, 209, 204, 243, 18, 176, ++ 203, 243, 142, 180, 45, 233, 240, 65, 140, 176, 26, 75, 157, 248, 84, ++ 128, 25, 78, 7, 70, 184, 241, 20, 15, 8, 191, 30, 70, 0, 41, 24, 191, ++ 14, 70, 157, 248, 88, 64, 48, 70, 2, 169, 157, 248, 80, 80, 255, 247, ++ 204, 254, 2, 168, 65, 70, 255, 247, 219, 255, 2, 168, 33, 70, 255, 247, ++ 196, 253, 19, 155, 0, 34, 141, 232, 40, 0, 157, 248, 72, 48, 2, 168, ++ 155, 26, 24, 191, 1, 35, 57, 70, 255, 247, 86, 255, 0, 34, 56, 70, 49, ++ 70, 149, 66, 20, 191, 35, 70, 1, 35, 255, 247, 245, 253, 12, 176, 189, ++ 232, 240, 129, 12, 240, 135, 0, 228, 239, 135, 0, 111, 240, 22, 0, 112, ++ 71, 0, 0, 5, 75, 0, 32, 83, 248, 4, 47, 138, 66, 4, 208, 1, 48, 192, ++ 178, 43, 40, 247, 209, 0, 32, 112, 71, 188, 82, 4, 0, 144, 248, 194, ++ 48, 19, 240, 1, 3, 26, 191, 64, 24, 144, 248, 43, 0, 24, 70, 112, 71, ++ 240, 181, 3, 70, 144, 248, 208, 64, 144, 248, 183, 96, 13, 224, 29, ++ 25, 149, 248, 148, 112, 32, 70, 151, 66, 5, 211, 47, 122, 5, 77, 21, ++ 248, 39, 80, 141, 66, 5, 208, 1, 52, 228, 178, 180, 66, 239, 211, 79, ++ 240, 255, 48, 240, 189, 192, 82, 4, 0, 248, 181, 30, 70, 144, 248, 193, ++ 48, 21, 70, 195, 24, 36, 79, 26, 122, 1, 41, 4, 70, 147, 248, 148, 192, ++ 87, 248, 34, 0, 7, 209, 147, 248, 78, 48, 43, 112, 148, 248, 193, 32, ++ 154, 66, 41, 209, 52, 224, 1, 49, 50, 209, 147, 248, 113, 32, 42, 112, ++ 148, 248, 193, 48, 147, 66, 45, 208, 64, 234, 12, 67, 19, 240, 64, 127, ++ 26, 209, 3, 240, 127, 3, 22, 43, 22, 216, 20, 74, 154, 64, 19, 213, ++ 99, 104, 154, 126, 130, 177, 148, 248, 214, 32, 106, 177, 211, 248, ++ 140, 32, 82, 177, 32, 104, 144, 71, 99, 104, 179, 249, 24, 48, 152, ++ 66, 3, 219, 148, 248, 193, 48, 43, 112, 11, 224, 43, 120, 1, 32, 228, ++ 24, 35, 122, 148, 248, 148, 32, 87, 248, 35, 48, 67, 234, 2, 67, 51, ++ 96, 248, 189, 0, 32, 248, 189, 0, 32, 248, 189, 192, 82, 4, 0, 0, 2, ++ 16, 40, 56, 181, 144, 248, 193, 16, 4, 70, 255, 247, 128, 255, 32, 24, ++ 21, 73, 3, 122, 144, 248, 148, 32, 148, 248, 193, 0, 81, 248, 35, 48, ++ 32, 24, 67, 234, 2, 67, 2, 122, 144, 248, 148, 80, 81, 248, 34, 32, ++ 212, 248, 16, 17, 66, 234, 5, 66, 145, 66, 5, 208, 196, 248, 16, 33, ++ 79, 244, 128, 82, 196, 248, 20, 33, 212, 248, 52, 33, 154, 66, 3, 209, ++ 212, 248, 56, 33, 1, 50, 5, 209, 196, 248, 52, 49, 79, 244, 128, 83, ++ 196, 248, 56, 49, 56, 189, 192, 82, 4, 0, 144, 248, 194, 32, 67, 104, ++ 7, 42, 2, 209, 147, 248, 152, 0, 112, 71, 210, 7, 3, 213, 147, 248, ++ 152, 0, 64, 8, 112, 71, 4, 32, 112, 71, 112, 181, 144, 248, 210, 48, ++ 4, 70, 13, 70, 0, 43, 0, 240, 217, 128, 144, 248, 193, 32, 144, 248, ++ 208, 48, 154, 66, 192, 240, 212, 128, 144, 249, 211, 96, 255, 247, 221, ++ 255, 113, 28, 1, 208, 12, 46, 33, 209, 99, 104, 212, 248, 112, 33, 91, ++ 104, 155, 106, 147, 66, 4, 210, 148, 248, 116, 17, 211, 26, 139, 66, ++ 4, 217, 0, 35, 132, 248, 211, 48, 93, 185, 97, 224, 0, 45, 95, 208, ++ 12, 46, 6, 209, 148, 248, 64, 49, 131, 66, 2, 211, 0, 35, 132, 248, ++ 211, 48, 148, 249, 211, 0, 0, 40, 85, 208, 0, 38, 89, 224, 0, 46, 87, ++ 208, 0, 45, 0, 240, 167, 128, 148, 248, 211, 32, 148, 249, 106, 17, ++ 83, 178, 153, 66, 0, 240, 161, 128, 132, 248, 106, 33, 148, 248, 64, ++ 33, 130, 66, 9, 210, 212, 248, 108, 33, 10, 33, 81, 67, 212, 248, 20, ++ 33, 2, 235, 194, 2, 145, 66, 3, 210, 255, 35, 132, 248, 211, 48, 6, ++ 224, 11, 43, 4, 209, 12, 35, 132, 248, 211, 48, 1, 35, 0, 224, 0, 35, ++ 148, 248, 211, 16, 74, 30, 210, 178, 10, 42, 38, 217, 98, 104, 148, ++ 248, 116, 1, 86, 104, 182, 106, 134, 25, 196, 248, 112, 97, 148, 248, ++ 117, 97, 158, 66, 8, 209, 146, 248, 154, 48, 64, 0, 152, 66, 168, 191, ++ 24, 70, 132, 248, 116, 1, 5, 224, 146, 248, 153, 32, 132, 248, 117, ++ 49, 132, 248, 116, 33, 12, 41, 12, 209, 212, 248, 108, 49, 196, 248, ++ 20, 49, 7, 224, 46, 70, 40, 70, 6, 224, 1, 38, 4, 224, 0, 38, 1, 32, ++ 1, 224, 1, 38, 48, 70, 148, 249, 211, 48, 0, 43, 65, 209, 213, 177, ++ 79, 244, 128, 82, 196, 248, 20, 33, 196, 248, 56, 33, 98, 104, 196, ++ 248, 188, 48, 82, 104, 146, 106, 196, 248, 60, 33, 79, 240, 255, 50, ++ 196, 248, 44, 33, 196, 248, 32, 33, 148, 248, 192, 32, 2, 42, 152, 191, ++ 83, 28, 132, 248, 192, 48, 1, 38, 99, 104, 212, 248, 188, 32, 91, 123, ++ 154, 66, 31, 211, 148, 248, 64, 49, 227, 185, 148, 248, 245, 48, 218, ++ 7, 24, 212, 180, 248, 0, 49, 219, 7, 20, 212, 148, 248, 193, 48, 148, ++ 248, 210, 32, 227, 24, 147, 248, 148, 48, 82, 250, 3, 243, 217, 7, 9, ++ 213, 212, 248, 20, 49, 1, 32, 132, 248, 211, 0, 132, 248, 106, 1, 196, ++ 248, 108, 49, 0, 224, 102, 177, 212, 248, 196, 48, 75, 177, 0, 34, 26, ++ 96, 112, 189, 24, 70, 112, 189, 0, 32, 112, 189, 1, 32, 112, 189, 1, ++ 32, 112, 189, 208, 248, 204, 48, 48, 181, 1, 43, 26, 209, 144, 248, ++ 245, 32, 2, 240, 17, 1, 16, 41, 59, 209, 208, 248, 188, 16, 208, 248, ++ 228, 64, 100, 24, 144, 248, 246, 16, 180, 251, 241, 245, 1, 251, 21, ++ 65, 144, 248, 247, 80, 169, 66, 44, 209, 66, 240, 1, 2, 128, 248, 245, ++ 32, 24, 70, 48, 189, 2, 43, 36, 209, 176, 248, 0, 49, 19, 240, 1, 4, ++ 31, 209, 176, 248, 10, 33, 242, 177, 208, 248, 228, 80, 208, 248, 188, ++ 16, 105, 24, 177, 251, 242, 245, 2, 251, 21, 18, 176, 248, 12, 81, 170, ++ 66, 19, 209, 144, 248, 8, 33, 18, 185, 3, 244, 128, 114, 1, 224, 3, ++ 240, 16, 2, 146, 178, 90, 177, 67, 240, 1, 3, 160, 248, 0, 49, 1, 32, ++ 48, 189, 0, 32, 48, 189, 16, 70, 48, 189, 32, 70, 48, 189, 16, 70, 48, ++ 189, 16, 181, 144, 248, 194, 48, 4, 70, 7, 43, 7, 208, 7, 35, 128, 248, ++ 194, 48, 208, 248, 196, 48, 11, 177, 0, 34, 26, 96, 99, 104, 147, 248, ++ 145, 32, 122, 177, 210, 7, 3, 213, 90, 104, 146, 106, 196, 248, 100, ++ 33, 147, 248, 145, 32, 144, 7, 5, 213, 211, 248, 140, 48, 32, 104, 152, ++ 71, 196, 248, 96, 1, 16, 189, 112, 181, 69, 104, 4, 70, 149, 248, 145, ++ 48, 14, 70, 0, 43, 49, 208, 144, 248, 194, 32, 209, 7, 45, 213, 218, ++ 7, 8, 213, 106, 104, 145, 106, 208, 248, 100, 33, 137, 26, 181, 248, ++ 150, 32, 145, 66, 34, 219, 153, 7, 21, 213, 212, 248, 96, 49, 235, 177, ++ 213, 248, 140, 48, 32, 104, 152, 71, 16, 241, 65, 15, 22, 218, 212, ++ 248, 96, 49, 181, 249, 146, 32, 19, 241, 65, 15, 168, 191, 111, 240, ++ 64, 3, 27, 26, 147, 66, 10, 221, 148, 248, 194, 48, 3, 240, 253, 3, ++ 132, 248, 194, 48, 30, 185, 35, 240, 1, 3, 132, 248, 194, 48, 112, 189, ++ 144, 248, 41, 48, 128, 248, 70, 48, 0, 35, 67, 101, 3, 101, 195, 100, ++ 112, 71, 195, 108, 130, 108, 17, 177, 147, 66, 6, 210, 12, 224, 29, ++ 33, 74, 67, 178, 235, 67, 31, 34, 217, 6, 224, 144, 248, 70, 48, 128, ++ 248, 69, 48, 0, 35, 131, 100, 23, 224, 144, 248, 69, 48, 128, 248, 70, ++ 48, 176, 248, 88, 48, 91, 0, 179, 245, 32, 127, 168, 191, 79, 244, 32, ++ 115, 160, 248, 88, 48, 176, 248, 90, 48, 91, 0, 179, 245, 72, 111, 168, ++ 191, 79, 244, 72, 99, 160, 248, 90, 48, 0, 35, 3, 101, 67, 101, 112, ++ 71, 48, 181, 144, 248, 69, 80, 144, 248, 70, 64, 10, 70, 172, 66, 29, ++ 209, 144, 248, 41, 16, 161, 66, 50, 208, 1, 42, 10, 208, 2, 42, 12, ++ 208, 0, 42, 44, 209, 40, 34, 160, 248, 88, 32, 200, 34, 160, 248, 90, ++ 32, 8, 224, 176, 248, 88, 32, 67, 109, 2, 224, 176, 248, 90, 32, 3, ++ 109, 147, 66, 28, 211, 189, 232, 48, 64, 255, 247, 162, 191, 1, 41, ++ 2, 208, 2, 41, 20, 209, 5, 224, 176, 248, 92, 32, 67, 109, 147, 66, ++ 14, 211, 9, 224, 2, 109, 176, 248, 94, 48, 154, 66, 1, 211, 1, 33, 2, ++ 224, 4, 42, 4, 217, 0, 33, 189, 232, 48, 64, 255, 247, 146, 191, 48, ++ 189, 48, 181, 3, 70, 64, 104, 144, 248, 40, 32, 1, 42, 80, 217, 179, ++ 248, 14, 33, 1, 50, 146, 178, 10, 42, 163, 248, 14, 33, 72, 217, 0, ++ 34, 163, 248, 14, 33, 144, 248, 67, 48, 97, 240, 127, 4, 194, 24, 23, ++ 43, 130, 248, 42, 64, 2, 208, 1, 51, 219, 178, 0, 224, 0, 35, 1, 240, ++ 7, 2, 132, 24, 148, 248, 32, 80, 128, 248, 67, 48, 1, 53, 132, 248, ++ 32, 80, 179, 241, 19, 4, 72, 191, 92, 29, 4, 25, 148, 248, 42, 48, 19, ++ 240, 128, 15, 7, 208, 3, 240, 7, 3, 195, 24, 147, 248, 32, 64, 1, 60, ++ 131, 248, 32, 64, 130, 24, 146, 248, 32, 32, 144, 248, 41, 48, 13, 42, ++ 10, 217, 1, 240, 7, 1, 139, 66, 6, 208, 144, 248, 68, 48, 128, 248, ++ 41, 16, 99, 177, 0, 33, 6, 224, 144, 248, 68, 48, 59, 177, 67, 109, ++ 1, 33, 1, 51, 67, 101, 189, 232, 48, 64, 255, 247, 104, 191, 48, 189, ++ 48, 181, 100, 36, 76, 67, 180, 251, 243, 245, 84, 67, 3, 154, 237, 178, ++ 83, 67, 100, 61, 5, 235, 213, 117, 109, 16, 100, 53, 237, 178, 180, ++ 251, 243, 244, 165, 66, 128, 248, 88, 81, 140, 191, 0, 37, 1, 37, 1, ++ 35, 128, 248, 84, 81, 128, 248, 85, 49, 48, 189, 145, 66, 52, 191, 0, ++ 34, 1, 34, 1, 35, 128, 248, 86, 33, 128, 248, 87, 49, 112, 71, 45, 233, ++ 240, 65, 30, 70, 144, 248, 243, 48, 4, 70, 255, 43, 6, 157, 0, 240, ++ 188, 128, 255, 42, 0, 240, 185, 128, 0, 45, 0, 240, 185, 128, 144, 248, ++ 242, 48, 83, 64, 19, 240, 120, 15, 64, 240, 181, 128, 67, 104, 27, 122, ++ 0, 43, 97, 208, 144, 248, 209, 0, 66, 240, 128, 114, 66, 234, 0, 64, ++ 255, 247, 211, 249, 148, 248, 193, 48, 79, 244, 250, 120, 227, 24, 144, ++ 251, 248, 247, 26, 122, 147, 248, 148, 0, 81, 75, 54, 3, 83, 248, 34, ++ 48, 126, 67, 67, 234, 0, 64, 255, 247, 192, 249, 212, 248, 20, 49, 144, ++ 251, 248, 240, 67, 67, 184, 66, 182, 251, 245, 245, 3, 217, 29, 34, ++ 83, 67, 91, 9, 3, 224, 2, 210, 29, 34, 85, 67, 109, 9, 212, 248, 224, ++ 32, 34, 185, 196, 248, 68, 81, 196, 248, 72, 49, 97, 224, 17, 42, 212, ++ 248, 68, 17, 15, 216, 80, 30, 1, 251, 0, 85, 212, 248, 72, 17, 181, ++ 251, 242, 245, 1, 251, 0, 51, 179, 251, 242, 242, 196, 248, 68, 81, ++ 196, 248, 72, 33, 77, 224, 98, 104, 208, 122, 49, 250, 0, 240, 9, 26, ++ 196, 248, 68, 17, 208, 122, 197, 64, 105, 24, 196, 248, 68, 17, 212, ++ 248, 72, 1, 209, 122, 48, 250, 1, 241, 65, 26, 196, 248, 72, 17, 210, ++ 122, 211, 64, 89, 24, 196, 248, 72, 17, 51, 224, 144, 248, 240, 32, ++ 174, 27, 2, 240, 7, 7, 1, 32, 184, 64, 117, 66, 69, 235, 6, 5, 21, 250, ++ 7, 247, 4, 235, 210, 1, 145, 248, 236, 96, 192, 178, 7, 64, 38, 234, ++ 0, 0, 56, 67, 23, 42, 129, 248, 236, 0, 1, 208, 83, 28, 219, 178, 179, ++ 241, 19, 2, 72, 191, 90, 29, 132, 248, 240, 48, 1, 32, 2, 240, 7, 3, ++ 152, 64, 4, 235, 226, 2, 146, 248, 236, 16, 148, 248, 239, 96, 0, 234, ++ 1, 2, 82, 250, 3, 243, 173, 25, 237, 178, 235, 26, 132, 248, 239, 48, ++ 212, 248, 224, 48, 89, 28, 2, 208, 1, 51, 196, 248, 224, 48, 212, 248, ++ 228, 48, 90, 28, 2, 208, 1, 51, 196, 248, 228, 48, 148, 248, 243, 48, ++ 1, 32, 132, 248, 244, 48, 189, 232, 240, 129, 0, 32, 189, 232, 240, ++ 129, 40, 70, 189, 232, 240, 129, 0, 32, 189, 232, 240, 129, 0, 191, ++ 192, 82, 4, 0, 45, 233, 248, 67, 144, 248, 193, 192, 4, 70, 96, 68, ++ 117, 73, 7, 122, 9, 157, 8, 158, 81, 248, 39, 112, 144, 248, 148, 0, ++ 137, 70, 0, 45, 0, 240, 215, 128, 71, 234, 0, 71, 148, 248, 8, 17, 23, ++ 240, 64, 127, 20, 191, 255, 178, 255, 39, 49, 185, 151, 66, 2, 209, ++ 148, 248, 252, 0, 12, 224, 8, 70, 16, 224, 1, 41, 64, 240, 198, 128, ++ 151, 66, 10, 208, 122, 64, 18, 240, 120, 0, 7, 208, 148, 248, 253, 0, ++ 195, 26, 88, 66, 64, 235, 3, 0, 0, 224, 0, 32, 192, 178, 0, 40, 0, 240, ++ 184, 128, 9, 177, 148, 248, 254, 192, 99, 104, 27, 122, 0, 43, 99, 208, ++ 4, 235, 12, 3, 147, 248, 148, 0, 27, 122, 79, 244, 250, 120, 89, 248, ++ 35, 48, 54, 3, 67, 234, 0, 64, 255, 247, 215, 248, 148, 248, 193, 48, ++ 144, 251, 248, 247, 227, 24, 147, 248, 148, 0, 27, 122, 126, 67, 89, ++ 248, 35, 48, 67, 234, 0, 64, 255, 247, 200, 248, 212, 248, 20, 49, 144, ++ 251, 248, 240, 67, 67, 184, 66, 182, 251, 245, 245, 3, 217, 29, 34, ++ 83, 67, 91, 9, 3, 224, 2, 210, 29, 34, 85, 67, 109, 9, 212, 248, 224, ++ 32, 34, 185, 196, 248, 76, 81, 196, 248, 80, 49, 98, 224, 17, 42, 212, ++ 248, 76, 17, 15, 216, 80, 30, 1, 251, 0, 85, 212, 248, 80, 17, 181, ++ 251, 242, 245, 1, 251, 0, 51, 179, 251, 242, 242, 196, 248, 76, 81, ++ 196, 248, 80, 33, 78, 224, 98, 104, 208, 122, 49, 250, 0, 240, 9, 26, ++ 196, 248, 76, 17, 208, 122, 197, 64, 105, 24, 196, 248, 76, 17, 212, ++ 248, 80, 1, 209, 122, 48, 250, 1, 241, 65, 26, 196, 248, 80, 17, 210, ++ 122, 211, 64, 89, 24, 196, 248, 80, 17, 52, 224, 148, 248, 2, 33, 174, ++ 27, 2, 240, 7, 7, 1, 32, 184, 64, 117, 66, 69, 235, 6, 5, 21, 250, 7, ++ 247, 4, 235, 210, 1, 145, 248, 5, 97, 192, 178, 7, 64, 38, 234, 0, 0, ++ 56, 67, 29, 42, 129, 248, 5, 1, 1, 208, 83, 28, 219, 178, 179, 241, ++ 19, 2, 72, 191, 3, 241, 11, 2, 132, 248, 2, 49, 1, 32, 2, 240, 7, 3, ++ 152, 64, 4, 235, 226, 2, 146, 248, 5, 17, 148, 248, 3, 97, 0, 234, 1, ++ 2, 82, 250, 3, 243, 173, 25, 237, 178, 235, 26, 132, 248, 3, 49, 212, ++ 248, 224, 48, 89, 28, 2, 208, 1, 51, 196, 248, 224, 48, 212, 248, 228, ++ 48, 90, 28, 11, 208, 1, 51, 196, 248, 228, 48, 1, 32, 189, 232, 248, ++ 131, 40, 70, 189, 232, 248, 131, 0, 32, 189, 232, 248, 131, 1, 32, 189, ++ 232, 248, 131, 192, 82, 4, 0, 45, 233, 240, 79, 133, 176, 157, 248, ++ 56, 176, 154, 70, 157, 248, 76, 48, 4, 70, 0, 43, 24, 191, 79, 240, ++ 1, 11, 21, 70, 157, 248, 60, 144, 157, 248, 64, 128, 157, 248, 68, 112, ++ 157, 248, 80, 96, 255, 247, 80, 251, 148, 248, 193, 32, 105, 75, 162, ++ 24, 146, 248, 148, 16, 18, 122, 83, 248, 34, 48, 67, 234, 1, 67, 212, ++ 248, 204, 16, 218, 178, 1, 41, 11, 209, 186, 66, 44, 208, 193, 69, 17, ++ 210, 32, 70, 58, 70, 43, 70, 205, 248, 0, 160, 255, 247, 7, 254, 26, ++ 224, 2, 41, 29, 209, 186, 66, 3, 209, 148, 248, 251, 32, 178, 66, 26, ++ 208, 193, 69, 8, 211, 212, 248, 232, 48, 88, 28, 0, 240, 165, 128, 1, ++ 51, 196, 248, 232, 48, 160, 224, 32, 70, 1, 33, 58, 70, 51, 70, 141, ++ 232, 32, 4, 255, 247, 189, 254, 0, 40, 20, 191, 1, 32, 2, 32, 150, 224, ++ 151, 66, 64, 240, 145, 128, 29, 177, 193, 69, 8, 216, 0, 34, 4, 224, ++ 193, 69, 4, 211, 148, 248, 64, 33, 1, 50, 132, 248, 64, 33, 98, 104, ++ 210, 126, 18, 185, 193, 69, 127, 210, 7, 224, 193, 69, 5, 217, 186, ++ 235, 69, 15, 212, 191, 2, 32, 0, 32, 121, 224, 187, 241, 0, 15, 11, ++ 209, 186, 241, 0, 15, 8, 208, 85, 69, 6, 209, 193, 69, 4, 210, 32, 70, ++ 3, 147, 255, 247, 101, 252, 3, 155, 148, 248, 249, 32, 98, 177, 98, ++ 104, 212, 248, 216, 16, 82, 127, 145, 66, 6, 211, 212, 248, 196, 32, ++ 0, 33, 132, 248, 249, 16, 2, 177, 17, 96, 193, 69, 3, 211, 212, 248, ++ 52, 33, 154, 66, 17, 209, 157, 248, 72, 48, 91, 177, 148, 248, 211, ++ 48, 90, 30, 210, 178, 10, 42, 5, 216, 1, 51, 4, 245, 182, 118, 132, ++ 248, 211, 48, 4, 224, 4, 245, 138, 118, 1, 224, 4, 245, 156, 118, 148, ++ 248, 194, 48, 45, 3, 149, 251, 250, 245, 67, 177, 99, 104, 212, 248, ++ 188, 16, 90, 123, 145, 66, 148, 191, 31, 123, 223, 122, 0, 224, 2, 39, ++ 99, 104, 27, 104, 27, 104, 147, 248, 229, 48, 67, 177, 4, 245, 138, ++ 115, 158, 66, 4, 209, 32, 70, 41, 70, 50, 104, 255, 247, 103, 253, 51, ++ 104, 253, 64, 51, 250, 7, 247, 237, 24, 235, 27, 51, 96, 4, 245, 156, ++ 115, 158, 66, 4, 209, 99, 104, 91, 104, 155, 106, 196, 248, 60, 49, ++ 212, 248, 216, 48, 89, 28, 2, 208, 1, 51, 196, 248, 216, 48, 212, 248, ++ 188, 48, 90, 28, 5, 208, 1, 51, 196, 248, 188, 48, 1, 224, 2, 32, 0, ++ 224, 0, 32, 5, 176, 189, 232, 240, 143, 192, 82, 4, 0, 56, 181, 8, 70, ++ 29, 70, 20, 70, 254, 247, 58, 255, 168, 66, 5, 211, 52, 177, 160, 66, ++ 140, 191, 0, 32, 1, 32, 56, 189, 0, 32, 56, 189, 1, 32, 56, 189, 112, ++ 181, 5, 70, 144, 248, 183, 64, 14, 70, 129, 185, 20, 224, 43, 25, 147, ++ 248, 148, 0, 26, 122, 12, 75, 83, 248, 34, 48, 67, 234, 0, 64, 254, ++ 247, 28, 255, 134, 66, 7, 217, 1, 52, 228, 178, 0, 224, 0, 36, 149, ++ 248, 183, 48, 163, 66, 234, 216, 149, 248, 183, 48, 163, 66, 1, 209, ++ 1, 60, 228, 178, 32, 70, 112, 189, 192, 82, 4, 0, 56, 181, 0, 37, 4, ++ 70, 192, 248, 232, 80, 192, 248, 224, 80, 41, 70, 236, 48, 3, 34, 201, ++ 243, 178, 247, 132, 248, 239, 80, 132, 248, 240, 80, 196, 248, 68, 81, ++ 196, 248, 72, 81, 56, 189, 0, 0, 208, 248, 224, 48, 112, 181, 17, 43, ++ 4, 70, 77, 217, 144, 248, 243, 16, 144, 248, 193, 32, 145, 66, 71, 208, ++ 144, 248, 183, 48, 139, 66, 67, 217, 130, 24, 16, 122, 34, 75, 146, ++ 248, 148, 32, 83, 248, 32, 48, 96, 104, 0, 122, 48, 177, 212, 248, 68, ++ 81, 212, 248, 72, 1, 133, 66, 12, 217, 7, 224, 148, 249, 239, 80, 148, ++ 248, 248, 0, 197, 241, 18, 5, 133, 66, 3, 220, 132, 248, 193, 16, 1, ++ 32, 112, 189, 219, 178, 1, 51, 30, 43, 34, 216, 148, 248, 214, 16, 2, ++ 41, 6, 217, 148, 249, 241, 96, 214, 241, 1, 6, 56, 191, 0, 38, 0, 224, ++ 0, 38, 3, 235, 131, 3, 13, 73, 155, 25, 81, 248, 35, 80, 107, 28, 14, ++ 208, 32, 70, 233, 178, 255, 247, 113, 249, 0, 40, 10, 221, 132, 248, ++ 243, 0, 132, 248, 241, 96, 132, 248, 242, 80, 32, 70, 255, 247, 150, ++ 255, 0, 32, 112, 189, 0, 32, 112, 189, 192, 82, 4, 0, 180, 85, 4, 0, ++ 45, 233, 240, 71, 144, 248, 193, 48, 4, 70, 195, 24, 147, 248, 148, ++ 32, 25, 122, 164, 75, 83, 248, 33, 96, 70, 234, 2, 70, 22, 240, 64, ++ 127, 6, 208, 245, 178, 87, 45, 6, 208, 88, 45, 8, 191, 9, 37, 3, 224, ++ 79, 240, 255, 53, 0, 224, 8, 37, 212, 248, 204, 48, 111, 28, 1, 43, ++ 81, 209, 148, 248, 241, 48, 105, 28, 95, 250, 131, 248, 30, 208, 150, ++ 73, 91, 178, 7, 235, 135, 0, 192, 24, 81, 248, 32, 80, 104, 28, 15, ++ 209, 148, 248, 214, 0, 2, 40, 4, 217, 211, 241, 1, 8, 56, 191, 79, 240, ++ 0, 8, 7, 235, 135, 3, 67, 68, 81, 248, 35, 80, 104, 28, 5, 208, 32, ++ 70, 233, 178, 255, 247, 26, 249, 129, 70, 0, 224, 169, 70, 0, 35, 153, ++ 69, 132, 248, 245, 48, 34, 219, 148, 248, 242, 48, 107, 64, 19, 240, ++ 120, 15, 2, 208, 32, 70, 255, 247, 57, 255, 148, 248, 245, 48, 20, 34, ++ 67, 240, 16, 3, 132, 248, 245, 48, 123, 75, 132, 248, 241, 128, 2, 251, ++ 7, 55, 187, 104, 132, 248, 242, 80, 132, 248, 248, 48, 251, 104, 132, ++ 248, 243, 144, 132, 248, 246, 48, 59, 105, 132, 248, 247, 48, 54, 224, ++ 255, 35, 132, 248, 243, 48, 50, 224, 2, 43, 48, 209, 105, 28, 223, 248, ++ 188, 129, 9, 208, 59, 1, 88, 248, 3, 16, 0, 41, 6, 221, 32, 70, 201, ++ 178, 255, 247, 220, 248, 3, 224, 40, 70, 1, 224, 79, 240, 255, 48, 0, ++ 35, 0, 40, 164, 248, 0, 49, 5, 219, 16, 35, 132, 248, 254, 0, 164, 248, ++ 0, 49, 2, 224, 255, 35, 132, 248, 254, 48, 180, 248, 0, 49, 8, 235, ++ 7, 23, 67, 244, 128, 115, 164, 248, 0, 49, 123, 104, 132, 248, 4, 49, ++ 59, 137, 191, 137, 164, 248, 10, 49, 164, 248, 12, 113, 212, 248, 20, ++ 49, 4, 245, 148, 121, 1, 51, 4, 245, 136, 119, 4, 245, 142, 117, 4, ++ 245, 154, 120, 75, 208, 48, 70, 254, 247, 225, 253, 130, 70, 212, 248, ++ 16, 1, 254, 247, 220, 253, 79, 244, 250, 115, 154, 251, 243, 242, 144, ++ 251, 243, 243, 154, 66, 59, 221, 212, 248, 32, 49, 1, 51, 14, 208, 99, ++ 104, 212, 248, 36, 17, 90, 104, 91, 105, 146, 106, 138, 26, 154, 66, ++ 5, 210, 64, 70, 41, 70, 12, 34, 200, 247, 248, 250, 3, 224, 79, 240, ++ 255, 51, 196, 248, 56, 49, 12, 34, 57, 70, 40, 70, 200, 247, 238, 250, ++ 99, 104, 212, 248, 44, 17, 90, 104, 1, 49, 146, 106, 196, 248, 36, 33, ++ 15, 208, 212, 248, 48, 17, 91, 105, 138, 26, 154, 66, 9, 210, 212, 248, ++ 40, 49, 179, 66, 5, 209, 56, 70, 73, 70, 12, 34, 200, 247, 214, 250, ++ 3, 224, 79, 244, 128, 83, 196, 248, 20, 49, 79, 240, 255, 51, 73, 224, ++ 212, 248, 20, 49, 1, 51, 59, 208, 48, 70, 254, 247, 145, 253, 130, 70, ++ 212, 248, 16, 1, 254, 247, 140, 253, 79, 244, 250, 115, 154, 251, 243, ++ 242, 144, 251, 243, 243, 154, 66, 43, 218, 12, 34, 57, 70, 72, 70, 200, ++ 247, 181, 250, 99, 104, 212, 248, 32, 17, 90, 104, 1, 49, 146, 106, ++ 196, 248, 48, 33, 15, 208, 212, 248, 36, 17, 91, 105, 138, 26, 154, ++ 66, 9, 210, 212, 248, 28, 49, 179, 66, 5, 209, 56, 70, 41, 70, 12, 34, ++ 200, 247, 157, 250, 3, 224, 79, 244, 128, 83, 196, 248, 20, 49, 40, ++ 70, 65, 70, 12, 34, 200, 247, 147, 250, 79, 240, 255, 51, 196, 248, ++ 56, 49, 11, 224, 79, 244, 128, 83, 196, 248, 20, 49, 79, 240, 255, 51, ++ 196, 248, 56, 49, 196, 248, 32, 49, 196, 248, 44, 49, 0, 35, 196, 248, ++ 16, 97, 132, 248, 64, 49, 189, 232, 240, 135, 0, 191, 192, 82, 4, 0, ++ 180, 85, 4, 0, 108, 83, 4, 0, 56, 181, 4, 70, 65, 177, 144, 248, 192, ++ 48, 2, 43, 1, 216, 1, 51, 0, 224, 0, 35, 132, 248, 192, 48, 0, 37, 196, ++ 248, 184, 80, 196, 248, 188, 80, 196, 248, 216, 80, 196, 248, 228, 80, ++ 32, 70, 255, 247, 144, 254, 212, 248, 196, 48, 3, 177, 29, 96, 56, 189, ++ 56, 181, 0, 37, 4, 70, 192, 248, 232, 80, 192, 248, 224, 80, 0, 245, ++ 130, 112, 1, 48, 41, 70, 3, 34, 201, 243, 201, 245, 132, 248, 3, 81, ++ 132, 248, 2, 81, 196, 248, 76, 81, 196, 248, 80, 81, 56, 189, 16, 181, ++ 4, 70, 255, 247, 229, 255, 148, 248, 8, 49, 195, 241, 1, 3, 219, 178, ++ 1, 43, 132, 248, 8, 49, 6, 209, 180, 248, 0, 49, 19, 240, 16, 3, 8, ++ 191, 132, 248, 8, 49, 16, 189, 8, 181, 67, 104, 27, 122, 51, 177, 208, ++ 248, 76, 33, 208, 248, 80, 49, 154, 66, 9, 211, 48, 224, 144, 249, 3, ++ 49, 208, 248, 224, 32, 210, 26, 144, 248, 4, 49, 154, 66, 39, 217, 144, ++ 248, 8, 49, 144, 248, 250, 32, 163, 185, 144, 248, 252, 16, 1, 58, 145, ++ 66, 1, 218, 75, 28, 219, 178, 144, 248, 251, 16, 128, 248, 252, 48, ++ 153, 66, 17, 209, 147, 66, 1, 218, 1, 51, 0, 224, 0, 35, 128, 248, 252, ++ 48, 9, 224, 144, 248, 253, 48, 1, 58, 147, 66, 1, 218, 1, 51, 0, 224, ++ 0, 35, 128, 248, 253, 48, 255, 247, 177, 255, 0, 32, 8, 189, 208, 248, ++ 224, 48, 17, 43, 31, 217, 144, 248, 8, 49, 19, 185, 144, 248, 252, 48, ++ 5, 224, 144, 248, 254, 48, 128, 248, 193, 48, 144, 248, 253, 48, 128, ++ 248, 251, 48, 144, 248, 250, 32, 144, 248, 251, 48, 1, 58, 147, 66, ++ 1, 218, 90, 28, 0, 224, 0, 34, 128, 248, 252, 32, 128, 248, 253, 48, ++ 255, 247, 141, 255, 1, 32, 8, 189, 0, 32, 8, 189, 0, 0, 45, 233, 247, ++ 67, 255, 35, 141, 248, 7, 48, 67, 104, 208, 248, 188, 32, 27, 105, 4, ++ 70, 154, 66, 192, 240, 195, 128, 1, 33, 13, 241, 7, 2, 107, 70, 254, ++ 247, 99, 255, 0, 40, 0, 240, 187, 128, 148, 248, 193, 48, 223, 248, ++ 120, 145, 227, 24, 147, 248, 148, 112, 27, 122, 79, 244, 250, 120, 89, ++ 248, 35, 48, 67, 234, 7, 71, 56, 70, 254, 247, 107, 252, 144, 251, 248, ++ 245, 0, 152, 254, 247, 102, 252, 144, 251, 248, 246, 212, 248, 52, 1, ++ 254, 247, 96, 252, 212, 248, 40, 33, 0, 155, 144, 251, 248, 248, 154, ++ 66, 72, 70, 7, 208, 212, 248, 44, 49, 1, 51, 28, 191, 79, 240, 255, ++ 51, 196, 248, 44, 49, 212, 248, 44, 49, 90, 28, 13, 208, 97, 104, 74, ++ 104, 73, 105, 210, 248, 40, 192, 212, 248, 48, 33, 194, 235, 12, 2, ++ 138, 66, 140, 191, 0, 34, 1, 34, 0, 224, 0, 34, 69, 69, 123, 208, 170, ++ 185, 212, 248, 56, 17, 212, 248, 20, 49, 153, 66, 15, 217, 200, 235, ++ 6, 12, 3, 251, 12, 243, 197, 235, 6, 12, 1, 251, 28, 51, 200, 235, 5, ++ 8, 179, 251, 248, 243, 179, 245, 128, 95, 136, 191, 19, 70, 212, 248, ++ 20, 33, 115, 67, 106, 67, 147, 66, 82, 217, 148, 248, 193, 32, 162, ++ 24, 19, 122, 146, 248, 148, 16, 80, 248, 35, 48, 157, 248, 7, 32, 67, ++ 234, 1, 67, 19, 240, 64, 127, 132, 248, 193, 32, 30, 208, 219, 178, ++ 12, 43, 1, 208, 21, 43, 25, 209, 148, 249, 242, 32, 80, 28, 1, 208, ++ 154, 66, 19, 218, 212, 248, 204, 48, 2, 43, 10, 209, 148, 248, 8, 49, ++ 1, 43, 11, 209, 32, 70, 255, 247, 214, 254, 0, 35, 132, 248, 8, 49, ++ 4, 224, 1, 43, 2, 209, 32, 70, 255, 247, 230, 252, 99, 104, 154, 126, ++ 114, 177, 148, 248, 209, 32, 1, 42, 20, 191, 22, 34, 11, 34, 149, 66, ++ 6, 216, 150, 66, 4, 217, 211, 248, 136, 48, 11, 177, 32, 104, 152, 71, ++ 212, 248, 52, 1, 1, 35, 184, 66, 132, 248, 249, 48, 1, 208, 254, 247, ++ 211, 251, 148, 249, 211, 48, 0, 43, 10, 221, 0, 35, 132, 248, 211, 48, ++ 6, 224, 212, 248, 52, 1, 184, 66, 4, 208, 254, 247, 197, 251, 1, 224, ++ 1, 32, 0, 224, 0, 32, 189, 232, 254, 131, 0, 42, 158, 208, 151, 231, ++ 192, 82, 4, 0, 1, 41, 45, 233, 240, 65, 7, 70, 136, 70, 22, 70, 68, ++ 104, 46, 217, 229, 127, 101, 187, 1, 35, 227, 119, 4, 241, 32, 0, 41, ++ 70, 8, 34, 201, 243, 94, 244, 40, 35, 132, 248, 40, 128, 132, 248, 41, ++ 96, 132, 248, 67, 80, 167, 248, 14, 81, 164, 248, 88, 48, 200, 35, 164, ++ 248, 90, 48, 10, 35, 164, 248, 92, 48, 20, 35, 132, 248, 68, 80, 132, ++ 248, 69, 96, 132, 248, 70, 96, 164, 248, 94, 48, 132, 248, 96, 80, 101, ++ 103, 101, 102, 165, 103, 165, 102, 229, 103, 229, 102, 196, 248, 128, ++ 80, 37, 103, 189, 232, 240, 129, 0, 0, 45, 233, 240, 79, 133, 176, 79, ++ 240, 255, 49, 13, 241, 15, 2, 2, 171, 4, 70, 254, 247, 89, 254, 0, 40, ++ 0, 240, 229, 128, 148, 248, 193, 48, 114, 78, 227, 24, 147, 248, 148, ++ 0, 27, 122, 212, 248, 4, 128, 86, 248, 35, 48, 79, 244, 250, 117, 67, ++ 234, 0, 64, 254, 247, 97, 251, 144, 251, 245, 247, 2, 152, 254, 247, ++ 92, 251, 144, 251, 245, 245, 32, 70, 254, 247, 195, 254, 148, 248, 64, ++ 49, 177, 70, 131, 66, 78, 210, 212, 248, 28, 33, 2, 155, 154, 66, 7, ++ 208, 212, 248, 32, 49, 1, 51, 28, 191, 79, 240, 255, 51, 196, 248, 32, ++ 49, 212, 248, 52, 1, 254, 247, 65, 251, 79, 244, 250, 118, 144, 251, ++ 246, 240, 135, 66, 0, 240, 170, 128, 175, 66, 14, 217, 133, 66, 12, ++ 211, 212, 248, 56, 17, 123, 27, 75, 67, 212, 248, 20, 97, 42, 26, 6, ++ 251, 2, 54, 56, 26, 182, 251, 240, 246, 1, 224, 79, 244, 128, 86, 212, ++ 248, 32, 49, 89, 28, 9, 208, 98, 104, 81, 104, 82, 105, 136, 106, 212, ++ 248, 36, 17, 65, 26, 145, 66, 152, 191, 30, 70, 216, 248, 0, 48, 212, ++ 248, 20, 33, 27, 104, 5, 251, 6, 250, 147, 248, 229, 48, 2, 251, 7, ++ 251, 51, 177, 45, 177, 32, 70, 57, 70, 43, 70, 0, 150, 255, 247, 233, ++ 248, 218, 69, 115, 217, 0, 224, 0, 38, 148, 248, 193, 48, 227, 24, 147, ++ 248, 148, 160, 27, 122, 89, 248, 35, 48, 67, 234, 10, 74, 157, 248, ++ 15, 48, 132, 248, 193, 48, 212, 248, 204, 48, 2, 43, 23, 209, 26, 240, ++ 64, 127, 20, 208, 95, 250, 138, 243, 8, 43, 16, 209, 32, 70, 255, 247, ++ 197, 253, 148, 248, 250, 32, 148, 248, 251, 48, 1, 58, 147, 66, 1, 218, ++ 90, 28, 0, 224, 0, 34, 132, 248, 252, 32, 132, 248, 253, 48, 152, 248, ++ 26, 48, 115, 177, 148, 248, 209, 48, 1, 43, 20, 191, 22, 35, 11, 35, ++ 159, 66, 6, 217, 157, 66, 4, 216, 216, 248, 132, 48, 11, 177, 32, 104, ++ 152, 71, 0, 35, 132, 248, 249, 48, 152, 248, 30, 48, 43, 179, 212, 248, ++ 204, 48, 1, 43, 33, 209, 212, 248, 224, 48, 243, 177, 148, 248, 244, ++ 48, 227, 24, 147, 248, 148, 0, 27, 122, 89, 248, 35, 48, 67, 234, 0, ++ 64, 254, 247, 51, 250, 7, 70, 80, 70, 254, 247, 47, 250, 135, 66, 12, ++ 210, 10, 34, 85, 67, 110, 67, 212, 248, 68, 49, 3, 235, 195, 3, 179, ++ 66, 132, 191, 148, 248, 244, 48, 132, 248, 193, 48, 148, 248, 211, 48, ++ 1, 59, 219, 178, 10, 43, 5, 216, 0, 35, 132, 248, 211, 48, 1, 224, 0, ++ 32, 0, 224, 1, 32, 5, 176, 189, 232, 240, 143, 192, 82, 4, 0, 112, 181, ++ 144, 248, 193, 48, 38, 77, 195, 24, 27, 122, 4, 70, 85, 248, 35, 96, ++ 233, 177, 208, 248, 204, 48, 1, 43, 4, 209, 255, 247, 134, 251, 0, 40, ++ 46, 209, 112, 189, 2, 43, 57, 209, 255, 247, 124, 253, 0, 40, 53, 208, ++ 148, 248, 193, 48, 22, 240, 64, 127, 35, 68, 27, 122, 85, 248, 35, 48, ++ 42, 208, 19, 240, 64, 127, 20, 191, 0, 33, 1, 33, 25, 224, 17, 70, 254, ++ 247, 217, 253, 0, 40, 33, 209, 32, 70, 255, 247, 216, 254, 0, 40, 26, ++ 209, 148, 248, 194, 48, 7, 43, 16, 209, 32, 70, 255, 247, 189, 253, ++ 96, 177, 17, 224, 212, 248, 196, 48, 131, 177, 0, 34, 26, 96, 112, 189, ++ 0, 33, 32, 70, 189, 232, 112, 64, 255, 247, 3, 189, 32, 70, 254, 247, ++ 163, 254, 0, 40, 238, 209, 112, 189, 1, 33, 242, 231, 112, 189, 192, ++ 82, 4, 0, 45, 233, 248, 67, 4, 70, 5, 70, 0, 38, 36, 224, 223, 248, ++ 188, 128, 43, 122, 212, 248, 204, 32, 119, 28, 88, 248, 35, 48, 149, ++ 248, 148, 0, 162, 177, 67, 234, 0, 64, 16, 240, 64, 127, 15, 208, 254, ++ 247, 164, 249, 107, 122, 129, 70, 88, 248, 35, 48, 149, 248, 149, 0, ++ 67, 234, 0, 64, 254, 247, 154, 249, 129, 69, 8, 191, 62, 70, 0, 224, ++ 62, 70, 133, 248, 78, 96, 1, 53, 62, 70, 148, 248, 183, 48, 1, 59, 158, ++ 66, 213, 219, 163, 25, 131, 248, 78, 96, 0, 35, 132, 248, 113, 48, 38, ++ 70, 1, 39, 38, 224, 22, 75, 114, 122, 212, 248, 204, 16, 53, 27, 83, ++ 248, 34, 32, 150, 248, 149, 0, 153, 70, 185, 177, 66, 234, 0, 64, 16, ++ 240, 64, 127, 18, 208, 254, 247, 235, 249, 128, 70, 99, 25, 147, 248, ++ 148, 0, 27, 122, 89, 248, 35, 48, 67, 234, 0, 64, 254, 247, 224, 249, ++ 64, 69, 3, 211, 21, 241, 255, 53, 240, 210, 0, 37, 134, 248, 114, 80, ++ 1, 55, 1, 54, 148, 248, 183, 48, 159, 66, 212, 219, 189, 232, 248, 131, ++ 192, 82, 4, 0, 45, 233, 248, 67, 10, 156, 136, 70, 11, 157, 6, 70, 23, ++ 70, 32, 70, 0, 33, 32, 34, 201, 243, 120, 242, 0, 35, 43, 112, 184, ++ 241, 16, 15, 40, 191, 79, 240, 16, 8, 44, 224, 241, 24, 73, 125, 90, ++ 0, 2, 43, 36, 248, 19, 16, 32, 216, 34, 72, 16, 248, 19, 192, 0, 235, ++ 67, 0, 6, 235, 220, 9, 153, 248, 21, 144, 12, 240, 7, 12, 73, 250, 12, ++ 252, 28, 240, 1, 15, 28, 191, 65, 244, 128, 113, 161, 82, 65, 120, 6, ++ 235, 209, 0, 64, 125, 1, 240, 7, 1, 80, 250, 1, 241, 200, 7, 3, 213, ++ 161, 90, 65, 244, 0, 113, 161, 82, 162, 90, 1, 51, 2, 177, 43, 112, ++ 219, 178, 67, 69, 208, 219, 111, 185, 43, 120, 1, 43, 10, 217, 179, ++ 125, 35, 240, 15, 3, 99, 128, 43, 120, 2, 43, 3, 217, 243, 125, 35, ++ 240, 31, 3, 163, 128, 43, 120, 1, 43, 7, 217, 35, 136, 19, 244, 64, ++ 127, 3, 208, 4, 72, 4, 73, 201, 243, 77, 242, 0, 32, 189, 232, 248, ++ 131, 174, 85, 4, 0, 92, 85, 4, 0, 32, 88, 4, 0, 45, 233, 247, 79, 7, ++ 70, 6, 70, 79, 240, 254, 8, 0, 37, 147, 224, 2, 45, 204, 191, 67, 70, ++ 0, 35, 0, 147, 50, 122, 74, 75, 83, 248, 34, 64, 153, 70, 20, 240, 64, ++ 127, 125, 208, 123, 104, 27, 104, 147, 249, 196, 50, 1, 51, 7, 209, ++ 151, 248, 208, 176, 219, 241, 1, 11, 56, 191, 79, 240, 0, 11, 1, 224, ++ 79, 240, 0, 11, 32, 70, 254, 247, 187, 248, 87, 40, 5, 208, 88, 40, ++ 20, 191, 130, 70, 79, 240, 9, 10, 1, 224, 79, 240, 8, 10, 32, 70, 254, ++ 247, 185, 248, 150, 248, 148, 48, 4, 70, 0, 45, 88, 208, 1, 40, 2, 220, ++ 186, 241, 0, 15, 83, 208, 186, 241, 7, 15, 26, 70, 10, 208, 186, 241, ++ 2, 15, 2, 221, 170, 241, 2, 0, 5, 224, 186, 241, 0, 15, 25, 208, 0, ++ 32, 0, 224, 4, 32, 187, 241, 0, 15, 21, 208, 1, 44, 19, 209, 186, 241, ++ 2, 15, 16, 220, 3, 43, 4, 209, 186, 241, 2, 15, 11, 209, 82, 70, 8, ++ 224, 2, 43, 7, 209, 186, 241, 1, 15, 4, 209, 82, 70, 84, 70, 0, 224, ++ 1, 36, 80, 70, 0, 35, 33, 70, 18, 4, 254, 247, 177, 248, 0, 35, 1, 144, ++ 5, 241, 255, 58, 0, 147, 7, 235, 10, 11, 155, 248, 8, 48, 155, 248, ++ 148, 0, 89, 248, 35, 48, 67, 234, 0, 64, 254, 247, 234, 248, 1, 155, ++ 152, 66, 14, 216, 155, 248, 8, 32, 16, 75, 155, 248, 148, 0, 83, 248, ++ 34, 48, 205, 248, 0, 160, 67, 234, 0, 64, 254, 247, 96, 248, 160, 66, ++ 2, 217, 26, 241, 255, 58, 222, 210, 0, 155, 8, 241, 1, 8, 134, 248, ++ 43, 48, 1, 53, 1, 54, 95, 250, 136, 248, 151, 248, 183, 48, 157, 66, ++ 255, 246, 103, 175, 189, 232, 254, 143, 0, 191, 192, 82, 4, 0, 45, 233, ++ 240, 79, 22, 70, 161, 74, 155, 176, 13, 70, 4, 70, 81, 104, 16, 104, ++ 31, 70, 21, 171, 3, 195, 17, 122, 25, 112, 82, 248, 9, 15, 18, 171, ++ 81, 104, 3, 195, 17, 137, 146, 122, 25, 128, 154, 112, 42, 104, 0, 35, ++ 4, 224, 233, 24, 9, 121, 22, 41, 4, 208, 1, 51, 147, 66, 248, 209, 0, ++ 35, 0, 224, 1, 35, 6, 147, 0, 35, 132, 248, 183, 48, 196, 248, 204, ++ 48, 148, 248, 212, 32, 99, 104, 40, 70, 25, 127, 0, 146, 148, 248, 213, ++ 32, 148, 248, 209, 48, 1, 146, 10, 170, 2, 146, 4, 241, 214, 2, 3, 146, ++ 1, 34, 255, 247, 183, 254, 148, 248, 214, 48, 132, 248, 200, 0, 0, 43, ++ 0, 240, 228, 128, 129, 75, 25, 136, 154, 120, 173, 248, 100, 16, 141, ++ 248, 102, 32, 211, 248, 3, 0, 6, 155, 24, 144, 27, 177, 148, 248, 209, ++ 48, 1, 43, 3, 208, 4, 35, 13, 241, 96, 9, 2, 224, 3, 35, 13, 241, 100, ++ 9, 79, 240, 0, 8, 171, 70, 40, 224, 30, 177, 25, 248, 8, 32, 178, 66, ++ 33, 216, 25, 248, 8, 16, 185, 66, 29, 211, 219, 248, 0, 0, 0, 34, 23, ++ 224, 11, 235, 2, 5, 45, 121, 141, 66, 17, 209, 148, 248, 183, 160, 1, ++ 34, 4, 235, 10, 5, 133, 248, 148, 32, 32, 70, 5, 147, 254, 247, 246, ++ 250, 10, 241, 1, 10, 40, 114, 132, 248, 183, 160, 5, 155, 2, 224, 1, ++ 50, 130, 66, 229, 209, 8, 241, 1, 8, 152, 69, 212, 211, 148, 248, 214, ++ 32, 148, 248, 183, 48, 1, 42, 93, 70, 132, 248, 208, 48, 2, 217, 1, ++ 34, 196, 248, 204, 32, 79, 244, 250, 114, 86, 67, 122, 67, 8, 146, 148, ++ 248, 209, 32, 7, 150, 1, 42, 44, 208, 98, 104, 18, 104, 146, 249, 196, ++ 34, 1, 50, 38, 209, 43, 187, 30, 70, 189, 248, 40, 48, 51, 65, 223, ++ 7, 28, 213, 148, 248, 183, 48, 1, 34, 227, 24, 70, 240, 128, 119, 131, ++ 248, 148, 32, 32, 70, 71, 244, 128, 49, 7, 154, 8, 155, 255, 247, 198, ++ 248, 96, 177, 32, 70, 57, 70, 148, 248, 183, 128, 254, 247, 175, 250, ++ 4, 235, 8, 3, 8, 241, 1, 8, 24, 114, 132, 248, 183, 128, 1, 54, 2, 46, ++ 218, 209, 148, 248, 208, 32, 148, 248, 183, 48, 154, 66, 5, 208, 189, ++ 248, 40, 48, 35, 240, 1, 3, 173, 248, 40, 48, 0, 39, 79, 240, 1, 9, ++ 168, 70, 51, 224, 10, 171, 251, 90, 43, 65, 222, 7, 40, 213, 7, 45, ++ 5, 217, 50, 75, 219, 25, 91, 25, 19, 248, 10, 108, 2, 224, 9, 155, 238, ++ 24, 246, 178, 148, 248, 209, 16, 70, 240, 128, 118, 32, 70, 70, 234, ++ 1, 65, 7, 154, 8, 155, 255, 247, 137, 248, 136, 177, 148, 248, 183, ++ 160, 148, 248, 209, 48, 4, 235, 10, 11, 139, 248, 148, 48, 32, 70, 49, ++ 70, 254, 247, 108, 250, 10, 241, 1, 10, 139, 248, 8, 0, 132, 248, 183, ++ 160, 1, 53, 16, 45, 206, 209, 9, 241, 1, 9, 2, 55, 148, 248, 214, 48, ++ 153, 69, 3, 216, 187, 0, 9, 147, 0, 37, 195, 231, 148, 248, 183, 48, ++ 69, 70, 11, 185, 132, 248, 214, 48, 7, 155, 79, 244, 250, 119, 179, ++ 251, 247, 246, 8, 155, 179, 251, 247, 247, 148, 248, 214, 48, 0, 43, ++ 65, 209, 6, 155, 27, 177, 9, 35, 13, 241, 84, 9, 2, 224, 11, 35, 13, ++ 241, 72, 9, 79, 240, 0, 8, 171, 70, 46, 224, 30, 177, 25, 248, 8, 32, ++ 178, 66, 39, 216, 25, 248, 8, 16, 185, 66, 35, 211, 219, 248, 0, 0, ++ 0, 34, 29, 224, 180, 22, 4, 0, 200, 22, 4, 0, 176, 85, 4, 0, 11, 235, ++ 2, 5, 45, 121, 141, 66, 17, 209, 148, 248, 183, 160, 1, 34, 4, 235, ++ 10, 5, 133, 248, 148, 32, 32, 70, 5, 147, 254, 247, 22, 250, 10, 241, ++ 1, 10, 40, 114, 132, 248, 183, 160, 5, 155, 2, 224, 1, 50, 130, 66, ++ 229, 209, 8, 241, 1, 8, 152, 69, 206, 211, 148, 248, 183, 48, 132, 248, ++ 208, 48, 32, 70, 255, 247, 233, 253, 32, 70, 255, 247, 24, 253, 32, ++ 70, 36, 153, 255, 247, 28, 248, 0, 35, 132, 248, 193, 0, 132, 248, 194, ++ 48, 27, 176, 189, 232, 240, 143, 56, 181, 83, 178, 2, 240, 127, 1, 0, ++ 43, 172, 191, 1, 34, 2, 34, 4, 70, 254, 247, 255, 249, 5, 70, 1, 48, ++ 7, 208, 32, 70, 233, 178, 254, 247, 238, 249, 148, 248, 208, 48, 157, ++ 66, 1, 218, 148, 248, 208, 0, 36, 24, 34, 122, 3, 75, 148, 248, 148, ++ 0, 83, 248, 34, 48, 67, 234, 0, 64, 56, 189, 192, 82, 4, 0, 74, 136, ++ 144, 248, 192, 48, 2, 240, 24, 2, 179, 235, 210, 15, 6, 209, 144, 248, ++ 193, 0, 208, 241, 1, 0, 56, 191, 0, 32, 112, 71, 0, 32, 112, 71, 144, ++ 248, 194, 48, 154, 7, 8, 213, 35, 240, 2, 3, 128, 248, 194, 48, 208, ++ 248, 196, 48, 11, 177, 0, 34, 26, 96, 112, 71, 0, 0, 45, 233, 243, 71, ++ 157, 248, 48, 128, 21, 70, 184, 241, 0, 15, 12, 191, 152, 70, 79, 240, ++ 0, 8, 4, 70, 10, 158, 11, 159, 157, 248, 52, 144, 157, 248, 60, 160, ++ 254, 247, 34, 250, 168, 69, 3, 216, 183, 66, 40, 191, 55, 70, 3, 224, ++ 183, 66, 136, 191, 55, 70, 168, 70, 148, 248, 193, 48, 212, 248, 204, ++ 16, 227, 24, 26, 122, 105, 75, 1, 41, 19, 248, 34, 48, 9, 209, 75, 69, ++ 42, 208, 125, 177, 32, 70, 74, 70, 67, 70, 0, 149, 254, 247, 214, 252, ++ 26, 224, 2, 41, 29, 209, 75, 69, 3, 209, 148, 248, 251, 48, 83, 69, ++ 26, 208, 69, 185, 212, 248, 232, 48, 90, 28, 0, 240, 175, 128, 1, 51, ++ 196, 248, 232, 48, 170, 224, 32, 70, 1, 33, 74, 70, 83, 70, 205, 248, ++ 0, 128, 1, 149, 254, 247, 140, 253, 0, 40, 20, 191, 1, 32, 2, 32, 161, ++ 224, 153, 69, 64, 240, 154, 128, 184, 241, 0, 15, 8, 209, 63, 185, 148, ++ 248, 64, 49, 32, 70, 1, 51, 132, 248, 64, 49, 255, 247, 143, 255, 181, ++ 235, 72, 15, 3, 211, 37, 177, 182, 235, 71, 15, 1, 210, 0, 35, 3, 224, ++ 38, 177, 148, 248, 64, 49, 1, 51, 132, 248, 64, 49, 99, 104, 219, 126, ++ 19, 185, 0, 45, 121, 208, 0, 224, 37, 177, 168, 69, 2, 209, 32, 70, ++ 254, 247, 53, 251, 148, 248, 249, 48, 99, 177, 99, 104, 212, 248, 216, ++ 32, 91, 127, 154, 66, 6, 211, 212, 248, 196, 48, 0, 34, 132, 248, 249, ++ 32, 3, 177, 26, 96, 148, 248, 194, 48, 83, 177, 99, 104, 212, 248, 188, ++ 16, 90, 123, 145, 66, 148, 191, 147, 248, 12, 144, 147, 248, 11, 144, ++ 1, 224, 79, 240, 2, 9, 109, 179, 157, 248, 56, 48, 79, 234, 8, 56, 184, ++ 251, 245, 241, 155, 177, 148, 248, 211, 48, 90, 30, 210, 178, 10, 42, ++ 13, 216, 33, 250, 9, 241, 212, 248, 108, 33, 1, 51, 137, 24, 34, 250, ++ 9, 242, 138, 26, 196, 248, 108, 33, 132, 248, 211, 48, 18, 224, 33, ++ 250, 9, 242, 212, 248, 20, 49, 210, 24, 35, 250, 9, 243, 210, 26, 99, ++ 104, 196, 248, 20, 33, 27, 104, 27, 104, 147, 248, 229, 48, 19, 177, ++ 32, 70, 254, 247, 50, 252, 150, 177, 63, 3, 212, 248, 56, 49, 183, 251, ++ 246, 246, 38, 250, 9, 246, 35, 250, 9, 249, 246, 24, 201, 235, 6, 3, ++ 196, 248, 56, 49, 99, 104, 91, 104, 155, 106, 196, 248, 60, 49, 133, ++ 177, 212, 248, 216, 48, 88, 28, 2, 208, 1, 51, 196, 248, 216, 48, 212, ++ 248, 188, 48, 89, 28, 7, 208, 1, 51, 196, 248, 188, 48, 3, 224, 2, 32, ++ 2, 224, 40, 70, 0, 224, 0, 32, 189, 232, 252, 135, 0, 191, 192, 82, ++ 4, 0, 45, 233, 240, 79, 133, 176, 3, 147, 4, 70, 14, 70, 144, 70, 157, ++ 248, 56, 144, 157, 248, 64, 112, 254, 247, 47, 249, 157, 248, 68, 48, ++ 19, 177, 8, 241, 1, 11, 1, 224, 182, 248, 26, 176, 182, 248, 28, 160, ++ 95, 250, 139, 251, 95, 250, 138, 250, 186, 241, 0, 15, 4, 209, 187, ++ 241, 0, 15, 0, 240, 240, 128, 2, 224, 187, 241, 0, 15, 10, 208, 195, ++ 69, 5, 216, 3, 154, 146, 69, 140, 191, 0, 35, 1, 35, 0, 224, 0, 35, ++ 219, 178, 3, 224, 194, 69, 140, 191, 0, 35, 1, 35, 150, 249, 25, 80, ++ 0, 53, 24, 191, 1, 37, 27, 177, 21, 177, 32, 70, 254, 247, 121, 250, ++ 195, 69, 5, 216, 3, 155, 187, 241, 0, 15, 24, 191, 152, 70, 1, 224, ++ 79, 240, 0, 8, 148, 248, 193, 32, 102, 75, 162, 24, 146, 248, 148, 16, ++ 18, 122, 83, 248, 34, 48, 212, 248, 204, 32, 67, 234, 1, 67, 19, 240, ++ 64, 127, 20, 191, 219, 178, 255, 35, 1, 42, 20, 209, 75, 69, 49, 208, ++ 208, 69, 180, 191, 66, 70, 82, 70, 210, 178, 37, 177, 194, 69, 204, ++ 191, 0, 35, 1, 35, 0, 224, 43, 70, 0, 146, 32, 70, 0, 33, 74, 70, 254, ++ 247, 157, 251, 25, 224, 2, 42, 28, 209, 75, 69, 3, 209, 148, 248, 251, ++ 48, 187, 66, 22, 208, 208, 69, 180, 191, 67, 70, 83, 70, 219, 178, 29, ++ 177, 194, 69, 204, 191, 0, 37, 1, 37, 1, 147, 32, 70, 0, 33, 74, 70, ++ 59, 70, 0, 149, 254, 247, 84, 252, 0, 40, 20, 191, 1, 32, 2, 32, 131, ++ 224, 148, 248, 194, 48, 67, 177, 99, 104, 212, 248, 188, 16, 90, 123, ++ 145, 66, 52, 191, 24, 123, 216, 122, 0, 224, 2, 32, 212, 248, 52, 49, ++ 212, 248, 16, 33, 154, 66, 157, 248, 60, 48, 12, 191, 4, 245, 138, 118, ++ 4, 245, 156, 118, 75, 177, 148, 248, 211, 48, 1, 59, 219, 178, 10, 43, ++ 3, 216, 4, 245, 182, 113, 0, 34, 9, 224, 99, 104, 4, 245, 138, 113, ++ 27, 104, 27, 104, 147, 248, 229, 32, 10, 177, 212, 248, 20, 33, 186, ++ 241, 0, 15, 16, 209, 11, 104, 51, 250, 0, 240, 27, 26, 11, 96, 32, 224, ++ 67, 69, 200, 191, 49, 70, 15, 104, 1, 51, 39, 250, 0, 252, 204, 235, ++ 7, 7, 15, 96, 0, 224, 1, 35, 83, 69, 241, 221, 141, 177, 192, 241, 12, ++ 3, 1, 39, 159, 64, 11, 104, 186, 241, 1, 15, 59, 68, 11, 96, 7, 209, ++ 177, 66, 5, 208, 51, 104, 51, 250, 0, 240, 223, 25, 59, 26, 51, 96, ++ 99, 104, 27, 104, 27, 104, 147, 248, 229, 48, 35, 177, 32, 70, 212, ++ 248, 20, 17, 254, 247, 16, 251, 4, 245, 156, 115, 158, 66, 4, 209, 99, ++ 104, 91, 104, 155, 106, 196, 248, 60, 49, 29, 177, 0, 35, 132, 248, ++ 64, 49, 7, 224, 148, 248, 64, 49, 32, 70, 1, 51, 132, 248, 64, 49, 255, ++ 247, 237, 253, 212, 248, 188, 48, 89, 28, 5, 208, 1, 51, 196, 248, 188, ++ 48, 1, 224, 2, 32, 0, 224, 0, 32, 5, 176, 189, 232, 240, 143, 192, 82, ++ 4, 0, 131, 123, 67, 185, 4, 35, 25, 177, 3, 115, 5, 35, 195, 114, 112, ++ 71, 2, 34, 2, 115, 195, 114, 112, 71, 211, 185, 144, 248, 245, 32, 209, ++ 7, 3, 213, 208, 248, 196, 32, 2, 177, 19, 96, 144, 248, 245, 48, 35, ++ 240, 1, 3, 128, 248, 245, 48, 176, 248, 0, 49, 218, 7, 4, 213, 208, ++ 248, 196, 32, 10, 177, 0, 33, 17, 96, 35, 240, 1, 3, 160, 248, 0, 49, ++ 112, 71, 45, 233, 240, 79, 144, 70, 74, 136, 31, 70, 144, 248, 192, ++ 48, 2, 240, 24, 2, 133, 176, 179, 235, 210, 15, 4, 70, 14, 70, 157, ++ 248, 56, 176, 157, 248, 60, 80, 157, 248, 64, 160, 157, 248, 68, 144, ++ 36, 209, 144, 248, 251, 16, 254, 247, 48, 250, 49, 70, 32, 70, 66, 70, ++ 59, 70, 205, 248, 0, 176, 1, 149, 205, 248, 8, 160, 205, 248, 12, 144, ++ 255, 247, 149, 254, 2, 40, 1, 70, 16, 208, 161, 241, 1, 12, 220, 241, ++ 0, 1, 32, 70, 65, 235, 12, 1, 42, 70, 5, 176, 189, 232, 240, 79, 255, ++ 247, 1, 186, 1, 51, 196, 248, 184, 48, 3, 224, 212, 248, 184, 48, 90, ++ 28, 247, 209, 5, 176, 189, 232, 240, 143, 45, 233, 240, 79, 139, 176, ++ 157, 248, 104, 64, 157, 248, 80, 192, 9, 148, 157, 248, 84, 128, 157, ++ 248, 88, 144, 157, 248, 92, 176, 157, 248, 96, 160, 157, 248, 100, 80, ++ 4, 70, 0, 40, 50, 208, 144, 248, 183, 112, 0, 47, 46, 208, 79, 136, ++ 144, 248, 192, 96, 7, 240, 24, 7, 182, 235, 215, 15, 34, 209, 9, 158, ++ 205, 248, 0, 192, 205, 248, 4, 128, 205, 248, 8, 144, 205, 248, 12, ++ 160, 4, 149, 205, 248, 20, 176, 6, 150, 254, 247, 30, 252, 2, 40, 1, ++ 70, 16, 208, 161, 241, 1, 12, 220, 241, 0, 1, 32, 70, 65, 235, 12, 1, ++ 42, 70, 11, 176, 189, 232, 240, 79, 255, 247, 182, 185, 1, 51, 196, ++ 248, 184, 48, 3, 224, 212, 248, 184, 48, 90, 28, 247, 209, 11, 176, ++ 189, 232, 240, 143, 45, 233, 240, 79, 135, 176, 16, 159, 221, 248, 68, ++ 128, 157, 248, 72, 144, 157, 248, 76, 160, 157, 248, 80, 80, 157, 248, ++ 84, 176, 4, 70, 0, 40, 48, 208, 144, 248, 183, 192, 188, 241, 0, 15, ++ 43, 208, 7, 235, 2, 12, 188, 241, 0, 15, 8, 191, 1, 34, 144, 248, 192, ++ 192, 1, 240, 24, 6, 188, 235, 214, 15, 26, 209, 141, 232, 128, 7, 4, ++ 149, 205, 248, 20, 176, 255, 247, 11, 253, 2, 40, 1, 70, 16, 208, 161, ++ 241, 1, 12, 220, 241, 0, 1, 32, 70, 65, 235, 12, 1, 42, 70, 7, 176, ++ 189, 232, 240, 79, 255, 247, 113, 185, 1, 51, 196, 248, 184, 48, 3, ++ 224, 212, 248, 184, 48, 90, 28, 247, 209, 7, 176, 189, 232, 240, 143, ++ 112, 181, 144, 248, 68, 48, 4, 70, 0, 43, 79, 208, 22, 11, 144, 248, ++ 69, 48, 144, 248, 70, 32, 6, 240, 3, 6, 147, 66, 2, 208, 150, 66, 68, ++ 209, 2, 224, 158, 66, 65, 209, 2, 224, 0, 241, 76, 5, 1, 224, 0, 241, ++ 72, 5, 8, 70, 253, 247, 209, 251, 148, 248, 96, 32, 79, 244, 250, 115, ++ 144, 251, 243, 243, 138, 177, 4, 235, 134, 2, 82, 111, 24, 54, 4, 235, ++ 134, 6, 10, 185, 115, 96, 8, 224, 113, 104, 226, 122, 49, 250, 2, 240, ++ 51, 250, 2, 242, 9, 26, 138, 24, 114, 96, 34, 109, 10, 185, 43, 96, ++ 16, 224, 41, 104, 224, 122, 49, 250, 0, 240, 8, 26, 40, 96, 226, 122, ++ 51, 250, 2, 242, 18, 24, 138, 66, 42, 96, 3, 209, 147, 66, 1, 217, 1, ++ 50, 42, 96, 35, 109, 90, 28, 1, 208, 1, 51, 35, 101, 32, 70, 2, 33, ++ 189, 232, 112, 64, 254, 247, 226, 184, 112, 189, 144, 248, 193, 32, ++ 144, 248, 208, 48, 154, 66, 52, 191, 0, 32, 1, 32, 112, 71, 45, 233, ++ 248, 67, 13, 70, 145, 122, 4, 70, 2, 41, 148, 191, 0, 33, 1, 33, 22, ++ 70, 152, 70, 254, 247, 88, 248, 0, 35, 168, 248, 0, 48, 148, 248, 251, ++ 48, 51, 114, 148, 248, 251, 48, 115, 114, 42, 136, 148, 249, 211, 112, ++ 34, 240, 24, 2, 18, 4, 18, 12, 148, 248, 193, 48, 42, 128, 148, 248, ++ 192, 16, 0, 47, 204, 191, 79, 244, 0, 7, 0, 39, 201, 0, 1, 240, 24, ++ 1, 10, 67, 82, 4, 82, 12, 42, 128, 148, 248, 183, 32, 147, 66, 3, 211, ++ 83, 30, 219, 178, 132, 248, 193, 48, 226, 24, 146, 248, 148, 0, 73, ++ 73, 18, 122, 137, 70, 81, 248, 34, 32, 66, 234, 0, 66, 50, 96, 212, ++ 248, 204, 32, 1, 42, 13, 209, 148, 248, 245, 32, 210, 7, 34, 213, 42, ++ 136, 148, 248, 243, 48, 111, 234, 66, 66, 111, 234, 82, 66, 42, 128, ++ 0, 39, 24, 224, 2, 42, 22, 209, 180, 248, 0, 33, 208, 7, 18, 213, 148, ++ 248, 8, 33, 26, 185, 148, 248, 252, 32, 50, 114, 5, 224, 148, 248, 253, ++ 32, 148, 248, 254, 48, 0, 39, 50, 114, 42, 136, 111, 234, 66, 66, 111, ++ 234, 82, 66, 42, 128, 148, 248, 193, 32, 154, 66, 7, 208, 148, 248, ++ 183, 32, 147, 66, 3, 211, 83, 30, 219, 178, 132, 248, 193, 48, 148, ++ 248, 249, 32, 42, 177, 184, 248, 0, 32, 66, 240, 1, 2, 168, 248, 0, ++ 32, 148, 248, 208, 32, 154, 66, 11, 216, 226, 24, 148, 248, 210, 16, ++ 146, 248, 148, 32, 81, 250, 2, 242, 18, 240, 1, 2, 8, 191, 23, 70, 0, ++ 224, 0, 39, 227, 24, 147, 248, 148, 32, 27, 122, 32, 70, 89, 248, 35, ++ 48, 67, 234, 2, 67, 59, 67, 51, 96, 148, 248, 193, 16, 253, 247, 171, ++ 253, 35, 24, 26, 122, 147, 248, 148, 16, 89, 248, 34, 32, 66, 234, 1, ++ 66, 114, 96, 143, 177, 148, 249, 211, 16, 12, 41, 13, 209, 148, 248, ++ 208, 16, 129, 66, 9, 216, 148, 248, 210, 16, 147, 248, 148, 48, 81, ++ 250, 3, 243, 217, 7, 68, 191, 23, 67, 119, 96, 150, 232, 12, 0, 154, ++ 66, 6, 209, 50, 122, 115, 122, 154, 66, 12, 191, 1, 35, 2, 35, 0, 224, ++ 2, 35, 179, 114, 189, 232, 248, 131, 192, 82, 4, 0, 79, 244, 188, 112, ++ 112, 71, 0, 0, 16, 181, 0, 35, 128, 248, 84, 49, 128, 248, 85, 49, 128, ++ 248, 86, 49, 128, 248, 87, 49, 100, 35, 128, 248, 88, 49, 144, 248, ++ 183, 48, 4, 70, 1, 59, 195, 24, 147, 248, 148, 0, 26, 122, 5, 75, 83, ++ 248, 34, 48, 67, 234, 0, 64, 253, 247, 160, 250, 196, 248, 92, 1, 16, ++ 189, 0, 191, 192, 82, 4, 0, 45, 233, 240, 79, 135, 176, 147, 70, 24, ++ 154, 31, 70, 4, 146, 25, 154, 128, 70, 16, 155, 157, 248, 68, 144, 157, ++ 249, 72, 160, 157, 248, 88, 96, 157, 248, 92, 80, 5, 146, 12, 70, 0, ++ 41, 124, 208, 8, 70, 79, 244, 188, 114, 0, 33, 3, 147, 200, 243, 51, ++ 243, 196, 248, 4, 128, 196, 248, 0, 176, 196, 248, 196, 112, 3, 155, ++ 15, 177, 0, 34, 58, 96, 79, 234, 74, 10, 132, 248, 209, 144, 132, 248, ++ 210, 160, 0, 39, 25, 70, 32, 70, 4, 154, 5, 155, 0, 151, 255, 247, 163, ++ 249, 1, 46, 132, 248, 250, 96, 15, 217, 2, 35, 196, 248, 204, 48, 115, ++ 30, 157, 66, 184, 191, 111, 28, 0, 35, 132, 248, 251, 80, 132, 248, ++ 252, 112, 132, 248, 253, 80, 132, 248, 8, 49, 42, 70, 32, 70, 49, 70, ++ 254, 247, 146, 254, 99, 104, 6, 34, 90, 119, 0, 33, 48, 34, 4, 245, ++ 136, 112, 200, 243, 249, 242, 212, 248, 204, 80, 79, 240, 255, 51, 1, ++ 45, 196, 248, 20, 49, 28, 209, 132, 248, 242, 48, 0, 35, 132, 248, 241, ++ 48, 148, 248, 214, 48, 2, 43, 19, 217, 148, 248, 193, 48, 227, 24, 147, ++ 248, 148, 0, 26, 122, 19, 75, 83, 248, 34, 48, 67, 234, 0, 64, 1, 40, ++ 148, 191, 0, 32, 1, 32, 253, 247, 167, 249, 8, 177, 132, 248, 241, 80, ++ 32, 70, 254, 247, 133, 251, 99, 104, 91, 104, 155, 106, 196, 248, 100, ++ 49, 0, 35, 196, 248, 96, 49, 216, 248, 0, 48, 27, 104, 147, 248, 229, ++ 48, 43, 177, 32, 70, 7, 176, 189, 232, 240, 79, 255, 247, 75, 191, 7, ++ 176, 189, 232, 240, 143, 192, 82, 4, 0, 45, 233, 240, 65, 152, 70, 144, ++ 248, 193, 48, 4, 70, 195, 24, 147, 248, 148, 0, 22, 70, 26, 122, 18, ++ 75, 13, 70, 83, 248, 34, 48, 6, 159, 67, 234, 0, 64, 253, 247, 238, ++ 249, 79, 244, 250, 114, 144, 251, 242, 240, 66, 67, 50, 96, 148, 248, ++ 194, 48, 7, 43, 6, 209, 212, 248, 188, 48, 171, 66, 148, 191, 0, 37, ++ 1, 37, 0, 224, 0, 37, 56, 70, 4, 245, 170, 113, 12, 34, 136, 248, 0, ++ 80, 189, 232, 240, 65, 198, 247, 8, 191, 192, 82, 4, 0, 208, 248, 196, ++ 48, 11, 177, 0, 34, 26, 96, 112, 71, 131, 105, 218, 104, 138, 66, 24, ++ 191, 217, 96, 112, 71, 56, 181, 4, 70, 37, 105, 0, 104, 53, 177, 5, ++ 245, 7, 113, 233, 243, 207, 243, 40, 70, 207, 247, 139, 254, 0, 35, ++ 35, 97, 56, 189, 248, 181, 132, 105, 5, 70, 6, 104, 224, 106, 8, 177, ++ 207, 247, 128, 254, 233, 105, 176, 104, 0, 39, 221, 243, 194, 246, 0, ++ 33, 40, 70, 255, 247, 218, 255, 40, 70, 132, 248, 61, 112, 255, 247, ++ 219, 255, 48, 70, 243, 243, 52, 246, 39, 130, 103, 98, 167, 98, 231, ++ 98, 39, 131, 248, 189, 115, 181, 4, 104, 3, 37, 32, 70, 1, 33, 79, 244, ++ 128, 98, 0, 35, 0, 149, 239, 243, 203, 246, 0, 33, 32, 70, 10, 70, 1, ++ 35, 0, 149, 24, 240, 2, 221, 0, 38, 212, 248, 104, 50, 157, 89, 157, ++ 177, 171, 121, 139, 185, 213, 248, 4, 49, 90, 108, 34, 240, 1, 2, 90, ++ 100, 26, 120, 1, 42, 1, 209, 91, 127, 51, 177, 40, 70, 0, 33, 216, 247, ++ 117, 255, 40, 70, 252, 247, 67, 249, 4, 54, 32, 46, 228, 209, 32, 70, ++ 2, 176, 189, 232, 112, 64, 243, 243, 250, 181, 248, 181, 208, 248, 152, ++ 85, 4, 70, 174, 105, 243, 104, 0, 43, 48, 208, 1, 43, 48, 208, 40, 70, ++ 1, 33, 255, 247, 138, 255, 160, 104, 233, 105, 221, 243, 106, 246, 40, ++ 177, 40, 70, 0, 33, 255, 247, 129, 255, 1, 39, 0, 224, 7, 70, 51, 138, ++ 131, 177, 35, 106, 24, 105, 242, 247, 134, 252, 51, 138, 131, 66, 9, ++ 208, 32, 70, 244, 243, 44, 243, 32, 70, 49, 138, 242, 243, 250, 247, ++ 32, 70, 238, 243, 219, 242, 212, 248, 152, 5, 255, 247, 155, 255, 32, ++ 70, 244, 243, 168, 245, 40, 70, 255, 247, 118, 255, 56, 70, 248, 189, ++ 1, 32, 248, 189, 0, 32, 248, 189, 255, 247, 193, 191, 0, 32, 112, 71, ++ 16, 181, 12, 70, 65, 177, 177, 248, 112, 48, 43, 177, 200, 110, 207, ++ 247, 235, 253, 0, 35, 164, 248, 112, 48, 16, 189, 8, 70, 207, 247, 228, ++ 189, 1, 70, 3, 104, 209, 248, 140, 32, 48, 181, 24, 104, 250, 177, 79, ++ 244, 97, 101, 178, 251, 245, 243, 5, 251, 19, 34, 0, 36, 193, 248, 152, ++ 64, 193, 248, 144, 48, 193, 248, 148, 32, 51, 177, 128, 104, 209, 248, ++ 156, 16, 72, 246, 160, 66, 35, 70, 6, 224, 74, 177, 79, 244, 122, 116, ++ 98, 67, 128, 104, 209, 248, 156, 16, 189, 232, 48, 64, 221, 243, 222, ++ 181, 48, 189, 8, 70, 204, 243, 168, 183, 56, 181, 8, 59, 152, 178, 161, ++ 248, 112, 0, 12, 70, 21, 70, 204, 243, 159, 247, 224, 102, 56, 177, ++ 180, 248, 112, 32, 5, 241, 8, 1, 189, 232, 56, 64, 198, 247, 9, 190, ++ 56, 189, 240, 181, 31, 70, 185, 176, 0, 35, 53, 147, 54, 147, 123, 75, ++ 6, 70, 12, 70, 13, 241, 192, 14, 3, 241, 16, 12, 24, 104, 89, 104, 117, ++ 70, 3, 197, 8, 51, 99, 69, 174, 70, 247, 209, 54, 104, 1, 33, 32, 35, ++ 2, 241, 8, 5, 112, 106, 0, 34, 201, 247, 247, 252, 53, 144, 48, 105, ++ 204, 247, 7, 253, 104, 47, 54, 144, 19, 217, 180, 248, 112, 48, 19, ++ 177, 224, 110, 207, 247, 122, 253, 104, 63, 184, 178, 164, 248, 112, ++ 0, 204, 243, 99, 247, 224, 102, 0, 40, 0, 240, 168, 128, 180, 248, 112, ++ 48, 237, 24, 1, 224, 64, 240, 164, 128, 160, 111, 1, 33, 42, 70, 32, ++ 35, 201, 247, 149, 253, 160, 111, 201, 247, 199, 254, 0, 40, 64, 240, ++ 154, 128, 160, 111, 113, 105, 201, 247, 51, 254, 0, 40, 128, 242, 147, ++ 128, 1, 33, 5, 241, 32, 2, 32, 35, 212, 248, 136, 0, 201, 247, 128, ++ 253, 1, 33, 212, 248, 140, 0, 5, 241, 64, 2, 32, 35, 201, 247, 120, ++ 253, 160, 111, 97, 111, 201, 247, 28, 254, 112, 185, 212, 248, 136, ++ 0, 212, 248, 128, 16, 201, 247, 21, 254, 56, 185, 212, 248, 140, 0, ++ 212, 248, 132, 16, 201, 247, 14, 254, 0, 40, 112, 208, 212, 248, 136, ++ 16, 212, 248, 148, 0, 212, 248, 140, 32, 204, 247, 50, 253, 48, 105, ++ 212, 248, 148, 16, 204, 247, 177, 255, 0, 40, 99, 208, 212, 248, 144, ++ 0, 161, 111, 54, 154, 205, 247, 135, 251, 54, 152, 212, 248, 148, 16, ++ 2, 70, 204, 247, 245, 255, 54, 152, 225, 111, 2, 70, 32, 173, 205, 247, ++ 123, 251, 54, 152, 52, 169, 0, 34, 204, 247, 3, 253, 42, 70, 32, 35, ++ 1, 33, 52, 152, 201, 247, 155, 253, 0, 33, 32, 34, 40, 168, 200, 243, ++ 229, 240, 32, 33, 55, 171, 42, 70, 24, 175, 1, 147, 40, 168, 11, 70, ++ 0, 151, 203, 243, 129, 242, 97, 111, 162, 111, 115, 105, 53, 152, 201, ++ 247, 97, 254, 32, 35, 42, 70, 1, 33, 53, 152, 201, 247, 128, 253, 41, ++ 70, 16, 34, 4, 241, 8, 0, 198, 247, 73, 253, 48, 168, 200, 243, 122, ++ 241, 0, 149, 64, 34, 32, 37, 3, 70, 4, 174, 3, 146, 41, 70, 48, 170, ++ 56, 70, 1, 149, 2, 150, 203, 243, 57, 242, 4, 241, 24, 0, 49, 70, 42, ++ 70, 198, 247, 51, 253, 4, 241, 56, 0, 12, 169, 42, 70, 198, 247, 45, ++ 253, 0, 36, 8, 224, 4, 70, 6, 224, 4, 36, 4, 224, 3, 36, 2, 224, 1, ++ 36, 0, 224, 2, 36, 53, 168, 201, 247, 127, 253, 54, 168, 204, 247, 113, ++ 252, 0, 33, 32, 34, 24, 168, 200, 243, 151, 240, 0, 33, 80, 34, 4, 168, ++ 200, 243, 146, 240, 32, 168, 0, 33, 32, 34, 200, 243, 141, 240, 32, ++ 70, 57, 176, 240, 189, 144, 88, 4, 0, 45, 233, 240, 79, 29, 70, 209, ++ 248, 244, 48, 137, 176, 179, 248, 98, 160, 131, 104, 129, 70, 238, 88, ++ 67, 104, 15, 70, 203, 88, 144, 70, 7, 147, 24, 70, 49, 70, 18, 154, ++ 19, 155, 255, 247, 234, 254, 3, 40, 202, 243, 64, 26, 4, 70, 1, 209, ++ 0, 144, 5, 224, 2, 40, 1, 208, 4, 40, 17, 209, 3, 35, 0, 147, 1, 35, ++ 1, 147, 2, 147, 0, 35, 3, 147, 4, 147, 56, 70, 5, 241, 20, 1, 66, 70, ++ 43, 70, 205, 248, 20, 160, 217, 247, 58, 255, 70, 224, 1, 40, 67, 208, ++ 0, 40, 66, 209, 182, 248, 98, 48, 5, 241, 20, 12, 1, 51, 166, 248, 98, ++ 48, 1, 35, 79, 240, 3, 11, 97, 70, 1, 147, 2, 144, 3, 144, 4, 144, 66, ++ 70, 43, 70, 56, 70, 205, 248, 0, 176, 205, 248, 24, 192, 205, 248, 20, ++ 160, 217, 247, 27, 255, 221, 248, 24, 192, 205, 248, 0, 176, 97, 70, ++ 79, 240, 2, 11, 66, 70, 43, 70, 56, 70, 205, 248, 4, 176, 2, 148, 3, ++ 148, 4, 148, 205, 248, 20, 160, 217, 247, 8, 255, 216, 248, 0, 48, 177, ++ 110, 198, 248, 89, 48, 184, 248, 4, 48, 166, 248, 93, 48, 217, 248, ++ 0, 48, 152, 104, 7, 155, 211, 248, 136, 32, 35, 70, 221, 243, 80, 244, ++ 134, 248, 88, 176, 0, 224, 255, 36, 32, 70, 9, 176, 189, 232, 240, 143, ++ 45, 233, 240, 79, 152, 70, 209, 248, 244, 48, 135, 176, 179, 248, 98, ++ 176, 131, 104, 6, 70, 88, 248, 3, 80, 67, 104, 15, 70, 81, 248, 3, 144, ++ 146, 70, 72, 70, 41, 70, 16, 154, 17, 155, 255, 247, 107, 254, 1, 40, ++ 4, 70, 9, 209, 51, 104, 169, 110, 152, 104, 217, 248, 136, 32, 0, 35, ++ 221, 243, 38, 244, 0, 36, 54, 224, 2, 40, 203, 243, 64, 19, 1, 208, ++ 4, 40, 16, 209, 3, 34, 0, 146, 1, 34, 1, 146, 2, 146, 0, 34, 3, 146, ++ 4, 146, 5, 147, 56, 70, 8, 241, 20, 1, 82, 70, 67, 70, 217, 247, 180, ++ 254, 31, 224, 240, 185, 181, 248, 98, 32, 79, 240, 2, 11, 1, 50, 165, ++ 248, 98, 32, 3, 34, 141, 232, 4, 8, 2, 144, 3, 144, 4, 144, 5, 147, ++ 8, 241, 20, 1, 82, 70, 67, 70, 56, 70, 217, 247, 157, 254, 51, 104, ++ 169, 110, 152, 104, 217, 248, 136, 32, 35, 70, 221, 243, 239, 243, 133, ++ 248, 88, 176, 32, 70, 7, 176, 189, 232, 240, 143, 112, 181, 188, 176, ++ 12, 70, 22, 70, 17, 70, 2, 168, 2, 34, 198, 247, 34, 252, 1, 33, 13, ++ 241, 10, 2, 32, 35, 160, 111, 201, 247, 76, 252, 1, 33, 13, 241, 42, ++ 2, 32, 35, 212, 248, 136, 0, 201, 247, 68, 252, 1, 33, 13, 241, 74, ++ 2, 32, 35, 212, 248, 140, 0, 201, 247, 60, 252, 1, 33, 13, 241, 106, ++ 2, 32, 35, 96, 111, 201, 247, 53, 252, 1, 33, 13, 241, 138, 2, 32, 35, ++ 212, 248, 128, 0, 201, 247, 45, 252, 1, 33, 13, 241, 170, 2, 32, 35, ++ 212, 248, 132, 0, 201, 247, 37, 252, 59, 171, 51, 173, 1, 147, 4, 241, ++ 24, 0, 194, 35, 32, 33, 2, 170, 0, 149, 203, 243, 15, 241, 176, 28, ++ 32, 34, 41, 70, 198, 247, 209, 251, 208, 241, 1, 0, 56, 191, 0, 32, ++ 60, 176, 112, 189, 48, 181, 208, 248, 80, 56, 197, 104, 28, 106, 165, ++ 248, 92, 70, 1, 52, 28, 98, 189, 232, 48, 64, 238, 243, 251, 179, 45, ++ 233, 247, 67, 177, 248, 112, 48, 208, 248, 0, 144, 5, 70, 12, 70, 2, ++ 241, 6, 8, 217, 248, 0, 112, 214, 136, 43, 177, 200, 110, 207, 247, ++ 93, 251, 0, 35, 164, 248, 112, 48, 72, 70, 33, 70, 66, 70, 255, 247, ++ 141, 255, 184, 177, 164, 248, 100, 96, 4, 241, 56, 6, 215, 248, 188, ++ 6, 105, 104, 50, 70, 32, 35, 4, 240, 255, 251, 35, 104, 105, 104, 20, ++ 51, 0, 147, 0, 35, 1, 147, 215, 248, 188, 6, 50, 70, 32, 35, 4, 240, ++ 179, 253, 1, 32, 189, 232, 254, 131, 247, 181, 177, 248, 100, 48, 214, ++ 136, 5, 70, 0, 104, 179, 66, 12, 70, 7, 104, 32, 210, 79, 246, 255, ++ 115, 158, 66, 28, 208, 6, 50, 255, 247, 97, 255, 200, 177, 164, 248, ++ 100, 96, 4, 241, 56, 6, 215, 248, 188, 6, 105, 104, 50, 70, 32, 35, ++ 4, 240, 211, 251, 35, 104, 105, 104, 20, 51, 0, 147, 0, 35, 1, 147, ++ 215, 248, 188, 6, 50, 70, 32, 35, 4, 240, 135, 253, 1, 32, 0, 224, 0, ++ 32, 254, 189, 45, 233, 243, 65, 6, 104, 0, 35, 5, 70, 13, 153, 48, 70, ++ 1, 147, 144, 70, 10, 156, 234, 247, 210, 252, 107, 104, 7, 70, 197, ++ 88, 9, 155, 3, 43, 4, 217, 1, 168, 8, 153, 4, 34, 198, 247, 89, 251, ++ 184, 241, 11, 15, 105, 216, 223, 232, 8, 240, 6, 10, 104, 40, 18, 22, ++ 29, 32, 83, 86, 93, 96, 51, 104, 147, 248, 102, 49, 9, 224, 1, 154, ++ 51, 104, 0, 50, 24, 191, 1, 34, 131, 248, 102, 33, 83, 224, 213, 248, ++ 136, 48, 35, 96, 79, 224, 1, 155, 179, 245, 150, 127, 80, 216, 197, ++ 248, 136, 48, 72, 224, 213, 248, 140, 48, 243, 231, 1, 155, 74, 246, ++ 192, 2, 147, 66, 69, 216, 197, 248, 140, 48, 61, 224, 35, 136, 127, ++ 43, 63, 216, 8, 53, 40, 70, 199, 243, 89, 247, 184, 177, 40, 70, 180, ++ 248, 0, 128, 199, 243, 83, 247, 128, 69, 5, 209, 160, 28, 41, 70, 34, ++ 136, 198, 247, 5, 251, 80, 177, 187, 121, 43, 185, 214, 248, 188, 6, ++ 57, 70, 49, 240, 164, 222, 2, 224, 51, 104, 27, 126, 43, 187, 0, 33, ++ 128, 34, 40, 70, 199, 243, 135, 246, 40, 70, 161, 28, 34, 136, 198, ++ 247, 2, 251, 18, 224, 149, 248, 160, 48, 189, 231, 1, 155, 0, 51, 24, ++ 191, 1, 35, 133, 248, 160, 48, 8, 224, 149, 248, 161, 48, 179, 231, ++ 1, 155, 0, 51, 24, 191, 1, 35, 133, 248, 161, 48, 0, 32, 7, 224, 111, ++ 240, 22, 0, 4, 224, 111, 240, 1, 0, 1, 224, 111, 240, 4, 0, 189, 232, ++ 252, 129, 248, 181, 134, 104, 5, 70, 140, 89, 15, 70, 156, 179, 161, ++ 110, 65, 177, 3, 104, 152, 104, 221, 243, 186, 242, 43, 104, 161, 110, ++ 152, 104, 221, 243, 45, 243, 33, 70, 40, 70, 255, 247, 118, 252, 4, ++ 241, 152, 0, 204, 247, 30, 250, 4, 241, 148, 0, 204, 247, 26, 250, 4, ++ 241, 144, 0, 204, 247, 22, 250, 4, 241, 124, 0, 201, 247, 29, 251, 4, ++ 241, 140, 0, 201, 247, 25, 251, 4, 241, 136, 0, 201, 247, 21, 251, 4, ++ 241, 116, 0, 201, 247, 17, 251, 4, 241, 120, 0, 201, 247, 13, 251, 32, ++ 70, 207, 247, 71, 250, 0, 35, 187, 81, 248, 189, 248, 181, 70, 104, ++ 5, 70, 140, 89, 15, 70, 140, 177, 212, 248, 156, 16, 73, 177, 3, 104, ++ 152, 104, 221, 243, 126, 242, 43, 104, 212, 248, 156, 16, 152, 104, ++ 221, 243, 240, 242, 32, 70, 207, 247, 46, 250, 0, 35, 187, 81, 248, ++ 189, 248, 181, 135, 104, 5, 70, 156, 32, 14, 70, 204, 243, 19, 244, ++ 4, 70, 0, 40, 84, 208, 0, 33, 156, 34, 199, 243, 0, 246, 38, 96, 101, ++ 96, 0, 35, 244, 81, 104, 106, 164, 248, 112, 48, 1, 33, 0, 34, 32, 35, ++ 201, 247, 129, 249, 160, 103, 0, 40, 68, 208, 104, 106, 1, 33, 0, 34, ++ 32, 35, 201, 247, 120, 249, 96, 103, 0, 40, 59, 208, 104, 106, 1, 33, ++ 0, 34, 32, 35, 201, 247, 111, 249, 196, 248, 136, 0, 144, 179, 104, ++ 106, 1, 33, 0, 34, 32, 35, 201, 247, 102, 249, 196, 248, 140, 0, 72, ++ 179, 104, 106, 1, 33, 0, 34, 32, 35, 201, 247, 93, 249, 224, 103, 8, ++ 179, 40, 105, 204, 247, 108, 249, 196, 248, 144, 0, 216, 177, 40, 105, ++ 204, 247, 102, 249, 196, 248, 148, 0, 168, 177, 40, 105, 204, 247, 96, ++ 249, 196, 248, 152, 0, 120, 177, 19, 35, 164, 248, 102, 48, 43, 104, ++ 9, 73, 152, 104, 50, 70, 0, 35, 221, 243, 156, 242, 160, 102, 0, 36, ++ 8, 224, 111, 240, 26, 4, 1, 224, 79, 240, 255, 52, 40, 70, 49, 70, 255, ++ 247, 68, 255, 32, 70, 248, 189, 5, 202, 3, 0, 248, 181, 71, 104, 6, ++ 70, 168, 32, 13, 70, 204, 243, 167, 243, 4, 70, 224, 177, 79, 244, 47, ++ 115, 232, 81, 192, 248, 136, 48, 74, 246, 192, 3, 69, 96, 192, 248, ++ 140, 48, 0, 37, 1, 35, 5, 114, 128, 248, 161, 48, 128, 248, 160, 48, ++ 51, 104, 6, 96, 8, 73, 152, 104, 34, 70, 43, 70, 221, 243, 106, 242, ++ 196, 248, 156, 0, 40, 70, 248, 189, 48, 70, 41, 70, 255, 247, 81, 255, ++ 111, 240, 26, 0, 248, 189, 0, 191, 49, 192, 3, 0, 240, 181, 208, 248, ++ 152, 48, 208, 248, 144, 16, 1, 51, 68, 104, 139, 66, 37, 104, 141, 176, ++ 2, 70, 192, 248, 152, 48, 9, 209, 208, 248, 148, 48, 123, 177, 210, ++ 248, 156, 16, 79, 244, 122, 114, 168, 104, 90, 67, 4, 224, 7, 210, 210, ++ 248, 156, 16, 168, 104, 20, 74, 0, 35, 221, 243, 144, 241, 34, 224, ++ 213, 248, 188, 6, 33, 70, 49, 240, 96, 221, 35, 122, 219, 177, 212, ++ 248, 244, 0, 205, 247, 2, 250, 7, 70, 168, 185, 32, 70, 4, 241, 188, ++ 1, 2, 34, 59, 240, 220, 217, 34, 126, 12, 174, 70, 248, 36, 45, 4, 241, ++ 25, 1, 4, 168, 198, 247, 181, 249, 40, 70, 26, 33, 50, 70, 36, 35, 0, ++ 151, 213, 247, 195, 255, 13, 176, 240, 189, 128, 238, 54, 0, 19, 181, ++ 2, 34, 4, 70, 13, 241, 6, 1, 238, 243, 205, 241, 227, 104, 189, 248, ++ 6, 32, 163, 248, 94, 38, 28, 189, 8, 181, 67, 104, 200, 88, 40, 177, ++ 8, 48, 199, 243, 202, 245, 0, 48, 24, 191, 1, 32, 8, 189, 67, 104, 200, ++ 88, 8, 177, 144, 248, 160, 0, 112, 71, 67, 104, 203, 88, 27, 177, 177, ++ 248, 90, 32, 195, 248, 164, 32, 112, 71, 67, 104, 200, 88, 88, 177, ++ 208, 248, 164, 48, 32, 43, 5, 209, 144, 248, 161, 0, 0, 48, 24, 191, ++ 1, 32, 0, 224, 0, 32, 192, 178, 112, 71, 45, 233, 240, 65, 32, 35, 138, ++ 176, 5, 70, 15, 70, 144, 70, 64, 106, 1, 33, 0, 34, 201, 247, 117, 248, ++ 0, 36, 9, 144, 38, 70, 0, 224, 1, 38, 40, 104, 1, 169, 32, 34, 238, ++ 243, 136, 241, 1, 33, 1, 170, 32, 35, 9, 152, 201, 247, 38, 249, 9, ++ 152, 170, 105, 1, 70, 201, 247, 176, 250, 9, 152, 169, 105, 201, 247, ++ 122, 252, 54, 185, 67, 28, 4, 208, 56, 70, 9, 153, 201, 247, 240, 249, ++ 9, 224, 44, 185, 1, 40, 4, 208, 64, 70, 9, 153, 201, 247, 232, 249, ++ 1, 36, 0, 46, 217, 208, 0, 44, 214, 208, 9, 168, 201, 247, 152, 249, ++ 1, 32, 10, 176, 189, 232, 240, 129, 45, 233, 240, 79, 145, 232, 16, ++ 2, 34, 104, 251, 176, 0, 38, 208, 248, 0, 128, 6, 146, 5, 70, 15, 70, ++ 96, 106, 1, 33, 50, 70, 227, 105, 113, 150, 117, 150, 118, 150, 119, ++ 150, 120, 150, 201, 247, 42, 248, 113, 144, 0, 40, 0, 240, 45, 129, ++ 32, 105, 204, 247, 55, 248, 118, 144, 0, 40, 0, 240, 38, 129, 1, 33, ++ 32, 35, 50, 70, 96, 106, 201, 247, 25, 248, 1, 33, 32, 35, 119, 144, ++ 50, 70, 96, 106, 201, 247, 18, 248, 8, 241, 20, 8, 1, 33, 32, 35, 120, ++ 144, 62, 170, 160, 105, 9, 241, 194, 9, 201, 247, 43, 249, 6, 34, 64, ++ 70, 73, 70, 198, 247, 226, 248, 176, 66, 110, 168, 7, 221, 65, 70, 6, ++ 34, 198, 247, 238, 248, 13, 245, 223, 112, 73, 70, 6, 224, 73, 70, 6, ++ 34, 198, 247, 230, 248, 13, 245, 223, 112, 65, 70, 6, 34, 8, 55, 198, ++ 247, 223, 248, 56, 70, 199, 243, 16, 245, 0, 40, 0, 240, 237, 128, 56, ++ 70, 199, 243, 10, 245, 6, 70, 57, 70, 50, 70, 9, 168, 198, 247, 208, ++ 248, 115, 28, 0, 33, 32, 34, 86, 168, 7, 147, 199, 243, 73, 244, 32, ++ 70, 119, 153, 120, 154, 255, 247, 80, 255, 79, 240, 0, 9, 79, 240, 1, ++ 8, 47, 70, 9, 170, 114, 171, 2, 248, 6, 128, 12, 33, 13, 245, 156, 123, ++ 1, 147, 110, 168, 7, 155, 205, 248, 0, 176, 202, 243, 215, 245, 114, ++ 153, 120, 72, 5, 145, 199, 243, 224, 244, 62, 170, 3, 70, 79, 240, 32, ++ 10, 0, 146, 42, 173, 5, 153, 115, 74, 88, 70, 205, 248, 4, 160, 2, 149, ++ 205, 248, 12, 160, 202, 243, 156, 245, 1, 33, 42, 70, 83, 70, 113, 152, ++ 201, 247, 100, 248, 6, 152, 255, 247, 233, 254, 113, 152, 161, 105, ++ 201, 247, 5, 249, 0, 40, 43, 218, 120, 155, 113, 153, 0, 147, 102, 75, ++ 118, 154, 1, 147, 6, 155, 2, 147, 32, 105, 119, 155, 204, 247, 76, 251, ++ 240, 185, 185, 241, 0, 15, 25, 209, 32, 105, 118, 153, 204, 247, 161, ++ 250, 176, 177, 89, 70, 114, 154, 86, 168, 198, 247, 115, 248, 118, 152, ++ 115, 169, 116, 170, 204, 247, 1, 248, 115, 153, 116, 154, 215, 248, ++ 144, 0, 204, 247, 12, 248, 32, 104, 9, 169, 50, 70, 238, 243, 141, 240, ++ 79, 240, 1, 9, 8, 241, 1, 8, 95, 250, 136, 248, 184, 241, 41, 15, 154, ++ 209, 61, 70, 185, 241, 0, 15, 105, 208, 215, 248, 144, 0, 115, 169, ++ 116, 170, 203, 247, 227, 255, 32, 35, 1, 33, 94, 170, 116, 152, 201, ++ 247, 123, 248, 114, 155, 122, 170, 211, 24, 19, 248, 145, 44, 157, 248, ++ 151, 49, 83, 64, 218, 7, 26, 213, 227, 105, 1, 33, 0, 34, 96, 106, 200, ++ 247, 71, 255, 1, 33, 2, 70, 121, 144, 32, 105, 203, 247, 176, 251, 116, ++ 152, 121, 153, 2, 70, 0, 35, 201, 247, 83, 249, 215, 248, 144, 0, 115, ++ 153, 116, 154, 203, 247, 204, 255, 121, 168, 201, 247, 133, 248, 32, ++ 104, 102, 169, 32, 34, 238, 243, 74, 240, 32, 35, 1, 33, 102, 170, 232, ++ 111, 200, 247, 232, 255, 32, 104, 70, 169, 32, 34, 238, 243, 63, 240, ++ 96, 106, 1, 33, 0, 34, 32, 35, 200, 247, 28, 255, 117, 144, 0, 179, ++ 1, 33, 70, 170, 32, 35, 200, 247, 214, 255, 99, 105, 104, 111, 233, ++ 111, 117, 154, 201, 247, 14, 249, 213, 248, 152, 32, 213, 248, 144, ++ 0, 117, 153, 204, 247, 1, 254, 213, 248, 152, 0, 0, 36, 1, 70, 204, ++ 247, 42, 250, 213, 248, 152, 0, 5, 241, 128, 1, 5, 241, 132, 2, 203, ++ 247, 128, 255, 1, 224, 79, 240, 255, 52, 117, 168, 201, 247, 71, 248, ++ 120, 168, 201, 247, 68, 248, 119, 168, 201, 247, 65, 248, 113, 168, ++ 201, 247, 62, 248, 118, 168, 203, 247, 48, 255, 0, 33, 32, 34, 70, 168, ++ 199, 243, 86, 243, 0, 33, 80, 34, 42, 168, 199, 243, 81, 243, 0, 33, ++ 32, 34, 78, 168, 199, 243, 76, 243, 0, 33, 32, 34, 86, 168, 199, 243, ++ 71, 243, 102, 168, 0, 33, 32, 34, 199, 243, 66, 243, 32, 70, 123, 176, ++ 189, 232, 240, 143, 164, 88, 4, 0, 89, 188, 3, 0, 128, 104, 1, 43, 0, ++ 153, 18, 88, 13, 209, 57, 185, 178, 248, 112, 0, 8, 177, 2, 48, 0, 224, ++ 2, 32, 96, 48, 112, 71, 77, 41, 12, 191, 2, 32, 0, 32, 112, 71, 2, 43, ++ 12, 191, 34, 32, 0, 32, 112, 71, 112, 181, 129, 104, 182, 176, 1, 43, ++ 58, 158, 59, 156, 85, 88, 48, 209, 14, 177, 77, 46, 119, 209, 181, 248, ++ 102, 32, 54, 169, 33, 248, 4, 45, 32, 70, 2, 34, 197, 247, 142, 255, ++ 2, 52, 0, 46, 107, 209, 181, 248, 112, 32, 50, 177, 32, 70, 233, 110, ++ 197, 247, 132, 255, 181, 248, 112, 48, 228, 24, 34, 70, 1, 33, 32, 35, ++ 104, 111, 200, 247, 172, 255, 4, 241, 32, 2, 1, 33, 32, 35, 213, 248, ++ 128, 0, 200, 247, 164, 255, 4, 241, 64, 2, 213, 248, 132, 0, 1, 33, ++ 32, 35, 200, 247, 156, 255, 96, 52, 73, 224, 2, 43, 71, 209, 181, 248, ++ 98, 32, 54, 169, 33, 248, 2, 45, 32, 70, 26, 70, 197, 247, 94, 255, ++ 189, 248, 214, 48, 54, 174, 38, 248, 204, 61, 1, 33, 13, 241, 14, 2, ++ 32, 35, 104, 111, 200, 247, 131, 255, 1, 33, 13, 241, 46, 2, 32, 35, ++ 213, 248, 128, 0, 200, 247, 123, 255, 1, 33, 13, 241, 78, 2, 32, 35, ++ 213, 248, 132, 0, 200, 247, 115, 255, 1, 33, 13, 241, 110, 2, 32, 35, ++ 168, 111, 200, 247, 108, 255, 1, 33, 13, 241, 142, 2, 32, 35, 213, 248, ++ 136, 0, 200, 247, 100, 255, 1, 33, 13, 241, 174, 2, 32, 35, 213, 248, ++ 140, 0, 200, 247, 92, 255, 163, 28, 0, 147, 52, 171, 1, 147, 5, 241, ++ 24, 0, 32, 33, 50, 70, 194, 35, 202, 243, 70, 244, 34, 52, 32, 70, 54, ++ 176, 112, 189, 8, 181, 88, 177, 90, 177, 129, 104, 82, 88, 66, 177, ++ 2, 241, 8, 1, 24, 70, 16, 34, 197, 247, 16, 255, 1, 34, 0, 224, 2, 70, ++ 16, 70, 8, 189, 45, 233, 240, 79, 146, 70, 209, 248, 244, 32, 137, 176, ++ 178, 248, 98, 32, 18, 158, 194, 243, 64, 18, 7, 146, 130, 104, 29, 70, ++ 180, 88, 66, 104, 7, 70, 81, 248, 2, 128, 148, 248, 88, 32, 137, 70, ++ 221, 248, 76, 176, 20, 155, 3, 42, 0, 242, 224, 129, 223, 232, 18, 240, ++ 4, 0, 111, 0, 254, 0, 166, 1, 1, 45, 53, 209, 187, 248, 4, 32, 7, 43, ++ 145, 178, 140, 191, 187, 248, 6, 0, 255, 32, 0, 41, 64, 240, 153, 128, ++ 19, 40, 16, 208, 3, 32, 1, 34, 77, 35, 141, 232, 13, 0, 7, 154, 3, 145, ++ 4, 145, 5, 146, 72, 70, 6, 241, 20, 1, 82, 70, 51, 70, 217, 247, 46, ++ 249, 133, 224, 164, 248, 96, 32, 164, 248, 98, 32, 164, 248, 100, 32, ++ 32, 70, 65, 70, 6, 147, 255, 247, 138, 253, 6, 155, 0, 40, 119, 209, ++ 1, 147, 56, 70, 73, 70, 82, 70, 51, 70, 205, 248, 0, 176, 255, 247, ++ 170, 249, 124, 224, 0, 45, 64, 240, 159, 129, 164, 248, 96, 80, 164, ++ 248, 98, 80, 164, 248, 100, 80, 32, 70, 65, 70, 255, 247, 112, 253, ++ 0, 40, 94, 209, 3, 35, 79, 240, 1, 11, 141, 232, 8, 8, 7, 155, 6, 241, ++ 20, 1, 5, 147, 82, 70, 51, 70, 72, 70, 2, 149, 3, 149, 4, 149, 217, ++ 247, 245, 248, 218, 248, 0, 48, 161, 110, 196, 248, 89, 48, 186, 248, ++ 4, 48, 164, 248, 93, 48, 59, 104, 216, 248, 136, 32, 152, 104, 43, 70, ++ 220, 243, 63, 246, 132, 248, 88, 176, 113, 225, 1, 45, 104, 209, 2, ++ 104, 161, 110, 144, 104, 6, 147, 220, 243, 90, 246, 180, 248, 112, 32, ++ 6, 155, 50, 177, 224, 110, 206, 247, 12, 254, 0, 33, 6, 155, 164, 248, ++ 112, 16, 187, 248, 4, 80, 7, 43, 140, 191, 187, 248, 6, 32, 255, 34, ++ 76, 45, 21, 209, 0, 37, 64, 70, 33, 70, 90, 70, 164, 248, 96, 80, 255, ++ 247, 62, 248, 7, 154, 3, 35, 79, 240, 1, 12, 141, 232, 8, 16, 2, 149, ++ 3, 149, 4, 149, 5, 146, 72, 70, 6, 241, 20, 1, 172, 224, 77, 45, 8, ++ 209, 180, 248, 102, 48, 147, 66, 98, 209, 0, 35, 132, 248, 88, 48, 2, ++ 37, 52, 225, 0, 45, 91, 209, 19, 42, 13, 209, 1, 147, 56, 70, 73, 70, ++ 82, 70, 51, 70, 205, 248, 0, 176, 255, 247, 170, 249, 0, 40, 20, 191, ++ 2, 37, 0, 37, 34, 225, 180, 248, 96, 48, 5, 43, 0, 242, 20, 129, 3, ++ 32, 1, 35, 79, 240, 77, 14, 141, 232, 9, 64, 7, 155, 72, 70, 5, 147, ++ 6, 241, 20, 1, 51, 70, 82, 70, 3, 149, 4, 149, 217, 247, 125, 248, 180, ++ 248, 96, 48, 1, 51, 164, 248, 96, 48, 119, 224, 171, 30, 1, 43, 79, ++ 240, 0, 3, 0, 242, 250, 128, 180, 248, 96, 32, 5, 42, 195, 216, 3, 45, ++ 9, 209, 1, 50, 164, 248, 96, 32, 2, 104, 161, 110, 144, 104, 216, 248, ++ 136, 32, 220, 243, 187, 245, 0, 37, 3, 33, 1, 35, 141, 232, 42, 0, 7, ++ 153, 3, 149, 5, 145, 4, 149, 72, 70, 6, 241, 20, 1, 82, 70, 208, 224, ++ 1, 45, 90, 209, 2, 104, 187, 248, 4, 80, 144, 104, 161, 110, 6, 147, ++ 220, 243, 201, 245, 6, 155, 69, 177, 59, 104, 161, 110, 152, 104, 216, ++ 248, 136, 32, 0, 35, 220, 243, 153, 245, 202, 224, 180, 248, 96, 32, ++ 5, 42, 0, 242, 191, 128, 7, 43, 136, 191, 187, 248, 6, 48, 180, 248, ++ 102, 16, 152, 191, 255, 35, 153, 66, 64, 240, 187, 128, 180, 248, 98, ++ 48, 1, 50, 164, 248, 96, 32, 1, 51, 7, 154, 164, 248, 98, 48, 6, 241, ++ 20, 12, 1, 35, 0, 37, 97, 70, 79, 240, 3, 11, 1, 147, 5, 146, 51, 70, ++ 72, 70, 82, 70, 205, 248, 24, 192, 205, 248, 0, 176, 2, 149, 3, 149, ++ 4, 149, 217, 247, 16, 248, 2, 35, 1, 147, 221, 248, 24, 192, 7, 155, ++ 205, 248, 0, 176, 2, 149, 3, 149, 4, 149, 5, 147, 72, 70, 97, 70, 82, ++ 70, 51, 70, 216, 247, 255, 255, 59, 104, 161, 110, 152, 104, 216, 248, ++ 136, 32, 43, 70, 220, 243, 81, 245, 133, 224, 2, 45, 26, 209, 39, 43, ++ 126, 217, 64, 70, 33, 70, 90, 70, 255, 247, 184, 249, 5, 70, 0, 40, ++ 121, 208, 59, 104, 79, 240, 255, 49, 152, 104, 164, 248, 98, 16, 161, ++ 110, 220, 243, 97, 245, 64, 70, 254, 247, 51, 255, 3, 35, 132, 248, ++ 88, 48, 1, 37, 104, 224, 3, 45, 79, 240, 0, 11, 95, 209, 180, 248, 96, ++ 48, 5, 43, 2, 217, 132, 248, 88, 176, 38, 231, 1, 51, 164, 248, 96, ++ 48, 180, 248, 98, 48, 7, 154, 1, 51, 164, 248, 98, 48, 2, 35, 1, 147, ++ 5, 146, 6, 241, 20, 1, 82, 70, 51, 70, 72, 70, 0, 149, 205, 248, 8, ++ 176, 205, 248, 12, 176, 205, 248, 16, 176, 216, 247, 180, 255, 59, 104, ++ 161, 110, 152, 104, 216, 248, 136, 32, 91, 70, 220, 243, 6, 245, 53, ++ 224, 2, 45, 42, 209, 180, 248, 96, 32, 5, 42, 3, 217, 0, 35, 132, 248, ++ 88, 48, 48, 224, 39, 43, 43, 217, 64, 70, 33, 70, 90, 70, 255, 247, ++ 153, 249, 56, 179, 180, 248, 96, 48, 7, 153, 1, 51, 164, 248, 96, 48, ++ 79, 240, 255, 51, 164, 248, 98, 48, 3, 35, 141, 232, 40, 0, 0, 37, 5, ++ 145, 2, 149, 3, 149, 4, 149, 72, 70, 6, 241, 20, 1, 9, 241, 194, 2, ++ 51, 70, 216, 247, 127, 255, 13, 224, 3, 45, 79, 240, 0, 5, 9, 209, 132, ++ 248, 88, 80, 207, 230, 29, 70, 4, 224, 93, 70, 2, 224, 0, 37, 0, 224, ++ 5, 70, 40, 70, 9, 176, 189, 232, 240, 143, 240, 181, 4, 105, 3, 70, ++ 39, 104, 133, 176, 215, 248, 80, 8, 33, 70, 130, 104, 158, 88, 0, 147, ++ 6, 241, 89, 5, 0, 35, 1, 147, 2, 147, 42, 70, 3, 35, 255, 247, 233, ++ 253, 2, 40, 12, 209, 215, 248, 80, 8, 49, 70, 254, 247, 150, 254, 3, ++ 35, 0, 147, 32, 70, 1, 33, 42, 70, 16, 35, 229, 247, 205, 252, 5, 176, ++ 240, 189, 45, 233, 255, 71, 7, 70, 138, 70, 153, 70, 208, 248, 0, 128, ++ 20, 70, 42, 179, 131, 104, 0, 37, 214, 88, 216, 248, 8, 0, 177, 110, ++ 220, 243, 182, 244, 134, 248, 88, 80, 141, 232, 48, 0, 2, 149, 216, ++ 248, 80, 8, 81, 70, 74, 70, 43, 70, 255, 247, 187, 253, 64, 185, 32, ++ 70, 19, 33, 45, 240, 115, 223, 32, 70, 12, 33, 46, 240, 203, 217, 9, ++ 224, 2, 40, 7, 209, 56, 70, 49, 70, 254, 247, 95, 254, 40, 70, 2, 224, ++ 16, 70, 0, 224, 1, 32, 4, 176, 189, 232, 240, 135, 45, 233, 240, 79, ++ 137, 176, 152, 70, 7, 104, 18, 155, 6, 70, 7, 147, 59, 104, 13, 70, ++ 147, 248, 102, 49, 147, 70, 0, 43, 93, 208, 184, 248, 0, 48, 2, 241, ++ 10, 10, 5, 147, 184, 248, 4, 48, 56, 70, 82, 70, 6, 147, 184, 248, 2, ++ 144, 0, 240, 89, 252, 5, 155, 4, 70, 3, 43, 75, 209, 185, 241, 1, 15, ++ 3, 208, 185, 241, 2, 15, 69, 209, 29, 224, 56, 185, 56, 70, 41, 70, ++ 82, 70, 0, 240, 1, 253, 4, 70, 0, 40, 59, 208, 7, 155, 141, 232, 16, ++ 1, 2, 147, 215, 248, 80, 8, 1, 35, 41, 70, 11, 241, 16, 2, 255, 247, ++ 102, 253, 2, 40, 45, 209, 179, 104, 48, 70, 225, 88, 254, 247, 19, 254, ++ 3, 35, 21, 224, 0, 40, 36, 208, 7, 155, 141, 232, 1, 1, 2, 147, 215, ++ 248, 80, 8, 41, 70, 11, 241, 16, 2, 75, 70, 255, 247, 79, 253, 2, 40, ++ 9, 209, 179, 104, 48, 70, 225, 88, 254, 247, 252, 253, 5, 155, 18, 147, ++ 40, 70, 1, 33, 5, 224, 1, 40, 10, 209, 5, 155, 40, 70, 18, 147, 0, 33, ++ 6, 155, 82, 70, 9, 176, 189, 232, 240, 79, 229, 247, 41, 188, 9, 176, ++ 189, 232, 240, 143, 192, 121, 1, 40, 5, 217, 160, 241, 4, 3, 88, 66, ++ 64, 235, 3, 0, 112, 71, 1, 32, 112, 71, 55, 181, 0, 35, 1, 147, 7, 155, ++ 4, 70, 3, 43, 21, 70, 4, 217, 1, 168, 6, 153, 4, 34, 197, 247, 38, 252, ++ 8, 45, 2, 208, 9, 45, 11, 209, 4, 224, 180, 248, 10, 34, 8, 155, 26, ++ 96, 3, 224, 189, 248, 4, 48, 164, 248, 10, 50, 0, 32, 1, 224, 111, 240, ++ 22, 0, 62, 189, 0, 0, 45, 233, 240, 65, 144, 248, 14, 50, 134, 176, ++ 4, 70, 208, 248, 36, 130, 83, 177, 144, 249, 224, 81, 208, 248, 20, ++ 50, 1, 61, 36, 34, 2, 251, 5, 53, 144, 249, 225, 113, 3, 224, 208, 248, ++ 20, 82, 208, 248, 16, 114, 0, 38, 17, 224, 11, 75, 160, 104, 0, 147, ++ 1, 147, 0, 35, 2, 147, 3, 147, 4, 147, 43, 104, 65, 70, 42, 29, 217, ++ 247, 170, 250, 148, 248, 14, 50, 3, 185, 36, 53, 1, 54, 190, 66, 235, ++ 219, 6, 176, 189, 232, 240, 129, 0, 191, 236, 125, 135, 0, 115, 181, ++ 4, 70, 128, 104, 243, 243, 147, 240, 160, 104, 237, 243, 194, 240, 160, ++ 104, 0, 37, 176, 248, 70, 20, 241, 243, 92, 245, 163, 104, 211, 248, ++ 104, 50, 88, 89, 56, 177, 131, 121, 43, 185, 3, 122, 27, 177, 3, 124, ++ 11, 185, 237, 243, 49, 246, 4, 53, 32, 45, 239, 209, 0, 33, 10, 70, ++ 11, 70, 160, 104, 23, 240, 190, 217, 3, 37, 1, 33, 0, 35, 160, 104, ++ 79, 244, 128, 98, 0, 149, 238, 243, 187, 243, 0, 33, 10, 70, 11, 70, ++ 160, 104, 0, 149, 23, 240, 242, 217, 163, 104, 0, 34, 131, 248, 13, ++ 34, 160, 104, 212, 247, 162, 255, 160, 104, 237, 243, 16, 240, 163, ++ 104, 147, 248, 116, 34, 209, 7, 13, 213, 27, 106, 24, 105, 241, 247, ++ 83, 249, 160, 104, 243, 243, 216, 242, 163, 104, 147, 248, 116, 34, ++ 34, 240, 1, 2, 131, 248, 116, 34, 0, 38, 163, 104, 211, 248, 104, 50, ++ 157, 89, 0, 45, 57, 208, 170, 121, 0, 42, 54, 209, 213, 248, 4, 49, ++ 89, 108, 33, 240, 1, 1, 89, 100, 147, 248, 118, 16, 1, 41, 8, 191, 131, ++ 248, 118, 32, 43, 122, 67, 179, 213, 248, 4, 49, 26, 120, 1, 42, 1, ++ 209, 90, 127, 10, 179, 27, 122, 251, 177, 160, 104, 3, 104, 147, 248, ++ 60, 48, 59, 177, 213, 248, 40, 51, 35, 177, 26, 137, 176, 248, 70, 52, ++ 154, 66, 18, 209, 41, 70, 1, 34, 5, 240, 245, 217, 1, 70, 72, 177, 180, ++ 248, 228, 33, 213, 248, 4, 49, 82, 8, 218, 98, 40, 70, 250, 247, 242, ++ 253, 2, 224, 40, 70, 215, 247, 29, 252, 4, 54, 32, 46, 188, 209, 160, ++ 104, 242, 243, 168, 242, 160, 104, 2, 176, 189, 232, 112, 64, 240, 243, ++ 132, 181, 248, 181, 131, 104, 4, 70, 26, 104, 6, 104, 146, 248, 173, ++ 112, 71, 177, 211, 248, 92, 1, 179, 248, 72, 20, 18, 240, 40, 223, 7, ++ 28, 24, 191, 1, 39, 163, 104, 211, 248, 40, 53, 0, 43, 59, 209, 0, 47, ++ 57, 209, 179, 136, 67, 240, 32, 3, 179, 128, 163, 104, 211, 248, 104, ++ 34, 213, 89, 21, 179, 170, 121, 2, 187, 213, 248, 4, 33, 81, 108, 65, ++ 240, 1, 1, 81, 100, 41, 122, 193, 177, 18, 122, 178, 185, 26, 104, 146, ++ 248, 60, 32, 58, 177, 213, 248, 40, 35, 34, 177, 18, 137, 179, 248, ++ 70, 52, 154, 66, 10, 209, 40, 70, 1, 33, 215, 247, 212, 251, 213, 248, ++ 4, 49, 26, 122, 18, 177, 1, 34, 131, 248, 118, 32, 4, 55, 32, 47, 212, ++ 209, 160, 104, 238, 243, 212, 245, 163, 104, 147, 248, 36, 50, 27, 185, ++ 179, 136, 35, 240, 32, 3, 179, 128, 160, 104, 242, 243, 77, 242, 176, ++ 136, 16, 240, 32, 0, 9, 208, 163, 104, 212, 248, 248, 17, 152, 104, ++ 148, 248, 64, 34, 0, 35, 220, 243, 156, 242, 1, 32, 248, 189, 45, 233, ++ 240, 67, 5, 104, 208, 248, 8, 144, 171, 136, 4, 70, 67, 244, 0, 99, ++ 208, 248, 36, 98, 135, 176, 171, 128, 217, 248, 16, 0, 23, 240, 245, ++ 216, 216, 177, 171, 121, 163, 177, 160, 104, 208, 248, 16, 19, 231, ++ 243, 161, 247, 32, 70, 4, 33, 43, 240, 33, 222, 4, 35, 0, 147, 160, ++ 104, 0, 35, 49, 70, 26, 34, 1, 147, 2, 147, 3, 147, 4, 147, 231, 243, ++ 193, 247, 163, 104, 152, 104, 207, 247, 162, 255, 130, 225, 148, 249, ++ 224, 49, 2, 51, 3, 209, 255, 35, 132, 248, 224, 49, 122, 225, 163, 104, ++ 27, 104, 27, 126, 0, 43, 0, 240, 117, 129, 171, 136, 19, 244, 132, 111, ++ 8, 208, 35, 244, 132, 99, 171, 128, 32, 70, 44, 240, 26, 218, 0, 40, ++ 64, 240, 104, 129, 171, 136, 26, 7, 68, 191, 35, 240, 8, 3, 171, 128, ++ 148, 248, 224, 49, 1, 51, 132, 248, 224, 49, 163, 105, 4, 235, 67, 3, ++ 158, 139, 163, 104, 49, 70, 163, 248, 48, 99, 211, 248, 92, 1, 18, 240, ++ 114, 222, 72, 185, 163, 104, 49, 70, 211, 248, 92, 1, 18, 240, 253, ++ 223, 16, 177, 148, 248, 226, 129, 1, 224, 79, 240, 1, 8, 148, 249, 224, ++ 49, 79, 250, 136, 242, 147, 66, 101, 221, 1, 50, 147, 66, 3, 209, 171, ++ 136, 35, 240, 16, 3, 171, 128, 212, 248, 220, 17, 163, 105, 1, 57, 139, ++ 66, 188, 191, 4, 235, 67, 3, 223, 139, 171, 136, 168, 191, 255, 39, ++ 19, 240, 128, 1, 28, 191, 212, 248, 240, 17, 1, 49, 196, 248, 240, 17, ++ 148, 249, 224, 17, 145, 66, 54, 209, 180, 248, 228, 33, 0, 42, 50, 208, ++ 255, 47, 64, 208, 27, 4, 48, 212, 212, 248, 240, 33, 212, 248, 236, ++ 49, 154, 66, 13, 218, 163, 104, 49, 70, 211, 248, 92, 1, 18, 240, 44, ++ 222, 48, 185, 163, 104, 57, 70, 211, 248, 92, 1, 18, 240, 37, 222, 224, ++ 177, 32, 70, 255, 247, 77, 254, 170, 136, 18, 244, 0, 83, 2, 208, 212, ++ 248, 60, 114, 118, 224, 34, 240, 128, 2, 170, 128, 162, 104, 212, 248, ++ 248, 17, 144, 104, 180, 248, 228, 33, 220, 243, 215, 241, 171, 136, ++ 111, 234, 67, 67, 111, 234, 83, 67, 230, 224, 255, 47, 13, 208, 163, ++ 105, 62, 70, 1, 51, 163, 97, 163, 104, 163, 248, 48, 115, 0, 35, 132, ++ 248, 224, 49, 171, 136, 91, 4, 91, 12, 171, 128, 148, 249, 224, 49, ++ 251, 185, 171, 136, 24, 6, 25, 212, 163, 104, 179, 248, 72, 36, 179, ++ 248, 70, 4, 144, 66, 18, 209, 200, 243, 14, 240, 176, 66, 14, 208, 32, ++ 70, 43, 240, 69, 223, 32, 70, 255, 247, 172, 254, 0, 40, 64, 240, 190, ++ 128, 32, 70, 44, 240, 106, 217, 0, 40, 64, 240, 184, 128, 1, 35, 132, ++ 248, 224, 49, 148, 249, 224, 49, 0, 43, 38, 221, 79, 250, 136, 248, ++ 67, 69, 34, 220, 107, 106, 217, 7, 10, 212, 48, 70, 199, 243, 204, 247, ++ 163, 104, 7, 70, 179, 248, 72, 4, 199, 243, 198, 247, 135, 66, 15, 208, ++ 160, 104, 242, 243, 129, 246, 32, 70, 43, 240, 26, 223, 160, 104, 213, ++ 247, 247, 252, 160, 104, 49, 70, 241, 243, 73, 243, 160, 104, 236, 243, ++ 42, 246, 32, 70, 49, 70, 43, 240, 146, 221, 137, 224, 171, 136, 32, ++ 70, 67, 244, 0, 83, 171, 128, 255, 247, 208, 253, 0, 39, 171, 136, 72, ++ 70, 35, 240, 128, 3, 171, 128, 79, 240, 255, 51, 163, 97, 33, 70, 0, ++ 38, 44, 240, 29, 217, 174, 113, 163, 104, 50, 70, 27, 106, 2, 33, 24, ++ 105, 240, 247, 37, 255, 32, 70, 44, 240, 254, 216, 160, 104, 242, 243, ++ 245, 240, 160, 104, 239, 243, 154, 244, 160, 104, 239, 243, 241, 244, ++ 163, 104, 26, 104, 146, 248, 175, 32, 34, 177, 211, 248, 136, 1, 49, ++ 70, 243, 243, 213, 246, 163, 104, 27, 104, 147, 248, 79, 32, 146, 7, ++ 6, 208, 147, 249, 82, 48, 27, 177, 32, 70, 0, 33, 43, 240, 172, 219, ++ 32, 70, 57, 70, 43, 240, 212, 220, 5, 241, 12, 0, 204, 247, 158, 249, ++ 0, 179, 171, 104, 2, 43, 29, 209, 0, 38, 163, 104, 211, 248, 104, 34, ++ 144, 89, 160, 177, 130, 121, 146, 185, 2, 122, 130, 177, 208, 248, 252, ++ 32, 106, 177, 146, 248, 93, 16, 81, 177, 146, 248, 60, 16, 57, 177, ++ 81, 108, 41, 185, 1, 33, 81, 100, 211, 248, 16, 19, 3, 240, 7, 217, ++ 4, 54, 32, 46, 226, 209, 160, 104, 0, 38, 208, 248, 16, 19, 231, 243, ++ 36, 246, 163, 104, 211, 248, 104, 50, 152, 89, 112, 177, 131, 121, 99, ++ 185, 3, 122, 83, 177, 3, 124, 67, 177, 208, 248, 4, 49, 26, 120, 2, ++ 42, 3, 209, 27, 122, 11, 185, 250, 247, 212, 251, 4, 54, 32, 46, 232, ++ 209, 171, 136, 35, 244, 0, 83, 171, 128, 171, 136, 35, 244, 0, 99, 171, ++ 128, 7, 176, 189, 232, 240, 131, 17, 177, 8, 70, 206, 247, 189, 184, ++ 112, 71, 56, 181, 0, 35, 129, 104, 4, 70, 131, 96, 4, 224, 13, 104, ++ 32, 70, 255, 247, 241, 255, 41, 70, 0, 41, 248, 209, 56, 189, 24, 177, ++ 3, 104, 152, 104, 0, 177, 0, 104, 112, 71, 3, 70, 138, 0, 7, 224, 4, ++ 216, 24, 104, 208, 248, 104, 2, 128, 88, 32, 185, 1, 49, 4, 50, 7, 41, ++ 245, 221, 0, 32, 112, 71, 48, 181, 208, 248, 164, 33, 3, 105, 34, 244, ++ 0, 82, 25, 104, 192, 248, 164, 33, 145, 248, 33, 66, 20, 177, 156, 121, ++ 0, 44, 56, 208, 18, 240, 1, 15, 53, 209, 69, 104, 27, 76, 44, 64, 0, ++ 44, 48, 208, 26, 76, 44, 64, 25, 77, 172, 66, 43, 209, 144, 248, 36, ++ 64, 20, 240, 18, 15, 38, 208, 211, 248, 72, 67, 28, 177, 164, 123, 20, ++ 240, 1, 15, 31, 209, 209, 248, 8, 66, 228, 185, 179, 248, 90, 64, 28, ++ 185, 28, 109, 20, 240, 1, 15, 17, 208, 28, 109, 64, 242, 55, 19, 35, ++ 64, 131, 177, 131, 108, 91, 7, 13, 213, 195, 104, 91, 177, 27, 122, ++ 4, 43, 8, 209, 145, 248, 148, 50, 43, 185, 35, 7, 3, 212, 66, 244, 0, ++ 82, 192, 248, 164, 33, 48, 189, 0, 191, 64, 0, 1, 0, 64, 0, 4, 0, 208, ++ 248, 36, 1, 48, 181, 128, 105, 20, 121, 9, 24, 208, 120, 81, 248, 35, ++ 48, 68, 64, 80, 121, 68, 64, 8, 122, 148, 251, 240, 245, 0, 251, 21, ++ 64, 83, 248, 32, 48, 131, 177, 27, 104, 14, 224, 24, 104, 84, 136, 193, ++ 138, 21, 136, 76, 64, 129, 138, 105, 64, 12, 67, 149, 136, 1, 139, 105, ++ 64, 33, 67, 137, 178, 25, 177, 91, 104, 0, 43, 238, 209, 24, 70, 48, ++ 189, 112, 181, 12, 104, 13, 70, 6, 70, 16, 34, 8, 70, 0, 33, 198, 243, ++ 252, 243, 44, 96, 32, 70, 0, 33, 242, 104, 198, 243, 246, 243, 4, 245, ++ 20, 115, 196, 248, 252, 48, 4, 245, 28, 115, 37, 96, 196, 248, 52, 49, ++ 112, 189, 56, 181, 5, 70, 12, 70, 23, 224, 32, 104, 40, 177, 3, 104, ++ 155, 104, 3, 177, 27, 104, 35, 96, 56, 189, 34, 122, 98, 177, 147, 249, ++ 68, 16, 40, 70, 1, 49, 255, 247, 77, 255, 96, 96, 40, 177, 171, 105, ++ 192, 24, 195, 104, 35, 96, 0, 224, 98, 96, 99, 104, 0, 43, 228, 209, ++ 35, 96, 24, 70, 56, 189, 0, 177, 0, 104, 192, 104, 112, 71, 56, 181, ++ 133, 105, 12, 70, 8, 104, 1, 34, 45, 240, 207, 218, 96, 89, 24, 177, ++ 189, 232, 56, 64, 205, 247, 214, 191, 56, 189, 3, 106, 91, 104, 255, ++ 247, 134, 191, 255, 247, 132, 191, 45, 233, 240, 71, 221, 248, 32, 160, ++ 0, 37, 7, 70, 14, 70, 144, 70, 153, 70, 202, 248, 0, 80, 215, 248, 104, ++ 50, 92, 89, 212, 177, 115, 136, 180, 248, 196, 32, 180, 248, 194, 16, ++ 90, 64, 51, 136, 75, 64, 26, 67, 180, 248, 198, 16, 179, 136, 75, 64, ++ 19, 67, 155, 178, 83, 185, 56, 70, 33, 70, 66, 70, 75, 70, 255, 247, ++ 95, 255, 24, 177, 202, 248, 0, 64, 189, 232, 240, 135, 4, 53, 32, 45, ++ 221, 209, 0, 32, 189, 232, 240, 135, 45, 233, 248, 67, 153, 70, 3, 104, ++ 208, 248, 36, 65, 219, 105, 23, 70, 27, 105, 34, 137, 5, 70, 154, 66, ++ 136, 70, 12, 218, 202, 243, 160, 244, 43, 104, 219, 105, 211, 248, 252, ++ 48, 152, 66, 4, 217, 32, 70, 44, 240, 105, 223, 6, 70, 120, 185, 40, ++ 70, 45, 240, 106, 217, 1, 70, 0, 40, 51, 208, 40, 70, 45, 240, 234, ++ 222, 0, 40, 46, 208, 32, 70, 44, 240, 89, 223, 6, 70, 72, 179, 35, 137, ++ 73, 70, 1, 51, 35, 129, 52, 104, 50, 70, 196, 248, 16, 128, 56, 104, ++ 96, 97, 187, 136, 40, 70, 35, 131, 2, 35, 45, 240, 1, 217, 7, 70, 40, ++ 177, 33, 70, 40, 70, 45, 240, 205, 222, 0, 36, 18, 224, 40, 70, 49, ++ 70, 66, 70, 45, 240, 86, 216, 40, 70, 33, 70, 217, 248, 4, 32, 67, 70, ++ 45, 240, 9, 216, 39, 97, 32, 70, 65, 70, 45, 240, 222, 219, 0, 224, ++ 4, 70, 32, 70, 189, 232, 248, 131, 45, 233, 240, 65, 31, 70, 19, 120, ++ 5, 70, 219, 7, 14, 70, 20, 70, 24, 212, 208, 248, 104, 6, 27, 240, 70, ++ 223, 1, 40, 21, 208, 4, 40, 19, 208, 40, 70, 49, 70, 34, 70, 59, 70, ++ 255, 247, 228, 254, 104, 185, 10, 55, 85, 248, 39, 48, 40, 70, 49, 70, ++ 34, 70, 189, 232, 240, 65, 255, 247, 133, 191, 0, 32, 189, 232, 240, ++ 129, 0, 32, 189, 232, 240, 129, 255, 247, 214, 191, 3, 106, 91, 104, ++ 255, 247, 210, 191, 195, 104, 200, 88, 112, 71, 4, 32, 112, 71, 208, ++ 248, 4, 49, 1, 51, 192, 248, 4, 49, 112, 71, 208, 248, 4, 49, 1, 59, ++ 192, 248, 4, 49, 112, 71, 3, 105, 154, 121, 26, 185, 211, 248, 0, 49, ++ 24, 105, 112, 71, 45, 240, 125, 154, 208, 248, 96, 49, 112, 181, 220, ++ 104, 13, 70, 225, 66, 8, 208, 142, 104, 22, 240, 8, 6, 4, 209, 8, 89, ++ 16, 177, 205, 247, 239, 254, 46, 81, 112, 189, 208, 248, 96, 49, 45, ++ 233, 240, 65, 222, 104, 211, 248, 16, 128, 12, 70, 129, 177, 141, 104, ++ 21, 240, 8, 5, 15, 209, 64, 70, 205, 247, 218, 254, 7, 70, 104, 177, ++ 41, 70, 66, 70, 198, 243, 186, 242, 167, 81, 40, 70, 189, 232, 240, ++ 129, 8, 70, 189, 232, 240, 129, 0, 32, 189, 232, 240, 129, 111, 240, ++ 26, 0, 189, 232, 240, 129, 56, 181, 4, 70, 8, 70, 13, 70, 255, 247, ++ 220, 254, 144, 177, 64, 108, 9, 75, 3, 64, 0, 240, 64, 112, 19, 185, ++ 176, 241, 128, 127, 3, 209, 0, 48, 24, 191, 1, 32, 56, 189, 227, 104, ++ 232, 88, 189, 232, 56, 64, 253, 247, 69, 190, 56, 189, 0, 191, 255, ++ 0, 0, 192, 112, 181, 20, 70, 18, 136, 30, 70, 4, 157, 255, 247, 140, ++ 255, 48, 177, 33, 70, 50, 70, 43, 70, 189, 232, 112, 64, 253, 247, 59, ++ 190, 112, 189, 112, 181, 20, 70, 30, 70, 157, 248, 16, 80, 255, 247, ++ 124, 255, 48, 177, 33, 70, 50, 70, 43, 70, 189, 232, 112, 64, 253, 247, ++ 219, 188, 112, 189, 128, 104, 253, 247, 199, 189, 45, 233, 240, 71, ++ 20, 70, 82, 136, 154, 70, 189, 248, 32, 80, 157, 248, 36, 144, 157, ++ 248, 40, 128, 157, 248, 44, 112, 157, 248, 48, 96, 255, 247, 95, 255, ++ 96, 177, 33, 70, 82, 70, 43, 70, 205, 248, 32, 144, 205, 248, 36, 128, ++ 10, 151, 11, 150, 189, 232, 240, 71, 253, 247, 213, 188, 189, 232, 240, ++ 135, 128, 104, 253, 247, 167, 188, 56, 181, 20, 70, 29, 70, 255, 247, ++ 71, 255, 33, 70, 42, 70, 189, 232, 56, 64, 253, 247, 68, 186, 45, 233, ++ 247, 79, 221, 248, 48, 176, 154, 70, 221, 248, 52, 144, 221, 248, 56, ++ 128, 157, 248, 60, 112, 157, 248, 64, 96, 157, 248, 68, 80, 157, 248, ++ 72, 64, 1, 146, 255, 247, 45, 255, 221, 248, 4, 192, 82, 70, 97, 70, ++ 91, 70, 205, 248, 48, 144, 205, 248, 52, 128, 14, 151, 15, 150, 16, ++ 149, 17, 148, 3, 176, 189, 232, 240, 79, 253, 247, 45, 189, 45, 233, ++ 247, 79, 156, 70, 157, 248, 48, 48, 20, 70, 82, 136, 157, 248, 52, 144, ++ 141, 232, 8, 16, 157, 248, 56, 128, 157, 248, 60, 112, 157, 248, 64, ++ 96, 157, 248, 68, 80, 157, 248, 72, 160, 157, 248, 76, 176, 255, 247, ++ 2, 255, 221, 248, 4, 192, 0, 155, 33, 70, 98, 70, 205, 248, 48, 144, ++ 205, 248, 52, 128, 14, 151, 15, 150, 16, 149, 205, 248, 68, 160, 205, ++ 248, 72, 176, 3, 176, 189, 232, 240, 79, 253, 247, 180, 188, 16, 181, ++ 20, 70, 82, 136, 255, 247, 232, 254, 33, 70, 189, 232, 16, 64, 253, ++ 247, 10, 186, 45, 233, 240, 79, 139, 104, 149, 176, 26, 7, 5, 70, 12, ++ 70, 208, 248, 96, 145, 176, 248, 72, 132, 0, 241, 190, 128, 79, 104, ++ 62, 3, 9, 213, 8, 244, 96, 88, 184, 245, 192, 95, 12, 191, 79, 240, ++ 2, 8, 79, 240, 1, 8, 1, 224, 79, 240, 1, 8, 213, 248, 116, 36, 146, ++ 249, 19, 16, 72, 28, 7, 209, 23, 244, 128, 55, 13, 208, 19, 240, 128, ++ 7, 24, 191, 255, 39, 8, 224, 1, 41, 5, 209, 23, 244, 128, 55, 3, 208, ++ 195, 243, 192, 23, 0, 224, 0, 39, 149, 249, 32, 18, 1, 49, 11, 209, ++ 184, 241, 2, 15, 3, 240, 1, 6, 64, 240, 137, 128, 153, 7, 4, 213, 70, ++ 240, 2, 6, 246, 178, 0, 224, 0, 38, 213, 248, 160, 1, 33, 70, 56, 240, ++ 161, 220, 99, 104, 131, 70, 218, 3, 5, 213, 213, 248, 116, 52, 147, ++ 248, 123, 48, 0, 43, 77, 209, 217, 248, 12, 48, 84, 248, 3, 160, 186, ++ 241, 0, 15, 112, 208, 40, 34, 10, 168, 4, 241, 76, 1, 196, 247, 254, ++ 253, 43, 104, 147, 248, 79, 48, 155, 7, 32, 208, 35, 105, 211, 248, ++ 204, 48, 216, 4, 27, 212, 148, 248, 14, 49, 155, 185, 3, 224, 0, 35, ++ 141, 248, 62, 48, 11, 224, 213, 248, 116, 36, 147, 120, 1, 43, 246, ++ 208, 146, 248, 60, 32, 1, 42, 242, 208, 2, 43, 8, 209, 0, 35, 141, 248, ++ 63, 48, 4, 224, 148, 248, 15, 49, 0, 43, 232, 208, 235, 231, 10, 171, ++ 141, 232, 8, 1, 118, 178, 0, 35, 127, 178, 4, 147, 5, 147, 6, 147, 7, ++ 147, 8, 147, 9, 147, 2, 150, 3, 151, 217, 248, 8, 0, 81, 70, 34, 70, ++ 91, 70, 253, 247, 243, 253, 213, 248, 228, 6, 33, 70, 45, 240, 206, ++ 221, 41, 224, 34, 70, 1, 35, 213, 248, 116, 20, 145, 248, 123, 16, 153, ++ 66, 2, 216, 0, 33, 130, 248, 98, 16, 1, 51, 219, 178, 1, 50, 4, 43, ++ 241, 209, 79, 240, 2, 10, 213, 248, 116, 52, 147, 248, 123, 48, 179, ++ 235, 234, 15, 5, 220, 4, 241, 97, 0, 10, 241, 85, 1, 198, 243, 102, ++ 247, 10, 241, 1, 10, 186, 241, 18, 15, 237, 209, 140, 231, 19, 108, ++ 0, 43, 24, 191, 0, 38, 120, 231, 21, 176, 189, 232, 240, 143, 31, 181, ++ 4, 70, 1, 169, 208, 248, 36, 1, 0, 34, 45, 240, 116, 216, 2, 224, 32, ++ 70, 255, 247, 38, 255, 1, 169, 212, 248, 36, 1, 255, 247, 19, 253, 1, ++ 70, 0, 40, 244, 209, 212, 248, 228, 6, 45, 240, 146, 221, 31, 189, 48, ++ 181, 13, 70, 133, 176, 4, 70, 1, 169, 208, 248, 36, 1, 42, 70, 45, 240, ++ 89, 216, 2, 224, 32, 70, 255, 247, 11, 255, 1, 169, 212, 248, 36, 1, ++ 255, 247, 248, 252, 1, 70, 0, 40, 244, 209, 212, 248, 228, 6, 41, 70, ++ 45, 240, 134, 221, 5, 176, 48, 189, 48, 181, 133, 176, 4, 70, 10, 70, ++ 208, 248, 96, 81, 1, 169, 208, 248, 36, 1, 45, 240, 59, 216, 212, 248, ++ 36, 1, 1, 169, 255, 247, 222, 252, 32, 177, 235, 104, 192, 88, 253, ++ 247, 2, 249, 244, 231, 5, 176, 48, 189, 45, 233, 240, 65, 6, 157, 30, ++ 70, 7, 156, 8, 159, 255, 247, 191, 253, 49, 70, 42, 70, 35, 70, 6, 151, ++ 189, 232, 240, 65, 253, 247, 250, 189, 25, 177, 195, 104, 200, 88, 253, ++ 247, 59, 189, 112, 71, 8, 181, 255, 247, 174, 253, 189, 232, 8, 64, ++ 253, 247, 31, 190, 112, 181, 5, 104, 189, 248, 16, 64, 46, 104, 150, ++ 248, 213, 96, 86, 185, 149, 249, 23, 85, 181, 241, 255, 63, 3, 209, ++ 144, 248, 152, 3, 40, 177, 1, 224, 1, 45, 2, 209, 157, 248, 20, 0, 144, ++ 177, 73, 107, 1, 235, 194, 0, 81, 248, 50, 32, 147, 66, 6, 211, 7, 209, ++ 128, 136, 160, 66, 148, 191, 0, 32, 1, 32, 2, 224, 1, 32, 0, 224, 0, ++ 32, 192, 178, 112, 189, 209, 248, 224, 16, 82, 1, 138, 24, 17, 105, ++ 139, 66, 27, 211, 2, 209, 145, 138, 161, 66, 25, 216, 145, 105, 139, ++ 66, 6, 211, 7, 209, 144, 139, 160, 66, 52, 191, 0, 32, 1, 32, 2, 224, ++ 1, 32, 0, 224, 0, 32, 96, 177, 4, 240, 127, 4, 227, 8, 208, 92, 4, 240, ++ 7, 4, 32, 65, 0, 240, 1, 0, 112, 189, 1, 32, 112, 189, 1, 32, 112, 189, ++ 0, 0, 45, 233, 240, 79, 28, 70, 147, 248, 96, 176, 95, 104, 211, 104, ++ 173, 245, 17, 125, 6, 70, 5, 145, 145, 70, 21, 105, 51, 177, 27, 122, ++ 11, 43, 3, 209, 59, 120, 3, 240, 1, 3, 1, 224, 251, 120, 155, 9, 227, ++ 99, 148, 248, 44, 48, 73, 70, 0, 147, 48, 70, 42, 70, 227, 107, 26, ++ 240, 77, 217, 1, 70, 160, 99, 32, 177, 42, 109, 64, 242, 55, 19, 19, ++ 64, 43, 185, 48, 70, 33, 70, 74, 70, 46, 240, 140, 218, 229, 224, 144, ++ 249, 14, 32, 144, 249, 15, 48, 211, 24, 162, 104, 154, 66, 192, 240, ++ 221, 128, 162, 105, 19, 138, 19, 240, 8, 15, 13, 208, 0, 122, 11, 40, ++ 10, 209, 150, 248, 197, 5, 56, 177, 136, 121, 3, 40, 4, 216, 35, 240, ++ 8, 3, 27, 4, 27, 12, 19, 130, 11, 122, 4, 43, 90, 208, 11, 43, 0, 240, ++ 177, 128, 2, 43, 64, 240, 195, 128, 187, 120, 151, 248, 0, 160, 151, ++ 248, 6, 128, 67, 234, 10, 42, 123, 121, 79, 234, 8, 72, 72, 234, 3, ++ 40, 59, 121, 72, 234, 3, 8, 251, 121, 180, 248, 104, 112, 72, 234, 3, ++ 104, 23, 240, 1, 7, 64, 240, 174, 128, 148, 248, 44, 48, 40, 70, 1, ++ 147, 90, 70, 67, 70, 205, 248, 0, 160, 255, 247, 57, 255, 0, 40, 0, ++ 240, 161, 128, 171, 121, 0, 43, 64, 240, 121, 130, 51, 104, 211, 248, ++ 136, 48, 211, 248, 220, 33, 1, 50, 195, 248, 220, 33, 148, 248, 44, ++ 32, 34, 177, 211, 248, 180, 34, 1, 50, 195, 248, 180, 34, 211, 248, ++ 232, 33, 1, 50, 195, 248, 232, 33, 213, 248, 4, 49, 147, 248, 52, 48, ++ 27, 177, 40, 70, 0, 33, 38, 240, 101, 217, 148, 248, 44, 112, 0, 47, ++ 0, 240, 86, 130, 51, 104, 211, 248, 136, 48, 211, 248, 192, 34, 1, 50, ++ 195, 248, 192, 34, 107, 224, 59, 120, 151, 248, 1, 160, 151, 248, 6, ++ 128, 67, 234, 10, 42, 251, 121, 79, 234, 8, 72, 72, 234, 3, 104, 59, ++ 121, 72, 234, 3, 8, 123, 121, 72, 234, 3, 40, 43, 124, 27, 185, 181, ++ 248, 90, 48, 219, 7, 88, 212, 180, 248, 104, 112, 23, 240, 1, 7, 83, ++ 209, 148, 248, 44, 48, 40, 70, 1, 147, 90, 70, 67, 70, 205, 248, 0, ++ 160, 255, 247, 223, 254, 0, 40, 71, 208, 171, 121, 0, 43, 64, 240, 32, ++ 130, 51, 104, 211, 248, 136, 48, 211, 248, 220, 33, 1, 50, 195, 248, ++ 220, 33, 148, 248, 44, 32, 34, 177, 211, 248, 180, 34, 1, 50, 195, 248, ++ 180, 34, 211, 248, 240, 33, 1, 50, 195, 248, 240, 33, 213, 248, 4, 49, ++ 147, 248, 52, 48, 27, 177, 40, 70, 0, 33, 38, 240, 12, 217, 148, 248, ++ 44, 112, 0, 47, 0, 240, 253, 129, 51, 104, 211, 248, 136, 48, 211, 248, ++ 200, 34, 1, 50, 195, 248, 200, 34, 18, 224, 2, 55, 200, 49, 16, 34, ++ 56, 70, 198, 243, 244, 241, 0, 40, 12, 218, 140, 72, 57, 70, 16, 34, ++ 198, 243, 91, 243, 161, 107, 138, 72, 200, 49, 16, 34, 198, 243, 85, ++ 243, 0, 39, 222, 225, 79, 240, 0, 8, 194, 70, 150, 248, 148, 50, 147, ++ 185, 43, 109, 31, 7, 15, 212, 160, 107, 3, 122, 2, 43, 2, 209, 203, ++ 247, 234, 251, 64, 185, 99, 105, 155, 105, 152, 0, 4, 212, 163, 105, ++ 27, 138, 25, 7, 0, 241, 250, 128, 99, 105, 155, 105, 90, 6, 224, 212, ++ 163, 105, 26, 138, 66, 240, 8, 2, 26, 130, 161, 107, 11, 122, 1, 59, ++ 10, 43, 0, 242, 206, 128, 223, 232, 19, 240, 53, 0, 11, 0, 53, 0, 108, ++ 0, 204, 0, 204, 0, 204, 0, 204, 0, 204, 0, 204, 0, 174, 0, 8, 70, 203, ++ 247, 193, 251, 8, 177, 43, 124, 75, 177, 163, 107, 211, 248, 136, 32, ++ 144, 69, 4, 216, 15, 208, 147, 248, 140, 32, 90, 69, 11, 208, 161, 107, ++ 34, 104, 4, 241, 64, 7, 56, 70, 20, 49, 10, 50, 67, 70, 211, 243, 168, ++ 247, 231, 101, 1, 224, 100, 51, 227, 101, 161, 107, 4, 241, 74, 7, 56, ++ 70, 20, 49, 226, 109, 83, 70, 212, 243, 101, 240, 56, 70, 16, 33, 16, ++ 224, 97, 104, 3, 34, 132, 168, 196, 247, 89, 251, 163, 107, 132, 168, ++ 3, 241, 20, 1, 26, 105, 3, 48, 196, 247, 81, 251, 163, 107, 132, 168, ++ 25, 105, 3, 49, 7, 170, 205, 243, 110, 241, 163, 107, 96, 104, 147, ++ 249, 14, 48, 161, 104, 192, 24, 201, 26, 7, 170, 205, 243, 134, 241, ++ 163, 107, 96, 104, 147, 249, 14, 48, 161, 104, 192, 24, 201, 26, 79, ++ 240, 255, 50, 198, 243, 57, 245, 68, 75, 162, 105, 152, 66, 19, 138, ++ 4, 209, 35, 240, 16, 3, 27, 4, 27, 12, 1, 224, 67, 240, 16, 3, 19, 130, ++ 124, 224, 99, 104, 223, 120, 23, 240, 32, 7, 31, 208, 10, 105, 72, 168, ++ 20, 49, 210, 0, 205, 243, 228, 245, 0, 35, 33, 104, 98, 105, 72, 70, ++ 45, 240, 26, 221, 0, 39, 163, 107, 1, 144, 0, 151, 25, 105, 72, 168, ++ 35, 104, 226, 104, 194, 243, 252, 242, 131, 28, 5, 209, 163, 105, 26, ++ 138, 66, 240, 16, 2, 26, 130, 89, 224, 1, 48, 87, 209, 51, 104, 211, ++ 248, 136, 48, 211, 248, 220, 33, 1, 50, 195, 248, 220, 33, 211, 248, ++ 244, 33, 1, 50, 195, 248, 244, 33, 148, 248, 44, 32, 0, 42, 0, 240, ++ 15, 129, 211, 248, 180, 34, 1, 50, 195, 248, 180, 34, 211, 248, 204, ++ 34, 1, 50, 195, 248, 204, 34, 6, 225, 1, 241, 20, 0, 226, 104, 36, 49, ++ 35, 104, 209, 243, 50, 245, 0, 40, 127, 244, 28, 175, 162, 107, 210, ++ 248, 216, 48, 1, 51, 194, 248, 216, 48, 51, 240, 124, 67, 39, 209, 242, ++ 34, 1, 146, 214, 248, 152, 1, 41, 70, 9, 241, 20, 2, 0, 147, 57, 240, ++ 238, 216, 28, 224, 175, 121, 0, 47, 127, 244, 4, 175, 51, 104, 211, ++ 248, 136, 48, 211, 248, 220, 33, 1, 50, 195, 248, 220, 33, 148, 248, ++ 44, 32, 0, 42, 0, 240, 213, 128, 211, 248, 180, 34, 1, 50, 195, 248, ++ 180, 34, 209, 224, 62, 200, 136, 0, 68, 200, 136, 0, 227, 32, 187, 222, ++ 163, 107, 97, 104, 147, 249, 14, 32, 138, 24, 98, 96, 147, 249, 14, ++ 16, 147, 249, 15, 32, 138, 24, 161, 104, 138, 26, 162, 96, 147, 249, ++ 14, 16, 147, 249, 15, 32, 138, 24, 33, 105, 138, 26, 34, 97, 162, 105, ++ 18, 138, 2, 240, 24, 2, 24, 42, 100, 209, 171, 121, 0, 43, 127, 244, ++ 203, 174, 149, 249, 68, 32, 0, 147, 1, 147, 2, 147, 48, 70, 49, 35, ++ 213, 248, 244, 16, 45, 240, 7, 219, 51, 104, 211, 248, 136, 48, 211, ++ 248, 220, 33, 1, 50, 195, 248, 220, 33, 211, 248, 236, 33, 1, 50, 195, ++ 248, 236, 33, 211, 248, 244, 33, 1, 50, 195, 248, 244, 33, 148, 248, ++ 44, 32, 114, 177, 211, 248, 180, 34, 1, 50, 195, 248, 180, 34, 211, ++ 248, 196, 34, 1, 50, 195, 248, 196, 34, 211, 248, 204, 34, 1, 50, 195, ++ 248, 204, 34, 162, 107, 18, 122, 2, 42, 5, 208, 3, 42, 18, 208, 1, 42, ++ 127, 244, 147, 174, 14, 224, 211, 248, 8, 34, 1, 50, 195, 248, 8, 34, ++ 148, 248, 44, 112, 0, 47, 105, 208, 211, 248, 224, 34, 1, 50, 195, 248, ++ 224, 34, 130, 230, 211, 248, 0, 34, 1, 50, 195, 248, 0, 34, 211, 248, ++ 252, 33, 1, 50, 195, 248, 252, 33, 148, 248, 44, 112, 0, 47, 85, 208, ++ 211, 248, 216, 34, 1, 50, 195, 248, 216, 34, 211, 248, 212, 34, 1, 50, ++ 195, 248, 212, 34, 105, 230, 97, 105, 138, 137, 226, 96, 148, 248, 45, ++ 32, 154, 185, 147, 249, 15, 32, 5, 152, 146, 178, 202, 243, 137, 243, ++ 99, 105, 218, 137, 151, 4, 2, 213, 179, 248, 80, 48, 139, 185, 163, ++ 107, 226, 104, 147, 249, 15, 48, 211, 26, 227, 96, 10, 224, 5, 152, ++ 198, 243, 214, 244, 163, 107, 1, 70, 147, 249, 15, 32, 5, 152, 146, ++ 178, 202, 243, 112, 243, 51, 104, 196, 248, 100, 128, 211, 248, 136, ++ 48, 164, 248, 98, 160, 211, 248, 4, 34, 1, 50, 195, 248, 4, 34, 148, ++ 248, 44, 32, 34, 177, 211, 248, 220, 34, 1, 50, 195, 248, 220, 34, 163, ++ 107, 27, 122, 4, 43, 1, 208, 2, 43, 10, 209, 180, 248, 104, 48, 216, ++ 7, 6, 212, 48, 70, 33, 70, 46, 240, 20, 216, 1, 224, 23, 70, 0, 224, ++ 1, 39, 56, 70, 13, 245, 17, 125, 189, 232, 240, 143, 0, 191, 75, 28, ++ 1, 209, 3, 106, 5, 224, 203, 178, 1, 43, 5, 216, 10, 49, 80, 248, 33, ++ 48, 147, 248, 76, 0, 112, 71, 111, 240, 28, 0, 112, 71, 208, 248, 116, ++ 52, 88, 123, 112, 71, 176, 248, 197, 2, 0, 240, 12, 0, 128, 8, 112, ++ 71, 111, 240, 22, 0, 112, 71, 3, 106, 147, 249, 77, 0, 112, 71, 0, 0, ++ 112, 181, 208, 248, 116, 52, 90, 120, 6, 42, 1, 209, 2, 34, 0, 224, ++ 1, 34, 0, 33, 26, 117, 11, 70, 20, 76, 208, 248, 116, 36, 13, 93, 2, ++ 235, 67, 2, 85, 117, 208, 248, 116, 36, 146, 248, 124, 96, 142, 177, ++ 176, 248, 72, 84, 5, 244, 96, 85, 181, 245, 128, 95, 79, 234, 67, 5, ++ 2, 209, 82, 25, 2, 36, 3, 224, 2, 46, 3, 209, 82, 25, 4, 36, 148, 117, ++ 6, 224, 93, 0, 86, 25, 18, 125, 237, 24, 173, 24, 98, 93, 178, 117, ++ 1, 51, 3, 49, 6, 43, 214, 209, 112, 189, 48, 89, 4, 0, 130, 120, 67, ++ 120, 145, 66, 54, 216, 1, 41, 37, 209, 144, 248, 124, 32, 1, 42, 10, ++ 209, 3, 240, 2, 0, 192, 178, 0, 40, 12, 191, 4, 32, 2, 32, 24, 66, 8, ++ 191, 1, 32, 112, 71, 2, 42, 10, 209, 3, 240, 4, 0, 192, 178, 0, 40, ++ 12, 191, 1, 32, 4, 32, 24, 66, 8, 191, 2, 32, 112, 71, 3, 240, 1, 0, ++ 0, 40, 12, 191, 2, 32, 1, 32, 24, 66, 8, 191, 4, 32, 112, 71, 2, 41, ++ 14, 209, 3, 240, 5, 2, 5, 42, 12, 191, 5, 34, 3, 34, 2, 234, 3, 0, 144, ++ 66, 12, 191, 16, 70, 6, 32, 112, 71, 0, 32, 112, 71, 7, 32, 112, 71, ++ 16, 181, 96, 177, 3, 120, 1, 34, 6, 224, 16, 248, 1, 79, 1, 50, 156, ++ 66, 40, 191, 35, 70, 219, 178, 138, 66, 246, 211, 0, 224, 3, 70, 24, ++ 70, 16, 189, 65, 24, 129, 248, 82, 32, 144, 248, 82, 32, 3, 120, 19, ++ 64, 144, 248, 83, 32, 19, 64, 144, 248, 84, 32, 19, 64, 144, 248, 85, ++ 32, 19, 64, 144, 248, 86, 32, 3, 234, 2, 0, 112, 71, 208, 248, 116, ++ 52, 17, 244, 64, 127, 88, 137, 3, 209, 147, 249, 8, 32, 3, 42, 1, 209, ++ 88, 120, 128, 1, 0, 244, 112, 112, 112, 71, 0, 0, 45, 233, 240, 71, ++ 208, 248, 116, 52, 154, 176, 220, 106, 176, 248, 72, 100, 157, 120, ++ 138, 70, 7, 70, 1, 169, 0, 34, 154, 72, 16, 92, 3, 50, 18, 42, 65, 248, ++ 4, 15, 248, 209, 0, 44, 0, 240, 217, 129, 1, 45, 64, 242, 214, 129, ++ 6, 244, 96, 86, 166, 245, 192, 81, 147, 248, 138, 32, 78, 66, 70, 235, ++ 1, 6, 34, 177, 155, 121, 1, 43, 1, 217, 1, 35, 114, 224, 32, 70, 174, ++ 177, 3, 33, 1, 34, 23, 171, 249, 247, 77, 254, 3, 33, 2, 34, 32, 70, ++ 24, 171, 249, 247, 71, 254, 3, 45, 5, 209, 32, 70, 41, 70, 42, 70, 25, ++ 171, 249, 247, 63, 254, 79, 240, 0, 8, 15, 224, 1, 34, 49, 70, 23, 171, ++ 249, 247, 55, 254, 2, 34, 32, 70, 49, 70, 24, 171, 249, 247, 49, 254, ++ 3, 45, 239, 209, 32, 70, 49, 70, 232, 231, 23, 171, 24, 249, 3, 32, ++ 128, 50, 5, 209, 215, 248, 116, 36, 146, 248, 120, 32, 8, 248, 3, 32, ++ 24, 171, 24, 249, 3, 32, 128, 50, 5, 209, 215, 248, 116, 36, 146, 248, ++ 120, 32, 8, 248, 3, 32, 3, 45, 10, 209, 25, 171, 24, 249, 3, 32, 128, ++ 50, 5, 209, 215, 248, 116, 36, 146, 248, 120, 32, 8, 248, 3, 32, 8, ++ 241, 1, 8, 184, 241, 4, 15, 215, 209, 65, 70, 23, 168, 255, 247, 76, ++ 255, 65, 70, 192, 241, 0, 9, 24, 168, 255, 247, 70, 255, 192, 241, 6, ++ 3, 75, 69, 128, 70, 1, 219, 2, 35, 2, 147, 2, 45, 16, 208, 4, 33, 25, ++ 168, 255, 247, 57, 255, 192, 241, 9, 3, 75, 69, 8, 219, 111, 240, 2, ++ 3, 200, 235, 3, 3, 64, 66, 131, 66, 1, 220, 3, 35, 2, 147, 17, 171, ++ 0, 147, 32, 70, 206, 177, 1, 33, 0, 34, 11, 70, 249, 247, 240, 253, ++ 2, 34, 19, 171, 0, 147, 1, 33, 32, 70, 19, 70, 249, 247, 232, 253, 3, ++ 45, 7, 209, 21, 171, 0, 147, 32, 70, 1, 33, 2, 34, 43, 70, 249, 247, ++ 222, 253, 79, 240, 0, 8, 19, 224, 1, 35, 49, 70, 50, 70, 249, 247, 214, ++ 253, 2, 34, 19, 171, 0, 147, 32, 70, 49, 70, 19, 70, 249, 247, 206, ++ 253, 3, 45, 237, 209, 21, 171, 0, 147, 32, 70, 49, 70, 228, 231, 17, ++ 171, 24, 249, 3, 32, 128, 50, 5, 209, 215, 248, 116, 36, 146, 248, 120, ++ 32, 8, 248, 3, 32, 19, 171, 24, 249, 3, 32, 128, 50, 5, 209, 215, 248, ++ 116, 36, 146, 248, 120, 32, 8, 248, 3, 32, 3, 45, 10, 209, 21, 171, ++ 24, 249, 3, 32, 128, 50, 5, 209, 215, 248, 116, 36, 146, 248, 120, 32, ++ 8, 248, 3, 32, 8, 241, 1, 8, 184, 241, 8, 15, 215, 209, 65, 70, 17, ++ 168, 255, 247, 206, 254, 65, 70, 192, 241, 0, 9, 19, 168, 255, 247, ++ 200, 254, 192, 241, 6, 3, 75, 69, 128, 70, 1, 219, 2, 35, 3, 147, 2, ++ 45, 16, 208, 8, 33, 21, 168, 255, 247, 187, 254, 192, 241, 9, 3, 75, ++ 69, 8, 219, 111, 240, 2, 3, 200, 235, 3, 3, 64, 66, 131, 66, 1, 220, ++ 3, 35, 3, 147, 79, 240, 1, 8, 8, 171, 205, 248, 0, 128, 1, 147, 32, ++ 70, 6, 179, 0, 35, 65, 70, 66, 70, 249, 247, 165, 253, 79, 240, 2, 9, ++ 11, 171, 1, 147, 32, 70, 65, 70, 66, 70, 75, 70, 205, 248, 0, 144, 249, ++ 247, 153, 253, 3, 45, 8, 209, 14, 171, 0, 149, 1, 147, 32, 70, 65, 70, ++ 66, 70, 75, 70, 249, 247, 142, 253, 79, 240, 0, 8, 26, 224, 48, 89, ++ 4, 0, 49, 70, 66, 70, 51, 70, 249, 247, 132, 253, 79, 240, 2, 9, 11, ++ 171, 1, 147, 32, 70, 49, 70, 66, 70, 75, 70, 205, 248, 0, 144, 249, ++ 247, 120, 253, 3, 45, 231, 209, 14, 171, 0, 149, 1, 147, 32, 70, 49, ++ 70, 221, 231, 8, 171, 24, 249, 3, 32, 128, 50, 5, 209, 215, 248, 116, ++ 36, 146, 248, 120, 32, 8, 248, 3, 32, 11, 171, 24, 249, 3, 32, 128, ++ 50, 5, 209, 215, 248, 116, 36, 146, 248, 120, 32, 8, 248, 3, 32, 3, ++ 45, 10, 209, 14, 171, 24, 249, 3, 32, 128, 50, 5, 209, 215, 248, 116, ++ 36, 146, 248, 120, 32, 8, 248, 3, 32, 8, 241, 1, 8, 184, 241, 8, 15, ++ 215, 209, 65, 70, 8, 168, 255, 247, 64, 254, 65, 70, 192, 241, 0, 9, ++ 11, 168, 255, 247, 58, 254, 192, 241, 6, 3, 75, 69, 128, 70, 1, 219, ++ 2, 35, 4, 147, 2, 45, 87, 208, 8, 33, 14, 168, 255, 247, 45, 254, 192, ++ 241, 9, 3, 75, 69, 8, 219, 111, 240, 2, 3, 200, 235, 3, 3, 64, 66, 131, ++ 66, 1, 220, 3, 35, 4, 147, 3, 34, 14, 171, 141, 232, 12, 0, 32, 70, ++ 102, 177, 1, 33, 2, 34, 0, 35, 249, 247, 25, 253, 11, 171, 2, 34, 1, ++ 147, 0, 146, 32, 70, 1, 33, 0, 35, 11, 224, 49, 70, 2, 34, 51, 70, 249, ++ 247, 12, 253, 11, 171, 2, 34, 1, 147, 0, 146, 32, 70, 49, 70, 51, 70, ++ 249, 247, 3, 253, 0, 36, 11, 171, 226, 86, 128, 50, 4, 209, 215, 248, ++ 116, 36, 146, 248, 120, 32, 226, 84, 14, 171, 226, 86, 128, 50, 4, 209, ++ 215, 248, 116, 36, 146, 248, 120, 32, 226, 84, 1, 52, 8, 44, 234, 209, ++ 33, 70, 11, 168, 255, 247, 229, 253, 33, 70, 5, 70, 14, 168, 255, 247, ++ 224, 253, 109, 66, 192, 241, 3, 0, 168, 66, 1, 219, 3, 35, 5, 147, 85, ++ 70, 0, 36, 2, 171, 225, 88, 215, 248, 116, 4, 255, 247, 146, 253, 4, ++ 52, 24, 44, 5, 248, 1, 11, 244, 209, 26, 176, 189, 232, 240, 135, 208, ++ 248, 116, 52, 26, 122, 10, 185, 64, 34, 5, 224, 1, 42, 1, 209, 128, ++ 34, 1, 224, 90, 120, 146, 1, 90, 129, 0, 105, 89, 137, 230, 247, 98, ++ 190, 56, 181, 75, 28, 1, 43, 4, 70, 13, 70, 7, 217, 1, 41, 38, 209, ++ 208, 248, 116, 52, 155, 120, 1, 43, 1, 209, 34, 224, 81, 177, 212, 248, ++ 116, 52, 155, 120, 1, 43, 5, 208, 35, 106, 24, 105, 240, 247, 23, 250, ++ 128, 7, 6, 212, 180, 248, 197, 50, 35, 240, 128, 3, 27, 4, 27, 12, 3, ++ 224, 180, 248, 197, 50, 67, 240, 128, 3, 164, 248, 197, 50, 163, 106, ++ 1, 32, 131, 248, 77, 80, 227, 106, 131, 248, 77, 80, 56, 189, 0, 32, ++ 56, 189, 0, 32, 56, 189, 16, 181, 176, 248, 197, 50, 4, 70, 35, 244, ++ 64, 115, 67, 234, 1, 35, 160, 248, 197, 50, 3, 104, 27, 126, 59, 177, ++ 241, 243, 243, 247, 32, 70, 1, 33, 189, 232, 16, 64, 242, 243, 169, ++ 176, 16, 189, 3, 42, 112, 181, 5, 70, 12, 70, 14, 216, 2, 42, 12, 208, ++ 214, 178, 49, 70, 236, 243, 87, 240, 76, 177, 35, 122, 75, 177, 40, ++ 70, 33, 70, 50, 70, 239, 243, 123, 240, 1, 224, 0, 32, 112, 189, 1, ++ 32, 112, 189, 1, 32, 112, 189, 115, 181, 0, 35, 1, 147, 208, 248, 116, ++ 52, 5, 70, 222, 106, 20, 35, 75, 128, 1, 35, 11, 128, 3, 106, 12, 70, ++ 24, 105, 239, 247, 146, 252, 43, 104, 32, 129, 147, 248, 63, 48, 19, ++ 177, 181, 248, 70, 52, 99, 129, 20, 35, 99, 96, 213, 248, 116, 52, 216, ++ 106, 56, 177, 48, 70, 4, 241, 16, 1, 226, 104, 1, 171, 249, 247, 225, ++ 253, 1, 152, 124, 189, 115, 181, 2, 174, 6, 248, 1, 45, 4, 70, 13, 70, ++ 48, 70, 1, 33, 197, 243, 75, 244, 212, 248, 116, 52, 155, 120, 152, ++ 66, 2, 217, 0, 35, 141, 248, 7, 48, 1, 33, 48, 70, 197, 243, 63, 244, ++ 212, 248, 116, 52, 154, 120, 144, 66, 9, 209, 157, 248, 7, 16, 90, 120, ++ 49, 234, 2, 0, 1, 209, 10, 66, 1, 209, 141, 248, 7, 32, 1, 45, 157, ++ 248, 7, 32, 8, 216, 58, 185, 90, 120, 66, 177, 3, 235, 69, 3, 154, 117, ++ 141, 248, 7, 32, 2, 224, 3, 235, 69, 3, 154, 117, 35, 106, 27, 104, ++ 1, 43, 2, 209, 1, 45, 41, 209, 2, 224, 2, 43, 38, 209, 45, 187, 157, ++ 248, 7, 16, 212, 248, 116, 52, 137, 1, 89, 129, 32, 105, 230, 247, 144, ++ 253, 99, 126, 211, 177, 35, 106, 32, 70, 26, 104, 212, 248, 160, 20, ++ 0, 35, 242, 243, 91, 240, 136, 177, 32, 70, 241, 243, 209, 242, 32, ++ 70, 212, 248, 160, 20, 230, 243, 56, 241, 32, 70, 212, 248, 160, 20, ++ 180, 248, 72, 36, 230, 243, 247, 240, 32, 70, 235, 243, 120, 242, 212, ++ 248, 160, 1, 8, 177, 55, 240, 133, 220, 124, 189, 16, 181, 0, 42, 12, ++ 191, 164, 36, 180, 36, 100, 41, 14, 216, 41, 177, 193, 241, 100, 2, ++ 18, 1, 146, 251, 241, 242, 0, 224, 10, 70, 67, 177, 33, 70, 146, 178, ++ 242, 243, 118, 241, 0, 32, 16, 189, 111, 240, 28, 0, 16, 189, 24, 70, ++ 16, 189, 112, 181, 208, 248, 116, 52, 5, 70, 147, 248, 72, 32, 145, ++ 7, 5, 213, 147, 248, 122, 64, 100, 44, 40, 191, 100, 36, 0, 224, 100, ++ 36, 210, 7, 4, 213, 147, 248, 73, 48, 156, 66, 40, 191, 28, 70, 43, ++ 104, 27, 126, 107, 177, 33, 70, 0, 34, 1, 35, 40, 70, 255, 247, 198, ++ 255, 1, 34, 40, 70, 33, 70, 19, 70, 189, 232, 112, 64, 255, 247, 190, ++ 191, 112, 189, 56, 181, 208, 248, 116, 52, 179, 248, 144, 64, 44, 179, ++ 34, 177, 3, 241, 146, 4, 179, 248, 74, 48, 3, 224, 3, 241, 158, 4, 179, ++ 248, 76, 48, 37, 136, 169, 66, 1, 219, 24, 41, 1, 220, 217, 178, 13, ++ 224, 165, 136, 169, 66, 1, 218, 97, 136, 4, 224, 37, 137, 169, 66, 180, ++ 191, 225, 136, 97, 137, 19, 41, 140, 191, 201, 178, 20, 33, 153, 66, ++ 136, 191, 217, 178, 3, 104, 27, 126, 255, 247, 145, 255, 0, 32, 56, ++ 189, 208, 248, 116, 52, 19, 181, 179, 248, 144, 32, 4, 70, 18, 179, ++ 3, 106, 13, 241, 6, 1, 24, 105, 240, 247, 40, 251, 40, 179, 212, 248, ++ 116, 52, 32, 70, 179, 248, 170, 32, 209, 0, 137, 26, 189, 249, 6, 32, ++ 137, 24, 72, 191, 7, 49, 201, 16, 163, 248, 170, 16, 1, 34, 9, 178, ++ 255, 247, 177, 255, 212, 248, 116, 52, 32, 70, 179, 249, 170, 16, 0, ++ 34, 255, 247, 169, 255, 9, 224, 100, 33, 1, 35, 255, 247, 97, 255, 1, ++ 34, 32, 70, 100, 33, 19, 70, 255, 247, 91, 255, 28, 189, 16, 181, 0, ++ 35, 11, 128, 3, 104, 134, 176, 27, 126, 12, 70, 27, 185, 79, 240, 255, ++ 51, 11, 128, 21, 224, 2, 244, 96, 81, 208, 248, 116, 52, 1, 34, 161, ++ 245, 192, 94, 3, 168, 222, 241, 0, 1, 0, 146, 1, 144, 65, 235, 14, 1, ++ 216, 106, 0, 35, 249, 247, 231, 250, 32, 70, 0, 33, 198, 243, 132, 242, ++ 6, 176, 16, 189, 1, 41, 8, 181, 3, 216, 255, 247, 111, 254, 1, 32, 8, ++ 189, 0, 32, 8, 189, 176, 248, 197, 2, 0, 244, 64, 112, 0, 10, 112, 71, ++ 111, 240, 22, 0, 112, 71, 17, 244, 64, 79, 176, 248, 72, 52, 208, 248, ++ 116, 36, 2, 209, 146, 248, 87, 16, 16, 224, 219, 178, 51, 43, 2, 216, ++ 146, 248, 88, 16, 10, 224, 99, 43, 2, 216, 146, 248, 89, 16, 5, 224, ++ 148, 43, 148, 191, 146, 248, 90, 16, 146, 248, 91, 16, 73, 178, 255, ++ 247, 223, 191, 247, 181, 208, 248, 116, 100, 5, 70, 15, 70, 104, 70, ++ 0, 33, 4, 34, 197, 243, 126, 240, 0, 36, 59, 93, 90, 178, 0, 42, 28, ++ 220, 13, 248, 4, 48, 1, 52, 4, 44, 246, 209, 92, 54, 49, 70, 34, 70, ++ 1, 168, 195, 247, 238, 252, 57, 70, 34, 70, 48, 70, 195, 247, 233, 252, ++ 43, 106, 105, 70, 24, 105, 240, 247, 120, 251, 5, 70, 56, 177, 48, 70, ++ 1, 169, 34, 70, 195, 247, 221, 252, 1, 224, 111, 240, 28, 5, 40, 70, ++ 254, 189, 115, 181, 208, 248, 116, 52, 201, 178, 90, 121, 4, 70, 138, ++ 66, 141, 248, 7, 16, 106, 208, 219, 120, 49, 234, 3, 5, 99, 209, 25, ++ 66, 97, 208, 1, 33, 13, 241, 7, 0, 197, 243, 171, 242, 212, 248, 116, ++ 52, 157, 248, 7, 32, 153, 121, 94, 121, 90, 113, 192, 178, 212, 248, ++ 116, 52, 136, 66, 152, 113, 68, 208, 1, 40, 2, 208, 1, 41, 64, 209, ++ 3, 37, 212, 248, 108, 50, 131, 248, 64, 83, 35, 104, 147, 248, 47, 32, ++ 138, 177, 212, 248, 116, 52, 34, 106, 89, 120, 16, 105, 90, 121, 240, ++ 247, 61, 250, 32, 70, 41, 70, 235, 243, 81, 246, 35, 104, 147, 248, ++ 63, 0, 0, 40, 53, 208, 16, 224, 147, 248, 63, 96, 166, 177, 3, 45, 11, ++ 209, 212, 248, 116, 52, 34, 106, 89, 120, 16, 105, 90, 121, 240, 247, ++ 38, 250, 32, 70, 41, 70, 235, 243, 58, 246, 32, 70, 212, 248, 108, 18, ++ 42, 70, 236, 243, 142, 244, 27, 224, 212, 248, 116, 52, 34, 106, 89, ++ 120, 16, 105, 90, 121, 240, 247, 19, 250, 32, 70, 41, 70, 235, 243, ++ 39, 246, 48, 70, 14, 224, 150, 66, 11, 208, 212, 248, 116, 52, 34, 106, ++ 89, 120, 16, 105, 90, 121, 240, 247, 3, 250, 2, 224, 111, 240, 28, 0, ++ 0, 224, 0, 32, 124, 189, 115, 181, 208, 248, 116, 52, 4, 70, 29, 123, ++ 3, 106, 14, 70, 24, 105, 239, 247, 143, 255, 130, 7, 24, 213, 212, 248, ++ 116, 4, 67, 123, 163, 177, 194, 137, 79, 246, 255, 115, 154, 66, 15, ++ 208, 1, 124, 81, 185, 131, 120, 1, 43, 8, 208, 14, 48, 197, 243, 102, ++ 246, 208, 241, 1, 1, 56, 191, 0, 33, 0, 224, 0, 33, 201, 178, 13, 224, ++ 35, 106, 179, 66, 41, 209, 212, 248, 116, 52, 25, 124, 41, 185, 155, ++ 120, 1, 43, 3, 208, 150, 248, 76, 16, 0, 224, 0, 33, 141, 66, 5, 208, ++ 212, 248, 116, 52, 25, 115, 32, 105, 5, 240, 134, 223, 212, 248, 116, ++ 52, 147, 248, 60, 48, 75, 185, 35, 104, 211, 248, 132, 48, 3, 244, 128, ++ 67, 0, 43, 12, 191, 64, 35, 0, 35, 0, 224, 64, 35, 0, 34, 0, 146, 32, ++ 70, 3, 33, 64, 34, 236, 243, 25, 244, 0, 32, 124, 189, 56, 181, 208, ++ 248, 116, 52, 4, 70, 91, 123, 13, 70, 139, 66, 21, 208, 3, 106, 24, ++ 105, 239, 247, 57, 255, 129, 7, 8, 213, 61, 177, 212, 248, 116, 20, ++ 32, 70, 14, 49, 180, 248, 72, 36, 255, 247, 154, 254, 212, 248, 116, ++ 52, 32, 70, 93, 115, 33, 106, 255, 247, 142, 255, 0, 32, 56, 189, 8, ++ 181, 83, 28, 1, 209, 3, 106, 5, 224, 211, 178, 1, 43, 18, 216, 10, 50, ++ 80, 248, 34, 48, 1, 41, 5, 209, 208, 248, 116, 36, 146, 120, 1, 42, ++ 1, 209, 7, 224, 8, 216, 131, 248, 76, 16, 25, 70, 255, 247, 115, 255, ++ 1, 32, 8, 189, 0, 32, 8, 189, 0, 32, 8, 189, 112, 181, 4, 70, 208, 248, ++ 116, 4, 1, 33, 80, 48, 197, 243, 174, 241, 212, 248, 116, 52, 6, 70, ++ 147, 248, 80, 32, 93, 120, 90, 112, 212, 248, 116, 52, 89, 120, 0, 41, ++ 57, 208, 173, 26, 147, 248, 34, 32, 24, 191, 1, 37, 130, 177, 17, 64, ++ 145, 66, 19, 208, 131, 248, 133, 32, 212, 248, 116, 52, 0, 34, 131, ++ 248, 34, 32, 212, 248, 116, 52, 91, 111, 67, 177, 32, 70, 152, 71, 5, ++ 224, 147, 248, 133, 32, 18, 177, 13, 177, 131, 248, 34, 32, 212, 248, ++ 116, 52, 147, 248, 33, 32, 138, 177, 89, 120, 17, 64, 145, 66, 19, 208, ++ 131, 248, 132, 32, 212, 248, 116, 52, 0, 34, 131, 248, 33, 32, 212, ++ 248, 116, 52, 91, 111, 67, 177, 32, 70, 152, 71, 5, 224, 147, 248, 132, ++ 32, 18, 177, 13, 177, 131, 248, 33, 32, 212, 248, 116, 52, 0, 37, 131, ++ 248, 80, 80, 212, 248, 116, 52, 32, 70, 158, 112, 35, 106, 147, 249, ++ 77, 16, 255, 247, 123, 252, 161, 106, 32, 70, 255, 247, 13, 255, 32, ++ 70, 225, 106, 255, 247, 9, 255, 212, 248, 116, 52, 154, 120, 1, 42, ++ 7, 209, 89, 120, 1, 41, 1, 209, 29, 114, 4, 224, 2, 41, 2, 209, 0, 224, ++ 3, 34, 26, 114, 32, 70, 255, 247, 80, 252, 32, 70, 255, 247, 159, 249, ++ 32, 70, 180, 248, 72, 20, 255, 247, 42, 254, 32, 70, 254, 247, 189, ++ 253, 212, 248, 160, 1, 8, 177, 55, 240, 202, 217, 212, 248, 116, 52, ++ 34, 106, 89, 120, 16, 105, 90, 121, 189, 232, 112, 64, 240, 247, 218, ++ 184, 45, 233, 243, 65, 4, 70, 208, 248, 116, 4, 30, 70, 21, 70, 195, ++ 24, 202, 178, 49, 70, 147, 248, 82, 112, 255, 247, 3, 250, 212, 248, ++ 116, 52, 141, 248, 7, 0, 90, 120, 130, 66, 117, 208, 26, 120, 48, 234, ++ 2, 1, 1, 209, 16, 66, 5, 209, 158, 25, 134, 248, 82, 112, 111, 240, ++ 28, 0, 106, 224, 88, 28, 1, 33, 197, 243, 1, 241, 1, 33, 128, 70, 13, ++ 241, 7, 0, 197, 243, 251, 240, 1, 40, 52, 209, 184, 241, 1, 15, 49, ++ 217, 163, 106, 88, 108, 249, 247, 129, 253, 1, 40, 5, 216, 163, 106, ++ 152, 108, 249, 247, 123, 253, 1, 40, 25, 217, 61, 185, 212, 248, 116, ++ 52, 79, 240, 255, 48, 158, 25, 134, 248, 82, 112, 70, 224, 163, 106, ++ 88, 108, 249, 247, 108, 253, 1, 40, 163, 106, 1, 217, 0, 34, 90, 100, ++ 152, 108, 249, 247, 100, 253, 1, 40, 2, 217, 163, 106, 0, 34, 154, 100, ++ 32, 70, 255, 247, 42, 249, 1, 40, 6, 209, 162, 106, 0, 35, 130, 248, ++ 77, 48, 226, 106, 130, 248, 77, 48, 212, 248, 116, 52, 157, 248, 7, ++ 32, 131, 248, 80, 32, 212, 248, 116, 52, 91, 120, 26, 64, 154, 66, 19, ++ 208, 227, 105, 179, 249, 28, 16, 179, 249, 30, 32, 138, 24, 179, 249, ++ 32, 16, 179, 249, 34, 48, 82, 24, 218, 66, 6, 208, 148, 248, 116, 50, ++ 67, 240, 32, 3, 132, 248, 116, 50, 8, 224, 148, 248, 116, 50, 32, 70, ++ 35, 240, 32, 3, 132, 248, 116, 50, 255, 247, 229, 254, 0, 32, 189, 232, ++ 252, 129, 208, 248, 116, 36, 11, 70, 17, 120, 0, 34, 255, 247, 107, ++ 191, 112, 181, 208, 248, 116, 52, 12, 70, 90, 120, 30, 120, 36, 9, 178, ++ 66, 5, 70, 1, 240, 15, 1, 13, 209, 219, 120, 145, 66, 44, 191, 0, 34, ++ 1, 34, 156, 66, 0, 209, 106, 185, 156, 66, 15, 210, 114, 177, 40, 70, ++ 33, 70, 7, 224, 10, 210, 177, 66, 4, 208, 219, 120, 163, 66, 5, 209, ++ 145, 66, 3, 208, 1, 34, 19, 70, 255, 247, 69, 255, 213, 248, 116, 52, ++ 90, 121, 219, 120, 154, 66, 2, 209, 148, 66, 10, 210, 2, 224, 8, 210, ++ 156, 66, 6, 209, 40, 70, 33, 70, 1, 34, 189, 232, 112, 64, 255, 247, ++ 152, 189, 112, 189, 0, 0, 138, 2, 16, 181, 4, 70, 3, 213, 208, 248, ++ 116, 52, 152, 120, 20, 224, 17, 240, 64, 112, 14, 209, 1, 240, 127, ++ 3, 2, 43, 17, 208, 4, 43, 15, 208, 11, 43, 13, 208, 22, 43, 11, 208, ++ 11, 74, 203, 178, 211, 86, 0, 43, 5, 219, 8, 70, 249, 247, 179, 252, ++ 1, 48, 192, 178, 0, 224, 1, 32, 212, 248, 116, 52, 5, 40, 40, 191, 5, ++ 32, 192, 178, 3, 235, 64, 0, 128, 125, 16, 189, 0, 191, 224, 248, 135, ++ 0, 7, 181, 255, 247, 207, 255, 2, 171, 3, 248, 1, 13, 24, 70, 1, 33, ++ 197, 243, 30, 240, 192, 178, 14, 189, 112, 71, 45, 233, 240, 79, 161, ++ 176, 0, 35, 47, 153, 43, 159, 4, 70, 144, 70, 42, 158, 44, 157, 221, ++ 248, 180, 176, 30, 147, 31, 147, 231, 247, 145, 251, 3, 47, 129, 70, ++ 11, 217, 4, 34, 30, 168, 49, 70, 195, 247, 27, 250, 7, 47, 4, 217, 31, ++ 168, 49, 29, 4, 34, 195, 247, 20, 250, 221, 248, 120, 160, 26, 241, ++ 0, 2, 24, 191, 1, 34, 211, 178, 184, 241, 75, 15, 0, 242, 67, 131, 223, ++ 232, 24, 240, 76, 0, 82, 0, 89, 0, 93, 0, 98, 0, 102, 0, 157, 0, 161, ++ 0, 141, 0, 146, 0, 183, 0, 65, 3, 187, 0, 191, 0, 108, 0, 113, 0, 243, ++ 0, 65, 3, 247, 0, 65, 3, 255, 0, 7, 1, 3, 1, 65, 3, 50, 1, 65, 3, 99, ++ 1, 65, 3, 33, 2, 49, 2, 127, 1, 132, 1, 137, 1, 143, 1, 70, 2, 75, 2, ++ 149, 1, 65, 3, 179, 1, 184, 1, 197, 1, 202, 1, 14, 2, 18, 2, 28, 2, ++ 65, 3, 65, 3, 65, 3, 205, 0, 213, 0, 106, 2, 88, 2, 129, 2, 111, 2, ++ 148, 2, 134, 2, 170, 2, 153, 2, 203, 2, 175, 2, 208, 2, 216, 2, 27, ++ 3, 13, 3, 65, 3, 65, 3, 238, 2, 65, 3, 248, 2, 65, 3, 8, 3, 255, 2, ++ 65, 3, 65, 3, 40, 3, 35, 3, 32, 70, 79, 250, 138, 241, 254, 247, 222, ++ 255, 61, 224, 32, 70, 81, 70, 157, 249, 124, 32, 255, 247, 194, 253, ++ 87, 224, 32, 70, 254, 247, 227, 255, 50, 224, 32, 70, 25, 70, 255, 247, ++ 153, 253, 48, 225, 32, 70, 254, 247, 222, 255, 41, 224, 32, 70, 73, ++ 70, 82, 70, 255, 247, 238, 250, 68, 224, 212, 248, 116, 52, 147, 248, ++ 60, 48, 186, 226, 212, 248, 116, 20, 145, 248, 60, 0, 152, 66, 0, 240, ++ 181, 130, 131, 240, 1, 5, 129, 248, 60, 32, 32, 70, 41, 70, 255, 247, ++ 122, 253, 32, 70, 41, 70, 79, 240, 255, 50, 255, 247, 148, 253, 0, 40, ++ 0, 240, 181, 130, 32, 70, 254, 247, 235, 251, 159, 226, 32, 70, 254, ++ 247, 188, 255, 40, 96, 154, 226, 35, 106, 24, 105, 239, 247, 169, 252, ++ 133, 7, 14, 213, 32, 70, 30, 153, 255, 247, 116, 250, 19, 224, 32, 70, ++ 255, 247, 56, 252, 238, 231, 35, 106, 24, 105, 239, 247, 154, 252, 128, ++ 7, 5, 212, 30, 157, 0, 45, 24, 191, 111, 240, 22, 5, 149, 226, 32, 70, ++ 30, 153, 255, 247, 30, 252, 0, 40, 12, 191, 111, 240, 28, 5, 0, 37, ++ 139, 226, 212, 248, 116, 52, 155, 120, 112, 226, 212, 248, 116, 52, ++ 91, 120, 108, 226, 186, 241, 255, 63, 3, 209, 212, 248, 116, 52, 27, ++ 120, 30, 147, 0, 34, 32, 70, 30, 153, 19, 70, 255, 247, 253, 253, 197, ++ 224, 212, 248, 116, 52, 0, 43, 0, 240, 111, 130, 147, 249, 96, 48, 86, ++ 226, 186, 241, 1, 15, 0, 243, 101, 130, 186, 241, 255, 63, 0, 240, 80, ++ 130, 212, 248, 116, 52, 131, 248, 96, 160, 212, 248, 116, 52, 89, 121, ++ 91, 120, 67, 234, 1, 17, 186, 241, 0, 15, 2, 208, 1, 240, 240, 1, 1, ++ 224, 1, 240, 15, 1, 32, 70, 255, 247, 108, 254, 57, 226, 212, 248, 116, ++ 52, 27, 120, 52, 226, 212, 248, 116, 4, 1, 33, 5, 48, 196, 243, 242, ++ 246, 192, 178, 144, 231, 212, 248, 116, 52, 91, 121, 40, 226, 212, 248, ++ 116, 52, 219, 120, 36, 226, 32, 70, 81, 70, 1, 34, 255, 247, 35, 252, ++ 5, 70, 0, 40, 64, 240, 51, 130, 212, 248, 116, 52, 154, 121, 26, 113, ++ 212, 248, 116, 52, 212, 248, 56, 3, 153, 121, 56, 48, 249, 247, 11, ++ 254, 212, 248, 108, 18, 32, 70, 212, 248, 56, 99, 234, 243, 226, 247, ++ 56, 54, 255, 35, 0, 147, 1, 144, 49, 70, 48, 70, 42, 70, 43, 70, 249, ++ 247, 150, 253, 32, 70, 41, 70, 255, 247, 162, 254, 16, 226, 212, 248, ++ 116, 52, 154, 127, 147, 248, 32, 16, 18, 4, 66, 234, 1, 98, 153, 126, ++ 10, 67, 25, 127, 66, 234, 1, 34, 28, 146, 25, 126, 154, 125, 66, 234, ++ 1, 34, 29, 146, 98, 126, 58, 177, 32, 70, 64, 242, 212, 81, 237, 243, ++ 185, 245, 131, 178, 219, 11, 15, 224, 147, 248, 138, 16, 65, 177, 153, ++ 120, 1, 41, 7, 217, 155, 121, 1, 43, 148, 191, 0, 35, 1, 35, 2, 224, ++ 11, 70, 0, 224, 19, 70, 219, 178, 29, 154, 66, 234, 195, 83, 22, 224, ++ 212, 248, 116, 52, 147, 248, 37, 32, 147, 248, 38, 16, 18, 4, 66, 234, ++ 1, 98, 147, 248, 35, 16, 10, 67, 147, 248, 36, 16, 66, 234, 1, 34, 28, ++ 146, 147, 248, 34, 32, 147, 248, 33, 48, 67, 234, 2, 35, 29, 147, 40, ++ 70, 28, 169, 8, 34, 117, 225, 212, 248, 116, 52, 147, 248, 48, 48, 167, ++ 225, 212, 248, 116, 52, 131, 248, 48, 160, 163, 225, 212, 248, 116, ++ 20, 40, 70, 92, 49, 4, 34, 101, 225, 32, 70, 49, 70, 255, 247, 108, ++ 251, 5, 70, 173, 225, 115, 136, 19, 43, 64, 242, 156, 129, 19, 47, 64, ++ 242, 153, 129, 51, 136, 1, 43, 64, 240, 143, 129, 187, 241, 19, 15, ++ 64, 243, 142, 129, 40, 70, 49, 70, 58, 70, 195, 247, 94, 248, 41, 70, ++ 32, 70, 255, 247, 198, 249, 0, 40, 20, 191, 0, 37, 111, 240, 22, 5, ++ 143, 225, 212, 248, 116, 52, 147, 248, 79, 48, 115, 225, 186, 241, 0, ++ 15, 192, 242, 130, 129, 212, 248, 116, 52, 26, 120, 146, 69, 128, 242, ++ 124, 129, 131, 248, 79, 160, 103, 225, 212, 248, 116, 52, 147, 248, ++ 78, 48, 97, 225, 186, 241, 0, 15, 192, 242, 112, 129, 212, 248, 116, ++ 52, 26, 120, 146, 69, 0, 243, 106, 129, 147, 248, 78, 32, 95, 250, 138, ++ 250, 82, 69, 0, 240, 82, 129, 131, 248, 78, 160, 212, 248, 116, 52, ++ 147, 248, 72, 80, 0, 45, 0, 240, 95, 129, 233, 7, 11, 213, 32, 70, 2, ++ 33, 255, 247, 109, 253, 212, 248, 116, 52, 147, 248, 72, 32, 34, 240, ++ 1, 2, 131, 248, 72, 32, 212, 248, 116, 52, 147, 248, 72, 80, 21, 240, ++ 2, 5, 0, 240, 73, 129, 1, 33, 32, 70, 255, 247, 89, 253, 212, 248, 116, ++ 52, 147, 248, 72, 32, 34, 240, 2, 2, 131, 248, 72, 32, 34, 104, 212, ++ 248, 116, 52, 145, 106, 90, 107, 138, 26, 154, 99, 30, 225, 212, 248, ++ 116, 52, 91, 108, 25, 225, 10, 241, 1, 3, 2, 43, 0, 242, 39, 129, 212, ++ 248, 116, 52, 195, 248, 68, 160, 16, 225, 212, 248, 116, 52, 147, 248, ++ 72, 48, 10, 225, 187, 241, 19, 15, 64, 243, 16, 129, 212, 248, 116, ++ 36, 0, 35, 209, 24, 145, 249, 87, 16, 1, 51, 5, 43, 69, 248, 4, 27, ++ 247, 209, 251, 224, 19, 47, 64, 242, 1, 129, 0, 35, 86, 248, 4, 43, ++ 28, 169, 210, 178, 90, 84, 1, 50, 210, 178, 2, 42, 0, 242, 255, 128, ++ 1, 51, 5, 43, 242, 209, 32, 70, 254, 247, 4, 254, 76, 231, 212, 248, ++ 116, 52, 147, 248, 81, 48, 224, 224, 212, 248, 116, 20, 32, 70, 129, ++ 248, 81, 32, 3, 34, 0, 146, 4, 33, 128, 34, 219, 1, 235, 243, 186, 247, ++ 212, 224, 35, 104, 32, 70, 81, 70, 0, 34, 27, 126, 255, 247, 166, 249, ++ 5, 70, 0, 40, 64, 240, 224, 128, 212, 248, 116, 52, 157, 248, 120, 32, ++ 163, 248, 76, 32, 216, 224, 212, 248, 116, 52, 179, 248, 76, 48, 188, ++ 224, 35, 104, 32, 70, 81, 70, 1, 34, 27, 126, 255, 247, 143, 249, 5, ++ 70, 0, 40, 64, 240, 201, 128, 212, 248, 116, 52, 157, 248, 120, 32, ++ 163, 248, 74, 32, 193, 224, 212, 248, 116, 52, 179, 248, 74, 48, 165, ++ 224, 186, 241, 100, 15, 0, 242, 180, 128, 212, 248, 116, 52, 186, 241, ++ 15, 15, 184, 191, 79, 240, 15, 10, 131, 248, 73, 160, 17, 224, 212, ++ 248, 116, 52, 147, 248, 73, 48, 146, 224, 186, 241, 100, 15, 0, 242, ++ 161, 128, 212, 248, 116, 52, 186, 241, 15, 15, 184, 191, 79, 240, 15, ++ 10, 131, 248, 122, 160, 32, 70, 255, 247, 119, 249, 130, 224, 212, 248, ++ 116, 52, 147, 248, 122, 48, 124, 224, 1, 33, 212, 248, 116, 4, 196, ++ 243, 59, 245, 95, 250, 138, 250, 130, 69, 127, 210, 30, 154, 212, 248, ++ 116, 52, 32, 70, 131, 248, 123, 32, 212, 248, 108, 18, 1, 241, 188, ++ 2, 253, 247, 11, 255, 1, 70, 0, 40, 115, 208, 32, 70, 254, 247, 223, ++ 248, 97, 224, 212, 248, 116, 52, 147, 248, 123, 48, 91, 224, 32, 70, ++ 64, 242, 212, 81, 237, 243, 48, 244, 0, 178, 192, 15, 183, 229, 32, ++ 70, 64, 242, 212, 81, 237, 243, 40, 244, 26, 240, 255, 15, 5, 208, 111, ++ 234, 64, 66, 111, 234, 82, 66, 146, 178, 1, 224, 66, 4, 82, 12, 32, ++ 70, 64, 242, 212, 81, 241, 243, 162, 242, 62, 224, 32, 70, 2, 169, 1, ++ 240, 187, 253, 40, 70, 2, 169, 104, 34, 194, 247, 16, 255, 52, 224, ++ 32, 70, 1, 240, 118, 253, 0, 35, 43, 96, 29, 70, 67, 224, 10, 241, 128, ++ 3, 255, 43, 58, 216, 212, 248, 116, 52, 131, 248, 75, 161, 36, 224, ++ 212, 248, 116, 52, 147, 249, 75, 49, 30, 224, 212, 248, 116, 52, 147, ++ 248, 28, 33, 114, 179, 211, 248, 80, 33, 32, 70, 81, 70, 211, 248, 84, ++ 49, 1, 240, 233, 253, 119, 230, 212, 248, 116, 52, 147, 248, 28, 33, ++ 2, 179, 211, 248, 76, 49, 8, 224, 212, 248, 116, 52, 163, 248, 144, ++ 160, 4, 224, 212, 248, 116, 52, 179, 248, 144, 48, 43, 96, 0, 37, 19, ++ 224, 111, 240, 36, 5, 16, 224, 111, 240, 23, 5, 13, 224, 111, 240, 13, ++ 5, 10, 224, 111, 240, 1, 5, 7, 224, 79, 240, 255, 53, 4, 224, 111, 240, ++ 28, 5, 1, 224, 111, 240, 22, 5, 40, 70, 33, 176, 189, 232, 240, 143, ++ 115, 181, 208, 248, 116, 36, 0, 35, 146, 248, 40, 16, 141, 248, 7, 48, ++ 130, 248, 39, 16, 208, 248, 116, 36, 4, 70, 130, 248, 40, 48, 208, 248, ++ 116, 52, 147, 248, 39, 80, 106, 178, 1, 50, 4, 209, 105, 70, 254, 247, ++ 159, 253, 0, 37, 28, 224, 109, 185, 13, 241, 255, 54, 38, 75, 212, 248, ++ 116, 4, 89, 93, 254, 247, 30, 253, 3, 53, 18, 45, 6, 248, 1, 15, 244, ++ 209, 238, 231, 91, 120, 141, 248, 0, 48, 141, 248, 1, 48, 141, 248, ++ 2, 48, 141, 248, 3, 48, 141, 248, 4, 48, 141, 248, 5, 48, 224, 231, ++ 212, 248, 116, 52, 238, 178, 90, 25, 146, 248, 33, 32, 10, 185, 29, ++ 248, 5, 32, 141, 248, 7, 32, 3, 235, 69, 2, 82, 125, 155, 120, 154, ++ 66, 2, 217, 0, 35, 141, 248, 7, 48, 1, 33, 13, 241, 7, 0, 196, 243, ++ 87, 244, 212, 248, 116, 52, 155, 120, 152, 66, 2, 217, 0, 35, 141, 248, ++ 7, 48, 32, 70, 49, 70, 157, 248, 7, 32, 1, 53, 254, 247, 243, 255, 6, ++ 45, 213, 209, 32, 70, 0, 33, 255, 247, 38, 252, 212, 248, 160, 1, 8, ++ 177, 54, 240, 215, 220, 124, 189, 48, 89, 4, 0, 75, 28, 4, 43, 10, 216, ++ 223, 232, 3, 240, 3, 4, 4, 9, 3, 0, 3, 33, 208, 248, 116, 52, 0, 32, ++ 25, 114, 112, 71, 111, 240, 28, 0, 112, 71, 254, 247, 55, 191, 254, ++ 247, 37, 189, 208, 248, 116, 52, 88, 137, 112, 71, 3, 104, 64, 242, ++ 110, 82, 211, 248, 216, 16, 112, 181, 139, 106, 4, 70, 147, 66, 14, ++ 208, 8, 107, 65, 242, 107, 2, 144, 66, 7, 209, 209, 43, 7, 208, 163, ++ 241, 233, 5, 106, 66, 66, 235, 5, 2, 2, 224, 0, 34, 0, 224, 1, 34, 9, ++ 107, 213, 178, 65, 242, 107, 2, 145, 66, 19, 209, 214, 43, 19, 208, ++ 245, 43, 17, 208, 239, 43, 15, 208, 64, 242, 15, 18, 147, 66, 11, 208, ++ 244, 43, 9, 208, 228, 43, 7, 208, 163, 245, 135, 112, 66, 66, 66, 235, ++ 0, 2, 2, 224, 0, 34, 0, 224, 1, 34, 65, 242, 228, 64, 129, 66, 210, ++ 178, 8, 209, 64, 242, 218, 86, 198, 235, 3, 12, 220, 241, 0, 6, 70, ++ 235, 12, 6, 0, 224, 0, 38, 22, 67, 65, 242, 107, 2, 145, 66, 44, 209, ++ 179, 245, 137, 127, 43, 208, 179, 245, 154, 127, 40, 208, 64, 242, 23, ++ 18, 147, 66, 36, 208, 64, 242, 55, 18, 147, 66, 32, 208, 64, 242, 51, ++ 18, 147, 66, 28, 208, 179, 245, 153, 127, 25, 208, 179, 245, 165, 127, ++ 22, 208, 64, 242, 41, 18, 147, 66, 18, 208, 179, 245, 161, 127, 15, ++ 208, 64, 242, 53, 18, 147, 66, 11, 208, 179, 245, 155, 127, 8, 208, ++ 64, 242, 17, 18, 152, 26, 66, 66, 66, 235, 0, 2, 2, 224, 0, 34, 0, 224, ++ 1, 34, 65, 242, 228, 64, 129, 66, 210, 178, 8, 209, 64, 242, 27, 96, ++ 192, 235, 3, 12, 220, 241, 0, 0, 64, 235, 12, 0, 0, 224, 0, 32, 2, 67, ++ 65, 242, 107, 0, 129, 66, 6, 209, 64, 242, 49, 17, 89, 26, 75, 66, 67, ++ 235, 1, 3, 0, 224, 0, 35, 212, 248, 116, 20, 0, 32, 129, 248, 97, 0, ++ 212, 248, 116, 20, 219, 178, 193, 248, 140, 0, 29, 185, 22, 185, 10, ++ 185, 0, 43, 99, 208, 1, 32, 129, 248, 97, 0, 61, 177, 212, 248, 116, ++ 20, 145, 248, 97, 0, 64, 240, 2, 0, 129, 248, 97, 0, 33, 104, 209, 248, ++ 216, 16, 136, 106, 239, 40, 12, 208, 64, 242, 15, 17, 136, 66, 8, 208, ++ 228, 40, 6, 208, 160, 245, 135, 124, 220, 241, 0, 0, 64, 235, 12, 0, ++ 0, 224, 1, 32, 212, 248, 116, 20, 13, 177, 2, 35, 2, 224, 35, 177, 79, ++ 244, 0, 83, 193, 248, 140, 48, 10, 224, 10, 177, 4, 35, 249, 231, 11, ++ 70, 22, 177, 8, 177, 8, 35, 244, 231, 16, 34, 195, 248, 140, 32, 212, ++ 248, 116, 52, 0, 38, 147, 248, 72, 80, 195, 248, 140, 96, 233, 7, 17, ++ 213, 147, 248, 97, 32, 146, 7, 32, 213, 1, 34, 147, 248, 73, 16, 32, ++ 70, 19, 70, 254, 247, 71, 255, 212, 248, 116, 52, 32, 70, 147, 248, ++ 73, 16, 50, 70, 13, 224, 141, 185, 1, 34, 179, 248, 74, 16, 32, 70, ++ 19, 70, 254, 247, 56, 255, 212, 248, 116, 52, 32, 70, 179, 248, 76, ++ 16, 42, 70, 1, 35, 189, 232, 112, 64, 254, 247, 45, 191, 112, 189, 45, ++ 233, 248, 67, 4, 70, 21, 70, 153, 70, 0, 38, 26, 224, 60, 39, 119, 67, ++ 7, 241, 56, 8, 160, 68, 40, 70, 8, 241, 10, 1, 16, 34, 194, 247, 9, ++ 253, 104, 185, 72, 70, 8, 241, 4, 1, 6, 34, 194, 247, 2, 253, 48, 185, ++ 225, 25, 8, 152, 82, 49, 32, 34, 194, 247, 14, 253, 3, 224, 1, 54, 163, ++ 107, 158, 66, 225, 211, 160, 107, 51, 26, 88, 66, 64, 235, 3, 0, 189, ++ 232, 248, 131, 45, 233, 240, 65, 68, 106, 5, 70, 4, 241, 108, 7, 56, ++ 70, 79, 244, 128, 113, 202, 243, 37, 247, 0, 40, 33, 209, 4, 241, 72, ++ 6, 49, 70, 32, 34, 56, 70, 202, 243, 90, 247, 32, 35, 227, 128, 43, ++ 105, 179, 248, 90, 48, 25, 6, 5, 212, 106, 104, 146, 248, 102, 33, 82, ++ 177, 154, 6, 8, 213, 4, 241, 196, 0, 49, 70, 32, 34, 194, 247, 219, ++ 252, 227, 136, 164, 248, 228, 48, 40, 105, 189, 232, 240, 65, 1, 240, ++ 183, 155, 35, 104, 0, 34, 152, 104, 161, 110, 19, 70, 189, 232, 240, ++ 65, 217, 243, 136, 180, 45, 233, 240, 79, 1, 58, 149, 176, 4, 70, 136, ++ 70, 208, 248, 12, 176, 6, 106, 6, 42, 0, 242, 242, 128, 223, 232, 18, ++ 240, 7, 0, 240, 0, 115, 0, 240, 0, 147, 0, 240, 0, 184, 0, 245, 104, ++ 0, 45, 0, 240, 230, 128, 182, 248, 206, 160, 26, 244, 128, 74, 12, 208, ++ 3, 104, 1, 105, 211, 248, 192, 6, 3, 104, 203, 88, 27, 120, 27, 177, ++ 19, 240, 78, 216, 130, 70, 0, 224, 154, 70, 247, 136, 32, 104, 87, 68, ++ 191, 178, 7, 241, 113, 3, 33, 105, 4, 241, 24, 2, 155, 178, 55, 240, ++ 29, 219, 5, 70, 0, 40, 0, 240, 196, 128, 95, 55, 191, 178, 208, 248, ++ 8, 144, 59, 10, 67, 234, 7, 39, 169, 248, 16, 112, 9, 241, 18, 7, 0, ++ 33, 95, 34, 56, 70, 195, 243, 255, 247, 72, 244, 132, 115, 26, 10, 137, ++ 248, 19, 32, 137, 248, 20, 48, 51, 139, 6, 241, 60, 1, 26, 10, 137, ++ 248, 21, 32, 137, 248, 22, 48, 32, 34, 9, 241, 31, 0, 194, 247, 107, ++ 252, 242, 136, 9, 241, 113, 0, 146, 68, 31, 250, 138, 250, 79, 234, ++ 26, 35, 67, 234, 10, 42, 169, 248, 111, 160, 241, 104, 194, 247, 92, ++ 252, 182, 248, 206, 48, 88, 4, 64, 241, 144, 128, 35, 104, 33, 105, ++ 211, 248, 192, 6, 3, 104, 203, 88, 27, 120, 0, 43, 0, 240, 134, 128, ++ 58, 70, 18, 240, 228, 222, 129, 224, 0, 104, 33, 105, 4, 241, 24, 2, ++ 113, 35, 55, 240, 204, 218, 5, 70, 0, 40, 115, 208, 208, 248, 8, 144, ++ 95, 34, 0, 33, 9, 241, 18, 7, 137, 248, 17, 32, 137, 248, 16, 16, 56, ++ 70, 195, 243, 178, 247, 72, 244, 128, 115, 26, 10, 137, 248, 19, 32, ++ 137, 248, 20, 48, 51, 139, 30, 224, 0, 104, 33, 105, 4, 241, 24, 2, ++ 113, 35, 55, 240, 172, 218, 5, 70, 0, 40, 83, 208, 208, 248, 8, 144, ++ 95, 34, 0, 33, 9, 241, 18, 7, 137, 248, 17, 32, 137, 248, 16, 16, 56, ++ 70, 195, 243, 146, 247, 72, 244, 64, 115, 26, 10, 137, 248, 19, 32, ++ 137, 248, 20, 48, 243, 138, 26, 10, 137, 248, 21, 32, 137, 248, 22, ++ 48, 60, 224, 0, 104, 33, 105, 4, 241, 24, 2, 113, 35, 55, 240, 135, ++ 218, 5, 70, 120, 179, 208, 248, 8, 144, 0, 33, 95, 34, 9, 241, 18, 7, ++ 137, 248, 16, 16, 137, 248, 17, 32, 56, 70, 195, 243, 110, 247, 79, ++ 234, 24, 35, 137, 248, 19, 48, 137, 248, 20, 128, 31, 224, 182, 248, ++ 206, 0, 201, 247, 146, 253, 1, 70, 72, 70, 6, 241, 140, 2, 107, 70, ++ 198, 243, 240, 240, 4, 70, 48, 185, 41, 70, 88, 70, 34, 70, 203, 247, ++ 165, 251, 37, 70, 7, 224, 7, 241, 77, 0, 105, 70, 16, 34, 194, 247, ++ 205, 251, 0, 224, 0, 37, 40, 70, 21, 176, 189, 232, 240, 143, 3, 35, ++ 137, 248, 15, 48, 182, 248, 206, 0, 201, 247, 252, 253, 6, 241, 92, ++ 4, 0, 40, 12, 191, 254, 35, 2, 35, 56, 70, 8, 34, 0, 248, 5, 59, 33, ++ 70, 194, 247, 179, 251, 8, 33, 32, 70, 198, 243, 185, 240, 24, 240, ++ 3, 1, 201, 209, 195, 231, 45, 233, 240, 79, 145, 248, 19, 128, 11, 125, ++ 139, 176, 67, 234, 8, 40, 24, 240, 3, 9, 4, 70, 14, 70, 7, 146, 71, ++ 105, 5, 106, 205, 248, 32, 128, 5, 209, 181, 248, 206, 0, 201, 247, ++ 68, 253, 132, 70, 0, 224, 204, 70, 5, 241, 92, 10, 6, 241, 23, 11, 1, ++ 32, 8, 35, 89, 70, 82, 70, 205, 248, 16, 192, 197, 243, 208, 244, 130, ++ 69, 221, 248, 16, 192, 0, 240, 200, 131, 24, 244, 128, 114, 6, 146, ++ 16, 208, 51, 138, 26, 10, 66, 234, 3, 35, 155, 178, 92, 43, 64, 242, ++ 188, 131, 48, 70, 97, 70, 5, 241, 140, 2, 197, 243, 93, 247, 0, 40, ++ 0, 240, 179, 131, 51, 138, 26, 10, 66, 234, 3, 35, 155, 178, 94, 43, ++ 64, 242, 171, 131, 150, 248, 111, 16, 150, 248, 112, 32, 66, 234, 1, ++ 34, 95, 50, 147, 66, 192, 240, 161, 131, 6, 241, 18, 3, 89, 70, 8, 34, ++ 80, 70, 9, 147, 194, 247, 82, 251, 5, 241, 100, 0, 89, 70, 8, 34, 194, ++ 247, 76, 251, 181, 248, 206, 0, 201, 247, 132, 253, 0, 40, 103, 208, ++ 24, 244, 128, 95, 100, 208, 150, 248, 111, 32, 150, 248, 112, 48, 67, ++ 234, 2, 35, 179, 245, 128, 127, 11, 221, 56, 70, 33, 105, 1, 34, 46, ++ 240, 7, 218, 32, 105, 4, 241, 24, 1, 1, 34, 55, 240, 77, 219, 186, 226, ++ 79, 244, 128, 112, 203, 247, 196, 250, 130, 70, 48, 185, 56, 70, 33, ++ 105, 1, 34, 46, 240, 245, 217, 209, 70, 105, 227, 32, 32, 203, 247, ++ 184, 250, 131, 70, 72, 185, 80, 70, 203, 247, 182, 250, 56, 70, 33, ++ 105, 1, 34, 46, 240, 230, 217, 217, 70, 90, 227, 79, 244, 129, 112, ++ 203, 247, 168, 250, 5, 144, 72, 185, 80, 70, 203, 247, 166, 250, 88, ++ 70, 203, 247, 163, 250, 56, 70, 33, 105, 1, 34, 198, 226, 185, 241, ++ 0, 15, 4, 209, 181, 248, 206, 0, 201, 247, 170, 252, 129, 70, 5, 154, ++ 73, 70, 0, 35, 2, 146, 9, 152, 5, 241, 156, 2, 141, 232, 0, 12, 197, ++ 243, 13, 247, 129, 70, 80, 70, 203, 247, 136, 250, 88, 70, 203, 247, ++ 133, 250, 5, 152, 203, 247, 130, 250, 185, 241, 0, 15, 3, 209, 56, 70, ++ 33, 105, 1, 34, 243, 226, 150, 248, 21, 160, 179, 125, 181, 248, 206, ++ 0, 67, 234, 10, 42, 197, 243, 99, 243, 16, 185, 24, 240, 8, 11, 43, ++ 208, 186, 241, 13, 15, 11, 208, 3, 216, 186, 241, 5, 15, 21, 209, 13, ++ 224, 186, 241, 16, 15, 24, 208, 186, 241, 32, 15, 14, 209, 17, 224, ++ 24, 240, 8, 15, 20, 208, 56, 70, 33, 105, 2, 34, 69, 226, 24, 240, 8, ++ 15, 16, 208, 56, 70, 33, 105, 3, 34, 62, 226, 56, 70, 33, 105, 4, 34, ++ 58, 226, 79, 240, 2, 11, 7, 224, 79, 240, 4, 11, 4, 224, 79, 240, 3, ++ 11, 1, 224, 79, 240, 1, 11, 24, 240, 8, 9, 0, 240, 249, 129, 43, 138, ++ 91, 69, 3, 208, 56, 70, 33, 105, 5, 34, 36, 226, 6, 155, 0, 43, 64, ++ 240, 195, 128, 3, 35, 43, 96, 181, 248, 206, 48, 88, 6, 5, 212, 98, ++ 104, 146, 248, 102, 33, 106, 179, 153, 6, 43, 213, 19, 244, 128, 73, ++ 40, 209, 150, 248, 111, 16, 150, 248, 112, 48, 4, 34, 6, 241, 113, 0, ++ 67, 234, 1, 33, 197, 243, 106, 247, 2, 70, 80, 179, 67, 120, 19, 43, ++ 3, 216, 56, 70, 33, 105, 4, 34, 136, 226, 99, 106, 33, 105, 72, 51, ++ 0, 147, 79, 240, 32, 9, 32, 70, 6, 50, 1, 241, 188, 3, 205, 248, 4, ++ 144, 255, 247, 55, 253, 0, 40, 64, 240, 169, 130, 99, 106, 163, 248, ++ 6, 144, 14, 224, 26, 6, 12, 213, 97, 106, 177, 248, 228, 32, 66, 177, ++ 1, 241, 72, 0, 196, 49, 194, 247, 83, 250, 99, 106, 179, 248, 228, 32, ++ 218, 128, 99, 106, 219, 136, 0, 43, 0, 240, 145, 130, 5, 241, 28, 9, ++ 6, 241, 31, 1, 32, 34, 72, 70, 5, 241, 60, 6, 194, 247, 64, 250, 32, ++ 34, 32, 104, 49, 70, 234, 243, 101, 242, 181, 248, 206, 224, 30, 244, ++ 128, 79, 10, 208, 35, 104, 33, 105, 211, 248, 192, 6, 3, 104, 203, 88, ++ 27, 120, 19, 177, 18, 240, 90, 221, 69, 224, 35, 104, 27, 104, 147, ++ 248, 102, 49, 27, 179, 33, 105, 10, 109, 19, 5, 12, 212, 73, 242, 32, ++ 3, 14, 234, 3, 3, 59, 185, 209, 248, 244, 48, 147, 248, 131, 48, 152, ++ 6, 20, 213, 146, 5, 18, 213, 99, 106, 4, 241, 24, 0, 3, 241, 72, 2, ++ 0, 146, 219, 136, 194, 49, 1, 147, 5, 241, 140, 3, 2, 147, 171, 138, ++ 74, 70, 3, 147, 51, 70, 197, 243, 225, 242, 28, 224, 33, 105, 4, 241, ++ 24, 10, 80, 70, 194, 49, 6, 34, 194, 247, 231, 249, 0, 40, 0, 240, 62, ++ 130, 99, 106, 33, 105, 3, 241, 72, 2, 0, 146, 219, 136, 80, 70, 1, 147, ++ 5, 241, 140, 3, 2, 147, 171, 138, 194, 49, 3, 147, 74, 70, 51, 70, 197, ++ 243, 195, 244, 64, 246, 59, 98, 56, 70, 33, 105, 8, 234, 2, 2, 1, 35, ++ 46, 240, 242, 216, 8, 177, 4, 35, 46, 225, 56, 70, 33, 105, 13, 34, ++ 46, 240, 166, 216, 25, 226, 7, 155, 75, 185, 151, 248, 22, 144, 185, ++ 241, 0, 15, 12, 191, 79, 244, 0, 121, 79, 240, 0, 9, 1, 224, 79, 240, ++ 0, 9, 181, 248, 206, 0, 201, 247, 253, 251, 65, 242, 200, 51, 0, 40, ++ 8, 191, 79, 244, 228, 115, 3, 234, 8, 2, 24, 191, 79, 240, 0, 9, 154, ++ 66, 64, 240, 250, 129, 25, 234, 8, 15, 64, 240, 246, 129, 43, 104, 3, ++ 59, 4, 43, 0, 242, 241, 129, 41, 70, 5, 35, 65, 248, 28, 59, 6, 241, ++ 31, 0, 32, 34, 194, 247, 142, 249, 0, 40, 64, 240, 229, 129, 150, 248, ++ 111, 160, 150, 248, 112, 48, 181, 248, 206, 0, 67, 234, 10, 42, 201, ++ 247, 208, 251, 0, 40, 65, 208, 6, 241, 113, 3, 24, 70, 81, 70, 48, 34, ++ 5, 147, 201, 247, 116, 250, 129, 70, 200, 177, 181, 248, 206, 48, 66, ++ 120, 91, 4, 64, 241, 207, 129, 35, 104, 33, 105, 211, 248, 192, 54, ++ 27, 104, 203, 88, 27, 120, 0, 43, 0, 240, 197, 129, 18, 58, 146, 178, ++ 193, 225, 168, 104, 9, 241, 2, 1, 2, 48, 194, 247, 92, 249, 24, 177, ++ 56, 70, 33, 105, 7, 34, 22, 224, 5, 155, 153, 248, 1, 32, 10, 235, 3, ++ 1, 201, 235, 1, 1, 137, 178, 144, 28, 129, 66, 29, 221, 111, 240, 1, ++ 3, 155, 26, 72, 68, 201, 24, 48, 34, 201, 247, 65, 250, 160, 177, 33, ++ 105, 56, 70, 6, 34, 46, 240, 35, 216, 9, 224, 171, 136, 83, 69, 6, 209, ++ 168, 104, 6, 241, 113, 1, 82, 70, 194, 247, 52, 249, 32, 177, 32, 105, ++ 4, 241, 24, 1, 17, 34, 23, 224, 181, 248, 206, 0, 201, 247, 121, 251, ++ 168, 177, 6, 241, 113, 0, 81, 70, 201, 247, 235, 250, 24, 177, 67, 120, ++ 6, 59, 32, 43, 11, 217, 56, 70, 33, 105, 9, 34, 45, 240, 255, 223, 32, ++ 105, 4, 241, 24, 1, 1, 34, 55, 240, 69, 217, 108, 225, 64, 242, 11, ++ 34, 56, 70, 33, 105, 8, 234, 2, 2, 3, 35, 46, 240, 51, 216, 129, 70, ++ 40, 177, 6, 35, 24, 240, 64, 9, 43, 96, 4, 209, 24, 224, 56, 70, 33, ++ 105, 13, 34, 38, 225, 4, 241, 24, 2, 5, 146, 42, 138, 43, 139, 0, 146, ++ 5, 154, 32, 104, 1, 146, 33, 105, 5, 241, 172, 2, 55, 240, 193, 216, ++ 181, 248, 206, 0, 201, 247, 59, 251, 0, 40, 51, 208, 3, 224, 56, 70, ++ 33, 105, 8, 34, 13, 225, 81, 70, 6, 241, 113, 0, 201, 247, 167, 250, ++ 66, 120, 128, 70, 6, 58, 146, 178, 234, 130, 131, 121, 5, 241, 108, ++ 9, 3, 240, 3, 3, 133, 248, 204, 48, 8, 241, 8, 1, 72, 70, 194, 247, ++ 226, 248, 149, 248, 204, 32, 235, 138, 141, 232, 4, 8, 6, 241, 79, 2, ++ 2, 146, 152, 248, 6, 32, 33, 105, 2, 240, 4, 2, 3, 146, 32, 104, 74, ++ 70, 55, 240, 16, 216, 35, 104, 33, 105, 211, 248, 100, 6, 50, 70, 236, ++ 247, 251, 252, 181, 248, 206, 0, 201, 247, 1, 251, 192, 177, 8, 35, ++ 43, 96, 56, 70, 33, 105, 0, 34, 45, 240, 143, 223, 35, 105, 5, 154, ++ 219, 104, 32, 104, 0, 147, 121, 33, 6, 35, 209, 247, 201, 254, 35, 104, ++ 34, 105, 211, 248, 192, 54, 27, 104, 211, 88, 0, 34, 26, 112, 241, 224, ++ 6, 35, 43, 96, 238, 224, 43, 104, 5, 43, 64, 242, 235, 128, 35, 106, ++ 90, 138, 90, 69, 8, 208, 179, 248, 206, 0, 197, 243, 42, 241, 24, 177, ++ 56, 70, 33, 105, 10, 34, 172, 224, 8, 244, 96, 115, 179, 245, 96, 127, ++ 64, 240, 216, 128, 7, 35, 43, 96, 181, 248, 206, 0, 201, 247, 199, 250, ++ 129, 70, 0, 40, 64, 208, 150, 248, 111, 16, 150, 248, 112, 48, 6, 241, ++ 113, 0, 67, 234, 1, 33, 201, 247, 50, 250, 129, 70, 24, 177, 66, 120, ++ 6, 58, 32, 42, 7, 217, 33, 105, 56, 70, 11, 34, 45, 240, 69, 223, 79, ++ 240, 0, 9, 184, 224, 146, 178, 234, 130, 131, 121, 5, 241, 108, 10, ++ 3, 240, 3, 3, 133, 248, 204, 48, 9, 241, 8, 1, 80, 70, 194, 247, 98, ++ 248, 149, 248, 204, 32, 235, 138, 0, 146, 106, 138, 33, 105, 1, 146, ++ 6, 241, 79, 2, 2, 146, 153, 248, 6, 32, 32, 104, 2, 240, 4, 2, 3, 146, ++ 82, 70, 54, 240, 143, 223, 35, 104, 33, 105, 211, 248, 100, 6, 50, 70, ++ 236, 247, 122, 252, 112, 224, 186, 241, 32, 15, 86, 216, 79, 244, 128, ++ 112, 202, 247, 218, 255, 5, 144, 56, 185, 33, 105, 56, 70, 12, 34, 45, ++ 240, 11, 223, 221, 248, 20, 144, 126, 224, 32, 32, 202, 247, 205, 255, ++ 6, 144, 80, 185, 5, 152, 202, 247, 203, 255, 56, 70, 33, 105, 12, 34, ++ 45, 240, 251, 222, 221, 248, 24, 144, 110, 224, 79, 244, 129, 112, 202, ++ 247, 188, 255, 132, 70, 128, 185, 5, 152, 205, 248, 16, 192, 202, 247, ++ 184, 255, 6, 152, 202, 247, 181, 255, 56, 70, 33, 105, 12, 34, 45, 240, ++ 229, 222, 221, 248, 16, 192, 225, 70, 87, 224, 5, 241, 108, 3, 7, 147, ++ 5, 154, 6, 155, 65, 70, 0, 146, 1, 147, 5, 241, 156, 2, 7, 155, 2, 144, ++ 9, 152, 205, 248, 16, 192, 197, 243, 22, 244, 129, 70, 5, 152, 202, ++ 247, 151, 255, 6, 152, 202, 247, 148, 255, 221, 248, 16, 192, 96, 70, ++ 202, 247, 143, 255, 165, 248, 22, 160, 185, 241, 0, 15, 5, 209, 33, ++ 105, 56, 70, 12, 34, 45, 240, 186, 222, 47, 224, 8, 154, 8, 240, 48, ++ 3, 27, 17, 141, 232, 8, 8, 2, 240, 64, 3, 79, 54, 3, 147, 32, 104, 33, ++ 105, 7, 154, 83, 70, 2, 150, 54, 240, 22, 223, 56, 70, 33, 105, 8, 240, ++ 11, 2, 5, 35, 45, 240, 229, 222, 40, 177, 8, 35, 43, 96, 56, 70, 33, ++ 105, 0, 34, 2, 224, 33, 105, 56, 70, 13, 34, 45, 240, 149, 222, 35, ++ 105, 32, 104, 219, 104, 121, 33, 0, 147, 4, 241, 24, 2, 6, 35, 209, ++ 247, 206, 253, 79, 240, 1, 9, 72, 70, 11, 176, 189, 232, 240, 143, 169, ++ 136, 147, 28, 153, 66, 127, 244, 64, 174, 55, 230, 16, 181, 120, 177, ++ 113, 177, 4, 104, 9, 89, 89, 177, 82, 177, 128, 138, 9, 24, 72, 106, ++ 17, 70, 195, 128, 26, 70, 72, 48, 189, 232, 16, 64, 193, 247, 155, 191, ++ 16, 189, 248, 181, 21, 70, 2, 104, 131, 138, 138, 88, 211, 24, 92, 106, ++ 227, 136, 3, 179, 43, 136, 7, 43, 29, 217, 162, 136, 154, 66, 29, 209, ++ 47, 29, 56, 70, 4, 241, 8, 1, 195, 243, 193, 243, 88, 177, 18, 224, ++ 163, 25, 56, 70, 41, 136, 10, 74, 147, 248, 72, 48, 195, 243, 97, 243, ++ 1, 54, 63, 24, 0, 224, 6, 70, 227, 136, 158, 66, 240, 219, 64, 35, 43, ++ 128, 0, 32, 248, 189, 79, 240, 255, 48, 248, 189, 79, 240, 255, 48, ++ 248, 189, 242, 27, 4, 0, 240, 181, 12, 70, 17, 70, 2, 104, 135, 176, ++ 162, 88, 134, 138, 0, 42, 119, 208, 16, 104, 0, 40, 119, 208, 136, 123, ++ 149, 25, 133, 248, 40, 0, 200, 123, 3, 40, 30, 209, 23, 104, 2, 63, ++ 1, 47, 26, 216, 15, 138, 79, 234, 23, 44, 76, 234, 7, 39, 191, 178, ++ 76, 47, 7, 216, 147, 89, 27, 104, 211, 248, 136, 48, 90, 110, 1, 50, ++ 90, 102, 91, 224, 142, 124, 254, 46, 1, 208, 2, 46, 5, 209, 40, 70, ++ 26, 70, 255, 247, 141, 251, 1, 32, 81, 224, 19, 104, 2, 43, 77, 209, ++ 0, 40, 75, 209, 139, 125, 1, 43, 73, 209, 139, 124, 1, 43, 70, 209, ++ 42, 106, 178, 248, 206, 48, 153, 7, 5, 212, 8, 43, 3, 208, 16, 43, 1, ++ 208, 91, 6, 59, 213, 1, 35, 19, 96, 107, 106, 0, 37, 221, 128, 180, ++ 248, 162, 51, 180, 248, 190, 0, 180, 248, 188, 32, 88, 64, 180, 248, ++ 160, 51, 83, 64, 24, 67, 180, 248, 192, 32, 180, 248, 164, 51, 83, 64, ++ 24, 67, 128, 178, 24, 179, 4, 241, 188, 6, 32, 70, 49, 70, 230, 247, ++ 11, 251, 224, 177, 39, 124, 49, 70, 197, 235, 7, 14, 222, 241, 0, 7, ++ 71, 235, 14, 7, 4, 245, 104, 112, 6, 34, 193, 247, 244, 254, 32, 104, ++ 33, 70, 125, 34, 51, 70, 0, 149, 1, 149, 2, 151, 3, 149, 4, 149, 228, ++ 243, 247, 243, 40, 70, 2, 224, 16, 70, 0, 224, 0, 32, 7, 176, 240, 189, ++ 45, 233, 255, 71, 144, 232, 16, 2, 142, 121, 5, 70, 15, 70, 0, 46, 87, ++ 209, 64, 242, 4, 64, 202, 247, 111, 254, 128, 70, 0, 40, 83, 208, 56, ++ 81, 49, 70, 64, 242, 4, 66, 195, 243, 76, 242, 171, 138, 217, 248, 188, ++ 38, 8, 235, 3, 4, 72, 248, 3, 144, 43, 105, 79, 240, 1, 10, 227, 96, ++ 235, 104, 98, 97, 163, 96, 171, 104, 39, 97, 99, 96, 212, 32, 200, 248, ++ 0, 96, 136, 248, 4, 160, 202, 247, 78, 254, 32, 98, 0, 40, 55, 208, ++ 49, 70, 212, 34, 195, 243, 45, 242, 232, 32, 202, 247, 68, 254, 96, ++ 98, 0, 40, 45, 208, 49, 70, 232, 34, 195, 243, 35, 242, 212, 248, 36, ++ 128, 232, 104, 200, 248, 0, 144, 20, 73, 34, 70, 51, 70, 216, 243, 3, ++ 247, 200, 248, 104, 0, 224, 177, 232, 104, 17, 73, 34, 70, 51, 70, 216, ++ 243, 250, 246, 96, 99, 160, 177, 35, 106, 40, 106, 1, 147, 99, 106, ++ 105, 70, 0, 151, 2, 147, 141, 248, 12, 160, 194, 243, 103, 244, 48, ++ 70, 4, 224, 111, 240, 6, 0, 1, 224, 79, 240, 255, 48, 4, 176, 189, 232, ++ 240, 135, 40, 70, 57, 70, 44, 240, 231, 218, 245, 231, 17, 250, 3, 0, ++ 61, 208, 134, 0, 240, 181, 3, 104, 137, 176, 205, 88, 12, 70, 131, 138, ++ 0, 45, 44, 208, 42, 121, 82, 179, 238, 88, 43, 104, 59, 179, 209, 248, ++ 236, 112, 214, 248, 188, 6, 1, 241, 188, 2, 45, 240, 17, 220, 2, 47, ++ 23, 208, 5, 171, 0, 147, 7, 171, 1, 147, 214, 248, 188, 6, 33, 70, 4, ++ 170, 6, 171, 44, 240, 62, 217, 6, 155, 33, 70, 0, 147, 5, 155, 1, 147, ++ 7, 155, 2, 147, 214, 248, 188, 6, 42, 104, 4, 155, 44, 240, 61, 218, ++ 214, 248, 188, 6, 33, 70, 1, 34, 45, 240, 237, 220, 9, 176, 240, 189, ++ 45, 233, 248, 67, 21, 70, 2, 104, 153, 70, 138, 88, 131, 138, 0, 39, ++ 12, 70, 2, 235, 3, 8, 62, 70, 15, 224, 60, 38, 6, 251, 7, 134, 60, 54, ++ 40, 70, 49, 70, 6, 34, 193, 247, 16, 254, 32, 185, 180, 248, 90, 32, ++ 179, 107, 154, 66, 4, 208, 1, 55, 216, 248, 56, 48, 159, 66, 235, 211, ++ 216, 248, 56, 48, 159, 66, 14, 209, 15, 47, 6, 216, 60, 38, 6, 251, ++ 7, 134, 1, 55, 60, 54, 200, 248, 56, 112, 38, 177, 48, 70, 41, 70, 6, ++ 34, 193, 247, 5, 254, 6, 241, 22, 5, 0, 33, 32, 34, 40, 70, 195, 243, ++ 126, 241, 216, 248, 36, 16, 32, 34, 72, 49, 40, 70, 193, 247, 247, 253, ++ 176, 29, 73, 70, 16, 34, 193, 247, 242, 253, 180, 248, 90, 48, 179, ++ 99, 189, 232, 248, 131, 45, 233, 240, 79, 135, 176, 5, 147, 3, 104, ++ 221, 248, 64, 128, 176, 248, 20, 176, 81, 248, 3, 160, 64, 70, 13, 70, ++ 4, 146, 10, 235, 11, 9, 200, 247, 23, 254, 0, 40, 64, 240, 145, 128, ++ 6, 70, 4, 70, 15, 224, 60, 36, 4, 251, 6, 148, 60, 52, 64, 70, 33, 70, ++ 6, 34, 193, 247, 185, 253, 32, 185, 181, 248, 90, 32, 163, 107, 154, ++ 66, 4, 208, 1, 54, 217, 248, 56, 48, 158, 66, 235, 211, 217, 248, 56, ++ 48, 158, 66, 13, 209, 15, 46, 6, 216, 60, 36, 4, 251, 6, 148, 1, 54, ++ 60, 52, 201, 248, 56, 96, 32, 70, 65, 70, 6, 34, 193, 247, 175, 253, ++ 0, 44, 104, 208, 4, 241, 22, 6, 48, 70, 0, 33, 32, 34, 195, 243, 38, ++ 241, 48, 70, 4, 153, 5, 154, 193, 247, 161, 253, 181, 248, 90, 48, 128, ++ 32, 163, 99, 202, 247, 53, 253, 6, 70, 0, 40, 86, 208, 80, 32, 202, ++ 247, 47, 253, 7, 70, 24, 185, 48, 70, 202, 247, 45, 253, 77, 224, 90, ++ 248, 11, 0, 3, 104, 147, 248, 102, 49, 147, 177, 181, 248, 90, 48, 153, ++ 6, 14, 213, 66, 70, 41, 70, 252, 247, 2, 254, 2, 70, 64, 179, 90, 248, ++ 11, 48, 41, 70, 211, 248, 80, 8, 163, 29, 251, 247, 91, 254, 31, 224, ++ 217, 248, 16, 48, 26, 109, 18, 5, 5, 212, 211, 248, 244, 48, 147, 248, ++ 131, 48, 152, 6, 10, 213, 163, 29, 141, 232, 200, 0, 64, 70, 5, 241, ++ 194, 1, 4, 154, 5, 155, 196, 243, 1, 246, 9, 224, 163, 29, 141, 232, ++ 200, 0, 64, 70, 5, 241, 194, 1, 4, 154, 5, 155, 196, 243, 248, 247, ++ 48, 70, 202, 247, 240, 252, 56, 70, 202, 247, 237, 252, 17, 155, 123, ++ 177, 24, 70, 161, 29, 16, 34, 193, 247, 73, 253, 0, 32, 9, 224, 111, ++ 240, 1, 0, 6, 224, 79, 240, 255, 48, 3, 224, 111, 240, 26, 0, 0, 224, ++ 17, 152, 7, 176, 189, 232, 240, 143, 45, 233, 247, 79, 221, 248, 48, ++ 128, 23, 70, 184, 248, 0, 32, 131, 70, 12, 70, 29, 70, 157, 248, 52, ++ 160, 0, 42, 0, 240, 161, 128, 184, 248, 2, 144, 0, 38, 25, 240, 1, 9, ++ 206, 128, 142, 128, 87, 208, 64, 42, 68, 209, 8, 70, 51, 70, 8, 241, ++ 4, 1, 0, 150, 54, 240, 244, 219, 176, 66, 192, 242, 143, 128, 183, 248, ++ 206, 0, 200, 247, 109, 255, 16, 179, 186, 241, 0, 15, 31, 208, 219, ++ 248, 188, 6, 3, 104, 235, 88, 139, 177, 27, 121, 123, 177, 183, 248, ++ 206, 48, 91, 6, 11, 213, 5, 241, 188, 2, 141, 232, 68, 0, 227, 136, ++ 41, 70, 4, 241, 72, 2, 255, 247, 13, 255, 0, 40, 116, 209, 181, 248, ++ 90, 48, 88, 4, 4, 213, 219, 248, 192, 6, 41, 70, 18, 240, 29, 216, 183, ++ 248, 206, 0, 16, 240, 128, 0, 2, 209, 186, 241, 0, 15, 99, 209, 4, 241, ++ 196, 0, 4, 241, 72, 1, 226, 136, 193, 247, 224, 252, 227, 136, 164, ++ 248, 228, 48, 79, 224, 162, 241, 8, 3, 155, 178, 55, 43, 78, 216, 1, ++ 241, 8, 0, 8, 241, 4, 1, 193, 247, 209, 252, 184, 248, 0, 128, 48, 70, ++ 164, 248, 4, 128, 71, 224, 32, 42, 67, 216, 1, 241, 72, 6, 48, 70, 8, ++ 241, 4, 1, 193, 247, 194, 252, 183, 248, 206, 48, 184, 248, 0, 32, 25, ++ 6, 164, 248, 4, 144, 226, 128, 2, 212, 186, 241, 0, 15, 7, 209, 4, 241, ++ 196, 0, 49, 70, 193, 247, 177, 252, 227, 136, 164, 248, 228, 48, 219, ++ 248, 188, 6, 3, 104, 235, 88, 147, 177, 27, 121, 131, 177, 183, 248, ++ 206, 48, 91, 6, 12, 213, 186, 241, 0, 15, 9, 208, 5, 241, 188, 2, 0, ++ 146, 0, 34, 1, 146, 227, 136, 41, 70, 50, 70, 255, 247, 169, 254, 181, ++ 248, 90, 0, 16, 244, 128, 64, 13, 208, 219, 248, 192, 6, 41, 70, 17, ++ 240, 186, 223, 0, 32, 6, 224, 16, 70, 4, 224, 79, 240, 255, 48, 1, 224, ++ 111, 240, 1, 0, 189, 232, 254, 143, 45, 233, 240, 71, 146, 70, 2, 104, ++ 31, 70, 138, 88, 131, 138, 12, 70, 2, 235, 3, 8, 0, 37, 27, 224, 207, ++ 177, 60, 38, 6, 251, 5, 134, 6, 241, 60, 9, 80, 70, 73, 70, 6, 34, 56, ++ 54, 193, 247, 86, 252, 104, 185, 180, 248, 90, 32, 243, 107, 154, 66, ++ 8, 209, 56, 70, 6, 241, 10, 1, 16, 34, 193, 247, 93, 252, 1, 32, 189, ++ 232, 240, 135, 1, 53, 216, 248, 56, 48, 157, 66, 223, 211, 0, 32, 189, ++ 232, 240, 135, 3, 104, 16, 181, 203, 88, 123, 177, 132, 138, 0, 33, ++ 28, 25, 32, 106, 8, 34, 92, 48, 194, 243, 198, 247, 32, 106, 0, 33, ++ 100, 48, 8, 34, 189, 232, 16, 64, 194, 243, 190, 183, 16, 189, 2, 104, ++ 112, 181, 131, 138, 141, 88, 12, 70, 6, 70, 237, 24, 45, 240, 6, 217, ++ 48, 70, 33, 70, 255, 247, 192, 253, 4, 245, 104, 114, 6, 50, 35, 122, ++ 33, 70, 48, 70, 45, 240, 234, 217, 6, 70, 32, 70, 230, 247, 103, 251, ++ 43, 106, 8, 34, 26, 96, 48, 70, 112, 189, 56, 181, 29, 70, 144, 177, ++ 3, 104, 132, 138, 203, 88, 115, 177, 28, 25, 17, 70, 4, 241, 48, 0, ++ 16, 34, 193, 247, 17, 252, 4, 241, 64, 0, 41, 70, 32, 34, 189, 232, ++ 56, 64, 193, 247, 9, 188, 56, 189, 240, 181, 208, 248, 116, 68, 133, ++ 176, 148, 248, 28, 49, 6, 70, 148, 248, 233, 80, 19, 185, 132, 248, ++ 40, 49, 76, 224, 3, 106, 13, 241, 15, 1, 24, 105, 237, 247, 6, 253, ++ 157, 248, 15, 48, 1, 43, 20, 191, 2, 33, 3, 33, 211, 241, 1, 2, 56, ++ 191, 0, 34, 132, 248, 175, 32, 23, 70, 0, 34, 196, 248, 204, 32, 196, ++ 248, 200, 32, 196, 248, 208, 32, 196, 248, 212, 32, 3, 241, 24, 2, 4, ++ 235, 130, 2, 210, 248, 172, 0, 1, 48, 194, 248, 172, 0, 214, 248, 32, ++ 35, 2, 42, 22, 208, 212, 248, 224, 0, 212, 248, 228, 32, 144, 66, 16, ++ 217, 152, 28, 4, 235, 128, 0, 4, 235, 67, 3, 179, 249, 178, 32, 208, ++ 248, 176, 224, 194, 235, 14, 2, 82, 250, 5, 245, 192, 248, 176, 32, ++ 163, 248, 178, 80, 132, 248, 73, 113, 0, 37, 1, 35, 1, 147, 48, 105, ++ 42, 70, 11, 70, 0, 149, 228, 247, 41, 251, 132, 248, 40, 81, 5, 176, ++ 240, 189, 16, 181, 10, 122, 208, 248, 116, 52, 42, 179, 144, 248, 45, ++ 34, 209, 248, 244, 0, 42, 177, 144, 248, 96, 0, 144, 66, 40, 191, 2, ++ 70, 1, 224, 144, 248, 96, 32, 209, 248, 4, 1, 4, 120, 100, 177, 0, 122, ++ 209, 248, 244, 16, 24, 177, 201, 141, 74, 67, 0, 33, 1, 224, 202, 141, ++ 1, 33, 131, 248, 41, 17, 5, 224, 1, 34, 131, 248, 41, 33, 209, 248, ++ 244, 32, 210, 141, 10, 50, 3, 224, 131, 248, 41, 33, 79, 244, 155, 114, ++ 195, 248, 36, 33, 16, 189, 45, 233, 240, 79, 139, 176, 23, 70, 155, ++ 70, 157, 249, 80, 32, 157, 248, 84, 48, 208, 248, 116, 68, 3, 146, 7, ++ 147, 157, 248, 92, 32, 24, 155, 8, 146, 9, 147, 180, 248, 198, 32, 180, ++ 248, 240, 48, 5, 146, 6, 147, 212, 248, 216, 32, 148, 248, 28, 49, 5, ++ 70, 14, 70, 157, 248, 88, 128, 148, 248, 233, 160, 4, 146, 0, 43, 0, ++ 240, 77, 129, 148, 248, 40, 49, 59, 177, 128, 104, 212, 248, 48, 17, ++ 216, 243, 48, 243, 0, 35, 132, 248, 40, 49, 142, 33, 40, 105, 4, 240, ++ 109, 223, 67, 0, 78, 51, 79, 246, 254, 113, 25, 64, 40, 105, 4, 240, ++ 101, 223, 148, 248, 88, 49, 129, 70, 255, 43, 8, 208, 148, 248, 232, ++ 48, 1, 34, 18, 250, 3, 243, 0, 234, 3, 9, 31, 250, 137, 249, 148, 248, ++ 175, 48, 67, 69, 20, 208, 0, 35, 8, 241, 50, 2, 4, 235, 130, 2, 195, ++ 235, 8, 1, 147, 96, 74, 66, 66, 235, 1, 2, 50, 50, 4, 235, 130, 2, 132, ++ 248, 175, 128, 196, 248, 204, 48, 196, 248, 200, 48, 147, 96, 187, 241, ++ 0, 15, 0, 240, 11, 129, 7, 155, 203, 185, 2, 46, 64, 243, 6, 129, 198, ++ 235, 11, 11, 180, 249, 242, 32, 15, 250, 139, 251, 4, 235, 72, 3, 147, ++ 69, 168, 191, 90, 70, 163, 248, 234, 32, 213, 248, 116, 52, 91, 121, ++ 1, 43, 37, 217, 3, 154, 211, 27, 164, 248, 238, 48, 32, 224, 6, 154, ++ 19, 178, 4, 235, 72, 2, 178, 249, 234, 96, 198, 235, 11, 6, 246, 26, ++ 2, 46, 3, 221, 28, 46, 168, 191, 28, 38, 0, 224, 3, 38, 213, 248, 116, ++ 36, 82, 121, 1, 42, 11, 217, 180, 249, 238, 112, 3, 154, 215, 27, 255, ++ 26, 2, 47, 3, 221, 28, 47, 168, 191, 28, 39, 0, 224, 3, 39, 213, 248, ++ 108, 50, 155, 121, 43, 185, 8, 155, 27, 177, 40, 70, 9, 153, 255, 247, ++ 31, 255, 212, 248, 224, 48, 212, 248, 228, 32, 147, 66, 3, 217, 5, 152, ++ 0, 178, 3, 144, 7, 224, 1, 51, 212, 248, 220, 32, 196, 248, 224, 48, ++ 1, 35, 4, 146, 3, 147, 8, 241, 84, 11, 8, 241, 44, 1, 4, 235, 129, 1, ++ 4, 235, 75, 2, 209, 248, 8, 192, 178, 249, 10, 0, 1, 35, 192, 235, 12, ++ 0, 128, 25, 136, 96, 64, 250, 10, 240, 8, 241, 50, 1, 4, 235, 129, 1, ++ 80, 129, 138, 104, 3, 250, 10, 243, 1, 50, 138, 96, 212, 248, 56, 17, ++ 196, 248, 204, 32, 1, 49, 196, 248, 56, 17, 8, 241, 78, 1, 4, 235, 129, ++ 1, 72, 104, 1, 48, 72, 96, 212, 248, 192, 0, 180, 249, 182, 16, 154, ++ 66, 193, 235, 0, 1, 15, 68, 196, 248, 192, 112, 71, 250, 10, 247, 4, ++ 235, 75, 1, 164, 248, 182, 112, 180, 249, 196, 0, 177, 249, 10, 16, ++ 40, 191, 132, 248, 177, 128, 136, 66, 100, 219, 4, 152, 130, 66, 12, ++ 217, 216, 241, 1, 1, 148, 248, 232, 32, 56, 191, 0, 33, 17, 250, 2, ++ 242, 145, 69, 43, 208, 8, 241, 60, 2, 35, 224, 148, 248, 68, 1, 184, ++ 241, 0, 15, 6, 208, 180, 249, 178, 96, 64, 178, 113, 26, 0, 235, 193, ++ 1, 5, 224, 180, 249, 180, 96, 64, 178, 113, 26, 201, 0, 9, 26, 3, 152, ++ 177, 235, 192, 15, 62, 219, 154, 66, 60, 211, 216, 241, 1, 1, 148, 248, ++ 232, 32, 56, 191, 0, 33, 17, 250, 2, 242, 145, 69, 6, 208, 8, 241, 62, ++ 2, 4, 235, 130, 2, 81, 104, 1, 49, 81, 96, 1, 34, 184, 241, 0, 15, 20, ++ 191, 3, 33, 2, 33, 148, 248, 175, 0, 132, 248, 73, 1, 148, 248, 29, ++ 1, 64, 177, 66, 177, 0, 34, 40, 105, 11, 70, 0, 146, 1, 146, 228, 247, ++ 160, 249, 4, 224, 26, 185, 212, 248, 204, 32, 154, 66, 25, 210, 148, ++ 248, 29, 49, 179, 177, 1, 35, 132, 248, 40, 49, 168, 104, 212, 248, ++ 48, 17, 212, 248, 36, 33, 0, 35, 11, 176, 189, 232, 240, 79, 216, 243, ++ 206, 177, 184, 241, 0, 15, 12, 191, 66, 70, 0, 34, 20, 191, 2, 33, 3, ++ 33, 208, 231, 11, 176, 189, 232, 240, 143, 127, 181, 208, 248, 116, ++ 100, 5, 70, 150, 248, 28, 49, 12, 70, 43, 179, 3, 105, 147, 248, 10, ++ 49, 11, 179, 150, 248, 29, 49, 243, 177, 3, 106, 13, 241, 15, 1, 24, ++ 105, 237, 247, 0, 251, 157, 248, 15, 48, 0, 34, 134, 248, 175, 48, 134, ++ 248, 73, 49, 0, 43, 20, 191, 3, 33, 2, 33, 1, 35, 141, 232, 12, 0, 40, ++ 105, 11, 70, 228, 247, 86, 249, 157, 248, 15, 48, 84, 248, 35, 32, 1, ++ 50, 68, 248, 35, 32, 127, 189, 112, 181, 208, 248, 116, 68, 5, 70, 148, ++ 248, 28, 49, 235, 177, 212, 248, 204, 32, 212, 248, 200, 48, 154, 66, ++ 3, 209, 4, 245, 138, 113, 255, 247, 192, 255, 212, 248, 204, 48, 196, ++ 248, 200, 48, 148, 248, 29, 49, 99, 177, 148, 248, 41, 49, 75, 177, ++ 168, 104, 212, 248, 52, 17, 79, 244, 250, 114, 0, 35, 189, 232, 112, ++ 64, 216, 243, 110, 177, 112, 189, 56, 181, 208, 248, 116, 68, 5, 70, ++ 212, 248, 52, 17, 128, 104, 216, 243, 138, 241, 212, 248, 204, 32, 212, ++ 248, 200, 48, 154, 66, 4, 209, 40, 70, 4, 245, 138, 113, 255, 247, 151, ++ 255, 212, 248, 204, 48, 196, 248, 200, 48, 56, 189, 208, 248, 116, 52, ++ 0, 34, 79, 246, 162, 113, 195, 248, 184, 32, 195, 248, 188, 32, 195, ++ 248, 192, 32, 163, 248, 178, 32, 163, 248, 180, 32, 163, 248, 182, 32, ++ 163, 248, 234, 16, 163, 248, 236, 16, 163, 248, 238, 16, 195, 248, 204, ++ 32, 195, 248, 208, 32, 195, 248, 212, 32, 195, 248, 56, 33, 195, 248, ++ 60, 33, 195, 248, 64, 33, 195, 248, 224, 32, 195, 248, 244, 32, 195, ++ 248, 248, 32, 195, 248, 252, 32, 195, 248, 0, 33, 195, 248, 4, 33, 195, ++ 248, 8, 33, 195, 248, 12, 33, 195, 248, 16, 33, 195, 248, 20, 33, 195, ++ 248, 24, 33, 131, 248, 41, 33, 112, 71, 208, 248, 116, 52, 211, 248, ++ 204, 32, 138, 96, 211, 248, 56, 33, 138, 100, 147, 248, 29, 33, 18, ++ 177, 147, 248, 175, 32, 1, 224, 147, 248, 172, 32, 74, 96, 147, 248, ++ 29, 33, 10, 96, 147, 248, 72, 33, 74, 101, 74, 104, 138, 101, 211, 248, ++ 208, 32, 10, 100, 211, 248, 212, 32, 74, 100, 211, 248, 60, 33, 202, ++ 100, 211, 248, 64, 33, 10, 101, 179, 249, 178, 32, 202, 96, 179, 249, ++ 180, 32, 10, 97, 179, 249, 182, 32, 74, 97, 211, 248, 244, 32, 138, ++ 97, 211, 248, 248, 32, 202, 97, 211, 248, 252, 32, 10, 98, 211, 248, ++ 0, 33, 74, 98, 211, 248, 4, 33, 138, 98, 211, 248, 8, 33, 202, 98, 211, ++ 248, 12, 33, 10, 99, 211, 248, 16, 33, 74, 99, 211, 248, 20, 33, 138, ++ 99, 211, 248, 24, 33, 202, 99, 211, 248, 76, 33, 202, 101, 211, 248, ++ 80, 33, 211, 248, 84, 49, 10, 102, 75, 102, 112, 71, 247, 181, 208, ++ 248, 116, 68, 212, 248, 76, 81, 141, 66, 7, 209, 212, 248, 80, 81, 149, ++ 66, 3, 209, 212, 248, 84, 33, 154, 66, 63, 208, 1, 240, 15, 5, 4, 45, ++ 61, 216, 2, 45, 59, 208, 3, 240, 3, 2, 2, 42, 55, 208, 31, 9, 7, 240, ++ 3, 7, 2, 47, 50, 208, 10, 9, 2, 240, 15, 2, 4, 42, 45, 216, 2, 42, 43, ++ 208, 158, 8, 6, 240, 3, 6, 2, 46, 38, 208, 158, 9, 6, 240, 3, 6, 2, ++ 46, 33, 208, 196, 248, 84, 49, 3, 106, 196, 248, 76, 17, 27, 104, 196, ++ 248, 80, 17, 2, 43, 4, 191, 62, 70, 42, 70, 4, 42, 20, 191, 17, 70, ++ 49, 70, 132, 248, 173, 16, 208, 248, 116, 52, 1, 34, 0, 36, 131, 248, ++ 70, 17, 141, 232, 20, 0, 11, 70, 0, 105, 228, 247, 48, 248, 32, 70, ++ 3, 224, 0, 32, 1, 224, 111, 240, 28, 0, 254, 189, 45, 233, 243, 65, ++ 4, 104, 221, 248, 36, 128, 0, 35, 5, 70, 13, 153, 32, 70, 22, 70, 8, ++ 159, 0, 147, 1, 147, 229, 247, 15, 250, 184, 241, 3, 15, 12, 217, 4, ++ 34, 104, 70, 57, 70, 193, 247, 153, 248, 184, 241, 7, 15, 4, 217, 1, ++ 168, 57, 29, 4, 34, 193, 247, 145, 248, 9, 46, 2, 208, 12, 46, 21, 209, ++ 14, 224, 0, 155, 43, 114, 35, 104, 147, 248, 63, 0, 128, 177, 32, 70, ++ 239, 243, 193, 241, 32, 70, 1, 33, 239, 243, 121, 242, 0, 32, 7, 224, ++ 40, 70, 10, 153, 11, 154, 52, 240, 148, 220, 1, 224, 111, 240, 22, 0, ++ 189, 232, 252, 129, 45, 233, 248, 67, 31, 70, 3, 106, 4, 70, 24, 105, ++ 13, 70, 22, 70, 237, 247, 194, 248, 35, 106, 129, 70, 24, 105, 238, ++ 247, 107, 249, 128, 70, 212, 248, 92, 1, 13, 240, 117, 222, 16, 240, ++ 1, 15, 200, 68, 7, 208, 35, 106, 147, 249, 4, 65, 24, 235, 4, 8, 72, ++ 191, 8, 241, 3, 8, 48, 70, 232, 243, 162, 245, 35, 35, 45, 26, 3, 61, ++ 59, 112, 2, 35, 127, 45, 168, 191, 127, 37, 123, 112, 111, 240, 127, ++ 3, 79, 234, 168, 4, 157, 66, 184, 191, 29, 70, 188, 112, 253, 112, 189, ++ 232, 248, 131, 112, 71, 0, 0, 5, 75, 27, 136, 195, 24, 27, 122, 163, ++ 241, 1, 2, 83, 66, 67, 235, 2, 3, 3, 112, 112, 71, 0, 191, 22, 7, 0, ++ 0, 112, 181, 0, 36, 6, 70, 37, 70, 5, 224, 115, 25, 216, 120, 200, 247, ++ 83, 250, 1, 53, 4, 67, 179, 120, 157, 66, 246, 211, 32, 70, 112, 189, ++ 45, 233, 243, 65, 152, 70, 83, 120, 20, 70, 177, 248, 90, 32, 19, 43, ++ 6, 70, 13, 70, 1, 146, 92, 217, 231, 120, 163, 120, 67, 234, 7, 35, ++ 1, 43, 86, 209, 103, 121, 34, 121, 66, 234, 7, 39, 1, 47, 78, 209, 160, ++ 29, 42, 73, 3, 34, 192, 247, 236, 255, 0, 40, 74, 209, 99, 122, 1, 43, ++ 3, 209, 1, 154, 82, 5, 65, 213, 4, 224, 2, 43, 65, 209, 1, 155, 27, ++ 5, 62, 213, 160, 29, 1, 169, 0, 34, 200, 247, 170, 249, 0, 40, 54, 208, ++ 189, 248, 4, 48, 168, 248, 0, 48, 231, 122, 163, 122, 67, 234, 7, 39, ++ 1, 47, 44, 209, 4, 241, 12, 8, 64, 70, 23, 73, 3, 34, 192, 247, 198, ++ 255, 40, 187, 226, 123, 48, 104, 41, 70, 1, 42, 12, 191, 11, 34, 0, ++ 34, 53, 240, 215, 220, 216, 177, 8, 153, 64, 70, 195, 243, 252, 247, ++ 4, 241, 16, 0, 12, 73, 3, 34, 192, 247, 177, 255, 128, 185, 226, 124, ++ 48, 104, 1, 42, 12, 191, 11, 34, 0, 34, 41, 70, 53, 240, 194, 220, 208, ++ 241, 1, 7, 56, 191, 0, 39, 2, 224, 31, 70, 0, 224, 1, 39, 56, 70, 189, ++ 232, 252, 129, 0, 191, 207, 22, 4, 0, 16, 181, 12, 70, 113, 177, 136, ++ 104, 8, 177, 201, 247, 66, 255, 224, 104, 8, 177, 201, 247, 62, 255, ++ 32, 70, 0, 33, 212, 34, 189, 232, 16, 64, 194, 243, 26, 179, 16, 189, ++ 0, 0, 0, 16, 24, 0, 0, 64, 150, 0, 0, 80, 242, 0, 0, 15, 172, 0, 0, ++ 20, 114, 0, 1, 50, 1, 3, 50, 61, 0, 144, 76, 51, 0, 170, 170, 3, 0, ++ 0, 0, 136, 180, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 0, 80, 242, 1, 0, 0, 80, ++ 242, 0, 0, 64, 150, 0, 0, 15, 172, 0, 0, 15, 172, 6, 0, 10, 32, 4, 4, ++ 0, 80, 242, 0, 0, 15, 172, 0, 0, 64, 150, 0, 0, 0, 0, 0, 0, 12, 11, ++ 18, 15, 24, 10, 36, 14, 48, 9, 72, 13, 96, 8, 108, 12, 94, 0, 96, 0, ++ 98, 0, 120, 0, 212, 0, 12, 18, 24, 36, 48, 72, 96, 108, 0, 144, 76, ++ 0, 0, 16, 24, 0, 0, 15, 172, 6, 0, 0, 15, 172, 0, 0, 204, 1, 2, 0, 0, ++ 0, 212, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 110, 132, 11, 0, 0, 0, ++ 212, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 12, 18, 24, 36, 48, 72, ++ 96, 108, 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 13, 12, ++ 12, 13, 16, 20, 25, 5, 12, 19, 2, 11, 20, 5, 15, 1, 25, 243, 2, 0, 179, ++ 211, 2, 0, 151, 211, 2, 0, 89, 212, 2, 0, 123, 211, 2, 0, 61, 216, 2, ++ 0, 113, 211, 2, 0, 0, 0, 0, 0, 16, 9, 30, 9, 31, 9, 36, 9, 37, 9, 38, ++ 9, 32, 9, 33, 9, 39, 9, 40, 9, 41, 9, 34, 9, 35, 9, 48, 9, 49, 9, 50, ++ 9, 18, 9, 15, 9, 0, 9, 1, 9, 6, 9, 7, 9, 8, 9, 2, 9, 3, 9, 9, 9, 10, ++ 9, 11, 9, 4, 9, 5, 9, 12, 9, 13, 9, 14, 9, 17, 9, 1, 1, 0, 0, 1, 1, ++ 28, 112, 64, 0, 45, 2, 240, 0, 10, 1, 40, 0, 40, 1, 56, 1, 72, 1, 88, ++ 1, 85, 1, 80, 1, 80, 3, 102, 102, 226, 1, 102, 102, 227, 1, 102, 102, ++ 228, 1, 102, 102, 229, 1, 102, 102, 230, 1, 102, 102, 231, 1, 102, 102, ++ 232, 1, 102, 102, 233, 1, 102, 102, 234, 1, 102, 102, 235, 1, 102, 102, ++ 236, 1, 102, 102, 237, 1, 102, 102, 238, 1, 205, 204, 240, 1, 10, 0, ++ 5, 0, 8, 0, 64, 6, 8, 0, 5, 0, 8, 0, 8, 0, 119, 0, 8, 0, 138, 0, 8, ++ 0, 1, 0, 5, 0, 1, 0, 10, 0, 1, 0, 5, 0, 64, 6, 101, 2, 52, 2, 132, 0, ++ 116, 0, 86, 0, 101, 2, 52, 2, 2, 4, 11, 22, 36, 48, 72, 96, 108, 2, ++ 4, 11, 12, 18, 24, 36, 48, 72, 96, 108, 2, 4, 11, 2, 4, 11, 22, 0, 20, ++ 114, 0, 55, 46, 52, 53, 46, 57, 56, 46, 57, 53, 32, 40, 114, 55, 50, ++ 52, 51, 48, 51, 32, 67, 89, 41, 0, 114, 101, 99, 108, 97, 105, 109, ++ 32, 115, 101, 99, 116, 105, 111, 110, 32, 37, 115, 58, 32, 82, 101, ++ 116, 117, 114, 110, 101, 100, 32, 37, 100, 32, 98, 121, 116, 101, 115, ++ 32, 116, 111, 32, 116, 104, 101, 32, 104, 101, 97, 112, 10, 0, 77, 101, ++ 109, 111, 114, 121, 32, 117, 115, 97, 103, 101, 58, 10, 0, 9, 84, 101, ++ 120, 116, 58, 32, 37, 108, 100, 40, 37, 108, 100, 75, 41, 44, 32, 68, ++ 97, 116, 97, 58, 32, 37, 108, 100, 40, 37, 108, 100, 75, 41, 44, 32, ++ 66, 115, 115, 58, 32, 37, 108, 100, 40, 37, 108, 100, 75, 41, 44, 32, ++ 83, 116, 97, 99, 107, 58, 32, 37, 100, 75, 10, 0, 9, 65, 114, 101, 110, ++ 97, 32, 116, 111, 116, 97, 108, 58, 32, 37, 100, 40, 37, 100, 75, 41, ++ 44, 32, 70, 114, 101, 101, 58, 32, 37, 100, 40, 37, 100, 75, 41, 44, ++ 32, 73, 110, 32, 117, 115, 101, 58, 32, 37, 100, 40, 37, 100, 75, 41, ++ 44, 32, 72, 87, 77, 58, 32, 37, 100, 40, 37, 100, 75, 41, 10, 0, 9, ++ 73, 110, 32, 117, 115, 101, 32, 43, 32, 111, 118, 101, 114, 104, 101, ++ 97, 100, 58, 32, 37, 100, 40, 37, 100, 75, 41, 44, 32, 77, 97, 120, ++ 32, 109, 101, 109, 111, 114, 121, 32, 105, 110, 32, 117, 115, 101, 58, ++ 32, 37, 108, 100, 40, 37, 108, 100, 75, 41, 10, 0, 9, 77, 97, 108, 108, ++ 111, 99, 32, 102, 97, 105, 108, 117, 114, 101, 32, 99, 111, 117, 110, ++ 116, 58, 32, 37, 100, 10, 0, 9, 83, 116, 97, 99, 107, 32, 98, 111, 116, ++ 116, 111, 109, 32, 104, 97, 115, 32, 98, 101, 101, 110, 32, 111, 118, ++ 101, 114, 119, 114, 105, 116, 116, 101, 110, 10, 0, 9, 83, 116, 97, ++ 99, 107, 32, 98, 111, 116, 116, 111, 109, 58, 32, 48, 120, 37, 112, ++ 44, 32, 108, 119, 109, 58, 32, 48, 120, 37, 112, 44, 32, 99, 117, 114, ++ 114, 58, 32, 48, 120, 37, 112, 44, 32, 116, 111, 112, 58, 32, 48, 120, ++ 37, 112, 10, 0, 9, 70, 114, 101, 101, 32, 115, 116, 97, 99, 107, 58, ++ 32, 48, 120, 37, 120, 40, 37, 100, 41, 32, 108, 119, 109, 58, 32, 48, ++ 120, 37, 120, 40, 37, 100, 41, 10, 0, 9, 73, 110, 117, 115, 101, 32, ++ 115, 116, 97, 99, 107, 58, 32, 48, 120, 37, 120, 40, 37, 100, 41, 32, ++ 104, 119, 109, 58, 32, 48, 120, 37, 120, 40, 37, 100, 41, 10, 0, 9, ++ 73, 110, 32, 117, 115, 101, 32, 112, 111, 111, 108, 32, 37, 100, 40, ++ 37, 100, 41, 58, 32, 37, 100, 40, 37, 100, 75, 41, 44, 32, 119, 47, ++ 111, 104, 58, 32, 37, 100, 40, 37, 100, 75, 41, 10, 0, 9, 73, 110, 32, ++ 117, 115, 101, 32, 45, 32, 112, 111, 111, 108, 58, 32, 37, 100, 40, ++ 37, 100, 75, 41, 44, 32, 119, 47, 111, 104, 58, 32, 37, 100, 40, 37, ++ 100, 75, 41, 10, 0, 9, 80, 107, 116, 73, 100, 32, 84, 111, 116, 97, ++ 108, 58, 32, 37, 100, 44, 32, 70, 114, 101, 101, 58, 32, 37, 100, 44, ++ 32, 70, 97, 105, 108, 101, 100, 58, 32, 37, 100, 10, 0, 109, 119, 0, ++ 109, 100, 0, 85, 78, 73, 77, 80, 76, 58, 32, 114, 97, 61, 37, 112, 10, ++ 0, 84, 67, 65, 77, 58, 32, 37, 100, 32, 117, 115, 101, 100, 58, 32, ++ 37, 100, 32, 101, 120, 99, 101, 101, 100, 58, 37, 100, 10, 0, 10, 70, ++ 87, 73, 68, 32, 48, 49, 45, 37, 120, 10, 102, 108, 97, 103, 115, 32, ++ 37, 120, 10, 0, 10, 84, 82, 65, 80, 32, 37, 120, 40, 37, 120, 41, 58, ++ 32, 112, 99, 32, 37, 120, 44, 32, 108, 114, 32, 37, 120, 44, 32, 115, ++ 112, 32, 37, 120, 44, 32, 99, 112, 115, 114, 32, 37, 120, 44, 32, 115, ++ 112, 115, 114, 32, 37, 120, 10, 0, 32, 32, 114, 48, 32, 37, 120, 44, ++ 32, 114, 49, 32, 37, 120, 44, 32, 114, 50, 32, 37, 120, 44, 32, 114, ++ 51, 32, 37, 120, 44, 32, 114, 52, 32, 37, 120, 44, 32, 114, 53, 32, ++ 37, 120, 44, 32, 114, 54, 32, 37, 120, 10, 0, 32, 32, 114, 55, 32, 37, ++ 120, 44, 32, 114, 56, 32, 37, 120, 44, 32, 114, 57, 32, 37, 120, 44, ++ 32, 114, 49, 48, 32, 37, 120, 44, 32, 114, 49, 49, 32, 37, 120, 44, ++ 32, 114, 49, 50, 32, 37, 120, 10, 0, 10, 32, 32, 32, 115, 112, 43, 48, ++ 32, 37, 48, 56, 120, 32, 37, 48, 56, 120, 32, 37, 48, 56, 120, 32, 37, ++ 48, 56, 120, 10, 0, 32, 32, 115, 112, 43, 49, 48, 32, 37, 48, 56, 120, ++ 32, 37, 48, 56, 120, 32, 37, 48, 56, 120, 32, 37, 48, 56, 120, 10, 10, ++ 0, 115, 112, 43, 37, 120, 32, 37, 48, 56, 120, 10, 0, 104, 110, 100, ++ 97, 114, 109, 95, 97, 114, 109, 114, 32, 97, 100, 100, 114, 58, 32, ++ 48, 120, 37, 120, 44, 32, 99, 114, 52, 95, 105, 100, 120, 58, 32, 37, ++ 100, 10, 0, 98, 117, 115, 115, 116, 97, 116, 115, 0, 65, 88, 73, 32, ++ 115, 108, 97, 118, 101, 32, 101, 114, 114, 111, 114, 0, 65, 88, 73, ++ 32, 116, 105, 109, 101, 111, 117, 116, 0, 65, 88, 73, 32, 100, 101, ++ 99, 111, 100, 101, 32, 101, 114, 114, 111, 114, 0, 9, 32, 101, 114, ++ 114, 108, 111, 103, 58, 32, 108, 111, 32, 48, 120, 37, 48, 56, 120, ++ 44, 32, 104, 105, 32, 48, 120, 37, 48, 56, 120, 44, 32, 105, 100, 32, ++ 48, 120, 37, 48, 56, 120, 44, 32, 102, 108, 97, 103, 115, 32, 48, 120, ++ 37, 48, 56, 120, 0, 44, 32, 115, 116, 97, 116, 117, 115, 32, 48, 120, ++ 37, 48, 56, 120, 10, 0, 0, 0, 0, 0, 0, 0, 128, 0, 0, 0, 64, 0, 0, 0, ++ 32, 0, 0, 0, 16, 0, 0, 0, 8, 0, 0, 0, 4, 0, 0, 0, 2, 0, 0, 0, 1, 0, ++ 0, 128, 0, 0, 0, 64, 0, 0, 0, 32, 0, 0, 0, 16, 0, 0, 0, 8, 0, 0, 0, ++ 4, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0, 128, 0, 0, 0, 64, 0, 0, 0, 32, 0, 0, ++ 0, 16, 0, 0, 0, 8, 0, 0, 0, 4, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0, 128, 0, ++ 0, 0, 64, 0, 0, 0, 32, 0, 0, 0, 16, 0, 0, 0, 8, 0, 0, 0, 4, 0, 0, 0, ++ 2, 0, 0, 0, 1, 0, 0, 0, 112, 97, 37, 100, 61, 48, 120, 37, 37, 120, ++ 0, 112, 100, 37, 100, 61, 48, 120, 37, 37, 120, 0, 112, 100, 104, 37, ++ 100, 61, 48, 120, 37, 37, 120, 0, 112, 100, 108, 37, 100, 61, 48, 120, ++ 37, 37, 120, 0, 103, 99, 114, 37, 100, 61, 48, 120, 37, 37, 120, 0, ++ 37, 48, 50, 88, 37, 48, 50, 88, 37, 48, 50, 88, 37, 48, 50, 88, 45, ++ 37, 48, 50, 88, 37, 48, 50, 88, 45, 37, 48, 50, 88, 37, 48, 50, 88, ++ 45, 37, 48, 50, 88, 37, 48, 50, 88, 45, 37, 48, 50, 88, 37, 48, 50, ++ 88, 37, 48, 50, 88, 37, 48, 50, 88, 37, 48, 50, 88, 37, 48, 50, 88, ++ 0, 85, 110, 100, 101, 102, 105, 110, 101, 100, 32, 101, 114, 114, 111, ++ 114, 32, 37, 100, 0, 32, 32, 37, 48, 52, 120, 58, 32, 0, 0, 1, 0, 2, ++ 0, 4, 0, 4, 0, 1, 0, 0, 0, 0, 0, 16, 0, 32, 0, 1, 0, 0, 1, 0, 0, 96, ++ 1, 4, 0, 5, 0, 1, 3, 100, 1, 4, 0, 0, 0, 39, 0, 36, 1, 4, 0, 4, 0, 0, ++ 0, 40, 1, 4, 0, 0, 0, 0, 0, 44, 1, 4, 0, 0, 0, 0, 0, 48, 1, 4, 0, 0, ++ 0, 0, 0, 52, 1, 4, 0, 10, 4, 112, 0, 52, 1, 4, 0, 239, 190, 212, 0, ++ 52, 1, 4, 0, 5, 0, 0, 255, 52, 1, 4, 0, 1, 255, 2, 255, 48, 1, 4, 0, ++ 24, 0, 0, 0, 52, 1, 4, 0, 10, 4, 224, 0, 52, 1, 4, 0, 239, 190, 72, ++ 0, 52, 1, 4, 0, 5, 0, 0, 255, 52, 1, 4, 0, 1, 255, 2, 255, 52, 1, 4, ++ 0, 0, 16, 24, 1, 52, 1, 4, 0, 2, 3, 0, 16, 52, 1, 4, 0, 24, 241, 242, ++ 243, 52, 1, 4, 0, 187, 204, 0, 0, 48, 1, 4, 0, 56, 0, 0, 0, 52, 1, 4, ++ 0, 0, 0, 0, 0, 48, 1, 4, 0, 88, 0, 0, 0, 52, 1, 4, 0, 0, 0, 0, 0, 48, ++ 1, 4, 0, 56, 0, 0, 0, 52, 1, 4, 0, 15, 32, 0, 7, 52, 1, 4, 0, 0, 0, ++ 148, 0, 52, 1, 4, 0, 0, 0, 0, 144, 52, 1, 4, 0, 116, 117, 118, 119, ++ 52, 1, 4, 0, 0, 0, 0, 0, 52, 1, 4, 0, 0, 0, 5, 0, 52, 1, 4, 0, 255, ++ 255, 255, 255, 48, 1, 4, 0, 104, 2, 0, 0, 52, 1, 4, 0, 110, 132, 51, ++ 0, 52, 1, 4, 0, 220, 186, 80, 0, 52, 1, 4, 0, 212, 0, 0, 171, 52, 1, ++ 4, 0, 186, 218, 186, 218, 52, 1, 4, 0, 0, 16, 24, 241, 52, 1, 4, 0, ++ 242, 243, 0, 16, 52, 1, 4, 0, 24, 241, 242, 243, 52, 1, 4, 0, 16, 0, ++ 0, 0, 52, 1, 4, 0, 0, 0, 0, 0, 52, 1, 4, 0, 0, 0, 10, 0, 52, 1, 4, 0, ++ 1, 0, 0, 14, 52, 1, 4, 0, 66, 82, 67, 77, 52, 1, 4, 0, 95, 84, 69, 83, ++ 52, 1, 4, 0, 84, 95, 83, 83, 52, 1, 4, 0, 73, 68, 1, 4, 52, 1, 4, 0, ++ 130, 132, 139, 150, 52, 1, 4, 0, 3, 1, 1, 6, 52, 1, 4, 0, 2, 0, 0, 0, ++ 48, 1, 4, 0, 104, 0, 0, 0, 52, 1, 4, 0, 10, 4, 40, 2, 52, 1, 4, 0, 220, ++ 186, 128, 0, 52, 1, 4, 0, 0, 0, 255, 255, 52, 1, 4, 0, 255, 255, 255, ++ 255, 52, 1, 4, 0, 0, 16, 24, 241, 52, 1, 4, 0, 242, 243, 0, 16, 52, ++ 1, 4, 0, 24, 241, 242, 243, 52, 1, 4, 0, 208, 175, 0, 0, 52, 1, 4, 0, ++ 0, 0, 0, 0, 52, 1, 4, 0, 0, 0, 0, 1, 52, 1, 4, 0, 2, 0, 0, 14, 52, 1, ++ 4, 0, 66, 82, 67, 77, 52, 1, 4, 0, 95, 84, 69, 83, 52, 1, 4, 0, 84, ++ 95, 83, 83, 52, 1, 4, 0, 73, 68, 1, 4, 52, 1, 4, 0, 130, 132, 139, 150, ++ 52, 1, 4, 0, 3, 1, 1, 6, 52, 1, 4, 0, 2, 1, 0, 0, 48, 1, 4, 0, 104, ++ 4, 0, 0, 52, 1, 4, 0, 10, 4, 40, 2, 52, 1, 4, 0, 220, 186, 128, 0, 52, ++ 1, 4, 0, 0, 0, 255, 255, 52, 1, 4, 0, 255, 255, 255, 255, 52, 1, 4, ++ 0, 0, 16, 24, 241, 52, 1, 4, 0, 242, 243, 0, 16, 52, 1, 4, 0, 24, 241, ++ 242, 243, 52, 1, 4, 0, 208, 175, 0, 0, 52, 1, 4, 0, 0, 0, 0, 0, 52, ++ 1, 4, 0, 0, 0, 0, 1, 52, 1, 4, 0, 2, 0, 0, 14, 52, 1, 4, 0, 66, 82, ++ 67, 77, 52, 1, 4, 0, 95, 84, 69, 83, 52, 1, 4, 0, 84, 95, 83, 83, 52, ++ 1, 4, 0, 73, 68, 1, 4, 52, 1, 4, 0, 130, 132, 139, 150, 52, 1, 4, 0, ++ 3, 1, 1, 6, 52, 1, 4, 0, 2, 1, 0, 0, 0, 1, 4, 0, 0, 0, 0, 1, 144, 4, ++ 2, 0, 0, 0, 0, 0, 160, 4, 2, 0, 241, 243, 0, 0, 176, 4, 2, 0, 239, 253, ++ 0, 0, 168, 4, 2, 0, 255, 255, 0, 0, 168, 4, 2, 0, 0, 0, 0, 0, 162, 4, ++ 2, 0, 1, 0, 0, 0, 178, 4, 2, 0, 251, 255, 0, 0, 170, 4, 2, 0, 255, 255, ++ 0, 0, 170, 4, 2, 0, 0, 0, 0, 0, 164, 4, 2, 0, 207, 26, 0, 0, 172, 4, ++ 2, 0, 0, 0, 0, 0, 188, 4, 2, 0, 0, 0, 0, 0, 166, 4, 2, 0, 215, 2, 0, ++ 0, 182, 4, 2, 0, 255, 253, 0, 0, 174, 4, 2, 0, 255, 255, 0, 0, 6, 4, ++ 2, 0, 1, 0, 0, 0, 6, 4, 2, 0, 0, 0, 0, 0, 12, 4, 2, 0, 24, 0, 0, 0, ++ 6, 4, 2, 0, 0, 0, 0, 0, 72, 4, 2, 0, 0, 12, 0, 0, 2, 4, 2, 0, 32, 6, ++ 0, 0, 2, 5, 2, 0, 0, 0, 0, 0, 0, 5, 2, 0, 0, 64, 0, 0, 2, 5, 2, 0, 4, ++ 0, 0, 0, 0, 5, 2, 0, 0, 64, 0, 0, 2, 5, 2, 0, 8, 0, 0, 0, 0, 5, 2, 0, ++ 0, 64, 0, 0, 2, 5, 2, 0, 12, 0, 0, 0, 0, 5, 2, 0, 0, 64, 0, 0, 2, 5, ++ 2, 0, 192, 0, 0, 0, 128, 5, 2, 0, 255, 255, 0, 0, 130, 5, 2, 0, 255, ++ 255, 0, 0, 132, 5, 2, 0, 255, 255, 0, 0, 134, 5, 2, 0, 255, 255, 0, ++ 0, 136, 5, 2, 0, 255, 255, 0, 0, 138, 5, 2, 0, 255, 255, 0, 0, 140, ++ 5, 2, 0, 255, 255, 0, 0, 142, 5, 2, 0, 255, 255, 0, 0, 144, 5, 2, 0, ++ 255, 255, 0, 0, 146, 5, 2, 0, 255, 255, 0, 0, 148, 5, 2, 0, 255, 255, ++ 0, 0, 150, 5, 2, 0, 255, 255, 0, 0, 152, 5, 2, 0, 255, 255, 0, 0, 154, ++ 5, 2, 0, 255, 255, 0, 0, 158, 5, 2, 0, 255, 255, 0, 0, 160, 5, 2, 0, ++ 255, 255, 0, 0, 156, 5, 2, 0, 240, 255, 0, 0, 64, 5, 2, 0, 0, 128, 0, ++ 0, 32, 5, 2, 0, 6, 15, 0, 0, 64, 5, 2, 0, 0, 128, 0, 0, 64, 5, 2, 0, ++ 0, 129, 0, 0, 32, 5, 2, 0, 0, 255, 0, 0, 44, 5, 2, 0, 1, 1, 0, 0, 64, ++ 5, 2, 0, 0, 129, 0, 0, 64, 5, 2, 0, 0, 130, 0, 0, 32, 5, 2, 0, 30, 40, ++ 0, 0, 44, 5, 2, 0, 0, 0, 0, 0, 64, 5, 2, 0, 0, 130, 0, 0, 64, 5, 2, ++ 0, 0, 131, 0, 0, 32, 5, 2, 0, 41, 49, 0, 0, 64, 5, 2, 0, 0, 131, 0, ++ 0, 64, 5, 2, 0, 0, 132, 0, 0, 32, 5, 2, 0, 50, 63, 0, 0, 64, 5, 2, 0, ++ 0, 132, 0, 0, 64, 5, 2, 0, 0, 133, 0, 0, 32, 5, 2, 0, 64, 65, 0, 0, ++ 64, 5, 2, 0, 0, 133, 0, 0, 18, 6, 2, 0, 1, 0, 0, 0, 46, 6, 2, 0, 205, ++ 204, 0, 0, 48, 6, 2, 0, 12, 0, 0, 0, 0, 6, 2, 0, 4, 128, 0, 0, 150, ++ 6, 2, 0, 8, 0, 0, 0, 154, 6, 2, 0, 228, 0, 0, 0, 136, 6, 2, 0, 0, 0, ++ 0, 0, 156, 6, 2, 0, 2, 0, 0, 0, 136, 6, 2, 0, 0, 16, 0, 0, 156, 6, 2, ++ 0, 2, 0, 0, 0, 136, 6, 2, 0, 0, 32, 0, 0, 156, 6, 2, 0, 2, 0, 0, 0, ++ 136, 6, 2, 0, 0, 48, 0, 0, 156, 6, 2, 0, 2, 0, 0, 0, 136, 6, 2, 0, 11, ++ 15, 0, 0, 158, 6, 2, 0, 7, 0, 0, 0, 16, 5, 2, 0, 11, 0, 0, 0, 80, 4, ++ 2, 0, 1, 78, 0, 0, 82, 4, 2, 0, 91, 1, 0, 0, 228, 4, 2, 0, 144, 0, 0, ++ 0, 4, 4, 2, 0, 180, 0, 0, 0, 84, 5, 2, 0, 255, 175, 0, 0, 254, 4, 2, ++ 0, 0, 0, 0, 0, 94, 5, 2, 0, 0, 16, 0, 0, 96, 1, 4, 0, 4, 0, 1, 3, 100, ++ 1, 4, 0, 0, 0, 0, 0, 100, 1, 4, 0, 180, 0, 0, 0, 100, 1, 4, 0, 71, 0, ++ 71, 0, 100, 1, 4, 0, 0, 0, 100, 0, 100, 1, 4, 0, 48, 9, 64, 0, 96, 1, ++ 4, 0, 13, 0, 1, 3, 100, 1, 4, 0, 2, 0, 2, 0, 100, 1, 4, 0, 1, 0, 128, ++ 0, 100, 1, 4, 0, 5, 0, 0, 0, 100, 1, 4, 0, 0, 0, 128, 0, 100, 1, 4, ++ 0, 100, 0, 100, 0, 100, 1, 4, 0, 14, 0, 71, 0, 100, 1, 4, 0, 0, 5, 0, ++ 0, 96, 1, 4, 0, 21, 0, 1, 3, 100, 1, 4, 0, 64, 0, 60, 8, 100, 1, 4, ++ 0, 0, 0, 7, 0, 100, 1, 4, 0, 10, 0, 0, 0, 96, 1, 4, 0, 26, 0, 1, 3, ++ 100, 1, 4, 0, 0, 192, 0, 0, 96, 1, 4, 0, 29, 0, 1, 3, 100, 1, 4, 0, ++ 16, 39, 0, 0, 96, 1, 4, 0, 31, 0, 1, 3, 100, 1, 4, 0, 0, 0, 19, 12, ++ 100, 1, 4, 0, 6, 0, 16, 39, 96, 1, 4, 0, 37, 0, 1, 3, 100, 1, 4, 0, ++ 0, 0, 50, 0, 96, 1, 4, 0, 40, 0, 1, 3, 100, 1, 4, 0, 0, 0, 76, 10, 100, ++ 1, 4, 0, 0, 0, 63, 1, 100, 1, 4, 0, 255, 255, 0, 4, 100, 1, 4, 0, 70, ++ 4, 30, 7, 100, 1, 4, 0, 2, 0, 236, 9, 96, 1, 4, 0, 46, 0, 1, 3, 100, ++ 1, 4, 0, 0, 0, 0, 128, 96, 1, 4, 0, 146, 1, 1, 3, 100, 1, 4, 0, 100, ++ 4, 0, 0, 100, 1, 4, 0, 0, 0, 64, 0, 100, 1, 4, 0, 150, 7, 0, 0, 96, ++ 1, 4, 0, 151, 1, 1, 3, 100, 1, 4, 0, 26, 8, 0, 0, 96, 1, 4, 0, 191, ++ 1, 1, 3, 100, 1, 4, 0, 0, 0, 5, 0, 96, 1, 4, 0, 8, 4, 1, 3, 100, 1, ++ 4, 0, 7, 2, 0, 0, 96, 1, 4, 0, 16, 4, 1, 3, 100, 1, 4, 0, 0, 0, 1, 0, ++ 96, 1, 4, 0, 19, 12, 1, 0, 100, 1, 2, 0, 255, 255, 0, 0, 96, 1, 4, 0, ++ 20, 12, 1, 0, 100, 1, 2, 0, 255, 255, 0, 0, 96, 1, 4, 0, 26, 0, 1, 3, ++ 100, 1, 4, 0, 0, 0, 22, 12, 96, 1, 4, 0, 35, 0, 1, 3, 100, 1, 4, 0, ++ 0, 0, 166, 7, 100, 1, 4, 0, 0, 0, 162, 10, 96, 1, 4, 0, 38, 0, 1, 3, ++ 100, 1, 4, 0, 10, 14, 11, 9, 100, 1, 4, 0, 14, 2, 0, 0, 96, 1, 4, 0, ++ 50, 0, 1, 3, 100, 1, 4, 0, 0, 0, 136, 11, 100, 1, 4, 0, 0, 0, 160, 4, ++ 100, 1, 4, 0, 0, 0, 124, 6, 96, 1, 4, 0, 88, 0, 1, 3, 100, 1, 4, 0, ++ 66, 82, 67, 77, 100, 1, 4, 0, 95, 84, 69, 83, 100, 1, 4, 0, 84, 95, ++ 83, 83, 100, 1, 4, 0, 73, 68, 0, 0, 96, 1, 4, 0, 96, 0, 1, 3, 100, 1, ++ 4, 0, 57, 0, 0, 0, 100, 1, 4, 0, 80, 0, 0, 0, 100, 1, 4, 0, 192, 0, ++ 0, 0, 96, 1, 4, 0, 112, 0, 1, 3, 100, 1, 4, 0, 190, 3, 190, 3, 100, ++ 1, 4, 0, 190, 3, 190, 3, 100, 1, 4, 0, 190, 3, 190, 3, 100, 1, 4, 0, ++ 190, 3, 190, 3, 100, 1, 4, 0, 0, 4, 234, 3, 100, 1, 4, 0, 212, 3, 190, ++ 3, 100, 1, 4, 0, 11, 4, 245, 3, 100, 1, 4, 0, 223, 3, 201, 3, 100, 1, ++ 4, 0, 190, 3, 190, 3, 100, 1, 4, 0, 190, 3, 190, 3, 100, 1, 4, 0, 190, ++ 3, 190, 3, 100, 1, 4, 0, 190, 3, 190, 3, 100, 1, 4, 0, 0, 4, 234, 3, ++ 100, 1, 4, 0, 212, 3, 190, 3, 100, 1, 4, 0, 11, 4, 245, 3, 100, 1, 4, ++ 0, 223, 3, 201, 3, 100, 1, 4, 0, 22, 4, 22, 4, 100, 1, 4, 0, 22, 4, ++ 22, 4, 100, 1, 4, 0, 34, 4, 22, 4, 100, 1, 4, 0, 22, 4, 46, 4, 100, ++ 1, 4, 0, 22, 4, 22, 4, 100, 1, 4, 0, 22, 4, 22, 4, 100, 1, 4, 0, 22, ++ 4, 22, 4, 100, 1, 4, 0, 58, 4, 22, 4, 100, 1, 4, 0, 22, 4, 22, 4, 100, ++ 1, 4, 0, 22, 4, 22, 4, 100, 1, 4, 0, 34, 4, 22, 4, 100, 1, 4, 0, 22, ++ 4, 46, 4, 100, 1, 4, 0, 22, 4, 22, 4, 100, 1, 4, 0, 22, 4, 22, 4, 100, ++ 1, 4, 0, 22, 4, 22, 4, 100, 1, 4, 0, 58, 4, 22, 4, 100, 1, 4, 0, 0, ++ 0, 31, 0, 100, 1, 4, 0, 255, 3, 31, 0, 100, 1, 4, 0, 2, 0, 0, 0, 100, ++ 1, 4, 0, 2, 0, 0, 0, 96, 1, 4, 0, 152, 0, 1, 3, 100, 1, 4, 0, 0, 0, ++ 31, 0, 100, 1, 4, 0, 255, 3, 31, 0, 100, 1, 4, 0, 1, 0, 0, 0, 100, 1, ++ 4, 0, 1, 0, 0, 0, 96, 1, 4, 0, 160, 0, 1, 3, 100, 1, 4, 0, 0, 0, 31, ++ 0, 100, 1, 4, 0, 255, 3, 31, 0, 100, 1, 4, 0, 1, 0, 0, 0, 100, 1, 4, ++ 0, 1, 0, 0, 0, 96, 1, 4, 0, 168, 0, 1, 3, 100, 1, 4, 0, 0, 0, 31, 0, ++ 100, 1, 4, 0, 255, 3, 31, 0, 100, 1, 4, 0, 1, 0, 0, 0, 100, 1, 4, 0, ++ 1, 0, 0, 0, 96, 1, 4, 0, 192, 0, 1, 3, 100, 1, 4, 0, 55, 36, 55, 36, ++ 100, 1, 4, 0, 55, 36, 55, 36, 96, 1, 4, 0, 186, 1, 1, 3, 100, 1, 4, ++ 0, 1, 0, 7, 2, 100, 1, 4, 0, 7, 2, 7, 3, 100, 1, 4, 0, 7, 0, 0, 0, 96, ++ 1, 4, 0, 223, 1, 1, 3, 100, 1, 4, 0, 32, 0, 203, 1, 100, 1, 4, 0, 0, ++ 0, 84, 0, 100, 1, 4, 0, 0, 0, 171, 8, 100, 1, 4, 0, 0, 0, 16, 4, 100, ++ 1, 4, 0, 132, 0, 2, 0, 100, 1, 4, 0, 0, 0, 20, 0, 100, 1, 4, 0, 207, ++ 1, 2, 0, 100, 1, 4, 0, 68, 0, 0, 0, 100, 1, 4, 0, 175, 8, 2, 0, 100, ++ 1, 4, 0, 16, 4, 100, 0, 100, 1, 4, 0, 2, 2, 0, 0, 100, 1, 4, 0, 16, ++ 0, 202, 1, 100, 1, 4, 0, 2, 0, 60, 0, 100, 1, 4, 0, 0, 0, 170, 8, 100, ++ 1, 4, 0, 2, 0, 16, 4, 100, 1, 4, 0, 84, 0, 2, 8, 100, 1, 4, 0, 0, 0, ++ 8, 0, 100, 1, 4, 0, 206, 1, 0, 0, 100, 1, 4, 0, 52, 0, 0, 0, 100, 1, ++ 4, 0, 174, 8, 0, 0, 100, 1, 4, 0, 16, 4, 68, 0, 100, 1, 4, 0, 2, 10, ++ 0, 0, 100, 1, 4, 0, 8, 0, 201, 1, 100, 1, 4, 0, 2, 0, 48, 0, 100, 1, ++ 4, 0, 0, 0, 169, 8, 100, 1, 4, 0, 2, 0, 16, 4, 100, 1, 4, 0, 60, 0, ++ 2, 16, 100, 1, 4, 0, 0, 0, 4, 0, 100, 1, 4, 0, 205, 1, 0, 0, 100, 1, ++ 4, 0, 44, 0, 0, 0, 100, 1, 4, 0, 173, 8, 0, 0, 100, 1, 4, 0, 16, 4, ++ 52, 0, 100, 1, 4, 0, 2, 18, 0, 0, 100, 1, 4, 0, 4, 0, 200, 1, 100, 1, ++ 4, 0, 0, 0, 44, 0, 100, 1, 4, 0, 0, 0, 168, 8, 100, 1, 4, 0, 0, 0, 16, ++ 4, 100, 1, 4, 0, 48, 0, 2, 25, 100, 1, 4, 0, 0, 0, 0, 0, 100, 1, 4, ++ 0, 204, 1, 2, 0, 100, 1, 4, 0, 44, 0, 0, 0, 100, 1, 4, 0, 172, 8, 2, ++ 0, 100, 1, 4, 0, 16, 4, 48, 0, 100, 1, 4, 0, 2, 26, 0, 0, 100, 1, 4, ++ 0, 192, 0, 10, 4, 100, 1, 4, 0, 112, 0, 0, 0, 100, 1, 4, 0, 58, 1, 10, ++ 4, 100, 1, 4, 0, 40, 2, 44, 192, 100, 1, 4, 0, 242, 2, 10, 4, 100, 1, ++ 4, 0, 0, 0, 0, 1, 100, 1, 4, 0, 96, 0, 20, 4, 100, 1, 4, 0, 56, 0, 0, ++ 0, 100, 1, 4, 0, 2, 1, 20, 4, 100, 1, 4, 0, 20, 1, 44, 192, 100, 1, ++ 4, 0, 222, 1, 20, 4, 100, 1, 4, 0, 0, 0, 128, 0, 100, 1, 4, 0, 34, 0, ++ 55, 4, 100, 1, 4, 0, 21, 0, 0, 0, 100, 1, 4, 0, 223, 0, 55, 4, 100, ++ 1, 4, 0, 101, 0, 44, 192, 100, 1, 4, 0, 46, 1, 55, 4, 100, 1, 4, 0, ++ 0, 0, 47, 0, 100, 1, 4, 0, 17, 0, 110, 132, 100, 1, 4, 0, 11, 0, 0, ++ 0, 100, 1, 4, 0, 212, 0, 110, 132, 100, 1, 4, 0, 51, 0, 44, 192, 100, ++ 1, 4, 0, 252, 0, 110, 132, 100, 1, 4, 0, 0, 0, 24, 0, 100, 1, 4, 0, ++ 2, 0, 138, 157, 100, 1, 4, 0, 251, 0, 2, 8, 100, 1, 4, 0, 197, 78, 250, ++ 0, 100, 1, 4, 0, 2, 10, 131, 52, 100, 1, 4, 0, 254, 0, 2, 16, 100, 1, ++ 4, 0, 98, 39, 249, 0, 100, 1, 4, 0, 2, 18, 66, 26, 100, 1, 4, 0, 253, ++ 0, 2, 25, 100, 1, 4, 0, 177, 19, 248, 0, 100, 1, 4, 0, 2, 26, 129, 17, ++ 100, 1, 4, 0, 252, 0, 2, 28, 100, 1, 4, 0, 193, 15, 252, 0, 100, 1, ++ 4, 0, 0, 0, 193, 15, 100, 1, 4, 0, 252, 0, 0, 0, 100, 1, 4, 0, 193, ++ 15, 252, 0, 96, 1, 4, 0, 80, 2, 1, 3, 100, 1, 4, 0, 0, 0, 0, 0, 100, ++ 1, 4, 0, 1, 0, 113, 20, 100, 1, 4, 0, 4, 2, 0, 0, 96, 1, 4, 0, 84, 2, ++ 1, 3, 100, 1, 4, 0, 1, 0, 0, 0, 100, 1, 4, 0, 1, 0, 113, 20, 100, 1, ++ 4, 0, 4, 2, 0, 0, 96, 1, 4, 0, 88, 2, 1, 3, 100, 1, 4, 0, 2, 0, 0, 0, ++ 100, 1, 4, 0, 1, 0, 113, 20, 100, 1, 4, 0, 4, 2, 0, 0, 96, 1, 4, 0, ++ 92, 2, 1, 3, 100, 1, 4, 0, 3, 0, 0, 0, 100, 1, 4, 0, 1, 0, 113, 20, ++ 100, 1, 4, 0, 4, 2, 0, 0, 96, 1, 4, 0, 96, 2, 1, 3, 100, 1, 4, 0, 0, ++ 0, 1, 0, 96, 1, 4, 0, 108, 2, 1, 3, 100, 1, 4, 0, 32, 0, 0, 0, 96, 1, ++ 4, 0, 18, 4, 1, 3, 100, 1, 4, 0, 0, 0, 12, 0, 96, 1, 4, 0, 80, 5, 1, ++ 3, 100, 1, 4, 0, 24, 0, 0, 0, 100, 1, 4, 0, 152, 58, 152, 58, 100, 1, ++ 4, 0, 166, 14, 100, 0, 100, 1, 4, 0, 0, 0, 244, 1, 100, 1, 4, 0, 15, ++ 0, 0, 0, 100, 1, 4, 0, 200, 175, 168, 97, 100, 1, 4, 0, 32, 78, 30, ++ 0, 100, 1, 4, 0, 0, 0, 3, 0, 100, 1, 4, 0, 3, 0, 0, 0, 100, 1, 4, 0, ++ 80, 195, 0, 0, 96, 1, 4, 0, 91, 5, 1, 3, 100, 1, 4, 0, 0, 0, 20, 5, ++ 100, 1, 4, 0, 226, 4, 0, 0, 96, 1, 4, 0, 95, 5, 1, 3, 100, 1, 4, 0, ++ 32, 78, 0, 0, 100, 1, 4, 0, 0, 0, 15, 0, 100, 1, 4, 0, 244, 1, 3, 0, ++ 96, 1, 4, 0, 101, 5, 1, 3, 100, 1, 4, 0, 0, 0, 19, 0, 100, 1, 4, 0, ++ 0, 0, 3, 0, 100, 1, 4, 0, 1, 0, 7, 0, 100, 1, 4, 0, 200, 175, 0, 0, ++ 100, 1, 4, 0, 136, 19, 0, 0, 100, 1, 4, 0, 44, 23, 223, 64, 96, 1, 4, ++ 0, 108, 5, 1, 3, 100, 1, 4, 0, 0, 0, 44, 1, 100, 1, 4, 0, 0, 0, 160, ++ 15, 96, 1, 4, 0, 111, 5, 1, 3, 100, 1, 4, 0, 0, 0, 2, 0, 100, 1, 4, ++ 0, 0, 0, 44, 1, 100, 1, 4, 0, 192, 0, 0, 0, 100, 1, 4, 0, 192, 68, 0, ++ 0, 100, 1, 4, 0, 100, 0, 0, 0, 100, 1, 4, 0, 220, 5, 64, 31, 100, 1, ++ 4, 0, 0, 0, 70, 0, 100, 1, 4, 0, 80, 0, 80, 0, 100, 1, 4, 0, 2, 0, 0, ++ 0, 100, 1, 4, 0, 245, 10, 0, 0, 96, 1, 4, 0, 122, 5, 1, 3, 100, 1, 4, ++ 0, 32, 16, 64, 156, 100, 1, 4, 0, 32, 78, 0, 0, 100, 1, 4, 0, 184, 11, ++ 0, 0, 96, 1, 4, 0, 126, 5, 1, 3, 100, 1, 4, 0, 0, 0, 32, 78, 100, 1, ++ 4, 0, 0, 0, 5, 0, 100, 1, 4, 0, 220, 5, 63, 0, 100, 1, 4, 0, 113, 2, ++ 0, 0, 100, 1, 4, 0, 48, 117, 0, 0, 96, 1, 4, 0, 134, 5, 1, 3, 100, 1, ++ 4, 0, 196, 9, 160, 15, 96, 1, 4, 0, 137, 5, 1, 3, 100, 1, 4, 0, 0, 0, ++ 208, 7, 96, 1, 4, 0, 139, 5, 1, 3, 100, 1, 4, 0, 32, 78, 32, 78, 96, ++ 1, 4, 0, 142, 5, 1, 3, 100, 1, 4, 0, 32, 0, 128, 64, 100, 1, 4, 0, 0, ++ 0, 10, 0, 100, 1, 4, 0, 232, 3, 232, 28, 100, 1, 4, 0, 56, 74, 0, 0, ++ 96, 1, 4, 0, 147, 5, 1, 3, 100, 1, 4, 0, 0, 0, 100, 0, 96, 1, 4, 0, ++ 159, 5, 1, 3, 100, 1, 4, 0, 2, 0, 148, 2, 96, 1, 4, 0, 161, 5, 1, 3, ++ 100, 1, 4, 0, 225, 0, 0, 0, 96, 1, 4, 0, 164, 5, 1, 3, 100, 1, 4, 0, ++ 48, 117, 0, 0, 96, 1, 4, 0, 167, 5, 1, 3, 100, 1, 4, 0, 220, 5, 0, 0, ++ 100, 1, 4, 0, 88, 27, 0, 0, 96, 1, 4, 0, 175, 5, 1, 3, 100, 1, 4, 0, ++ 0, 0, 15, 0, 100, 1, 4, 0, 200, 0, 0, 0, 96, 1, 4, 0, 178, 5, 1, 3, ++ 100, 1, 4, 0, 0, 0, 2, 0, 100, 1, 4, 0, 0, 0, 100, 0, 96, 1, 4, 0, 191, ++ 5, 1, 3, 100, 1, 4, 0, 0, 0, 190, 0, 96, 1, 4, 0, 47, 12, 1, 0, 100, ++ 1, 2, 0, 0, 0, 0, 0, 96, 1, 4, 0, 3, 0, 2, 0, 100, 1, 4, 0, 31, 0, 0, ++ 0, 96, 1, 4, 0, 4, 0, 2, 0, 100, 1, 4, 0, 255, 3, 0, 0, 96, 1, 4, 0, ++ 5, 0, 2, 0, 100, 1, 4, 0, 31, 0, 0, 0, 96, 1, 4, 0, 6, 0, 2, 0, 100, ++ 1, 4, 0, 7, 0, 0, 0, 96, 1, 4, 0, 7, 0, 2, 0, 100, 1, 4, 0, 4, 0, 0, ++ 0, 96, 1, 4, 0, 8, 0, 2, 0, 100, 1, 4, 0, 255, 255, 0, 0, 96, 1, 4, ++ 0, 9, 0, 2, 0, 100, 1, 4, 0, 0, 0, 0, 0, 96, 1, 4, 0, 10, 0, 2, 0, 100, ++ 1, 4, 0, 0, 0, 0, 0, 96, 1, 4, 0, 11, 0, 2, 0, 100, 1, 4, 0, 0, 0, 0, ++ 0, 96, 1, 4, 0, 12, 0, 2, 0, 100, 1, 4, 0, 0, 0, 0, 0, 96, 1, 4, 0, ++ 13, 0, 2, 0, 100, 1, 4, 0, 0, 0, 0, 0, 96, 1, 4, 0, 14, 0, 2, 0, 100, ++ 1, 4, 0, 0, 0, 0, 0, 96, 1, 4, 0, 15, 0, 2, 0, 100, 1, 4, 0, 0, 0, 0, ++ 0, 96, 1, 4, 0, 16, 0, 2, 0, 100, 1, 4, 0, 31, 0, 0, 0, 96, 1, 4, 0, ++ 17, 0, 2, 0, 100, 1, 4, 0, 0, 0, 0, 0, 96, 1, 4, 0, 18, 0, 2, 0, 100, ++ 1, 4, 0, 0, 0, 0, 0, 96, 1, 4, 0, 19, 0, 2, 0, 100, 1, 4, 0, 0, 0, 0, ++ 0, 96, 1, 4, 0, 21, 0, 2, 0, 100, 1, 4, 0, 0, 0, 0, 0, 96, 1, 4, 0, ++ 22, 0, 2, 0, 100, 1, 4, 0, 0, 0, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 134, ++ 6, 2, 0, 208, 9, 0, 0, 128, 6, 2, 0, 62, 62, 0, 0, 130, 6, 2, 0, 62, ++ 2, 0, 0, 0, 7, 2, 0, 60, 0, 0, 0, 132, 6, 2, 0, 18, 2, 0, 0, 96, 1, ++ 4, 0, 3, 0, 1, 0, 100, 1, 2, 0, 192, 0, 0, 0, 96, 1, 4, 0, 3, 0, 1, ++ 0, 102, 1, 2, 0, 10, 0, 0, 0, 96, 1, 4, 0, 4, 0, 1, 0, 100, 1, 2, 0, ++ 20, 0, 0, 0, 96, 1, 4, 0, 7, 0, 1, 0, 100, 1, 2, 0, 131, 1, 0, 0, 96, ++ 1, 4, 0, 37, 0, 1, 0, 100, 1, 2, 0, 244, 1, 0, 0, 96, 1, 4, 0, 193, ++ 5, 1, 0, 100, 1, 2, 0, 43, 4, 0, 0, 96, 1, 4, 0, 193, 5, 1, 0, 102, ++ 1, 2, 0, 0, 1, 0, 0, 96, 1, 4, 0, 225, 1, 1, 0, 100, 1, 2, 0, 60, 0, ++ 0, 0, 96, 1, 4, 0, 230, 1, 1, 0, 102, 1, 2, 0, 52, 0, 0, 0, 96, 1, 4, ++ 0, 236, 1, 1, 0, 100, 1, 2, 0, 48, 0, 0, 0, 96, 1, 4, 0, 241, 1, 1, ++ 0, 102, 1, 2, 0, 44, 0, 0, 0, 96, 1, 4, 0, 247, 1, 1, 0, 100, 1, 2, ++ 0, 44, 0, 0, 0, 96, 1, 4, 0, 252, 1, 1, 0, 102, 1, 2, 0, 40, 0, 0, 0, ++ 96, 1, 4, 0, 2, 2, 1, 0, 100, 1, 2, 0, 40, 0, 0, 0, 96, 1, 4, 0, 7, ++ 2, 1, 0, 102, 1, 2, 0, 40, 0, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 121, ++ 113, 128, 0, 245, 117, 128, 0, 153, 118, 128, 0, 149, 117, 128, 0, 113, ++ 120, 128, 0, 33, 119, 128, 0, 133, 120, 128, 0, 153, 120, 128, 0, 165, ++ 117, 128, 0, 185, 117, 128, 0, 41, 159, 0, 0, 193, 120, 128, 0, 153, ++ 116, 128, 0, 93, 120, 128, 0, 247, 158, 0, 0, 173, 155, 0, 0, 47, 154, ++ 0, 0, 115, 154, 0, 0, 205, 115, 128, 0, 41, 116, 128, 0, 181, 115, 128, ++ 0, 53, 119, 128, 0, 157, 114, 128, 0, 73, 117, 128, 0, 41, 117, 128, ++ 0, 129, 117, 128, 0, 187, 153, 0, 0, 25, 117, 128, 0, 37, 158, 0, 0, ++ 81, 160, 0, 0, 215, 157, 0, 0, 201, 157, 0, 0, 29, 155, 0, 0, 33, 154, ++ 0, 0, 197, 113, 128, 0, 209, 113, 128, 0, 249, 112, 128, 0, 121, 155, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 99, 155, 0, 0, 253, 115, 128, ++ 0, 213, 115, 128, 0, 117, 156, 0, 0, 49, 115, 128, 0, 237, 112, 128, ++ 0, 229, 112, 128, 0, 125, 156, 0, 0, 1, 114, 128, 0, 177, 112, 128, ++ 0, 40, 0, 0, 0, 119, 108, 48, 58, 100, 109, 97, 48, 0, 15, 0, 0, 0, ++ 4, 1, 0, 0, 8, 7, 0, 0, 0, 7, 7, 0, 0, 7, 4, 0, 0, 0, 4, 4, 0, 0, 4, ++ 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 177, 8, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 1, 4, 0, 226, ++ 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 6, ++ 0, 0, 221, 200, 141, 0, 4, 4, 4, 4, 4, 1, 4, 0, 226, 4, 0, 8, 10, 0, ++ 0, 0, 106, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 4, 0, 0, 140, 46, 186, ++ 0, 4, 4, 4, 4, 4, 1, 4, 0, 226, 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, ++ 0, 0, 0, 0, 24, 24, 0, 0, 0, 0, 0, 0, 0, 6, 6, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 49, 25, 0, 0, 0, 0, 160, 0, 12, 12, 12, 12, 10, 3, ++ 4, 0, 226, 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 177, 18, 0, 0, 39, 118, 98, 0, 12, 12, 12, 12, 10, 3, 4, 0, 226, ++ 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 177, 12, ++ 0, 0, 20, 67, 253, 0, 12, 12, 12, 12, 10, 3, 4, 0, 226, 4, 0, 8, 10, ++ 0, 0, 0, 106, 16, 0, 0, 224, 46, 1, 1, 1, 80, 0, 0, 0, 0, 0, 0, 200, ++ 50, 2, 1, 1, 73, 0, 0, 137, 157, 216, 0, 64, 56, 3, 1, 1, 66, 0, 0, ++ 170, 170, 170, 0, 0, 60, 4, 1, 1, 62, 0, 0, 0, 0, 128, 0, 72, 63, 5, ++ 1, 1, 59, 0, 0, 208, 94, 66, 0, 160, 65, 6, 1, 1, 57, 0, 0, 73, 146, ++ 36, 0, 0, 75, 7, 1, 1, 50, 0, 0, 0, 0, 0, 0, 88, 77, 8, 1, 1, 48, 0, ++ 0, 7, 31, 124, 0, 32, 78, 9, 1, 1, 48, 0, 0, 0, 0, 0, 0, 192, 93, 10, ++ 1, 1, 40, 0, 0, 0, 0, 0, 0, 168, 97, 11, 1, 1, 38, 0, 0, 102, 102, 102, ++ 0, 144, 101, 12, 1, 1, 36, 0, 0, 196, 78, 236, 0, 48, 117, 13, 1, 1, ++ 32, 0, 0, 0, 0, 0, 0, 64, 131, 14, 1, 1, 28, 0, 0, 36, 73, 146, 0, 24, ++ 146, 15, 2, 1, 51, 0, 0, 249, 62, 86, 0, 0, 150, 16, 2, 1, 50, 0, 0, ++ 0, 0, 0, 0, 64, 156, 17, 2, 1, 48, 0, 0, 0, 0, 0, 0, 128, 187, 18, 2, ++ 1, 40, 0, 0, 0, 0, 0, 0, 32, 203, 19, 2, 1, 36, 0, 0, 196, 78, 236, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 98, 111, 97, 114, 100, 102, 108, ++ 97, 103, 115, 51, 0, 115, 112, 117, 114, 99, 111, 110, 102, 105, 103, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 177, 25, 0, 0, 171, 170, 10, 0, 11, 12, ++ 12, 12, 10, 3, 4, 0, 226, 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 177, 18, 0, 0, 20, 59, 177, 0, 11, 12, 12, 12, 10, ++ 3, 4, 0, 226, 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 49, 13, 0, 0, 122, 5, 52, 0, 11, 12, 12, 12, 10, 3, 4, 0, 226, ++ 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, 0, 0, 0, 0, 18, 16, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 177, 25, 0, 0, 0, 0, 64, 0, 12, 12, 12, ++ 12, 10, 3, 4, 0, 226, 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 177, 18, 0, 0, 255, 136, 216, 0, 12, 12, 12, 12, 10, ++ 3, 4, 0, 226, 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 177, 13, 0, 0, 240, 255, 78, 0, 12, 12, 12, 12, 10, 3, 4, 0, 226, ++ 4, 0, 8, 10, 0, 0, 0, 106, 16, 0, 0, 119, 100, 115, 37, 100, 46, 37, ++ 100, 0, 119, 108, 37, 100, 0, 37, 48, 52, 120, 0, 119, 108, 0, 119, ++ 108, 37, 100, 58, 32, 37, 115, 32, 37, 115, 32, 118, 101, 114, 115, ++ 105, 111, 110, 32, 37, 115, 32, 70, 87, 73, 68, 32, 48, 49, 45, 37, ++ 120, 10, 0, 74, 97, 110, 32, 51, 48, 32, 50, 48, 50, 48, 0, 50, 49, ++ 58, 52, 49, 58, 53, 51, 0, 170, 170, 3, 0, 0, 0, 116, 107, 111, 0, 72, ++ 50, 4, 0, 0, 0, 0, 0, 8, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15, 255, 15, 2, 0, ++ 4, 0, 6, 0, 97, 112, 32, 0, 115, 116, 97, 32, 0, 119, 109, 101, 32, ++ 0, 56, 48, 50, 46, 49, 49, 100, 32, 0, 56, 48, 50, 46, 49, 49, 104, ++ 32, 0, 114, 109, 32, 0, 99, 97, 99, 32, 0, 97, 109, 112, 100, 117, 32, ++ 0, 97, 109, 112, 100, 117, 95, 116, 120, 32, 0, 97, 109, 112, 100, 117, ++ 95, 114, 120, 32, 0, 97, 109, 115, 100, 117, 114, 120, 32, 0, 97, 109, ++ 115, 100, 117, 116, 120, 32, 0, 114, 97, 100, 105, 111, 95, 112, 119, ++ 114, 115, 97, 118, 101, 32, 0, 112, 50, 112, 32, 0, 109, 99, 104, 97, ++ 110, 32, 0, 112, 50, 112, 111, 32, 0, 97, 110, 113, 112, 111, 32, 0, ++ 100, 102, 114, 116, 115, 32, 0, 116, 120, 112, 119, 114, 99, 97, 99, ++ 104, 101, 32, 0, 115, 116, 98, 99, 45, 116, 120, 32, 0, 115, 116, 98, ++ 99, 45, 114, 120, 45, 49, 115, 115, 32, 0, 119, 110, 109, 32, 0, 98, ++ 115, 115, 116, 114, 97, 110, 115, 32, 0, 109, 102, 112, 32, 0, 115, ++ 97, 101, 32, 0, 119, 108, 37, 100, 58, 32, 80, 83, 77, 32, 109, 105, ++ 99, 114, 111, 99, 111, 100, 101, 32, 119, 97, 116, 99, 104, 100, 111, ++ 103, 32, 102, 105, 114, 101, 100, 32, 40, 37, 100, 41, 32, 97, 116, ++ 32, 37, 100, 32, 40, 115, 101, 99, 111, 110, 100, 115, 41, 10, 0, 119, ++ 108, 37, 100, 58, 32, 80, 83, 77, 32, 75, 101, 101, 112, 32, 65, 108, ++ 105, 118, 101, 32, 40, 37, 100, 41, 32, 35, 32, 37, 100, 32, 10, 0, ++ 119, 108, 99, 0, 109, 105, 110, 95, 116, 120, 112, 111, 119, 101, 114, ++ 0, 98, 99, 110, 116, 114, 105, 109, 95, 115, 116, 97, 116, 115, 0, 98, ++ 99, 110, 116, 114, 105, 109, 0, 98, 99, 110, 95, 108, 111, 115, 115, ++ 95, 114, 111, 97, 109, 95, 115, 116, 97, 114, 116, 0, 98, 99, 110, 95, ++ 114, 101, 97, 113, 117, 105, 114, 101, 95, 115, 116, 97, 114, 116, 0, ++ 98, 99, 110, 95, 119, 97, 105, 116, 95, 112, 114, 100, 0, 99, 117, 115, ++ 116, 111, 109, 118, 97, 114, 50, 0, 108, 111, 103, 116, 114, 97, 99, ++ 101, 0, 112, 109, 95, 98, 99, 109, 99, 95, 109, 111, 114, 101, 100, ++ 97, 116, 97, 95, 119, 97, 105, 116, 0, 114, 111, 97, 109, 95, 98, 99, ++ 110, 108, 111, 115, 115, 95, 111, 102, 102, 0, 114, 111, 97, 109, 111, ++ 102, 102, 108, 95, 98, 115, 115, 105, 100, 95, 108, 105, 115, 116, 0, ++ 0, 166, 51, 4, 0, 28, 1, 0, 0, 8, 0, 44, 0, 180, 51, 4, 0, 27, 1, 0, ++ 0, 6, 0, 0, 0, 188, 51, 4, 0, 26, 1, 0, 0, 7, 0, 0, 0, 208, 51, 4, 0, ++ 25, 1, 0, 0, 7, 0, 0, 0, 227, 51, 4, 0, 24, 1, 0, 0, 3, 0, 0, 0, 240, ++ 51, 4, 0, 42, 0, 0, 128, 7, 0, 0, 0, 210, 82, 136, 0, 241, 0, 0, 0, ++ 8, 0, 188, 1, 76, 134, 136, 0, 2, 0, 0, 64, 6, 0, 0, 0, 201, 81, 136, ++ 0, 39, 0, 0, 64, 5, 0, 0, 0, 173, 101, 136, 0, 233, 0, 0, 64, 8, 0, ++ 4, 0, 11, 180, 136, 0, 20, 1, 0, 64, 8, 0, 176, 0, 251, 51, 4, 0, 23, ++ 1, 0, 0, 1, 0, 0, 0, 4, 52, 4, 0, 21, 1, 0, 0, 5, 0, 0, 0, 159, 90, ++ 136, 0, 9, 1, 0, 0, 5, 0, 0, 0, 60, 84, 136, 0, 136, 0, 1, 0, 5, 0, ++ 0, 0, 246, 81, 136, 0, 44, 0, 16, 64, 7, 0, 0, 0, 229, 88, 136, 0, 235, ++ 0, 0, 0, 7, 0, 0, 0, 130, 82, 136, 0, 73, 0, 0, 0, 0, 0, 0, 0, 26, 52, ++ 4, 0, 22, 1, 0, 0, 1, 0, 0, 0, 43, 52, 4, 0, 19, 1, 0, 0, 8, 0, 0, 0, ++ 5, 91, 136, 0, 17, 1, 0, 0, 1, 0, 0, 0, 82, 83, 136, 0, 80, 0, 0, 64, ++ 3, 0, 0, 0, 89, 83, 136, 0, 81, 0, 0, 64, 2, 0, 0, 0, 149, 44, 136, ++ 0, 28, 0, 0, 64, 8, 0, 4, 0, 37, 77, 136, 0, 46, 0, 0, 64, 6, 0, 0, ++ 0, 194, 76, 136, 0, 30, 0, 0, 64, 8, 0, 164, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 49, 49, 100, 0, 0, 0, 76, 93, 136, ++ 0, 0, 0, 0, 0, 8, 0, 0, 0, 96, 93, 136, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 49, 104, 0, 49, 49, 117, 0, 221, ++ 22, 0, 80, 242, 1, 1, 0, 0, 80, 242, 255, 1, 0, 0, 80, 242, 255, 1, ++ 0, 0, 80, 242, 255, 119, 108, 99, 95, 100, 117, 109, 112, 95, 97, 103, ++ 103, 102, 105, 102, 111, 0, 0, 0, 0, 216, 54, 4, 0, 0, 0, 128, 0, 1, ++ 0, 0, 0, 123, 55, 4, 0, 1, 0, 0, 0, 8, 0, 2, 0, 133, 55, 4, 0, 2, 0, ++ 0, 0, 3, 0, 0, 0, 150, 55, 4, 0, 3, 0, 0, 0, 8, 0, 8, 0, 167, 55, 4, ++ 0, 4, 0, 0, 0, 8, 0, 8, 0, 184, 55, 4, 0, 5, 0, 128, 0, 1, 0, 0, 0, ++ 202, 55, 4, 0, 7, 0, 0, 0, 2, 0, 0, 0, 213, 55, 4, 0, 9, 0, 0, 0, 1, ++ 0, 0, 0, 223, 55, 4, 0, 11, 0, 0, 0, 3, 0, 0, 0, 241, 55, 4, 0, 23, ++ 0, 0, 0, 3, 0, 0, 0, 251, 55, 4, 0, 24, 0, 0, 0, 3, 0, 0, 0, 11, 56, ++ 4, 0, 25, 0, 0, 0, 3, 0, 0, 0, 20, 56, 4, 0, 26, 0, 128, 0, 2, 0, 0, ++ 0, 34, 56, 4, 0, 28, 0, 0, 0, 1, 0, 0, 0, 54, 56, 4, 0, 29, 0, 0, 0, ++ 0, 0, 0, 0, 75, 56, 4, 0, 30, 0, 0, 0, 0, 0, 0, 0, 95, 56, 4, 0, 31, ++ 0, 0, 0, 0, 0, 0, 0, 108, 56, 4, 0, 32, 0, 0, 0, 3, 0, 0, 0, 122, 56, ++ 4, 0, 37, 0, 4, 0, 8, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 97, ++ 109, 112, 100, 117, 95, 116, 120, 0, 37, 115, 58, 32, 99, 108, 107, ++ 32, 111, 102, 102, 10, 0, 102, 105, 102, 111, 32, 37, 100, 58, 32, 114, ++ 112, 116, 114, 32, 37, 120, 32, 119, 112, 116, 114, 32, 37, 120, 10, ++ 0, 9, 101, 110, 116, 114, 121, 32, 37, 100, 32, 97, 100, 100, 114, 32, ++ 48, 120, 37, 120, 58, 32, 48, 120, 37, 120, 10, 0, 100, 114, 105, 118, ++ 101, 114, 32, 115, 116, 97, 116, 105, 115, 116, 105, 99, 115, 58, 32, ++ 97, 103, 103, 102, 105, 102, 111, 32, 112, 101, 110, 100, 105, 110, ++ 103, 32, 37, 100, 32, 101, 110, 113, 117, 101, 47, 99, 111, 110, 115, ++ 32, 37, 100, 32, 37, 100, 10, 0, 84, 88, 32, 77, 67, 83, 32, 32, 58, ++ 0, 32, 32, 37, 100, 40, 37, 100, 37, 37, 41, 0, 10, 32, 32, 32, 32, ++ 32, 32, 32, 32, 58, 0, 97, 109, 112, 100, 117, 95, 116, 105, 100, 0, ++ 97, 109, 112, 100, 117, 95, 116, 120, 95, 100, 101, 110, 115, 105, 116, ++ 121, 0, 97, 109, 112, 100, 117, 95, 115, 101, 110, 100, 95, 97, 100, ++ 100, 98, 97, 0, 97, 109, 112, 100, 117, 95, 115, 101, 110, 100, 95, ++ 100, 101, 108, 98, 97, 0, 97, 109, 112, 100, 117, 95, 109, 97, 110, ++ 117, 97, 108, 95, 109, 111, 100, 101, 0, 97, 109, 112, 100, 117, 95, ++ 109, 112, 100, 117, 0, 97, 109, 112, 100, 117, 95, 114, 116, 115, 0, ++ 97, 109, 112, 100, 117, 95, 114, 101, 116, 114, 121, 95, 108, 105, 109, ++ 105, 116, 0, 97, 99, 107, 95, 114, 97, 116, 105, 111, 0, 97, 99, 107, ++ 95, 114, 97, 116, 105, 111, 95, 100, 101, 112, 116, 104, 0, 97, 109, ++ 112, 100, 117, 109, 97, 99, 0, 97, 109, 112, 100, 117, 95, 97, 103, ++ 103, 109, 111, 100, 101, 0, 102, 114, 97, 109, 101, 98, 117, 114, 115, ++ 116, 95, 111, 118, 101, 114, 114, 105, 100, 101, 0, 97, 109, 112, 100, ++ 117, 95, 116, 120, 113, 95, 112, 114, 111, 102, 95, 115, 116, 97, 114, ++ 116, 0, 97, 109, 112, 100, 117, 95, 116, 120, 113, 95, 112, 114, 111, ++ 102, 95, 100, 117, 109, 112, 0, 97, 109, 112, 100, 117, 95, 116, 120, ++ 113, 95, 115, 115, 0, 97, 109, 112, 100, 117, 95, 114, 101, 108, 101, ++ 97, 115, 101, 0, 97, 109, 112, 100, 117, 95, 116, 120, 97, 103, 103, ++ 114, 0, 0, 160, 56, 4, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 97, 109, 112, 100, 117, 95, 99, 108, 101, 97, 114, ++ 95, 100, 117, 109, 112, 0, 82, 88, 32, 77, 67, 83, 32, 32, 58, 0, 0, ++ 148, 107, 136, 0, 4, 0, 0, 0, 7, 0, 0, 0, 136, 107, 136, 0, 3, 0, 0, ++ 0, 5, 0, 0, 0, 135, 106, 136, 0, 12, 0, 128, 0, 1, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 115, 136, 0, 6, 0, 0, 0, 6, 0, 0, 0, ++ 28, 57, 4, 0, 40, 0, 0, 0, 1, 0, 0, 0, 48, 57, 4, 0, 39, 0, 32, 0, 7, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 112, 114, 111, 120, 121, ++ 95, 97, 114, 112, 95, 97, 100, 118, 101, 114, 116, 105, 115, 101, 0, ++ 115, 99, 98, 95, 109, 97, 120, 95, 112, 114, 111, 98, 101, 0, 97, 112, ++ 112, 115, 0, 97, 95, 119, 112, 97, 0, 97, 95, 119, 112, 97, 105, 0, ++ 37, 115, 58, 32, 104, 111, 115, 116, 95, 101, 110, 97, 98, 32, 37, 100, ++ 10, 0, 0, 0, 136, 57, 4, 0, 0, 0, 0, 64, 8, 0, 16, 0, 153, 57, 4, 0, ++ 1, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 105, 110, ++ 116, 101, 114, 102, 97, 99, 101, 95, 99, 114, 101, 97, 116, 101, 0, ++ 105, 110, 116, 101, 114, 102, 97, 99, 101, 95, 114, 101, 109, 111, 118, ++ 101, 0, 98, 116, 99, 0, 0, 0, 220, 57, 4, 0, 3, 0, 0, 0, 7, 0, 0, 0, ++ 235, 57, 4, 0, 2, 0, 128, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 66, 76, 79, 66, 0, 95, 95, 0, 99, 108, 109, 108, 111, 97, 100, ++ 95, 115, 116, 97, 116, 117, 115, 0, 99, 108, 109, 108, 111, 97, 100, ++ 0, 88, 89, 0, 0, 88, 65, 0, 0, 88, 66, 0, 0, 88, 48, 0, 0, 88, 49, 0, ++ 0, 88, 50, 0, 0, 88, 51, 0, 0, 88, 83, 0, 0, 88, 86, 0, 0, 88, 84, 0, ++ 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0, 3, 0, 0, 0, 24, 59, 4, 0, ++ 0, 0, 0, 0, 178, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, ++ 0, 0, 22, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 4, 0, 0, 0, ++ 0, 0, 0, 0, 4, 0, 0, 0, 8, 0, 0, 0, 1, 0, 0, 0, 26, 0, 0, 0, 8, 0, 0, ++ 0, 1, 0, 0, 0, 68, 0, 0, 0, 8, 0, 0, 0, 1, 0, 0, 0, 116, 0, 0, 0, 8, ++ 0, 0, 0, 1, 0, 0, 0, 142, 0, 0, 0, 8, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, ++ 0, 240, 58, 4, 0, 119, 119, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 11, 1, 0, 16, 17, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 1, 0, 0, 0, 8, 0, 0, 0, 2, 0, 0, ++ 0, 12, 0, 0, 0, 3, 0, 0, 0, 38, 62, 8, 102, 142, 8, 151, 159, 8, 0, ++ 0, 0, 32, 60, 4, 0, 12, 60, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 214, 218, ++ 135, 0, 0, 0, 0, 0, 6, 60, 4, 0, 0, 60, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 220, 59, 4, 0, 144, 60, 4, 0, 228, 59, 4, 0, 127, 178, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 236, 59, 4, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 20, 60, 4, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 50, 48, 50, 48, 45, 48, 49, 45, 51, 48, 32, 50, 49, 58, ++ 51, 48, 58, 50, 48, 0, 0, 0, 255, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 35, 110, 0, 0, 0, 255, 255, 240, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 67, 76, 77, 32, 68, 65, 84, 65, 0, 0, 12, 0, 2, 0, ++ 57, 46, 49, 48, 46, 51, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, ++ 46, 50, 57, 46, 52, 0, 0, 0, 0, 40, 60, 4, 0, 36, 59, 4, 0, 67, 108, ++ 109, 73, 109, 112, 111, 114, 116, 58, 32, 49, 46, 51, 54, 46, 51, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 66, 114, 111, 97, 100, 99, 111, ++ 109, 45, 48, 46, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 63, 157, 136, 0, 3, 0, 0, 0, 8, 0, 188, 1, 100, 93, 136, 0, 0, ++ 0, 0, 0, 8, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 99, 110, 116, ++ 114, 121, 0, 100, 117, 109, 112, 95, 105, 110, 102, 111, 0, 10, 37, ++ 115, 58, 45, 45, 45, 45, 45, 45, 10, 0, 90, 56, 4, 0, 0, 0, 0, 64, 8, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, 118, 101, 110, 116, ++ 113, 0, 102, 98, 116, 0, 0, 88, 232, 135, 0, 21, 0, 0, 0, 109, 232, ++ 135, 0, 23, 0, 0, 0, 0, 233, 135, 0, 26, 0, 0, 0, 26, 233, 135, 0, 27, ++ 0, 0, 0, 192, 232, 135, 0, 14, 0, 0, 0, 206, 232, 135, 0, 50, 0, 0, ++ 0, 206, 232, 135, 0, 50, 0, 0, 0, 139, 232, 135, 0, 51, 0, 0, 0, 139, ++ 232, 135, 0, 51, 0, 0, 0, 139, 232, 135, 0, 51, 0, 0, 0, 191, 232, 135, ++ 0, 1, 0, 0, 0, 132, 232, 135, 0, 7, 0, 0, 0, 190, 232, 135, 0, 1, 0, ++ 0, 0, 105, 101, 109, 0, 0, 144, 76, 4, 104, 0, 144, 76, 51, 80, 0, 144, ++ 76, 53, 88, 0, 144, 76, 54, 156, 0, 144, 76, 90, 200, 0, 80, 242, 1, ++ 160, 0, 80, 242, 4, 164, 80, 111, 154, 16, 190, 80, 111, 154, 9, 192, ++ 80, 111, 154, 18, 196, 0, 64, 150, 4, 170, 0, 64, 150, 8, 178, 0, 64, ++ 150, 3, 174, 0, 64, 150, 1, 173, 80, 111, 154, 19, 197, 105, 101, 114, ++ 0, 108, 113, 0, 110, 111, 105, 115, 101, 95, 108, 116, 101, 95, 114, ++ 101, 115, 101, 116, 0, 114, 115, 115, 105, 95, 109, 111, 110, 105, 116, ++ 111, 114, 0, 0, 186, 61, 4, 0, 3, 0, 0, 0, 6, 0, 0, 0, 71, 172, 136, ++ 0, 0, 0, 0, 0, 8, 0, 12, 0, 202, 61, 4, 0, 26, 0, 0, 0, 8, 0, 4, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 206, 175, 136, 0, 14, 0, 0, 0, 7, ++ 0, 0, 0, 0, 176, 136, 0, 18, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 98, 105, 112, 0, 44, 62, 4, 0, 1, 0, 64, 0, 8, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 68, 73, 82, 69, 67, 84, 45, ++ 0, 67, 50, 136, 0, 4, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 45, 0, 167, 144, 26, 0, 71, 9, 14, 0, 1, 32, 7, 0, 139, ++ 147, 3, 0, 56, 202, 1, 0, 42, 229, 0, 0, 151, 114, 0, 0, 76, 57, 0, ++ 0, 166, 28, 0, 0, 83, 14, 0, 0, 41, 7, 0, 0, 149, 3, 0, 0, 202, 1, 0, ++ 0, 229, 0, 0, 0, 115, 0, 0, 0, 57, 0, 0, 0, 29, 0, 0, 0, 1, 0, 108, ++ 9, 2, 0, 113, 9, 3, 0, 118, 9, 4, 0, 123, 9, 5, 0, 128, 9, 6, 0, 133, ++ 9, 7, 0, 138, 9, 8, 0, 143, 9, 9, 0, 148, 9, 10, 0, 153, 9, 11, 0, 158, ++ 9, 12, 0, 163, 9, 13, 0, 168, 9, 14, 0, 180, 9, 96, 48, 24, 12, 108, ++ 72, 36, 18, 4, 65, 4, 0, 247, 1, 0, 0, 7, 0, 0, 0, 15, 65, 4, 0, 55, ++ 1, 32, 0, 7, 0, 0, 0, 32, 65, 4, 0, 71, 1, 0, 0, 3, 0, 0, 0, 42, 65, ++ 4, 0, 119, 1, 128, 0, 8, 0, 64, 0, 49, 65, 4, 0, 245, 1, 128, 0, 3, ++ 0, 0, 0, 62, 65, 4, 0, 1, 2, 128, 0, 3, 0, 0, 0, 70, 65, 4, 0, 81, 1, ++ 8, 0, 3, 0, 0, 0, 86, 65, 4, 0, 82, 1, 8, 0, 3, 0, 0, 0, 99, 65, 4, ++ 0, 83, 1, 8, 0, 3, 0, 0, 0, 113, 65, 4, 0, 90, 1, 0, 0, 3, 0, 0, 0, ++ 124, 65, 4, 0, 91, 1, 0, 0, 5, 0, 0, 0, 141, 65, 4, 0, 187, 1, 64, 0, ++ 8, 0, 4, 0, 158, 65, 4, 0, 64, 1, 64, 0, 7, 0, 7, 0, 170, 65, 4, 0, ++ 213, 1, 64, 4, 8, 0, 6, 0, 194, 65, 4, 0, 214, 1, 64, 4, 8, 0, 6, 0, ++ 219, 65, 4, 0, 215, 1, 64, 4, 8, 0, 6, 0, 244, 65, 4, 0, 216, 1, 64, ++ 4, 8, 0, 6, 0, 12, 66, 4, 0, 159, 1, 0, 4, 7, 0, 0, 0, 26, 66, 4, 0, ++ 66, 1, 0, 0, 6, 0, 0, 0, 37, 66, 4, 0, 67, 1, 0, 0, 2, 0, 0, 0, 48, ++ 66, 4, 0, 161, 1, 0, 0, 2, 0, 0, 0, 154, 51, 4, 0, 69, 1, 0, 0, 7, 0, ++ 0, 0, 61, 66, 4, 0, 241, 1, 64, 4, 3, 0, 0, 0, 84, 66, 4, 0, 242, 1, ++ 64, 4, 3, 0, 0, 0, 107, 66, 4, 0, 107, 1, 0, 4, 4, 0, 0, 0, 121, 66, ++ 4, 0, 40, 0, 8, 0, 3, 0, 0, 0, 138, 66, 4, 0, 186, 1, 8, 0, 3, 0, 0, ++ 0, 145, 66, 4, 0, 41, 0, 0, 0, 3, 0, 0, 0, 158, 66, 4, 0, 166, 1, 0, ++ 0, 2, 0, 0, 0, 170, 66, 4, 0, 67, 1, 0, 0, 2, 0, 0, 0, 182, 66, 4, 0, ++ 190, 1, 136, 0, 8, 0, 18, 0, 233, 144, 136, 0, 191, 1, 64, 0, 7, 0, ++ 0, 0, 190, 66, 4, 0, 192, 1, 64, 0, 7, 0, 0, 0, 199, 66, 4, 0, 193, ++ 1, 64, 4, 6, 0, 0, 0, 213, 66, 4, 0, 237, 1, 0, 0, 2, 0, 0, 0, 229, ++ 66, 4, 0, 138, 1, 72, 4, 4, 0, 0, 0, 247, 66, 4, 0, 139, 1, 72, 4, 4, ++ 0, 0, 0, 0, 67, 4, 0, 140, 1, 72, 4, 4, 0, 0, 0, 13, 67, 4, 0, 141, ++ 1, 72, 4, 4, 0, 0, 0, 28, 67, 4, 0, 142, 1, 72, 4, 4, 0, 0, 0, 42, 67, ++ 4, 0, 143, 1, 72, 4, 4, 0, 0, 0, 51, 67, 4, 0, 144, 1, 72, 4, 4, 0, ++ 0, 0, 68, 67, 4, 0, 246, 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 112, 104, 121, 0, 99, 97, 108, 95, 112, 101, 114, 105, 111, ++ 100, 0, 110, 111, 105, 115, 101, 95, 109, 101, 97, 115, 95, 116, 105, ++ 109, 101, 114, 0, 112, 104, 121, 95, 109, 117, 116, 101, 100, 0, 112, ++ 97, 118, 97, 114, 115, 0, 112, 97, 112, 97, 114, 97, 109, 98, 119, 118, ++ 101, 114, 0, 115, 114, 111, 109, 114, 101, 118, 0, 112, 104, 121, 95, ++ 103, 108, 105, 116, 99, 104, 116, 104, 114, 115, 104, 0, 112, 104, 121, ++ 95, 110, 111, 105, 115, 101, 95, 117, 112, 0, 112, 104, 121, 95, 110, ++ 111, 105, 115, 101, 95, 100, 119, 110, 0, 112, 104, 121, 95, 112, 101, ++ 114, 99, 97, 108, 0, 112, 104, 121, 95, 112, 101, 114, 99, 97, 108, ++ 95, 100, 101, 108, 97, 121, 0, 112, 104, 121, 95, 102, 111, 114, 99, ++ 101, 95, 99, 114, 115, 109, 105, 110, 0, 112, 104, 121, 95, 114, 120, ++ 105, 113, 101, 115, 116, 0, 112, 104, 121, 95, 114, 115, 115, 105, 95, ++ 103, 97, 105, 110, 95, 100, 101, 108, 116, 97, 95, 53, 103, 108, 0, ++ 112, 104, 121, 95, 114, 115, 115, 105, 95, 103, 97, 105, 110, 95, 100, ++ 101, 108, 116, 97, 95, 53, 103, 109, 108, 0, 112, 104, 121, 95, 114, ++ 115, 115, 105, 95, 103, 97, 105, 110, 95, 100, 101, 108, 116, 97, 95, ++ 53, 103, 109, 117, 0, 112, 104, 121, 95, 114, 115, 115, 105, 95, 103, ++ 97, 105, 110, 95, 100, 101, 108, 116, 97, 95, 53, 103, 104, 0, 112, ++ 104, 121, 110, 111, 105, 115, 101, 95, 115, 114, 111, 109, 0, 110, 117, ++ 109, 95, 115, 116, 114, 101, 97, 109, 0, 98, 97, 110, 100, 95, 114, ++ 97, 110, 103, 101, 0, 115, 117, 98, 98, 97, 110, 100, 53, 103, 118, ++ 101, 114, 0, 97, 110, 116, 95, 100, 105, 118, 101, 114, 115, 105, 116, ++ 121, 95, 115, 119, 95, 99, 111, 114, 101, 48, 0, 97, 110, 116, 95, 100, ++ 105, 118, 101, 114, 115, 105, 116, 121, 95, 115, 119, 95, 99, 111, 114, ++ 101, 49, 0, 112, 104, 121, 95, 116, 101, 109, 112, 115, 101, 110, 115, ++ 101, 0, 112, 104, 121, 95, 111, 99, 108, 115, 99, 100, 101, 110, 97, ++ 98, 108, 101, 0, 108, 110, 108, 100, 111, 50, 0, 112, 104, 121, 95, ++ 114, 120, 97, 110, 116, 115, 101, 108, 0, 112, 104, 121, 95, 99, 114, ++ 115, 95, 119, 97, 114, 0, 115, 117, 98, 98, 97, 110, 100, 95, 105, 100, ++ 120, 0, 112, 97, 118, 97, 114, 115, 50, 0, 112, 104, 121, 95, 100, 115, ++ 115, 102, 0, 112, 104, 121, 95, 101, 100, 95, 116, 104, 114, 101, 115, ++ 104, 0, 112, 104, 121, 95, 116, 120, 115, 119, 99, 116, 114, 108, 109, ++ 97, 112, 0, 112, 104, 121, 95, 115, 114, 111, 109, 116, 101, 109, 112, ++ 115, 101, 110, 115, 101, 0, 114, 120, 103, 95, 114, 115, 115, 105, 0, ++ 114, 115, 115, 105, 95, 99, 97, 108, 95, 114, 101, 118, 0, 114, 117, ++ 100, 95, 97, 103, 99, 95, 101, 110, 97, 98, 108, 101, 0, 103, 97, 105, ++ 110, 95, 99, 97, 108, 95, 116, 101, 109, 112, 0, 105, 110, 116, 95, ++ 111, 118, 114, 50, 0, 116, 101, 109, 112, 95, 99, 111, 109, 112, 95, ++ 116, 114, 108, 111, 115, 115, 0, 112, 104, 121, 95, 111, 99, 108, 95, ++ 102, 111, 114, 99, 101, 95, 99, 111, 114, 101, 48, 0, 164, 4, 247, 5, ++ 74, 7, 158, 8, 241, 9, 241, 9, 164, 4, 164, 4, 164, 4, 164, 4, 164, ++ 4, 164, 4, 164, 4, 164, 4, 164, 4, 228, 12, 146, 16, 65, 20, 240, 23, ++ 159, 27, 159, 27, 228, 12, 228, 12, 228, 12, 228, 12, 228, 12, 228, ++ 12, 228, 12, 228, 12, 228, 12, 187, 62, 187, 62, 187, 62, 142, 67, 97, ++ 72, 97, 72, 154, 38, 184, 7, 166, 9, 16, 12, 113, 15, 77, 19, 32, 24, ++ 226, 30, 65, 48, 24, 94, 24, 94, 85, 101, 12, 123, 195, 144, 195, 144, ++ 231, 57, 148, 11, 121, 14, 24, 18, 41, 23, 243, 28, 48, 36, 83, 46, ++ 97, 72, 207, 115, 118, 125, 29, 135, 17, 164, 4, 193, 4, 193, 53, 77, ++ 121, 14, 77, 19, 32, 24, 243, 28, 154, 38, 65, 48, 231, 57, 130, 96, ++ 173, 128, 140, 141, 106, 154, 72, 167, 38, 180, 4, 193, 53, 77, 21, ++ 16, 77, 19, 188, 25, 43, 32, 154, 38, 120, 51, 86, 64, 241, 102, 226, ++ 3, 203, 10, 65, 48, 97, 72, 62, 68, 253, 90, 90, 7, 130, 7, 74, 7, 216, ++ 6, 70, 6, 251, 4, 168, 11, 108, 58, 104, 46, 220, 36, 71, 29, 66, 23, ++ 121, 18, 172, 14, 66, 9, 110, 20, 221, 20, 65, 20, 4, 19, 109, 17, 216, ++ 13, 97, 32, 72, 162, 232, 128, 100, 102, 85, 81, 155, 64, 81, 51, 195, ++ 40, 184, 25, 40, 97, 45, 77, 77, 61, 112, 52, 161, 44, 115, 35, 194, ++ 94, 252, 94, 80, 94, 164, 93, 54, 95, 137, 94, 221, 93, 112, 95, 22, ++ 94, 189, 145, 195, 115, 7, 99, 132, 95, 66, 89, 231, 70, 36, 142, 122, ++ 142, 120, 141, 119, 140, 209, 142, 206, 141, 204, 140, 40, 143, 34, ++ 141, 72, 173, 28, 149, 142, 127, 8, 123, 249, 114, 83, 91, 22, 183, ++ 13, 172, 56, 182, 238, 180, 118, 172, 167, 182, 92, 181, 222, 172, 202, ++ 181, 136, 192, 58, 168, 199, 145, 113, 125, 79, 107, 83, 91, 22, 183, ++ 43, 191, 56, 182, 254, 192, 159, 191, 167, 182, 115, 193, 20, 192, 232, ++ 193, 255, 255, 255, 255, 192, 255, 255, 255, 183, 181, 151, 96, 229, ++ 0, 0, 0, 0, 0, 20, 29, 40, 52, 52, 52, 0, 29, 0, 0, 0, 0, 0, 32, 32, ++ 32, 32, 32, 32, 0, 32, 0, 0, 0, 0, 0, 64, 64, 64, 64, 91, 108, 0, 128, ++ 0, 74, 0, 0, 64, 4, 1, 0, 0, 0, 74, 100, 68, 0, 74, 68, 128, 0, 0, 74, ++ 255, 0, 64, 4, 1, 0, 1, 0, 24, 0, 48, 0, 96, 0, 96, 0, 128, 0, 128, ++ 0, 249, 5, 217, 5, 6, 6, 107, 6, 1, 7, 209, 8, 197, 3, 192, 0, 242, ++ 0, 49, 1, 128, 1, 227, 1, 97, 2, 254, 2, 191, 4, 153, 16, 64, 16, 189, ++ 16, 213, 17, 117, 19, 126, 24, 121, 10, 22, 2, 161, 2, 79, 3, 43, 4, ++ 63, 5, 155, 6, 81, 8, 47, 13, 247, 23, 43, 30, 251, 37, 103, 44, 44, ++ 52, 174, 65, 146, 24, 131, 24, 176, 24, 221, 24, 116, 24, 161, 24, 206, ++ 24, 101, 24, 191, 24, 242, 35, 65, 45, 231, 52, 217, 54, 177, 58, 228, ++ 73, 219, 36, 197, 36, 8, 37, 76, 37, 175, 36, 242, 36, 53, 37, 152, ++ 36, 31, 37, 192, 53, 118, 62, 5, 73, 180, 75, 2, 81, 252, 101, 223, ++ 50, 34, 54, 29, 51, 122, 51, 1, 54, 254, 50, 91, 51, 225, 53, 60, 51, ++ 0, 86, 109, 98, 150, 113, 255, 131, 78, 154, 79, 181, 112, 90, 157, ++ 86, 222, 90, 204, 85, 105, 86, 167, 90, 152, 85, 52, 86, 100, 85, 0, ++ 1, 2, 3, 4, 5, 254, 247, 248, 249, 250, 251, 252, 253, 255, 0, 62, 0, ++ 172, 0, 4, 3, 134, 4, 8, 6, 10, 8, 13, 4, 255, 3, 64, 0, 13, 4, 0, 112, ++ 0, 64, 162, 4, 255, 3, 64, 0, 162, 4, 0, 112, 0, 64, 12, 5, 255, 1, ++ 0, 0, 248, 9, 4, 0, 4, 0, 218, 6, 64, 0, 64, 0, 116, 5, 0, 32, 0, 32, ++ 117, 5, 0, 2, 0, 2, 164, 4, 0, 64, 0, 0, 164, 4, 0, 128, 0, 128, 208, ++ 4, 32, 0, 0, 0, 164, 4, 255, 1, 0, 0, 164, 4, 0, 4, 0, 4, 165, 4, 255, ++ 3, 44, 1, 165, 4, 0, 224, 0, 160, 165, 4, 0, 28, 0, 0, 13, 4, 255, 3, ++ 64, 0, 13, 4, 0, 112, 0, 64, 162, 4, 255, 3, 64, 0, 162, 4, 0, 112, ++ 0, 64, 168, 4, 255, 0, 1, 0, 208, 4, 192, 127, 0, 0, 12, 5, 255, 1, ++ 0, 0, 166, 4, 0, 128, 0, 128, 166, 4, 255, 1, 255, 0, 154, 4, 255, 1, ++ 255, 0, 244, 9, 0, 128, 0, 128, 244, 9, 0, 56, 0, 32, 244, 9, 255, 3, ++ 55, 0, 153, 4, 255, 3, 120, 0, 159, 4, 0, 192, 0, 64, 159, 4, 255, 3, ++ 144, 1, 215, 4, 8, 0, 8, 0, 215, 4, 0, 112, 0, 32, 172, 9, 60, 0, 20, ++ 0, 248, 9, 4, 0, 4, 0, 214, 70, 1, 0, 218, 6, 8, 0, 0, 0, 218, 6, 128, ++ 0, 0, 0, 218, 6, 0, 128, 0, 0, 218, 6, 0, 128, 0, 128, 211, 6, 0, 128, ++ 0, 128, 211, 6, 0, 128, 0, 0, 218, 6, 0, 128, 0, 0, 217, 4, 4, 0, 0, ++ 0, 217, 4, 8, 0, 8, 0, 3, 0, 4, 0, 6, 0, 9, 0, 13, 0, 18, 0, 25, 0, ++ 25, 1, 25, 2, 25, 3, 25, 4, 25, 5, 25, 6, 25, 7, 35, 7, 50, 7, 71, 7, ++ 100, 7, 64, 4, 1, 0, 1, 0, 74, 68, 0, 0, 85, 6, 0, 240, 0, 128, 218, ++ 10, 0, 64, 0, 64, 0, 1, 0, 1, 252, 0, 2, 0, 252, 0, 1, 0, 252, 0, 0, ++ 0, 253, 0, 0, 0, 254, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, ++ 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7, 0, ++ 0, 0, 8, 0, 0, 0, 9, 0, 0, 217, 4, 4, 0, 4, 0, 217, 4, 8, 0, 0, 0, 217, ++ 4, 2, 0, 2, 0, 215, 4, 1, 0, 1, 0, 215, 4, 64, 0, 0, 0, 251, 227, 101, ++ 0, 5, 174, 101, 0, 73, 120, 101, 0, 197, 66, 101, 0, 121, 13, 101, 0, ++ 102, 216, 100, 0, 138, 163, 100, 0, 229, 110, 100, 0, 119, 58, 100, ++ 0, 64, 6, 100, 0, 64, 210, 99, 0, 117, 158, 99, 0, 224, 106, 99, 0, ++ 236, 239, 98, 0, 3, 0, 4, 0, 6, 0, 9, 0, 13, 0, 18, 0, 25, 0, 35, 0, ++ 50, 0, 71, 0, 100, 0, 100, 1, 100, 2, 100, 3, 100, 4, 100, 5, 100, 6, ++ 100, 7, 0, 1, 4, 0, 0, 0, 3, 0, 0, 1, 3, 0, 0, 2, 3, 0, 0, 3, 3, 0, ++ 0, 4, 3, 0, 0, 5, 3, 0, 0, 6, 3, 0, 0, 7, 3, 0, 0, 8, 3, 0, 0, 9, 3, ++ 0, 0, 10, 3, 0, 0, 10, 3, 1, 0, 10, 3, 2, 0, 10, 3, 3, 0, 10, 3, 4, ++ 208, 4, 1, 0, 0, 0, 211, 4, 255, 0, 0, 0, 211, 4, 0, 255, 0, 0, 208, ++ 4, 16, 0, 0, 0, 208, 4, 4, 0, 0, 0, 208, 4, 2, 0, 0, 0, 210, 4, 255, ++ 0, 0, 0, 210, 4, 0, 255, 0, 0, 208, 4, 8, 0, 0, 0, 217, 4, 1, 0, 1, ++ 0, 217, 4, 2, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 181, ++ 0, 128, 0, 90, 0, 64, 0, 45, 0, 32, 0, 0, 0, 0, 0, 0, 1, 181, 0, 128, ++ 0, 91, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 128, 0, 31, ++ 8, 224, 23, 255, 127, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 216, 4, 1, 0, 0, 0, 216, ++ 4, 2, 0, 0, 0, 215, 4, 8, 0, 0, 0, 64, 4, 1, 0, 0, 0, 74, 68, 79, 0, ++ 58, 68, 0, 0, 117, 69, 0, 0, 76, 68, 0, 0, 176, 68, 0, 0, 249, 68, 0, ++ 0, 56, 73, 0, 0, 61, 69, 0, 0, 113, 69, 0, 0, 115, 69, 0, 0, 78, 68, ++ 0, 0, 52, 5, 255, 0, 18, 0, 228, 4, 0, 255, 0, 6, 77, 4, 0, 2, 0, 0, ++ 76, 4, 0, 2, 0, 2, 54, 5, 16, 0, 16, 0, 156, 74, 4, 0, 26, 0, 0, 0, ++ 17, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 224, 79, 4, 0, 96, 0, 0, 0, 18, ++ 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 216, 77, 4, 0, 76, 0, 0, 0, 13, 0, ++ 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 2, 3, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 2, 3, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 125, 100, 12, 10, 125, 123, 1, ++ 7, 13, 19, 25, 0, 127, 126, 125, 123, 121, 119, 117, 115, 112, 109, ++ 107, 112, 109, 107, 26, 0, 52, 0, 78, 0, 104, 0, 156, 0, 208, 0, 234, ++ 0, 4, 1, 52, 0, 104, 0, 156, 0, 208, 0, 56, 1, 160, 1, 212, 1, 8, 2, ++ 78, 0, 156, 0, 234, 0, 56, 1, 212, 1, 112, 2, 190, 2, 12, 3, 104, 0, ++ 208, 0, 56, 1, 160, 1, 112, 2, 64, 3, 168, 3, 16, 4, 24, 0, 156, 0, ++ 208, 0, 4, 1, 234, 0, 56, 1, 134, 1, 208, 0, 4, 1, 4, 1, 56, 1, 108, ++ 1, 108, 1, 160, 1, 56, 1, 134, 1, 134, 1, 212, 1, 34, 2, 34, 2, 112, ++ 2, 4, 1, 56, 1, 108, 1, 56, 1, 108, 1, 160, 1, 212, 1, 160, 1, 212, ++ 1, 8, 2, 8, 2, 60, 2, 134, 1, 212, 1, 34, 2, 212, 1, 34, 2, 112, 2, ++ 190, 2, 112, 2, 190, 2, 12, 3, 12, 3, 90, 3, 54, 0, 108, 0, 162, 0, ++ 216, 0, 68, 1, 176, 1, 230, 1, 28, 2, 108, 0, 216, 0, 68, 1, 176, 1, ++ 136, 2, 96, 3, 204, 3, 56, 4, 162, 0, 68, 1, 230, 1, 136, 2, 204, 3, ++ 16, 5, 178, 5, 84, 6, 216, 0, 176, 1, 136, 2, 96, 3, 16, 5, 192, 6, ++ 152, 7, 112, 8, 24, 0, 68, 1, 176, 1, 28, 2, 230, 1, 136, 2, 42, 3, ++ 176, 1, 28, 2, 28, 2, 136, 2, 244, 2, 244, 2, 96, 3, 136, 2, 42, 3, ++ 42, 3, 204, 3, 110, 4, 110, 4, 16, 5, 28, 2, 136, 2, 244, 2, 136, 2, ++ 244, 2, 96, 3, 204, 3, 96, 3, 204, 3, 56, 4, 56, 4, 164, 4, 42, 3, 204, ++ 3, 110, 4, 204, 3, 110, 4, 16, 5, 178, 5, 16, 5, 178, 5, 84, 6, 84, ++ 6, 246, 6, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, 1, 183, ++ 1, 183, 1, 183, 1, 183, 1, 0, 0, 234, 75, 4, 0, 128, 0, 0, 0, 2, 0, ++ 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 88, 77, 4, 0, 64, 0, 0, 0, 1, 0, 0, 0, ++ 0, 0, 0, 0, 16, 0, 0, 0, 156, 73, 4, 0, 0, 1, 0, 0, 20, 0, 0, 0, 0, ++ 0, 0, 0, 8, 0, 0, 0, 182, 74, 4, 0, 154, 0, 0, 0, 23, 0, 0, 0, 0, 0, ++ 0, 0, 16, 0, 0, 0, 8, 79, 4, 0, 108, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 16, 0, 0, 0, 5, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 128, 48, 0, 0, 128, 48, 0, 0, 128, 48, 0, 0, 128, 48, 0, 0, ++ 128, 48, 0, 0, 128, 48, 0, 128, 128, 48, 0, 0, 129, 48, 0, 128, 129, ++ 48, 0, 0, 130, 48, 0, 128, 130, 48, 0, 0, 131, 48, 0, 128, 131, 48, ++ 0, 0, 132, 48, 0, 128, 132, 16, 0, 0, 133, 16, 0, 128, 197, 16, 0, 0, ++ 198, 16, 0, 128, 6, 17, 0, 0, 7, 17, 0, 128, 71, 17, 0, 0, 72, 17, 0, ++ 128, 72, 11, 0, 0, 73, 11, 0, 128, 73, 1, 0, 0, 74, 1, 0, 128, 74, 1, ++ 0, 0, 75, 1, 0, 128, 75, 1, 0, 0, 76, 1, 0, 128, 76, 1, 0, 0, 77, 1, ++ 0, 128, 77, 1, 0, 0, 78, 1, 0, 128, 78, 1, 0, 0, 79, 1, 0, 128, 79, ++ 1, 0, 0, 80, 1, 0, 0, 64, 49, 0, 0, 64, 49, 0, 0, 64, 49, 0, 0, 64, ++ 49, 0, 0, 64, 49, 0, 0, 64, 49, 0, 0, 64, 49, 0, 0, 64, 49, 0, 128, ++ 64, 49, 0, 128, 80, 49, 0, 0, 81, 49, 0, 128, 81, 49, 0, 0, 82, 49, ++ 0, 128, 82, 49, 0, 0, 83, 49, 0, 128, 83, 49, 0, 0, 84, 49, 0, 128, ++ 84, 49, 0, 0, 85, 49, 0, 128, 149, 16, 0, 0, 150, 16, 0, 128, 150, 16, ++ 0, 0, 151, 16, 0, 128, 215, 16, 0, 0, 216, 16, 0, 128, 216, 16, 0, 0, ++ 25, 17, 0, 128, 25, 17, 0, 0, 90, 17, 0, 128, 90, 17, 0, 0, 91, 11, ++ 0, 128, 91, 11, 0, 0, 92, 11, 0, 128, 92, 11, 0, 0, 93, 1, 0, 128, 93, ++ 1, 0, 0, 94, 1, 0, 128, 94, 1, 0, 0, 2, 0, 3, 0, 4, 0, 6, 0, 8, 0, 11, ++ 0, 16, 1, 16, 2, 16, 3, 16, 4, 16, 5, 16, 6, 16, 7, 16, 7, 23, 7, 32, ++ 7, 45, 7, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 3, 0, 4, 0, 6, 0, 8, 0, 11, 0, ++ 16, 1, 16, 2, 16, 3, 16, 4, 16, 5, 16, 6, 16, 7, 16, 7, 23, 7, 32, 7, ++ 45, 7, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 248, 3, 0, 0, 248, 11, 0, 128, 232, 11, 0, 0, 217, ++ 11, 0, 128, 209, 11, 0, 0, 194, 11, 0, 128, 186, 11, 0, 0, 179, 11, ++ 0, 129, 114, 11, 0, 129, 250, 10, 0, 1, 243, 10, 0, 129, 66, 10, 0, ++ 1, 59, 10, 0, 129, 146, 9, 0, 1, 139, 9, 0, 129, 234, 8, 0, 1, 235, ++ 8, 0, 129, 146, 8, 0, 1, 147, 8, 0, 129, 106, 8, 0, 1, 107, 8, 0, 131, ++ 98, 8, 0, 3, 99, 8, 0, 3, 99, 16, 0, 3, 99, 24, 0, 3, 99, 32, 0, 131, ++ 99, 32, 0, 3, 100, 32, 0, 131, 100, 32, 0, 3, 101, 32, 0, 3, 101, 40, ++ 0, 3, 101, 48, 0, 3, 101, 56, 0, 0, 248, 19, 0, 0, 248, 27, 0, 0, 248, ++ 35, 0, 0, 248, 43, 0, 0, 248, 51, 0, 0, 248, 59, 0, 128, 232, 59, 0, ++ 1, 176, 59, 0, 129, 152, 59, 0, 3, 56, 59, 0, 128, 53, 3, 0, 128, 53, ++ 11, 0, 129, 237, 2, 0, 129, 237, 10, 0, 129, 53, 2, 0, 129, 53, 10, ++ 0, 129, 53, 18, 0, 129, 141, 9, 0, 129, 141, 17, 0, 129, 229, 8, 0, ++ 129, 229, 16, 0, 129, 141, 8, 0, 129, 141, 16, 0, 129, 141, 24, 0, 129, ++ 141, 32, 0, 129, 109, 24, 0, 129, 109, 32, 0, 129, 109, 40, 0, 129, ++ 109, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 112, 107, 116, 95, 102, 105, 108, 116, 101, 114, 0, 97, 112, 102, ++ 95, 115, 105, 122, 101, 95, 108, 105, 109, 105, 116, 0, 97, 112, 102, ++ 95, 118, 101, 114, 0, 0, 0, 107, 81, 4, 0, 16, 0, 0, 0, 7, 0, 4, 0, ++ 122, 81, 4, 0, 15, 0, 0, 0, 7, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 49, 124, 3, 0, 1, 0, 0, 0, 59, 124, 3, 0, 2, 0, 0, ++ 0, 83, 124, 3, 0, 6, 0, 0, 0, 127, 124, 3, 0, 11, 0, 0, 0, 165, 124, ++ 3, 0, 12, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 22, 44, 66, 1, 2, 3, 0, 0, 0, 4, 0, 0, 0, 0, 5, 112, 114, ++ 111, 116, 95, 103, 0, 112, 114, 111, 116, 95, 110, 0, 0, 0, 0, 12, 0, ++ 0, 0, 24, 0, 0, 0, 36, 0, 0, 0, 48, 0, 0, 0, 72, 0, 0, 0, 96, 0, 0, ++ 0, 108, 0, 0, 0, 108, 0, 0, 0, 108, 0, 0, 0, 108, 0, 0, 0, 1, 1, 2, ++ 2, 1, 2, 2, 3, 4, 4, 1, 2, 4, 3, 4, 6, 2, 3, 6, 3, 4, 6, 5, 6, 8, 3, ++ 4, 8, 5, 6, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 8, 0, 0, 0, 11, ++ 0, 0, 0, 16, 0, 0, 0, 22, 0, 0, 0, 24, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, ++ 0, 18, 0, 0, 0, 2, 0, 0, 0, 24, 0, 0, 0, 8, 0, 0, 0, 36, 0, 0, 0, 10, ++ 0, 0, 0, 48, 0, 0, 0, 16, 0, 0, 0, 72, 0, 0, 0, 18, 0, 0, 0, 96, 0, ++ 0, 0, 25, 0, 0, 0, 108, 0, 0, 0, 26, 0, 0, 0, 160, 85, 4, 0, 0, 0, 128, ++ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 4, 0, ++ 0, 0, 11, 0, 0, 0, 12, 0, 0, 0, 18, 0, 0, 0, 22, 0, 0, 0, 24, 0, 0, ++ 0, 36, 0, 0, 0, 48, 0, 0, 0, 72, 0, 0, 0, 96, 0, 0, 0, 108, 0, 0, 0, ++ 32, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 2, 0, 0, 1, 3, 0, 0, 1, 4, 0, 0, ++ 1, 5, 0, 0, 1, 6, 0, 0, 1, 7, 0, 0, 1, 8, 0, 0, 1, 9, 0, 0, 1, 10, 0, ++ 0, 1, 11, 0, 0, 1, 12, 0, 0, 1, 13, 0, 0, 1, 14, 0, 0, 1, 15, 0, 0, ++ 1, 16, 0, 0, 1, 17, 0, 0, 1, 18, 0, 0, 1, 19, 0, 0, 1, 20, 0, 0, 1, ++ 21, 0, 0, 1, 22, 0, 0, 1, 23, 0, 0, 1, 87, 0, 0, 1, 88, 0, 0, 1, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 255, 255, 255, 255, 2, ++ 0, 0, 0, 17, 0, 0, 0, 6, 0, 0, 0, 8, 0, 0, 0, 2, 0, 0, 0, 17, 0, 0, ++ 0, 6, 0, 0, 0, 8, 0, 0, 0, 2, 0, 0, 0, 17, 0, 0, 0, 6, 0, 0, 0, 9, 0, ++ 0, 0, 2, 0, 0, 0, 18, 0, 0, 0, 6, 0, 0, 0, 9, 0, 0, 0, 2, 0, 0, 0, 18, ++ 0, 0, 0, 6, 0, 0, 0, 10, 0, 0, 0, 2, 0, 0, 0, 19, 0, 0, 0, 6, 0, 0, ++ 0, 11, 0, 0, 0, 2, 0, 0, 0, 20, 0, 0, 0, 6, 0, 0, 0, 12, 0, 0, 0, 2, ++ 0, 0, 0, 20, 0, 0, 0, 6, 0, 0, 0, 12, 0, 0, 0, 2, 0, 0, 0, 20, 0, 0, ++ 0, 6, 0, 0, 0, 2, 0, 0, 0, 2, 0, 0, 0, 17, 0, 0, 0, 6, 0, 0, 0, 3, 0, ++ 0, 0, 2, 0, 0, 0, 18, 0, 0, 0, 6, 0, 0, 0, 4, 0, 0, 0, 2, 0, 0, 0, 19, ++ 0, 0, 0, 7, 0, 0, 0, 5, 0, 0, 0, 2, 0, 0, 0, 20, 0, 0, 0, 7, 0, 0, 0, ++ 7, 0, 0, 0, 2, 0, 0, 0, 30, 0, 0, 0, 7, 0, 0, 0, 255, 255, 255, 255, ++ 2, 0, 0, 0, 40, 0, 0, 0, 7, 0, 0, 0, 255, 255, 255, 255, 2, 0, 0, 0, ++ 100, 0, 0, 0, 7, 0, 0, 0, 255, 255, 255, 255, 2, 0, 0, 0, 200, 0, 0, ++ 0, 7, 0, 0, 0, 255, 255, 255, 255, 2, 0, 0, 0, 44, 1, 0, 0, 8, 0, 0, ++ 0, 255, 255, 255, 255, 2, 0, 0, 0, 44, 1, 0, 0, 8, 0, 0, 0, 255, 255, ++ 255, 255, 2, 0, 0, 0, 44, 1, 0, 0, 8, 0, 0, 0, 255, 255, 255, 255, 2, ++ 0, 0, 0, 44, 1, 0, 0, 8, 0, 0, 0, 255, 255, 255, 255, 2, 0, 0, 0, 44, ++ 1, 0, 0, 8, 0, 0, 0, 255, 255, 255, 255, 2, 0, 0, 0, 44, 1, 0, 0, 8, ++ 0, 0, 0, 255, 255, 255, 255, 2, 0, 0, 0, 44, 1, 0, 0, 8, 0, 0, 0, 255, ++ 255, 255, 255, 2, 0, 0, 0, 44, 1, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37, 115, ++ 58, 32, 111, 110, 108, 121, 32, 115, 117, 112, 112, 111, 114, 116, 32, ++ 49, 45, 115, 116, 114, 101, 97, 109, 32, 49, 49, 110, 95, 50, 53, 54, ++ 81, 65, 77, 32, 102, 111, 114, 32, 110, 111, 110, 45, 49, 49, 97, 99, ++ 32, 99, 111, 109, 112, 105, 108, 101, 100, 32, 100, 101, 118, 105, 99, ++ 101, 33, 10, 0, 114, 97, 116, 101, 115, 101, 108, 95, 100, 117, 109, ++ 109, 121, 0, 87, 88, 99, 100, 101, 102, 255, 255, 255, 255, 255, 255, ++ 255, 255, 2, 0, 0, 0, 17, 0, 0, 0, 6, 0, 0, 0, 8, 0, 0, 0, 255, 255, ++ 255, 255, 2, 0, 0, 0, 17, 0, 0, 0, 6, 0, 0, 0, 8, 0, 0, 0, 255, 255, ++ 255, 255, 2, 0, 0, 0, 17, 0, 0, 0, 6, 0, 0, 0, 9, 0, 0, 0, 255, 255, ++ 255, 255, 2, 0, 0, 0, 18, 0, 0, 0, 6, 0, 0, 0, 9, 0, 0, 0, 255, 255, ++ 255, 255, 2, 0, 0, 0, 18, 0, 0, 0, 6, 0, 0, 0, 10, 0, 0, 0, 255, 255, ++ 255, 255, 2, 0, 0, 0, 19, 0, 0, 0, 6, 0, 0, 0, 11, 0, 0, 0, 255, 255, ++ 255, 255, 2, 0, 0, 0, 20, 0, 0, 0, 6, 0, 0, 0, 12, 0, 0, 0, 255, 255, ++ 255, 255, 2, 0, 0, 0, 20, 0, 0, 0, 6, 0, 0, 0, 12, 0, 0, 0, 255, 255, ++ 255, 255, 2, 0, 0, 0, 20, 0, 0, 0, 6, 0, 0, 0, 2, 0, 0, 0, 16, 0, 0, ++ 0, 2, 0, 0, 0, 17, 0, 0, 0, 6, 0, 0, 0, 3, 0, 0, 0, 17, 0, 0, 0, 2, ++ 0, 0, 0, 18, 0, 0, 0, 6, 0, 0, 0, 4, 0, 0, 0, 17, 0, 0, 0, 2, 0, 0, ++ 0, 19, 0, 0, 0, 7, 0, 0, 0, 5, 0, 0, 0, 18, 0, 0, 0, 2, 0, 0, 0, 20, ++ 0, 0, 0, 7, 0, 0, 0, 7, 0, 0, 0, 19, 0, 0, 0, 2, 0, 0, 0, 30, 0, 0, ++ 0, 7, 0, 0, 0, 255, 255, 255, 255, 20, 0, 0, 0, 2, 0, 0, 0, 40, 0, 0, ++ 0, 7, 0, 0, 0, 255, 255, 255, 255, 20, 0, 0, 0, 2, 0, 0, 0, 50, 0, 0, ++ 0, 7, 0, 0, 0, 255, 255, 255, 255, 21, 0, 0, 0, 2, 0, 0, 0, 60, 0, 0, ++ 0, 7, 0, 0, 0, 255, 255, 255, 255, 9, 0, 0, 0, 2, 0, 0, 0, 19, 0, 0, ++ 0, 8, 0, 0, 0, 255, 255, 255, 255, 10, 0, 0, 0, 2, 0, 0, 0, 19, 0, 0, ++ 0, 8, 0, 0, 0, 255, 255, 255, 255, 11, 0, 0, 0, 2, 0, 0, 0, 23, 0, 0, ++ 0, 8, 0, 0, 0, 255, 255, 255, 255, 12, 0, 0, 0, 2, 0, 0, 0, 40, 0, 0, ++ 0, 8, 0, 0, 0, 255, 255, 255, 255, 14, 0, 0, 0, 2, 0, 0, 0, 50, 0, 0, ++ 0, 8, 0, 0, 0, 255, 255, 255, 255, 15, 0, 0, 0, 2, 0, 0, 0, 60, 0, 0, ++ 0, 8, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 2, 0, 0, 0, 21, ++ 0, 0, 0, 8, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 2, 0, 0, ++ 0, 21, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 119, 108, 99, 95, 114, 97, ++ 116, 101, 115, 101, 108, 95, 102, 105, 108, 116, 101, 114, 95, 109, ++ 99, 115, 115, 101, 116, 0, 0, 0, 160, 88, 4, 0, 0, 0, 0, 0, 1, 0, 0, ++ 0, 188, 88, 4, 0, 2, 0, 0, 0, 7, 0, 0, 0, 210, 88, 4, 0, 3, 0, 0, 0, ++ 7, 0, 0, 0, 233, 88, 4, 0, 1, 0, 0, 0, 8, 0, 0, 0, 246, 88, 4, 0, 4, ++ 0, 0, 0, 1, 0, 0, 0, 4, 89, 4, 0, 5, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 83, 65, 69, 32, 75, 67, 75, 32, 97, 110, 100, ++ 32, 80, 77, 75, 0, 115, 97, 101, 0, 83, 65, 69, 32, 72, 117, 110, 116, ++ 105, 110, 103, 32, 97, 110, 100, 32, 80, 101, 99, 107, 105, 110, 103, ++ 0, 115, 97, 101, 95, 97, 117, 116, 104, 95, 114, 101, 116, 120, 95, ++ 116, 105, 109, 101, 111, 117, 116, 0, 115, 97, 101, 95, 112, 109, 107, ++ 95, 101, 120, 112, 105, 114, 121, 95, 116, 105, 109, 101, 111, 117, ++ 116, 0, 115, 97, 101, 95, 112, 97, 115, 115, 119, 111, 114, 100, 0, ++ 115, 97, 101, 95, 109, 102, 112, 95, 99, 104, 101, 99, 107, 0, 115, ++ 97, 101, 95, 116, 114, 97, 110, 115, 105, 116, 105, 111, 110, 95, 109, ++ 111, 100, 101, 0, 251, 127, 136, 0, 4, 0, 16, 64, 5, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 1, 2, 1, 1, 2, 2, 3, 6, 3, ++ 7, 7, 4, 15, 15, 109, 105, 109, 111, 95, 112, 115, 0, 109, 105, 109, ++ 111, 95, 115, 115, 95, 115, 116, 102, 0, 115, 116, 102, 95, 115, 115, ++ 95, 97, 117, 116, 111, 0, 115, 116, 98, 99, 95, 114, 120, 0, 115, 116, ++ 98, 99, 95, 116, 120, 0, 115, 105, 115, 111, 95, 116, 120, 0, 116, 120, ++ 115, 116, 114, 101, 97, 109, 115, 0, 104, 119, 95, 116, 120, 99, 104, ++ 97, 105, 110, 0, 114, 120, 115, 116, 114, 101, 97, 109, 115, 0, 104, ++ 119, 95, 114, 120, 99, 104, 97, 105, 110, 0, 116, 120, 99, 111, 114, ++ 101, 0, 116, 120, 99, 111, 114, 101, 95, 111, 118, 101, 114, 114, 105, ++ 100, 101, 0, 116, 101, 109, 112, 115, 101, 110, 115, 101, 95, 100, 105, ++ 115, 97, 98, 108, 101, 0, 116, 120, 99, 104, 97, 105, 110, 95, 112, ++ 119, 114, 95, 111, 102, 102, 115, 101, 116, 0, 99, 117, 114, 112, 112, ++ 114, 0, 112, 119, 114, 116, 104, 114, 111, 116, 116, 108, 101, 95, 116, ++ 101, 115, 116, 0, 112, 119, 114, 116, 104, 114, 111, 116, 116, 108, ++ 101, 95, 109, 97, 115, 107, 0, 112, 119, 114, 116, 104, 114, 111, 116, ++ 116, 108, 101, 0, 112, 119, 114, 116, 104, 114, 111, 116, 116, 108, ++ 101, 95, 115, 116, 97, 116, 101, 0, 115, 112, 97, 116, 105, 97, 108, ++ 95, 112, 111, 108, 105, 99, 121, 0, 114, 115, 115, 105, 95, 112, 119, ++ 114, 100, 110, 95, 100, 105, 115, 97, 98, 108, 101, 0, 114, 97, 116, ++ 101, 116, 98, 108, 95, 112, 112, 114, 0, 111, 110, 101, 99, 104, 97, ++ 105, 110, 0, 100, 117, 116, 121, 99, 121, 99, 108, 101, 95, 99, 99, ++ 107, 0, 100, 117, 116, 121, 99, 121, 99, 108, 101, 95, 111, 102, 100, ++ 109, 0, 100, 117, 116, 121, 99, 121, 99, 108, 101, 95, 112, 119, 114, ++ 0, 100, 117, 116, 121, 99, 121, 99, 108, 101, 95, 116, 104, 101, 114, ++ 109, 97, 108, 0, 116, 120, 95, 110, 115, 115, 0, 99, 99, 107, 95, 116, ++ 120, 109, 111, 100, 101, 0, 115, 119, 100, 105, 118, 95, 115, 116, 97, ++ 116, 115, 0, 115, 119, 100, 105, 118, 95, 114, 101, 115, 101, 116, 95, ++ 115, 116, 97, 116, 115, 0, 115, 119, 100, 105, 118, 95, 116, 120, 95, ++ 119, 101, 105, 103, 104, 116, 0, 115, 119, 100, 105, 118, 95, 99, 101, ++ 108, 108, 95, 112, 111, 108, 105, 99, 121, 0, 115, 119, 100, 105, 118, ++ 95, 114, 120, 95, 112, 111, 108, 105, 99, 121, 0, 115, 119, 100, 105, ++ 118, 95, 116, 120, 95, 112, 111, 108, 105, 99, 121, 0, 115, 116, 102, ++ 95, 116, 104, 114, 111, 116, 116, 108, 101, 95, 101, 110, 0, 0, 0, 0, ++ 66, 89, 4, 0, 2, 0, 0, 64, 3, 0, 0, 0, 74, 89, 4, 0, 0, 0, 0, 64, 2, ++ 0, 0, 0, 86, 89, 4, 0, 1, 0, 0, 0, 2, 0, 0, 0, 98, 89, 4, 0, 3, 0, 0, ++ 64, 3, 0, 0, 0, 106, 89, 4, 0, 4, 0, 0, 64, 2, 0, 0, 0, 114, 89, 4, ++ 0, 7, 0, 0, 0, 1, 0, 0, 0, 122, 89, 4, 0, 5, 0, 0, 0, 3, 0, 0, 0, 135, ++ 89, 4, 0, 6, 0, 0, 0, 6, 0, 0, 0, 132, 89, 4, 0, 8, 0, 0, 0, 3, 0, 0, ++ 0, 143, 89, 4, 0, 9, 0, 0, 0, 3, 0, 0, 0, 153, 89, 4, 0, 11, 0, 0, 0, ++ 3, 0, 0, 0, 156, 89, 4, 0, 10, 0, 0, 0, 3, 0, 0, 0, 164, 89, 4, 0, 12, ++ 0, 0, 0, 8, 0, 8, 0, 171, 89, 4, 0, 13, 0, 0, 0, 8, 0, 8, 0, 187, 89, ++ 4, 0, 15, 0, 0, 0, 1, 0, 0, 0, 205, 89, 4, 0, 16, 0, 0, 0, 8, 0, 4, ++ 0, 224, 89, 4, 0, 18, 0, 0, 0, 8, 0, 0, 0, 231, 89, 4, 0, 19, 0, 0, ++ 0, 3, 0, 0, 0, 248, 89, 4, 0, 20, 0, 0, 0, 3, 0, 0, 0, 9, 90, 4, 0, ++ 21, 0, 0, 0, 6, 0, 0, 0, 21, 90, 4, 0, 22, 0, 0, 0, 6, 0, 0, 0, 39, ++ 90, 4, 0, 14, 0, 0, 0, 8, 0, 20, 0, 54, 90, 4, 0, 17, 0, 0, 0, 1, 0, ++ 0, 0, 73, 90, 4, 0, 23, 0, 0, 0, 8, 0, 48, 0, 85, 90, 4, 0, 24, 0, 0, ++ 0, 2, 0, 0, 0, 94, 90, 4, 0, 25, 0, 0, 0, 3, 0, 0, 0, 108, 90, 4, 0, ++ 26, 0, 0, 0, 3, 0, 0, 0, 123, 90, 4, 0, 27, 0, 0, 0, 3, 0, 0, 0, 137, ++ 90, 4, 0, 28, 0, 0, 0, 3, 0, 0, 0, 155, 90, 4, 0, 29, 0, 0, 0, 3, 0, ++ 0, 0, 162, 90, 4, 0, 30, 0, 64, 4, 6, 0, 0, 0, 173, 90, 4, 0, 33, 0, ++ 0, 64, 8, 0, 104, 0, 185, 90, 4, 0, 34, 0, 0, 0, 6, 0, 0, 0, 203, 90, ++ 4, 0, 35, 0, 0, 0, 6, 0, 0, 0, 219, 90, 4, 0, 36, 0, 0, 0, 7, 0, 0, ++ 0, 237, 90, 4, 0, 31, 0, 0, 0, 7, 0, 0, 0, 253, 90, 4, 0, 32, 0, 0, ++ 0, 7, 0, 0, 0, 13, 91, 4, 0, 37, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 105, 100, 115, 117, 112, 0, 116, 112, 99, 0, 116, ++ 120, 112, 119, 114, 95, 116, 97, 114, 103, 101, 116, 95, 109, 97, 120, ++ 0, 0, 51, 228, 136, 0, 4, 0, 0, 0, 3, 0, 0, 0, 254, 92, 4, 0, 6, 0, ++ 0, 4, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 116, 120, 99, ++ 0, 119, 97, 112, 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 16, 22, 0, 0, 128, 56, 1, 0, 115, 100, 112, 99, 109, 100, 101, 118, ++ 0, 0, 0, 0, 0, 0, 0, 0, 172, 93, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, 190, 128, 0, 233, 202, ++ 128, 0, 253, 202, 128, 0, 201, 63, 0, 0, 93, 190, 128, 0, 249, 63, 0, ++ 0, 37, 188, 128, 0, 0, 0, 0, 0, 249, 202, 128, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 57, 137, 4, 0, 21, 137, 4, 0, 255, 136, 4, 0, 51, 64, 0, 0, 0, ++ 0, 0, 0, 73, 203, 128, 0, 43, 64, 0, 0, 101, 203, 128, 0, 133, 203, ++ 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 254, 0, 0, 0, 253, 255, 255, 255, 2, ++ 0, 0, 0, 242, 209, 23, 107, 71, 66, 44, 225, 229, 230, 188, 248, 242, ++ 64, 164, 99, 129, 125, 3, 119, 160, 51, 235, 45, 69, 57, 161, 244, 150, ++ 194, 152, 216, 34, 202, 135, 170, 55, 5, 139, 190, 30, 199, 177, 142, ++ 116, 173, 32, 243, 98, 59, 29, 110, 152, 155, 167, 139, 224, 65, 247, ++ 89, 56, 42, 84, 130, 93, 242, 2, 85, 108, 41, 85, 191, 56, 94, 84, 58, ++ 183, 10, 118, 114, 74, 222, 23, 54, 111, 44, 38, 150, 191, 152, 158, ++ 93, 41, 220, 146, 146, 189, 29, 244, 248, 124, 20, 154, 40, 19, 49, ++ 218, 233, 192, 184, 240, 181, 206, 177, 96, 10, 157, 129, 126, 29, 124, ++ 29, 67, 122, 95, 14, 234, 144, 43, 131, 36, 128, 79, 193, 223, 11, 43, ++ 77, 0, 153, 61, 251, 215, 167, 47, 67, 24, 6, 173, 47, 228, 120, 196, ++ 238, 27, 39, 74, 14, 160, 176, 255, 255, 255, 255, 0, 0, 0, 0, 255, ++ 255, 255, 255, 255, 255, 255, 255, 188, 230, 250, 173, 167, 23, 158, ++ 132, 243, 185, 202, 194, 252, 99, 37, 81, 16, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 20, 222, 249, 222, 162, 247, 156, 214, 88, 18, ++ 99, 26, 92, 245, 211, 237, 0, 0, 0, 81, 149, 62, 185, 97, 142, 28, 154, ++ 31, 146, 154, 33, 160, 182, 133, 64, 238, 162, 218, 114, 91, 153, 179, ++ 21, 243, 184, 180, 137, 145, 142, 241, 9, 225, 86, 25, 57, 81, 236, ++ 126, 147, 123, 22, 82, 192, 189, 59, 177, 191, 7, 53, 115, 223, 136, ++ 61, 44, 52, 241, 239, 69, 31, 212, 107, 80, 63, 0, 226, 66, 227, 79, ++ 155, 127, 26, 254, 74, 235, 231, 142, 22, 158, 15, 124, 87, 51, 206, ++ 43, 206, 94, 49, 107, 104, 64, 182, 203, 245, 81, 191, 55, 3, 0, 0, ++ 0, 9, 2, 0, 0, 68, 1, 0, 0, 127, 115, 0, 0, 205, 118, 0, 0, 31, 118, ++ 0, 0, 27, 117, 0, 0, 163, 116, 0, 0, 20, 98, 4, 0, 144, 97, 4, 0, 76, ++ 96, 4, 0, 184, 95, 4, 0, 252, 96, 4, 0, 253, 255, 255, 255, 196, 94, ++ 4, 0, 128, 1, 0, 0, 128, 255, 255, 255, 160, 255, 255, 255, 32, 0, 0, ++ 0, 2, 0, 0, 0, 255, 255, 255, 255, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 161, 25, 174, 32, 180, 134, 160, 184, 44, 221, 30, 224, 76, 209, ++ 72, 119, 126, 77, 61, 146, 178, 97, 124, 109, 162, 197, 233, 41, 217, ++ 211, 206, 126, 198, 0, 0, 0, 183, 6, 142, 133, 205, 233, 4, 4, 102, ++ 203, 62, 158, 66, 180, 149, 35, 57, 129, 100, 156, 33, 181, 63, 5, 96, ++ 175, 40, 248, 186, 61, 77, 107, 119, 94, 75, 161, 40, 89, 231, 239, ++ 39, 193, 29, 254, 222, 168, 255, 162, 193, 179, 72, 51, 155, 66, 106, ++ 133, 49, 126, 126, 249, 102, 189, 229, 194, 0, 1, 0, 0, 32, 255, 255, ++ 255, 192, 0, 0, 0, 96, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, ++ 32, 1, 0, 0, 41, 115, 0, 0, 233, 114, 0, 0, 143, 118, 0, 0, 165, 117, ++ 0, 0, 7, 116, 0, 0, 252, 95, 4, 0, 120, 95, 4, 0, 132, 94, 4, 0, 228, ++ 93, 4, 0, 8, 95, 4, 0, 253, 255, 255, 255, 244, 97, 4, 0, 0, 0, 1, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 250, 81, 134, 135, 131, 191, 47, 150, 107, 127, 204, ++ 1, 72, 247, 9, 165, 208, 59, 181, 201, 184, 137, 156, 71, 174, 187, ++ 111, 183, 30, 145, 56, 100, 9, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 254, 255, 255, 255, 255, ++ 0, 0, 0, 0, 0, 0, 0, 0, 255, 255, 255, 255, 4, 0, 0, 0, 255, 0, 0, 0, ++ 32, 8, 0, 0, 35, 109, 0, 0, 229, 108, 0, 0, 237, 117, 0, 0, 217, 116, ++ 0, 0, 91, 116, 0, 0, 216, 93, 4, 0, 112, 97, 4, 0, 164, 94, 4, 0, 212, ++ 97, 4, 0, 152, 95, 4, 0, 6, 109, 7, 0, 100, 94, 4, 0, 24, 1, 0, 0, 120, ++ 106, 41, 57, 4, 192, 59, 154, 180, 95, 138, 92, 217, 27, 125, 44, 73, ++ 68, 245, 152, 104, 68, 155, 87, 23, 189, 175, 23, 44, 102, 62, 39, 153, ++ 114, 238, 151, 64, 38, 244, 94, 1, 185, 80, 197, 97, 7, 173, 63, 134, ++ 112, 60, 53, 64, 194, 114, 162, 118, 148, 190, 136, 80, 102, 209, 159, ++ 179, 49, 47, 167, 226, 62, 231, 228, 152, 142, 5, 107, 227, 248, 45, ++ 25, 24, 29, 156, 110, 254, 129, 65, 18, 3, 20, 8, 143, 80, 19, 135, ++ 90, 198, 86, 57, 141, 138, 46, 209, 157, 42, 133, 200, 237, 211, 236, ++ 42, 239, 127, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 237, 0, 0, 1, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 90, 198, 53, 216, 170, 58, ++ 147, 231, 179, 235, 189, 85, 118, 152, 134, 188, 101, 29, 6, 176, 204, ++ 83, 176, 246, 59, 206, 60, 62, 39, 210, 96, 75, 9, 2, 0, 0, 2, 0, 0, ++ 0, 2, 0, 0, 0, 128, 1, 0, 0, 48, 1, 0, 0, 153, 115, 0, 0, 231, 118, ++ 0, 0, 81, 118, 0, 0, 93, 117, 0, 0, 179, 115, 0, 0, 100, 95, 4, 0, 144, ++ 96, 4, 0, 88, 98, 4, 0, 4, 94, 4, 0, 52, 94, 4, 0, 253, 255, 255, 255, ++ 64, 97, 4, 0, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, ++ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 199, ++ 99, 77, 129, 244, 55, 45, 223, 88, 26, 13, 178, 72, 176, 167, 122, 236, ++ 236, 25, 106, 204, 197, 41, 115, 137, 148, 4, 0, 221, 148, 4, 0, 0, ++ 0, 0, 0, 133, 148, 4, 0, 153, 152, 4, 0, 105, 150, 4, 0, 205, 149, 4, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 57, 150, ++ 4, 0, 0, 0, 0, 0, 29, 30, 28, 11, 119, 108, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 240, 98, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 241, 238, 4, 0, 237, 154, 129, 0, ++ 177, 150, 129, 0, 49, 198, 0, 0, 0, 0, 0, 0, 133, 153, 129, 0, 0, 0, ++ 0, 0, 205, 154, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, ++ 0, 1, 0, 3, 0, 3, 0, 6, 0, 0, 0, 3, 0, 3, 0, 3, 0, 14, 0, 13, 0, 14, ++ 0, 14, 0, 14, 0, 2, 0, 9, 0, 12, 0, 10, 0, 8, 0, 13, 0, 1, 0, 9, 0, ++ 12, 0, 10, 0, 8, 0, 13, 0, 1, 0, 9, 0, 12, 0, 10, 0, 8, 0, 13, 0, 1, ++ 0, 9, 0, 12, 0, 10, 0, 8, 0, 13, 0, 1, 0, 10, 0, 13, 0, 11, 0, 9, 0, ++ 14, 0, 2, 0, 10, 0, 13, 0, 11, 0, 9, 0, 14, 0, 2, 0, 9, 0, 57, 0, 22, ++ 0, 14, 0, 14, 0, 5, 0, 9, 0, 57, 0, 22, 0, 14, 0, 14, 0, 5, 0, 10, 0, ++ 13, 0, 11, 0, 9, 0, 14, 0, 4, 0, 10, 0, 13, 0, 11, 0, 9, 0, 14, 0, 2, ++ 0, 10, 0, 13, 0, 11, 0, 9, 0, 14, 0, 2, 0, 20, 0, 191, 0, 192, 0, 21, ++ 0, 17, 0, 5, 0, 20, 0, 191, 0, 192, 0, 21, 0, 17, 0, 5, 0, 20, 0, 191, ++ 0, 192, 0, 21, 0, 17, 0, 5, 0, 20, 0, 191, 0, 192, 0, 21, 0, 17, 0, ++ 5, 0, 20, 0, 191, 0, 192, 0, 21, 0, 17, 0, 5, 0, 9, 0, 57, 0, 22, 0, ++ 14, 0, 14, 0, 5, 0, 9, 0, 57, 0, 22, 0, 14, 0, 14, 0, 5, 0, 20, 0, 191, ++ 0, 192, 0, 21, 0, 17, 0, 5, 0, 9, 0, 57, 0, 22, 0, 14, 0, 14, 0, 5, ++ 0, 9, 0, 57, 0, 22, 0, 14, 0, 14, 0, 5, 0, 150, 0, 222, 0, 223, 0, 21, ++ 0, 17, 0, 5, 0, 20, 0, 191, 0, 192, 0, 21, 0, 17, 0, 5, 0, 9, 0, 57, ++ 0, 22, 0, 14, 0, 14, 0, 5, 0, 9, 0, 57, 0, 22, 0, 14, 0, 14, 0, 5, 0, ++ 9, 0, 97, 0, 22, 0, 14, 0, 14, 0, 5, 0, 9, 0, 57, 0, 22, 0, 14, 0, 14, ++ 0, 5, 0, 12, 0, 182, 0, 25, 0, 17, 0, 17, 0, 8, 0, 9, 0, 57, 0, 22, ++ 0, 14, 0, 14, 0, 5, 0, 9, 0, 182, 0, 25, 0, 17, 0, 17, 0, 8, 0, 9, 0, ++ 182, 0, 25, 0, 17, 0, 17, 0, 8, 0, 9, 0, 182, 0, 25, 0, 17, 0, 17, 0, ++ 8, 0, 9, 0, 57, 0, 22, 0, 14, 0, 14, 0, 5, 0, 9, 0, 182, 0, 25, 0, 17, ++ 0, 17, 0, 8, 0, 9, 0, 57, 0, 22, 0, 14, 0, 14, 0, 5, 0, 9, 0, 182, 0, ++ 25, 0, 17, 0, 17, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 40, 35, 64, 31, 160, ++ 15, 184, 11, 24, 252, 48, 248, 144, 232, 168, 228, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 120, 5, 0, 0, 240, 241, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 40, 35, 0, 0, 160, 15, 0, 0, ++ 24, 252, 0, 0, 144, 232, 0, 0, 0, 0, 112, 23, 0, 0, 232, 3, 0, 0, 96, ++ 240, 0, 0, 216, 220, 0, 25, 0, 0, 120, 5, 0, 0, 240, 241, 0, 0, 0, 0, ++ 0, 0, 57, 51, 45, 40, 36, 32, 29, 0, 0, 0, 0, 0, 0, 0, 0, 0, 255, 1, ++ 0, 0, 0, 0, 0, 0, 0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 255, 1, 0, 0, ++ 0, 0, 9, 0, 1, 0, 0, 0, 164, 0, 0, 0, 45, 1, 45, 1, 0, 0, 226, 1, 227, ++ 254, 128, 0, 0, 1, 128, 0, 5, 1, 81, 254, 64, 0, 128, 0, 64, 0, 8, 0, ++ 2, 0, 0, 0, 119, 1, 22, 255, 37, 0, 76, 0, 37, 0, 31, 3, 116, 254, 32, ++ 0, 20, 0, 32, 0, 236, 2, 242, 254, 128, 0, 226, 255, 128, 0, 8, 0, 3, ++ 0, 0, 0, 119, 1, 22, 255, 37, 0, 76, 0, 37, 0, 31, 3, 116, 254, 32, ++ 0, 20, 0, 32, 0, 236, 2, 242, 254, 148, 0, 221, 255, 148, 0, 8, 0, 4, ++ 0, 0, 0, 51, 1, 174, 7, 53, 0, 106, 0, 53, 0, 11, 3, 133, 6, 53, 0, ++ 246, 7, 53, 0, 253, 2, 43, 6, 212, 0, 54, 7, 212, 0, 8, 0, 5, 0, 0, ++ 0, 197, 1, 29, 255, 32, 0, 64, 0, 32, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, ++ 0, 107, 3, 130, 254, 20, 0, 41, 0, 20, 0, 8, 0, 6, 0, 0, 0, 119, 1, ++ 22, 255, 37, 0, 76, 0, 37, 0, 31, 3, 116, 254, 32, 0, 20, 0, 32, 0, ++ 236, 2, 242, 254, 114, 0, 229, 255, 114, 0, 8, 0, 7, 0, 0, 0, 170, 0, ++ 0, 0, 211, 1, 210, 1, 0, 0, 153, 1, 201, 6, 128, 0, 0, 1, 128, 0, 98, ++ 0, 66, 6, 36, 0, 72, 0, 36, 0, 9, 0, 8, 0, 0, 0, 174, 0, 0, 0, 121, ++ 1, 120, 1, 0, 0, 194, 1, 196, 6, 128, 0, 0, 1, 128, 0, 158, 0, 65, 6, ++ 36, 0, 72, 0, 36, 0, 9, 0, 9, 0, 0, 0, 178, 0, 0, 0, 63, 1, 63, 1, 0, ++ 0, 223, 1, 192, 6, 128, 0, 0, 1, 128, 0, 202, 0, 65, 6, 36, 0, 72, 0, ++ 36, 0, 9, 0, 10, 0, 0, 0, 162, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, ++ 255, 1, 0, 0, 0, 0, 120, 2, 160, 254, 0, 1, 255, 1, 0, 1, 8, 0, 12, ++ 0, 0, 0, 138, 1, 22, 255, 29, 0, 58, 0, 29, 0, 32, 3, 118, 254, 24, ++ 0, 48, 0, 24, 0, 68, 3, 160, 254, 38, 0, 76, 0, 38, 0, 8, 0, 13, 0, ++ 0, 0, 174, 0, 0, 0, 211, 1, 210, 1, 0, 0, 183, 1, 192, 254, 120, 0, ++ 240, 0, 120, 0, 85, 0, 89, 254, 36, 0, 72, 0, 36, 0, 9, 0, 14, 0, 0, ++ 0, 177, 0, 0, 0, 182, 1, 181, 1, 0, 0, 201, 1, 188, 254, 120, 0, 240, ++ 0, 120, 0, 77, 0, 101, 254, 35, 0, 70, 0, 35, 0, 9, 0, 15, 0, 0, 0, ++ 186, 0, 0, 0, 63, 1, 63, 1, 0, 0, 11, 2, 185, 254, 120, 0, 240, 0, 120, ++ 0, 174, 0, 95, 254, 35, 0, 70, 0, 35, 0, 9, 0, 16, 0, 0, 0, 0, 0, 0, ++ 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 255, ++ 1, 0, 0, 0, 0, 9, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, ++ 0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 236, 1, 20, 0, 0, 0, 9, 0, 18, ++ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 255, 1, 0, 0, 0, ++ 0, 0, 0, 0, 0, 36, 1, 36, 1, 0, 0, 9, 0, 102, 0, 70, 11, 108, 0, 165, ++ 10, 115, 0, 12, 10, 122, 0, 124, 9, 129, 0, 244, 8, 137, 0, 116, 8, ++ 145, 0, 251, 7, 153, 0, 137, 7, 162, 0, 29, 7, 172, 0, 183, 6, 182, ++ 0, 87, 6, 193, 0, 252, 5, 204, 0, 166, 5, 216, 0, 86, 5, 229, 0, 9, ++ 5, 243, 0, 193, 4, 1, 1, 125, 4, 16, 1, 61, 4, 33, 1, 0, 4, 50, 1, 199, ++ 3, 68, 1, 145, 3, 87, 1, 94, 3, 107, 1, 45, 3, 129, 1, 0, 3, 152, 1, ++ 213, 2, 176, 1, 172, 2, 201, 1, 134, 2, 229, 1, 98, 2, 1, 2, 64, 2, ++ 32, 2, 32, 2, 64, 2, 1, 2, 98, 2, 229, 1, 134, 2, 201, 1, 172, 2, 176, ++ 1, 213, 2, 152, 1, 0, 3, 129, 1, 45, 3, 107, 1, 94, 3, 87, 1, 145, 3, ++ 68, 1, 199, 3, 50, 1, 0, 4, 33, 1, 61, 4, 16, 1, 125, 4, 1, 1, 193, ++ 4, 243, 0, 9, 5, 229, 0, 86, 5, 216, 0, 166, 5, 204, 0, 252, 5, 193, ++ 0, 87, 6, 182, 0, 183, 6, 172, 0, 29, 7, 162, 0, 137, 7, 153, 0, 251, ++ 7, 145, 0, 116, 8, 137, 0, 244, 8, 129, 0, 124, 9, 122, 0, 12, 10, 115, ++ 0, 165, 10, 108, 0, 70, 11, 102, 0, 241, 11, 97, 0, 166, 12, 91, 0, ++ 102, 13, 86, 0, 49, 14, 81, 0, 9, 15, 77, 0, 112, 23, 0, 0, 232, 3, ++ 0, 0, 96, 240, 64, 31, 216, 220, 184, 11, 0, 0, 48, 248, 88, 27, 168, ++ 228, 208, 7, 0, 0, 72, 244, 0, 0, 192, 224, 0, 0, 0, 0, 0, 0, 64, 31, ++ 0, 0, 184, 11, 0, 0, 48, 248, 0, 0, 0, 0, 0, 0, 59, 117, 117, 59, 117, ++ 117, 43, 43, 117, 59, 91, 117, 43, 43, 97, 59, 91, 97, 0, 0, 156, 230, ++ 0, 0, 0, 0, 40, 35, 0, 0, 160, 15, 0, 0, 24, 252, 0, 0, 144, 232, 0, ++ 0, 0, 0, 64, 31, 0, 0, 184, 11, 0, 0, 48, 248, 0, 0, 168, 228, 0, 25, ++ 0, 0, 120, 5, 0, 0, 240, 241, 0, 0, 0, 0, 0, 0, 32, 28, 156, 230, 152, ++ 8, 0, 0, 16, 245, 0, 0, 136, 225, 0, 0, 0, 25, 0, 0, 120, 5, 0, 0, 240, ++ 241, 64, 31, 104, 222, 184, 11, 224, 21, 48, 248, 88, 2, 168, 228, 208, ++ 238, 0, 0, 72, 219, 72, 38, 192, 18, 0, 0, 224, 227, 0, 0, 125, 0, 61, ++ 0, 38, 0, 250, 0, 54, 0, 46, 0, 44, 1, 51, 0, 49, 0, 25, 0, 64, 0, 32, ++ 0, 50, 0, 64, 0, 34, 0, 225, 0, 56, 0, 44, 0, 112, 23, 0, 0, 232, 3, ++ 0, 0, 96, 240, 0, 0, 216, 220, 0, 0, 0, 0, 0, 0, 88, 27, 0, 0, 208, ++ 7, 112, 23, 72, 244, 232, 3, 192, 224, 96, 240, 0, 0, 216, 220, 64, ++ 31, 0, 0, 184, 11, 0, 0, 48, 248, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, ++ 0, 164, 255, 45, 1, 45, 1, 0, 0, 122, 1, 72, 255, 64, 0, 128, 0, 64, ++ 0, 248, 1, 128, 255, 64, 0, 128, 0, 64, 0, 8, 0, 1, 0, 0, 0, 165, 0, ++ 164, 255, 150, 0, 150, 0, 0, 0, 249, 1, 72, 255, 64, 0, 128, 0, 64, ++ 0, 252, 1, 128, 255, 64, 0, 128, 0, 64, 0, 8, 0, 2, 0, 1, 0, 159, 1, ++ 82, 7, 64, 0, 128, 0, 64, 0, 24, 3, 120, 6, 192, 0, 128, 1, 192, 0, ++ 10, 3, 46, 6, 64, 0, 128, 0, 64, 0, 8, 0, 3, 0, 1, 0, 46, 1, 49, 7, ++ 129, 0, 2, 1, 129, 0, 146, 2, 184, 6, 205, 0, 154, 1, 205, 0, 242, 2, ++ 224, 6, 170, 0, 84, 1, 170, 0, 8, 0, 20, 0, 1, 0, 104, 1, 92, 255, 242, ++ 0, 198, 254, 242, 0, 240, 2, 184, 254, 205, 0, 53, 255, 205, 0, 255, ++ 2, 224, 254, 253, 0, 183, 0, 253, 0, 8, 0, 21, 0, 1, 0, 104, 1, 92, ++ 7, 149, 0, 82, 7, 149, 0, 240, 2, 184, 6, 205, 0, 92, 7, 205, 0, 255, ++ 2, 224, 6, 0, 1, 17, 1, 0, 1, 8, 0, 22, 0, 1, 0, 104, 1, 92, 7, 98, ++ 0, 156, 7, 98, 0, 240, 2, 184, 6, 205, 0, 132, 7, 205, 0, 255, 2, 224, ++ 6, 0, 1, 96, 1, 0, 1, 8, 0, 23, 0, 1, 0, 94, 1, 92, 7, 116, 0, 174, ++ 7, 116, 0, 240, 2, 184, 6, 205, 0, 216, 7, 205, 0, 255, 2, 224, 6, 129, ++ 0, 235, 0, 129, 0, 8, 0, 24, 0, 1, 0, 69, 1, 92, 7, 32, 0, 40, 0, 32, ++ 0, 244, 2, 184, 6, 0, 1, 215, 1, 0, 1, 254, 2, 224, 6, 6, 1, 86, 7, ++ 6, 1, 8, 0, 25, 0, 1, 0, 43, 1, 92, 7, 51, 0, 64, 0, 51, 0, 224, 2, ++ 184, 6, 0, 1, 215, 1, 0, 1, 253, 2, 224, 6, 6, 1, 86, 7, 6, 1, 8, 0, ++ 26, 0, 1, 0, 21, 1, 151, 7, 39, 0, 117, 0, 88, 0, 125, 2, 46, 7, 64, ++ 0, 192, 0, 144, 0, 102, 2, 72, 7, 128, 0, 128, 1, 32, 1, 8, 0, 27, 0, ++ 1, 0, 245, 0, 151, 7, 49, 0, 147, 0, 110, 0, 114, 2, 46, 7, 162, 0, ++ 229, 1, 107, 1, 101, 2, 72, 7, 62, 0, 186, 0, 139, 0, 8, 0, 28, 0, 1, ++ 0, 104, 1, 92, 7, 149, 0, 82, 7, 149, 0, 240, 2, 184, 6, 205, 0, 92, ++ 7, 205, 0, 255, 2, 224, 6, 114, 0, 121, 0, 114, 0, 8, 0, 30, 0, 1, 0, ++ 46, 1, 49, 7, 61, 0, 122, 0, 61, 0, 146, 2, 184, 6, 205, 0, 154, 1, ++ 205, 0, 242, 2, 224, 6, 170, 0, 84, 1, 170, 0, 8, 0, 31, 0, 1, 0, 63, ++ 1, 25, 7, 234, 1, 0, 0, 234, 1, 187, 2, 142, 6, 68, 1, 0, 0, 68, 1, ++ 242, 2, 224, 6, 114, 0, 0, 0, 114, 0, 8, 0, 40, 0, 1, 0, 104, 1, 92, ++ 7, 242, 0, 198, 6, 242, 0, 240, 2, 184, 6, 205, 0, 53, 7, 205, 0, 255, ++ 2, 224, 6, 255, 1, 114, 1, 255, 1, 8, 0, 50, 0, 1, 0, 217, 1, 12, 255, ++ 32, 0, 64, 0, 32, 0, 162, 3, 65, 254, 16, 0, 32, 0, 16, 0, 161, 3, 88, ++ 254, 16, 0, 32, 0, 16, 0, 8, 0, 112, 23, 156, 230, 232, 3, 0, 0, 96, ++ 240, 0, 0, 216, 220, 0, 0, 0, 0, 0, 0, 88, 27, 0, 0, 208, 7, 64, 31, ++ 72, 244, 184, 11, 192, 224, 48, 248, 0, 0, 168, 228, 64, 31, 0, 0, 184, ++ 11, 0, 0, 48, 248, 0, 0, 0, 0, 0, 0, 32, 28, 0, 0, 152, 8, 0, 0, 16, ++ 245, 0, 0, 136, 225, 0, 0, 0, 25, 0, 0, 120, 5, 0, 0, 240, 241, 112, ++ 23, 104, 222, 232, 3, 224, 21, 96, 240, 88, 2, 216, 220, 208, 238, 0, ++ 0, 72, 219, 72, 38, 192, 18, 0, 0, 224, 227, 0, 0, 32, 28, 0, 0, 152, ++ 8, 0, 0, 16, 245, 64, 31, 136, 225, 184, 11, 0, 25, 48, 248, 120, 5, ++ 168, 228, 240, 241, 0, 0, 104, 222, 0, 0, 224, 21, 0, 0, 88, 2, 0, 0, ++ 208, 238, 0, 0, 72, 219, 72, 38, 192, 18, 0, 0, 224, 227, 0, 0, 0, 2, ++ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 45, 233, 248, 67, 5, 70, 136, 70, 199, 243, 90, ++ 243, 0, 33, 40, 70, 199, 243, 98, 244, 4, 70, 40, 70, 110, 105, 175, ++ 105, 191, 243, 26, 246, 10, 46, 129, 70, 22, 217, 15, 46, 22, 208, 40, ++ 70, 199, 243, 114, 240, 20, 46, 5, 70, 3, 217, 163, 104, 35, 240, 8, ++ 3, 163, 96, 163, 104, 20, 46, 67, 240, 1, 3, 163, 96, 20, 217, 163, ++ 104, 67, 240, 8, 3, 163, 96, 15, 224, 2, 46, 15, 217, 40, 70, 199, 243, ++ 183, 240, 212, 248, 164, 48, 5, 70, 35, 240, 255, 3, 67, 240, 2, 3, ++ 196, 248, 164, 48, 2, 35, 3, 224, 1, 35, 1, 224, 16, 77, 48, 35, 162, ++ 104, 210, 7, 7, 212, 7, 240, 24, 2, 8, 42, 12, 191, 181, 251, 243, 245, ++ 79, 244, 225, 21, 7, 240, 3, 7, 0, 38, 11, 224, 4, 245, 64, 115, 184, ++ 241, 0, 15, 5, 208, 48, 2, 24, 24, 73, 70, 42, 70, 0, 35, 192, 71, 1, ++ 54, 190, 66, 241, 219, 189, 232, 248, 131, 0, 191, 0, 198, 62, 5, 45, ++ 233, 248, 67, 22, 70, 152, 70, 4, 70, 13, 70, 199, 243, 182, 240, 0, ++ 33, 7, 70, 32, 70, 199, 243, 255, 243, 0, 34, 129, 70, 19, 70, 19, 73, ++ 136, 24, 64, 104, 176, 185, 12, 34, 83, 67, 202, 24, 206, 80, 85, 96, ++ 194, 248, 8, 128, 32, 70, 199, 243, 226, 242, 217, 248, 36, 48, 12, ++ 77, 30, 67, 46, 96, 32, 70, 199, 243, 218, 242, 43, 104, 1, 37, 201, ++ 248, 36, 48, 4, 224, 1, 51, 12, 50, 5, 43, 224, 209, 0, 37, 32, 70, ++ 57, 70, 199, 243, 216, 243, 40, 70, 189, 232, 248, 131, 0, 191, 36, ++ 109, 4, 0, 28, 7, 0, 0, 56, 181, 18, 76, 0, 33, 72, 34, 32, 70, 188, ++ 243, 221, 242, 16, 74, 1, 35, 132, 232, 12, 0, 0, 37, 14, 73, 31, 34, ++ 4, 241, 12, 0, 188, 243, 178, 243, 132, 248, 43, 80, 193, 243, 8, 240, ++ 79, 244, 0, 35, 163, 99, 79, 244, 0, 3, 227, 99, 7, 75, 32, 99, 35, ++ 100, 7, 75, 101, 99, 219, 105, 101, 100, 163, 96, 56, 189, 0, 191, 128, ++ 109, 4, 0, 68, 69, 66, 71, 211, 22, 4, 0, 128, 20, 8, 0, 220, 109, 4, ++ 0, 67, 105, 20, 43, 1, 221, 196, 247, 7, 187, 112, 71, 67, 105, 16, ++ 181, 10, 43, 4, 70, 10, 221, 6, 73, 1, 34, 3, 70, 255, 247, 132, 255, ++ 32, 70, 1, 33, 189, 232, 16, 64, 7, 240, 238, 185, 16, 189, 0, 191, ++ 9, 37, 0, 0, 195, 105, 16, 181, 89, 7, 4, 70, 12, 213, 7, 75, 0, 34, ++ 25, 104, 199, 243, 210, 241, 5, 73, 32, 70, 16, 34, 35, 70, 189, 232, ++ 16, 64, 255, 247, 104, 191, 16, 189, 0, 191, 252, 109, 4, 0, 185, 121, ++ 128, 0, 19, 75, 19, 181, 19, 96, 19, 70, 1, 224, 17, 76, 28, 96, 4, ++ 51, 173, 241, 124, 4, 163, 66, 248, 211, 196, 28, 36, 240, 3, 4, 13, ++ 75, 9, 27, 13, 72, 25, 96, 0, 35, 3, 96, 12, 72, 8, 57, 3, 96, 11, 72, ++ 132, 232, 10, 0, 3, 96, 10, 72, 2, 96, 10, 72, 2, 245, 0, 82, 2, 96, ++ 9, 74, 19, 96, 186, 247, 64, 255, 68, 96, 28, 189, 75, 65, 84, 83, 44, ++ 7, 0, 0, 76, 7, 0, 0, 120, 7, 0, 0, 108, 109, 4, 0, 208, 109, 4, 0, ++ 120, 109, 4, 0, 40, 7, 0, 0, 8, 181, 0, 33, 20, 32, 186, 247, 65, 255, ++ 5, 75, 0, 33, 24, 96, 20, 34, 188, 243, 63, 242, 189, 232, 8, 64, 192, ++ 243, 227, 181, 0, 191, 100, 7, 0, 0, 45, 233, 240, 71, 77, 28, 41, 70, ++ 130, 70, 5, 240, 245, 250, 19, 76, 32, 96, 0, 179, 79, 234, 133, 9, ++ 72, 70, 0, 33, 186, 247, 36, 255, 15, 79, 128, 70, 56, 96, 15, 78, 104, ++ 177, 74, 70, 0, 33, 188, 243, 31, 242, 32, 104, 0, 33, 188, 243, 191, ++ 245, 59, 104, 0, 34, 26, 96, 53, 96, 189, 232, 240, 135, 80, 70, 33, ++ 104, 5, 240, 41, 251, 198, 248, 0, 128, 196, 248, 0, 128, 189, 232, ++ 240, 135, 0, 191, 48, 7, 0, 0, 32, 7, 0, 0, 60, 7, 0, 0, 240, 181, 24, ++ 79, 133, 176, 15, 33, 56, 104, 5, 240, 23, 250, 15, 40, 3, 144, 62, ++ 70, 36, 209, 132, 32, 0, 33, 186, 247, 241, 254, 18, 76, 32, 96, 208, ++ 177, 0, 33, 132, 34, 188, 243, 238, 241, 0, 37, 1, 35, 4, 170, 66, 248, ++ 4, 61, 0, 149, 1, 149, 56, 104, 33, 104, 79, 244, 240, 99, 5, 240, 41, ++ 250, 1, 48, 32, 104, 3, 208, 40, 33, 193, 247, 223, 253, 5, 224, 186, ++ 247, 92, 255, 37, 96, 48, 104, 5, 240, 12, 250, 5, 176, 240, 189, 252, ++ 109, 4, 0, 116, 7, 0, 0, 177, 245, 224, 111, 115, 181, 4, 70, 14, 70, ++ 21, 70, 6, 209, 3, 105, 0, 145, 0, 33, 1, 145, 30, 104, 10, 70, 12, ++ 224, 13, 75, 0, 34, 24, 104, 199, 243, 153, 242, 1, 70, 128, 177, 35, ++ 105, 0, 34, 0, 150, 1, 146, 30, 104, 32, 70, 43, 70, 176, 71, 56, 177, ++ 6, 75, 160, 97, 26, 104, 101, 97, 34, 98, 28, 96, 0, 32, 1, 224, 79, ++ 240, 255, 48, 124, 189, 0, 191, 56, 7, 0, 0, 96, 109, 4, 0, 45, 233, ++ 248, 67, 16, 32, 12, 70, 0, 33, 145, 70, 152, 70, 186, 247, 147, 254, ++ 5, 70, 32, 179, 20, 78, 48, 104, 198, 243, 47, 247, 9, 155, 7, 70, 35, ++ 185, 48, 104, 33, 70, 74, 70, 199, 243, 103, 242, 48, 104, 198, 243, ++ 238, 247, 1, 35, 131, 64, 8, 154, 235, 96, 170, 96, 11, 74, 197, 248, ++ 4, 128, 17, 104, 21, 96, 9, 74, 41, 96, 17, 104, 48, 104, 11, 67, 19, ++ 96, 57, 70, 199, 243, 95, 242, 0, 32, 189, 232, 248, 131, 111, 240, ++ 26, 0, 189, 232, 248, 131, 56, 7, 0, 0, 112, 7, 0, 0, 72, 7, 0, 0, 19, ++ 181, 0, 33, 4, 70, 199, 243, 77, 242, 23, 75, 24, 96, 23, 75, 0, 245, ++ 112, 96, 24, 96, 99, 105, 34, 43, 18, 221, 227, 105, 88, 6, 15, 213, ++ 64, 246, 39, 1, 0, 34, 32, 70, 198, 243, 163, 247, 1, 70, 32, 70, 199, ++ 243, 55, 242, 14, 75, 0, 33, 24, 96, 32, 70, 199, 243, 49, 242, 0, 32, ++ 79, 244, 0, 97, 2, 70, 10, 75, 0, 144, 1, 144, 255, 247, 156, 255, 40, ++ 177, 1, 32, 2, 176, 189, 232, 16, 64, 187, 247, 121, 187, 2, 176, 16, ++ 189, 0, 191, 92, 7, 0, 0, 4, 110, 4, 0, 104, 7, 0, 0, 165, 121, 128, ++ 0, 115, 181, 55, 75, 55, 76, 1, 147, 55, 75, 0, 33, 32, 34, 32, 70, ++ 29, 104, 38, 105, 188, 243, 30, 241, 1, 35, 35, 96, 51, 75, 38, 97, ++ 27, 104, 227, 97, 69, 248, 4, 76, 0, 240, 72, 252, 173, 245, 254, 81, ++ 60, 57, 10, 70, 46, 72, 255, 247, 139, 254, 192, 243, 95, 240, 192, ++ 243, 135, 244, 0, 240, 115, 248, 255, 247, 33, 254, 0, 32, 6, 240, 40, ++ 253, 40, 77, 41, 76, 40, 96, 7, 240, 103, 249, 32, 96, 255, 247, 148, ++ 255, 255, 247, 174, 254, 32, 104, 0, 240, 41, 251, 32, 104, 6, 240, ++ 60, 253, 34, 75, 32, 104, 26, 104, 2, 245, 128, 50, 26, 96, 32, 75, ++ 26, 104, 2, 245, 128, 50, 26, 96, 31, 75, 26, 104, 2, 245, 128, 50, ++ 26, 96, 0, 240, 192, 248, 0, 34, 28, 72, 28, 73, 192, 243, 211, 245, ++ 2, 34, 27, 72, 28, 73, 192, 243, 206, 245, 0, 34, 27, 72, 27, 73, 192, ++ 243, 201, 245, 0, 34, 26, 73, 27, 72, 192, 243, 196, 245, 32, 104, 255, ++ 247, 21, 254, 32, 104, 255, 247, 24, 254, 32, 104, 255, 247, 41, 254, ++ 40, 104, 64, 242, 143, 17, 255, 247, 134, 254, 255, 247, 184, 254, 32, ++ 104, 124, 189, 173, 222, 173, 222, 220, 109, 4, 0, 64, 93, 4, 0, 0, ++ 110, 4, 0, 180, 107, 6, 0, 252, 109, 4, 0, 56, 7, 0, 0, 44, 7, 0, 0, ++ 76, 7, 0, 0, 108, 109, 4, 0, 241, 65, 4, 0, 45, 41, 0, 0, 90, 56, 4, ++ 0, 229, 123, 128, 0, 42, 25, 4, 0, 233, 125, 128, 0, 217, 121, 128, ++ 0, 45, 25, 4, 0, 112, 71, 0, 0, 112, 181, 23, 77, 44, 104, 44, 187, ++ 176, 32, 33, 70, 186, 247, 136, 253, 40, 96, 16, 179, 33, 70, 176, 34, ++ 188, 243, 134, 240, 79, 244, 128, 96, 33, 70, 46, 104, 186, 247, 124, ++ 253, 176, 96, 40, 104, 134, 104, 30, 185, 186, 247, 254, 253, 46, 96, ++ 13, 224, 79, 244, 128, 98, 194, 96, 33, 70, 48, 70, 188, 243, 113, 240, ++ 43, 104, 6, 74, 32, 70, 19, 96, 6, 74, 83, 97, 112, 189, 79, 240, 255, ++ 48, 112, 189, 79, 240, 255, 48, 112, 189, 28, 110, 4, 0, 124, 7, 0, ++ 0, 220, 109, 4, 0, 112, 181, 24, 76, 5, 70, 35, 104, 51, 185, 23, 78, ++ 51, 104, 11, 185, 255, 247, 192, 255, 51, 104, 35, 96, 32, 104, 8, 179, ++ 0, 35, 3, 96, 192, 248, 156, 48, 67, 96, 1, 35, 128, 248, 164, 48, 107, ++ 108, 14, 59, 1, 43, 3, 217, 40, 70, 13, 73, 255, 247, 192, 252, 12, ++ 75, 154, 104, 18, 177, 34, 104, 194, 248, 156, 48, 32, 104, 1, 35, 192, ++ 248, 156, 48, 192, 243, 10, 245, 7, 72, 8, 73, 34, 104, 192, 243, 39, ++ 245, 32, 104, 112, 189, 0, 191, 124, 7, 0, 0, 28, 110, 4, 0, 233, 121, ++ 4, 0, 12, 110, 4, 0, 172, 185, 135, 0, 97, 133, 128, 0, 16, 181, 0, ++ 35, 4, 70, 16, 34, 10, 73, 255, 247, 249, 252, 0, 33, 32, 70, 196, 247, ++ 169, 249, 0, 34, 32, 70, 79, 244, 160, 81, 196, 247, 1, 249, 5, 75, ++ 0, 34, 32, 70, 154, 96, 189, 232, 16, 64, 255, 247, 169, 191, 0, 191, ++ 33, 132, 128, 0, 12, 110, 4, 0, 56, 181, 4, 70, 13, 70, 81, 177, 16, ++ 32, 192, 243, 7, 246, 4, 75, 24, 96, 32, 177, 128, 232, 48, 0, 79, 244, ++ 240, 99, 131, 96, 56, 189, 32, 110, 4, 0, 19, 75, 2, 70, 27, 104, 0, ++ 104, 16, 181, 0, 244, 112, 65, 220, 30, 9, 11, 4, 44, 8, 216, 0, 244, ++ 112, 96, 0, 10, 14, 48, 1, 35, 19, 250, 0, 240, 72, 67, 16, 189, 7, ++ 43, 12, 216, 0, 32, 16, 189, 67, 244, 128, 116, 20, 97, 20, 108, 1, ++ 51, 4, 240, 127, 4, 1, 52, 100, 3, 0, 25, 1, 224, 0, 35, 24, 70, 139, ++ 66, 240, 209, 16, 189, 216, 33, 0, 0, 3, 104, 64, 104, 24, 24, 35, 240, ++ 7, 3, 8, 51, 152, 66, 140, 191, 0, 32, 1, 32, 112, 71, 0, 0, 4, 75, ++ 5, 74, 24, 104, 144, 66, 26, 191, 0, 241, 8, 2, 26, 96, 0, 32, 112, ++ 71, 76, 93, 4, 0, 0, 24, 0, 0, 45, 233, 243, 65, 144, 232, 72, 0, 35, ++ 240, 7, 4, 8, 52, 19, 240, 7, 2, 2, 209, 157, 25, 172, 66, 74, 208, ++ 53, 70, 128, 104, 0, 34, 3, 224, 135, 92, 13, 248, 2, 112, 1, 50, 178, ++ 66, 249, 209, 158, 24, 166, 66, 4, 217, 0, 41, 61, 208, 54, 27, 149, ++ 27, 0, 224, 0, 38, 35, 240, 7, 7, 199, 235, 3, 12, 0, 34, 4, 224, 18, ++ 248, 7, 128, 0, 248, 2, 128, 1, 50, 98, 69, 248, 209, 130, 24, 0, 32, ++ 3, 224, 29, 248, 0, 112, 23, 84, 1, 48, 168, 66, 249, 209, 91, 25, 82, ++ 25, 231, 26, 0, 32, 4, 224, 19, 248, 0, 192, 2, 248, 0, 192, 1, 48, ++ 184, 66, 248, 209, 0, 46, 24, 221, 0, 171, 93, 25, 0, 35, 234, 92, 202, ++ 84, 1, 51, 179, 66, 250, 209, 201, 24, 228, 24, 0, 34, 195, 241, 8, ++ 3, 2, 224, 160, 92, 136, 84, 1, 50, 154, 66, 250, 209, 4, 224, 16, 70, ++ 3, 224, 79, 240, 255, 48, 0, 224, 0, 32, 189, 232, 252, 129, 45, 233, ++ 240, 71, 28, 75, 29, 76, 0, 38, 196, 235, 3, 8, 28, 75, 79, 234, 168, ++ 8, 3, 251, 8, 248, 71, 70, 41, 224, 35, 104, 212, 248, 8, 160, 35, 240, ++ 7, 9, 0, 37, 26, 248, 5, 32, 21, 248, 9, 48, 154, 66, 2, 208, 1, 32, ++ 187, 247, 115, 249, 1, 53, 8, 45, 243, 209, 32, 70, 255, 247, 99, 255, ++ 136, 185, 14, 75, 5, 70, 3, 235, 199, 10, 1, 55, 5, 235, 9, 3, 26, 248, ++ 5, 32, 27, 122, 154, 66, 2, 208, 1, 32, 187, 247, 93, 249, 1, 53, 8, ++ 45, 242, 209, 1, 54, 12, 52, 70, 69, 211, 219, 189, 232, 240, 135, 24, ++ 33, 0, 0, 0, 24, 0, 0, 171, 170, 170, 170, 0, 16, 0, 0, 20, 75, 45, ++ 233, 240, 71, 27, 104, 19, 77, 155, 104, 19, 79, 3, 240, 15, 9, 127, ++ 27, 1, 35, 18, 74, 3, 250, 9, 249, 187, 16, 2, 251, 3, 248, 0, 38, 68, ++ 70, 6, 224, 40, 70, 255, 247, 43, 255, 0, 185, 1, 52, 1, 54, 12, 53, ++ 70, 69, 246, 219, 34, 70, 187, 16, 79, 240, 85, 52, 4, 251, 3, 35, 7, ++ 72, 73, 70, 189, 232, 240, 71, 187, 243, 5, 183, 0, 191, 212, 33, 0, ++ 0, 0, 24, 0, 0, 24, 33, 0, 0, 171, 170, 170, 170, 63, 25, 4, 0, 65, ++ 244, 0, 49, 56, 181, 66, 99, 4, 70, 1, 99, 101, 37, 2, 224, 10, 32, ++ 192, 243, 55, 242, 35, 107, 0, 43, 1, 219, 1, 61, 247, 209, 56, 189, ++ 131, 106, 67, 240, 0, 67, 131, 98, 112, 71, 131, 106, 35, 240, 0, 67, ++ 131, 98, 112, 71, 248, 181, 134, 104, 5, 70, 1, 36, 15, 70, 6, 240, ++ 15, 6, 255, 247, 242, 255, 20, 250, 6, 246, 172, 98, 239, 98, 0, 36, ++ 5, 224, 161, 178, 40, 70, 0, 34, 255, 247, 209, 255, 1, 52, 180, 66, ++ 247, 219, 248, 189, 0, 0, 45, 233, 240, 65, 255, 247, 226, 254, 25, ++ 78, 26, 75, 223, 248, 112, 128, 25, 79, 246, 26, 25, 75, 200, 235, 7, ++ 7, 0, 40, 20, 191, 5, 70, 29, 70, 4, 70, 93, 27, 255, 247, 131, 255, ++ 71, 177, 0, 33, 64, 70, 58, 70, 187, 243, 133, 246, 64, 70, 57, 70, ++ 191, 243, 155, 246, 70, 177, 0, 33, 12, 72, 50, 70, 187, 243, 123, 246, ++ 10, 72, 49, 70, 191, 243, 145, 246, 85, 177, 0, 33, 32, 70, 42, 70, ++ 187, 243, 113, 246, 32, 70, 41, 70, 189, 232, 240, 65, 191, 243, 133, ++ 182, 189, 232, 240, 129, 0, 191, 24, 33, 0, 0, 0, 24, 0, 0, 0, 16, 0, ++ 0, 0, 24, 0, 0, 129, 8, 0, 0, 66, 75, 45, 233, 247, 79, 29, 104, 65, ++ 73, 40, 70, 255, 247, 157, 255, 64, 74, 65, 75, 169, 104, 211, 26, 64, ++ 74, 155, 16, 90, 67, 1, 146, 113, 208, 1, 32, 1, 240, 15, 1, 16, 250, ++ 1, 241, 138, 66, 1, 221, 187, 247, 136, 248, 40, 70, 255, 247, 81, 254, ++ 57, 75, 160, 241, 4, 11, 26, 104, 153, 70, 14, 42, 1, 216, 134, 16, ++ 0, 224, 1, 38, 79, 240, 0, 8, 49, 76, 76, 224, 99, 104, 1, 59, 7, 43, ++ 1, 216, 163, 104, 19, 185, 1, 32, 187, 247, 110, 248, 32, 70, 255, 247, ++ 97, 254, 56, 185, 255, 247, 106, 254, 7, 70, 32, 185, 1, 32, 187, 247, ++ 99, 248, 0, 224, 0, 39, 32, 70, 57, 70, 255, 247, 109, 254, 16, 177, ++ 1, 32, 187, 247, 89, 248, 223, 248, 124, 160, 161, 104, 34, 104, 217, ++ 248, 0, 48, 202, 235, 1, 1, 34, 240, 7, 2, 201, 16, 14, 43, 150, 191, ++ 2, 234, 11, 2, 50, 67, 70, 234, 146, 2, 137, 178, 40, 70, 255, 247, ++ 43, 255, 167, 177, 34, 104, 217, 248, 0, 48, 34, 240, 7, 2, 202, 235, ++ 7, 1, 8, 50, 201, 16, 14, 43, 152, 191, 2, 234, 11, 2, 137, 178, 140, ++ 191, 50, 67, 70, 234, 146, 2, 40, 70, 255, 247, 21, 255, 8, 241, 1, ++ 8, 12, 52, 1, 155, 152, 69, 175, 219, 40, 70, 255, 247, 29, 255, 3, ++ 176, 189, 232, 240, 79, 255, 247, 143, 190, 3, 176, 189, 232, 240, 143, ++ 212, 33, 0, 0, 0, 16, 0, 0, 24, 33, 0, 0, 0, 24, 0, 0, 171, 170, 170, ++ 170, 216, 33, 0, 0, 45, 233, 247, 67, 4, 70, 198, 243, 167, 245, 32, ++ 70, 0, 240, 136, 249, 107, 72, 186, 247, 37, 249, 32, 70, 191, 243, ++ 94, 240, 0, 245, 120, 112, 79, 244, 122, 115, 7, 48, 103, 79, 176, 251, ++ 243, 240, 56, 96, 32, 70, 191, 243, 82, 240, 100, 75, 101, 74, 195, ++ 24, 97, 105, 179, 251, 242, 243, 99, 74, 34, 41, 19, 96, 99, 78, 99, ++ 77, 4, 221, 227, 105, 88, 6, 1, 213, 51, 104, 0, 224, 43, 104, 3, 245, ++ 194, 99, 4, 51, 211, 248, 0, 224, 48, 104, 43, 104, 34, 41, 5, 221, ++ 226, 105, 82, 6, 2, 213, 0, 245, 194, 98, 1, 224, 3, 245, 194, 98, 4, ++ 50, 18, 104, 150, 69, 241, 208, 34, 41, 5, 221, 226, 105, 82, 6, 2, ++ 213, 0, 245, 194, 99, 1, 224, 3, 245, 194, 99, 4, 51, 211, 248, 0, 128, ++ 186, 247, 192, 248, 49, 104, 129, 70, 96, 105, 42, 104, 16, 37, 34, ++ 40, 5, 221, 227, 105, 91, 6, 2, 213, 1, 245, 194, 99, 1, 224, 2, 245, ++ 194, 99, 4, 51, 27, 104, 152, 69, 241, 208, 34, 40, 5, 221, 227, 105, ++ 94, 6, 2, 213, 1, 245, 194, 99, 1, 224, 2, 245, 194, 99, 4, 51, 1, 61, ++ 211, 248, 0, 128, 226, 209, 186, 247, 156, 248, 58, 104, 201, 235, 0, ++ 6, 178, 250, 130, 243, 154, 64, 25, 31, 178, 251, 246, 242, 56, 75, ++ 1, 50, 26, 96, 79, 244, 122, 115, 162, 251, 3, 35, 53, 72, 202, 64, ++ 1, 96, 193, 241, 32, 1, 19, 250, 1, 240, 128, 24, 194, 247, 96, 254, ++ 57, 104, 4, 35, 15, 224, 181, 250, 133, 242, 182, 250, 134, 240, 1, ++ 58, 130, 66, 168, 191, 2, 70, 150, 64, 149, 64, 155, 24, 182, 251, 241, ++ 242, 1, 251, 18, 102, 85, 25, 21, 240, 64, 79, 236, 208, 38, 74, 19, ++ 96, 38, 75, 64, 242, 255, 50, 29, 96, 35, 106, 0, 43, 36, 75, 200, 191, ++ 111, 240, 127, 66, 26, 96, 99, 105, 34, 43, 12, 221, 227, 105, 88, 6, ++ 9, 213, 0, 32, 64, 246, 39, 1, 2, 70, 30, 75, 0, 144, 1, 144, 255, 247, ++ 108, 251, 5, 224, 32, 70, 26, 73, 32, 34, 0, 35, 255, 247, 229, 249, ++ 0, 32, 24, 73, 188, 243, 85, 243, 24, 77, 40, 96, 120, 177, 1, 32, 191, ++ 243, 79, 247, 32, 70, 45, 104, 190, 243, 151, 247, 181, 251, 240, 240, ++ 79, 244, 122, 117, 69, 67, 17, 75, 165, 245, 250, 101, 29, 96, 189, ++ 232, 254, 131, 45, 49, 0, 0, 80, 93, 4, 0, 63, 66, 15, 0, 64, 66, 15, ++ 0, 216, 6, 0, 0, 104, 7, 0, 0, 92, 7, 0, 0, 204, 6, 0, 0, 208, 6, 0, ++ 0, 200, 6, 0, 0, 196, 6, 0, 0, 212, 6, 0, 0, 85, 128, 128, 0, 240, 136, ++ 5, 0, 180, 7, 0, 0, 176, 7, 0, 0, 13, 75, 0, 33, 26, 104, 66, 240, 16, ++ 2, 26, 96, 26, 104, 34, 244, 0, 114, 26, 96, 9, 74, 19, 104, 67, 240, ++ 128, 115, 67, 244, 128, 51, 19, 96, 7, 75, 7, 34, 26, 96, 67, 248, 4, ++ 28, 89, 104, 90, 96, 4, 75, 32, 34, 26, 96, 112, 71, 20, 237, 0, 224, ++ 252, 237, 0, 224, 36, 16, 0, 224, 0, 228, 0, 224, 112, 181, 4, 70, 14, ++ 70, 198, 243, 131, 244, 32, 70, 198, 243, 62, 242, 5, 70, 186, 247, ++ 193, 255, 64, 246, 42, 1, 2, 70, 32, 70, 198, 243, 117, 245, 130, 105, ++ 67, 105, 38, 177, 66, 240, 0, 66, 67, 240, 0, 67, 3, 224, 34, 240, 0, ++ 66, 35, 240, 0, 67, 130, 97, 41, 70, 67, 97, 32, 70, 189, 232, 112, ++ 64, 198, 243, 111, 181, 45, 233, 248, 67, 4, 70, 30, 70, 144, 70, 13, ++ 70, 198, 243, 91, 244, 32, 70, 198, 243, 22, 242, 65, 70, 50, 70, 7, ++ 70, 32, 70, 198, 243, 80, 245, 32, 70, 198, 243, 215, 242, 6, 70, 186, ++ 247, 144, 255, 64, 246, 42, 1, 2, 70, 32, 70, 198, 243, 68, 245, 79, ++ 240, 1, 8, 129, 70, 133, 177, 8, 250, 6, 245, 131, 105, 51, 234, 5, ++ 5, 2, 209, 64, 70, 185, 247, 143, 255, 1, 54, 1, 32, 176, 64, 185, 247, ++ 124, 255, 201, 248, 24, 80, 14, 224, 112, 28, 8, 250, 6, 246, 8, 250, ++ 0, 240, 185, 247, 128, 255, 64, 70, 185, 247, 111, 255, 217, 248, 24, ++ 48, 30, 67, 201, 248, 24, 96, 32, 70, 57, 70, 189, 232, 248, 67, 198, ++ 243, 40, 181, 45, 233, 248, 67, 4, 70, 198, 243, 23, 244, 32, 70, 64, ++ 246, 14, 1, 0, 34, 198, 243, 15, 245, 5, 70, 0, 40, 56, 208, 32, 70, ++ 198, 243, 7, 244, 1, 70, 24, 185, 32, 70, 10, 70, 198, 243, 183, 241, ++ 32, 70, 47, 104, 213, 248, 0, 128, 198, 243, 197, 241, 4, 40, 6, 70, ++ 5, 216, 37, 209, 8, 244, 224, 40, 184, 245, 64, 63, 32, 209, 0, 32, ++ 79, 73, 188, 243, 102, 242, 216, 185, 7, 240, 240, 7, 63, 9, 15, 224, ++ 1, 63, 7, 46, 47, 97, 8, 217, 12, 46, 6, 208, 43, 108, 3, 244, 64, 99, ++ 179, 245, 64, 111, 0, 208, 16, 177, 69, 75, 1, 32, 107, 97, 0, 47, 237, ++ 209, 213, 248, 232, 49, 35, 240, 16, 3, 197, 248, 232, 49, 186, 247, ++ 23, 255, 64, 246, 42, 1, 2, 70, 32, 70, 198, 243, 203, 244, 61, 77, ++ 6, 70, 40, 96, 186, 247, 12, 255, 49, 70, 2, 70, 58, 72, 187, 243, 9, ++ 244, 32, 70, 198, 243, 134, 241, 56, 75, 24, 96, 43, 104, 26, 104, 66, ++ 240, 128, 114, 26, 96, 26, 104, 66, 240, 2, 2, 26, 96, 0, 34, 195, 248, ++ 224, 33, 98, 105, 39, 42, 5, 221, 211, 248, 224, 33, 66, 240, 64, 2, ++ 195, 248, 224, 33, 64, 242, 221, 86, 2, 224, 10, 32, 191, 243, 49, 247, ++ 43, 104, 211, 248, 224, 49, 155, 3, 1, 212, 1, 62, 245, 209, 0, 33, ++ 11, 70, 32, 70, 79, 244, 0, 98, 255, 247, 50, 255, 0, 33, 11, 70, 32, ++ 70, 64, 246, 18, 2, 255, 247, 43, 255, 0, 33, 11, 70, 32, 70, 64, 246, ++ 41, 2, 255, 247, 36, 255, 32, 70, 1, 33, 255, 247, 251, 254, 0, 32, ++ 26, 73, 188, 243, 243, 241, 0, 179, 32, 70, 198, 243, 57, 241, 6, 70, ++ 186, 247, 188, 254, 64, 246, 42, 1, 2, 70, 32, 70, 198, 243, 112, 244, ++ 208, 248, 20, 144, 7, 70, 208, 248, 152, 128, 32, 70, 198, 243, 40, ++ 241, 1, 35, 131, 64, 67, 234, 9, 3, 123, 97, 72, 240, 1, 3, 199, 248, ++ 152, 48, 32, 70, 49, 70, 198, 243, 105, 244, 43, 104, 26, 106, 66, 240, ++ 3, 2, 26, 98, 189, 232, 248, 131, 251, 136, 5, 0, 255, 127, 1, 33, 36, ++ 110, 4, 0, 81, 26, 4, 0, 44, 110, 4, 0, 6, 137, 5, 0, 7, 33, 192, 248, ++ 164, 17, 64, 33, 192, 248, 168, 17, 79, 244, 240, 97, 192, 248, 200, ++ 17, 24, 33, 192, 248, 204, 17, 8, 33, 1, 34, 192, 248, 208, 17, 6, 33, ++ 10, 35, 192, 248, 156, 33, 192, 248, 176, 33, 192, 248, 220, 17, 200, ++ 34, 28, 33, 192, 248, 152, 49, 192, 248, 180, 33, 32, 35, 16, 34, 192, ++ 248, 224, 17, 12, 33, 192, 248, 160, 49, 192, 248, 188, 49, 192, 248, ++ 192, 49, 192, 248, 196, 33, 192, 248, 212, 49, 192, 248, 228, 17, 3, ++ 35, 192, 248, 232, 33, 4, 33, 192, 248, 240, 33, 0, 34, 192, 248, 216, ++ 49, 192, 248, 236, 17, 192, 248, 244, 33, 192, 248, 252, 33, 192, 248, ++ 0, 50, 112, 71, 65, 242, 228, 67, 152, 66, 6, 209, 68, 242, 244, 48, ++ 11, 26, 88, 66, 64, 235, 3, 0, 112, 71, 0, 32, 112, 71, 208, 248, 28, ++ 18, 56, 181, 4, 70, 89, 177, 128, 104, 4, 240, 166, 251, 5, 70, 212, ++ 248, 28, 2, 194, 247, 43, 255, 0, 35, 196, 248, 28, 50, 0, 224, 13, ++ 70, 40, 70, 56, 189, 127, 181, 4, 70, 6, 35, 132, 32, 3, 147, 194, 247, ++ 26, 255, 196, 248, 28, 2, 184, 177, 0, 33, 132, 34, 187, 243, 249, 242, ++ 0, 37, 28, 35, 160, 104, 212, 248, 28, 18, 3, 170, 0, 149, 1, 149, 4, ++ 240, 55, 251, 6, 70, 1, 48, 8, 209, 212, 248, 28, 2, 194, 247, 5, 255, ++ 196, 248, 28, 82, 1, 224, 79, 240, 255, 54, 48, 70, 4, 176, 112, 189, ++ 45, 233, 240, 65, 4, 70, 13, 70, 22, 70, 152, 70, 64, 242, 233, 55, ++ 2, 224, 10, 32, 191, 243, 66, 246, 99, 105, 26, 109, 0, 42, 4, 218, ++ 1, 63, 246, 209, 56, 70, 189, 232, 240, 129, 6, 154, 70, 68, 54, 2, ++ 178, 241, 128, 127, 70, 240, 0, 70, 3, 209, 42, 120, 66, 240, 128, 114, ++ 182, 24, 30, 101, 64, 242, 233, 54, 2, 224, 10, 32, 191, 243, 38, 246, ++ 99, 105, 27, 109, 0, 43, 3, 219, 43, 112, 1, 32, 189, 232, 240, 129, ++ 1, 62, 242, 209, 48, 70, 189, 232, 240, 129, 0, 0, 45, 233, 240, 67, ++ 139, 176, 29, 70, 221, 248, 72, 144, 159, 75, 8, 70, 195, 248, 0, 144, ++ 17, 70, 23, 70, 255, 247, 116, 255, 0, 40, 0, 240, 48, 129, 79, 244, ++ 11, 112, 194, 247, 175, 254, 4, 70, 0, 40, 0, 240, 41, 129, 0, 33, 79, ++ 244, 11, 114, 187, 243, 140, 242, 165, 96, 196, 248, 20, 144, 32, 70, ++ 255, 247, 28, 255, 145, 75, 30, 104, 196, 248, 24, 98, 30, 177, 54, ++ 120, 0, 54, 24, 191, 1, 38, 4, 241, 40, 8, 64, 70, 2, 33, 65, 34, 188, ++ 243, 138, 242, 0, 35, 0, 147, 1, 147, 2, 147, 56, 70, 41, 70, 74, 70, ++ 19, 155, 6, 240, 254, 250, 224, 96, 0, 40, 0, 240, 250, 128, 197, 243, ++ 252, 247, 32, 96, 224, 104, 198, 243, 8, 240, 103, 105, 128, 74, 123, ++ 104, 128, 73, 3, 240, 1, 3, 131, 240, 1, 3, 212, 248, 0, 192, 0, 43, ++ 24, 191, 17, 70, 132, 248, 122, 49, 64, 246, 41, 3, 156, 69, 96, 96, ++ 212, 248, 8, 224, 226, 104, 7, 245, 0, 115, 3, 209, 16, 177, 7, 245, ++ 8, 119, 1, 224, 7, 245, 4, 119, 0, 151, 212, 248, 188, 1, 1, 144, 212, ++ 248, 192, 1, 2, 144, 212, 248, 200, 1, 3, 144, 79, 240, 255, 48, 4, ++ 144, 212, 248, 196, 1, 5, 144, 8, 32, 6, 144, 0, 32, 7, 144, 112, 70, ++ 4, 240, 36, 252, 96, 98, 0, 40, 0, 240, 186, 128, 212, 248, 24, 18, ++ 100, 79, 185, 177, 11, 120, 171, 177, 215, 248, 176, 48, 152, 71, 98, ++ 73, 34, 70, 212, 248, 24, 2, 188, 243, 155, 241, 212, 248, 24, 2, 95, ++ 73, 34, 70, 4, 240, 199, 250, 46, 177, 32, 70, 255, 247, 8, 255, 0, ++ 40, 64, 240, 158, 128, 2, 33, 10, 70, 215, 248, 184, 48, 96, 106, 152, ++ 71, 32, 70, 0, 33, 226, 104, 43, 70, 0, 240, 110, 249, 32, 97, 0, 40, ++ 0, 240, 142, 128, 0, 33, 11, 70, 32, 70, 81, 74, 191, 243, 198, 242, ++ 0, 35, 196, 248, 148, 1, 132, 248, 125, 49, 78, 72, 194, 243, 74, 240, ++ 16, 179, 187, 243, 73, 244, 1, 35, 131, 64, 75, 72, 196, 248, 132, 49, ++ 194, 243, 64, 240, 16, 177, 187, 243, 63, 244, 8, 177, 212, 248, 132, ++ 1, 196, 248, 136, 1, 69, 73, 0, 32, 188, 243, 44, 240, 3, 12, 164, 248, ++ 140, 49, 164, 248, 142, 1, 59, 177, 0, 33, 32, 70, 64, 74, 11, 70, 191, ++ 243, 156, 242, 196, 248, 144, 1, 0, 32, 62, 73, 188, 243, 26, 240, 1, ++ 40, 8, 191, 132, 248, 34, 2, 32, 70, 186, 247, 233, 252, 0, 40, 53, ++ 208, 0, 32, 1, 37, 196, 248, 164, 1, 132, 248, 42, 82, 54, 73, 188, ++ 243, 8, 240, 32, 177, 132, 248, 5, 82, 52, 72, 187, 243, 212, 241, 0, ++ 32, 51, 73, 187, 243, 254, 247, 192, 178, 141, 248, 38, 0, 104, 177, ++ 0, 240, 15, 0, 79, 240, 128, 115, 10, 169, 1, 248, 2, 13, 79, 244, 64, ++ 114, 0, 147, 32, 70, 15, 35, 255, 247, 184, 254, 10, 169, 8, 35, 1, ++ 248, 1, 61, 99, 105, 0, 34, 29, 111, 26, 103, 79, 240, 128, 115, 0, ++ 147, 32, 70, 240, 35, 255, 247, 169, 254, 99, 105, 29, 103, 33, 73, ++ 34, 70, 33, 72, 191, 243, 122, 246, 32, 72, 191, 243, 15, 245, 32, 75, ++ 4, 245, 132, 114, 81, 28, 26, 96, 3, 50, 218, 96, 212, 248, 240, 32, ++ 89, 96, 4, 245, 133, 113, 153, 96, 195, 248, 16, 128, 90, 97, 5, 224, ++ 32, 70, 194, 247, 136, 253, 0, 36, 0, 224, 4, 70, 32, 70, 11, 176, 189, ++ 232, 240, 131, 184, 7, 0, 0, 116, 7, 0, 0, 29, 137, 5, 0, 47, 137, 5, ++ 0, 208, 134, 135, 0, 241, 57, 0, 0, 213, 49, 0, 0, 109, 58, 0, 0, 68, ++ 137, 5, 0, 110, 137, 5, 0, 102, 137, 5, 0, 165, 196, 128, 0, 57, 137, ++ 5, 0, 37, 137, 5, 0, 77, 137, 5, 0, 17, 137, 5, 0, 77, 196, 128, 0, ++ 118, 26, 4, 0, 77, 193, 128, 0, 48, 110, 4, 0, 56, 181, 0, 37, 4, 70, ++ 128, 248, 121, 81, 0, 105, 0, 240, 222, 248, 32, 70, 195, 243, 43, 246, ++ 224, 104, 41, 70, 197, 243, 189, 246, 212, 248, 148, 1, 40, 177, 185, ++ 247, 200, 255, 212, 248, 148, 1, 191, 243, 172, 241, 212, 248, 144, ++ 1, 40, 177, 185, 247, 191, 255, 212, 248, 144, 1, 191, 243, 163, 241, ++ 224, 104, 5, 240, 104, 255, 212, 248, 28, 50, 35, 177, 27, 120, 19, ++ 177, 32, 70, 255, 247, 245, 253, 32, 70, 189, 232, 56, 64, 194, 247, ++ 40, 189, 16, 181, 132, 105, 160, 104, 255, 247, 202, 255, 224, 104, ++ 5, 240, 55, 253, 0, 32, 16, 189, 0, 0, 16, 181, 132, 105, 0, 33, 52, ++ 34, 4, 241, 28, 0, 187, 243, 248, 240, 3, 75, 160, 104, 99, 98, 36, ++ 98, 195, 243, 26, 244, 0, 32, 16, 189, 53, 203, 128, 0, 45, 233, 243, ++ 71, 39, 77, 153, 70, 43, 104, 6, 70, 7, 43, 15, 70, 146, 70, 64, 220, ++ 5, 240, 8, 253, 128, 70, 80, 32, 194, 247, 248, 252, 4, 70, 0, 40, 58, ++ 208, 0, 33, 80, 34, 187, 243, 215, 240, 43, 104, 164, 248, 20, 144, ++ 132, 232, 72, 0, 39, 97, 196, 248, 12, 128, 32, 70, 65, 242, 228, 65, ++ 74, 70, 67, 70, 141, 232, 128, 4, 255, 247, 28, 254, 160, 96, 16, 179, ++ 0, 32, 10, 153, 11, 154, 19, 75, 141, 232, 64, 4, 254, 247, 28, 255, ++ 7, 70, 24, 177, 160, 104, 255, 247, 123, 255, 18, 224, 160, 104, 187, ++ 247, 185, 249, 43, 104, 160, 97, 15, 33, 11, 74, 48, 70, 187, 243, 18, ++ 241, 247, 115, 10, 72, 49, 70, 187, 243, 205, 240, 43, 104, 1, 51, 43, ++ 96, 2, 224, 0, 36, 0, 224, 4, 70, 32, 70, 189, 232, 252, 135, 0, 191, ++ 72, 110, 4, 0, 101, 203, 128, 0, 151, 137, 5, 0, 119, 137, 5, 0, 194, ++ 247, 175, 188, 45, 233, 240, 65, 27, 79, 152, 70, 59, 120, 5, 70, 7, ++ 43, 20, 70, 38, 216, 84, 32, 194, 247, 160, 252, 6, 70, 16, 179, 0, ++ 33, 84, 34, 187, 243, 128, 240, 59, 120, 0, 34, 134, 248, 68, 48, 1, ++ 51, 59, 112, 1, 35, 180, 96, 134, 232, 32, 1, 166, 248, 76, 32, 166, ++ 248, 80, 32, 166, 248, 78, 32, 166, 248, 82, 32, 179, 100, 4, 32, 194, ++ 247, 132, 252, 4, 70, 48, 100, 64, 177, 0, 33, 4, 34, 187, 243, 99, ++ 240, 0, 224, 0, 38, 48, 70, 189, 232, 240, 129, 48, 70, 194, 247, 120, ++ 252, 38, 70, 247, 231, 0, 191, 76, 110, 4, 0, 194, 107, 26, 177, 0, ++ 35, 83, 98, 130, 107, 83, 98, 192, 104, 255, 247, 185, 191, 0, 0, 5, ++ 74, 6, 75, 209, 126, 25, 112, 17, 127, 89, 112, 81, 127, 153, 112, 146, ++ 127, 218, 112, 112, 71, 0, 191, 180, 107, 6, 0, 0, 110, 4, 0, 45, 233, ++ 240, 79, 143, 176, 185, 247, 175, 254, 71, 78, 71, 77, 51, 104, 4, 144, ++ 5, 147, 43, 104, 179, 245, 128, 95, 0, 242, 129, 128, 68, 79, 68, 73, ++ 56, 104, 187, 243, 124, 246, 1, 40, 122, 208, 43, 104, 223, 248, 28, ++ 145, 3, 147, 217, 248, 0, 48, 0, 36, 6, 147, 223, 248, 16, 129, 35, ++ 104, 223, 248, 16, 161, 7, 147, 216, 248, 0, 48, 223, 248, 8, 177, 8, ++ 147, 218, 248, 0, 48, 56, 74, 9, 147, 219, 248, 0, 48, 215, 248, 0, ++ 192, 10, 147, 53, 75, 18, 104, 25, 104, 12, 146, 11, 145, 52, 73, 48, ++ 29, 9, 104, 3, 154, 13, 145, 97, 70, 205, 248, 8, 192, 1, 147, 185, ++ 247, 122, 252, 33, 70, 42, 104, 56, 104, 186, 243, 245, 247, 45, 74, ++ 1, 155, 202, 248, 0, 32, 40, 73, 41, 74, 4, 152, 28, 96, 20, 96, 12, ++ 96, 79, 240, 255, 50, 49, 26, 60, 96, 201, 248, 0, 64, 44, 96, 200, ++ 248, 0, 64, 203, 248, 0, 64, 187, 243, 98, 246, 5, 153, 1, 155, 202, ++ 67, 144, 66, 221, 248, 8, 192, 41, 209, 3, 154, 6, 153, 42, 96, 201, ++ 248, 0, 16, 33, 104, 28, 74, 199, 248, 0, 192, 17, 96, 7, 154, 8, 153, ++ 34, 96, 9, 154, 200, 248, 0, 16, 202, 248, 0, 32, 10, 153, 11, 154, ++ 203, 248, 0, 16, 26, 96, 15, 73, 12, 155, 3, 154, 11, 96, 13, 155, 15, ++ 73, 96, 70, 11, 96, 49, 29, 185, 247, 53, 252, 42, 104, 48, 29, 33, ++ 70, 15, 176, 189, 232, 240, 79, 186, 243, 173, 183, 254, 231, 254, 231, ++ 15, 176, 189, 232, 240, 143, 180, 107, 6, 0, 72, 93, 4, 0, 68, 93, 4, ++ 0, 230, 137, 5, 0, 212, 33, 0, 0, 208, 33, 0, 0, 216, 33, 0, 0, 221, ++ 186, 173, 187, 192, 33, 0, 0, 64, 93, 4, 0, 204, 33, 0, 0, 188, 33, ++ 0, 0, 200, 33, 0, 0, 112, 71, 0, 0, 119, 75, 45, 233, 240, 79, 27, 104, ++ 145, 176, 4, 59, 1, 43, 3, 216, 116, 75, 24, 104, 255, 247, 242, 255, ++ 254, 247, 84, 254, 0, 33, 4, 70, 198, 243, 150, 240, 32, 70, 0, 33, ++ 198, 243, 98, 240, 5, 70, 88, 177, 32, 70, 197, 243, 81, 247, 43, 106, ++ 0, 43, 5, 218, 32, 70, 197, 243, 75, 247, 79, 240, 0, 67, 43, 98, 187, ++ 247, 67, 254, 32, 70, 197, 243, 143, 244, 14, 169, 8, 34, 187, 243, ++ 243, 241, 2, 70, 32, 70, 212, 248, 64, 176, 11, 146, 197, 243, 98, 244, ++ 130, 70, 32, 70, 197, 243, 94, 244, 129, 70, 32, 70, 197, 243, 90, 244, ++ 128, 70, 32, 70, 197, 243, 178, 244, 7, 70, 32, 70, 197, 243, 174, 244, ++ 6, 70, 32, 70, 197, 243, 170, 244, 5, 70, 32, 70, 190, 243, 224, 241, ++ 1, 70, 32, 70, 12, 145, 190, 243, 219, 241, 132, 70, 32, 70, 205, 248, ++ 52, 192, 190, 243, 213, 241, 11, 154, 12, 153, 221, 248, 52, 192, 2, ++ 146, 8, 245, 66, 72, 74, 74, 5, 245, 66, 69, 0, 245, 66, 64, 10, 245, ++ 66, 74, 9, 245, 66, 73, 8, 245, 168, 120, 7, 245, 66, 71, 6, 245, 66, ++ 70, 5, 245, 168, 117, 1, 245, 66, 65, 12, 245, 66, 76, 0, 245, 168, ++ 112, 184, 251, 242, 248, 181, 251, 242, 245, 12, 245, 168, 124, 176, ++ 251, 242, 240, 10, 245, 168, 122, 9, 245, 168, 121, 7, 245, 168, 119, ++ 6, 245, 168, 118, 1, 245, 168, 113, 177, 251, 242, 241, 223, 248, 248, ++ 224, 186, 251, 242, 250, 2, 251, 24, 153, 183, 251, 242, 247, 2, 251, ++ 21, 102, 2, 251, 16, 194, 205, 248, 4, 224, 223, 248, 224, 224, 46, ++ 75, 178, 251, 254, 242, 185, 251, 254, 249, 182, 251, 254, 246, 8, 145, ++ 9, 146, 42, 73, 43, 74, 43, 72, 0, 147, 205, 248, 12, 176, 205, 248, ++ 16, 160, 205, 248, 20, 144, 6, 151, 7, 150, 186, 243, 2, 247, 38, 72, ++ 64, 246, 13, 1, 68, 242, 244, 50, 254, 247, 7, 253, 56, 177, 34, 72, ++ 64, 246, 41, 1, 68, 242, 244, 50, 254, 247, 255, 252, 32, 185, 31, 74, ++ 32, 75, 29, 77, 26, 96, 0, 224, 0, 37, 32, 70, 5, 240, 245, 253, 68, ++ 242, 24, 51, 79, 246, 255, 114, 144, 66, 20, 191, 2, 70, 26, 70, 64, ++ 246, 18, 1, 24, 72, 254, 247, 232, 252, 22, 73, 0, 40, 24, 191, 0, 33, ++ 77, 177, 65, 177, 18, 75, 40, 70, 27, 104, 91, 104, 152, 71, 43, 105, ++ 40, 70, 91, 104, 152, 71, 32, 70, 197, 243, 132, 246, 41, 70, 254, 247, ++ 159, 254, 32, 70, 17, 176, 189, 232, 240, 143, 0, 191, 216, 33, 0, 0, ++ 212, 33, 0, 0, 64, 66, 15, 0, 225, 137, 5, 0, 163, 137, 5, 0, 226, 137, ++ 5, 0, 168, 137, 5, 0, 84, 93, 4, 0, 128, 93, 4, 0, 188, 7, 0, 0, 196, ++ 98, 4, 0, 211, 22, 4, 0, 160, 134, 1, 0, 8, 70, 112, 71, 45, 233, 240, ++ 79, 209, 248, 252, 48, 145, 176, 11, 147, 3, 245, 96, 99, 4, 70, 9, ++ 147, 113, 225, 14, 34, 0, 35, 32, 70, 11, 169, 183, 243, 135, 247, 15, ++ 40, 7, 70, 32, 70, 2, 209, 183, 243, 31, 247, 108, 225, 0, 34, 11, 169, ++ 19, 70, 183, 243, 123, 247, 16, 240, 14, 15, 64, 240, 97, 129, 139, ++ 78, 58, 13, 62, 64, 64, 242, 59, 67, 54, 10, 0, 244, 248, 120, 154, ++ 66, 8, 146, 79, 234, 24, 24, 4, 209, 64, 246, 255, 115, 158, 66, 0, ++ 240, 74, 129, 0, 244, 120, 83, 79, 234, 83, 43, 0, 43, 0, 240, 67, 129, ++ 0, 244, 248, 42, 0, 244, 120, 3, 219, 12, 79, 234, 154, 58, 19, 235, ++ 10, 2, 7, 147, 37, 209, 64, 242, 103, 51, 158, 66, 20, 209, 12, 171, ++ 1, 147, 13, 171, 2, 147, 14, 171, 3, 147, 15, 171, 4, 147, 32, 70, 11, ++ 169, 19, 70, 0, 146, 183, 243, 225, 246, 0, 40, 0, 240, 35, 129, 12, ++ 155, 196, 248, 88, 51, 30, 225, 64, 242, 220, 83, 158, 66, 8, 208, 64, ++ 242, 11, 83, 158, 66, 4, 208, 64, 246, 39, 3, 158, 66, 64, 240, 18, ++ 129, 212, 248, 208, 80, 49, 70, 5, 241, 182, 3, 68, 248, 35, 112, 5, ++ 241, 198, 3, 68, 248, 35, 0, 32, 70, 255, 247, 133, 255, 4, 235, 133, ++ 3, 195, 248, 212, 0, 0, 39, 11, 224, 1, 34, 32, 70, 11, 169, 19, 70, ++ 183, 243, 19, 247, 0, 240, 14, 0, 2, 40, 64, 240, 248, 128, 1, 55, 71, ++ 69, 241, 209, 12, 171, 1, 147, 13, 171, 2, 147, 14, 171, 0, 39, 3, 147, ++ 15, 171, 4, 147, 32, 70, 11, 169, 58, 70, 59, 70, 0, 151, 183, 243, ++ 155, 246, 32, 177, 185, 70, 39, 224, 79, 240, 1, 9, 0, 224, 129, 70, ++ 64, 35, 0, 147, 12, 171, 1, 147, 13, 171, 2, 147, 14, 171, 3, 147, 0, ++ 34, 15, 171, 4, 147, 32, 70, 11, 169, 19, 70, 183, 243, 132, 246, 0, ++ 40, 233, 209, 185, 241, 1, 15, 14, 208, 13, 155, 0, 43, 64, 240, 197, ++ 128, 15, 155, 0, 43, 64, 240, 193, 128, 14, 154, 178, 245, 128, 95, ++ 64, 240, 188, 128, 153, 70, 219, 231, 12, 154, 4, 235, 133, 3, 195, ++ 248, 20, 33, 14, 154, 1, 39, 195, 248, 212, 33, 12, 171, 1, 147, 13, ++ 171, 2, 147, 14, 171, 3, 147, 15, 171, 0, 34, 4, 147, 32, 70, 11, 169, ++ 59, 70, 0, 146, 183, 243, 88, 246, 96, 177, 1, 47, 10, 209, 14, 155, ++ 179, 245, 128, 95, 6, 209, 12, 153, 4, 235, 133, 2, 194, 248, 148, 17, ++ 194, 248, 20, 50, 1, 55, 0, 40, 223, 209, 55, 70, 79, 240, 1, 8, 46, ++ 70, 23, 224, 0, 37, 0, 35, 0, 147, 12, 171, 1, 147, 13, 171, 2, 147, ++ 14, 171, 3, 147, 15, 171, 4, 147, 32, 70, 11, 169, 66, 70, 43, 70, 183, ++ 243, 49, 246, 8, 177, 1, 53, 236, 231, 0, 45, 117, 208, 8, 241, 1, 8, ++ 216, 69, 229, 209, 53, 70, 62, 70, 0, 39, 31, 224, 192, 35, 0, 147, ++ 12, 171, 1, 147, 13, 171, 2, 147, 14, 171, 3, 147, 15, 171, 4, 147, ++ 32, 70, 11, 169, 58, 70, 0, 35, 183, 243, 20, 246, 0, 40, 91, 208, 15, ++ 155, 0, 43, 88, 209, 14, 155, 179, 245, 128, 95, 84, 209, 39, 185, 12, ++ 154, 5, 241, 166, 3, 68, 248, 35, 32, 1, 55, 87, 69, 221, 209, 0, 39, ++ 57, 224, 0, 255, 15, 0, 128, 35, 0, 147, 12, 171, 1, 147, 13, 171, 2, ++ 147, 14, 171, 3, 147, 15, 171, 187, 241, 1, 15, 12, 191, 58, 70, 122, ++ 28, 4, 147, 32, 70, 0, 35, 11, 169, 183, 243, 234, 245, 8, 154, 64, ++ 242, 59, 67, 154, 66, 13, 209, 64, 242, 53, 19, 158, 66, 9, 209, 212, ++ 248, 112, 51, 12, 153, 4, 235, 131, 2, 1, 51, 194, 248, 116, 19, 196, ++ 248, 112, 51, 248, 177, 15, 155, 235, 185, 14, 155, 179, 245, 128, 95, ++ 25, 209, 186, 241, 0, 15, 5, 209, 39, 185, 12, 154, 5, 241, 166, 3, ++ 68, 248, 35, 32, 1, 55, 7, 155, 159, 66, 196, 209, 185, 241, 0, 15, ++ 4, 209, 212, 248, 208, 48, 1, 51, 196, 248, 208, 48, 11, 155, 9, 154, ++ 147, 66, 255, 244, 137, 174, 0, 35, 196, 248, 208, 48, 17, 176, 189, ++ 232, 240, 143, 16, 181, 208, 248, 112, 35, 0, 35, 6, 224, 208, 248, ++ 112, 19, 79, 244, 76, 116, 193, 248, 0, 73, 1, 51, 4, 48, 147, 66, 245, ++ 209, 16, 189, 45, 233, 248, 67, 0, 39, 4, 70, 21, 70, 153, 70, 14, 70, ++ 184, 70, 9, 224, 48, 70, 0, 33, 4, 34, 186, 243, 218, 244, 1, 55, 198, ++ 248, 0, 128, 176, 70, 118, 25, 79, 69, 243, 219, 196, 248, 0, 128, 189, ++ 232, 248, 131, 112, 181, 13, 70, 4, 70, 216, 177, 209, 177, 14, 104, ++ 198, 177, 179, 137, 203, 185, 115, 138, 3, 240, 3, 3, 1, 43, 3, 209, ++ 240, 105, 8, 177, 194, 247, 218, 248, 115, 138, 32, 29, 35, 240, 4, ++ 3, 115, 130, 49, 70, 185, 243, 69, 246, 35, 137, 0, 32, 1, 59, 35, 129, ++ 40, 96, 112, 189, 111, 240, 1, 0, 112, 189, 111, 240, 15, 0, 112, 189, ++ 45, 233, 247, 79, 12, 159, 1, 145, 22, 70, 154, 70, 221, 248, 52, 176, ++ 189, 248, 56, 144, 5, 70, 0, 40, 87, 208, 15, 155, 0, 43, 84, 208, 0, ++ 41, 82, 208, 0, 42, 80, 208, 187, 241, 0, 15, 77, 208, 155, 248, 0, ++ 48, 0, 43, 73, 208, 0, 241, 4, 8, 64, 70, 185, 243, 37, 246, 4, 70, ++ 0, 40, 68, 208, 185, 241, 1, 15, 11, 209, 87, 185, 6, 251, 10, 240, ++ 194, 247, 152, 248, 7, 70, 56, 185, 64, 70, 33, 70, 185, 243, 8, 246, ++ 53, 224, 79, 240, 0, 8, 0, 224, 128, 70, 0, 33, 36, 34, 32, 70, 186, ++ 243, 110, 244, 1, 155, 8, 34, 163, 96, 99, 138, 32, 70, 35, 240, 3, ++ 3, 73, 234, 3, 3, 67, 240, 4, 3, 99, 130, 89, 70, 186, 243, 63, 245, ++ 0, 35, 185, 241, 1, 15, 227, 113, 12, 209, 164, 248, 20, 160, 196, 248, ++ 28, 128, 166, 97, 4, 241, 32, 0, 57, 70, 50, 70, 83, 70, 255, 247, 102, ++ 255, 1, 224, 235, 104, 99, 97, 43, 137, 0, 32, 1, 51, 43, 129, 15, 155, ++ 28, 96, 4, 224, 111, 240, 1, 0, 1, 224, 111, 240, 26, 0, 189, 232, 254, ++ 143, 45, 233, 248, 67, 7, 70, 14, 70, 21, 70, 0, 42, 45, 208, 0, 40, ++ 43, 208, 0, 41, 41, 221, 16, 32, 194, 247, 73, 248, 4, 70, 64, 179, ++ 0, 33, 16, 34, 186, 243, 41, 244, 231, 96, 36, 39, 7, 251, 6, 249, 102, ++ 129, 72, 70, 194, 247, 59, 248, 128, 70, 48, 185, 32, 70, 194, 247, ++ 57, 248, 111, 240, 26, 0, 189, 232, 248, 131, 0, 33, 74, 70, 186, 243, ++ 20, 244, 32, 70, 64, 248, 4, 139, 65, 70, 58, 70, 51, 70, 255, 247, ++ 36, 255, 44, 96, 0, 32, 189, 232, 248, 131, 111, 240, 1, 0, 189, 232, ++ 248, 131, 111, 240, 26, 0, 189, 232, 248, 131, 112, 181, 6, 70, 96, ++ 177, 4, 104, 84, 177, 37, 137, 93, 185, 32, 104, 194, 247, 19, 248, ++ 32, 70, 194, 247, 16, 248, 53, 96, 40, 70, 112, 189, 111, 240, 1, 0, ++ 112, 189, 111, 240, 15, 0, 112, 189, 255, 247, 25, 191, 31, 181, 0, ++ 36, 1, 146, 3, 147, 10, 70, 35, 70, 0, 148, 2, 148, 255, 247, 53, 255, ++ 4, 176, 16, 189, 255, 247, 11, 191, 81, 177, 3, 41, 2, 216, 4, 35, 19, ++ 96, 3, 224, 3, 49, 33, 240, 3, 1, 17, 96, 0, 32, 112, 71, 111, 240, ++ 1, 0, 112, 71, 45, 233, 240, 65, 134, 176, 5, 70, 12, 70, 30, 70, 221, ++ 248, 48, 128, 23, 70, 18, 179, 27, 177, 184, 241, 0, 15, 3, 209, 29, ++ 224, 184, 241, 0, 15, 26, 209, 40, 70, 33, 70, 5, 170, 255, 247, 218, ++ 255, 176, 185, 46, 177, 5, 155, 123, 67, 152, 69, 15, 211, 179, 7, 13, ++ 209, 13, 155, 40, 70, 1, 147, 1, 35, 2, 147, 14, 155, 33, 70, 3, 147, ++ 5, 154, 59, 70, 0, 150, 255, 247, 246, 254, 1, 224, 111, 240, 1, 0, ++ 6, 176, 189, 232, 240, 129, 16, 181, 4, 70, 144, 177, 195, 104, 35, ++ 177, 64, 104, 4, 241, 12, 1, 255, 247, 165, 255, 163, 104, 35, 177, ++ 96, 104, 4, 241, 8, 1, 255, 247, 158, 255, 32, 70, 189, 232, 16, 64, ++ 193, 247, 160, 191, 16, 189, 45, 233, 255, 65, 7, 70, 16, 32, 13, 70, ++ 22, 70, 152, 70, 193, 247, 147, 255, 4, 70, 248, 177, 0, 33, 16, 34, ++ 186, 243, 115, 243, 18, 74, 39, 96, 101, 96, 1, 146, 4, 241, 8, 2, 0, ++ 35, 2, 146, 40, 70, 12, 33, 50, 70, 0, 147, 255, 247, 154, 255, 3, 70, ++ 88, 185, 11, 74, 0, 144, 1, 146, 4, 241, 12, 2, 2, 146, 40, 70, 12, ++ 33, 66, 70, 255, 247, 141, 255, 24, 177, 32, 70, 255, 247, 187, 255, ++ 0, 36, 32, 70, 4, 176, 189, 232, 240, 129, 0, 191, 244, 137, 5, 0, 236, ++ 137, 5, 0, 255, 247, 175, 191, 128, 105, 112, 71, 0, 138, 64, 0, 112, ++ 71, 0, 0, 128, 138, 203, 105, 178, 251, 240, 243, 0, 251, 19, 34, 210, ++ 178, 66, 240, 0, 66, 27, 6, 66, 234, 19, 67, 139, 97, 0, 35, 0, 224, ++ 1, 51, 136, 105, 9, 74, 0, 40, 2, 218, 147, 66, 248, 209, 6, 224, 147, ++ 66, 4, 208, 195, 0, 5, 212, 192, 243, 64, 112, 112, 71, 79, 246, 255, ++ 112, 112, 71, 79, 246, 255, 112, 112, 71, 128, 150, 152, 0, 16, 181, ++ 132, 104, 0, 35, 100, 105, 75, 97, 48, 44, 196, 191, 209, 248, 244, ++ 48, 3, 244, 126, 3, 193, 248, 244, 48, 189, 232, 16, 64, 255, 247, 201, ++ 191, 45, 233, 240, 65, 0, 36, 128, 70, 15, 70, 22, 1, 37, 70, 64, 70, ++ 57, 70, 170, 25, 255, 247, 227, 255, 79, 246, 255, 115, 152, 66, 6, ++ 208, 168, 64, 1, 53, 4, 67, 16, 45, 164, 178, 240, 209, 0, 224, 4, 70, ++ 32, 70, 189, 232, 240, 129, 191, 35, 11, 128, 255, 35, 19, 128, 112, ++ 71, 1, 57, 6, 41, 29, 216, 223, 232, 1, 240, 4, 10, 28, 28, 16, 28, ++ 23, 0, 32, 35, 67, 130, 64, 35, 131, 130, 128, 35, 16, 224, 64, 35, ++ 67, 130, 131, 130, 79, 244, 128, 115, 10, 224, 96, 35, 67, 130, 64, ++ 35, 131, 130, 79, 244, 192, 115, 3, 224, 16, 35, 67, 130, 64, 35, 131, ++ 130, 3, 130, 0, 32, 112, 71, 1, 57, 10, 41, 25, 216, 223, 232, 1, 240, ++ 6, 8, 10, 12, 14, 24, 16, 24, 24, 24, 19, 0, 64, 35, 12, 224, 96, 35, ++ 10, 224, 128, 35, 8, 224, 160, 35, 6, 224, 192, 35, 4, 224, 79, 244, ++ 128, 115, 1, 224, 79, 244, 192, 115, 67, 130, 32, 35, 131, 130, 131, ++ 138, 66, 138, 83, 67, 27, 17, 3, 130, 0, 32, 112, 71, 111, 240, 22, ++ 0, 112, 71, 112, 181, 4, 70, 5, 138, 128, 104, 197, 243, 57, 240, 0, ++ 33, 6, 70, 160, 104, 197, 243, 130, 243, 162, 104, 83, 105, 34, 43, ++ 5, 221, 195, 108, 155, 5, 155, 13, 7, 51, 219, 8, 163, 133, 16, 70, ++ 49, 70, 197, 243, 116, 243, 163, 141, 109, 0, 232, 26, 2, 56, 112, 189, ++ 112, 181, 4, 70, 128, 104, 13, 70, 22, 70, 197, 243, 50, 242, 48, 177, ++ 32, 70, 41, 70, 50, 70, 189, 232, 112, 64, 255, 247, 105, 191, 6, 245, ++ 128, 102, 53, 248, 22, 0, 128, 178, 112, 189, 248, 181, 4, 70, 128, ++ 104, 22, 70, 15, 70, 197, 243, 5, 240, 0, 33, 5, 70, 160, 104, 197, ++ 243, 78, 243, 58, 70, 1, 70, 32, 70, 255, 247, 218, 255, 41, 70, 48, ++ 128, 160, 104, 197, 243, 68, 243, 0, 32, 248, 189, 1, 57, 45, 233, 248, ++ 79, 4, 70, 145, 70, 30, 70, 14, 41, 113, 216, 223, 232, 1, 240, 8, 24, ++ 112, 40, 112, 112, 112, 52, 112, 112, 112, 112, 112, 112, 59, 0, 144, ++ 248, 46, 32, 131, 139, 10, 177, 197, 140, 0, 224, 197, 139, 237, 26, ++ 163, 105, 217, 5, 46, 213, 51, 104, 171, 66, 51, 211, 167, 139, 54, ++ 224, 144, 248, 46, 32, 3, 140, 10, 177, 197, 140, 0, 224, 69, 140, 237, ++ 26, 163, 105, 154, 5, 30, 213, 51, 104, 171, 66, 35, 211, 39, 140, 38, ++ 224, 131, 105, 79, 240, 2, 5, 19, 244, 128, 111, 19, 208, 51, 104, 1, ++ 43, 24, 217, 135, 106, 2, 55, 26, 224, 135, 140, 197, 140, 131, 105, ++ 237, 27, 19, 244, 0, 111, 5, 224, 135, 139, 197, 140, 131, 105, 237, ++ 27, 19, 244, 64, 127, 4, 209, 53, 96, 111, 240, 29, 0, 189, 232, 248, ++ 143, 51, 104, 171, 66, 4, 210, 53, 96, 111, 240, 13, 0, 189, 232, 248, ++ 143, 160, 104, 196, 243, 152, 247, 0, 33, 131, 70, 160, 104, 197, 243, ++ 225, 242, 79, 240, 0, 8, 130, 70, 9, 224, 8, 235, 7, 2, 32, 70, 81, ++ 70, 255, 247, 104, 255, 8, 241, 1, 8, 41, 248, 2, 11, 168, 69, 243, ++ 209, 160, 104, 89, 70, 197, 243, 205, 242, 198, 248, 0, 128, 0, 32, ++ 189, 232, 248, 143, 111, 240, 1, 0, 189, 232, 248, 143, 115, 181, 0, ++ 35, 173, 248, 4, 48, 173, 248, 6, 48, 131, 104, 4, 70, 91, 105, 13, ++ 70, 39, 43, 5, 221, 203, 105, 27, 5, 27, 13, 27, 17, 4, 59, 6, 224, ++ 27, 43, 6, 216, 79, 244, 146, 98, 154, 64, 2, 213, 12, 35, 131, 98, ++ 14, 224, 36, 43, 1, 208, 39, 43, 4, 209, 35, 138, 127, 43, 5, 216, 12, ++ 35, 4, 224, 23, 43, 1, 208, 24, 43, 1, 221, 20, 35, 163, 98, 235, 105, ++ 3, 244, 224, 35, 179, 245, 128, 63, 14, 208, 79, 240, 4, 67, 171, 97, ++ 0, 35, 0, 224, 1, 51, 170, 105, 0, 42, 46, 74, 2, 218, 147, 66, 248, ++ 209, 87, 224, 147, 66, 85, 208, 43, 105, 162, 106, 163, 97, 3, 50, 32, ++ 70, 41, 70, 255, 247, 14, 255, 40, 75, 162, 105, 0, 9, 3, 64, 19, 67, ++ 163, 97, 3, 244, 64, 115, 0, 34, 179, 245, 64, 127, 132, 248, 46, 32, ++ 2, 209, 1, 35, 132, 248, 46, 48, 163, 106, 13, 241, 6, 2, 4, 51, 163, ++ 131, 35, 138, 32, 70, 227, 131, 227, 132, 1, 169, 255, 247, 132, 254, ++ 189, 248, 6, 32, 189, 248, 4, 48, 214, 26, 182, 178, 22, 177, 227, 131, ++ 99, 132, 162, 132, 163, 105, 219, 5, 10, 213, 32, 70, 41, 70, 162, 106, ++ 255, 247, 223, 254, 0, 9, 128, 178, 0, 177, 224, 131, 227, 139, 0, 224, ++ 163, 139, 35, 132, 174, 185, 32, 70, 255, 247, 181, 254, 163, 105, 0, ++ 235, 208, 112, 64, 16, 96, 132, 152, 5, 9, 213, 162, 106, 32, 70, 41, ++ 70, 1, 50, 255, 247, 198, 254, 0, 9, 96, 132, 160, 132, 1, 224, 35, ++ 140, 163, 132, 124, 189, 128, 150, 152, 0, 0, 255, 255, 0, 248, 181, ++ 67, 105, 5, 70, 21, 43, 1, 208, 22, 43, 60, 221, 40, 70, 197, 243, 222, ++ 240, 6, 70, 0, 40, 54, 209, 40, 70, 197, 243, 218, 240, 0, 40, 51, 208, ++ 40, 70, 196, 243, 199, 246, 49, 70, 7, 70, 40, 70, 197, 243, 16, 242, ++ 6, 70, 191, 247, 27, 252, 107, 105, 4, 70, 48, 43, 4, 221, 241, 105, ++ 1, 244, 112, 65, 9, 11, 3, 224, 169, 105, 1, 244, 96, 17, 201, 12, 145, ++ 177, 243, 105, 3, 244, 224, 35, 27, 12, 1, 43, 3, 209, 32, 70, 255, ++ 247, 66, 254, 3, 224, 19, 185, 32, 70, 255, 247, 26, 254, 32, 70, 49, ++ 70, 255, 247, 41, 255, 0, 224, 12, 70, 40, 70, 57, 70, 197, 243, 231, ++ 241, 2, 224, 0, 36, 0, 224, 4, 70, 32, 70, 248, 189, 8, 181, 67, 104, ++ 219, 104, 152, 71, 8, 189, 8, 181, 67, 104, 27, 104, 152, 71, 8, 189, ++ 115, 181, 0, 38, 4, 70, 1, 150, 191, 247, 223, 251, 76, 34, 49, 70, ++ 5, 70, 186, 243, 224, 240, 99, 105, 21, 43, 43, 96, 1, 208, 22, 43, ++ 2, 217, 191, 247, 214, 251, 104, 96, 107, 104, 211, 177, 172, 96, 32, ++ 70, 197, 243, 177, 240, 232, 96, 32, 70, 197, 243, 121, 240, 6, 70, ++ 32, 185, 32, 70, 1, 33, 1, 170, 197, 243, 168, 240, 107, 104, 32, 70, ++ 27, 105, 152, 71, 5, 70, 54, 185, 32, 70, 49, 70, 1, 170, 197, 243, ++ 157, 240, 0, 224, 29, 70, 40, 70, 124, 189, 45, 233, 247, 67, 153, 70, ++ 0, 35, 4, 70, 15, 70, 144, 70, 1, 147, 197, 243, 89, 240, 5, 70, 32, ++ 185, 32, 70, 1, 33, 1, 170, 197, 243, 136, 240, 32, 70, 197, 243, 79, ++ 240, 120, 177, 32, 70, 197, 243, 73, 240, 88, 185, 32, 70, 255, 247, ++ 176, 255, 80, 177, 67, 104, 57, 70, 94, 105, 66, 70, 75, 70, 176, 71, ++ 6, 70, 4, 224, 111, 240, 24, 6, 1, 224, 79, 240, 255, 54, 37, 185, 32, ++ 70, 41, 70, 1, 170, 197, 243, 105, 240, 48, 70, 189, 232, 254, 131, ++ 130, 96, 65, 96, 1, 96, 112, 71, 45, 233, 240, 65, 84, 26, 1, 44, 15, ++ 70, 30, 70, 6, 157, 14, 221, 32, 70, 193, 247, 143, 252, 128, 70, 112, ++ 177, 57, 70, 34, 70, 184, 247, 239, 252, 198, 248, 0, 128, 0, 32, 44, ++ 96, 189, 232, 240, 129, 0, 32, 24, 96, 40, 96, 189, 232, 240, 129, 111, ++ 240, 26, 0, 189, 232, 240, 129, 14, 180, 243, 181, 129, 104, 4, 70, ++ 1, 41, 69, 217, 8, 171, 64, 104, 7, 154, 1, 147, 186, 243, 170, 241, ++ 67, 28, 6, 70, 3, 208, 163, 104, 2, 59, 152, 66, 2, 221, 0, 32, 160, ++ 96, 54, 224, 96, 104, 61, 33, 186, 243, 196, 240, 64, 179, 103, 104, ++ 37, 104, 199, 27, 33, 224, 40, 70, 58, 70, 184, 247, 170, 252, 176, ++ 185, 235, 93, 61, 43, 19, 209, 40, 70, 186, 243, 234, 240, 98, 104, ++ 71, 28, 115, 28, 219, 27, 82, 27, 233, 25, 210, 24, 40, 70, 186, 243, ++ 8, 240, 99, 104, 219, 27, 99, 96, 163, 104, 223, 25, 167, 96, 8, 224, ++ 43, 70, 19, 248, 1, 43, 29, 70, 0, 42, 250, 209, 97, 104, 141, 66, 218, ++ 211, 163, 104, 112, 28, 27, 26, 163, 96, 99, 104, 27, 24, 99, 96, 0, ++ 224, 0, 32, 189, 232, 252, 64, 3, 176, 112, 71, 0, 0, 45, 233, 240, ++ 79, 187, 176, 26, 144, 25, 145, 27, 146, 24, 147, 0, 43, 2, 240, 30, ++ 135, 79, 244, 128, 80, 193, 247, 26, 252, 18, 144, 0, 40, 2, 240, 22, ++ 135, 55, 168, 18, 153, 79, 244, 128, 82, 255, 247, 114, 255, 0, 33, ++ 79, 244, 128, 82, 18, 152, 185, 243, 240, 247, 24, 154, 17, 104, 217, ++ 177, 11, 120, 203, 177, 68, 154, 19, 104, 2, 43, 3, 216, 20, 224, 1, ++ 58, 2, 96, 0, 224, 68, 152, 2, 104, 139, 24, 19, 248, 1, 76, 28, 185, ++ 19, 248, 2, 60, 0, 43, 242, 208, 18, 152, 184, 247, 86, 252, 68, 153, ++ 56, 154, 11, 104, 211, 24, 56, 147, 0, 35, 141, 248, 156, 48, 79, 240, ++ 255, 50, 21, 147, 19, 147, 1, 35, 17, 146, 22, 147, 2, 240, 170, 190, ++ 25, 153, 1, 34, 81, 248, 4, 107, 0, 35, 25, 145, 23, 146, 20, 147, 23, ++ 153, 73, 177, 242, 92, 95, 28, 16, 146, 1, 58, 210, 178, 253, 42, 15, ++ 216, 245, 93, 159, 28, 13, 224, 241, 92, 74, 30, 210, 178, 253, 42, ++ 16, 145, 3, 216, 128, 34, 13, 70, 16, 146, 0, 224, 23, 157, 95, 28, ++ 0, 224, 0, 37, 123, 25, 179, 245, 96, 127, 130, 242, 128, 134, 16, 155, ++ 32, 43, 40, 208, 5, 216, 21, 43, 11, 208, 27, 43, 66, 240, 114, 134, ++ 100, 224, 16, 153, 34, 41, 53, 208, 48, 211, 128, 41, 66, 240, 106, ++ 134, 103, 224, 243, 25, 90, 120, 243, 93, 18, 2, 211, 24, 7, 43, 18, ++ 221, 188, 28, 52, 25, 34, 70, 219, 73, 55, 168, 255, 247, 30, 255, 32, ++ 70, 186, 243, 47, 240, 250, 28, 18, 24, 216, 73, 55, 168, 178, 24, 255, ++ 247, 20, 255, 2, 240, 79, 190, 244, 25, 98, 120, 243, 93, 18, 2, 210, ++ 24, 55, 168, 210, 73, 255, 247, 9, 255, 227, 120, 162, 120, 27, 2, 55, ++ 168, 208, 73, 154, 24, 255, 247, 1, 255, 2, 240, 60, 190, 242, 93, 20, ++ 146, 2, 240, 56, 190, 20, 155, 12, 43, 2, 240, 47, 134, 157, 248, 156, ++ 48, 0, 43, 66, 240, 47, 134, 243, 93, 4, 43, 66, 240, 43, 134, 7, 241, ++ 2, 8, 6, 235, 8, 4, 32, 70, 191, 247, 3, 252, 0, 40, 66, 240, 33, 134, ++ 22, 248, 8, 48, 219, 7, 2, 241, 28, 134, 39, 169, 32, 70, 186, 243, ++ 39, 242, 17, 153, 1, 49, 66, 240, 20, 134, 243, 25, 154, 121, 219, 121, ++ 18, 2, 211, 24, 17, 147, 2, 240, 12, 190, 243, 25, 218, 121, 155, 121, ++ 55, 168, 180, 73, 67, 234, 2, 34, 255, 247, 198, 254, 2, 240, 1, 190, ++ 243, 93, 244, 25, 143, 43, 2, 242, 252, 133, 1, 162, 82, 248, 35, 240, ++ 77, 159, 4, 0, 157, 159, 4, 0, 149, 160, 4, 0, 77, 165, 4, 0, 41, 167, ++ 4, 0, 13, 165, 4, 0, 139, 164, 4, 0, 169, 164, 4, 0, 187, 160, 4, 0, ++ 81, 167, 4, 0, 197, 167, 4, 0, 237, 167, 4, 0, 1, 168, 4, 0, 207, 200, ++ 4, 0, 115, 166, 4, 0, 243, 164, 4, 0, 47, 164, 4, 0, 153, 168, 4, 0, ++ 217, 168, 4, 0, 95, 159, 4, 0, 25, 169, 4, 0, 39, 169, 4, 0, 73, 169, ++ 4, 0, 87, 169, 4, 0, 31, 160, 4, 0, 101, 169, 4, 0, 207, 200, 4, 0, ++ 61, 161, 4, 0, 163, 169, 4, 0, 81, 161, 4, 0, 207, 200, 4, 0, 207, 200, ++ 4, 0, 207, 200, 4, 0, 185, 169, 4, 0, 253, 169, 4, 0, 17, 170, 4, 0, ++ 53, 171, 4, 0, 249, 172, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 157, ++ 174, 4, 0, 61, 159, 4, 0, 45, 159, 4, 0, 29, 159, 4, 0, 23, 176, 4, ++ 0, 43, 176, 4, 0, 63, 176, 4, 0, 83, 176, 4, 0, 207, 200, 4, 0, 33, ++ 168, 4, 0, 47, 161, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 45, 160, 4, ++ 0, 31, 179, 4, 0, 103, 176, 4, 0, 225, 169, 4, 0, 239, 169, 4, 0, 45, ++ 179, 4, 0, 149, 192, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 207, 200, ++ 4, 0, 207, 200, 4, 0, 93, 161, 4, 0, 191, 176, 4, 0, 233, 176, 4, 0, ++ 43, 177, 4, 0, 105, 177, 4, 0, 167, 177, 4, 0, 229, 177, 4, 0, 35, 178, ++ 4, 0, 97, 178, 4, 0, 117, 178, 4, 0, 207, 200, 4, 0, 5, 162, 4, 0, 207, ++ 200, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 15, 164, 4, 0, 113, 161, ++ 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, ++ 233, 192, 4, 0, 207, 200, 4, 0, 67, 164, 4, 0, 163, 179, 4, 0, 115, ++ 180, 4, 0, 201, 181, 4, 0, 179, 182, 4, 0, 157, 183, 4, 0, 215, 183, ++ 4, 0, 95, 184, 4, 0, 173, 184, 4, 0, 187, 185, 4, 0, 69, 187, 4, 0, ++ 241, 187, 4, 0, 157, 188, 4, 0, 7, 193, 4, 0, 179, 162, 4, 0, 115, 163, ++ 4, 0, 233, 188, 4, 0, 37, 190, 4, 0, 49, 191, 4, 0, 61, 192, 4, 0, 77, ++ 193, 4, 0, 39, 195, 4, 0, 95, 193, 4, 0, 125, 193, 4, 0, 155, 193, 4, ++ 0, 185, 193, 4, 0, 203, 193, 4, 0, 221, 193, 4, 0, 239, 193, 4, 0, 1, ++ 194, 4, 0, 107, 194, 4, 0, 119, 194, 4, 0, 131, 194, 4, 0, 167, 200, ++ 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, ++ 207, 200, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 207, ++ 200, 4, 0, 137, 178, 4, 0, 253, 178, 4, 0, 207, 200, 4, 0, 207, 200, ++ 4, 0, 121, 195, 4, 0, 225, 195, 4, 0, 103, 196, 4, 0, 237, 196, 4, 0, ++ 25, 198, 4, 0, 43, 198, 4, 0, 55, 198, 4, 0, 97, 198, 4, 0, 89, 199, ++ 4, 0, 81, 200, 4, 0, 79, 234, 149, 10, 95, 250, 138, 250, 79, 240, 0, ++ 8, 1, 240, 62, 184, 79, 234, 85, 9, 95, 250, 137, 249, 79, 240, 0, 8, ++ 1, 240, 7, 184, 79, 234, 85, 9, 95, 250, 137, 249, 79, 240, 0, 8, 0, ++ 240, 237, 191, 100, 120, 55, 168, 16, 73, 34, 70, 22, 148, 255, 247, ++ 125, 253, 2, 240, 184, 188, 227, 120, 34, 121, 27, 4, 67, 234, 2, 99, ++ 98, 120, 55, 168, 19, 67, 162, 120, 9, 73, 67, 234, 2, 34, 255, 247, ++ 109, 253, 2, 240, 168, 188, 0, 191, 66, 151, 5, 0, 105, 140, 5, 0, 155, ++ 146, 5, 0, 216, 141, 5, 0, 167, 149, 5, 0, 144, 151, 5, 0, 152, 147, ++ 5, 0, 162, 120, 99, 120, 18, 2, 210, 24, 155, 73, 55, 168, 255, 247, ++ 84, 253, 34, 121, 227, 120, 18, 2, 55, 168, 152, 73, 210, 24, 255, 247, ++ 76, 253, 6, 45, 66, 242, 134, 132, 162, 121, 99, 121, 18, 2, 55, 168, ++ 148, 73, 210, 24, 255, 247, 65, 253, 8, 45, 66, 242, 123, 132, 35, 122, ++ 226, 121, 27, 2, 55, 168, 143, 73, 154, 24, 255, 247, 54, 253, 10, 45, ++ 66, 242, 112, 132, 7, 241, 10, 8, 7, 241, 9, 4, 22, 248, 8, 32, 51, ++ 93, 18, 2, 210, 24, 55, 168, 136, 73, 255, 247, 38, 253, 22, 248, 8, ++ 48, 50, 93, 27, 2, 55, 168, 133, 73, 154, 24, 255, 247, 29, 253, 2, ++ 240, 88, 188, 163, 120, 98, 120, 27, 2, 154, 24, 17, 146, 2, 240, 81, ++ 188, 127, 75, 6, 34, 181, 251, 242, 242, 26, 112, 79, 240, 0, 8, 153, ++ 70, 36, 224, 67, 70, 16, 33, 123, 74, 29, 168, 185, 243, 203, 245, 67, ++ 70, 16, 33, 121, 74, 47, 168, 185, 243, 197, 245, 99, 120, 162, 120, ++ 29, 169, 67, 234, 2, 34, 55, 168, 255, 247, 247, 252, 99, 121, 162, ++ 121, 27, 4, 67, 234, 2, 99, 226, 120, 55, 168, 19, 67, 34, 121, 47, ++ 169, 67, 234, 2, 34, 255, 247, 233, 252, 8, 241, 1, 8, 6, 52, 153, 248, ++ 0, 48, 152, 69, 214, 219, 2, 240, 29, 188, 2, 45, 6, 209, 55, 168, 103, ++ 73, 98, 120, 255, 247, 217, 252, 2, 240, 20, 188, 163, 120, 98, 120, ++ 27, 2, 55, 168, 98, 73, 154, 24, 255, 247, 207, 252, 2, 240, 10, 188, ++ 162, 120, 99, 120, 18, 2, 4, 45, 26, 68, 5, 217, 35, 121, 225, 120, ++ 27, 6, 9, 4, 91, 24, 26, 67, 55, 168, 89, 73, 255, 247, 189, 252, 6, ++ 45, 66, 242, 247, 131, 243, 25, 154, 121, 89, 121, 18, 2, 8, 45, 10, ++ 68, 5, 217, 25, 122, 219, 121, 9, 6, 27, 4, 201, 24, 10, 67, 55, 168, ++ 80, 73, 255, 247, 169, 252, 10, 45, 66, 242, 227, 131, 243, 25, 154, ++ 122, 89, 122, 18, 2, 12, 45, 10, 68, 5, 217, 25, 123, 219, 122, 9, 6, ++ 27, 4, 201, 24, 10, 67, 55, 168, 71, 73, 255, 247, 149, 252, 2, 240, ++ 208, 187, 55, 168, 69, 73, 98, 120, 255, 247, 142, 252, 2, 240, 201, ++ 187, 163, 120, 98, 120, 27, 2, 55, 168, 56, 73, 154, 24, 255, 247, 132, ++ 252, 2, 240, 191, 187, 1, 53, 0, 35, 237, 178, 23, 147, 2, 240, 185, ++ 187, 163, 120, 98, 120, 55, 168, 58, 73, 66, 234, 3, 34, 255, 247, 116, ++ 252, 2, 240, 175, 187, 148, 248, 3, 160, 35, 121, 79, 234, 10, 74, 74, ++ 234, 3, 106, 99, 120, 181, 241, 5, 11, 74, 234, 3, 10, 72, 191, 165, ++ 241, 2, 11, 163, 120, 79, 234, 171, 11, 74, 234, 3, 42, 95, 250, 139, ++ 251, 79, 240, 0, 8, 36, 224, 67, 68, 16, 33, 34, 74, 47, 168, 185, 243, ++ 25, 245, 153, 248, 0, 48, 16, 33, 67, 68, 31, 74, 29, 168, 185, 243, ++ 17, 245, 82, 70, 47, 169, 55, 168, 255, 247, 70, 252, 227, 120, 34, ++ 121, 27, 4, 67, 234, 2, 99, 98, 120, 55, 168, 19, 67, 162, 120, 29, ++ 169, 67, 234, 2, 34, 255, 247, 56, 252, 10, 241, 4, 10, 8, 241, 1, 8, ++ 223, 248, 60, 144, 4, 52, 216, 69, 153, 248, 0, 48, 211, 219, 155, 68, ++ 137, 248, 0, 176, 2, 240, 101, 187, 9, 75, 234, 8, 26, 112, 79, 240, ++ 0, 8, 153, 70, 73, 224, 0, 191, 198, 144, 5, 0, 190, 151, 5, 0, 242, ++ 141, 5, 0, 241, 138, 5, 0, 236, 147, 5, 0, 99, 147, 5, 0, 156, 110, ++ 4, 0, 120, 27, 4, 0, 131, 27, 4, 0, 131, 150, 5, 0, 61, 145, 5, 0, 135, ++ 141, 5, 0, 152, 141, 5, 0, 141, 142, 5, 0, 19, 145, 5, 0, 67, 70, 16, ++ 33, 177, 74, 29, 168, 185, 243, 194, 244, 67, 70, 16, 33, 175, 74, 47, ++ 168, 185, 243, 188, 244, 227, 120, 34, 121, 27, 4, 67, 234, 2, 99, 98, ++ 120, 29, 169, 19, 67, 162, 120, 55, 168, 67, 234, 2, 34, 255, 247, 232, ++ 251, 227, 121, 34, 122, 27, 4, 67, 234, 2, 99, 98, 121, 55, 168, 19, ++ 67, 162, 121, 47, 169, 67, 234, 2, 34, 255, 247, 218, 251, 8, 241, 1, ++ 8, 8, 52, 153, 248, 0, 48, 152, 69, 208, 219, 2, 240, 14, 187, 148, ++ 248, 3, 160, 35, 121, 79, 234, 10, 74, 74, 234, 3, 106, 99, 120, 181, ++ 241, 5, 11, 74, 234, 3, 10, 72, 191, 5, 241, 2, 11, 163, 120, 79, 234, ++ 235, 11, 74, 234, 3, 42, 95, 250, 139, 251, 79, 240, 0, 8, 59, 224, ++ 67, 68, 16, 33, 140, 74, 47, 168, 185, 243, 120, 244, 153, 248, 0, 48, ++ 16, 33, 67, 68, 138, 74, 29, 168, 185, 243, 112, 244, 153, 248, 0, 48, ++ 16, 33, 67, 68, 135, 74, 51, 168, 185, 243, 104, 244, 82, 70, 47, 169, ++ 55, 168, 255, 247, 157, 251, 227, 121, 34, 122, 27, 4, 67, 234, 2, 99, ++ 98, 121, 51, 169, 19, 67, 162, 121, 55, 168, 67, 234, 2, 34, 255, 247, ++ 143, 251, 227, 122, 34, 123, 27, 4, 67, 234, 2, 99, 98, 122, 55, 168, ++ 19, 67, 162, 122, 29, 169, 67, 234, 2, 34, 255, 247, 129, 251, 10, 241, ++ 8, 10, 8, 241, 1, 8, 8, 52, 223, 248, 204, 145, 216, 69, 153, 248, 0, ++ 48, 189, 219, 155, 68, 137, 248, 0, 176, 2, 240, 174, 186, 110, 75, ++ 12, 34, 181, 251, 242, 242, 26, 112, 79, 240, 0, 8, 153, 70, 62, 224, ++ 67, 70, 16, 33, 100, 74, 51, 168, 185, 243, 40, 244, 67, 70, 16, 33, ++ 99, 74, 29, 168, 185, 243, 34, 244, 67, 70, 16, 33, 97, 74, 47, 168, ++ 185, 243, 28, 244, 227, 120, 34, 121, 27, 4, 67, 234, 2, 99, 98, 120, ++ 51, 169, 19, 67, 162, 120, 55, 168, 67, 234, 2, 34, 255, 247, 72, 251, ++ 227, 121, 34, 122, 27, 4, 67, 234, 2, 99, 98, 121, 47, 169, 19, 67, ++ 162, 121, 55, 168, 67, 234, 2, 34, 255, 247, 58, 251, 227, 122, 34, ++ 123, 27, 4, 67, 234, 2, 99, 98, 122, 55, 168, 19, 67, 162, 122, 29, ++ 169, 67, 234, 2, 34, 255, 247, 44, 251, 8, 241, 1, 8, 12, 52, 153, 248, ++ 0, 48, 152, 69, 188, 219, 2, 240, 96, 186, 227, 120, 34, 121, 27, 4, ++ 67, 234, 2, 99, 98, 120, 55, 168, 19, 67, 162, 120, 67, 73, 67, 234, ++ 2, 34, 255, 247, 21, 251, 2, 240, 80, 186, 163, 120, 98, 120, 55, 168, ++ 63, 73, 66, 234, 3, 34, 255, 247, 11, 251, 2, 240, 70, 186, 79, 240, ++ 5, 9, 181, 251, 249, 249, 95, 250, 137, 249, 79, 240, 0, 8, 22, 224, ++ 99, 120, 16, 33, 55, 74, 47, 168, 185, 243, 192, 243, 35, 121, 98, 121, ++ 27, 4, 67, 234, 2, 99, 162, 120, 55, 168, 19, 67, 226, 120, 47, 169, ++ 67, 234, 2, 34, 255, 247, 236, 250, 8, 241, 1, 8, 5, 52, 200, 69, 230, ++ 219, 2, 240, 34, 186, 55, 168, 43, 73, 98, 120, 255, 247, 224, 250, ++ 2, 45, 66, 242, 26, 130, 55, 168, 40, 73, 162, 120, 255, 247, 216, 250, ++ 2, 240, 19, 186, 0, 34, 55, 168, 37, 73, 99, 120, 255, 247, 208, 250, ++ 2, 45, 66, 242, 77, 130, 1, 34, 55, 168, 33, 73, 163, 120, 255, 247, ++ 199, 250, 3, 45, 2, 240, 68, 130, 2, 34, 55, 168, 28, 73, 227, 120, ++ 255, 247, 190, 250, 4, 45, 2, 240, 246, 129, 25, 73, 55, 168, 3, 34, ++ 35, 121, 255, 247, 181, 250, 1, 33, 19, 145, 2, 240, 238, 185, 98, 120, ++ 55, 168, 18, 73, 255, 247, 172, 250, 55, 168, 17, 73, 1, 34, 163, 120, ++ 255, 247, 166, 250, 2, 240, 225, 185, 55, 168, 14, 73, 98, 120, 255, ++ 247, 159, 250, 2, 240, 218, 185, 0, 191, 120, 27, 4, 0, 131, 27, 4, ++ 0, 142, 27, 4, 0, 154, 27, 4, 0, 156, 110, 4, 0, 169, 138, 5, 0, 141, ++ 147, 5, 0, 166, 27, 4, 0, 206, 141, 5, 0, 149, 148, 5, 0, 0, 139, 5, ++ 0, 190, 142, 5, 0, 171, 30, 14, 43, 2, 242, 189, 129, 1, 162, 82, 248, ++ 35, 240, 0, 191, 153, 165, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 207, ++ 200, 4, 0, 207, 200, 4, 0, 17, 166, 4, 0, 223, 165, 4, 0, 191, 165, ++ 4, 0, 167, 165, 4, 0, 207, 200, 4, 0, 207, 200, 4, 0, 17, 166, 4, 0, ++ 223, 165, 4, 0, 191, 165, 4, 0, 167, 165, 4, 0, 55, 168, 169, 73, 98, ++ 120, 255, 247, 89, 250, 2, 240, 148, 185, 55, 168, 166, 73, 98, 122, ++ 255, 247, 82, 250, 12, 45, 140, 191, 79, 240, 9, 8, 79, 240, 0, 8, 1, ++ 224, 79, 240, 0, 8, 243, 25, 55, 168, 158, 73, 26, 122, 255, 247, 67, ++ 250, 12, 45, 7, 217, 184, 241, 0, 15, 8, 191, 79, 240, 8, 8, 1, 224, ++ 79, 240, 0, 8, 7, 241, 7, 9, 152, 73, 22, 248, 9, 32, 55, 168, 255, ++ 247, 49, 250, 0, 34, 55, 168, 149, 73, 22, 248, 9, 48, 255, 247, 42, ++ 250, 12, 45, 7, 217, 184, 241, 0, 15, 8, 191, 79, 240, 7, 8, 1, 224, ++ 79, 240, 0, 8, 79, 240, 0, 9, 162, 120, 99, 120, 140, 73, 18, 2, 73, ++ 68, 55, 168, 210, 24, 9, 241, 9, 9, 255, 247, 19, 250, 2, 52, 185, 241, ++ 27, 15, 240, 209, 12, 45, 66, 242, 73, 129, 184, 241, 0, 15, 8, 191, ++ 79, 240, 6, 8, 131, 76, 184, 68, 176, 68, 4, 241, 36, 9, 152, 248, 2, ++ 32, 152, 248, 1, 48, 18, 2, 33, 70, 55, 168, 210, 24, 12, 52, 255, 247, ++ 247, 249, 76, 69, 8, 241, 2, 8, 240, 209, 2, 240, 46, 185, 20, 45, 25, ++ 208, 23, 45, 3, 208, 19, 45, 66, 240, 39, 129, 25, 224, 6, 235, 7, 8, ++ 116, 73, 152, 248, 22, 32, 55, 168, 255, 247, 225, 249, 114, 73, 152, ++ 248, 21, 32, 55, 168, 255, 247, 219, 249, 55, 168, 111, 73, 152, 248, ++ 20, 32, 255, 247, 213, 249, 243, 25, 55, 168, 109, 73, 218, 124, 255, ++ 247, 207, 249, 169, 70, 162, 70, 79, 240, 0, 8, 37, 70, 170, 120, 107, ++ 120, 104, 73, 18, 2, 65, 68, 55, 168, 210, 24, 8, 241, 9, 8, 255, 247, ++ 191, 249, 2, 53, 184, 241, 27, 15, 240, 209, 77, 70, 79, 240, 0, 8, ++ 34, 122, 227, 121, 96, 73, 18, 2, 65, 68, 55, 168, 210, 24, 8, 241, ++ 11, 8, 255, 247, 173, 249, 2, 52, 184, 241, 33, 15, 240, 209, 0, 36, ++ 154, 248, 14, 32, 154, 248, 13, 48, 88, 73, 18, 2, 9, 25, 55, 168, 210, ++ 24, 11, 52, 255, 247, 156, 249, 33, 44, 10, 241, 2, 10, 239, 209, 2, ++ 240, 211, 184, 225, 120, 98, 120, 163, 120, 0, 145, 33, 121, 55, 168, ++ 1, 145, 97, 121, 2, 145, 161, 121, 3, 145, 225, 121, 4, 145, 33, 122, ++ 5, 145, 75, 73, 255, 247, 132, 249, 2, 240, 191, 184, 169, 70, 79, 240, ++ 0, 8, 37, 70, 21, 248, 1, 63, 255, 43, 4, 208, 55, 168, 69, 73, 66, ++ 70, 255, 247, 117, 249, 8, 241, 1, 8, 184, 241, 4, 15, 241, 209, 185, ++ 241, 12, 15, 77, 70, 66, 242, 168, 128, 4, 235, 8, 3, 91, 120, 255, ++ 43, 4, 208, 55, 168, 59, 73, 66, 70, 255, 247, 97, 249, 8, 241, 1, 8, ++ 184, 241, 12, 15, 240, 209, 16, 45, 66, 242, 150, 128, 4, 235, 8, 3, ++ 91, 120, 255, 43, 4, 208, 55, 168, 50, 73, 66, 70, 255, 247, 79, 249, ++ 8, 241, 1, 8, 184, 241, 16, 15, 240, 209, 2, 240, 133, 184, 98, 120, ++ 55, 168, 10, 177, 163, 120, 27, 185, 43, 73, 255, 247, 64, 249, 2, 224, ++ 42, 73, 255, 247, 60, 249, 243, 25, 55, 168, 40, 73, 218, 120, 255, ++ 247, 54, 249, 2, 240, 113, 184, 163, 120, 98, 120, 55, 168, 37, 73, ++ 66, 234, 3, 34, 255, 247, 44, 249, 2, 240, 103, 184, 227, 120, 34, 121, ++ 27, 4, 67, 234, 2, 99, 98, 120, 55, 168, 19, 67, 162, 120, 30, 73, 67, ++ 234, 2, 34, 255, 247, 28, 249, 2, 240, 87, 184, 55, 168, 27, 73, 98, ++ 120, 255, 247, 21, 249, 2, 45, 66, 242, 79, 128, 55, 168, 24, 73, 162, ++ 120, 255, 247, 13, 249, 2, 240, 72, 184, 0, 191, 154, 145, 5, 0, 55, ++ 146, 5, 0, 255, 150, 5, 0, 174, 140, 5, 0, 55, 143, 5, 0, 23, 147, 5, ++ 0, 33, 145, 5, 0, 74, 148, 5, 0, 75, 138, 5, 0, 42, 143, 5, 0, 77, 145, ++ 5, 0, 250, 147, 5, 0, 27, 138, 5, 0, 10, 139, 5, 0, 169, 141, 5, 0, ++ 157, 149, 5, 0, 232, 152, 5, 0, 11, 144, 5, 0, 160, 144, 5, 0, 47, 139, ++ 5, 0, 11, 152, 5, 0, 76, 152, 5, 0, 124, 28, 50, 93, 55, 168, 134, 73, ++ 2, 240, 15, 2, 255, 247, 214, 248, 50, 93, 55, 168, 18, 9, 188, 28, ++ 130, 73, 255, 247, 207, 248, 50, 93, 55, 168, 129, 73, 2, 240, 7, 2, ++ 255, 247, 200, 248, 50, 93, 55, 168, 210, 8, 126, 73, 2, 240, 3, 2, ++ 255, 247, 192, 248, 1, 240, 251, 191, 124, 28, 50, 93, 55, 168, 122, ++ 73, 2, 240, 15, 2, 255, 247, 182, 248, 50, 93, 55, 168, 18, 9, 188, ++ 28, 118, 73, 255, 247, 175, 248, 50, 93, 55, 168, 117, 73, 2, 240, 7, ++ 2, 255, 247, 168, 248, 50, 93, 55, 168, 210, 8, 114, 73, 2, 240, 3, ++ 2, 255, 247, 160, 248, 1, 240, 219, 191, 55, 168, 111, 73, 98, 120, ++ 255, 247, 153, 248, 1, 240, 212, 191, 98, 120, 55, 168, 108, 73, 255, ++ 247, 146, 248, 162, 120, 55, 168, 106, 73, 255, 247, 141, 248, 55, 168, ++ 105, 73, 226, 120, 255, 247, 136, 248, 1, 240, 195, 191, 55, 168, 103, ++ 73, 98, 120, 255, 247, 129, 248, 1, 240, 188, 191, 55, 168, 100, 73, ++ 98, 120, 255, 247, 122, 248, 1, 240, 181, 191, 7, 241, 1, 8, 6, 235, ++ 8, 4, 32, 70, 190, 247, 141, 253, 0, 40, 65, 240, 171, 135, 22, 248, ++ 8, 48, 216, 7, 1, 241, 166, 135, 32, 70, 39, 169, 185, 243, 177, 243, ++ 17, 155, 1, 51, 65, 240, 158, 135, 243, 25, 90, 121, 155, 121, 18, 2, ++ 211, 24, 17, 147, 1, 240, 150, 191, 162, 120, 99, 120, 18, 6, 55, 168, ++ 81, 73, 66, 234, 3, 34, 255, 247, 80, 248, 1, 240, 139, 191, 98, 120, ++ 55, 168, 77, 73, 255, 247, 73, 248, 162, 120, 55, 168, 76, 73, 255, ++ 247, 68, 248, 35, 121, 226, 120, 27, 2, 55, 168, 73, 73, 154, 24, 255, ++ 247, 60, 248, 1, 240, 119, 191, 55, 168, 71, 73, 98, 120, 255, 247, ++ 53, 248, 1, 240, 112, 191, 55, 168, 68, 73, 98, 120, 255, 247, 46, 248, ++ 1, 240, 105, 191, 163, 120, 98, 120, 27, 2, 55, 168, 64, 73, 154, 24, ++ 255, 247, 36, 248, 1, 240, 95, 191, 148, 248, 2, 128, 99, 120, 79, 234, ++ 8, 40, 152, 68, 31, 250, 136, 248, 58, 73, 79, 234, 216, 34, 55, 168, ++ 255, 247, 20, 248, 8, 244, 224, 98, 18, 10, 55, 73, 55, 168, 255, 247, ++ 13, 248, 8, 240, 248, 2, 210, 8, 52, 73, 55, 168, 255, 247, 6, 248, ++ 8, 240, 6, 2, 82, 8, 50, 73, 55, 168, 254, 247, 255, 255, 55, 168, 48, ++ 73, 8, 240, 1, 2, 254, 247, 249, 255, 4, 45, 65, 242, 51, 135, 35, 121, ++ 228, 120, 27, 2, 28, 25, 164, 178, 226, 10, 55, 168, 42, 73, 254, 247, ++ 236, 255, 4, 244, 224, 98, 18, 10, 55, 168, 39, 73, 254, 247, 229, 255, ++ 4, 240, 248, 2, 210, 8, 55, 168, 37, 73, 254, 247, 222, 255, 4, 240, ++ 6, 2, 82, 8, 55, 168, 34, 73, 254, 247, 215, 255, 55, 168, 33, 73, 4, ++ 240, 1, 2, 254, 247, 209, 255, 1, 240, 12, 191, 0, 191, 88, 139, 5, ++ 0, 166, 139, 5, 0, 42, 146, 5, 0, 157, 139, 5, 0, 35, 152, 5, 0, 156, ++ 138, 5, 0, 185, 143, 5, 0, 167, 145, 5, 0, 247, 149, 5, 0, 74, 151, ++ 5, 0, 171, 144, 5, 0, 56, 151, 5, 0, 27, 151, 5, 0, 75, 146, 5, 0, 16, ++ 146, 5, 0, 104, 145, 5, 0, 48, 145, 5, 0, 114, 147, 5, 0, 167, 146, ++ 5, 0, 86, 152, 5, 0, 255, 143, 5, 0, 89, 140, 5, 0, 48, 152, 5, 0, 209, ++ 138, 5, 0, 72, 140, 5, 0, 61, 152, 5, 0, 218, 149, 5, 0, 236, 142, 5, ++ 0, 71, 141, 5, 0, 85, 146, 5, 0, 12, 151, 5, 0, 0, 34, 99, 120, 103, ++ 73, 55, 168, 254, 247, 138, 255, 79, 240, 0, 8, 101, 73, 162, 120, 55, ++ 168, 254, 247, 131, 255, 205, 248, 0, 128, 34, 121, 227, 120, 18, 2, ++ 211, 24, 1, 147, 2, 34, 96, 73, 67, 70, 55, 168, 254, 247, 118, 255, ++ 205, 248, 0, 128, 162, 121, 99, 121, 18, 2, 211, 24, 1, 147, 2, 34, ++ 1, 35, 89, 73, 55, 168, 254, 247, 105, 255, 205, 248, 0, 128, 34, 122, ++ 227, 121, 18, 2, 211, 24, 2, 34, 1, 147, 55, 168, 82, 73, 19, 70, 254, ++ 247, 92, 255, 30, 45, 65, 242, 150, 134, 98, 122, 55, 168, 79, 73, 254, ++ 247, 84, 255, 162, 122, 55, 168, 77, 73, 254, 247, 79, 255, 226, 122, ++ 55, 168, 76, 73, 254, 247, 74, 255, 34, 123, 55, 168, 74, 73, 254, 247, ++ 69, 255, 205, 248, 0, 128, 162, 123, 99, 123, 18, 2, 211, 24, 1, 147, ++ 5, 34, 67, 70, 55, 168, 64, 73, 254, 247, 56, 255, 205, 248, 0, 128, ++ 34, 124, 227, 123, 18, 2, 211, 24, 1, 147, 5, 34, 1, 35, 55, 168, 57, ++ 73, 254, 247, 43, 255, 205, 248, 0, 128, 162, 124, 99, 124, 18, 2, 211, ++ 24, 1, 147, 5, 34, 2, 35, 55, 168, 51, 73, 254, 247, 30, 255, 205, 248, ++ 0, 128, 205, 248, 4, 128, 34, 125, 227, 124, 18, 2, 211, 24, 2, 147, ++ 5, 34, 108, 35, 79, 240, 1, 9, 55, 168, 47, 73, 254, 247, 13, 255, 205, ++ 248, 0, 144, 205, 248, 4, 128, 162, 125, 99, 125, 18, 2, 211, 24, 2, ++ 147, 5, 34, 108, 35, 79, 240, 2, 10, 55, 168, 39, 73, 254, 247, 252, ++ 254, 205, 248, 0, 160, 205, 248, 4, 128, 34, 126, 227, 125, 18, 2, 211, ++ 24, 2, 147, 5, 34, 108, 35, 55, 168, 31, 73, 254, 247, 237, 254, 205, ++ 248, 0, 128, 205, 248, 4, 128, 162, 126, 99, 126, 18, 2, 211, 24, 2, ++ 147, 5, 34, 104, 35, 55, 168, 24, 73, 254, 247, 222, 254, 205, 248, ++ 0, 144, 205, 248, 4, 128, 34, 127, 227, 126, 18, 2, 211, 24, 2, 147, ++ 5, 34, 55, 168, 104, 35, 16, 73, 254, 247, 207, 254, 205, 248, 0, 160, ++ 205, 248, 4, 128, 163, 127, 98, 127, 27, 2, 155, 24, 2, 147, 55, 168, ++ 10, 73, 5, 34, 104, 35, 254, 247, 192, 254, 1, 240, 251, 189, 174, 140, ++ 5, 0, 144, 139, 5, 0, 10, 138, 5, 0, 72, 149, 5, 0, 38, 150, 5, 0, 164, ++ 147, 5, 0, 223, 151, 5, 0, 138, 149, 5, 0, 1, 34, 99, 120, 156, 73, ++ 55, 168, 254, 247, 168, 254, 79, 240, 1, 8, 154, 73, 162, 120, 55, 168, ++ 254, 247, 161, 254, 205, 248, 0, 128, 34, 121, 227, 120, 18, 2, 211, ++ 24, 1, 147, 2, 34, 0, 35, 148, 73, 55, 168, 254, 247, 148, 254, 205, ++ 248, 0, 128, 162, 121, 99, 121, 18, 2, 211, 24, 1, 147, 2, 34, 142, ++ 73, 67, 70, 55, 168, 254, 247, 135, 254, 205, 248, 0, 128, 34, 122, ++ 227, 121, 18, 2, 211, 24, 2, 34, 1, 147, 55, 168, 135, 73, 19, 70, 254, ++ 247, 122, 254, 30, 45, 65, 242, 180, 133, 98, 122, 55, 168, 132, 73, ++ 254, 247, 114, 254, 162, 122, 55, 168, 130, 73, 254, 247, 109, 254, ++ 226, 122, 55, 168, 129, 73, 254, 247, 104, 254, 34, 123, 55, 168, 127, ++ 73, 254, 247, 99, 254, 205, 248, 0, 128, 162, 123, 99, 123, 18, 2, 211, ++ 24, 1, 147, 5, 34, 0, 35, 55, 168, 117, 73, 254, 247, 86, 254, 205, ++ 248, 0, 128, 34, 124, 227, 123, 18, 2, 211, 24, 1, 147, 5, 34, 67, 70, ++ 55, 168, 110, 73, 254, 247, 73, 254, 205, 248, 0, 128, 162, 124, 99, ++ 124, 18, 2, 211, 24, 1, 147, 5, 34, 2, 35, 79, 240, 0, 9, 55, 168, 103, ++ 73, 254, 247, 58, 254, 205, 248, 0, 144, 205, 248, 4, 128, 34, 125, ++ 227, 124, 18, 2, 211, 24, 2, 147, 5, 34, 108, 35, 55, 168, 100, 73, ++ 254, 247, 43, 254, 205, 248, 0, 128, 205, 248, 4, 128, 162, 125, 99, ++ 125, 18, 2, 211, 24, 2, 147, 5, 34, 108, 35, 79, 240, 2, 10, 55, 168, ++ 92, 73, 254, 247, 26, 254, 205, 248, 0, 160, 205, 248, 4, 128, 34, 126, ++ 227, 125, 18, 2, 211, 24, 2, 147, 5, 34, 108, 35, 55, 168, 84, 73, 254, ++ 247, 11, 254, 205, 248, 0, 144, 205, 248, 4, 128, 162, 126, 99, 126, ++ 18, 2, 211, 24, 2, 147, 5, 34, 104, 35, 55, 168, 77, 73, 254, 247, 252, ++ 253, 205, 248, 0, 128, 205, 248, 4, 128, 34, 127, 227, 126, 18, 2, 211, ++ 24, 2, 147, 5, 34, 55, 168, 104, 35, 69, 73, 254, 247, 237, 253, 205, ++ 248, 0, 160, 205, 248, 4, 128, 163, 127, 98, 127, 27, 2, 155, 24, 2, ++ 147, 55, 168, 63, 73, 5, 34, 104, 35, 254, 247, 222, 253, 1, 240, 25, ++ 189, 162, 120, 99, 120, 18, 2, 210, 24, 58, 73, 55, 168, 254, 247, 212, ++ 253, 162, 121, 99, 121, 18, 6, 27, 4, 210, 24, 35, 121, 55, 168, 27, ++ 2, 210, 24, 227, 120, 52, 73, 210, 24, 254, 247, 198, 253, 18, 45, 65, ++ 242, 0, 133, 162, 122, 99, 122, 18, 6, 27, 4, 210, 24, 35, 122, 55, ++ 168, 27, 2, 210, 24, 227, 121, 45, 73, 210, 24, 254, 247, 181, 253, ++ 162, 123, 99, 123, 18, 6, 27, 4, 210, 24, 35, 123, 55, 168, 27, 2, 210, ++ 24, 227, 122, 39, 73, 210, 24, 254, 247, 167, 253, 162, 124, 99, 124, ++ 18, 6, 27, 4, 211, 24, 34, 124, 55, 168, 18, 2, 155, 24, 226, 123, 33, ++ 73, 154, 24, 254, 247, 153, 253, 1, 240, 212, 188, 162, 120, 99, 120, ++ 18, 2, 211, 24, 0, 147, 2, 34, 67, 70, 55, 168, 27, 73, 8, 241, 1, 8, ++ 254, 247, 138, 253, 2, 52, 200, 69, 239, 221, 1, 240, 194, 188, 162, ++ 120, 99, 120, 18, 2, 211, 24, 0, 147, 5, 34, 67, 70, 55, 168, 18, 73, ++ 8, 241, 1, 8, 254, 247, 120, 253, 2, 52, 200, 69, 239, 221, 1, 240, ++ 176, 188, 0, 191, 174, 140, 5, 0, 62, 146, 5, 0, 10, 138, 5, 0, 86, ++ 149, 5, 0, 51, 150, 5, 0, 175, 151, 5, 0, 238, 151, 5, 0, 138, 149, ++ 5, 0, 234, 149, 5, 0, 252, 137, 5, 0, 122, 148, 5, 0, 240, 150, 5, 0, ++ 102, 146, 5, 0, 119, 141, 5, 0, 205, 248, 0, 128, 162, 120, 99, 120, ++ 18, 2, 211, 24, 1, 147, 5, 34, 108, 35, 55, 168, 187, 73, 8, 241, 1, ++ 8, 254, 247, 71, 253, 2, 52, 208, 69, 237, 221, 79, 234, 85, 9, 95, ++ 250, 137, 249, 9, 241, 1, 11, 9, 241, 2, 9, 185, 68, 187, 68, 6, 235, ++ 9, 4, 79, 240, 0, 8, 205, 248, 0, 128, 34, 120, 201, 235, 4, 3, 19, ++ 248, 11, 48, 18, 2, 211, 24, 1, 147, 5, 34, 104, 35, 55, 168, 170, 73, ++ 8, 241, 1, 8, 254, 247, 36, 253, 2, 52, 208, 69, 234, 221, 1, 240, 92, ++ 188, 163, 120, 98, 120, 27, 2, 55, 168, 164, 73, 154, 24, 254, 247, ++ 23, 253, 1, 240, 82, 188, 163, 120, 98, 120, 27, 2, 55, 168, 160, 73, ++ 154, 24, 254, 247, 13, 253, 1, 240, 72, 188, 163, 120, 98, 120, 27, ++ 2, 55, 168, 156, 73, 154, 24, 254, 247, 3, 253, 1, 240, 62, 188, 163, ++ 120, 98, 120, 27, 2, 55, 168, 152, 73, 154, 24, 254, 247, 249, 252, ++ 1, 240, 52, 188, 34, 121, 227, 120, 18, 6, 27, 4, 210, 24, 163, 120, ++ 55, 168, 27, 2, 210, 24, 99, 120, 145, 73, 210, 24, 254, 247, 233, 252, ++ 34, 122, 227, 121, 18, 6, 27, 4, 210, 24, 163, 121, 55, 168, 27, 2, ++ 210, 24, 99, 121, 139, 73, 210, 24, 254, 247, 219, 252, 34, 123, 227, ++ 122, 18, 6, 27, 4, 211, 24, 162, 122, 55, 168, 18, 2, 155, 24, 98, 122, ++ 133, 73, 154, 24, 254, 247, 205, 252, 1, 240, 8, 188, 162, 120, 99, ++ 120, 18, 2, 55, 168, 129, 73, 210, 24, 254, 247, 195, 252, 4, 45, 65, ++ 242, 253, 131, 35, 121, 226, 120, 27, 2, 55, 168, 124, 73, 154, 24, ++ 254, 247, 184, 252, 1, 240, 243, 187, 34, 121, 227, 120, 18, 6, 27, ++ 4, 210, 24, 163, 120, 55, 168, 27, 2, 210, 24, 99, 120, 117, 73, 210, ++ 24, 254, 247, 168, 252, 6, 45, 65, 242, 226, 131, 34, 122, 227, 121, ++ 18, 6, 27, 4, 211, 24, 162, 121, 55, 168, 18, 2, 155, 24, 98, 121, 110, ++ 73, 154, 24, 254, 247, 151, 252, 1, 240, 210, 187, 223, 248, 188, 145, ++ 79, 240, 1, 8, 168, 69, 129, 242, 203, 131, 34, 121, 227, 120, 18, 6, ++ 27, 4, 210, 24, 163, 120, 73, 70, 27, 2, 210, 24, 99, 120, 55, 168, ++ 210, 24, 8, 241, 4, 8, 254, 247, 126, 252, 4, 52, 184, 241, 25, 15, ++ 9, 241, 24, 9, 230, 209, 1, 240, 179, 187, 223, 248, 128, 145, 79, 240, ++ 1, 8, 168, 69, 129, 242, 172, 131, 34, 121, 227, 120, 18, 6, 27, 4, ++ 210, 24, 163, 120, 73, 70, 27, 2, 210, 24, 99, 120, 55, 168, 210, 24, ++ 8, 241, 4, 8, 254, 247, 95, 252, 4, 52, 184, 241, 13, 15, 9, 241, 19, ++ 9, 230, 209, 1, 240, 148, 187, 223, 248, 72, 145, 79, 240, 1, 8, 168, ++ 69, 129, 242, 141, 131, 34, 121, 227, 120, 18, 6, 27, 4, 210, 24, 163, ++ 120, 73, 70, 27, 2, 210, 24, 99, 120, 55, 168, 210, 24, 8, 241, 4, 8, ++ 254, 247, 64, 252, 4, 52, 184, 241, 13, 15, 9, 241, 20, 9, 230, 209, ++ 1, 240, 117, 187, 223, 248, 12, 145, 79, 240, 1, 8, 168, 69, 129, 242, ++ 110, 131, 34, 121, 227, 120, 18, 6, 27, 4, 210, 24, 163, 120, 73, 70, ++ 27, 2, 210, 24, 99, 120, 55, 168, 210, 24, 8, 241, 4, 8, 254, 247, 33, ++ 252, 4, 52, 184, 241, 13, 15, 9, 241, 20, 9, 230, 209, 1, 240, 86, 187, ++ 223, 248, 212, 144, 79, 240, 1, 8, 168, 69, 129, 242, 79, 131, 34, 121, ++ 227, 120, 18, 6, 27, 4, 210, 24, 163, 120, 73, 70, 27, 2, 210, 24, 99, ++ 120, 55, 168, 210, 24, 8, 241, 4, 8, 254, 247, 2, 252, 4, 52, 184, 241, ++ 13, 15, 9, 241, 20, 9, 230, 209, 1, 240, 55, 187, 163, 120, 98, 120, ++ 27, 2, 55, 168, 28, 73, 154, 24, 254, 247, 242, 251, 1, 240, 45, 187, ++ 163, 120, 98, 120, 27, 2, 55, 168, 24, 73, 154, 24, 254, 247, 232, 251, ++ 1, 240, 35, 187, 34, 121, 227, 120, 18, 6, 27, 4, 211, 24, 162, 120, ++ 100, 120, 18, 2, 155, 24, 55, 168, 17, 73, 1, 34, 27, 25, 254, 247, ++ 215, 251, 1, 240, 18, 187, 0, 191, 100, 149, 5, 0, 88, 147, 5, 0, 27, ++ 148, 5, 0, 228, 140, 5, 0, 189, 140, 5, 0, 122, 148, 5, 0, 240, 150, ++ 5, 0, 102, 146, 5, 0, 0, 150, 5, 0, 19, 150, 5, 0, 13, 149, 5, 0, 36, ++ 149, 5, 0, 29, 146, 5, 0, 155, 151, 5, 0, 159, 148, 5, 0, 253, 141, ++ 5, 0, 198, 143, 5, 0, 251, 139, 5, 0, 172, 152, 5, 0, 84, 151, 5, 0, ++ 34, 121, 227, 120, 18, 6, 27, 4, 211, 24, 162, 120, 100, 120, 18, 2, ++ 155, 24, 55, 168, 151, 73, 2, 34, 27, 25, 254, 247, 157, 251, 1, 240, ++ 216, 186, 55, 168, 148, 73, 98, 120, 254, 247, 150, 251, 1, 240, 209, ++ 186, 146, 73, 98, 120, 7, 241, 2, 8, 55, 168, 254, 247, 141, 251, 22, ++ 248, 8, 32, 143, 73, 18, 9, 55, 168, 254, 247, 134, 251, 22, 248, 8, ++ 32, 55, 168, 140, 73, 2, 240, 15, 2, 254, 247, 126, 251, 3, 45, 65, ++ 242, 184, 130, 226, 120, 55, 168, 136, 73, 254, 247, 118, 251, 7, 241, ++ 5, 8, 34, 121, 55, 168, 133, 73, 254, 247, 111, 251, 22, 248, 8, 32, ++ 55, 168, 146, 8, 131, 73, 254, 247, 104, 251, 22, 248, 8, 32, 55, 168, ++ 129, 73, 2, 240, 3, 2, 254, 247, 96, 251, 55, 168, 127, 73, 162, 121, ++ 254, 247, 91, 251, 1, 240, 150, 186, 148, 248, 2, 128, 99, 120, 79, ++ 234, 8, 40, 152, 68, 31, 250, 136, 248, 79, 234, 216, 34, 55, 168, 119, ++ 73, 254, 247, 75, 251, 8, 244, 128, 99, 2, 34, 155, 10, 55, 168, 116, ++ 73, 254, 247, 67, 251, 8, 244, 0, 115, 2, 34, 91, 10, 55, 168, 113, ++ 73, 254, 247, 59, 251, 8, 244, 248, 115, 2, 34, 27, 9, 55, 168, 110, ++ 73, 254, 247, 51, 251, 8, 240, 14, 3, 2, 34, 91, 8, 55, 168, 107, 73, ++ 254, 247, 43, 251, 2, 34, 8, 240, 1, 3, 55, 168, 105, 73, 254, 247, ++ 36, 251, 35, 121, 228, 120, 27, 2, 28, 25, 164, 178, 226, 10, 55, 168, ++ 101, 73, 254, 247, 26, 251, 4, 244, 128, 99, 5, 34, 155, 10, 55, 168, ++ 92, 73, 254, 247, 18, 251, 4, 244, 0, 115, 5, 34, 91, 10, 55, 168, 89, ++ 73, 254, 247, 10, 251, 4, 244, 248, 115, 5, 34, 27, 9, 55, 168, 86, ++ 73, 254, 247, 2, 251, 4, 240, 14, 3, 5, 34, 91, 8, 55, 168, 83, 73, ++ 254, 247, 250, 250, 55, 168, 82, 73, 5, 34, 4, 240, 1, 3, 254, 247, ++ 243, 250, 1, 240, 46, 186, 162, 120, 99, 120, 18, 2, 210, 24, 55, 168, ++ 77, 73, 254, 247, 233, 250, 148, 248, 4, 224, 227, 120, 79, 234, 14, ++ 46, 0, 34, 115, 68, 55, 168, 73, 73, 254, 247, 222, 250, 33, 122, 226, ++ 121, 9, 2, 138, 24, 148, 248, 6, 224, 99, 121, 0, 146, 161, 122, 98, ++ 122, 9, 2, 79, 234, 14, 46, 138, 24, 115, 68, 1, 146, 55, 168, 0, 34, ++ 63, 73, 254, 247, 201, 250, 34, 123, 227, 122, 0, 146, 98, 123, 55, ++ 168, 1, 146, 162, 123, 59, 73, 2, 146, 0, 34, 254, 247, 189, 250, 161, ++ 124, 98, 124, 9, 2, 138, 24, 148, 248, 16, 224, 227, 123, 0, 146, 33, ++ 125, 226, 124, 9, 2, 138, 24, 1, 146, 161, 125, 98, 125, 9, 2, 138, ++ 24, 2, 146, 33, 126, 226, 125, 9, 2, 138, 24, 3, 146, 161, 126, 98, ++ 126, 9, 2, 138, 24, 4, 146, 33, 127, 226, 126, 9, 2, 138, 24, 5, 146, ++ 161, 127, 98, 127, 9, 2, 138, 24, 6, 146, 148, 248, 32, 16, 226, 127, ++ 9, 2, 138, 24, 7, 146, 148, 248, 34, 16, 148, 248, 33, 32, 9, 2, 138, ++ 24, 8, 146, 148, 248, 36, 16, 148, 248, 35, 32, 9, 2, 138, 24, 9, 146, ++ 148, 248, 38, 32, 148, 248, 37, 16, 18, 2, 82, 24, 79, 234, 14, 46, ++ 10, 146, 55, 168, 24, 73, 0, 34, 115, 68, 254, 247, 116, 250, 1, 240, ++ 175, 185, 159, 148, 5, 0, 180, 144, 5, 0, 228, 141, 5, 0, 150, 142, ++ 5, 0, 99, 141, 5, 0, 59, 139, 5, 0, 249, 142, 5, 0, 109, 148, 5, 0, ++ 235, 148, 5, 0, 118, 149, 5, 0, 210, 144, 5, 0, 255, 148, 5, 0, 117, ++ 146, 5, 0, 59, 149, 5, 0, 253, 151, 5, 0, 37, 151, 5, 0, 60, 138, 5, ++ 0, 169, 143, 5, 0, 174, 140, 5, 0, 133, 138, 5, 0, 12, 143, 5, 0, 82, ++ 143, 5, 0, 148, 248, 2, 224, 99, 120, 79, 234, 14, 46, 1, 34, 115, 68, ++ 55, 168, 170, 73, 254, 247, 59, 250, 161, 121, 98, 121, 9, 2, 138, 24, ++ 148, 248, 4, 224, 227, 120, 0, 146, 33, 122, 226, 121, 9, 2, 79, 234, ++ 14, 46, 138, 24, 115, 68, 1, 146, 55, 168, 1, 34, 161, 73, 254, 247, ++ 38, 250, 162, 122, 99, 122, 0, 146, 226, 122, 55, 168, 1, 146, 34, 123, ++ 157, 73, 2, 146, 1, 34, 254, 247, 26, 250, 33, 124, 226, 123, 9, 2, ++ 138, 24, 148, 248, 14, 224, 99, 123, 0, 146, 161, 124, 98, 124, 9, 2, ++ 138, 24, 1, 146, 33, 125, 226, 124, 9, 2, 138, 24, 2, 146, 161, 125, ++ 98, 125, 9, 2, 138, 24, 3, 146, 33, 126, 226, 125, 9, 2, 138, 24, 4, ++ 146, 161, 126, 98, 126, 9, 2, 138, 24, 5, 146, 33, 127, 226, 126, 9, ++ 2, 138, 24, 6, 146, 161, 127, 98, 127, 9, 2, 138, 24, 7, 146, 148, 248, ++ 32, 16, 226, 127, 9, 2, 138, 24, 8, 146, 148, 248, 34, 16, 148, 248, ++ 33, 32, 9, 2, 138, 24, 9, 146, 148, 248, 36, 32, 148, 248, 35, 16, 18, ++ 2, 82, 24, 79, 234, 14, 46, 10, 146, 55, 168, 122, 73, 1, 34, 115, 68, ++ 254, 247, 211, 249, 1, 240, 14, 185, 148, 248, 2, 224, 99, 120, 79, ++ 234, 14, 46, 2, 34, 115, 68, 55, 168, 112, 73, 254, 247, 198, 249, 161, ++ 121, 98, 121, 9, 2, 138, 24, 148, 248, 4, 224, 227, 120, 0, 146, 33, ++ 122, 226, 121, 9, 2, 79, 234, 14, 46, 138, 24, 115, 68, 1, 146, 55, ++ 168, 2, 34, 102, 73, 254, 247, 177, 249, 162, 122, 99, 122, 0, 146, ++ 226, 122, 55, 168, 1, 146, 34, 123, 98, 73, 2, 146, 2, 34, 254, 247, ++ 165, 249, 33, 124, 226, 123, 9, 2, 138, 24, 148, 248, 14, 224, 99, 123, ++ 0, 146, 161, 124, 98, 124, 9, 2, 138, 24, 1, 146, 33, 125, 226, 124, ++ 9, 2, 138, 24, 2, 146, 161, 125, 98, 125, 9, 2, 138, 24, 3, 146, 33, ++ 126, 226, 125, 9, 2, 138, 24, 4, 146, 161, 126, 98, 126, 9, 2, 138, ++ 24, 5, 146, 33, 127, 226, 126, 9, 2, 138, 24, 6, 146, 161, 127, 98, ++ 127, 9, 2, 138, 24, 7, 146, 148, 248, 32, 16, 226, 127, 9, 2, 138, 24, ++ 8, 146, 148, 248, 34, 16, 148, 248, 33, 32, 9, 2, 138, 24, 9, 146, 148, ++ 248, 36, 32, 148, 248, 35, 16, 18, 2, 82, 24, 79, 234, 14, 46, 10, 146, ++ 55, 168, 64, 73, 2, 34, 115, 68, 254, 247, 94, 249, 1, 240, 153, 184, ++ 98, 120, 55, 168, 60, 73, 254, 247, 87, 249, 1, 34, 163, 120, 55, 168, ++ 58, 73, 254, 247, 81, 249, 2, 34, 227, 120, 55, 168, 55, 73, 254, 247, ++ 75, 249, 99, 121, 34, 121, 3, 240, 1, 3, 27, 2, 55, 168, 52, 73, 154, ++ 24, 254, 247, 65, 249, 1, 240, 124, 184, 162, 120, 99, 120, 18, 2, 211, ++ 24, 0, 147, 40, 34, 0, 35, 55, 168, 46, 73, 254, 247, 52, 249, 34, 121, ++ 227, 120, 18, 2, 211, 24, 0, 147, 40, 34, 1, 35, 55, 168, 40, 73, 254, ++ 247, 41, 249, 162, 121, 99, 121, 18, 2, 211, 24, 0, 147, 40, 34, 2, ++ 35, 55, 168, 35, 73, 254, 247, 30, 249, 34, 122, 227, 121, 18, 2, 211, ++ 24, 0, 147, 80, 34, 0, 35, 55, 168, 29, 73, 254, 247, 19, 249, 162, ++ 122, 99, 122, 18, 2, 211, 24, 0, 147, 80, 34, 1, 35, 55, 168, 24, 73, ++ 254, 247, 8, 249, 35, 123, 226, 122, 27, 2, 155, 24, 0, 147, 55, 168, ++ 19, 73, 80, 34, 2, 35, 254, 247, 253, 248, 1, 240, 56, 184, 162, 120, ++ 99, 120, 18, 2, 210, 24, 55, 168, 14, 73, 254, 247, 243, 248, 35, 121, ++ 226, 120, 27, 2, 55, 168, 12, 73, 154, 24, 254, 247, 235, 248, 1, 240, ++ 38, 184, 0, 191, 174, 140, 5, 0, 133, 138, 5, 0, 12, 143, 5, 0, 82, ++ 143, 5, 0, 73, 139, 5, 0, 88, 138, 5, 0, 145, 150, 5, 0, 89, 148, 5, ++ 0, 117, 139, 5, 0, 182, 149, 5, 0, 148, 248, 4, 224, 227, 120, 79, 234, ++ 14, 110, 27, 4, 158, 68, 163, 120, 108, 34, 27, 2, 158, 68, 99, 120, ++ 55, 168, 115, 68, 151, 73, 254, 247, 195, 248, 148, 248, 8, 224, 227, ++ 121, 79, 234, 14, 110, 27, 4, 158, 68, 163, 121, 108, 34, 27, 2, 158, ++ 68, 99, 121, 55, 168, 115, 68, 144, 73, 254, 247, 178, 248, 148, 248, ++ 12, 224, 227, 122, 79, 234, 14, 110, 27, 4, 158, 68, 163, 122, 109, ++ 34, 27, 2, 158, 68, 99, 122, 55, 168, 115, 68, 134, 73, 254, 247, 161, ++ 248, 148, 248, 16, 224, 227, 123, 79, 234, 14, 110, 27, 4, 158, 68, ++ 163, 123, 109, 34, 27, 2, 158, 68, 99, 123, 55, 168, 115, 68, 127, 73, ++ 254, 247, 144, 248, 148, 248, 20, 224, 227, 124, 79, 234, 14, 110, 27, ++ 4, 158, 68, 163, 124, 104, 34, 27, 2, 158, 68, 99, 124, 55, 168, 115, ++ 68, 117, 73, 254, 247, 127, 248, 148, 248, 24, 224, 227, 125, 79, 234, ++ 14, 110, 27, 4, 158, 68, 163, 125, 104, 34, 27, 2, 158, 68, 99, 125, ++ 55, 168, 115, 68, 110, 73, 254, 247, 110, 248, 148, 248, 26, 224, 99, ++ 126, 79, 234, 14, 46, 108, 34, 115, 68, 55, 168, 105, 73, 254, 247, ++ 99, 248, 148, 248, 28, 224, 227, 126, 79, 234, 14, 46, 109, 34, 115, ++ 68, 55, 168, 100, 73, 254, 247, 88, 248, 163, 127, 100, 127, 27, 2, ++ 55, 168, 96, 73, 104, 34, 27, 25, 254, 247, 79, 248, 0, 240, 138, 191, ++ 148, 248, 2, 224, 99, 120, 79, 234, 14, 46, 115, 68, 104, 34, 55, 168, ++ 90, 73, 254, 247, 66, 248, 34, 121, 227, 120, 18, 2, 211, 24, 0, 147, ++ 104, 34, 108, 35, 55, 168, 85, 73, 254, 247, 55, 248, 162, 121, 99, ++ 121, 18, 2, 211, 24, 0, 147, 104, 34, 108, 35, 55, 168, 81, 73, 254, ++ 247, 44, 248, 34, 122, 227, 121, 18, 2, 211, 24, 0, 147, 104, 34, 109, ++ 35, 55, 168, 74, 73, 254, 247, 33, 248, 162, 122, 99, 122, 18, 2, 211, ++ 24, 0, 147, 104, 34, 109, 35, 55, 168, 70, 73, 254, 247, 22, 248, 34, ++ 123, 227, 122, 18, 2, 211, 24, 104, 34, 0, 147, 55, 168, 19, 70, 63, ++ 73, 254, 247, 11, 248, 162, 123, 99, 123, 18, 2, 211, 24, 104, 34, 0, ++ 147, 55, 168, 19, 70, 59, 73, 254, 247, 0, 248, 148, 248, 16, 224, 227, ++ 123, 79, 234, 14, 46, 115, 68, 108, 34, 55, 168, 51, 73, 253, 247, 245, ++ 255, 162, 124, 99, 124, 18, 2, 211, 24, 108, 34, 0, 147, 55, 168, 19, ++ 70, 47, 73, 253, 247, 234, 255, 34, 125, 227, 124, 18, 2, 211, 24, 108, ++ 34, 0, 147, 55, 168, 19, 70, 42, 73, 253, 247, 223, 255, 162, 125, 99, ++ 125, 18, 2, 211, 24, 0, 147, 108, 34, 7, 241, 24, 8, 109, 35, 55, 168, ++ 35, 73, 253, 247, 210, 255, 22, 248, 8, 32, 227, 125, 18, 2, 211, 24, ++ 0, 147, 108, 34, 109, 35, 7, 241, 26, 9, 55, 168, 29, 73, 253, 247, ++ 196, 255, 22, 248, 9, 32, 99, 126, 18, 2, 211, 24, 0, 147, 108, 34, ++ 104, 35, 55, 168, 22, 73, 253, 247, 184, 255, 34, 127, 227, 126, 18, ++ 2, 211, 24, 0, 147, 108, 34, 104, 35, 55, 168, 17, 73, 253, 247, 173, ++ 255, 163, 127, 22, 248, 8, 224, 27, 2, 104, 34, 115, 68, 55, 168, 13, ++ 73, 253, 247, 163, 255, 148, 248, 32, 48, 22, 248, 9, 64, 27, 2, 55, ++ 168, 9, 73, 108, 34, 27, 25, 253, 247, 152, 255, 0, 240, 211, 190, 150, ++ 143, 5, 0, 243, 152, 5, 0, 64, 150, 5, 0, 136, 146, 5, 0, 59, 147, 5, ++ 0, 166, 142, 5, 0, 204, 142, 5, 0, 99, 120, 0, 34, 55, 168, 170, 73, ++ 3, 240, 31, 3, 253, 247, 128, 255, 163, 120, 1, 34, 55, 168, 166, 73, ++ 3, 240, 31, 3, 253, 247, 120, 255, 227, 120, 2, 34, 55, 168, 162, 73, ++ 3, 240, 31, 3, 253, 247, 112, 255, 98, 121, 35, 121, 2, 240, 31, 2, ++ 0, 146, 162, 121, 55, 168, 2, 240, 31, 2, 1, 146, 226, 121, 155, 73, ++ 2, 240, 31, 2, 2, 146, 3, 240, 31, 3, 0, 34, 253, 247, 92, 255, 98, ++ 122, 35, 122, 2, 240, 31, 2, 0, 146, 162, 122, 55, 168, 2, 240, 31, ++ 2, 1, 146, 226, 122, 145, 73, 2, 240, 31, 2, 2, 146, 3, 240, 31, 3, ++ 1, 34, 253, 247, 72, 255, 98, 123, 35, 123, 2, 240, 31, 2, 0, 146, 162, ++ 123, 55, 168, 2, 240, 31, 2, 1, 146, 226, 123, 135, 73, 2, 240, 31, ++ 2, 2, 146, 3, 240, 31, 3, 2, 34, 253, 247, 52, 255, 0, 240, 111, 190, ++ 99, 120, 0, 34, 55, 168, 129, 73, 3, 240, 63, 3, 253, 247, 42, 255, ++ 163, 120, 1, 34, 55, 168, 125, 73, 3, 240, 31, 3, 253, 247, 34, 255, ++ 227, 120, 2, 34, 55, 168, 121, 73, 3, 240, 31, 3, 253, 247, 26, 255, ++ 98, 121, 35, 121, 2, 240, 63, 2, 0, 146, 162, 121, 55, 168, 2, 240, ++ 63, 2, 1, 146, 226, 121, 114, 73, 2, 240, 63, 2, 2, 146, 3, 240, 63, ++ 3, 0, 34, 253, 247, 6, 255, 98, 122, 35, 122, 2, 240, 31, 2, 0, 146, ++ 162, 122, 55, 168, 2, 240, 31, 2, 1, 146, 226, 122, 104, 73, 2, 240, ++ 31, 2, 2, 146, 3, 240, 31, 3, 1, 34, 253, 247, 242, 254, 98, 123, 35, ++ 123, 2, 240, 31, 2, 0, 146, 162, 123, 55, 168, 2, 240, 31, 2, 1, 146, ++ 226, 123, 94, 73, 2, 240, 31, 2, 2, 146, 3, 240, 31, 3, 2, 34, 253, ++ 247, 222, 254, 0, 240, 25, 190, 0, 34, 99, 120, 55, 168, 88, 73, 253, ++ 247, 214, 254, 1, 34, 163, 120, 55, 168, 85, 73, 253, 247, 208, 254, ++ 2, 34, 227, 120, 55, 168, 82, 73, 253, 247, 202, 254, 0, 34, 35, 121, ++ 55, 168, 80, 73, 253, 247, 196, 254, 1, 34, 99, 121, 55, 168, 77, 73, ++ 253, 247, 190, 254, 55, 168, 75, 73, 2, 34, 163, 121, 253, 247, 184, ++ 254, 0, 240, 243, 189, 148, 248, 2, 128, 99, 120, 79, 234, 8, 40, 152, ++ 68, 31, 250, 136, 248, 79, 234, 216, 51, 0, 147, 5, 34, 0, 35, 55, 168, ++ 65, 73, 253, 247, 165, 254, 8, 244, 240, 67, 219, 18, 0, 147, 5, 34, ++ 0, 35, 55, 168, 61, 73, 253, 247, 155, 254, 8, 244, 224, 99, 27, 18, ++ 0, 147, 5, 34, 0, 35, 55, 168, 57, 73, 253, 247, 145, 254, 8, 240, 128, ++ 3, 219, 17, 0, 147, 2, 34, 0, 35, 55, 168, 50, 73, 253, 247, 135, 254, ++ 8, 240, 120, 3, 219, 16, 0, 147, 2, 34, 0, 35, 55, 168, 46, 73, 253, ++ 247, 125, 254, 8, 240, 7, 3, 0, 147, 2, 34, 0, 35, 55, 168, 43, 73, ++ 253, 247, 116, 254, 35, 121, 228, 120, 27, 2, 28, 25, 164, 178, 79, ++ 240, 0, 8, 79, 234, 212, 57, 5, 34, 104, 35, 55, 168, 36, 73, 4, 244, ++ 240, 74, 79, 234, 234, 42, 141, 232, 0, 3, 4, 244, 224, 100, 253, 247, ++ 93, 254, 5, 34, 104, 35, 55, 168, 30, 73, 36, 18, 141, 232, 0, 5, 253, ++ 247, 84, 254, 104, 35, 55, 168, 27, 73, 5, 34, 205, 248, 0, 128, 1, ++ 148, 253, 247, 75, 254, 5, 34, 55, 168, 109, 35, 20, 73, 141, 232, 0, ++ 3, 253, 247, 67, 254, 5, 34, 109, 35, 55, 168, 17, 73, 141, 232, 0, ++ 5, 253, 247, 59, 254, 55, 168, 15, 73, 5, 34, 109, 35, 205, 248, 0, ++ 128, 1, 148, 253, 247, 50, 254, 0, 240, 109, 189, 21, 144, 5, 0, 202, ++ 140, 5, 0, 150, 140, 5, 0, 39, 148, 5, 0, 176, 145, 5, 0, 225, 142, ++ 5, 0, 105, 150, 5, 0, 201, 151, 5, 0, 179, 147, 5, 0, 105, 138, 5, 0, ++ 182, 141, 5, 0, 117, 145, 5, 0, 148, 248, 2, 128, 99, 120, 79, 234, ++ 8, 40, 152, 68, 31, 250, 136, 248, 79, 234, 216, 51, 0, 147, 5, 34, ++ 1, 35, 55, 168, 181, 73, 253, 247, 7, 254, 8, 244, 240, 67, 219, 18, ++ 0, 147, 5, 34, 1, 35, 55, 168, 177, 73, 253, 247, 253, 253, 8, 244, ++ 224, 99, 27, 18, 0, 147, 5, 34, 1, 35, 55, 168, 173, 73, 253, 247, 243, ++ 253, 8, 240, 128, 3, 219, 17, 0, 147, 2, 34, 1, 35, 55, 168, 166, 73, ++ 253, 247, 233, 253, 8, 240, 120, 3, 219, 16, 0, 147, 2, 34, 1, 35, 55, ++ 168, 162, 73, 253, 247, 223, 253, 8, 240, 7, 3, 0, 147, 2, 34, 1, 35, ++ 55, 168, 159, 73, 253, 247, 214, 253, 35, 121, 228, 120, 27, 2, 28, ++ 25, 164, 178, 79, 240, 1, 8, 79, 234, 212, 57, 5, 34, 104, 35, 55, 168, ++ 152, 73, 4, 244, 240, 74, 79, 234, 234, 42, 141, 232, 0, 3, 4, 244, ++ 224, 100, 253, 247, 191, 253, 5, 34, 104, 35, 55, 168, 146, 73, 36, ++ 18, 141, 232, 0, 5, 253, 247, 182, 253, 104, 35, 55, 168, 143, 73, 5, ++ 34, 205, 248, 0, 128, 1, 148, 253, 247, 173, 253, 5, 34, 55, 168, 109, ++ 35, 136, 73, 141, 232, 0, 3, 253, 247, 165, 253, 5, 34, 109, 35, 55, ++ 168, 133, 73, 141, 232, 0, 5, 253, 247, 157, 253, 55, 168, 131, 73, ++ 5, 34, 109, 35, 205, 248, 0, 128, 1, 148, 253, 247, 148, 253, 0, 240, ++ 207, 188, 148, 248, 2, 128, 99, 120, 79, 234, 8, 40, 152, 68, 31, 250, ++ 136, 248, 79, 234, 216, 51, 0, 147, 5, 34, 2, 35, 55, 168, 114, 73, ++ 253, 247, 129, 253, 8, 244, 240, 67, 219, 18, 0, 147, 5, 34, 2, 35, ++ 55, 168, 110, 73, 253, 247, 119, 253, 8, 244, 224, 99, 27, 18, 0, 147, ++ 5, 34, 2, 35, 55, 168, 106, 73, 253, 247, 109, 253, 8, 240, 128, 3, ++ 2, 34, 219, 17, 0, 147, 55, 168, 19, 70, 99, 73, 253, 247, 99, 253, ++ 8, 240, 120, 3, 2, 34, 219, 16, 0, 147, 55, 168, 19, 70, 95, 73, 253, ++ 247, 89, 253, 2, 34, 8, 240, 7, 3, 0, 147, 55, 168, 19, 70, 92, 73, ++ 253, 247, 80, 253, 35, 121, 228, 120, 27, 2, 28, 25, 164, 178, 79, 240, ++ 2, 8, 79, 234, 212, 57, 5, 34, 104, 35, 55, 168, 85, 73, 4, 244, 240, ++ 74, 79, 234, 234, 42, 141, 232, 0, 3, 4, 244, 224, 100, 253, 247, 57, ++ 253, 5, 34, 104, 35, 55, 168, 79, 73, 36, 18, 141, 232, 0, 5, 253, 247, ++ 48, 253, 5, 34, 104, 35, 55, 168, 76, 73, 205, 248, 0, 128, 1, 148, ++ 253, 247, 39, 253, 109, 35, 55, 168, 70, 73, 5, 34, 141, 232, 0, 3, ++ 253, 247, 31, 253, 5, 34, 55, 168, 109, 35, 66, 73, 141, 232, 0, 5, ++ 253, 247, 23, 253, 55, 168, 64, 73, 5, 34, 109, 35, 205, 248, 0, 128, ++ 1, 148, 253, 247, 14, 253, 0, 240, 73, 188, 148, 248, 2, 224, 99, 120, ++ 79, 234, 14, 46, 40, 34, 115, 68, 55, 168, 56, 73, 253, 247, 1, 253, ++ 148, 248, 4, 224, 227, 120, 79, 234, 14, 46, 40, 34, 115, 68, 55, 168, ++ 52, 73, 253, 247, 246, 252, 148, 248, 6, 224, 99, 121, 79, 234, 14, ++ 46, 80, 34, 115, 68, 55, 168, 45, 73, 253, 247, 235, 252, 35, 122, 228, ++ 121, 27, 2, 55, 168, 43, 73, 80, 34, 27, 25, 253, 247, 226, 252, 0, ++ 240, 29, 188, 162, 120, 99, 120, 0, 146, 226, 120, 37, 33, 1, 146, 34, ++ 121, 29, 168, 2, 146, 98, 121, 3, 146, 162, 121, 4, 146, 226, 121, 5, ++ 146, 34, 122, 6, 146, 98, 122, 7, 146, 162, 122, 8, 146, 226, 122, 9, ++ 146, 34, 123, 10, 146, 98, 123, 11, 146, 162, 123, 12, 146, 226, 123, ++ 13, 146, 34, 124, 14, 146, 24, 74, 183, 243, 130, 245, 55, 168, 23, ++ 73, 29, 170, 253, 247, 183, 252, 242, 227, 124, 28, 50, 93, 55, 168, ++ 20, 73, 2, 240, 127, 2, 253, 247, 174, 252, 50, 93, 55, 168, 17, 73, ++ 210, 9, 253, 247, 168, 252, 227, 227, 163, 120, 98, 120, 55, 168, 14, ++ 73, 66, 234, 3, 34, 253, 247, 159, 252, 218, 227, 105, 150, 5, 0, 201, ++ 151, 5, 0, 179, 147, 5, 0, 105, 138, 5, 0, 182, 141, 5, 0, 117, 145, ++ 5, 0, 176, 148, 5, 0, 120, 140, 5, 0, 178, 27, 4, 0, 204, 148, 5, 0, ++ 22, 152, 5, 0, 202, 149, 5, 0, 212, 148, 5, 0, 163, 120, 98, 120, 55, ++ 168, 148, 73, 66, 234, 3, 34, 253, 247, 124, 252, 183, 227, 227, 120, ++ 34, 121, 27, 4, 67, 234, 2, 99, 98, 120, 55, 168, 19, 67, 162, 120, ++ 141, 73, 67, 234, 2, 34, 253, 247, 109, 252, 168, 227, 227, 120, 34, ++ 121, 27, 4, 67, 234, 2, 99, 98, 120, 55, 168, 19, 67, 162, 120, 135, ++ 73, 67, 234, 2, 34, 253, 247, 94, 252, 153, 227, 227, 120, 34, 121, ++ 27, 4, 67, 234, 2, 99, 98, 120, 55, 168, 19, 67, 162, 120, 128, 73, ++ 67, 234, 2, 34, 253, 247, 79, 252, 138, 227, 163, 120, 98, 120, 55, ++ 168, 125, 73, 66, 234, 3, 34, 253, 247, 70, 252, 129, 227, 163, 120, ++ 98, 120, 55, 168, 121, 73, 66, 234, 3, 34, 253, 247, 61, 252, 120, 227, ++ 163, 120, 98, 120, 55, 168, 118, 73, 66, 234, 3, 34, 253, 247, 52, 252, ++ 111, 227, 163, 120, 98, 120, 55, 168, 114, 73, 66, 234, 3, 34, 253, ++ 247, 43, 252, 102, 227, 148, 248, 1, 144, 95, 234, 153, 9, 0, 240, 97, ++ 131, 79, 240, 0, 8, 161, 121, 226, 121, 9, 2, 148, 248, 3, 224, 65, ++ 234, 2, 65, 98, 121, 35, 121, 10, 67, 79, 234, 14, 46, 78, 234, 3, 78, ++ 163, 120, 0, 146, 97, 122, 162, 122, 9, 2, 65, 234, 2, 65, 34, 122, ++ 55, 168, 10, 67, 1, 146, 33, 123, 98, 123, 9, 2, 65, 234, 2, 65, 226, ++ 122, 78, 234, 3, 3, 10, 67, 2, 146, 91, 73, 66, 70, 8, 241, 1, 8, 253, ++ 247, 249, 251, 12, 52, 200, 69, 211, 219, 49, 227, 55, 168, 86, 73, ++ 98, 120, 253, 247, 240, 251, 43, 227, 55, 168, 84, 73, 98, 120, 253, ++ 247, 234, 251, 37, 227, 34, 122, 225, 121, 35, 121, 17, 67, 162, 121, ++ 148, 248, 3, 224, 17, 67, 98, 121, 78, 234, 3, 14, 163, 120, 10, 67, ++ 78, 234, 3, 14, 99, 120, 0, 146, 34, 123, 225, 122, 78, 234, 3, 3, 17, ++ 67, 162, 122, 55, 168, 17, 67, 98, 122, 10, 67, 1, 146, 34, 124, 225, ++ 123, 17, 67, 162, 123, 17, 67, 98, 123, 10, 67, 2, 146, 65, 73, 0, 34, ++ 253, 247, 193, 251, 34, 126, 225, 125, 35, 125, 17, 67, 162, 125, 148, ++ 248, 19, 224, 17, 67, 98, 125, 78, 234, 3, 14, 163, 124, 10, 67, 78, ++ 234, 3, 14, 99, 124, 0, 146, 34, 127, 225, 126, 55, 168, 17, 67, 162, ++ 126, 78, 234, 3, 3, 17, 67, 98, 126, 10, 67, 1, 146, 148, 248, 32, 32, ++ 225, 127, 17, 67, 162, 127, 10, 67, 97, 127, 10, 67, 2, 146, 44, 73, ++ 1, 34, 253, 247, 152, 251, 211, 226, 163, 120, 100, 120, 27, 2, 28, ++ 25, 164, 178, 4, 240, 15, 3, 0, 147, 40, 34, 0, 35, 55, 168, 37, 73, ++ 253, 247, 137, 251, 4, 240, 240, 3, 27, 17, 0, 147, 40, 34, 1, 35, 55, ++ 168, 32, 73, 253, 247, 127, 251, 4, 244, 112, 99, 27, 18, 0, 147, 40, ++ 34, 2, 35, 55, 168, 27, 73, 253, 247, 117, 251, 55, 168, 26, 73, 40, ++ 34, 227, 11, 253, 247, 111, 251, 170, 226, 33, 121, 226, 120, 9, 2, ++ 138, 24, 148, 248, 2, 224, 99, 120, 0, 146, 162, 121, 97, 121, 18, 2, ++ 82, 24, 79, 234, 14, 46, 1, 146, 55, 168, 16, 73, 0, 34, 115, 68, 253, ++ 247, 89, 251, 148, 226, 55, 140, 5, 0, 163, 150, 5, 0, 187, 150, 5, ++ 0, 211, 150, 5, 0, 188, 145, 5, 0, 209, 145, 5, 0, 230, 145, 5, 0, 251, ++ 145, 5, 0, 204, 147, 5, 0, 136, 148, 5, 0, 56, 141, 5, 0, 221, 144, ++ 5, 0, 253, 144, 5, 0, 81, 150, 5, 0, 183, 138, 5, 0, 33, 121, 226, 120, ++ 9, 2, 138, 24, 148, 248, 2, 224, 99, 120, 0, 146, 161, 121, 98, 121, ++ 9, 2, 138, 24, 1, 146, 33, 122, 226, 121, 9, 2, 138, 24, 2, 146, 161, ++ 122, 98, 122, 9, 2, 138, 24, 3, 146, 33, 123, 226, 122, 9, 2, 138, 24, ++ 4, 146, 161, 123, 98, 123, 9, 2, 138, 24, 5, 146, 33, 124, 226, 123, ++ 9, 2, 138, 24, 6, 146, 161, 124, 98, 124, 9, 2, 138, 24, 7, 146, 33, ++ 125, 226, 124, 9, 2, 138, 24, 8, 146, 161, 125, 98, 125, 9, 2, 138, ++ 24, 9, 146, 34, 126, 225, 125, 18, 2, 82, 24, 79, 234, 14, 46, 10, 146, ++ 55, 168, 123, 73, 0, 34, 115, 68, 253, 247, 248, 250, 51, 226, 33, 121, ++ 226, 120, 9, 2, 138, 24, 148, 248, 2, 224, 99, 120, 0, 146, 161, 121, ++ 98, 121, 9, 2, 138, 24, 1, 146, 33, 122, 226, 121, 9, 2, 138, 24, 2, ++ 146, 161, 122, 98, 122, 9, 2, 138, 24, 3, 146, 33, 123, 226, 122, 9, ++ 2, 138, 24, 4, 146, 161, 123, 98, 123, 9, 2, 138, 24, 5, 146, 33, 124, ++ 226, 123, 9, 2, 138, 24, 6, 146, 161, 124, 98, 124, 9, 2, 138, 24, 7, ++ 146, 33, 125, 226, 124, 9, 2, 138, 24, 8, 146, 161, 125, 98, 125, 9, ++ 2, 138, 24, 9, 146, 34, 126, 225, 125, 18, 2, 82, 24, 79, 234, 14, 46, ++ 10, 146, 55, 168, 90, 73, 0, 34, 115, 68, 253, 247, 181, 250, 240, 225, ++ 33, 121, 226, 120, 9, 2, 138, 24, 148, 248, 2, 224, 99, 120, 0, 146, ++ 161, 121, 98, 121, 9, 2, 138, 24, 1, 146, 33, 122, 226, 121, 9, 2, 138, ++ 24, 2, 146, 161, 122, 98, 122, 9, 2, 138, 24, 3, 146, 33, 123, 226, ++ 122, 9, 2, 138, 24, 4, 146, 161, 123, 98, 123, 9, 2, 138, 24, 5, 146, ++ 33, 124, 226, 123, 9, 2, 138, 24, 6, 146, 161, 124, 98, 124, 9, 2, 138, ++ 24, 7, 146, 33, 125, 226, 124, 9, 2, 138, 24, 8, 146, 161, 125, 98, ++ 125, 9, 2, 138, 24, 9, 146, 33, 126, 226, 125, 9, 2, 79, 234, 14, 46, ++ 138, 24, 10, 146, 115, 68, 0, 34, 55, 168, 57, 73, 253, 247, 114, 250, ++ 33, 127, 226, 126, 9, 2, 138, 24, 148, 248, 26, 224, 99, 126, 0, 146, ++ 161, 127, 98, 127, 9, 2, 138, 24, 1, 146, 148, 248, 32, 16, 226, 127, ++ 9, 2, 138, 24, 2, 146, 148, 248, 34, 16, 148, 248, 33, 32, 9, 2, 138, ++ 24, 3, 146, 148, 248, 36, 16, 148, 248, 35, 32, 9, 2, 138, 24, 4, 146, ++ 148, 248, 38, 16, 148, 248, 37, 32, 9, 2, 138, 24, 5, 146, 148, 248, ++ 40, 16, 148, 248, 39, 32, 9, 2, 138, 24, 6, 146, 148, 248, 42, 16, 148, ++ 248, 41, 32, 9, 2, 138, 24, 7, 146, 148, 248, 44, 16, 148, 248, 43, ++ 32, 9, 2, 138, 24, 8, 146, 148, 248, 46, 16, 148, 248, 45, 32, 9, 2, ++ 138, 24, 9, 146, 148, 248, 48, 32, 148, 248, 47, 16, 18, 2, 82, 24, ++ 79, 234, 14, 46, 10, 146, 55, 168, 16, 73, 1, 34, 115, 68, 253, 247, ++ 31, 250, 90, 225, 163, 120, 98, 120, 27, 2, 55, 168, 12, 73, 154, 24, ++ 253, 247, 22, 250, 81, 225, 55, 168, 10, 73, 98, 120, 253, 247, 16, ++ 250, 75, 225, 163, 120, 98, 120, 55, 168, 7, 73, 66, 234, 3, 34, 253, ++ 247, 7, 250, 66, 225, 179, 139, 5, 0, 240, 140, 5, 0, 98, 152, 5, 0, ++ 169, 143, 5, 0, 101, 139, 5, 0, 226, 138, 5, 0, 226, 120, 35, 121, 18, ++ 4, 66, 234, 3, 98, 99, 120, 33, 122, 26, 67, 227, 121, 32, 123, 27, ++ 4, 67, 234, 1, 99, 97, 121, 148, 248, 2, 192, 11, 67, 225, 122, 148, ++ 248, 6, 224, 9, 4, 65, 234, 0, 97, 96, 122, 66, 234, 12, 34, 1, 67, ++ 160, 122, 67, 234, 14, 35, 65, 234, 0, 33, 0, 145, 225, 123, 32, 124, ++ 9, 4, 65, 234, 0, 97, 96, 123, 1, 67, 160, 123, 65, 234, 0, 33, 1, 145, ++ 225, 124, 32, 125, 9, 4, 65, 234, 0, 97, 96, 124, 1, 67, 160, 124, 65, ++ 234, 0, 33, 2, 145, 225, 125, 32, 126, 9, 4, 65, 234, 0, 97, 96, 125, ++ 1, 67, 160, 125, 65, 234, 0, 33, 3, 145, 225, 126, 32, 127, 9, 4, 65, ++ 234, 0, 97, 96, 126, 1, 67, 160, 126, 65, 234, 0, 33, 4, 145, 225, 127, ++ 148, 248, 32, 0, 9, 4, 65, 234, 0, 97, 96, 127, 1, 67, 160, 127, 65, ++ 234, 0, 33, 5, 145, 148, 248, 35, 16, 148, 248, 36, 0, 9, 4, 65, 234, ++ 0, 97, 148, 248, 33, 0, 1, 67, 148, 248, 34, 0, 65, 234, 0, 33, 6, 145, ++ 148, 248, 39, 0, 148, 248, 40, 16, 0, 4, 64, 234, 1, 96, 148, 248, 37, ++ 16, 1, 67, 148, 248, 38, 0, 65, 234, 0, 33, 7, 145, 55, 168, 130, 73, ++ 253, 247, 127, 249, 186, 224, 226, 120, 35, 121, 18, 4, 66, 234, 3, ++ 98, 99, 120, 33, 122, 26, 67, 227, 121, 32, 123, 27, 4, 67, 234, 1, ++ 99, 97, 121, 148, 248, 2, 192, 11, 67, 225, 122, 148, 248, 6, 224, 9, ++ 4, 65, 234, 0, 97, 96, 122, 66, 234, 12, 34, 1, 67, 160, 122, 67, 234, ++ 14, 35, 65, 234, 0, 33, 0, 145, 225, 123, 32, 124, 9, 4, 65, 234, 0, ++ 97, 96, 123, 1, 67, 160, 123, 65, 234, 0, 33, 1, 145, 225, 124, 32, ++ 125, 9, 4, 65, 234, 0, 97, 96, 124, 1, 67, 160, 124, 65, 234, 0, 33, ++ 2, 145, 225, 125, 32, 126, 9, 4, 65, 234, 0, 97, 96, 125, 1, 67, 160, ++ 125, 65, 234, 0, 33, 3, 145, 225, 126, 32, 127, 9, 4, 65, 234, 0, 97, ++ 96, 126, 1, 67, 160, 126, 65, 234, 0, 33, 4, 145, 225, 127, 148, 248, ++ 32, 0, 9, 4, 65, 234, 0, 97, 96, 127, 1, 67, 160, 127, 65, 234, 0, 33, ++ 5, 145, 148, 248, 35, 16, 148, 248, 36, 0, 9, 4, 65, 234, 0, 97, 148, ++ 248, 33, 0, 1, 67, 148, 248, 34, 0, 65, 234, 0, 33, 6, 145, 148, 248, ++ 39, 0, 148, 248, 40, 16, 0, 4, 64, 234, 1, 96, 148, 248, 37, 16, 1, ++ 67, 148, 248, 38, 0, 65, 234, 0, 33, 7, 145, 55, 168, 69, 73, 253, 247, ++ 3, 249, 62, 224, 11, 45, 60, 209, 163, 120, 98, 120, 27, 2, 210, 24, ++ 55, 168, 65, 73, 253, 247, 248, 248, 35, 121, 226, 120, 27, 2, 210, ++ 24, 55, 168, 62, 73, 253, 247, 240, 248, 163, 121, 98, 121, 27, 2, 210, ++ 24, 55, 168, 59, 73, 253, 247, 232, 248, 35, 122, 226, 121, 27, 2, 210, ++ 24, 55, 168, 56, 73, 253, 247, 224, 248, 162, 122, 99, 122, 18, 2, 55, ++ 168, 53, 73, 154, 24, 253, 247, 216, 248, 19, 224, 227, 120, 34, 121, ++ 27, 4, 67, 234, 2, 99, 98, 120, 55, 168, 19, 67, 162, 120, 47, 73, 67, ++ 234, 2, 34, 253, 247, 201, 248, 4, 224, 0, 33, 20, 145, 1, 224, 1, 34, ++ 19, 146, 16, 153, 123, 25, 255, 41, 125, 244, 97, 169, 21, 154, 1, 50, ++ 21, 146, 21, 155, 27, 153, 139, 66, 125, 244, 81, 169, 17, 154, 81, ++ 28, 3, 208, 55, 168, 34, 73, 253, 247, 175, 248, 157, 248, 156, 48, ++ 35, 177, 55, 168, 32, 73, 39, 170, 253, 247, 167, 248, 22, 155, 10, ++ 43, 12, 216, 0, 32, 29, 73, 183, 243, 120, 247, 56, 185, 19, 153, 41, ++ 185, 55, 168, 26, 73, 19, 154, 255, 35, 253, 247, 151, 248, 56, 154, ++ 0, 35, 2, 248, 1, 59, 68, 155, 26, 152, 0, 147, 18, 153, 24, 155, 56, ++ 146, 253, 247, 107, 248, 4, 70, 18, 152, 190, 247, 4, 253, 1, 224, 111, ++ 240, 1, 4, 32, 70, 59, 176, 189, 232, 240, 143, 1, 33, 19, 145, 185, ++ 231, 0, 191, 38, 144, 5, 0, 99, 144, 5, 0, 179, 146, 5, 0, 199, 146, ++ 5, 0, 219, 146, 5, 0, 239, 146, 5, 0, 3, 147, 5, 0, 144, 145, 5, 0, ++ 129, 147, 5, 0, 88, 141, 5, 0, 170, 140, 5, 0, 0, 139, 5, 0, 45, 233, ++ 240, 79, 141, 176, 5, 146, 5, 70, 138, 70, 6, 168, 0, 33, 20, 34, 152, ++ 70, 11, 145, 183, 243, 183, 240, 89, 75, 28, 120, 0, 44, 64, 240, 163, ++ 128, 107, 105, 35, 43, 12, 221, 28, 34, 40, 70, 33, 70, 35, 70, 0, 148, ++ 193, 243, 74, 246, 0, 40, 6, 218, 1, 38, 2, 39, 177, 70, 5, 224, 4, ++ 39, 1, 38, 1, 224, 12, 39, 3, 38, 161, 70, 40, 70, 193, 243, 205, 245, ++ 1, 40, 131, 70, 2, 208, 2, 40, 19, 209, 5, 224, 40, 70, 81, 70, 183, ++ 243, 55, 240, 64, 0, 11, 224, 40, 70, 252, 247, 159, 255, 4, 70, 56, ++ 177, 252, 247, 145, 255, 194, 5, 3, 213, 32, 70, 252, 247, 145, 255, ++ 11, 144, 11, 152, 0, 40, 78, 208, 190, 247, 149, 252, 4, 70, 0, 40, ++ 110, 208, 187, 241, 1, 15, 3, 208, 187, 241, 2, 15, 27, 209, 11, 224, ++ 11, 155, 0, 33, 1, 147, 2, 144, 5, 154, 40, 70, 83, 70, 0, 145, 3, 145, ++ 183, 243, 12, 240, 12, 224, 11, 154, 12, 171, 82, 8, 67, 248, 4, 45, ++ 40, 70, 1, 33, 34, 70, 252, 247, 164, 255, 11, 155, 91, 0, 11, 147, ++ 0, 40, 64, 209, 34, 136, 79, 246, 253, 115, 1, 58, 146, 178, 154, 66, ++ 3, 217, 32, 70, 190, 247, 105, 252, 28, 224, 185, 241, 0, 15, 3, 208, ++ 4, 235, 71, 7, 6, 151, 25, 224, 227, 25, 98, 136, 6, 147, 163, 136, ++ 167, 245, 128, 87, 7, 235, 18, 34, 27, 6, 2, 235, 19, 67, 227, 24, 7, ++ 147, 227, 136, 219, 25, 227, 24, 8, 147, 35, 137, 223, 25, 231, 25, ++ 9, 151, 3, 224, 21, 75, 0, 36, 6, 147, 1, 38, 22, 154, 80, 70, 0, 146, ++ 6, 169, 50, 70, 67, 70, 253, 247, 20, 248, 80, 185, 22, 155, 40, 70, ++ 26, 104, 216, 248, 0, 16, 1, 240, 12, 253, 216, 248, 0, 32, 11, 75, ++ 26, 96, 20, 177, 32, 70, 190, 247, 47, 252, 6, 74, 1, 35, 19, 112, 22, ++ 155, 0, 32, 200, 248, 0, 0, 24, 96, 1, 224, 111, 240, 26, 0, 13, 176, ++ 189, 232, 240, 143, 157, 110, 4, 0, 196, 142, 5, 0, 236, 150, 5, 0, ++ 48, 181, 25, 70, 3, 155, 4, 156, 67, 177, 76, 177, 0, 37, 29, 96, 37, ++ 96, 3, 148, 189, 232, 48, 64, 255, 247, 44, 191, 24, 70, 48, 189, 32, ++ 70, 48, 189, 1, 75, 0, 34, 26, 112, 112, 71, 157, 110, 4, 0, 112, 181, ++ 12, 78, 13, 70, 48, 104, 128, 185, 11, 73, 188, 247, 224, 250, 1, 36, ++ 4, 224, 32, 70, 0, 33, 188, 247, 218, 250, 1, 52, 51, 104, 156, 66, ++ 247, 217, 3, 75, 40, 70, 29, 96, 112, 189, 79, 240, 255, 48, 112, 189, ++ 0, 191, 208, 7, 0, 0, 173, 222, 173, 222, 6, 75, 26, 104, 25, 70, 50, ++ 177, 1, 35, 0, 224, 1, 51, 147, 66, 252, 217, 0, 35, 11, 96, 0, 32, ++ 112, 71, 0, 191, 208, 7, 0, 0, 45, 233, 240, 71, 12, 70, 22, 104, 130, ++ 70, 21, 70, 8, 70, 132, 34, 0, 33, 152, 70, 157, 248, 36, 112, 182, ++ 243, 170, 247, 32, 70, 183, 243, 211, 245, 192, 178, 0, 40, 50, 208, ++ 1, 35, 35, 112, 157, 248, 32, 48, 160, 112, 0, 51, 24, 191, 1, 35, 227, ++ 112, 40, 35, 40, 46, 180, 191, 177, 70, 79, 240, 40, 9, 164, 248, 14, ++ 128, 103, 112, 163, 129, 0, 38, 21, 224, 80, 70, 65, 70, 58, 70, 187, ++ 243, 162, 245, 48, 185, 99, 104, 0, 43, 12, 191, 111, 240, 26, 0, 0, ++ 32, 11, 224, 163, 120, 1, 54, 195, 112, 99, 104, 67, 97, 35, 137, 96, ++ 96, 1, 51, 35, 129, 78, 69, 231, 219, 0, 32, 35, 137, 99, 129, 43, 96, ++ 189, 232, 240, 135, 79, 240, 255, 48, 189, 232, 240, 135, 248, 181, ++ 6, 70, 12, 70, 0, 37, 11, 224, 123, 105, 48, 70, 99, 96, 0, 35, 123, ++ 97, 251, 112, 57, 70, 226, 120, 190, 247, 174, 251, 1, 53, 173, 178, ++ 103, 104, 0, 47, 240, 209, 35, 137, 32, 70, 91, 27, 35, 129, 99, 137, ++ 93, 27, 101, 129, 183, 243, 108, 245, 167, 112, 39, 112, 56, 70, 248, ++ 189, 16, 181, 195, 124, 3, 43, 8, 208, 156, 29, 0, 235, 196, 4, 1, 51, ++ 97, 96, 162, 96, 195, 116, 0, 32, 16, 189, 79, 240, 255, 48, 16, 189, ++ 45, 233, 248, 67, 17, 240, 31, 6, 24, 191, 1, 38, 6, 235, 81, 23, 7, ++ 241, 7, 9, 79, 234, 137, 9, 72, 70, 13, 70, 1, 240, 31, 8, 190, 247, ++ 68, 251, 4, 70, 0, 40, 59, 208, 0, 33, 74, 70, 191, 178, 182, 243, 34, ++ 247, 103, 128, 165, 128, 229, 128, 164, 96, 33, 70, 34, 70, 0, 35, 3, ++ 224, 79, 240, 255, 48, 144, 97, 1, 51, 4, 50, 187, 66, 248, 211, 86, ++ 177, 79, 240, 255, 50, 2, 250, 8, 248, 123, 29, 4, 235, 131, 3, 90, ++ 104, 130, 234, 8, 2, 90, 96, 23, 240, 31, 3, 24, 191, 1, 35, 7, 240, ++ 31, 0, 3, 235, 87, 23, 39, 128, 0, 34, 3, 224, 79, 240, 255, 53, 141, ++ 96, 1, 50, 4, 49, 186, 66, 248, 211, 67, 177, 79, 240, 255, 51, 131, ++ 64, 1, 55, 4, 235, 135, 7, 122, 104, 83, 64, 123, 96, 32, 70, 189, 232, ++ 248, 131, 8, 70, 190, 247, 2, 187, 67, 107, 35, 177, 79, 244, 127, 98, ++ 154, 96, 67, 107, 5, 224, 131, 107, 75, 177, 79, 244, 127, 98, 154, ++ 96, 131, 107, 152, 104, 208, 241, 1, 0, 56, 191, 0, 32, 112, 71, 1, ++ 32, 112, 71, 3, 70, 0, 32, 1, 224, 1, 48, 192, 178, 91, 8, 251, 209, ++ 112, 71, 11, 104, 67, 244, 64, 51, 11, 96, 8, 104, 11, 104, 0, 244, ++ 64, 48, 35, 244, 64, 51, 11, 96, 160, 245, 64, 49, 72, 66, 64, 235, ++ 1, 0, 112, 71, 8, 181, 65, 107, 9, 185, 129, 107, 33, 177, 128, 106, ++ 255, 247, 231, 255, 1, 32, 8, 189, 8, 70, 8, 189, 45, 233, 240, 71, ++ 221, 248, 32, 128, 31, 136, 9, 157, 16, 70, 137, 70, 20, 70, 30, 70, ++ 57, 70, 66, 70, 43, 70, 187, 243, 28, 242, 130, 70, 232, 177, 1, 35, ++ 19, 250, 7, 247, 43, 104, 1, 59, 219, 25, 179, 251, 247, 243, 95, 67, ++ 99, 30, 219, 25, 95, 64, 23, 234, 9, 15, 14, 208, 32, 70, 255, 247, ++ 184, 255, 48, 128, 80, 70, 187, 243, 14, 242, 49, 136, 32, 70, 66, 70, ++ 43, 70, 189, 232, 240, 71, 187, 243, 252, 177, 80, 70, 189, 232, 240, ++ 135, 112, 181, 0, 35, 1, 41, 12, 191, 176, 248, 70, 32, 176, 248, 108, ++ 32, 134, 176, 4, 147, 176, 248, 68, 48, 18, 1, 1, 41, 4, 70, 173, 248, ++ 22, 48, 13, 70, 128, 106, 65, 246, 255, 115, 41, 209, 4, 174, 212, 248, ++ 196, 16, 0, 150, 4, 241, 92, 6, 1, 150, 153, 66, 20, 191, 79, 244, 128, ++ 49, 79, 244, 0, 81, 4, 241, 80, 6, 13, 241, 22, 3, 2, 150, 255, 247, ++ 164, 255, 0, 40, 64, 208, 189, 248, 22, 48, 226, 109, 21, 250, 3, 243, ++ 81, 30, 201, 24, 177, 251, 243, 241, 75, 67, 163, 101, 155, 26, 155, ++ 178, 192, 24, 164, 248, 96, 48, 4, 155, 224, 99, 99, 102, 43, 224, 4, ++ 173, 212, 248, 204, 16, 0, 149, 4, 241, 132, 5, 1, 149, 153, 66, 20, ++ 191, 79, 244, 128, 49, 79, 244, 0, 81, 4, 241, 120, 5, 13, 241, 22, ++ 3, 2, 149, 255, 247, 122, 255, 184, 177, 189, 248, 22, 48, 1, 37, 21, ++ 250, 3, 243, 212, 248, 132, 32, 81, 30, 201, 24, 177, 251, 243, 241, ++ 75, 67, 196, 248, 128, 48, 155, 26, 155, 178, 192, 24, 164, 248, 136, ++ 48, 4, 155, 32, 100, 196, 248, 140, 48, 40, 70, 6, 176, 112, 189, 255, ++ 247, 143, 191, 45, 233, 247, 79, 141, 232, 3, 0, 14, 174, 224, 32, 20, ++ 70, 154, 70, 13, 159, 150, 232, 64, 10, 221, 248, 76, 128, 190, 247, ++ 19, 250, 5, 70, 0, 40, 0, 240, 121, 129, 0, 33, 224, 34, 182, 243, 241, ++ 245, 154, 75, 0, 33, 184, 241, 0, 15, 8, 191, 152, 70, 10, 70, 197, ++ 248, 28, 128, 32, 70, 193, 243, 121, 243, 12, 155, 192, 243, 0, 48, ++ 171, 99, 147, 75, 3, 33, 43, 96, 0, 34, 133, 248, 48, 0, 197, 248, 52, ++ 160, 40, 70, 188, 247, 8, 254, 8, 34, 5, 241, 32, 0, 1, 153, 182, 243, ++ 176, 246, 0, 35, 133, 248, 39, 48, 0, 155, 236, 98, 171, 98, 187, 241, ++ 255, 63, 20, 191, 91, 70, 204, 35, 185, 241, 204, 15, 136, 191, 195, ++ 235, 9, 9, 197, 248, 152, 48, 189, 248, 68, 48, 165, 248, 70, 112, 197, ++ 248, 156, 48, 157, 248, 72, 48, 165, 248, 108, 96, 197, 248, 160, 48, ++ 12, 155, 165, 248, 148, 144, 0, 43, 69, 208, 170, 107, 19, 104, 217, ++ 7, 4, 213, 35, 240, 1, 3, 19, 96, 170, 107, 19, 96, 171, 107, 79, 240, ++ 255, 50, 154, 96, 32, 70, 193, 243, 51, 243, 64, 246, 60, 3, 152, 66, ++ 18, 209, 232, 106, 193, 243, 60, 243, 5, 40, 9, 208, 232, 106, 193, ++ 243, 55, 243, 8, 40, 4, 208, 232, 106, 193, 243, 50, 243, 12, 40, 3, ++ 209, 171, 107, 79, 240, 255, 50, 154, 96, 171, 107, 154, 104, 18, 5, ++ 18, 13, 26, 177, 90, 104, 66, 240, 15, 2, 1, 224, 65, 246, 255, 114, ++ 197, 248, 204, 32, 26, 104, 2, 244, 224, 18, 146, 12, 133, 248, 181, ++ 32, 26, 104, 2, 244, 96, 2, 82, 13, 133, 248, 186, 32, 27, 104, 3, 240, ++ 64, 115, 27, 14, 133, 248, 187, 48, 186, 241, 0, 15, 77, 208, 106, 107, ++ 19, 104, 216, 7, 4, 213, 35, 240, 1, 3, 19, 96, 106, 107, 19, 96, 107, ++ 107, 79, 240, 255, 50, 154, 96, 232, 106, 193, 243, 234, 242, 64, 246, ++ 60, 3, 152, 66, 18, 209, 232, 106, 193, 243, 243, 242, 5, 40, 9, 208, ++ 232, 106, 193, 243, 238, 242, 8, 40, 4, 208, 232, 106, 193, 243, 233, ++ 242, 12, 40, 3, 209, 107, 107, 79, 240, 255, 50, 154, 96, 107, 107, ++ 154, 104, 18, 5, 18, 13, 26, 177, 90, 104, 66, 240, 15, 2, 1, 224, 65, ++ 246, 255, 114, 197, 248, 196, 32, 197, 248, 200, 32, 26, 104, 2, 244, ++ 224, 18, 146, 12, 133, 248, 182, 32, 26, 104, 2, 244, 224, 114, 146, ++ 9, 133, 248, 183, 32, 26, 104, 2, 244, 96, 2, 82, 13, 133, 248, 184, ++ 32, 27, 104, 3, 240, 64, 115, 27, 14, 133, 248, 185, 48, 98, 104, 0, ++ 35, 1, 42, 197, 248, 164, 48, 197, 248, 172, 48, 24, 209, 162, 104, ++ 178, 245, 2, 111, 3, 208, 64, 246, 60, 1, 138, 66, 2, 209, 79, 240, ++ 0, 67, 3, 224, 79, 240, 128, 66, 197, 248, 164, 32, 197, 248, 168, 48, ++ 213, 248, 164, 48, 197, 248, 172, 48, 213, 248, 168, 48, 197, 248, 176, ++ 48, 32, 70, 193, 243, 136, 242, 64, 246, 41, 3, 152, 66, 8, 209, 32, ++ 70, 193, 243, 145, 242, 32, 177, 32, 70, 193, 243, 141, 242, 2, 40, ++ 15, 217, 32, 70, 193, 243, 120, 242, 64, 246, 52, 3, 152, 66, 12, 209, ++ 32, 70, 193, 243, 129, 242, 32, 177, 32, 70, 193, 243, 125, 242, 1, ++ 40, 3, 209, 0, 35, 133, 248, 49, 48, 4, 224, 40, 70, 255, 247, 23, 254, ++ 133, 248, 49, 0, 40, 70, 255, 247, 228, 253, 133, 248, 180, 0, 104, ++ 177, 13, 35, 255, 47, 165, 248, 68, 48, 12, 216, 255, 46, 9, 216, 12, ++ 35, 5, 224, 0, 191, 0, 111, 4, 0, 20, 46, 4, 0, 4, 35, 165, 248, 68, ++ 48, 79, 177, 188, 0, 32, 70, 190, 247, 202, 248, 232, 100, 104, 179, ++ 0, 33, 34, 70, 182, 243, 170, 244, 78, 177, 180, 0, 32, 70, 190, 247, ++ 191, 248, 104, 103, 16, 179, 0, 33, 34, 70, 182, 243, 159, 244, 39, ++ 177, 40, 70, 1, 33, 255, 247, 144, 254, 192, 177, 38, 177, 40, 70, 2, ++ 33, 255, 247, 138, 254, 144, 177, 213, 248, 164, 48, 91, 177, 149, 248, ++ 49, 48, 67, 185, 171, 109, 179, 241, 128, 79, 8, 216, 213, 248, 128, ++ 48, 179, 241, 128, 79, 3, 216, 1, 35, 133, 248, 221, 48, 3, 224, 40, ++ 70, 185, 243, 175, 247, 0, 37, 40, 70, 189, 232, 254, 143, 0, 191, 16, ++ 181, 4, 70, 193, 243, 84, 244, 0, 33, 32, 70, 10, 70, 193, 243, 3, 242, ++ 192, 4, 7, 213, 32, 70, 193, 243, 126, 241, 0, 40, 12, 191, 32, 32, ++ 64, 32, 16, 189, 32, 32, 16, 189, 45, 233, 240, 71, 4, 70, 38, 106, ++ 9, 169, 4, 46, 102, 106, 157, 248, 32, 0, 204, 191, 6, 244, 120, 22, ++ 6, 244, 240, 22, 145, 232, 34, 2, 118, 12, 79, 240, 0, 8, 75, 224, 49, ++ 248, 40, 160, 31, 250, 131, 252, 226, 69, 1, 235, 136, 7, 3, 209, 151, ++ 248, 2, 192, 132, 69, 4, 208, 8, 241, 1, 8, 95, 250, 136, 248, 58, 224, ++ 0, 42, 53, 208, 6, 251, 8, 248, 0, 37, 46, 224, 99, 105, 32, 70, 34, ++ 43, 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 193, 243, ++ 128, 242, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 204, 98, 193, 243, ++ 200, 241, 5, 96, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 91, 6, ++ 7, 213, 64, 246, 39, 1, 0, 34, 193, 243, 107, 242, 1, 70, 32, 70, 0, ++ 224, 0, 33, 64, 242, 100, 98, 193, 243, 179, 241, 9, 235, 136, 3, 83, ++ 248, 37, 48, 1, 53, 3, 96, 235, 178, 179, 66, 205, 211, 248, 120, 189, ++ 232, 240, 135, 168, 69, 177, 211, 0, 32, 189, 232, 240, 135, 45, 233, ++ 248, 67, 4, 70, 30, 70, 0, 43, 0, 240, 180, 128, 67, 106, 2, 235, 6, ++ 21, 3, 244, 248, 89, 79, 234, 25, 41, 85, 248, 4, 60, 1, 62, 11, 185, ++ 0, 39, 159, 224, 32, 70, 152, 71, 0, 40, 0, 240, 158, 128, 247, 231, ++ 1, 34, 186, 64, 85, 248, 16, 60, 26, 66, 0, 240, 146, 128, 99, 105, ++ 32, 70, 34, 43, 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, ++ 34, 193, 243, 37, 242, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 196, 98, ++ 193, 243, 109, 241, 7, 96, 21, 249, 12, 44, 34, 177, 1, 42, 25, 208, ++ 1, 50, 117, 209, 68, 224, 99, 105, 32, 70, 34, 43, 9, 221, 227, 105, ++ 91, 6, 6, 213, 64, 246, 39, 1, 193, 243, 9, 242, 1, 70, 32, 70, 0, 224, ++ 0, 33, 64, 242, 36, 98, 193, 243, 81, 241, 85, 248, 8, 60, 3, 96, 93, ++ 224, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 89, 6, 7, 213, 64, ++ 246, 39, 1, 0, 34, 193, 243, 241, 241, 1, 70, 32, 70, 0, 224, 0, 33, ++ 64, 242, 36, 98, 193, 243, 57, 241, 99, 105, 128, 70, 34, 43, 32, 70, ++ 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 193, 243, 220, ++ 241, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 36, 98, 193, 243, 36, 241, ++ 85, 248, 8, 60, 2, 104, 19, 67, 45, 224, 99, 105, 32, 70, 34, 43, 10, ++ 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, 193, 243, 195, ++ 241, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 36, 98, 193, 243, 11, 241, ++ 99, 105, 128, 70, 34, 43, 32, 70, 10, 221, 227, 105, 89, 6, 7, 213, ++ 64, 246, 39, 1, 0, 34, 193, 243, 174, 241, 1, 70, 32, 70, 0, 224, 0, ++ 33, 64, 242, 36, 98, 193, 243, 246, 240, 85, 248, 8, 44, 3, 104, 35, ++ 234, 2, 3, 200, 248, 0, 48, 1, 55, 79, 69, 127, 244, 99, 175, 16, 61, ++ 0, 46, 127, 244, 83, 175, 189, 232, 248, 131, 0, 0, 112, 181, 157, 73, ++ 4, 70, 0, 32, 183, 243, 142, 241, 0, 40, 0, 240, 49, 129, 0, 32, 152, ++ 73, 183, 243, 135, 241, 151, 73, 5, 70, 0, 32, 183, 243, 130, 241, 148, ++ 73, 6, 70, 0, 32, 183, 243, 125, 241, 21, 240, 0, 101, 0, 240, 172, ++ 128, 79, 244, 0, 18, 0, 33, 19, 70, 32, 70, 189, 247, 11, 249, 2, 34, ++ 6, 33, 19, 70, 32, 70, 193, 243, 130, 241, 99, 105, 32, 70, 34, 43, ++ 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 193, 243, 96, ++ 241, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 193, 98, 193, 243, 168, ++ 240, 6, 104, 0, 37, 6, 244, 128, 118, 27, 224, 79, 244, 122, 112, 186, ++ 243, 105, 246, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 91, 6, 7, ++ 213, 64, 246, 39, 1, 50, 70, 193, 243, 67, 241, 1, 70, 32, 70, 0, 224, ++ 0, 33, 79, 244, 193, 98, 193, 243, 139, 240, 6, 104, 1, 53, 6, 244, ++ 128, 118, 30, 185, 181, 245, 122, 127, 223, 209, 112, 189, 181, 245, ++ 122, 127, 0, 240, 212, 128, 79, 244, 122, 112, 186, 243, 68, 246, 8, ++ 34, 6, 33, 19, 70, 32, 70, 193, 243, 58, 241, 0, 35, 6, 33, 4, 34, 32, ++ 70, 193, 243, 52, 241, 79, 244, 122, 112, 186, 243, 52, 246, 99, 105, ++ 32, 70, 34, 43, 10, 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 0, ++ 34, 193, 243, 14, 241, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 192, 98, ++ 193, 243, 86, 240, 5, 104, 0, 38, 5, 240, 1, 5, 27, 224, 79, 244, 122, ++ 112, 186, 243, 23, 246, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, ++ 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 193, 243, 241, 240, 1, 70, 32, ++ 70, 0, 224, 0, 33, 79, 244, 192, 98, 193, 243, 57, 240, 5, 104, 1, 54, ++ 5, 240, 1, 5, 29, 177, 182, 245, 122, 127, 223, 209, 2, 224, 182, 245, ++ 122, 127, 3, 209, 32, 70, 6, 33, 8, 34, 121, 224, 41, 70, 79, 244, 128, ++ 18, 43, 70, 32, 70, 189, 247, 107, 248, 32, 70, 6, 33, 1, 34, 43, 70, ++ 110, 224, 115, 1, 112, 213, 79, 244, 128, 18, 19, 70, 41, 70, 32, 70, ++ 189, 247, 93, 248, 1, 34, 6, 33, 19, 70, 32, 70, 193, 243, 212, 240, ++ 79, 244, 122, 112, 186, 243, 212, 245, 4, 34, 6, 33, 19, 70, 32, 70, ++ 193, 243, 202, 240, 6, 33, 8, 34, 43, 70, 32, 70, 193, 243, 196, 240, ++ 79, 244, 122, 112, 186, 243, 196, 245, 99, 105, 32, 70, 34, 43, 10, ++ 221, 227, 105, 94, 6, 7, 213, 64, 246, 39, 1, 42, 70, 193, 243, 158, ++ 240, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 192, 98, 192, 243, 230, ++ 247, 6, 104, 0, 37, 6, 240, 1, 6, 27, 224, 79, 244, 122, 112, 186, 243, ++ 167, 245, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 89, 6, 7, 213, ++ 64, 246, 39, 1, 50, 70, 193, 243, 129, 240, 1, 70, 32, 70, 0, 224, 0, ++ 33, 79, 244, 192, 98, 192, 243, 201, 247, 6, 104, 1, 53, 6, 240, 1, ++ 6, 30, 185, 181, 245, 122, 127, 223, 209, 2, 224, 181, 245, 122, 127, ++ 3, 209, 32, 70, 6, 33, 4, 34, 9, 224, 0, 33, 79, 244, 0, 18, 11, 70, ++ 32, 70, 188, 247, 251, 255, 32, 70, 6, 33, 2, 34, 0, 35, 189, 232, 112, ++ 64, 193, 243, 112, 176, 112, 189, 0, 191, 248, 48, 4, 0, 70, 242, 144, ++ 83, 153, 66, 16, 181, 4, 70, 9, 208, 73, 242, 24, 35, 153, 66, 7, 208, ++ 177, 245, 150, 79, 12, 191, 31, 35, 0, 35, 2, 224, 42, 35, 0, 224, 60, ++ 35, 5, 33, 255, 34, 32, 70, 189, 247, 67, 248, 79, 244, 0, 2, 6, 33, ++ 19, 70, 32, 70, 189, 247, 6, 248, 30, 32, 186, 243, 78, 245, 32, 70, ++ 6, 33, 79, 244, 0, 2, 0, 35, 189, 232, 16, 64, 188, 247, 250, 191, 0, ++ 0, 240, 181, 3, 106, 70, 106, 4, 43, 204, 191, 6, 244, 120, 22, 6, 244, ++ 240, 22, 133, 176, 4, 70, 118, 12, 0, 37, 59, 224, 16, 33, 104, 70, ++ 31, 74, 43, 70, 182, 243, 40, 242, 0, 32, 105, 70, 183, 243, 54, 240, ++ 0, 40, 46, 208, 0, 33, 10, 70, 187, 247, 6, 254, 99, 105, 7, 70, 34, ++ 43, 32, 70, 10, 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 0, 34, ++ 192, 243, 255, 247, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 204, 98, ++ 192, 243, 71, 247, 5, 96, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, ++ 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 234, 247, 1, 70, 32, ++ 70, 0, 224, 0, 33, 64, 242, 100, 98, 192, 243, 50, 247, 7, 96, 1, 53, ++ 235, 178, 179, 66, 192, 211, 5, 176, 240, 189, 0, 191, 57, 153, 5, 0, ++ 240, 181, 3, 106, 133, 176, 4, 43, 4, 70, 70, 106, 3, 221, 6, 240, 248, ++ 102, 182, 13, 2, 224, 6, 240, 240, 118, 118, 13, 0, 37, 59, 224, 16, ++ 33, 104, 70, 31, 74, 43, 70, 182, 243, 212, 241, 0, 32, 105, 70, 182, ++ 243, 226, 247, 0, 40, 46, 208, 0, 33, 10, 70, 187, 247, 178, 253, 99, ++ 105, 7, 70, 34, 43, 32, 70, 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, ++ 39, 1, 0, 34, 192, 243, 171, 247, 1, 70, 32, 70, 0, 224, 0, 33, 79, ++ 244, 203, 98, 192, 243, 243, 246, 5, 96, 99, 105, 32, 70, 34, 43, 10, ++ 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 150, ++ 247, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 92, 98, 192, 243, 222, 246, ++ 7, 96, 1, 53, 235, 178, 179, 66, 192, 211, 5, 176, 240, 189, 0, 191, ++ 112, 156, 5, 0, 240, 181, 3, 106, 133, 176, 4, 43, 4, 70, 70, 106, 1, ++ 221, 246, 14, 2, 224, 6, 240, 240, 86, 118, 14, 0, 37, 59, 224, 16, ++ 33, 104, 70, 30, 74, 43, 70, 182, 243, 130, 241, 0, 32, 105, 70, 182, ++ 243, 144, 247, 0, 40, 46, 208, 0, 33, 10, 70, 187, 247, 96, 253, 99, ++ 105, 7, 70, 34, 43, 32, 70, 10, 221, 227, 105, 91, 6, 7, 213, 64, 246, ++ 39, 1, 0, 34, 192, 243, 89, 247, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, ++ 202, 98, 192, 243, 161, 246, 5, 96, 99, 105, 32, 70, 34, 43, 10, 221, ++ 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 68, 247, 1, ++ 70, 32, 70, 0, 224, 0, 33, 64, 242, 84, 98, 192, 243, 140, 246, 7, 96, ++ 1, 53, 181, 66, 193, 209, 5, 176, 240, 189, 127, 156, 5, 0, 0, 72, 112, ++ 71, 192, 173, 58, 2, 45, 233, 240, 67, 4, 70, 15, 70, 133, 176, 0, 32, ++ 144, 73, 21, 70, 30, 70, 182, 243, 37, 247, 96, 185, 32, 70, 57, 70, ++ 21, 177, 255, 247, 235, 255, 7, 224, 255, 247, 232, 255, 79, 244, 122, ++ 117, 176, 251, 245, 245, 0, 224, 5, 70, 0, 32, 135, 73, 182, 243, 18, ++ 247, 0, 240, 15, 0, 1, 40, 8, 208, 2, 40, 9, 208, 131, 75, 132, 74, ++ 3, 40, 20, 191, 145, 70, 153, 70, 4, 224, 223, 248, 20, 146, 1, 224, ++ 223, 248, 16, 146, 41, 70, 32, 70, 255, 247, 166, 254, 32, 70, 192, ++ 243, 67, 246, 0, 33, 128, 70, 32, 70, 193, 243, 140, 241, 121, 75, 2, ++ 70, 0, 46, 75, 209, 1, 147, 3, 35, 2, 147, 57, 70, 32, 70, 50, 70, 43, ++ 70, 0, 150, 205, 248, 12, 144, 255, 247, 45, 252, 7, 70, 0, 40, 55, ++ 208, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 91, 6, 7, 213, 64, ++ 246, 39, 1, 50, 70, 192, 243, 213, 246, 1, 70, 32, 70, 0, 224, 0, 33, ++ 79, 244, 192, 98, 192, 243, 29, 246, 2, 104, 191, 0, 79, 246, 131, 115, ++ 19, 64, 7, 240, 124, 2, 5, 241, 127, 7, 255, 9, 1, 63, 66, 234, 7, 71, ++ 31, 67, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 89, 6, 7, 213, 64, ++ 246, 39, 1, 0, 34, 192, 243, 179, 246, 1, 70, 32, 70, 0, 224, 0, 33, ++ 79, 244, 192, 98, 192, 243, 251, 245, 7, 96, 150, 224, 41, 70, 84, 72, ++ 182, 243, 119, 240, 146, 224, 0, 33, 141, 232, 10, 0, 3, 35, 2, 147, ++ 32, 70, 57, 70, 43, 70, 205, 248, 12, 144, 255, 247, 225, 251, 0, 45, ++ 0, 240, 131, 128, 32, 70, 188, 247, 62, 252, 6, 70, 6, 224, 171, 66, ++ 3, 209, 99, 105, 34, 43, 7, 220, 18, 224, 12, 54, 0, 46, 116, 208, 51, ++ 136, 0, 43, 243, 209, 112, 224, 227, 105, 90, 6, 8, 213, 64, 246, 39, ++ 1, 32, 70, 0, 34, 192, 243, 122, 246, 1, 70, 32, 70, 1, 224, 32, 70, ++ 0, 33, 79, 244, 192, 98, 192, 243, 193, 245, 2, 104, 179, 120, 2, 240, ++ 124, 2, 179, 235, 146, 15, 87, 208, 53, 121, 243, 120, 45, 6, 27, 5, ++ 5, 240, 112, 101, 3, 244, 112, 3, 0, 33, 79, 240, 127, 98, 43, 67, 32, ++ 70, 188, 247, 96, 254, 115, 121, 2, 33, 27, 5, 45, 74, 67, 244, 0, 51, ++ 32, 70, 188, 247, 87, 254, 179, 104, 111, 240, 127, 66, 3, 33, 19, 64, ++ 32, 70, 188, 247, 79, 254, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, ++ 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 62, 246, 1, 70, 32, ++ 70, 0, 224, 0, 33, 79, 244, 192, 98, 192, 243, 134, 245, 2, 104, 79, ++ 246, 131, 115, 53, 136, 19, 64, 178, 120, 127, 53, 237, 17, 146, 0, ++ 1, 61, 2, 240, 124, 2, 66, 234, 5, 69, 29, 67, 99, 105, 32, 70, 34, ++ 43, 10, 221, 227, 105, 94, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, ++ 27, 246, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 192, 98, 192, 243, 99, ++ 245, 5, 96, 1, 38, 32, 70, 65, 70, 193, 243, 165, 240, 48, 70, 5, 176, ++ 189, 232, 240, 131, 0, 191, 80, 153, 5, 0, 4, 49, 4, 0, 28, 47, 4, 0, ++ 156, 47, 4, 0, 106, 154, 5, 0, 7, 153, 5, 0, 0, 0, 254, 31, 16, 49, ++ 4, 0, 136, 49, 4, 0, 45, 233, 240, 67, 153, 70, 139, 176, 0, 35, 7, ++ 147, 8, 147, 9, 147, 3, 106, 71, 106, 4, 43, 204, 191, 7, 244, 120, ++ 23, 7, 244, 240, 23, 4, 70, 13, 70, 144, 70, 127, 12, 0, 38, 12, 224, ++ 16, 33, 3, 168, 51, 74, 51, 70, 181, 243, 236, 247, 0, 32, 3, 169, 182, ++ 243, 250, 245, 32, 185, 1, 54, 246, 178, 190, 66, 240, 211, 78, 224, ++ 8, 171, 0, 147, 9, 171, 1, 147, 32, 70, 41, 70, 66, 70, 7, 171, 188, ++ 247, 138, 255, 1, 35, 41, 70, 74, 70, 32, 70, 255, 247, 144, 254, 32, ++ 70, 41, 70, 255, 247, 146, 253, 35, 106, 1, 43, 44, 221, 99, 105, 32, ++ 70, 34, 43, 10, 221, 227, 105, 94, 6, 7, 213, 64, 246, 39, 1, 0, 34, ++ 192, 243, 173, 245, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 192, 98, ++ 192, 243, 245, 244, 99, 105, 6, 70, 34, 43, 32, 70, 10, 221, 227, 105, ++ 89, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 152, 245, 1, 70, 32, ++ 70, 0, 224, 0, 33, 79, 244, 192, 98, 192, 243, 224, 244, 3, 104, 67, ++ 244, 128, 99, 51, 96, 8, 155, 32, 70, 0, 147, 9, 155, 41, 70, 1, 147, ++ 66, 70, 7, 155, 188, 247, 158, 252, 7, 224, 32, 70, 41, 70, 74, 70, ++ 0, 35, 255, 247, 75, 254, 0, 40, 168, 209, 11, 176, 189, 232, 240, 131, ++ 57, 153, 5, 0, 45, 233, 240, 79, 0, 37, 135, 176, 4, 70, 14, 70, 4, ++ 149, 5, 149, 192, 243, 180, 244, 41, 70, 131, 70, 32, 70, 192, 243, ++ 253, 247, 161, 73, 130, 70, 40, 70, 182, 243, 132, 245, 72, 177, 1, ++ 35, 132, 248, 96, 51, 41, 70, 42, 70, 187, 247, 82, 251, 196, 248, 92, ++ 3, 1, 224, 132, 248, 96, 3, 0, 32, 152, 73, 182, 243, 115, 245, 72, ++ 177, 1, 35, 0, 33, 132, 248, 104, 51, 10, 70, 187, 247, 65, 251, 196, ++ 248, 100, 3, 1, 224, 132, 248, 104, 3, 32, 70, 192, 243, 245, 243, 144, ++ 75, 103, 106, 152, 66, 143, 75, 148, 191, 32, 37, 33, 37, 163, 241, ++ 8, 8, 152, 191, 152, 70, 7, 244, 248, 87, 63, 10, 8, 235, 197, 8, 99, ++ 105, 32, 70, 34, 43, 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, ++ 1, 0, 34, 192, 243, 35, 245, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, ++ 196, 98, 192, 243, 107, 244, 24, 248, 8, 60, 1, 61, 3, 96, 99, 105, ++ 32, 70, 34, 43, 10, 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, ++ 34, 192, 243, 11, 245, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 197, 98, ++ 192, 243, 83, 244, 88, 248, 4, 60, 168, 241, 8, 8, 3, 96, 0, 45, 204, ++ 209, 71, 224, 8, 33, 2, 168, 111, 74, 43, 70, 181, 243, 7, 247, 0, 32, ++ 2, 169, 182, 243, 21, 245, 0, 40, 58, 208, 0, 33, 10, 70, 187, 247, ++ 229, 250, 35, 106, 128, 70, 12, 43, 7, 221, 176, 245, 128, 63, 4, 210, ++ 195, 178, 79, 234, 16, 40, 67, 234, 8, 72, 99, 105, 32, 70, 34, 43, ++ 10, 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 211, ++ 244, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 196, 98, 192, 243, 27, 244, ++ 5, 96, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 90, 6, 7, 213, 64, ++ 246, 39, 1, 0, 34, 192, 243, 190, 244, 1, 70, 32, 70, 0, 224, 0, 33, ++ 79, 244, 197, 98, 192, 243, 6, 244, 192, 248, 0, 128, 1, 53, 189, 66, ++ 181, 209, 32, 70, 49, 70, 75, 74, 31, 35, 255, 247, 89, 250, 0, 37, ++ 62, 224, 8, 33, 72, 74, 43, 70, 2, 168, 181, 243, 181, 246, 0, 32, 2, ++ 169, 182, 243, 195, 244, 129, 70, 0, 40, 48, 208, 99, 105, 32, 70, 34, ++ 43, 10, 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, ++ 144, 244, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 196, 98, 192, 243, ++ 216, 243, 5, 96, 99, 105, 32, 70, 34, 43, 10, 221, 227, 105, 89, 6, ++ 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 123, 244, 1, 70, 32, 70, 0, ++ 224, 0, 33, 64, 242, 36, 98, 192, 243, 195, 243, 0, 33, 128, 70, 10, ++ 70, 72, 70, 187, 247, 103, 250, 200, 248, 0, 0, 1, 53, 189, 66, 190, ++ 209, 32, 70, 4, 169, 5, 170, 188, 247, 217, 250, 4, 159, 82, 70, 59, ++ 70, 49, 70, 0, 37, 32, 70, 0, 149, 188, 247, 28, 250, 56, 67, 4, 144, ++ 32, 70, 190, 247, 144, 248, 5, 154, 4, 155, 0, 42, 60, 208, 26, 67, ++ 99, 105, 5, 146, 34, 43, 32, 70, 10, 221, 227, 105, 90, 6, 7, 213, 64, ++ 246, 39, 1, 42, 70, 192, 243, 67, 244, 1, 70, 32, 70, 0, 224, 0, 33, ++ 64, 242, 28, 98, 192, 243, 139, 243, 99, 105, 5, 70, 34, 43, 32, 70, ++ 10, 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 46, ++ 244, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 28, 98, 192, 243, 118, 243, ++ 5, 155, 2, 104, 58, 224, 0, 191, 41, 153, 5, 0, 100, 154, 5, 0, 191, ++ 173, 58, 2, 100, 153, 5, 0, 75, 153, 5, 0, 128, 154, 5, 0, 70, 153, ++ 5, 0, 0, 43, 43, 208, 99, 105, 32, 70, 34, 43, 9, 221, 227, 105, 89, ++ 6, 6, 213, 64, 246, 39, 1, 192, 243, 7, 244, 1, 70, 32, 70, 0, 224, ++ 0, 33, 64, 242, 28, 98, 192, 243, 79, 243, 99, 105, 5, 70, 34, 43, 32, ++ 70, 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, ++ 242, 243, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 28, 98, 192, 243, 58, ++ 243, 4, 155, 2, 104, 19, 67, 43, 96, 4, 155, 171, 177, 99, 105, 32, ++ 70, 34, 43, 10, 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, 1, 0, 34, ++ 192, 243, 216, 243, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 195, 98, ++ 192, 243, 32, 243, 4, 155, 3, 96, 5, 155, 171, 177, 99, 105, 32, 70, ++ 34, 43, 10, 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, ++ 243, 192, 243, 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 28, 98, 192, 243, ++ 8, 243, 5, 155, 3, 96, 49, 70, 82, 70, 32, 70, 188, 247, 72, 253, 79, ++ 244, 250, 96, 186, 243, 199, 240, 32, 70, 89, 70, 192, 243, 65, 246, ++ 7, 176, 189, 232, 240, 143, 248, 181, 4, 70, 21, 70, 14, 70, 192, 243, ++ 234, 242, 0, 33, 7, 70, 32, 70, 192, 243, 51, 246, 49, 70, 2, 70, 43, ++ 70, 32, 70, 255, 247, 159, 253, 32, 70, 49, 70, 42, 70, 188, 247, 162, ++ 249, 32, 70, 57, 70, 189, 232, 248, 64, 192, 243, 34, 182, 56, 181, ++ 3, 106, 4, 70, 1, 43, 45, 209, 67, 105, 34, 43, 10, 221, 195, 105, 90, ++ 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 122, 243, 1, 70, 32, 70, ++ 1, 224, 32, 70, 0, 33, 79, 244, 192, 98, 192, 243, 193, 242, 99, 105, ++ 5, 70, 34, 43, 32, 70, 10, 221, 227, 105, 91, 6, 7, 213, 64, 246, 39, ++ 1, 0, 34, 192, 243, 100, 243, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, ++ 192, 98, 192, 243, 172, 242, 3, 104, 35, 244, 0, 115, 43, 96, 56, 189, ++ 44, 221, 67, 105, 34, 43, 10, 221, 195, 105, 89, 6, 7, 213, 64, 246, ++ 39, 1, 0, 34, 192, 243, 75, 243, 1, 70, 32, 70, 1, 224, 32, 70, 0, 33, ++ 79, 244, 192, 98, 192, 243, 146, 242, 99, 105, 5, 70, 34, 43, 32, 70, ++ 10, 221, 227, 105, 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 53, ++ 243, 1, 70, 32, 70, 0, 224, 0, 33, 79, 244, 192, 98, 192, 243, 125, ++ 242, 3, 104, 67, 244, 0, 115, 43, 96, 56, 189, 112, 71, 1, 32, 112, ++ 71, 56, 181, 5, 70, 12, 70, 255, 247, 156, 251, 40, 70, 33, 70, 0, 34, ++ 255, 247, 243, 255, 40, 70, 33, 70, 189, 232, 56, 64, 255, 247, 129, ++ 185, 0, 0, 56, 181, 4, 70, 13, 70, 0, 32, 49, 73, 182, 243, 49, 243, ++ 64, 177, 0, 33, 10, 70, 187, 247, 2, 249, 41, 70, 195, 178, 1, 34, 32, ++ 70, 3, 224, 32, 70, 41, 70, 1, 34, 5, 35, 188, 247, 85, 251, 0, 32, ++ 40, 73, 182, 243, 29, 243, 72, 177, 0, 33, 10, 70, 187, 247, 238, 248, ++ 41, 70, 195, 178, 9, 34, 32, 70, 188, 247, 70, 251, 0, 32, 34, 73, 182, ++ 243, 14, 243, 72, 177, 0, 33, 10, 70, 187, 247, 223, 248, 41, 70, 195, ++ 178, 5, 34, 32, 70, 188, 247, 55, 251, 0, 32, 27, 73, 182, 243, 255, ++ 242, 72, 177, 0, 33, 10, 70, 187, 247, 208, 248, 41, 70, 195, 178, 6, ++ 34, 32, 70, 188, 247, 40, 251, 0, 33, 32, 70, 79, 244, 120, 98, 79, ++ 244, 56, 99, 188, 247, 151, 250, 0, 33, 32, 70, 79, 244, 96, 66, 79, ++ 244, 32, 67, 188, 247, 143, 250, 79, 244, 192, 34, 0, 33, 19, 70, 32, ++ 70, 188, 247, 136, 250, 1, 34, 0, 33, 32, 70, 19, 70, 188, 247, 130, ++ 250, 32, 70, 41, 70, 189, 232, 56, 64, 255, 247, 213, 186, 0, 191, 118, ++ 154, 5, 0, 63, 153, 5, 0, 118, 156, 5, 0, 46, 153, 5, 0, 56, 181, 3, ++ 106, 4, 70, 9, 43, 105, 221, 67, 105, 34, 43, 10, 221, 195, 105, 91, ++ 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 148, 242, 1, 70, 32, 70, ++ 1, 224, 32, 70, 0, 33, 79, 244, 192, 98, 192, 243, 219, 241, 2, 104, ++ 18, 240, 1, 2, 83, 209, 99, 105, 32, 70, 34, 43, 9, 221, 227, 105, 93, ++ 6, 6, 213, 64, 246, 39, 1, 192, 243, 124, 242, 1, 70, 32, 70, 0, 224, ++ 0, 33, 64, 242, 108, 98, 192, 243, 196, 241, 79, 240, 0, 67, 3, 96, ++ 79, 244, 122, 112, 185, 243, 135, 247, 99, 105, 32, 70, 34, 43, 10, ++ 221, 227, 105, 89, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 97, 242, ++ 1, 70, 32, 70, 0, 224, 0, 33, 64, 242, 108, 98, 192, 243, 169, 241, ++ 5, 104, 99, 105, 237, 4, 237, 12, 34, 43, 32, 70, 10, 221, 227, 105, ++ 90, 6, 7, 213, 64, 246, 39, 1, 0, 34, 192, 243, 74, 242, 1, 70, 32, ++ 70, 0, 224, 0, 33, 64, 242, 108, 98, 192, 243, 146, 241, 109, 3, 0, ++ 35, 3, 96, 5, 245, 66, 69, 6, 72, 5, 245, 168, 117, 181, 251, 240, 245, ++ 100, 32, 104, 67, 56, 189, 0, 32, 56, 189, 0, 32, 56, 189, 0, 191, 160, ++ 134, 1, 0, 56, 181, 0, 33, 5, 70, 16, 32, 180, 247, 208, 248, 0, 33, ++ 4, 70, 16, 34, 181, 243, 207, 243, 101, 96, 32, 70, 56, 189, 8, 177, ++ 180, 247, 77, 185, 112, 71, 16, 181, 4, 70, 180, 247, 54, 250, 96, 96, ++ 224, 96, 32, 104, 189, 247, 194, 251, 99, 104, 160, 245, 0, 96, 32, ++ 97, 24, 24, 1, 35, 160, 96, 35, 118, 16, 189, 56, 181, 5, 70, 192, 243, ++ 146, 243, 28, 32, 188, 247, 201, 255, 8, 76, 0, 33, 28, 34, 32, 96, ++ 181, 243, 169, 243, 32, 104, 5, 96, 255, 247, 221, 255, 4, 73, 34, 104, ++ 40, 70, 189, 232, 56, 64, 0, 240, 122, 185, 16, 111, 4, 0, 85, 180, ++ 0, 0, 45, 233, 248, 79, 12, 70, 192, 243, 117, 243, 65, 242, 1, 0, 229, ++ 104, 188, 247, 170, 255, 0, 40, 124, 208, 0, 241, 1, 12, 6, 70, 32, ++ 224, 1, 50, 25, 112, 210, 178, 67, 70, 57, 120, 61, 70, 1, 55, 193, ++ 177, 61, 41, 3, 241, 1, 8, 243, 209, 50, 112, 41, 70, 70, 70, 0, 34, ++ 3, 224, 1, 50, 55, 112, 210, 178, 102, 70, 17, 248, 1, 127, 195, 235, ++ 5, 8, 176, 68, 6, 241, 1, 12, 0, 47, 242, 209, 26, 112, 8, 241, 1, 5, ++ 231, 104, 163, 104, 251, 24, 157, 66, 5, 210, 43, 120, 27, 177, 47, ++ 70, 99, 70, 0, 34, 215, 231, 37, 70, 1, 35, 226, 104, 131, 70, 186, ++ 26, 42, 130, 59, 224, 89, 70, 17, 248, 1, 43, 154, 66, 2, 209, 79, 240, ++ 0, 12, 10, 224, 16, 43, 42, 209, 15, 42, 248, 220, 39, 224, 27, 248, ++ 1, 143, 7, 248, 12, 128, 12, 241, 1, 12, 98, 69, 247, 209, 1, 235, 2, ++ 8, 137, 92, 7, 235, 2, 12, 79, 240, 61, 9, 7, 248, 2, 144, 8, 241, 1, ++ 11, 12, 241, 1, 7, 1, 241, 1, 9, 0, 34, 3, 224, 24, 248, 2, 160, 12, ++ 248, 2, 160, 1, 50, 74, 69, 248, 209, 122, 24, 79, 240, 0, 12, 7, 248, ++ 1, 192, 139, 68, 87, 28, 6, 224, 17, 248, 2, 176, 1, 235, 2, 12, 11, ++ 241, 1, 11, 227, 68, 179, 69, 193, 211, 1, 51, 2, 53, 17, 43, 184, 209, ++ 189, 232, 248, 79, 188, 247, 46, 191, 189, 232, 248, 143, 0, 0, 248, ++ 181, 14, 70, 23, 70, 4, 70, 192, 243, 232, 242, 48, 32, 188, 247, 31, ++ 255, 5, 70, 104, 177, 198, 96, 7, 78, 48, 35, 67, 96, 51, 104, 135, ++ 96, 3, 96, 41, 70, 32, 70, 255, 247, 94, 255, 53, 96, 0, 32, 248, 189, ++ 111, 240, 26, 0, 248, 189, 0, 8, 0, 0, 8, 181, 6, 75, 27, 104, 59, 185, ++ 5, 75, 25, 104, 33, 177, 5, 75, 26, 104, 10, 177, 255, 247, 214, 255, ++ 0, 32, 8, 189, 0, 8, 0, 0, 68, 93, 4, 0, 72, 93, 4, 0, 248, 181, 16, ++ 75, 7, 70, 28, 104, 30, 70, 188, 177, 227, 104, 155, 177, 13, 77, 42, ++ 104, 154, 66, 15, 209, 192, 243, 174, 242, 224, 104, 188, 247, 232, ++ 254, 0, 35, 43, 96, 7, 224, 56, 70, 37, 104, 192, 243, 164, 242, 32, ++ 70, 188, 247, 222, 254, 44, 70, 0, 44, 245, 209, 0, 35, 51, 96, 248, ++ 189, 0, 191, 0, 8, 0, 0, 236, 150, 5, 0, 115, 181, 133, 110, 4, 70, ++ 109, 177, 208, 248, 204, 48, 0, 235, 131, 3, 211, 248, 212, 32, 3, 110, ++ 154, 66, 3, 209, 64, 110, 168, 71, 5, 70, 0, 224, 0, 37, 32, 70, 192, ++ 243, 63, 240, 0, 35, 2, 169, 65, 248, 8, 61, 6, 70, 105, 70, 32, 70, ++ 1, 170, 13, 240, 7, 249, 157, 232, 6, 0, 79, 244, 255, 32, 179, 247, ++ 17, 255, 32, 70, 49, 70, 192, 243, 121, 243, 227, 110, 91, 177, 212, ++ 248, 204, 32, 4, 235, 130, 2, 210, 248, 212, 16, 34, 110, 145, 66, 2, ++ 209, 96, 110, 41, 70, 152, 71, 124, 189, 248, 181, 4, 70, 189, 247, ++ 22, 248, 0, 40, 79, 208, 165, 110, 109, 177, 212, 248, 204, 48, 4, 235, ++ 131, 3, 211, 248, 212, 32, 35, 110, 154, 66, 3, 209, 96, 110, 168, 71, ++ 5, 70, 0, 224, 0, 37, 32, 70, 192, 243, 3, 240, 0, 33, 7, 70, 32, 70, ++ 192, 243, 76, 243, 1, 33, 6, 70, 0, 34, 32, 70, 188, 247, 158, 255, ++ 79, 244, 128, 17, 10, 70, 32, 70, 188, 247, 134, 255, 64, 33, 10, 70, ++ 32, 70, 188, 247, 138, 255, 79, 240, 128, 113, 10, 70, 32, 70, 188, ++ 247, 123, 255, 32, 70, 255, 247, 144, 255, 15, 75, 1, 33, 198, 248, ++ 4, 53, 79, 244, 252, 115, 198, 248, 8, 53, 10, 70, 32, 70, 188, 247, ++ 126, 255, 32, 70, 57, 70, 192, 243, 34, 243, 227, 110, 91, 177, 212, ++ 248, 204, 32, 4, 235, 130, 2, 210, 248, 212, 16, 34, 110, 145, 66, 2, ++ 209, 96, 110, 41, 70, 152, 71, 248, 189, 0, 191, 242, 0, 57, 64, 112, ++ 181, 12, 70, 22, 70, 188, 247, 187, 255, 128, 177, 0, 37, 40, 70, 188, ++ 247, 250, 254, 3, 104, 27, 185, 128, 232, 80, 0, 24, 70, 112, 189, 1, ++ 53, 237, 178, 4, 45, 242, 209, 79, 240, 255, 48, 112, 189, 79, 240, ++ 255, 48, 112, 189, 1, 32, 112, 71, 195, 107, 68, 242, 88, 50, 147, 66, ++ 13, 208, 4, 216, 68, 242, 86, 50, 147, 66, 24, 209, 18, 224, 74, 246, ++ 46, 34, 147, 66, 8, 208, 74, 246, 47, 34, 147, 66, 15, 209, 192, 248, ++ 132, 51, 74, 246, 50, 35, 3, 224, 192, 248, 132, 51, 74, 246, 49, 35, ++ 195, 99, 112, 71, 192, 248, 132, 51, 68, 242, 84, 51, 195, 99, 112, ++ 71, 56, 181, 65, 242, 228, 67, 4, 70, 3, 99, 13, 70, 41, 177, 8, 70, ++ 15, 73, 182, 243, 45, 240, 160, 98, 64, 185, 40, 70, 13, 73, 182, 243, ++ 39, 240, 160, 98, 16, 185, 79, 246, 255, 115, 163, 98, 10, 73, 40, 70, ++ 182, 243, 30, 240, 9, 73, 224, 98, 40, 70, 182, 243, 25, 240, 8, 73, ++ 96, 99, 40, 70, 182, 243, 20, 240, 132, 248, 85, 0, 56, 189, 0, 191, ++ 145, 156, 5, 0, 135, 156, 5, 0, 206, 156, 5, 0, 167, 156, 5, 0, 178, ++ 156, 5, 0, 112, 71, 0, 0, 48, 181, 133, 176, 1, 144, 0, 36, 4, 168, ++ 64, 248, 4, 77, 1, 169, 4, 34, 179, 247, 37, 254, 1, 157, 181, 177, ++ 43, 70, 211, 248, 140, 32, 18, 177, 0, 34, 195, 248, 140, 32, 1, 52, ++ 4, 51, 16, 44, 245, 209, 3, 152, 254, 247, 169, 249, 3, 152, 255, 247, ++ 182, 254, 3, 75, 157, 66, 2, 208, 40, 70, 188, 247, 169, 253, 5, 176, ++ 48, 189, 96, 111, 4, 0, 3, 103, 208, 248, 204, 48, 16, 181, 0, 235, ++ 131, 3, 2, 156, 211, 248, 212, 48, 68, 102, 129, 102, 194, 102, 3, 102, ++ 16, 189, 0, 35, 131, 102, 195, 102, 3, 103, 112, 71, 45, 233, 248, 67, ++ 4, 70, 30, 70, 8, 157, 9, 159, 250, 247, 117, 252, 0, 33, 32, 70, 192, ++ 243, 85, 242, 128, 70, 32, 70, 191, 243, 11, 247, 10, 40, 200, 191, ++ 216, 248, 44, 48, 96, 97, 200, 191, 163, 100, 34, 40, 216, 248, 4, 48, ++ 200, 191, 216, 248, 172, 32, 163, 97, 200, 191, 226, 97, 219, 0, 28, ++ 213, 34, 40, 20, 221, 227, 105, 89, 6, 17, 213, 0, 34, 32, 70, 64, 246, ++ 39, 1, 191, 243, 156, 247, 1, 70, 32, 70, 192, 243, 48, 242, 208, 248, ++ 4, 54, 0, 33, 99, 98, 32, 70, 192, 243, 41, 242, 2, 224, 216, 248, 4, ++ 54, 99, 98, 148, 248, 36, 48, 35, 98, 79, 244, 224, 99, 163, 96, 79, ++ 240, 255, 51, 227, 96, 17, 35, 35, 97, 161, 70, 79, 240, 0, 8, 23, 224, ++ 65, 70, 192, 243, 19, 242, 32, 70, 191, 243, 186, 246, 32, 70, 191, ++ 243, 199, 246, 30, 177, 217, 248, 20, 49, 158, 66, 3, 208, 217, 248, ++ 140, 48, 159, 66, 1, 209, 197, 248, 0, 128, 8, 241, 1, 8, 9, 241, 4, ++ 9, 212, 248, 208, 48, 32, 70, 152, 69, 226, 211, 41, 104, 192, 243, ++ 246, 241, 1, 32, 189, 232, 248, 131, 247, 181, 0, 34, 19, 70, 13, 70, ++ 1, 33, 4, 70, 187, 247, 236, 254, 0, 33, 40, 34, 11, 70, 7, 70, 32, ++ 70, 0, 145, 191, 243, 153, 246, 41, 7, 6, 70, 9, 208, 32, 70, 1, 33, ++ 6, 34, 192, 243, 27, 240, 32, 70, 2, 33, 6, 34, 192, 243, 22, 240, 21, ++ 240, 240, 15, 4, 208, 32, 70, 0, 33, 2, 34, 192, 243, 14, 240, 1, 33, ++ 59, 70, 32, 70, 79, 240, 255, 50, 187, 247, 200, 254, 32, 70, 0, 33, ++ 40, 34, 79, 240, 255, 51, 0, 150, 191, 243, 117, 246, 254, 189, 0, 32, ++ 181, 243, 35, 183, 0, 0, 16, 181, 12, 73, 4, 70, 255, 247, 247, 255, ++ 128, 178, 136, 185, 212, 248, 128, 0, 8, 73, 181, 243, 22, 247, 128, ++ 178, 80, 185, 212, 248, 128, 0, 5, 73, 181, 243, 15, 247, 79, 246, 255, ++ 115, 128, 178, 0, 40, 8, 191, 24, 70, 16, 189, 200, 156, 5, 0, 8, 157, ++ 5, 0, 67, 105, 7, 181, 10, 43, 9, 221, 0, 49, 24, 191, 1, 33, 0, 145, ++ 36, 34, 0, 33, 1, 35, 191, 243, 69, 246, 1, 224, 79, 240, 255, 48, 14, ++ 189, 7, 181, 0, 33, 248, 34, 11, 70, 0, 145, 191, 243, 58, 246, 0, 240, ++ 15, 0, 14, 189, 0, 0, 45, 233, 255, 71, 221, 248, 48, 128, 146, 70, ++ 221, 248, 52, 144, 15, 70, 79, 244, 99, 114, 0, 33, 4, 70, 30, 70, 14, ++ 157, 184, 241, 1, 15, 8, 191, 79, 240, 0, 8, 181, 243, 127, 240, 17, ++ 35, 35, 97, 196, 248, 136, 96, 196, 248, 92, 144, 196, 248, 88, 160, ++ 196, 248, 4, 128, 184, 241, 0, 15, 64, 240, 197, 128, 32, 70, 65, 70, ++ 58, 70, 75, 70, 255, 247, 97, 254, 0, 40, 0, 240, 192, 128, 79, 240, ++ 192, 83, 26, 104, 19, 15, 2, 244, 112, 33, 35, 96, 147, 178, 2, 244, ++ 112, 2, 18, 13, 98, 100, 68, 242, 88, 50, 9, 12, 147, 66, 227, 99, 33, ++ 100, 10, 208, 4, 216, 68, 242, 86, 50, 147, 66, 8, 209, 4, 224, 163, ++ 245, 42, 67, 46, 59, 1, 43, 2, 216, 32, 70, 255, 247, 63, 254, 99, 108, ++ 32, 70, 14, 59, 1, 43, 140, 191, 0, 35, 1, 35, 132, 248, 76, 48, 79, ++ 240, 192, 81, 58, 70, 250, 247, 185, 249, 212, 248, 208, 48, 0, 43, ++ 0, 240, 138, 128, 0, 39, 4, 171, 67, 248, 4, 125, 141, 232, 72, 0, 32, ++ 70, 79, 240, 192, 81, 58, 70, 59, 70, 255, 247, 178, 254, 0, 40, 124, ++ 208, 32, 70, 255, 247, 50, 253, 15, 155, 0, 149, 1, 147, 32, 70, 57, ++ 70, 50, 70, 163, 109, 254, 247, 27, 248, 0, 40, 112, 209, 5, 177, 45, ++ 104, 58, 78, 32, 70, 41, 70, 255, 247, 44, 254, 50, 120, 0, 42, 66, ++ 209, 99, 105, 19, 43, 25, 221, 79, 244, 0, 97, 32, 70, 192, 243, 227, ++ 240, 51, 73, 7, 70, 40, 70, 181, 243, 120, 246, 56, 177, 40, 70, 47, ++ 73, 181, 243, 79, 246, 176, 241, 255, 63, 8, 191, 0, 32, 0, 35, 187, ++ 101, 3, 153, 248, 101, 32, 70, 192, 243, 220, 240, 32, 70, 161, 109, ++ 255, 247, 182, 250, 32, 70, 161, 109, 255, 247, 23, 251, 40, 70, 37, ++ 73, 181, 243, 56, 246, 2, 70, 32, 185, 32, 70, 161, 109, 255, 247, 142, ++ 251, 2, 70, 196, 248, 136, 35, 161, 109, 32, 70, 255, 247, 133, 250, ++ 32, 70, 255, 247, 86, 253, 32, 70, 161, 109, 255, 247, 176, 248, 32, ++ 70, 161, 109, 255, 247, 12, 251, 1, 35, 51, 112, 32, 70, 191, 243, 165, ++ 247, 40, 70, 21, 73, 181, 243, 59, 246, 56, 177, 19, 73, 40, 70, 181, ++ 243, 18, 246, 1, 70, 32, 70, 255, 247, 179, 254, 40, 70, 16, 73, 181, ++ 243, 46, 246, 120, 177, 40, 70, 13, 73, 181, 243, 5, 246, 1, 70, 32, ++ 70, 255, 247, 251, 253, 6, 224, 0, 36, 4, 224, 28, 70, 2, 224, 4, 70, ++ 0, 224, 60, 70, 32, 70, 4, 176, 189, 232, 240, 135, 0, 191, 92, 111, ++ 4, 0, 162, 156, 5, 0, 191, 156, 5, 0, 0, 157, 5, 0, 152, 156, 5, 0, ++ 31, 181, 15, 76, 2, 70, 35, 120, 187, 185, 16, 185, 3, 70, 1, 70, 1, ++ 224, 12, 75, 25, 29, 0, 32, 0, 144, 1, 144, 2, 147, 3, 145, 9, 72, 68, ++ 242, 16, 113, 79, 240, 192, 83, 255, 247, 235, 254, 40, 177, 6, 75, ++ 32, 34, 26, 96, 1, 35, 35, 112, 3, 72, 4, 176, 16, 189, 236, 114, 4, ++ 0, 224, 111, 4, 0, 96, 111, 4, 0, 12, 8, 0, 0, 45, 233, 255, 71, 7, ++ 70, 79, 244, 99, 112, 136, 70, 145, 70, 154, 70, 13, 158, 14, 157, 188, ++ 247, 124, 251, 4, 70, 200, 177, 12, 155, 57, 70, 1, 147, 66, 70, 75, ++ 70, 205, 248, 0, 160, 2, 150, 3, 149, 255, 247, 193, 254, 7, 70, 32, ++ 185, 32, 70, 188, 247, 109, 251, 60, 70, 7, 224, 6, 177, 54, 104, 196, ++ 248, 128, 96, 5, 177, 45, 104, 196, 248, 132, 80, 32, 70, 4, 176, 189, ++ 232, 240, 135, 112, 181, 6, 70, 134, 176, 79, 244, 188, 112, 188, 247, ++ 85, 251, 4, 70, 232, 177, 0, 33, 79, 244, 188, 114, 180, 243, 52, 247, ++ 13, 75, 38, 96, 0, 147, 13, 75, 0, 37, 1, 147, 48, 104, 12, 73, 12, ++ 74, 35, 70, 2, 149, 3, 149, 4, 149, 5, 149, 0, 240, 128, 254, 48, 185, ++ 79, 244, 150, 99, 196, 248, 96, 49, 132, 248, 100, 1, 0, 224, 44, 70, ++ 32, 70, 6, 176, 112, 189, 21, 49, 129, 0, 65, 54, 129, 0, 36, 179, 135, ++ 0, 163, 170, 136, 0, 16, 181, 4, 70, 80, 177, 3, 104, 5, 73, 24, 104, ++ 34, 70, 0, 240, 8, 254, 32, 70, 189, 232, 16, 64, 188, 247, 31, 187, ++ 16, 189, 0, 191, 163, 170, 136, 0, 56, 181, 5, 70, 24, 32, 188, 247, ++ 19, 251, 4, 70, 160, 177, 0, 33, 24, 34, 180, 243, 243, 246, 37, 96, ++ 168, 104, 8, 73, 34, 70, 0, 35, 202, 243, 214, 243, 5, 70, 32, 97, 32, ++ 185, 32, 70, 188, 247, 3, 251, 44, 70, 1, 224, 4, 35, 227, 96, 32, 70, ++ 56, 189, 201, 58, 129, 0, 16, 181, 4, 70, 40, 185, 16, 189, 203, 107, ++ 32, 70, 99, 96, 196, 243, 157, 246, 97, 104, 0, 41, 247, 209, 3, 224, ++ 3, 104, 99, 97, 188, 247, 234, 250, 96, 105, 0, 40, 248, 209, 35, 104, ++ 33, 105, 152, 104, 202, 243, 41, 243, 35, 104, 33, 105, 152, 104, 202, ++ 243, 156, 243, 32, 70, 189, 232, 16, 64, 188, 247, 216, 186, 0, 0, 45, ++ 233, 240, 65, 5, 70, 134, 176, 128, 32, 188, 247, 205, 250, 4, 70, 0, ++ 40, 68, 208, 0, 33, 128, 34, 180, 243, 172, 246, 4, 35, 99, 96, 180, ++ 35, 37, 96, 163, 129, 160, 70, 197, 248, 68, 71, 39, 70, 0, 38, 14, ++ 224, 28, 34, 2, 251, 6, 66, 60, 97, 168, 104, 27, 73, 16, 50, 0, 35, ++ 202, 243, 129, 243, 56, 98, 28, 55, 0, 40, 43, 208, 1, 54, 99, 104, ++ 158, 66, 237, 219, 22, 75, 22, 73, 0, 147, 0, 35, 1, 147, 2, 147, 3, ++ 147, 4, 147, 5, 147, 40, 104, 19, 74, 35, 70, 0, 240, 221, 253, 192, ++ 185, 19, 224, 216, 248, 32, 16, 49, 177, 35, 104, 152, 104, 202, 243, ++ 84, 243, 0, 35, 200, 248, 32, 48, 1, 53, 8, 241, 28, 8, 99, 104, 157, ++ 66, 239, 219, 32, 70, 188, 247, 137, 250, 0, 36, 32, 70, 6, 176, 189, ++ 232, 240, 129, 0, 37, 242, 231, 0, 191, 241, 63, 129, 0, 81, 62, 129, ++ 0, 200, 179, 135, 0, 235, 40, 136, 0, 112, 181, 4, 70, 0, 40, 30, 208, ++ 3, 104, 15, 73, 24, 104, 34, 70, 0, 240, 83, 253, 37, 70, 0, 38, 13, ++ 224, 41, 106, 41, 177, 35, 104, 152, 104, 202, 243, 37, 243, 0, 35, ++ 43, 98, 232, 105, 8, 177, 188, 247, 96, 250, 1, 54, 28, 53, 99, 104, ++ 158, 66, 238, 219, 32, 70, 189, 232, 112, 64, 188, 247, 86, 186, 112, ++ 189, 235, 40, 136, 0, 16, 181, 4, 70, 192, 111, 8, 177, 255, 247, 32, ++ 255, 212, 248, 132, 0, 8, 177, 7, 240, 219, 250, 212, 248, 128, 0, 8, ++ 177, 255, 247, 202, 255, 212, 248, 164, 0, 8, 177, 255, 247, 67, 255, ++ 212, 248, 180, 0, 8, 177, 0, 240, 26, 249, 160, 104, 8, 177, 1, 240, ++ 44, 249, 32, 70, 189, 232, 16, 64, 188, 247, 48, 186, 0, 0, 45, 233, ++ 240, 79, 7, 70, 141, 176, 188, 32, 138, 70, 144, 70, 29, 70, 23, 158, ++ 188, 247, 33, 250, 4, 70, 0, 40, 0, 240, 166, 128, 79, 240, 0, 11, 0, ++ 33, 188, 34, 180, 243, 253, 245, 38, 96, 132, 248, 140, 176, 56, 70, ++ 255, 247, 29, 250, 11, 171, 196, 248, 172, 176, 42, 70, 1, 144, 6, 147, ++ 129, 70, 65, 242, 228, 65, 32, 70, 51, 70, 205, 248, 0, 176, 205, 248, ++ 8, 160, 205, 248, 12, 128, 4, 148, 205, 248, 20, 176, 1, 240, 165, 249, ++ 5, 70, 0, 40, 123, 208, 160, 96, 221, 243, 141, 244, 43, 105, 16, 33, ++ 227, 96, 63, 75, 96, 96, 163, 100, 63, 74, 51, 70, 39, 97, 100, 100, ++ 56, 70, 180, 243, 52, 246, 43, 105, 216, 111, 191, 243, 246, 242, 73, ++ 246, 152, 19, 152, 66, 43, 105, 216, 111, 6, 216, 191, 243, 238, 242, ++ 8, 33, 3, 70, 53, 74, 9, 168, 5, 224, 191, 243, 231, 242, 52, 74, 3, ++ 70, 8, 33, 9, 168, 180, 243, 27, 246, 49, 70, 9, 170, 49, 75, 49, 72, ++ 180, 243, 213, 245, 50, 70, 0, 32, 22, 153, 47, 75, 141, 232, 128, 1, ++ 248, 247, 7, 252, 6, 70, 0, 40, 65, 209, 99, 104, 1, 39, 131, 248, 120, ++ 112, 8, 33, 10, 70, 40, 105, 246, 243, 11, 243, 54, 33, 58, 70, 213, ++ 248, 124, 2, 218, 247, 171, 254, 40, 70, 255, 247, 216, 254, 196, 248, ++ 128, 0, 96, 179, 40, 70, 255, 247, 142, 254, 196, 248, 164, 0, 48, 179, ++ 40, 70, 7, 240, 2, 250, 196, 248, 132, 0, 0, 179, 40, 70, 255, 247, ++ 62, 254, 224, 103, 216, 177, 99, 104, 25, 73, 131, 248, 228, 112, 24, ++ 75, 2, 150, 141, 232, 72, 0, 3, 150, 4, 150, 5, 150, 40, 104, 21, 74, ++ 35, 70, 0, 240, 202, 252, 80, 185, 40, 70, 0, 240, 50, 248, 196, 248, ++ 180, 0, 32, 177, 17, 72, 33, 70, 184, 243, 241, 246, 32, 177, 32, 70, ++ 73, 70, 255, 247, 40, 255, 0, 36, 32, 70, 13, 176, 189, 232, 240, 143, ++ 0, 191, 149, 149, 129, 0, 253, 49, 4, 0, 2, 50, 4, 0, 48, 184, 136, ++ 0, 211, 22, 4, 0, 14, 157, 5, 0, 205, 154, 129, 0, 20, 182, 135, 0, ++ 225, 150, 129, 0, 7, 50, 4, 0, 189, 150, 129, 0, 1, 32, 112, 71, 2, ++ 75, 1, 34, 26, 112, 179, 247, 63, 187, 0, 191, 52, 7, 0, 0, 112, 181, ++ 6, 70, 134, 176, 32, 32, 185, 243, 62, 243, 4, 70, 240, 177, 0, 33, ++ 32, 34, 180, 243, 44, 245, 79, 244, 225, 83, 227, 128, 75, 35, 35, 129, ++ 10, 35, 99, 129, 14, 75, 38, 96, 0, 37, 0, 147, 48, 104, 12, 73, 13, ++ 74, 35, 70, 1, 149, 2, 149, 3, 149, 4, 149, 5, 149, 0, 240, 114, 252, ++ 48, 185, 51, 104, 1, 34, 131, 248, 103, 33, 32, 70, 6, 176, 112, 189, ++ 32, 70, 188, 247, 40, 249, 44, 70, 247, 231, 0, 191, 81, 211, 0, 0, ++ 76, 50, 4, 0, 72, 50, 4, 0, 16, 181, 4, 70, 120, 177, 190, 247, 140, ++ 248, 35, 104, 34, 70, 24, 104, 5, 73, 0, 240, 248, 251, 32, 70, 188, ++ 247, 17, 249, 35, 104, 0, 34, 27, 104, 131, 248, 103, 33, 16, 189, 72, ++ 50, 4, 0, 3, 104, 211, 248, 216, 32, 65, 242, 107, 3, 17, 107, 153, ++ 66, 11, 209, 147, 106, 239, 43, 40, 208, 1, 216, 214, 43, 4, 224, 245, ++ 43, 35, 208, 64, 242, 15, 17, 139, 66, 31, 208, 147, 106, 64, 242, 198, ++ 82, 147, 66, 26, 208, 64, 242, 116, 82, 147, 66, 22, 208, 3, 106, 127, ++ 34, 16, 224, 72, 34, 131, 248, 5, 33, 6, 224, 2, 240, 192, 2, 146, 17, ++ 2, 235, 129, 1, 131, 248, 5, 17, 3, 106, 147, 249, 5, 33, 20, 42, 11, ++ 220, 72, 34, 131, 248, 5, 33, 112, 71, 3, 106, 147, 248, 5, 17, 74, ++ 178, 178, 241, 255, 63, 232, 209, 227, 231, 112, 71, 208, 248, 236, ++ 17, 16, 181, 4, 70, 41, 177, 128, 104, 202, 243, 131, 241, 0, 35, 196, ++ 248, 236, 49, 212, 248, 4, 18, 41, 177, 160, 104, 202, 243, 122, 241, ++ 0, 35, 196, 248, 4, 50, 212, 248, 116, 52, 211, 248, 48, 17, 57, 177, ++ 160, 104, 202, 243, 111, 241, 212, 248, 116, 52, 0, 34, 195, 248, 48, ++ 33, 212, 248, 52, 19, 41, 177, 160, 104, 202, 243, 100, 241, 0, 35, ++ 196, 248, 52, 51, 212, 248, 60, 21, 41, 177, 160, 104, 202, 243, 91, ++ 241, 0, 35, 196, 248, 60, 53, 212, 248, 220, 21, 41, 177, 160, 104, ++ 202, 243, 82, 241, 0, 35, 196, 248, 220, 53, 212, 248, 180, 23, 41, ++ 177, 160, 104, 202, 243, 73, 241, 0, 35, 196, 248, 180, 55, 16, 189, ++ 16, 181, 4, 70, 0, 104, 6, 240, 94, 253, 212, 248, 104, 6, 32, 177, ++ 5, 240, 215, 252, 0, 35, 196, 248, 104, 54, 212, 248, 100, 6, 32, 177, ++ 5, 240, 5, 255, 0, 35, 196, 248, 100, 54, 212, 248, 160, 1, 32, 177, ++ 8, 240, 75, 250, 0, 35, 196, 248, 160, 49, 212, 248, 144, 1, 32, 177, ++ 1, 240, 157, 253, 0, 35, 196, 248, 144, 49, 212, 248, 68, 1, 32, 177, ++ 2, 240, 217, 254, 0, 35, 196, 248, 68, 49, 212, 248, 88, 1, 32, 177, ++ 205, 243, 185, 244, 0, 35, 196, 248, 88, 49, 212, 248, 48, 1, 32, 177, ++ 2, 240, 125, 251, 0, 35, 196, 248, 48, 49, 212, 248, 52, 1, 32, 177, ++ 2, 240, 27, 249, 0, 35, 196, 248, 52, 49, 212, 248, 56, 1, 32, 177, ++ 2, 240, 123, 250, 0, 35, 196, 248, 56, 49, 32, 70, 2, 240, 47, 250, ++ 212, 248, 80, 1, 32, 177, 5, 240, 124, 255, 0, 35, 196, 248, 80, 49, ++ 212, 248, 76, 1, 32, 177, 8, 240, 58, 249, 0, 35, 196, 248, 76, 49, ++ 212, 248, 72, 1, 32, 177, 5, 240, 238, 253, 0, 35, 196, 248, 72, 49, ++ 212, 248, 96, 1, 32, 177, 7, 240, 250, 253, 0, 35, 196, 248, 96, 49, ++ 212, 248, 44, 49, 19, 177, 0, 35, 196, 248, 44, 49, 212, 248, 100, 1, ++ 32, 177, 3, 240, 34, 255, 0, 35, 196, 248, 100, 49, 32, 70, 7, 240, ++ 136, 254, 32, 70, 5, 240, 85, 252, 212, 248, 84, 1, 32, 177, 5, 240, ++ 176, 252, 0, 35, 196, 248, 84, 49, 212, 248, 116, 1, 32, 177, 1, 240, ++ 22, 252, 0, 35, 196, 248, 116, 49, 212, 248, 124, 1, 32, 177, 4, 240, ++ 34, 250, 0, 35, 196, 248, 124, 49, 212, 248, 128, 1, 32, 177, 7, 240, ++ 122, 250, 0, 35, 196, 248, 128, 49, 212, 248, 120, 1, 32, 177, 8, 240, ++ 52, 249, 0, 35, 196, 248, 120, 49, 212, 248, 136, 1, 32, 177, 1, 240, ++ 142, 251, 0, 35, 196, 248, 136, 49, 212, 248, 140, 1, 32, 177, 4, 240, ++ 92, 249, 0, 35, 196, 248, 140, 49, 212, 248, 104, 4, 32, 177, 7, 240, ++ 2, 249, 0, 35, 196, 248, 104, 52, 212, 248, 108, 4, 32, 177, 7, 240, ++ 60, 249, 0, 35, 196, 248, 108, 52, 212, 248, 112, 4, 32, 177, 7, 240, ++ 206, 249, 0, 35, 196, 248, 112, 52, 212, 248, 152, 1, 32, 177, 8, 240, ++ 100, 250, 0, 35, 196, 248, 152, 49, 212, 248, 228, 6, 32, 177, 7, 240, ++ 44, 253, 0, 35, 196, 248, 228, 54, 212, 248, 132, 6, 32, 177, 4, 240, ++ 96, 252, 0, 35, 196, 248, 132, 54, 212, 248, 136, 6, 32, 177, 1, 240, ++ 224, 252, 0, 35, 196, 248, 136, 54, 212, 248, 184, 6, 32, 177, 4, 240, ++ 56, 252, 0, 35, 196, 248, 184, 54, 212, 248, 192, 6, 32, 177, 4, 240, ++ 118, 250, 0, 35, 196, 248, 192, 54, 212, 248, 188, 6, 32, 177, 7, 240, ++ 106, 254, 0, 35, 196, 248, 188, 54, 212, 248, 80, 8, 32, 177, 7, 240, ++ 236, 250, 0, 35, 196, 248, 80, 56, 212, 248, 200, 6, 32, 177, 7, 240, ++ 20, 248, 0, 35, 196, 248, 200, 54, 212, 248, 156, 6, 8, 177, 5, 240, ++ 57, 250, 212, 248, 152, 6, 8, 177, 5, 240, 52, 250, 212, 248, 148, 6, ++ 8, 177, 5, 240, 47, 250, 212, 248, 144, 6, 8, 177, 5, 240, 42, 250, ++ 212, 248, 164, 6, 8, 177, 5, 240, 37, 250, 212, 248, 168, 6, 8, 177, ++ 5, 240, 32, 250, 212, 248, 164, 1, 32, 177, 3, 240, 188, 253, 0, 35, ++ 196, 248, 164, 49, 212, 248, 220, 6, 32, 177, 5, 240, 120, 254, 0, 35, ++ 196, 248, 220, 54, 212, 248, 28, 7, 32, 177, 187, 247, 55, 255, 0, 35, ++ 196, 248, 28, 55, 212, 248, 140, 6, 32, 177, 5, 240, 222, 249, 0, 35, ++ 196, 248, 140, 54, 212, 248, 124, 6, 32, 177, 4, 240, 218, 252, 0, 35, ++ 196, 248, 124, 54, 212, 248, 36, 1, 32, 177, 7, 240, 68, 252, 0, 35, ++ 196, 248, 36, 49, 212, 248, 40, 1, 32, 177, 3, 240, 170, 252, 0, 35, ++ 196, 248, 40, 49, 212, 248, 120, 4, 32, 177, 5, 240, 104, 255, 0, 35, ++ 196, 248, 120, 52, 212, 248, 208, 5, 32, 177, 4, 240, 88, 218, 0, 35, ++ 196, 248, 208, 53, 212, 248, 32, 6, 32, 177, 249, 247, 152, 255, 0, ++ 35, 196, 248, 32, 54, 32, 70, 189, 232, 16, 64, 4, 240, 66, 185, 247, ++ 181, 3, 106, 4, 70, 147, 249, 4, 1, 67, 28, 44, 208, 35, 104, 147, 248, ++ 124, 32, 10, 42, 2, 216, 205, 243, 70, 243, 37, 224, 211, 248, 220, ++ 80, 20, 73, 40, 70, 181, 243, 25, 241, 19, 73, 141, 248, 4, 0, 40, 70, ++ 181, 243, 19, 241, 17, 73, 141, 248, 5, 0, 40, 70, 181, 243, 13, 241, ++ 0, 37, 141, 248, 6, 0, 46, 70, 1, 175, 120, 87, 205, 243, 43, 243, 118, ++ 178, 232, 85, 1, 53, 176, 66, 168, 191, 6, 70, 3, 45, 246, 178, 242, ++ 209, 48, 70, 0, 224, 8, 32, 35, 106, 131, 248, 4, 1, 254, 189, 0, 191, ++ 66, 157, 5, 0, 72, 157, 5, 0, 78, 157, 5, 0, 3, 104, 208, 248, 116, ++ 36, 112, 181, 211, 248, 220, 80, 3, 35, 211, 113, 208, 248, 116, 36, ++ 4, 70, 19, 114, 208, 248, 116, 36, 65, 73, 130, 248, 173, 48, 208, 248, ++ 116, 36, 40, 70, 130, 248, 174, 48, 181, 243, 214, 240, 64, 178, 32, ++ 185, 40, 70, 60, 73, 181, 243, 208, 240, 64, 178, 67, 30, 14, 43, 14, ++ 216, 1, 40, 3, 209, 212, 248, 116, 36, 0, 35, 4, 224, 2, 40, 6, 209, ++ 212, 248, 116, 36, 1, 35, 211, 113, 212, 248, 116, 36, 19, 114, 50, ++ 73, 40, 70, 38, 106, 181, 243, 184, 240, 134, 248, 4, 1, 32, 70, 255, ++ 247, 133, 255, 46, 73, 40, 70, 38, 106, 181, 243, 174, 240, 134, 248, ++ 5, 1, 32, 70, 255, 247, 105, 253, 35, 106, 147, 248, 5, 33, 131, 248, ++ 6, 33, 33, 104, 65, 242, 107, 2, 209, 248, 216, 48, 24, 107, 144, 66, ++ 41, 209, 34, 106, 146, 249, 4, 1, 8, 40, 36, 220, 155, 106, 209, 43, ++ 18, 208, 233, 43, 16, 208, 144, 43, 14, 208, 139, 43, 12, 208, 141, ++ 43, 1, 209, 13, 35, 21, 224, 147, 43, 10, 209, 177, 248, 122, 48, 27, ++ 5, 27, 13, 179, 245, 130, 111, 1, 220, 24, 35, 10, 224, 27, 35, 8, 224, ++ 142, 43, 1, 209, 16, 35, 4, 224, 214, 43, 1, 208, 228, 43, 2, 209, 23, ++ 35, 130, 248, 4, 49, 35, 104, 64, 242, 116, 82, 211, 248, 216, 48, 155, ++ 106, 147, 66, 3, 208, 64, 242, 198, 82, 147, 66, 7, 209, 35, 106, 147, ++ 249, 4, 33, 8, 42, 2, 220, 23, 34, 131, 248, 4, 33, 1, 32, 112, 189, ++ 150, 158, 5, 0, 84, 157, 5, 0, 167, 158, 5, 0, 88, 157, 5, 0, 16, 181, ++ 4, 70, 28, 73, 128, 104, 34, 70, 0, 35, 201, 243, 226, 246, 196, 248, ++ 236, 1, 112, 179, 160, 104, 24, 73, 34, 70, 0, 35, 201, 243, 217, 246, ++ 196, 248, 4, 2, 40, 179, 160, 104, 21, 73, 34, 70, 0, 35, 201, 243, ++ 208, 246, 196, 248, 52, 3, 224, 177, 160, 104, 17, 73, 34, 70, 0, 35, ++ 201, 243, 199, 246, 196, 248, 60, 5, 152, 177, 160, 104, 14, 73, 34, ++ 70, 0, 35, 201, 243, 190, 246, 196, 248, 220, 5, 80, 177, 0, 35, 160, ++ 104, 10, 73, 34, 70, 201, 243, 181, 246, 196, 248, 180, 7, 0, 48, 24, ++ 191, 1, 32, 16, 189, 0, 191, 49, 56, 130, 0, 133, 255, 129, 0, 237, ++ 239, 129, 0, 241, 250, 129, 0, 129, 50, 130, 0, 151, 117, 1, 0, 112, ++ 181, 255, 34, 4, 70, 1, 35, 132, 248, 99, 36, 132, 248, 191, 34, 65, ++ 242, 1, 1, 212, 248, 116, 36, 0, 38, 3, 118, 164, 248, 72, 20, 100, ++ 32, 3, 33, 132, 248, 48, 5, 132, 248, 102, 52, 132, 248, 98, 100, 209, ++ 113, 212, 248, 116, 36, 64, 246, 42, 21, 17, 114, 164, 248, 74, 84, ++ 164, 248, 76, 84, 164, 248, 78, 84, 164, 248, 80, 84, 164, 248, 82, ++ 84, 164, 248, 84, 84, 164, 248, 86, 84, 164, 248, 94, 20, 64, 246, 43, ++ 21, 2, 33, 164, 248, 88, 84, 164, 248, 96, 20, 7, 37, 4, 33, 164, 248, ++ 90, 84, 164, 248, 92, 20, 164, 248, 22, 6, 164, 248, 88, 99, 132, 248, ++ 36, 98, 164, 248, 20, 102, 132, 248, 56, 98, 132, 248, 39, 98, 132, ++ 248, 37, 98, 132, 248, 226, 100, 132, 248, 148, 98, 132, 248, 23, 101, ++ 33, 104, 79, 240, 255, 48, 129, 248, 83, 48, 72, 99, 33, 104, 32, 70, ++ 129, 248, 66, 48, 33, 104, 129, 248, 67, 48, 33, 104, 129, 248, 213, ++ 96, 33, 104, 129, 248, 68, 96, 33, 104, 132, 248, 18, 98, 132, 248, ++ 19, 98, 196, 248, 56, 102, 129, 248, 57, 96, 34, 104, 130, 248, 148, ++ 48, 34, 104, 130, 248, 249, 48, 34, 104, 130, 248, 248, 48, 34, 104, ++ 130, 248, 160, 48, 34, 104, 130, 248, 54, 49, 34, 104, 150, 102, 132, ++ 248, 84, 51, 132, 248, 85, 51, 146, 248, 79, 16, 137, 7, 24, 191, 130, ++ 248, 82, 48, 3, 35, 0, 34, 1, 37, 132, 248, 58, 101, 164, 248, 56, 37, ++ 132, 248, 224, 49, 132, 248, 232, 49, 79, 244, 72, 115, 164, 248, 36, ++ 53, 132, 248, 197, 85, 212, 243, 175, 244, 5, 35, 132, 248, 8, 54, 35, ++ 104, 132, 248, 32, 97, 132, 248, 64, 86, 131, 248, 21, 81, 35, 104, ++ 79, 240, 255, 49, 164, 248, 92, 23, 164, 248, 68, 24, 132, 248, 95, ++ 103, 132, 248, 145, 87, 132, 248, 160, 87, 131, 248, 70, 81, 35, 104, ++ 131, 248, 71, 81, 35, 104, 131, 248, 96, 97, 112, 189, 45, 233, 240, ++ 71, 15, 70, 146, 70, 0, 40, 52, 208, 4, 104, 0, 44, 53, 208, 79, 240, ++ 0, 8, 193, 70, 40, 224, 212, 248, 168, 2, 57, 70, 64, 68, 180, 243, ++ 120, 241, 232, 185, 212, 248, 172, 50, 79, 234, 137, 6, 83, 248, 41, ++ 48, 83, 69, 21, 209, 212, 248, 168, 50, 67, 68, 93, 107, 1, 61, 93, ++ 99, 237, 185, 24, 70, 41, 70, 56, 34, 180, 243, 215, 240, 212, 248, ++ 172, 2, 41, 70, 128, 25, 4, 34, 180, 243, 208, 240, 40, 70, 189, 232, ++ 240, 135, 9, 241, 1, 9, 8, 241, 56, 8, 35, 104, 147, 248, 184, 48, 153, ++ 69, 209, 219, 111, 240, 29, 0, 189, 232, 240, 135, 111, 240, 29, 0, ++ 189, 232, 240, 135, 248, 181, 0, 37, 15, 70, 6, 104, 44, 70, 8, 224, ++ 214, 248, 168, 2, 57, 70, 64, 25, 180, 243, 60, 241, 56, 53, 56, 177, ++ 1, 52, 51, 104, 147, 248, 184, 48, 156, 66, 241, 219, 111, 240, 29, ++ 4, 32, 70, 248, 189, 45, 233, 240, 71, 138, 70, 17, 70, 152, 70, 145, ++ 70, 4, 104, 255, 247, 223, 255, 3, 30, 5, 218, 35, 104, 0, 38, 147, ++ 248, 184, 32, 53, 70, 59, 224, 212, 248, 172, 34, 56, 32, 66, 248, 35, ++ 128, 212, 248, 168, 34, 0, 251, 3, 32, 67, 107, 1, 51, 67, 99, 0, 32, ++ 189, 232, 240, 135, 212, 248, 168, 50, 6, 241, 56, 1, 159, 93, 152, ++ 25, 31, 187, 73, 70, 31, 34, 180, 243, 89, 241, 212, 248, 168, 50, 12, ++ 153, 158, 25, 8, 155, 198, 248, 32, 160, 179, 98, 9, 155, 56, 70, 115, ++ 98, 10, 155, 243, 98, 11, 155, 51, 99, 212, 248, 4, 55, 67, 248, 53, ++ 16, 3, 235, 197, 2, 13, 155, 83, 96, 115, 107, 1, 51, 115, 99, 212, ++ 248, 172, 50, 67, 248, 37, 128, 189, 232, 240, 135, 1, 53, 14, 70, 149, ++ 66, 208, 219, 111, 240, 21, 0, 189, 232, 240, 135, 45, 233, 240, 65, ++ 7, 104, 12, 70, 21, 70, 152, 70, 215, 248, 176, 2, 0, 38, 4, 224, 3, ++ 104, 156, 66, 11, 208, 6, 70, 0, 105, 0, 40, 248, 209, 17, 224, 0, 35, ++ 3, 97, 14, 177, 48, 97, 1, 224, 199, 248, 176, 2, 6, 155, 128, 232, ++ 48, 1, 195, 96, 0, 32, 189, 232, 240, 129, 111, 240, 21, 0, 189, 232, ++ 240, 129, 20, 32, 187, 247, 68, 252, 0, 40, 232, 209, 245, 231, 0, 0, ++ 19, 181, 0, 35, 4, 70, 0, 147, 33, 70, 0, 104, 25, 74, 255, 247, 204, ++ 255, 1, 70, 88, 187, 212, 248, 120, 4, 3, 34, 22, 75, 5, 240, 243, 252, ++ 1, 70, 24, 187, 212, 248, 120, 4, 2, 34, 19, 75, 5, 240, 235, 252, 1, ++ 70, 216, 185, 212, 248, 120, 4, 5, 34, 16, 75, 5, 240, 227, 252, 1, ++ 70, 152, 185, 212, 248, 120, 4, 6, 34, 13, 75, 5, 240, 219, 252, 1, ++ 70, 88, 185, 212, 248, 120, 4, 8, 34, 10, 75, 5, 240, 211, 252, 0, 40, ++ 20, 191, 79, 240, 255, 48, 0, 32, 1, 224, 79, 240, 255, 48, 28, 189, ++ 213, 162, 129, 0, 45, 202, 129, 0, 37, 45, 130, 0, 121, 47, 130, 0, ++ 193, 255, 129, 0, 253, 250, 129, 0, 2, 104, 16, 181, 210, 248, 176, ++ 2, 0, 35, 14, 224, 4, 104, 161, 66, 9, 209, 1, 105, 11, 177, 25, 97, ++ 1, 224, 194, 248, 176, 18, 187, 247, 236, 251, 0, 32, 16, 189, 3, 70, ++ 0, 105, 0, 40, 238, 209, 111, 240, 29, 0, 16, 189, 65, 242, 228, 67, ++ 152, 66, 8, 209, 0, 35, 6, 74, 154, 90, 138, 66, 5, 208, 2, 51, 179, ++ 245, 140, 127, 247, 209, 0, 32, 112, 71, 1, 32, 112, 71, 0, 191, 120, ++ 157, 5, 0, 45, 233, 240, 67, 208, 248, 56, 83, 0, 33, 135, 176, 4, 70, ++ 79, 244, 146, 114, 40, 70, 179, 243, 166, 247, 100, 35, 235, 133, 3, ++ 35, 133, 248, 96, 48, 0, 34, 1, 35, 212, 248, 92, 1, 79, 244, 128, 81, ++ 255, 243, 159, 247, 255, 40, 7, 70, 5, 209, 35, 106, 24, 105, 25, 104, ++ 222, 247, 111, 250, 7, 70, 35, 106, 111, 134, 0, 33, 164, 248, 70, 116, ++ 32, 70, 7, 244, 96, 87, 179, 248, 8, 128, 30, 104, 218, 243, 1, 243, ++ 183, 245, 32, 95, 5, 241, 56, 9, 8, 208, 183, 245, 192, 95, 7, 208, ++ 183, 245, 128, 95, 20, 191, 10, 39, 20, 39, 2, 224, 160, 39, 0, 224, ++ 40, 39, 0, 33, 255, 35, 141, 232, 10, 0, 212, 248, 116, 52, 2, 144, ++ 3, 151, 27, 121, 66, 70, 4, 147, 72, 70, 51, 70, 233, 247, 29, 249, ++ 35, 104, 147, 248, 79, 48, 154, 7, 3, 208, 235, 136, 67, 240, 32, 3, ++ 235, 128, 7, 176, 189, 232, 240, 131, 130, 176, 16, 181, 20, 36, 97, ++ 67, 208, 248, 184, 66, 3, 147, 99, 80, 5, 155, 96, 24, 67, 96, 6, 155, ++ 2, 97, 131, 96, 4, 155, 195, 96, 189, 232, 16, 64, 2, 176, 112, 71, ++ 0, 0, 48, 181, 3, 104, 4, 70, 219, 105, 133, 176, 154, 109, 64, 104, ++ 212, 248, 36, 22, 219, 109, 249, 247, 180, 251, 196, 248, 32, 6, 0, ++ 40, 0, 240, 198, 129, 32, 70, 3, 240, 132, 255, 196, 248, 208, 5, 0, ++ 40, 0, 240, 193, 129, 32, 70, 5, 240, 188, 251, 196, 248, 120, 4, 0, ++ 40, 0, 240, 188, 129, 32, 70, 3, 240, 254, 248, 196, 248, 40, 1, 0, ++ 40, 0, 240, 183, 129, 32, 70, 7, 240, 34, 248, 196, 248, 36, 1, 0, 40, ++ 0, 240, 178, 129, 32, 70, 4, 240, 134, 250, 196, 248, 124, 6, 0, 40, ++ 0, 240, 173, 129, 32, 70, 4, 240, 228, 253, 196, 248, 140, 6, 0, 40, ++ 0, 240, 168, 129, 32, 70, 4, 240, 72, 252, 0, 40, 64, 240, 165, 129, ++ 32, 70, 4, 240, 164, 252, 0, 40, 64, 240, 159, 129, 32, 70, 4, 240, ++ 204, 252, 0, 40, 64, 240, 153, 129, 32, 70, 4, 240, 42, 253, 0, 40, ++ 64, 240, 147, 129, 32, 70, 4, 240, 96, 253, 0, 40, 64, 240, 141, 129, ++ 32, 70, 4, 240, 118, 253, 5, 70, 0, 40, 64, 240, 134, 129, 3, 33, 212, ++ 248, 140, 6, 10, 70, 4, 240, 170, 254, 196, 248, 164, 6, 0, 40, 0, 240, ++ 126, 129, 212, 248, 140, 6, 2, 33, 42, 70, 4, 240, 159, 254, 196, 248, ++ 168, 6, 0, 40, 0, 240, 118, 129, 41, 70, 193, 74, 193, 75, 32, 70, 0, ++ 149, 1, 148, 7, 240, 14, 248, 191, 75, 26, 29, 7, 202, 27, 104, 141, ++ 232, 7, 0, 8, 33, 34, 70, 32, 70, 255, 247, 92, 255, 32, 104, 5, 240, ++ 142, 255, 32, 70, 6, 240, 25, 252, 196, 248, 104, 4, 0, 40, 0, 240, ++ 91, 129, 32, 70, 6, 240, 91, 252, 196, 248, 108, 4, 0, 40, 0, 240, 85, ++ 129, 32, 70, 6, 240, 233, 252, 196, 248, 112, 4, 0, 40, 0, 240, 79, ++ 129, 32, 70, 1, 240, 121, 254, 196, 248, 8, 5, 0, 40, 0, 240, 73, 129, ++ 169, 75, 32, 70, 196, 248, 88, 49, 1, 240, 242, 253, 196, 248, 48, 1, ++ 0, 40, 0, 240, 64, 129, 32, 70, 1, 240, 160, 251, 196, 248, 52, 1, 0, ++ 40, 0, 240, 71, 129, 32, 70, 1, 240, 10, 253, 196, 248, 56, 1, 0, 40, ++ 0, 240, 65, 129, 32, 70, 1, 240, 146, 252, 0, 40, 64, 240, 62, 129, ++ 32, 70, 7, 240, 28, 248, 196, 248, 96, 1, 0, 40, 0, 240, 57, 129, 32, ++ 70, 6, 240, 26, 254, 196, 248, 80, 8, 0, 40, 0, 240, 51, 129, 32, 104, ++ 33, 70, 162, 104, 144, 75, 3, 240, 235, 252, 196, 248, 124, 2, 0, 40, ++ 0, 240, 42, 129, 32, 70, 3, 240, 207, 249, 196, 248, 100, 1, 0, 40, ++ 0, 240, 36, 129, 137, 75, 32, 70, 196, 248, 44, 49, 5, 240, 98, 248, ++ 196, 248, 72, 1, 0, 40, 0, 240, 27, 129, 32, 70, 7, 240, 134, 251, 196, ++ 248, 76, 1, 0, 40, 0, 240, 21, 129, 32, 70, 5, 240, 224, 249, 196, 248, ++ 80, 1, 0, 40, 0, 240, 16, 129, 32, 70, 2, 240, 236, 248, 196, 248, 68, ++ 1, 0, 40, 0, 240, 10, 129, 35, 104, 1, 34, 131, 248, 164, 32, 32, 70, ++ 3, 240, 6, 255, 196, 248, 132, 6, 0, 40, 0, 240, 0, 129, 32, 70, 7, ++ 240, 40, 248, 0, 40, 64, 240, 252, 128, 32, 70, 4, 240, 64, 255, 196, ++ 248, 84, 1, 0, 40, 0, 240, 246, 128, 32, 70, 4, 240, 90, 254, 0, 40, ++ 64, 240, 242, 128, 32, 70, 0, 240, 90, 254, 196, 248, 116, 1, 0, 40, ++ 0, 240, 236, 128, 32, 70, 3, 240, 186, 251, 196, 248, 124, 1, 0, 40, ++ 0, 240, 230, 128, 32, 70, 6, 240, 196, 252, 196, 248, 128, 1, 0, 40, ++ 0, 240, 225, 128, 32, 70, 7, 240, 120, 251, 196, 248, 120, 1, 0, 40, ++ 0, 240, 220, 128, 32, 70, 0, 240, 210, 253, 196, 248, 136, 1, 0, 40, ++ 0, 240, 214, 128, 32, 70, 3, 240, 78, 251, 196, 248, 140, 1, 0, 40, ++ 0, 240, 208, 128, 32, 70, 7, 240, 38, 252, 196, 248, 152, 1, 0, 40, ++ 0, 240, 202, 128, 32, 70, 0, 240, 136, 254, 196, 248, 144, 1, 0, 40, ++ 0, 240, 196, 128, 32, 70, 7, 240, 216, 251, 196, 248, 160, 1, 0, 40, ++ 0, 240, 190, 128, 32, 70, 6, 240, 44, 255, 196, 248, 228, 6, 0, 40, ++ 0, 240, 184, 128, 32, 70, 5, 240, 120, 248, 196, 248, 100, 6, 0, 40, ++ 0, 240, 178, 128, 32, 70, 4, 240, 52, 254, 196, 248, 104, 6, 0, 40, ++ 0, 240, 172, 128, 32, 70, 7, 240, 214, 248, 196, 248, 188, 6, 0, 40, ++ 0, 240, 166, 128, 35, 104, 1, 34, 131, 248, 166, 32, 32, 70, 0, 240, ++ 20, 255, 196, 248, 136, 6, 0, 40, 0, 240, 156, 128, 32, 70, 3, 240, ++ 4, 254, 196, 248, 184, 6, 0, 40, 0, 240, 150, 128, 32, 70, 3, 240, 190, ++ 252, 196, 248, 192, 6, 0, 40, 0, 240, 144, 128, 32, 70, 6, 240, 86, ++ 250, 196, 248, 200, 6, 0, 40, 0, 240, 138, 128, 32, 70, 3, 240, 30, ++ 248, 196, 248, 164, 1, 0, 40, 0, 240, 132, 128, 32, 70, 5, 240, 162, ++ 248, 196, 248, 220, 6, 0, 40, 12, 191, 118, 32, 0, 32, 122, 224, 79, ++ 244, 150, 112, 119, 224, 64, 242, 45, 16, 116, 224, 79, 244, 151, 112, ++ 113, 224, 64, 242, 47, 16, 110, 224, 79, 244, 152, 112, 107, 224, 64, ++ 242, 49, 16, 104, 224, 79, 244, 153, 112, 101, 224, 64, 242, 65, 16, ++ 98, 224, 64, 242, 71, 16, 95, 224, 79, 244, 164, 112, 92, 224, 36, 32, ++ 90, 224, 37, 32, 88, 224, 38, 32, 86, 224, 42, 32, 84, 224, 49, 32, ++ 82, 224, 0, 191, 153, 48, 130, 0, 101, 48, 130, 0, 104, 157, 5, 0, 239, ++ 190, 173, 222, 69, 253, 129, 0, 239, 190, 173, 13, 50, 32, 67, 224, ++ 64, 242, 245, 16, 64, 224, 79, 244, 251, 112, 61, 224, 53, 32, 59, 224, ++ 189, 32, 57, 224, 57, 32, 55, 224, 60, 32, 53, 224, 62, 32, 51, 224, ++ 64, 242, 109, 32, 48, 224, 63, 32, 46, 224, 67, 32, 44, 224, 106, 32, ++ 42, 224, 71, 32, 40, 224, 73, 32, 38, 224, 72, 32, 36, 224, 74, 32, ++ 34, 224, 64, 242, 229, 32, 31, 224, 64, 242, 230, 32, 28, 224, 75, 32, ++ 26, 224, 90, 32, 24, 224, 91, 32, 22, 224, 94, 32, 20, 224, 95, 32, ++ 18, 224, 99, 32, 16, 224, 101, 32, 14, 224, 8, 72, 12, 224, 103, 32, ++ 10, 224, 108, 32, 8, 224, 110, 32, 6, 224, 111, 32, 4, 224, 112, 32, ++ 2, 224, 114, 32, 0, 224, 115, 32, 5, 176, 48, 189, 80, 70, 77, 0, 248, ++ 181, 4, 70, 0, 40, 0, 240, 166, 128, 220, 243, 91, 244, 212, 248, 220, ++ 21, 208, 241, 1, 6, 56, 191, 0, 38, 33, 177, 160, 104, 201, 243, 63, ++ 241, 0, 185, 1, 54, 32, 70, 212, 248, 16, 19, 212, 243, 50, 246, 32, ++ 70, 212, 248, 204, 20, 212, 243, 45, 246, 32, 70, 212, 248, 24, 19, ++ 212, 243, 40, 246, 212, 248, 36, 3, 8, 177, 187, 247, 226, 248, 212, ++ 248, 124, 2, 32, 177, 3, 240, 168, 251, 0, 35, 196, 248, 124, 50, 39, ++ 106, 185, 105, 17, 177, 32, 70, 26, 240, 177, 216, 0, 37, 189, 97, 212, ++ 248, 104, 50, 89, 89, 17, 177, 32, 70, 247, 243, 130, 244, 4, 53, 32, ++ 45, 245, 209, 212, 248, 92, 1, 3, 240, 223, 248, 32, 70, 254, 247, 245, ++ 255, 212, 248, 8, 5, 32, 177, 1, 240, 95, 252, 0, 35, 196, 248, 8, 53, ++ 32, 70, 255, 247, 48, 248, 32, 70, 2, 240, 142, 250, 35, 104, 134, 25, ++ 211, 248, 216, 16, 49, 177, 96, 104, 2, 240, 129, 250, 35, 104, 0, 34, ++ 195, 248, 216, 32, 35, 104, 211, 248, 220, 0, 40, 177, 187, 247, 161, ++ 248, 35, 104, 0, 34, 195, 248, 220, 32, 212, 248, 180, 82, 4, 224, 40, ++ 70, 239, 104, 187, 247, 150, 248, 61, 70, 0, 45, 248, 209, 33, 70, 196, ++ 248, 180, 82, 32, 104, 255, 247, 144, 252, 32, 104, 24, 73, 34, 70, ++ 255, 247, 108, 251, 212, 248, 104, 1, 24, 177, 6, 240, 64, 253, 196, ++ 248, 104, 81, 212, 248, 128, 2, 32, 177, 187, 247, 124, 248, 0, 35, ++ 196, 248, 128, 50, 212, 248, 232, 4, 72, 177, 187, 247, 116, 248, 0, ++ 35, 196, 248, 232, 52, 3, 224, 32, 70, 97, 104, 224, 243, 97, 241, 212, ++ 248, 120, 34, 0, 42, 247, 209, 4, 245, 196, 96, 4, 48, 249, 247, 70, ++ 248, 32, 70, 97, 104, 1, 240, 161, 248, 0, 224, 6, 70, 48, 70, 248, ++ 189, 150, 51, 4, 0, 45, 233, 240, 79, 145, 176, 0, 36, 145, 70, 27, ++ 158, 157, 248, 104, 32, 7, 144, 221, 248, 120, 160, 32, 70, 9, 145, ++ 152, 70, 8, 146, 221, 248, 128, 176, 12, 148, 13, 148, 14, 148, 185, ++ 247, 120, 249, 72, 70, 49, 70, 28, 154, 29, 155, 205, 248, 0, 160, 11, ++ 240, 225, 250, 5, 70, 8, 177, 1, 35, 165, 227, 254, 247, 216, 254, 13, ++ 171, 1, 147, 14, 171, 2, 147, 72, 70, 49, 70, 28, 154, 29, 155, 205, ++ 248, 0, 160, 2, 240, 250, 249, 7, 70, 24, 185, 1, 35, 12, 147, 4, 70, ++ 183, 227, 13, 152, 72, 177, 170, 73, 180, 243, 121, 242, 40, 177, 41, ++ 70, 42, 70, 185, 247, 74, 248, 31, 250, 128, 249, 31, 155, 48, 70, 0, ++ 147, 65, 70, 12, 170, 75, 70, 1, 240, 132, 248, 4, 70, 0, 40, 0, 240, ++ 184, 131, 5, 104, 14, 154, 70, 96, 13, 155, 197, 248, 224, 32, 208, ++ 248, 116, 36, 255, 33, 197, 248, 216, 112, 197, 248, 220, 48, 130, 248, ++ 96, 16, 66, 106, 0, 35, 194, 97, 7, 154, 13, 147, 130, 96, 150, 74, ++ 197, 248, 12, 128, 197, 248, 168, 32, 110, 97, 14, 147, 1, 34, 128, ++ 248, 42, 38, 208, 248, 196, 34, 192, 248, 168, 161, 99, 243, 23, 34, ++ 192, 248, 196, 34, 8, 154, 65, 70, 133, 248, 33, 32, 128, 248, 211, ++ 49, 3, 35, 128, 248, 49, 53, 255, 247, 4, 250, 35, 104, 4, 245, 196, ++ 98, 219, 105, 96, 104, 25, 110, 4, 50, 248, 247, 118, 255, 7, 70, 0, ++ 40, 64, 240, 97, 131, 32, 70, 57, 70, 211, 243, 75, 247, 32, 70, 7, ++ 153, 50, 70, 67, 70, 6, 240, 225, 251, 196, 248, 104, 1, 8, 185, 15, ++ 35, 43, 227, 122, 75, 40, 70, 141, 232, 136, 0, 121, 75, 122, 73, 4, ++ 147, 122, 75, 122, 74, 5, 147, 35, 70, 2, 151, 3, 151, 255, 247, 237, ++ 250, 8, 177, 16, 35, 25, 227, 8, 155, 28, 154, 141, 232, 72, 0, 29, ++ 155, 2, 146, 3, 147, 32, 70, 9, 153, 74, 70, 67, 70, 205, 248, 16, 160, ++ 2, 240, 99, 250, 12, 144, 0, 40, 64, 240, 45, 131, 35, 105, 216, 111, ++ 254, 247, 216, 250, 164, 248, 40, 6, 180, 248, 174, 1, 194, 247, 111, ++ 252, 0, 48, 24, 191, 1, 32, 10, 48, 84, 248, 32, 48, 10, 169, 35, 98, ++ 32, 105, 245, 243, 134, 246, 0, 40, 61, 209, 10, 155, 7, 70, 196, 248, ++ 180, 49, 57, 70, 15, 170, 32, 70, 211, 243, 23, 244, 57, 70, 32, 70, ++ 189, 248, 60, 32, 1, 55, 211, 243, 20, 244, 6, 47, 241, 209, 79, 244, ++ 0, 115, 197, 248, 236, 48, 42, 35, 197, 248, 188, 48, 50, 35, 197, 248, ++ 192, 48, 54, 35, 79, 244, 125, 98, 197, 248, 200, 48, 64, 242, 212, ++ 83, 165, 248, 206, 32, 165, 248, 196, 48, 79, 244, 93, 114, 0, 35, 133, ++ 248, 187, 112, 165, 248, 204, 32, 132, 248, 132, 55, 213, 248, 188, ++ 48, 132, 43, 2, 217, 132, 35, 197, 248, 188, 48, 79, 244, 4, 112, 186, ++ 247, 67, 255, 196, 248, 128, 2, 8, 185, 20, 35, 175, 226, 79, 244, 4, ++ 114, 0, 33, 179, 243, 31, 243, 34, 70, 0, 35, 210, 248, 132, 2, 212, ++ 248, 128, 18, 4, 50, 65, 248, 35, 0, 212, 248, 128, 18, 81, 248, 35, ++ 16, 139, 113, 1, 51, 4, 43, 240, 209, 1, 35, 133, 248, 147, 48, 35, ++ 106, 24, 105, 222, 247, 191, 250, 0, 240, 1, 0, 133, 248, 84, 0, 35, ++ 106, 24, 105, 222, 247, 183, 250, 192, 243, 192, 0, 133, 248, 85, 0, ++ 41, 70, 32, 70, 6, 240, 137, 254, 43, 73, 213, 248, 220, 0, 180, 243, ++ 70, 241, 213, 248, 216, 32, 64, 242, 110, 81, 147, 106, 7, 70, 139, ++ 66, 8, 208, 18, 107, 65, 242, 107, 1, 138, 66, 90, 209, 209, 43, 1, ++ 208, 233, 43, 18, 209, 212, 248, 116, 52, 25, 34, 131, 248, 73, 32, ++ 212, 248, 116, 52, 79, 240, 255, 50, 90, 100, 100, 34, 131, 248, 122, ++ 32, 212, 248, 116, 52, 1, 34, 131, 248, 48, 32, 89, 224, 179, 245, 137, ++ 127, 17, 216, 179, 245, 136, 127, 50, 216, 245, 43, 7, 216, 244, 43, ++ 46, 210, 228, 43, 44, 208, 239, 43, 42, 208, 214, 43, 39, 224, 163, ++ 245, 135, 115, 1, 43, 69, 216, 35, 224, 179, 245, 154, 127, 23, 210, ++ 179, 245, 152, 127, 29, 216, 64, 242, 23, 18, 147, 66, 24, 224, 0, 191, ++ 144, 158, 5, 0, 95, 98, 45, 7, 229, 91, 130, 0, 64, 52, 4, 0, 216, 182, ++ 135, 0, 117, 73, 1, 0, 150, 51, 4, 0, 155, 158, 5, 0, 179, 245, 154, ++ 127, 38, 217, 179, 245, 155, 127, 2, 217, 179, 245, 165, 127, 32, 209, ++ 212, 248, 116, 52, 50, 34, 131, 248, 122, 32, 212, 248, 116, 52, 100, ++ 34, 131, 248, 73, 32, 16, 224, 65, 242, 228, 65, 138, 66, 17, 209, 64, ++ 242, 218, 82, 147, 66, 13, 209, 212, 248, 116, 36, 100, 35, 130, 248, ++ 122, 48, 212, 248, 116, 36, 130, 248, 73, 48, 212, 248, 116, 52, 79, ++ 240, 255, 50, 90, 100, 212, 248, 116, 52, 100, 34, 163, 248, 74, 32, ++ 163, 248, 76, 32, 80, 34, 163, 248, 146, 32, 255, 34, 163, 248, 150, ++ 32, 163, 248, 154, 32, 40, 34, 163, 248, 148, 32, 100, 34, 163, 248, ++ 152, 32, 163, 248, 156, 32, 80, 34, 163, 248, 158, 32, 255, 34, 163, ++ 248, 162, 32, 163, 248, 166, 32, 40, 34, 163, 248, 160, 32, 100, 34, ++ 163, 248, 164, 32, 163, 248, 168, 32, 79, 240, 1, 9, 25, 34, 163, 248, ++ 170, 32, 163, 248, 144, 144, 32, 70, 6, 240, 245, 252, 212, 248, 116, ++ 52, 34, 106, 25, 120, 16, 105, 218, 120, 222, 247, 74, 252, 212, 248, ++ 96, 54, 131, 248, 52, 144, 225, 105, 32, 105, 4, 49, 3, 240, 231, 251, ++ 35, 106, 212, 248, 116, 164, 24, 105, 222, 247, 91, 252, 202, 248, 64, ++ 0, 4, 245, 230, 122, 32, 105, 81, 70, 245, 243, 46, 240, 6, 34, 40, ++ 29, 81, 70, 177, 247, 159, 254, 35, 106, 24, 105, 222, 247, 211, 249, ++ 195, 5, 4, 213, 35, 104, 195, 248, 64, 145, 131, 248, 61, 145, 180, ++ 248, 174, 1, 194, 247, 14, 251, 0, 48, 24, 191, 1, 32, 10, 48, 84, 248, ++ 32, 48, 32, 70, 35, 98, 254, 247, 108, 255, 8, 185, 24, 35, 142, 225, ++ 33, 106, 15, 35, 64, 242, 255, 50, 161, 248, 8, 49, 161, 248, 10, 33, ++ 1, 245, 128, 115, 1, 241, 252, 2, 32, 70, 1, 240, 34, 252, 35, 106, ++ 211, 248, 252, 32, 195, 248, 248, 32, 195, 248, 240, 32, 211, 248, 0, ++ 33, 195, 248, 244, 32, 26, 104, 2, 42, 1, 209, 1, 34, 90, 117, 7, 240, ++ 1, 3, 0, 43, 12, 191, 3, 35, 0, 35, 133, 248, 79, 48, 35, 106, 24, 105, ++ 222, 247, 144, 249, 16, 244, 0, 96, 35, 104, 6, 208, 147, 248, 79, 32, ++ 2, 177, 1, 34, 131, 248, 81, 32, 1, 224, 131, 248, 81, 0, 33, 106, 32, ++ 70, 28, 49, 213, 243, 4, 241, 0, 33, 32, 70, 212, 248, 32, 144, 217, ++ 243, 62, 245, 0, 34, 127, 35, 9, 241, 80, 1, 0, 147, 1, 144, 19, 70, ++ 9, 241, 28, 0, 232, 247, 241, 250, 32, 70, 238, 247, 241, 255, 64, 242, ++ 204, 99, 196, 248, 16, 54, 32, 70, 255, 247, 105, 250, 12, 144, 0, 40, ++ 64, 240, 89, 129, 212, 248, 112, 4, 2, 33, 157, 249, 44, 32, 21, 240, ++ 88, 217, 32, 70, 65, 70, 254, 247, 156, 255, 16, 185, 79, 244, 122, ++ 115, 35, 225, 32, 70, 2, 240, 241, 253, 196, 248, 92, 1, 16, 185, 64, ++ 242, 233, 51, 26, 225, 32, 70, 255, 247, 218, 249, 32, 70, 49, 70, 223, ++ 243, 122, 246, 16, 185, 64, 242, 235, 51, 15, 225, 196, 248, 164, 5, ++ 196, 248, 168, 5, 49, 70, 32, 70, 223, 243, 110, 246, 16, 185, 79, 244, ++ 123, 115, 3, 225, 1, 35, 196, 248, 172, 5, 133, 248, 172, 48, 32, 70, ++ 2, 240, 218, 251, 16, 177, 64, 242, 237, 51, 247, 224, 6, 35, 165, 248, ++ 96, 48, 165, 248, 98, 48, 149, 248, 156, 48, 1, 43, 4, 209, 64, 34, ++ 165, 248, 96, 32, 165, 248, 98, 32, 213, 248, 136, 48, 10, 34, 26, 128, ++ 79, 244, 84, 114, 90, 128, 213, 248, 140, 48, 1, 38, 196, 34, 30, 128, ++ 90, 128, 212, 248, 48, 1, 230, 243, 65, 243, 8, 177, 132, 248, 18, 98, ++ 180, 248, 197, 50, 67, 244, 192, 83, 67, 240, 30, 3, 164, 248, 197, ++ 50, 35, 106, 24, 105, 222, 247, 246, 248, 192, 6, 7, 213, 212, 248, ++ 116, 52, 1, 34, 154, 116, 212, 248, 116, 52, 255, 34, 218, 116, 180, ++ 248, 197, 34, 79, 242, 255, 115, 19, 64, 212, 248, 116, 36, 164, 248, ++ 197, 50, 210, 120, 1, 42, 7, 209, 35, 244, 0, 99, 35, 240, 12, 3, 27, ++ 4, 27, 12, 164, 248, 197, 50, 255, 38, 2, 33, 1, 34, 132, 248, 196, ++ 98, 132, 248, 195, 98, 132, 248, 194, 98, 32, 70, 210, 243, 18, 244, ++ 1, 33, 50, 70, 32, 70, 210, 243, 13, 244, 35, 106, 79, 240, 255, 56, ++ 196, 248, 24, 130, 24, 105, 222, 247, 191, 248, 16, 240, 4, 6, 32, 70, ++ 5, 208, 3, 33, 206, 243, 250, 240, 132, 248, 32, 130, 4, 224, 49, 70, ++ 206, 243, 244, 240, 132, 248, 32, 98, 35, 106, 24, 105, 222, 247, 172, ++ 248, 57, 7, 2, 213, 0, 35, 132, 248, 32, 50, 250, 6, 3, 213, 32, 70, ++ 0, 33, 206, 243, 227, 240, 187, 7, 14, 213, 162, 106, 0, 35, 130, 248, ++ 77, 48, 226, 106, 130, 248, 77, 48, 180, 248, 197, 50, 35, 240, 128, ++ 3, 27, 4, 27, 12, 164, 248, 197, 50, 126, 7, 3, 213, 32, 70, 0, 33, ++ 238, 247, 26, 248, 56, 6, 7, 213, 180, 248, 197, 50, 35, 240, 16, 3, ++ 27, 4, 27, 12, 164, 248, 197, 50, 149, 248, 66, 48, 163, 177, 149, 248, ++ 67, 48, 139, 177, 23, 240, 96, 15, 14, 208, 7, 240, 32, 1, 209, 241, ++ 1, 1, 7, 240, 64, 2, 56, 191, 0, 33, 210, 241, 1, 2, 32, 70, 56, 191, ++ 0, 34, 0, 240, 254, 254, 180, 248, 174, 1, 194, 247, 170, 249, 0, 48, ++ 24, 191, 1, 32, 0, 241, 10, 6, 84, 248, 38, 112, 212, 248, 108, 18, ++ 32, 70, 56, 74, 59, 70, 25, 240, 86, 220, 184, 97, 84, 248, 38, 16, ++ 136, 105, 16, 185, 64, 242, 76, 67, 33, 224, 80, 49, 40, 34, 76, 48, ++ 177, 247, 17, 253, 20, 32, 183, 243, 154, 246, 196, 248, 28, 7, 16, ++ 185, 64, 242, 77, 67, 19, 224, 171, 109, 32, 70, 67, 240, 4, 3, 171, ++ 101, 220, 243, 11, 240, 32, 70, 255, 247, 88, 248, 16, 177, 79, 244, ++ 250, 99, 5, 224, 32, 70, 2, 240, 231, 254, 24, 177, 64, 242, 209, 115, ++ 12, 147, 35, 224, 35, 104, 33, 73, 211, 248, 220, 0, 179, 243, 228, ++ 246, 112, 177, 3, 70, 24, 70, 19, 248, 1, 43, 26, 177, 28, 73, 138, ++ 92, 81, 7, 247, 213, 0, 33, 10, 34, 184, 247, 172, 252, 196, 248, 108, ++ 6, 160, 104, 0, 33, 200, 243, 62, 245, 1, 35, 132, 248, 152, 55, 187, ++ 241, 0, 15, 23, 208, 0, 35, 203, 248, 0, 48, 19, 224, 13, 152, 32, 177, ++ 186, 247, 103, 252, 0, 35, 13, 147, 14, 147, 20, 177, 32, 70, 255, 247, ++ 87, 251, 187, 241, 0, 15, 4, 208, 12, 155, 0, 36, 203, 248, 0, 48, 0, ++ 224, 92, 70, 32, 70, 17, 176, 189, 232, 240, 143, 48, 70, 57, 70, 1, ++ 240, 37, 254, 226, 231, 0, 191, 132, 53, 4, 0, 94, 157, 5, 0, 22, 119, ++ 135, 0, 56, 181, 4, 70, 112, 177, 5, 104, 33, 70, 40, 104, 255, 247, ++ 66, 248, 40, 104, 5, 73, 34, 70, 254, 247, 30, 255, 32, 70, 189, 232, ++ 56, 64, 186, 247, 53, 188, 56, 189, 0, 191, 138, 53, 4, 0, 112, 181, ++ 6, 106, 142, 176, 5, 70, 56, 32, 183, 243, 25, 246, 4, 70, 0, 40, 49, ++ 208, 28, 75, 5, 96, 0, 147, 0, 35, 1, 147, 2, 147, 3, 147, 26, 75, 26, ++ 73, 4, 147, 26, 75, 27, 74, 5, 147, 40, 104, 35, 70, 254, 247, 85, 255, ++ 248, 185, 24, 75, 33, 70, 0, 147, 40, 104, 23, 74, 2, 35, 254, 247, ++ 159, 255, 5, 70, 168, 185, 41, 70, 28, 34, 4, 241, 11, 0, 178, 243, ++ 232, 247, 48, 105, 49, 104, 7, 170, 221, 247, 153, 250, 35, 70, 7, 170, ++ 217, 122, 170, 92, 1, 53, 10, 67, 218, 114, 1, 51, 28, 45, 246, 209, ++ 3, 224, 32, 70, 255, 247, 171, 255, 0, 36, 32, 70, 14, 176, 112, 189, ++ 0, 191, 57, 12, 131, 0, 144, 53, 4, 0, 108, 194, 135, 0, 213, 148, 1, ++ 0, 138, 53, 4, 0, 92, 194, 135, 0, 241, 11, 131, 0, 56, 181, 4, 70, ++ 112, 177, 5, 104, 33, 70, 40, 104, 254, 247, 218, 255, 40, 104, 5, 73, ++ 34, 70, 254, 247, 182, 254, 32, 70, 189, 232, 56, 64, 186, 247, 205, ++ 187, 56, 189, 0, 191, 180, 53, 4, 0, 48, 181, 5, 70, 135, 176, 12, 32, ++ 183, 243, 178, 245, 4, 70, 0, 40, 63, 208, 0, 35, 5, 96, 1, 33, 0, 147, ++ 1, 144, 32, 74, 40, 70, 32, 75, 2, 240, 207, 249, 0, 40, 96, 96, 50, ++ 219, 30, 75, 213, 248, 124, 6, 141, 232, 24, 0, 5, 33, 33, 34, 28, 75, ++ 3, 240, 240, 249, 56, 187, 27, 75, 213, 248, 124, 6, 141, 232, 24, 0, ++ 5, 33, 36, 34, 24, 75, 3, 240, 229, 249, 224, 185, 23, 75, 1, 144, 0, ++ 147, 2, 144, 3, 144, 4, 144, 5, 144, 21, 73, 40, 104, 21, 74, 35, 70, ++ 254, 247, 207, 254, 112, 185, 19, 75, 40, 104, 0, 147, 33, 70, 18, 74, ++ 3, 35, 254, 247, 25, 255, 40, 185, 42, 104, 1, 35, 163, 96, 130, 248, ++ 173, 48, 3, 224, 32, 70, 255, 247, 158, 255, 0, 36, 32, 70, 7, 176, ++ 48, 189, 185, 16, 131, 0, 181, 16, 131, 0, 33, 150, 1, 0, 189, 16, 131, ++ 0, 125, 19, 131, 0, 221, 16, 131, 0, 221, 17, 131, 0, 168, 194, 135, ++ 0, 180, 53, 4, 0, 144, 194, 135, 0, 97, 17, 131, 0, 48, 181, 5, 70, ++ 135, 176, 0, 40, 109, 208, 8, 32, 183, 243, 74, 245, 4, 70, 0, 40, 104, ++ 208, 0, 35, 5, 96, 20, 33, 0, 147, 1, 144, 53, 74, 40, 70, 53, 75, 2, ++ 240, 103, 249, 0, 40, 96, 96, 94, 219, 51, 75, 79, 244, 152, 113, 141, ++ 232, 24, 0, 107, 34, 213, 248, 124, 6, 48, 75, 3, 240, 135, 249, 0, ++ 40, 81, 209, 47, 75, 5, 33, 141, 232, 24, 0, 107, 34, 213, 248, 124, ++ 6, 44, 75, 3, 240, 123, 249, 0, 40, 69, 209, 43, 75, 79, 244, 144, 113, ++ 141, 232, 24, 0, 108, 34, 213, 248, 124, 6, 40, 75, 3, 240, 110, 249, ++ 0, 40, 56, 209, 38, 75, 79, 244, 144, 113, 141, 232, 24, 0, 111, 34, ++ 213, 248, 124, 6, 35, 75, 3, 240, 97, 249, 0, 40, 43, 209, 34, 75, 10, ++ 33, 141, 232, 24, 0, 110, 34, 213, 248, 124, 6, 31, 75, 3, 240, 85, ++ 249, 0, 40, 31, 209, 0, 149, 213, 248, 124, 6, 10, 33, 110, 34, 27, ++ 75, 3, 240, 59, 251, 176, 185, 26, 75, 1, 144, 0, 147, 2, 144, 3, 144, ++ 4, 144, 5, 144, 40, 104, 23, 73, 24, 74, 35, 70, 254, 247, 53, 254, ++ 64, 185, 43, 104, 1, 34, 131, 248, 176, 32, 0, 224, 4, 70, 32, 70, 7, ++ 176, 48, 189, 32, 70, 186, 247, 233, 250, 0, 36, 247, 231, 15, 151, ++ 1, 0, 239, 150, 1, 0, 249, 26, 131, 0, 33, 151, 1, 0, 217, 26, 131, ++ 0, 5, 25, 131, 0, 25, 27, 131, 0, 65, 25, 131, 0, 133, 27, 131, 0, 129, ++ 25, 131, 0, 177, 27, 131, 0, 173, 25, 131, 0, 205, 24, 131, 0, 217, ++ 25, 131, 0, 192, 194, 135, 0, 184, 53, 4, 0, 16, 181, 4, 70, 80, 177, ++ 3, 104, 5, 73, 24, 104, 34, 70, 254, 247, 162, 253, 32, 70, 189, 232, ++ 16, 64, 186, 247, 185, 186, 16, 189, 0, 191, 184, 53, 4, 0, 16, 181, ++ 4, 70, 80, 177, 3, 104, 5, 73, 24, 104, 34, 70, 254, 247, 144, 253, ++ 32, 70, 189, 232, 16, 64, 186, 247, 167, 186, 16, 189, 0, 191, 171, ++ 158, 5, 0, 112, 181, 5, 70, 134, 176, 8, 32, 186, 247, 154, 250, 4, ++ 70, 0, 40, 0, 240, 161, 128, 83, 75, 5, 96, 79, 244, 144, 113, 0, 147, ++ 1, 144, 48, 34, 213, 248, 124, 6, 80, 75, 3, 240, 212, 248, 0, 40, 64, ++ 240, 146, 128, 78, 75, 213, 248, 124, 6, 141, 232, 24, 0, 79, 244, 144, ++ 113, 160, 34, 75, 75, 3, 240, 82, 249, 0, 40, 64, 240, 132, 128, 73, ++ 75, 213, 248, 124, 6, 141, 232, 24, 0, 79, 244, 144, 113, 196, 34, 70, ++ 75, 3, 240, 68, 249, 0, 40, 118, 209, 68, 75, 213, 248, 124, 6, 141, ++ 232, 24, 0, 5, 33, 48, 34, 66, 75, 3, 240, 172, 248, 0, 40, 106, 209, ++ 64, 75, 213, 248, 124, 6, 141, 232, 24, 0, 5, 33, 160, 34, 62, 75, 3, ++ 240, 44, 249, 0, 40, 94, 209, 60, 75, 213, 248, 124, 6, 141, 232, 24, ++ 0, 5, 33, 196, 34, 58, 75, 3, 240, 32, 249, 0, 40, 82, 209, 213, 248, ++ 124, 6, 5, 33, 48, 34, 54, 75, 0, 148, 3, 240, 122, 250, 0, 40, 72, ++ 209, 213, 248, 124, 6, 5, 33, 160, 34, 50, 75, 0, 148, 3, 240, 246, ++ 250, 0, 40, 62, 209, 213, 248, 124, 6, 5, 33, 196, 34, 46, 75, 0, 148, ++ 3, 240, 236, 250, 0, 40, 52, 209, 213, 248, 124, 6, 192, 33, 48, 34, ++ 42, 75, 0, 148, 3, 240, 92, 250, 88, 187, 213, 248, 124, 6, 192, 33, ++ 160, 34, 39, 75, 0, 148, 3, 240, 217, 250, 16, 187, 213, 248, 124, 6, ++ 128, 33, 48, 34, 35, 75, 0, 148, 3, 240, 6, 249, 6, 70, 192, 185, 141, ++ 232, 17, 0, 1, 33, 40, 70, 31, 74, 32, 75, 2, 240, 34, 248, 0, 40, 96, ++ 96, 13, 219, 30, 75, 40, 104, 141, 232, 72, 0, 29, 73, 29, 74, 35, 70, ++ 2, 150, 3, 150, 4, 150, 5, 150, 254, 247, 56, 253, 24, 177, 32, 70, ++ 255, 247, 64, 255, 0, 36, 32, 70, 6, 176, 112, 189, 209, 44, 131, 0, ++ 193, 43, 131, 0, 253, 44, 131, 0, 237, 43, 131, 0, 165, 44, 131, 0, ++ 161, 43, 131, 0, 189, 42, 131, 0, 253, 39, 131, 0, 233, 42, 131, 0, ++ 41, 40, 131, 0, 145, 42, 131, 0, 221, 39, 131, 0, 69, 41, 131, 0, 113, ++ 41, 131, 0, 225, 40, 131, 0, 249, 47, 131, 0, 17, 48, 131, 0, 81, 44, ++ 131, 0, 85, 45, 131, 0, 81, 45, 131, 0, 117, 46, 131, 0, 124, 195, 135, ++ 0, 171, 158, 5, 0, 79, 244, 240, 98, 130, 96, 16, 34, 194, 96, 66, 98, ++ 192, 248, 184, 32, 128, 34, 66, 99, 24, 34, 130, 99, 2, 100, 2, 101, ++ 29, 34, 45, 233, 240, 65, 194, 101, 11, 37, 5, 34, 64, 36, 10, 33, 69, ++ 97, 133, 97, 2, 102, 4, 37, 79, 244, 240, 114, 32, 35, 8, 38, 4, 96, ++ 192, 248, 176, 64, 1, 97, 193, 97, 133, 98, 1, 33, 79, 244, 128, 101, ++ 196, 98, 79, 240, 20, 12, 9, 36, 17, 39, 130, 102, 79, 240, 39, 8, 3, ++ 34, 67, 96, 192, 248, 180, 48, 1, 98, 65, 102, 193, 100, 67, 101, 132, ++ 103, 192, 248, 48, 192, 198, 99, 135, 101, 197, 102, 5, 103, 66, 103, ++ 192, 248, 124, 128, 192, 248, 164, 16, 176, 33, 192, 248, 192, 16, 72, ++ 33, 192, 248, 196, 16, 96, 33, 192, 248, 132, 64, 192, 248, 136, 64, ++ 192, 248, 200, 16, 2, 36, 48, 33, 192, 248, 224, 48, 192, 248, 240, ++ 48, 211, 35, 79, 240, 18, 8, 192, 248, 140, 64, 192, 248, 144, 64, 192, ++ 248, 156, 64, 192, 248, 160, 64, 192, 248, 204, 16, 79, 244, 250, 100, ++ 6, 33, 192, 248, 244, 48, 0, 35, 192, 248, 128, 128, 192, 248, 148, ++ 192, 192, 248, 152, 32, 192, 248, 168, 32, 192, 248, 172, 96, 192, 248, ++ 208, 16, 192, 248, 212, 112, 192, 248, 216, 64, 192, 248, 220, 96, 192, ++ 248, 232, 16, 192, 248, 228, 80, 192, 248, 252, 48, 192, 248, 248, 32, ++ 189, 232, 240, 129, 1, 32, 112, 71, 112, 71, 56, 181, 4, 70, 208, 248, ++ 16, 3, 32, 177, 186, 247, 52, 249, 0, 35, 196, 248, 16, 51, 212, 248, ++ 24, 3, 32, 177, 186, 247, 44, 249, 0, 35, 196, 248, 24, 51, 212, 248, ++ 4, 7, 48, 177, 35, 104, 35, 177, 186, 247, 34, 249, 0, 35, 196, 248, ++ 4, 55, 212, 248, 168, 2, 24, 177, 35, 104, 11, 177, 186, 247, 24, 249, ++ 212, 248, 172, 2, 0, 37, 196, 248, 168, 82, 40, 177, 35, 104, 27, 177, ++ 186, 247, 14, 249, 196, 248, 172, 82, 212, 248, 104, 2, 8, 177, 186, ++ 247, 7, 249, 212, 248, 56, 3, 0, 37, 196, 248, 104, 82, 24, 177, 186, ++ 247, 255, 248, 196, 248, 56, 83, 212, 248, 248, 2, 32, 177, 186, 247, ++ 248, 248, 0, 35, 196, 248, 248, 50, 212, 248, 184, 2, 8, 177, 186, 247, ++ 240, 248, 0, 37, 99, 25, 211, 248, 132, 50, 211, 248, 224, 0, 8, 177, ++ 186, 247, 231, 248, 4, 53, 16, 45, 244, 209, 212, 248, 132, 2, 8, 177, ++ 186, 247, 223, 248, 212, 248, 116, 4, 32, 177, 186, 247, 218, 248, 0, ++ 35, 196, 248, 116, 52, 212, 248, 204, 4, 32, 177, 186, 247, 210, 248, ++ 0, 35, 196, 248, 204, 52, 212, 248, 24, 5, 32, 177, 186, 247, 202, 248, ++ 0, 35, 196, 248, 24, 53, 56, 189, 16, 181, 12, 70, 209, 177, 200, 105, ++ 24, 177, 186, 247, 191, 248, 0, 35, 227, 97, 212, 248, 136, 0, 32, 177, ++ 186, 247, 184, 248, 0, 35, 196, 248, 136, 48, 212, 248, 140, 0, 32, ++ 177, 186, 247, 176, 248, 0, 35, 196, 248, 140, 48, 32, 70, 189, 232, ++ 16, 64, 186, 247, 168, 184, 16, 189, 112, 181, 4, 70, 79, 244, 182, ++ 112, 22, 70, 183, 243, 143, 242, 5, 70, 168, 177, 79, 244, 128, 112, ++ 183, 243, 137, 242, 232, 97, 120, 177, 49, 70, 255, 247, 210, 254, 79, ++ 244, 84, 112, 183, 243, 128, 242, 197, 248, 136, 0, 40, 177, 196, 32, ++ 183, 243, 122, 242, 197, 248, 140, 0, 32, 185, 41, 70, 32, 70, 255, ++ 247, 190, 255, 0, 37, 40, 70, 112, 189, 45, 233, 240, 65, 29, 70, 0, ++ 38, 3, 104, 192, 248, 168, 98, 147, 248, 184, 48, 4, 70, 56, 32, 88, ++ 67, 183, 243, 98, 242, 196, 248, 168, 2, 0, 40, 86, 208, 35, 104, 147, ++ 248, 184, 0, 128, 0, 183, 243, 88, 242, 196, 248, 172, 2, 16, 185, 64, ++ 242, 245, 51, 149, 224, 79, 244, 2, 112, 183, 243, 78, 242, 196, 248, ++ 4, 7, 0, 40, 0, 240, 150, 128, 196, 248, 104, 98, 32, 32, 183, 243, ++ 68, 242, 196, 248, 104, 2, 16, 185, 79, 244, 126, 115, 129, 224, 79, ++ 244, 146, 112, 183, 243, 58, 242, 196, 248, 56, 3, 16, 185, 64, 242, ++ 242, 51, 119, 224, 79, 244, 174, 112, 183, 243, 48, 242, 196, 248, 116, ++ 4, 16, 185, 64, 242, 249, 51, 109, 224, 128, 32, 102, 106, 183, 243, ++ 38, 242, 176, 98, 16, 185, 64, 242, 3, 67, 100, 224, 79, 244, 132, 112, ++ 183, 243, 29, 242, 196, 248, 16, 3, 16, 185, 64, 242, 239, 51, 90, 224, ++ 79, 244, 132, 112, 183, 243, 19, 242, 196, 248, 24, 3, 16, 185, 79, ++ 244, 124, 115, 80, 224, 18, 32, 183, 243, 10, 242, 196, 248, 248, 2, ++ 16, 185, 79, 244, 125, 115, 71, 224, 180, 32, 183, 243, 1, 242, 196, ++ 248, 184, 2, 16, 185, 64, 242, 246, 51, 62, 224, 79, 244, 100, 112, ++ 183, 243, 247, 241, 196, 248, 132, 2, 240, 177, 0, 241, 228, 3, 196, ++ 248, 136, 50, 0, 245, 228, 115, 0, 245, 43, 112, 196, 248, 140, 50, ++ 196, 248, 144, 2, 38, 70, 4, 241, 16, 7, 35, 104, 214, 248, 132, 130, ++ 219, 105, 211, 248, 212, 0, 64, 1, 183, 243, 220, 241, 200, 248, 224, ++ 0, 214, 248, 132, 50, 211, 248, 224, 0, 16, 185, 64, 242, 247, 51, 21, ++ 224, 4, 54, 190, 66, 233, 209, 79, 244, 132, 112, 183, 243, 203, 241, ++ 196, 248, 204, 4, 16, 185, 64, 242, 251, 51, 8, 224, 79, 244, 134, 112, ++ 183, 243, 193, 241, 196, 248, 24, 5, 32, 185, 64, 242, 255, 51, 43, ++ 96, 189, 232, 240, 129, 56, 32, 183, 243, 182, 241, 196, 248, 96, 6, ++ 16, 185, 79, 244, 129, 99, 243, 231, 1, 32, 189, 232, 240, 129, 56, ++ 181, 13, 70, 4, 70, 0, 40, 43, 208, 255, 247, 123, 254, 32, 70, 41, ++ 70, 255, 247, 120, 254, 160, 106, 8, 177, 185, 247, 175, 255, 99, 106, ++ 91, 177, 152, 106, 32, 177, 185, 247, 169, 255, 99, 106, 0, 34, 154, ++ 98, 96, 106, 185, 247, 163, 255, 0, 35, 99, 98, 212, 248, 96, 6, 32, ++ 177, 185, 247, 156, 255, 0, 35, 196, 248, 96, 54, 33, 104, 33, 177, ++ 40, 70, 255, 247, 206, 254, 0, 35, 35, 96, 32, 70, 189, 232, 56, 64, ++ 185, 247, 141, 191, 56, 189, 0, 0, 45, 233, 243, 65, 6, 70, 64, 246, ++ 100, 0, 136, 70, 21, 70, 31, 70, 183, 243, 112, 241, 4, 70, 16, 185, ++ 64, 242, 234, 51, 16, 224, 38, 35, 192, 248, 200, 53, 192, 248, 204, ++ 53, 8, 155, 65, 70, 192, 248, 8, 55, 58, 70, 48, 70, 255, 247, 200, ++ 254, 32, 96, 24, 185, 64, 242, 235, 51, 43, 96, 45, 224, 65, 35, 26, ++ 74, 128, 248, 184, 48, 35, 104, 18, 104, 4, 96, 195, 248, 152, 32, 79, ++ 244, 10, 112, 183, 243, 75, 241, 160, 98, 64, 177, 0, 245, 138, 112, ++ 224, 98, 44, 32, 183, 243, 67, 241, 96, 98, 48, 185, 2, 224, 64, 242, ++ 242, 51, 226, 231, 64, 242, 243, 51, 223, 231, 32, 70, 49, 70, 66, 70, ++ 43, 70, 0, 151, 255, 247, 195, 254, 56, 177, 32, 70, 49, 70, 66, 70, ++ 43, 70, 0, 151, 255, 247, 254, 253, 32, 185, 32, 70, 49, 70, 255, 247, ++ 121, 255, 0, 36, 32, 70, 189, 232, 252, 129, 116, 7, 0, 0, 3, 104, 11, ++ 34, 219, 105, 195, 248, 188, 32, 90, 97, 154, 97, 112, 71, 16, 181, ++ 4, 70, 248, 177, 208, 248, 80, 2, 8, 177, 185, 247, 33, 255, 212, 248, ++ 232, 2, 32, 177, 185, 247, 28, 255, 0, 35, 196, 248, 232, 50, 212, 248, ++ 252, 3, 32, 177, 185, 247, 20, 255, 0, 35, 196, 248, 252, 51, 35, 104, ++ 5, 73, 24, 104, 34, 70, 254, 247, 239, 249, 32, 70, 189, 232, 16, 64, ++ 185, 247, 6, 191, 16, 189, 216, 54, 4, 0, 128, 248, 192, 19, 112, 71, ++ 0, 0, 240, 181, 135, 176, 5, 70, 255, 247, 201, 255, 64, 242, 4, 64, ++ 185, 247, 243, 254, 4, 70, 0, 40, 0, 240, 212, 128, 0, 33, 64, 242, ++ 4, 66, 64, 38, 178, 243, 207, 242, 37, 96, 132, 248, 225, 99, 188, 32, ++ 185, 247, 227, 254, 196, 248, 80, 2, 0, 40, 0, 240, 186, 128, 0, 33, ++ 188, 34, 178, 243, 192, 242, 1, 35, 163, 114, 99, 115, 163, 115, 227, ++ 115, 163, 116, 148, 248, 225, 51, 0, 34, 63, 43, 230, 116, 152, 191, ++ 227, 116, 255, 35, 132, 248, 40, 48, 11, 35, 34, 116, 98, 116, 34, 115, ++ 226, 114, 5, 33, 2, 34, 132, 248, 222, 51, 0, 35, 132, 248, 39, 16, ++ 132, 248, 45, 32, 65, 242, 40, 80, 132, 248, 44, 48, 96, 133, 40, 104, ++ 144, 248, 156, 0, 33, 117, 1, 40, 12, 191, 1, 32, 16, 70, 132, 248, ++ 46, 0, 1, 32, 132, 248, 192, 3, 79, 244, 0, 96, 162, 117, 96, 99, 34, ++ 70, 33, 70, 5, 32, 208, 117, 2, 32, 208, 119, 35, 185, 79, 244, 128, ++ 112, 164, 248, 228, 3, 2, 224, 32, 32, 161, 248, 228, 3, 1, 51, 1, 50, ++ 2, 49, 8, 43, 237, 209, 0, 38, 1, 39, 32, 70, 65, 242, 40, 81, 132, ++ 248, 47, 96, 132, 248, 48, 112, 201, 247, 155, 250, 2, 33, 32, 70, 133, ++ 248, 190, 114, 200, 247, 141, 254, 132, 248, 216, 99, 4, 33, 40, 70, ++ 50, 74, 50, 75, 0, 150, 1, 148, 1, 240, 147, 252, 176, 66, 196, 248, ++ 0, 4, 78, 219, 4, 33, 40, 70, 46, 74, 46, 75, 0, 150, 1, 148, 5, 240, ++ 161, 251, 176, 66, 96, 96, 67, 219, 79, 244, 62, 112, 185, 247, 100, ++ 254, 196, 248, 232, 2, 0, 40, 59, 208, 49, 70, 79, 244, 62, 114, 178, ++ 243, 65, 242, 16, 32, 183, 243, 74, 240, 196, 248, 252, 3, 0, 40, 47, ++ 208, 33, 75, 40, 104, 0, 147, 33, 75, 33, 73, 1, 147, 33, 75, 34, 74, ++ 3, 147, 35, 70, 2, 150, 4, 150, 5, 150, 254, 247, 135, 249, 248, 185, ++ 30, 75, 132, 248, 84, 114, 26, 29, 7, 202, 141, 232, 7, 0, 34, 70, 27, ++ 104, 40, 70, 7, 33, 254, 247, 198, 250, 255, 35, 132, 248, 221, 51, ++ 43, 104, 32, 70, 147, 248, 66, 16, 204, 247, 209, 248, 200, 35, 196, ++ 248, 236, 50, 32, 70, 200, 247, 27, 254, 32, 35, 132, 248, 226, 51, ++ 8, 224, 212, 248, 80, 2, 8, 177, 185, 247, 34, 254, 32, 70, 185, 247, ++ 31, 254, 0, 36, 32, 70, 7, 176, 240, 189, 41, 175, 1, 0, 89, 167, 1, ++ 0, 197, 174, 1, 0, 113, 214, 1, 0, 249, 223, 1, 0, 201, 221, 1, 0, 232, ++ 53, 4, 0, 47, 214, 1, 0, 216, 54, 4, 0, 176, 158, 5, 0, 2, 70, 24, 177, ++ 0, 104, 2, 73, 254, 247, 229, 184, 112, 71, 0, 191, 118, 107, 136, 0, ++ 16, 181, 4, 70, 134, 176, 15, 73, 15, 74, 35, 70, 0, 104, 188, 247, ++ 239, 251, 14, 75, 32, 104, 0, 147, 0, 35, 1, 147, 2, 147, 3, 147, 11, ++ 75, 12, 73, 4, 147, 12, 75, 6, 74, 5, 147, 35, 70, 254, 247, 35, 249, ++ 32, 177, 32, 70, 255, 247, 217, 255, 79, 240, 255, 48, 6, 176, 16, 189, ++ 0, 191, 118, 107, 136, 0, 17, 228, 1, 0, 145, 67, 131, 0, 136, 56, 4, ++ 0, 160, 195, 135, 0, 217, 227, 1, 0, 56, 181, 4, 70, 208, 248, 52, 1, ++ 21, 70, 255, 247, 197, 254, 212, 248, 56, 1, 41, 70, 189, 232, 56, 64, ++ 0, 240, 48, 184, 16, 181, 4, 70, 0, 40, 40, 208, 65, 105, 105, 177, ++ 144, 248, 41, 48, 27, 177, 3, 104, 152, 104, 199, 243, 251, 245, 35, ++ 104, 97, 105, 152, 104, 199, 243, 110, 246, 0, 35, 99, 97, 160, 105, ++ 8, 177, 185, 247, 169, 253, 32, 107, 8, 177, 185, 247, 165, 253, 224, ++ 105, 24, 177, 185, 247, 161, 253, 0, 35, 227, 97, 35, 104, 5, 73, 24, ++ 104, 34, 70, 254, 247, 125, 248, 32, 70, 189, 232, 16, 64, 185, 247, ++ 148, 189, 16, 189, 186, 103, 136, 0, 128, 248, 40, 16, 112, 71, 0, 0, ++ 112, 181, 6, 70, 134, 176, 56, 32, 185, 247, 132, 253, 4, 70, 0, 40, ++ 0, 240, 148, 128, 0, 33, 56, 34, 178, 243, 98, 241, 64, 35, 38, 96, ++ 132, 248, 42, 48, 80, 32, 185, 247, 117, 253, 160, 97, 0, 40, 121, 208, ++ 0, 33, 80, 34, 178, 243, 84, 241, 1, 35, 132, 248, 32, 48, 132, 248, ++ 33, 48, 132, 248, 34, 48, 132, 248, 35, 48, 132, 248, 36, 48, 132, 248, ++ 37, 48, 132, 248, 38, 48, 132, 248, 39, 48, 35, 114, 16, 35, 99, 114, ++ 148, 248, 42, 48, 15, 43, 152, 191, 99, 114, 51, 106, 0, 37, 24, 105, ++ 221, 247, 238, 248, 79, 244, 122, 115, 227, 129, 200, 35, 35, 130, 0, ++ 240, 16, 0, 1, 35, 0, 40, 12, 191, 5, 32, 7, 32, 132, 248, 40, 48, 3, ++ 35, 32, 115, 227, 114, 32, 70, 165, 114, 228, 243, 235, 242, 4, 33, ++ 48, 70, 40, 74, 40, 75, 0, 149, 1, 148, 1, 240, 79, 251, 168, 66, 96, ++ 99, 55, 219, 4, 33, 48, 70, 36, 74, 37, 75, 0, 149, 1, 148, 5, 240, ++ 94, 250, 168, 66, 96, 96, 44, 219, 176, 104, 33, 73, 34, 70, 43, 70, ++ 199, 243, 239, 245, 96, 97, 32, 179, 79, 244, 186, 112, 185, 247, 25, ++ 253, 224, 97, 240, 177, 41, 70, 79, 244, 186, 114, 178, 243, 248, 240, ++ 25, 75, 48, 104, 0, 147, 25, 75, 25, 73, 1, 147, 25, 75, 26, 74, 3, ++ 147, 35, 70, 2, 149, 4, 149, 5, 149, 254, 247, 69, 248, 5, 70, 64, 185, ++ 51, 104, 32, 70, 147, 248, 67, 16, 228, 243, 93, 242, 132, 248, 41, ++ 80, 11, 224, 160, 105, 8, 177, 185, 247, 247, 252, 32, 107, 8, 177, ++ 185, 247, 243, 252, 32, 70, 185, 247, 240, 252, 0, 36, 32, 70, 6, 176, ++ 112, 189, 0, 191, 141, 85, 131, 0, 117, 85, 131, 0, 233, 85, 131, 0, ++ 201, 85, 131, 0, 73, 237, 1, 0, 101, 86, 131, 0, 177, 92, 131, 0, 208, ++ 195, 135, 0, 177, 87, 131, 0, 186, 103, 136, 0, 0, 32, 112, 71, 0, 35, ++ 3, 116, 64, 246, 251, 99, 195, 129, 112, 71, 16, 181, 4, 70, 144, 177, ++ 205, 247, 143, 251, 96, 104, 8, 73, 34, 70, 253, 247, 169, 255, 224, ++ 110, 8, 177, 185, 247, 193, 252, 32, 110, 185, 247, 190, 252, 32, 70, ++ 189, 232, 16, 64, 185, 247, 185, 188, 16, 189, 0, 191, 135, 106, 136, ++ 0, 48, 181, 5, 70, 135, 176, 112, 32, 185, 247, 172, 252, 4, 70, 0, ++ 40, 61, 208, 0, 33, 112, 34, 178, 243, 139, 240, 43, 104, 37, 96, 99, ++ 96, 24, 32, 185, 247, 159, 252, 32, 102, 0, 40, 44, 208, 0, 33, 24, ++ 34, 178, 243, 126, 240, 100, 32, 185, 247, 149, 252, 224, 102, 24, 179, ++ 0, 33, 100, 34, 178, 243, 117, 240, 19, 75, 19, 73, 0, 147, 0, 35, 1, ++ 147, 18, 75, 19, 74, 2, 147, 19, 75, 3, 147, 19, 75, 4, 147, 19, 75, ++ 5, 147, 96, 104, 35, 70, 253, 247, 191, 255, 96, 185, 1, 35, 99, 130, ++ 163, 130, 32, 70, 41, 70, 255, 247, 161, 255, 0, 40, 3, 219, 32, 70, ++ 255, 247, 158, 255, 3, 224, 32, 70, 255, 247, 160, 255, 0, 36, 32, 70, ++ 7, 176, 48, 189, 213, 100, 131, 0, 36, 196, 135, 0, 25, 104, 131, 0, ++ 135, 106, 136, 0, 217, 240, 1, 0, 188, 56, 4, 0, 239, 240, 1, 0, 112, ++ 181, 4, 70, 232, 177, 5, 106, 70, 106, 40, 70, 0, 240, 30, 249, 225, ++ 108, 65, 177, 168, 104, 199, 243, 151, 244, 168, 104, 225, 108, 199, ++ 243, 11, 245, 0, 35, 227, 100, 34, 70, 48, 70, 6, 73, 253, 247, 41, ++ 255, 40, 104, 33, 70, 254, 247, 68, 248, 32, 70, 189, 232, 112, 64, ++ 185, 247, 60, 188, 112, 189, 145, 83, 136, 0, 45, 233, 240, 65, 60, ++ 35, 192, 248, 244, 52, 10, 39, 5, 35, 208, 248, 0, 128, 192, 248, 248, ++ 52, 192, 248, 0, 117, 134, 176, 4, 70, 172, 32, 185, 247, 36, 252, 5, ++ 70, 0, 40, 0, 240, 181, 128, 0, 33, 172, 34, 0, 38, 178, 243, 1, 240, ++ 46, 112, 44, 98, 197, 248, 36, 128, 40, 70, 231, 243, 54, 244, 4, 33, ++ 40, 99, 87, 74, 32, 70, 51, 70, 0, 150, 1, 149, 1, 240, 39, 250, 176, ++ 66, 40, 103, 192, 242, 156, 128, 32, 70, 0, 240, 234, 248, 6, 70, 0, ++ 40, 64, 240, 149, 128, 160, 104, 79, 73, 42, 70, 51, 70, 199, 243, 202, ++ 244, 232, 100, 0, 40, 0, 240, 139, 128, 75, 75, 64, 70, 0, 147, 75, ++ 75, 75, 73, 1, 147, 75, 75, 76, 74, 2, 147, 76, 75, 3, 150, 4, 147, ++ 75, 75, 5, 147, 43, 70, 253, 247, 39, 255, 3, 70, 0, 40, 118, 209, 0, ++ 144, 41, 70, 32, 104, 71, 74, 253, 247, 113, 255, 6, 70, 0, 40, 109, ++ 209, 141, 232, 33, 0, 108, 33, 32, 70, 50, 70, 66, 75, 5, 240, 7, 249, ++ 0, 40, 168, 103, 98, 219, 212, 248, 120, 4, 49, 70, 1, 34, 62, 75, 3, ++ 240, 139, 252, 0, 40, 89, 209, 61, 75, 212, 248, 124, 6, 141, 232, 24, ++ 0, 57, 70, 1, 34, 58, 75, 2, 240, 5, 250, 0, 40, 77, 209, 57, 75, 212, ++ 248, 124, 6, 141, 232, 24, 0, 57, 70, 50, 34, 54, 75, 2, 240, 249, 249, ++ 0, 40, 65, 209, 212, 248, 124, 6, 5, 33, 0, 34, 51, 75, 0, 148, 2, 240, ++ 223, 251, 0, 40, 55, 209, 212, 248, 124, 6, 5, 33, 1, 34, 47, 75, 0, ++ 148, 2, 240, 213, 251, 112, 187, 212, 248, 124, 6, 5, 33, 50, 34, 43, ++ 75, 0, 148, 2, 240, 204, 251, 40, 187, 212, 248, 124, 6, 5, 33, 164, ++ 34, 40, 75, 0, 148, 2, 240, 73, 252, 224, 185, 212, 248, 124, 6, 192, ++ 33, 45, 34, 36, 75, 0, 148, 2, 240, 186, 251, 152, 185, 212, 248, 124, ++ 6, 144, 33, 45, 34, 33, 75, 0, 148, 2, 240, 109, 250, 80, 185, 216, ++ 248, 220, 0, 30, 73, 178, 243, 171, 245, 79, 244, 122, 115, 144, 251, ++ 243, 243, 43, 130, 3, 224, 40, 70, 255, 247, 14, 255, 0, 37, 40, 70, ++ 6, 176, 189, 232, 240, 129, 0, 191, 237, 112, 131, 0, 193, 139, 131, ++ 0, 245, 112, 131, 0, 141, 255, 1, 0, 240, 196, 135, 0, 149, 134, 131, ++ 0, 145, 83, 136, 0, 236, 56, 4, 0, 113, 249, 1, 0, 229, 120, 131, 0, ++ 177, 245, 1, 0, 1, 122, 131, 0, 149, 136, 131, 0, 177, 134, 131, 0, ++ 121, 136, 131, 0, 161, 134, 131, 0, 157, 135, 131, 0, 213, 135, 131, ++ 0, 97, 135, 131, 0, 25, 136, 131, 0, 45, 138, 131, 0, 101, 1, 2, 0, ++ 238, 102, 136, 0, 56, 181, 208, 248, 4, 85, 4, 70, 117, 177, 8, 73, ++ 2, 70, 25, 240, 251, 216, 7, 73, 34, 70, 32, 104, 253, 247, 13, 254, ++ 40, 70, 185, 247, 38, 251, 0, 35, 196, 248, 4, 53, 56, 189, 0, 191, ++ 65, 9, 2, 0, 62, 57, 4, 0, 240, 181, 4, 70, 135, 176, 79, 244, 10, 96, ++ 185, 247, 19, 251, 5, 70, 32, 185, 196, 248, 4, 5, 79, 240, 255, 48, ++ 5, 225, 0, 33, 79, 244, 10, 98, 177, 243, 237, 246, 34, 104, 5, 241, ++ 32, 3, 43, 96, 0, 38, 8, 35, 107, 97, 46, 97, 248, 33, 211, 101, 32, ++ 70, 123, 74, 124, 75, 0, 150, 1, 148, 5, 240, 44, 248, 176, 66, 168, ++ 97, 5, 218, 32, 70, 255, 247, 188, 255, 111, 240, 1, 0, 230, 224, 118, ++ 75, 0, 34, 67, 248, 4, 43, 242, 7, 31, 213, 116, 73, 1, 39, 10, 120, ++ 13, 42, 7, 250, 2, 254, 3, 220, 210, 25, 23, 250, 2, 240, 1, 224, 79, ++ 244, 0, 64, 202, 120, 1, 33, 17, 250, 2, 247, 13, 42, 71, 234, 14, 7, ++ 71, 234, 0, 0, 3, 220, 82, 24, 17, 250, 2, 242, 1, 224, 79, 244, 0, ++ 66, 2, 67, 67, 248, 4, 44, 176, 7, 35, 213, 99, 73, 1, 39, 74, 120, ++ 83, 248, 4, 236, 13, 42, 7, 250, 2, 252, 3, 220, 210, 25, 23, 250, 2, ++ 240, 1, 224, 79, 244, 0, 64, 138, 120, 1, 33, 17, 250, 2, 247, 13, 42, ++ 71, 234, 12, 7, 71, 234, 0, 0, 3, 220, 82, 24, 17, 250, 2, 242, 1, 224, ++ 79, 244, 0, 66, 2, 67, 66, 234, 14, 2, 67, 248, 4, 44, 113, 7, 35, 213, ++ 80, 73, 1, 39, 10, 121, 83, 248, 4, 236, 13, 42, 7, 250, 2, 252, 3, ++ 220, 210, 25, 23, 250, 2, 240, 1, 224, 79, 244, 0, 64, 74, 121, 1, 33, ++ 17, 250, 2, 247, 13, 42, 71, 234, 12, 7, 71, 234, 0, 0, 3, 220, 82, ++ 24, 17, 250, 2, 242, 1, 224, 79, 244, 0, 66, 2, 67, 66, 234, 14, 2, ++ 67, 248, 4, 44, 50, 7, 35, 213, 61, 73, 1, 39, 138, 121, 83, 248, 4, ++ 236, 13, 42, 7, 250, 2, 252, 3, 220, 210, 25, 23, 250, 2, 240, 1, 224, ++ 79, 244, 0, 64, 202, 121, 1, 33, 17, 250, 2, 247, 13, 42, 71, 234, 12, ++ 7, 71, 234, 0, 0, 3, 220, 82, 24, 17, 250, 2, 242, 1, 224, 79, 244, ++ 0, 66, 2, 67, 66, 234, 14, 2, 67, 248, 4, 44, 1, 54, 16, 46, 127, 244, ++ 101, 175, 42, 75, 0, 33, 3, 147, 32, 104, 41, 74, 35, 70, 0, 145, 1, ++ 145, 2, 145, 4, 145, 5, 145, 253, 247, 134, 253, 112, 187, 1, 33, 212, ++ 248, 120, 4, 10, 70, 35, 75, 3, 240, 0, 251, 72, 187, 212, 248, 120, ++ 4, 1, 33, 2, 34, 32, 75, 3, 240, 248, 250, 32, 187, 31, 75, 212, 248, ++ 124, 6, 141, 232, 24, 0, 128, 33, 5, 34, 28, 75, 1, 240, 241, 255, 224, ++ 185, 27, 75, 26, 29, 7, 202, 141, 232, 7, 0, 32, 70, 3, 33, 34, 70, ++ 27, 104, 253, 247, 172, 254, 32, 70, 22, 73, 34, 70, 24, 240, 226, 223, ++ 112, 185, 196, 248, 4, 85, 13, 224, 111, 240, 3, 0, 10, 224, 111, 240, ++ 4, 0, 7, 224, 111, 240, 5, 0, 4, 224, 111, 240, 6, 0, 1, 224, 111, 240, ++ 8, 0, 7, 176, 240, 189, 217, 170, 131, 0, 61, 170, 131, 0, 240, 114, ++ 4, 0, 72, 194, 135, 0, 245, 163, 131, 0, 62, 57, 4, 0, 89, 162, 131, ++ 0, 33, 168, 131, 0, 237, 171, 131, 0, 229, 163, 131, 0, 192, 158, 5, ++ 0, 65, 9, 2, 0, 112, 181, 30, 70, 139, 137, 21, 70, 66, 242, 86, 2, ++ 147, 66, 12, 70, 8, 216, 66, 242, 85, 2, 147, 66, 45, 210, 66, 242, ++ 80, 2, 147, 66, 41, 209, 8, 224, 66, 242, 96, 2, 147, 66, 26, 208, 78, ++ 242, 245, 66, 147, 66, 32, 209, 26, 224, 203, 137, 1, 43, 4, 209, 111, ++ 240, 59, 3, 43, 96, 15, 35, 3, 224, 111, 240, 69, 3, 43, 96, 20, 35, ++ 51, 96, 3, 104, 211, 248, 128, 48, 218, 4, 18, 213, 43, 104, 2, 59, ++ 43, 96, 14, 224, 111, 240, 74, 3, 43, 96, 15, 35, 8, 224, 111, 240, ++ 149, 3, 43, 96, 150, 35, 3, 224, 111, 240, 74, 3, 43, 96, 20, 35, 51, ++ 96, 212, 248, 16, 1, 48, 179, 0, 33, 64, 34, 177, 243, 139, 245, 212, ++ 248, 16, 33, 128, 35, 19, 112, 212, 248, 16, 33, 41, 104, 81, 112, 212, ++ 248, 16, 33, 147, 112, 212, 248, 16, 49, 50, 104, 218, 112, 212, 248, ++ 16, 49, 191, 34, 26, 113, 212, 248, 16, 49, 0, 34, 90, 113, 212, 248, ++ 16, 49, 3, 34, 218, 128, 70, 34, 26, 129, 10, 34, 90, 129, 1, 34, 154, ++ 129, 10, 34, 218, 129, 112, 189, 0, 0, 16, 181, 4, 70, 224, 177, 3, ++ 104, 14, 73, 24, 104, 34, 70, 253, 247, 94, 252, 227, 104, 51, 177, ++ 33, 70, 81, 248, 12, 59, 211, 248, 36, 6, 247, 247, 120, 249, 163, 104, ++ 51, 177, 33, 70, 81, 248, 8, 59, 211, 248, 36, 6, 247, 247, 111, 249, ++ 32, 70, 189, 232, 16, 64, 185, 247, 99, 185, 16, 189, 0, 191, 76, 134, ++ 136, 0, 112, 181, 5, 70, 134, 176, 16, 32, 185, 247, 86, 249, 4, 70, ++ 0, 40, 55, 208, 0, 33, 16, 34, 177, 243, 53, 245, 213, 248, 36, 6, 212, ++ 33, 25, 74, 4, 241, 8, 3, 247, 247, 69, 249, 48, 187, 213, 248, 36, ++ 6, 232, 33, 22, 74, 4, 241, 12, 3, 247, 247, 60, 249, 6, 70, 224, 185, ++ 141, 232, 17, 0, 4, 33, 40, 70, 17, 74, 18, 75, 4, 240, 106, 254, 0, ++ 40, 96, 96, 17, 219, 16, 75, 40, 104, 0, 147, 15, 75, 16, 73, 1, 147, ++ 16, 75, 16, 74, 3, 147, 35, 70, 2, 150, 4, 150, 5, 150, 253, 247, 100, ++ 252, 8, 185, 37, 96, 3, 224, 32, 70, 255, 247, 156, 255, 0, 36, 32, ++ 70, 6, 176, 112, 189, 67, 57, 4, 0, 73, 57, 4, 0, 21, 47, 132, 0, 213, ++ 46, 132, 0, 173, 39, 132, 0, 137, 47, 132, 0, 128, 198, 135, 0, 177, ++ 39, 132, 0, 76, 134, 136, 0, 1, 32, 112, 71, 1, 41, 112, 181, 14, 70, ++ 20, 70, 7, 209, 23, 75, 3, 33, 16, 70, 211, 248, 184, 48, 10, 70, 152, ++ 71, 112, 189, 25, 187, 18, 75, 211, 248, 192, 80, 255, 247, 235, 255, ++ 49, 70, 2, 70, 32, 70, 168, 71, 32, 70, 1, 33, 50, 70, 168, 71, 32, ++ 70, 2, 33, 50, 70, 168, 71, 32, 70, 3, 33, 1, 34, 168, 71, 32, 70, 79, ++ 244, 129, 113, 1, 34, 168, 71, 32, 70, 79, 244, 128, 113, 50, 70, 168, ++ 71, 32, 70, 64, 242, 1, 17, 50, 70, 168, 71, 112, 189, 0, 191, 208, ++ 134, 135, 0, 128, 108, 32, 56, 31, 40, 5, 216, 128, 35, 51, 250, 0, ++ 240, 0, 240, 1, 0, 112, 71, 0, 32, 112, 71, 193, 111, 176, 248, 78, ++ 48, 16, 181, 138, 106, 179, 177, 255, 43, 22, 217, 24, 11, 1, 56, 1, ++ 40, 20, 216, 3, 244, 112, 96, 0, 10, 9, 40, 15, 216, 120, 177, 3, 240, ++ 240, 0, 144, 40, 10, 216, 3, 240, 15, 0, 9, 40, 140, 191, 0, 32, 1, ++ 32, 4, 224, 24, 70, 2, 224, 1, 32, 0, 224, 0, 32, 12, 107, 65, 242, ++ 228, 65, 140, 66, 21, 209, 162, 245, 130, 97, 7, 57, 1, 41, 3, 216, ++ 63, 43, 152, 191, 0, 32, 16, 189, 64, 242, 12, 65, 138, 66, 7, 208, ++ 64, 242, 33, 65, 138, 66, 4, 209, 80, 43, 152, 191, 0, 32, 16, 189, ++ 0, 32, 16, 189, 144, 248, 118, 48, 16, 181, 4, 70, 59, 185, 4, 75, 4, ++ 73, 26, 104, 242, 243, 96, 243, 1, 35, 132, 248, 118, 48, 16, 189, 36, ++ 185, 5, 0, 40, 185, 5, 0, 112, 181, 12, 70, 5, 70, 22, 70, 8, 70, 10, ++ 34, 0, 33, 177, 243, 79, 244, 99, 136, 30, 67, 43, 109, 102, 128, 152, ++ 6, 3, 213, 35, 136, 67, 244, 128, 99, 35, 128, 213, 248, 148, 48, 66, ++ 242, 80, 2, 25, 140, 145, 66, 5, 209, 91, 140, 5, 43, 156, 191, 70, ++ 240, 4, 6, 102, 128, 112, 189, 0, 0, 208, 248, 128, 0, 1, 73, 178, 243, ++ 169, 178, 0, 191, 255, 158, 5, 0, 16, 181, 4, 70, 12, 32, 185, 247, ++ 67, 248, 196, 248, 12, 1, 56, 177, 12, 34, 0, 33, 177, 243, 34, 244, ++ 212, 248, 12, 49, 16, 34, 154, 114, 16, 189, 16, 181, 4, 70, 208, 248, ++ 12, 1, 32, 177, 185, 247, 51, 248, 0, 35, 196, 248, 12, 49, 16, 189, ++ 112, 181, 6, 70, 5, 70, 0, 36, 104, 105, 56, 177, 6, 75, 27, 104, 152, ++ 71, 48, 70, 33, 70, 0, 34, 1, 240, 196, 222, 1, 52, 4, 53, 6, 44, 241, ++ 209, 112, 189, 0, 191, 208, 134, 135, 0, 45, 233, 240, 67, 4, 105, 133, ++ 176, 5, 70, 236, 32, 166, 111, 185, 247, 13, 248, 48, 98, 0, 40, 115, ++ 208, 14, 32, 166, 111, 185, 247, 6, 248, 112, 98, 0, 40, 108, 208, 0, ++ 38, 55, 70, 15, 33, 104, 70, 55, 74, 51, 70, 177, 243, 71, 244, 212, ++ 248, 128, 0, 105, 70, 178, 243, 84, 242, 8, 177, 1, 55, 191, 178, 1, ++ 54, 182, 245, 124, 127, 237, 209, 55, 185, 212, 248, 128, 0, 46, 73, ++ 178, 243, 71, 242, 0, 40, 66, 208, 184, 0, 6, 48, 184, 247, 227, 255, ++ 197, 248, 68, 6, 0, 40, 72, 208, 0, 35, 131, 128, 0, 38, 15, 33, 104, ++ 70, 36, 74, 51, 70, 177, 243, 34, 244, 212, 248, 128, 0, 105, 70, 178, ++ 243, 47, 242, 152, 177, 213, 248, 68, 134, 105, 70, 212, 248, 128, 0, ++ 184, 248, 4, 144, 178, 243, 1, 242, 8, 235, 137, 3, 24, 129, 213, 248, ++ 68, 54, 154, 136, 3, 235, 130, 1, 1, 50, 206, 128, 154, 128, 1, 54, ++ 182, 245, 124, 127, 219, 209, 212, 248, 128, 0, 19, 73, 178, 243, 17, ++ 242, 213, 248, 68, 102, 80, 177, 212, 248, 128, 0, 15, 73, 178, 243, ++ 229, 241, 213, 248, 68, 54, 1, 34, 112, 128, 26, 112, 0, 224, 48, 112, ++ 163, 111, 88, 106, 96, 177, 1, 35, 3, 128, 131, 128, 195, 128, 3, 129, ++ 2, 35, 67, 129, 4, 35, 131, 129, 0, 32, 1, 224, 111, 240, 26, 0, 5, ++ 176, 189, 232, 240, 131, 0, 191, 36, 159, 5, 0, 73, 159, 5, 0, 45, 233, ++ 240, 79, 5, 104, 198, 104, 43, 104, 143, 176, 223, 105, 0, 35, 4, 70, ++ 0, 147, 136, 70, 11, 168, 9, 33, 164, 74, 51, 70, 177, 243, 199, 243, ++ 212, 248, 20, 144, 185, 241, 0, 15, 64, 240, 49, 129, 121, 104, 224, ++ 111, 9, 145, 212, 248, 136, 16, 212, 248, 8, 160, 1, 245, 0, 113, 215, ++ 248, 0, 176, 250, 247, 214, 254, 1, 70, 168, 104, 252, 247, 8, 254, ++ 0, 40, 0, 240, 38, 129, 9, 33, 148, 74, 11, 168, 51, 70, 205, 248, 0, ++ 144, 177, 243, 165, 243, 226, 111, 212, 248, 136, 16, 184, 241, 0, 15, ++ 2, 208, 1, 245, 0, 115, 0, 224, 67, 70, 1, 245, 8, 113, 0, 145, 9, 153, ++ 184, 241, 0, 15, 20, 191, 88, 70, 0, 32, 1, 144, 2, 145, 185, 104, 79, ++ 240, 255, 57, 3, 145, 205, 248, 16, 144, 249, 104, 223, 248, 28, 130, ++ 5, 145, 213, 248, 200, 21, 80, 70, 6, 145, 11, 169, 205, 248, 28, 128, ++ 250, 247, 15, 253, 5, 70, 0, 40, 0, 240, 242, 128, 42, 70, 123, 75, ++ 32, 70, 0, 33, 255, 247, 35, 254, 42, 70, 32, 70, 0, 33, 1, 240, 200, ++ 221, 1, 35, 0, 37, 0, 147, 9, 33, 115, 74, 51, 70, 11, 168, 177, 243, ++ 101, 243, 0, 149, 58, 104, 212, 248, 136, 48, 1, 146, 80, 70, 11, 169, ++ 226, 111, 3, 245, 16, 115, 2, 149, 3, 149, 205, 248, 16, 144, 5, 149, ++ 6, 149, 205, 248, 28, 128, 250, 247, 227, 252, 7, 70, 0, 40, 0, 240, ++ 199, 128, 58, 70, 101, 75, 32, 70, 41, 70, 255, 247, 247, 253, 58, 70, ++ 32, 70, 1, 33, 1, 240, 156, 221, 2, 33, 0, 145, 94, 74, 9, 33, 51, 70, ++ 11, 168, 177, 243, 58, 243, 212, 248, 136, 48, 80, 70, 11, 169, 226, ++ 111, 3, 245, 32, 115, 141, 232, 32, 8, 2, 149, 3, 149, 205, 248, 16, ++ 144, 5, 149, 6, 149, 205, 248, 28, 128, 250, 247, 185, 252, 7, 70, 0, ++ 40, 0, 240, 157, 128, 58, 70, 80, 75, 32, 70, 41, 70, 255, 247, 205, ++ 253, 58, 70, 32, 70, 2, 33, 1, 240, 114, 221, 3, 35, 0, 147, 9, 33, ++ 73, 74, 51, 70, 11, 168, 177, 243, 16, 243, 212, 248, 136, 48, 80, 70, ++ 11, 169, 226, 111, 3, 245, 48, 115, 141, 232, 32, 8, 2, 149, 3, 149, ++ 205, 248, 16, 144, 5, 149, 6, 149, 205, 248, 28, 128, 250, 247, 143, ++ 252, 7, 70, 0, 40, 115, 208, 58, 70, 60, 75, 32, 70, 41, 70, 255, 247, ++ 164, 253, 58, 70, 32, 70, 3, 33, 1, 240, 73, 221, 4, 33, 0, 145, 53, ++ 74, 9, 33, 51, 70, 11, 168, 177, 243, 231, 242, 212, 248, 136, 48, 80, ++ 70, 11, 169, 226, 111, 3, 245, 64, 115, 141, 232, 32, 8, 2, 149, 3, ++ 149, 205, 248, 16, 144, 5, 149, 6, 149, 205, 248, 28, 128, 250, 247, ++ 102, 252, 7, 70, 0, 40, 74, 208, 58, 70, 39, 75, 32, 70, 41, 70, 255, ++ 247, 123, 253, 58, 70, 32, 70, 4, 33, 1, 240, 32, 221, 5, 39, 51, 70, ++ 9, 33, 32, 74, 11, 168, 0, 151, 177, 243, 190, 242, 212, 248, 136, 48, ++ 80, 70, 11, 169, 226, 111, 3, 245, 80, 115, 141, 232, 32, 8, 2, 149, ++ 3, 149, 205, 248, 16, 144, 5, 149, 6, 149, 205, 248, 28, 128, 250, 247, ++ 61, 252, 6, 70, 8, 179, 50, 70, 32, 70, 41, 70, 18, 75, 255, 247, 83, ++ 253, 50, 70, 32, 70, 57, 70, 1, 240, 248, 220, 38, 70, 112, 105, 48, ++ 177, 14, 75, 14, 73, 211, 248, 140, 48, 152, 71, 198, 248, 192, 0, 1, ++ 53, 4, 54, 6, 45, 242, 209, 212, 248, 148, 16, 32, 70, 8, 49, 0, 34, ++ 255, 247, 203, 253, 1, 39, 0, 224, 7, 70, 56, 70, 15, 176, 189, 232, ++ 240, 143, 219, 158, 5, 0, 32, 99, 4, 0, 208, 134, 135, 0, 187, 25, 136, ++ 0, 8, 7, 0, 0, 16, 181, 189, 232, 16, 64, 252, 247, 159, 186, 17, 177, ++ 8, 70, 252, 247, 89, 184, 112, 71, 248, 181, 4, 105, 5, 70, 0, 44, 66, ++ 208, 224, 111, 8, 177, 252, 247, 133, 248, 32, 70, 255, 247, 234, 253, ++ 212, 248, 148, 96, 180, 248, 70, 0, 192, 247, 244, 250, 112, 106, 40, ++ 177, 3, 240, 69, 249, 0, 35, 7, 70, 115, 98, 0, 224, 7, 70, 212, 248, ++ 144, 0, 3, 240, 27, 249, 0, 38, 63, 24, 212, 248, 140, 0, 3, 240, 87, ++ 254, 32, 70, 196, 248, 128, 96, 230, 103, 255, 247, 192, 253, 213, 248, ++ 68, 6, 24, 177, 184, 247, 245, 253, 197, 248, 68, 102, 163, 111, 24, ++ 106, 32, 177, 184, 247, 238, 253, 163, 111, 0, 34, 26, 98, 163, 111, ++ 88, 106, 32, 177, 184, 247, 230, 253, 163, 111, 0, 34, 90, 98, 32, 70, ++ 1, 240, 35, 251, 0, 35, 43, 97, 0, 224, 39, 70, 56, 70, 248, 189, 0, ++ 0, 240, 181, 135, 176, 79, 244, 128, 53, 0, 33, 4, 35, 3, 170, 4, 70, ++ 208, 248, 136, 112, 0, 149, 242, 243, 17, 245, 35, 75, 6, 174, 70, 248, ++ 8, 61, 0, 33, 4, 35, 32, 70, 50, 70, 0, 149, 242, 243, 82, 245, 4, 35, ++ 0, 33, 5, 170, 32, 70, 0, 149, 242, 243, 255, 244, 4, 155, 5, 154, 154, ++ 66, 42, 209, 25, 75, 0, 33, 4, 147, 32, 70, 4, 35, 50, 70, 0, 149, 242, ++ 243, 62, 245, 4, 35, 0, 33, 5, 170, 32, 70, 0, 149, 242, 243, 235, 244, ++ 4, 155, 5, 154, 154, 66, 22, 209, 4, 35, 0, 33, 32, 70, 3, 170, 0, 149, ++ 242, 243, 44, 245, 0, 35, 199, 248, 140, 49, 215, 248, 32, 49, 179, ++ 241, 4, 47, 9, 208, 8, 72, 192, 235, 3, 12, 220, 241, 0, 0, 64, 235, ++ 12, 0, 2, 224, 0, 32, 0, 224, 1, 32, 7, 176, 240, 189, 0, 191, 170, ++ 85, 85, 170, 85, 170, 170, 85, 0, 4, 0, 132, 31, 75, 112, 181, 79, 240, ++ 0, 97, 0, 38, 3, 102, 10, 70, 70, 102, 4, 70, 5, 104, 243, 243, 4, 244, ++ 79, 240, 128, 115, 196, 248, 32, 49, 3, 35, 164, 248, 168, 48, 2, 35, ++ 164, 248, 170, 48, 7, 35, 164, 248, 164, 48, 4, 35, 164, 248, 166, 48, ++ 65, 242, 1, 3, 132, 248, 162, 96, 164, 248, 188, 48, 79, 244, 22, 115, ++ 165, 248, 248, 53, 43, 104, 13, 72, 147, 248, 156, 32, 12, 73, 1, 42, ++ 12, 191, 12, 34, 6, 34, 165, 248, 246, 37, 147, 248, 156, 32, 18, 241, ++ 255, 50, 24, 191, 1, 34, 177, 243, 79, 241, 255, 35, 132, 248, 52, 49, ++ 1, 35, 99, 116, 112, 189, 0, 191, 96, 168, 231, 184, 80, 57, 4, 0, 220, ++ 120, 5, 0, 45, 233, 240, 79, 151, 176, 155, 70, 79, 240, 0, 9, 22, 171, ++ 138, 70, 23, 70, 67, 248, 4, 157, 33, 153, 90, 70, 5, 70, 1, 240, 133, ++ 250, 4, 70, 0, 40, 0, 240, 165, 130, 157, 248, 128, 48, 40, 97, 3, 116, ++ 43, 104, 64, 246, 18, 1, 211, 248, 216, 0, 211, 248, 220, 96, 211, 248, ++ 224, 48, 74, 70, 196, 248, 132, 48, 224, 103, 196, 248, 128, 96, 188, ++ 243, 209, 241, 196, 248, 136, 0, 128, 70, 232, 96, 224, 111, 187, 243, ++ 146, 246, 160, 100, 32, 70, 255, 247, 134, 255, 48, 70, 164, 73, 177, ++ 243, 92, 247, 40, 177, 73, 70, 74, 70, 182, 247, 45, 253, 31, 250, 128, ++ 250, 48, 70, 159, 73, 177, 243, 81, 247, 72, 177, 0, 33, 10, 70, 182, ++ 247, 34, 253, 79, 246, 255, 115, 128, 178, 152, 66, 24, 191, 7, 70, ++ 80, 70, 57, 70, 253, 247, 4, 249, 8, 185, 12, 35, 98, 226, 150, 73, ++ 164, 248, 68, 160, 164, 248, 70, 112, 48, 70, 177, 243, 19, 247, 147, ++ 73, 196, 248, 92, 1, 48, 70, 177, 243, 13, 247, 196, 248, 96, 1, 180, ++ 248, 70, 0, 192, 247, 177, 249, 0, 48, 24, 191, 1, 32, 38, 48, 84, 248, ++ 32, 48, 180, 248, 70, 0, 196, 248, 148, 48, 192, 247, 165, 249, 0, 48, ++ 24, 191, 1, 32, 10, 48, 85, 248, 32, 48, 32, 70, 43, 98, 255, 247, 233, ++ 251, 8, 185, 13, 35, 53, 226, 224, 111, 187, 243, 247, 245, 224, 111, ++ 188, 243, 136, 240, 32, 70, 0, 33, 241, 243, 126, 245, 32, 70, 79, 240, ++ 255, 49, 242, 243, 221, 244, 32, 70, 255, 247, 204, 254, 8, 185, 14, ++ 35, 32, 226, 48, 70, 118, 73, 177, 243, 213, 246, 255, 40, 8, 191, 1, ++ 32, 164, 248, 78, 0, 32, 70, 255, 247, 209, 251, 8, 185, 15, 35, 17, ++ 226, 112, 73, 48, 70, 177, 243, 198, 246, 111, 73, 132, 248, 76, 0, ++ 48, 70, 177, 243, 192, 246, 109, 73, 32, 101, 48, 70, 177, 243, 187, ++ 246, 148, 248, 76, 48, 96, 101, 11, 43, 5, 217, 48, 70, 105, 73, 177, ++ 243, 178, 246, 196, 248, 80, 1, 103, 73, 48, 70, 177, 243, 172, 246, ++ 102, 73, 132, 248, 53, 1, 48, 70, 177, 243, 166, 246, 100, 73, 132, ++ 248, 54, 1, 48, 70, 177, 243, 160, 246, 98, 73, 196, 248, 84, 1, 48, ++ 70, 177, 243, 154, 246, 227, 111, 132, 248, 88, 1, 25, 107, 65, 242, ++ 107, 2, 145, 66, 32, 209, 155, 106, 78, 43, 8, 209, 180, 248, 78, 48, ++ 64, 43, 25, 217, 35, 109, 67, 240, 2, 3, 35, 101, 20, 224, 228, 43, ++ 4, 209, 180, 248, 78, 48, 179, 245, 168, 95, 6, 224, 239, 43, 11, 209, ++ 180, 248, 78, 32, 65, 242, 1, 35, 154, 66, 5, 216, 35, 109, 67, 244, ++ 128, 3, 35, 101, 0, 35, 99, 101, 48, 70, 75, 73, 167, 111, 177, 243, ++ 108, 246, 56, 118, 163, 111, 26, 126, 1, 42, 1, 208, 3, 34, 26, 118, ++ 35, 109, 152, 6, 4, 213, 1, 33, 32, 70, 10, 70, 242, 243, 111, 247, ++ 180, 248, 70, 32, 1, 35, 196, 248, 184, 48, 180, 248, 68, 0, 43, 104, ++ 165, 248, 174, 33, 226, 111, 165, 248, 172, 1, 195, 248, 216, 32, 162, ++ 108, 26, 97, 148, 248, 76, 32, 131, 248, 124, 32, 43, 104, 34, 109, ++ 180, 248, 78, 0, 195, 248, 128, 32, 98, 109, 163, 248, 122, 0, 195, ++ 248, 132, 32, 148, 248, 76, 32, 32, 70, 11, 42, 132, 191, 212, 248, ++ 80, 33, 195, 248, 76, 33, 212, 248, 184, 32, 1, 39, 131, 248, 62, 112, ++ 90, 98, 169, 104, 42, 70, 3, 240, 56, 252, 196, 248, 140, 0, 8, 185, ++ 25, 35, 108, 225, 33, 154, 227, 111, 2, 146, 162, 108, 4, 144, 6, 146, ++ 180, 248, 70, 32, 180, 248, 68, 0, 173, 248, 42, 32, 218, 107, 3, 147, ++ 11, 146, 26, 108, 173, 248, 40, 0, 12, 146, 90, 108, 2, 168, 13, 146, ++ 148, 248, 76, 32, 205, 248, 20, 176, 14, 146, 154, 106, 9, 150, 15, ++ 146, 180, 248, 78, 32, 16, 146, 26, 107, 17, 146, 34, 109, 18, 146, ++ 98, 109, 19, 146, 90, 104, 219, 104, 7, 146, 8, 147, 3, 240, 54, 248, ++ 196, 248, 144, 0, 240, 185, 16, 35, 58, 225, 0, 191, 7, 159, 5, 0, 116, ++ 159, 5, 0, 14, 159, 5, 0, 25, 159, 5, 0, 107, 159, 5, 0, 122, 159, 5, ++ 0, 244, 158, 5, 0, 83, 159, 5, 0, 95, 159, 5, 0, 49, 159, 5, 0, 130, ++ 159, 5, 0, 60, 159, 5, 0, 208, 158, 5, 0, 230, 158, 5, 0, 38, 35, 197, ++ 248, 200, 53, 197, 248, 204, 53, 79, 244, 255, 115, 196, 248, 56, 49, ++ 180, 248, 70, 0, 192, 247, 115, 248, 16, 241, 0, 9, 24, 191, 79, 240, ++ 1, 9, 73, 70, 32, 70, 243, 243, 32, 247, 185, 241, 0, 15, 212, 248, ++ 148, 48, 12, 191, 2, 34, 1, 34, 195, 248, 4, 144, 26, 96, 43, 106, 20, ++ 191, 1, 34, 2, 34, 195, 248, 4, 144, 26, 96, 224, 111, 213, 248, 28, ++ 144, 187, 243, 244, 244, 216, 248, 92, 49, 201, 248, 0, 0, 35, 240, ++ 0, 67, 120, 74, 227, 102, 35, 103, 163, 108, 12, 33, 1, 251, 3, 35, ++ 48, 59, 196, 248, 216, 48, 32, 70, 57, 70, 241, 243, 32, 247, 212, 248, ++ 148, 144, 212, 248, 144, 0, 65, 70, 217, 248, 0, 32, 51, 70, 2, 240, ++ 212, 254, 201, 248, 36, 0, 8, 185, 17, 35, 206, 224, 79, 240, 255, 49, ++ 32, 70, 243, 243, 254, 240, 212, 248, 148, 48, 225, 110, 88, 106, 2, ++ 240, 120, 254, 212, 248, 148, 48, 3, 241, 34, 2, 0, 146, 3, 241, 28, ++ 1, 3, 241, 30, 2, 88, 106, 32, 51, 2, 240, 88, 254, 212, 248, 148, 128, ++ 216, 248, 36, 0, 2, 240, 96, 254, 136, 248, 40, 0, 212, 248, 148, 48, ++ 213, 248, 32, 128, 88, 106, 2, 240, 87, 254, 136, 248, 20, 0, 212, 248, ++ 148, 128, 216, 248, 36, 0, 2, 240, 82, 254, 212, 248, 148, 48, 200, ++ 248, 24, 0, 218, 139, 55, 250, 2, 241, 201, 7, 1, 212, 18, 35, 148, ++ 224, 41, 106, 88, 106, 8, 97, 152, 139, 74, 129, 8, 129, 26, 140, 88, ++ 140, 138, 129, 200, 129, 15, 34, 64, 242, 255, 48, 216, 130, 154, 130, ++ 32, 70, 57, 70, 255, 247, 116, 251, 8, 185, 19, 35, 126, 224, 0, 33, ++ 32, 70, 242, 243, 73, 241, 48, 70, 64, 73, 167, 111, 177, 243, 46, 245, ++ 35, 109, 192, 178, 218, 7, 56, 96, 32, 213, 99, 109, 27, 6, 29, 212, ++ 227, 111, 154, 105, 144, 0, 2, 213, 218, 105, 209, 7, 4, 213, 219, 105, ++ 218, 7, 1, 212, 88, 7, 17, 213, 227, 110, 153, 0, 14, 213, 48, 70, 50, ++ 73, 177, 243, 55, 245, 48, 177, 48, 73, 48, 70, 177, 243, 14, 245, 193, ++ 178, 32, 70, 4, 224, 32, 70, 8, 33, 1, 224, 32, 70, 0, 33, 210, 247, ++ 132, 255, 224, 111, 184, 247, 73, 252, 32, 70, 210, 247, 206, 254, 0, ++ 148, 224, 111, 38, 73, 39, 74, 0, 35, 251, 247, 27, 253, 32, 70, 0, ++ 33, 243, 243, 37, 245, 32, 70, 255, 247, 102, 250, 8, 185, 21, 35, 52, ++ 224, 4, 241, 252, 6, 49, 70, 177, 243, 106, 241, 48, 70, 182, 247, 65, ++ 251, 24, 185, 48, 70, 182, 247, 73, 251, 8, 177, 22, 35, 37, 224, 32, ++ 70, 255, 247, 89, 250, 40, 70, 161, 108, 1, 240, 65, 248, 43, 104, 211, ++ 248, 152, 0, 168, 177, 3, 120, 155, 177, 19, 73, 34, 70, 177, 243, 251, ++ 245, 43, 104, 17, 73, 211, 248, 152, 0, 34, 70, 249, 247, 38, 255, 96, ++ 105, 48, 177, 43, 104, 211, 248, 152, 16, 13, 75, 211, 248, 176, 48, ++ 152, 71, 40, 70, 255, 247, 106, 250, 16, 177, 27, 35, 21, 147, 21, 152, ++ 23, 176, 189, 232, 240, 143, 0, 191, 48, 99, 4, 0, 235, 158, 5, 0, 233, ++ 73, 132, 0, 253, 73, 132, 0, 85, 78, 2, 0, 83, 78, 2, 0, 208, 134, 135, ++ 0, 16, 181, 4, 70, 0, 40, 40, 208, 3, 104, 20, 73, 24, 104, 34, 70, ++ 252, 247, 71, 253, 35, 106, 27, 177, 4, 241, 32, 0, 176, 243, 64, 240, ++ 227, 105, 27, 177, 4, 241, 28, 0, 176, 243, 58, 240, 163, 105, 27, 177, ++ 4, 241, 24, 0, 176, 243, 52, 240, 99, 105, 27, 177, 4, 241, 20, 0, 176, ++ 243, 46, 240, 35, 105, 27, 177, 4, 241, 16, 0, 176, 243, 40, 240, 32, ++ 70, 189, 232, 16, 64, 184, 247, 64, 186, 16, 189, 166, 179, 136, 0, ++ 3, 104, 48, 181, 219, 105, 5, 70, 88, 109, 135, 176, 0, 1, 36, 48, 181, ++ 243, 34, 244, 4, 70, 0, 40, 56, 208, 3, 70, 67, 248, 36, 91, 195, 96, ++ 4, 241, 16, 1, 213, 248, 32, 6, 175, 243, 243, 247, 104, 187, 213, 248, ++ 32, 6, 4, 241, 20, 1, 175, 243, 236, 247, 48, 187, 213, 248, 32, 6, ++ 4, 241, 24, 1, 175, 243, 229, 247, 248, 185, 213, 248, 32, 6, 4, 241, ++ 28, 1, 175, 243, 222, 247, 192, 185, 213, 248, 32, 6, 4, 241, 32, 1, ++ 175, 243, 215, 247, 136, 185, 79, 244, 130, 99, 99, 96, 11, 75, 1, 144, ++ 0, 147, 10, 75, 3, 144, 2, 147, 4, 144, 5, 144, 9, 73, 40, 104, 9, 74, ++ 35, 70, 252, 247, 55, 253, 24, 177, 32, 70, 255, 247, 135, 255, 0, 36, ++ 32, 70, 7, 176, 48, 189, 0, 191, 133, 106, 2, 0, 17, 118, 132, 0, 100, ++ 57, 4, 0, 166, 179, 136, 0, 240, 181, 208, 248, 40, 65, 0, 104, 165, ++ 104, 192, 105, 64, 109, 133, 66, 17, 210, 231, 104, 46, 1, 184, 25, ++ 67, 96, 5, 155, 1, 53, 131, 96, 6, 155, 186, 81, 195, 96, 96, 104, 165, ++ 96, 195, 28, 89, 24, 33, 240, 3, 1, 97, 96, 240, 189, 111, 240, 21, ++ 0, 240, 189, 208, 248, 40, 49, 24, 105, 175, 243, 109, 183, 208, 248, ++ 40, 1, 16, 177, 0, 105, 175, 243, 201, 183, 112, 71, 208, 248, 40, 49, ++ 216, 105, 175, 243, 97, 183, 208, 248, 40, 49, 216, 105, 175, 243, 190, ++ 183, 115, 181, 5, 70, 211, 247, 202, 250, 4, 70, 184, 177, 43, 104, ++ 79, 240, 0, 82, 197, 248, 108, 2, 0, 146, 147, 248, 47, 32, 40, 70, ++ 1, 146, 33, 70, 0, 34, 4, 51, 243, 243, 245, 246, 6, 70, 80, 185, 40, ++ 70, 33, 70, 211, 247, 45, 253, 6, 70, 32, 185, 1, 224, 111, 240, 26, ++ 6, 48, 70, 124, 189, 40, 70, 33, 70, 244, 243, 68, 245, 248, 231, 0, ++ 0, 16, 181, 4, 70, 80, 177, 3, 104, 5, 73, 24, 104, 34, 70, 252, 247, ++ 102, 252, 32, 70, 189, 232, 16, 64, 184, 247, 125, 185, 16, 189, 0, ++ 191, 170, 57, 4, 0, 240, 181, 6, 105, 135, 176, 5, 70, 116, 32, 181, ++ 243, 97, 243, 4, 70, 0, 40, 97, 208, 0, 35, 5, 96, 4, 33, 0, 147, 1, ++ 144, 50, 74, 40, 70, 50, 75, 3, 240, 152, 254, 0, 40, 32, 100, 84, 219, ++ 40, 70, 47, 73, 34, 70, 255, 247, 148, 255, 0, 40, 77, 209, 45, 75, ++ 4, 144, 0, 147, 45, 75, 5, 144, 1, 147, 44, 75, 40, 104, 2, 147, 44, ++ 75, 44, 73, 3, 147, 44, 74, 35, 70, 252, 247, 138, 252, 0, 40, 59, 209, ++ 42, 75, 213, 248, 124, 6, 141, 232, 24, 0, 128, 33, 200, 34, 40, 75, ++ 0, 240, 166, 255, 128, 187, 213, 248, 124, 6, 128, 33, 200, 34, 37, ++ 75, 0, 148, 1, 240, 139, 249, 7, 70, 48, 187, 132, 248, 44, 0, 43, 105, ++ 33, 73, 211, 248, 128, 0, 177, 243, 99, 243, 57, 70, 132, 248, 111, ++ 0, 8, 34, 4, 241, 45, 0, 176, 243, 7, 245, 132, 248, 56, 112, 132, 248, ++ 57, 112, 231, 134, 214, 248, 128, 0, 24, 73, 177, 243, 117, 243, 56, ++ 177, 214, 248, 128, 0, 21, 73, 177, 243, 75, 243, 132, 248, 63, 0, 7, ++ 224, 186, 35, 132, 248, 63, 48, 3, 224, 32, 70, 255, 247, 127, 255, ++ 0, 36, 32, 70, 7, 176, 240, 189, 0, 191, 139, 108, 2, 0, 163, 108, 2, ++ 0, 137, 108, 2, 0, 53, 134, 132, 0, 181, 112, 2, 0, 29, 114, 2, 0, 129, ++ 108, 2, 0, 176, 198, 135, 0, 170, 57, 4, 0, 147, 108, 2, 0, 143, 108, ++ 2, 0, 151, 108, 2, 0, 141, 159, 5, 0, 157, 159, 5, 0, 48, 181, 4, 70, ++ 133, 176, 0, 40, 64, 208, 208, 248, 32, 17, 49, 177, 3, 104, 152, 104, ++ 198, 243, 156, 241, 0, 35, 196, 248, 32, 49, 35, 104, 26, 104, 146, ++ 248, 47, 32, 34, 179, 211, 248, 36, 1, 1, 169, 0, 34, 23, 240, 30, 220, ++ 15, 224, 67, 104, 90, 6, 12, 213, 212, 248, 48, 81, 69, 25, 4, 224, ++ 3, 104, 197, 248, 16, 49, 184, 247, 194, 248, 213, 248, 16, 1, 0, 40, ++ 246, 209, 35, 104, 1, 169, 211, 248, 36, 1, 234, 247, 175, 248, 0, 40, ++ 231, 209, 4, 224, 3, 104, 196, 248, 68, 49, 184, 247, 176, 248, 212, ++ 248, 68, 1, 0, 40, 246, 209, 35, 104, 4, 73, 24, 104, 34, 70, 252, 247, ++ 138, 251, 32, 70, 184, 247, 163, 248, 5, 176, 48, 189, 95, 147, 136, ++ 0, 48, 181, 5, 70, 135, 176, 79, 244, 166, 112, 184, 247, 149, 248, ++ 4, 70, 0, 40, 117, 208, 0, 33, 79, 244, 166, 114, 176, 243, 115, 244, ++ 60, 75, 37, 96, 0, 147, 59, 75, 60, 74, 1, 147, 0, 35, 2, 147, 3, 146, ++ 4, 147, 5, 147, 40, 104, 57, 73, 57, 74, 35, 70, 252, 247, 190, 251, ++ 0, 40, 93, 209, 43, 106, 26, 104, 2, 42, 5, 209, 91, 125, 0, 43, 12, ++ 191, 22, 35, 48, 35, 0, 224, 48, 35, 34, 24, 68, 48, 176, 245, 136, ++ 127, 19, 116, 238, 209, 168, 104, 46, 73, 42, 70, 0, 35, 198, 243, 51, ++ 241, 196, 248, 32, 1, 0, 40, 66, 208, 79, 244, 122, 115, 69, 242, 115, ++ 82, 196, 248, 28, 49, 164, 248, 60, 33, 0, 35, 70, 34, 196, 248, 68, ++ 49, 164, 248, 62, 33, 40, 70, 141, 232, 40, 0, 79, 244, 138, 113, 33, ++ 74, 34, 75, 3, 240, 126, 253, 0, 40, 196, 248, 48, 1, 39, 219, 31, 75, ++ 213, 248, 124, 6, 141, 232, 24, 0, 5, 33, 176, 34, 29, 75, 0, 240, 16, ++ 255, 224, 185, 28, 75, 213, 248, 124, 6, 141, 232, 24, 0, 5, 33, 178, ++ 34, 25, 75, 0, 240, 5, 255, 136, 185, 213, 248, 124, 6, 10, 33, 176, ++ 34, 22, 75, 0, 148, 1, 240, 230, 248, 64, 185, 213, 248, 168, 6, 176, ++ 33, 19, 74, 20, 75, 0, 148, 1, 240, 71, 251, 24, 177, 32, 70, 255, 247, ++ 51, 255, 0, 36, 32, 70, 7, 176, 48, 189, 0, 191, 137, 167, 132, 0, 241, ++ 187, 132, 0, 93, 165, 132, 0, 244, 199, 135, 0, 95, 147, 136, 0, 77, ++ 160, 132, 0, 9, 173, 132, 0, 229, 172, 132, 0, 141, 180, 132, 0, 225, ++ 161, 132, 0, 201, 179, 132, 0, 73, 161, 132, 0, 141, 170, 132, 0, 125, ++ 165, 132, 0, 145, 165, 132, 0, 16, 181, 4, 70, 48, 177, 211, 247, 185, ++ 255, 32, 70, 189, 232, 16, 64, 183, 247, 239, 191, 16, 189, 16, 181, ++ 4, 70, 36, 32, 181, 243, 216, 241, 0, 177, 4, 96, 16, 189, 0, 0, 16, ++ 181, 4, 70, 224, 177, 67, 104, 14, 73, 24, 104, 34, 70, 252, 247, 192, ++ 250, 212, 248, 60, 1, 255, 247, 223, 255, 212, 248, 52, 1, 255, 247, ++ 219, 255, 212, 248, 156, 0, 8, 177, 183, 247, 207, 255, 212, 248, 148, ++ 0, 8, 177, 183, 247, 202, 255, 32, 70, 189, 232, 16, 64, 183, 247, 197, ++ 191, 16, 189, 0, 191, 218, 29, 134, 0, 45, 233, 240, 65, 117, 75, 0, ++ 39, 31, 96, 117, 75, 5, 104, 136, 176, 6, 70, 31, 96, 79, 244, 160, ++ 112, 183, 247, 176, 255, 4, 70, 0, 40, 0, 240, 216, 128, 57, 70, 79, ++ 244, 160, 114, 176, 243, 141, 243, 132, 232, 96, 0, 48, 70, 198, 248, ++ 92, 65, 255, 247, 181, 255, 128, 70, 196, 248, 52, 1, 48, 177, 48, 70, ++ 255, 247, 174, 255, 128, 70, 196, 248, 60, 1, 32, 185, 32, 70, 183, ++ 247, 149, 255, 68, 70, 187, 224, 127, 33, 4, 34, 4, 241, 68, 0, 176, ++ 243, 112, 243, 127, 33, 4, 34, 4, 241, 112, 0, 176, 243, 106, 243, 4, ++ 34, 7, 168, 57, 70, 176, 243, 101, 243, 51, 104, 147, 248, 124, 32, ++ 211, 248, 220, 0, 1, 42, 19, 217, 85, 73, 177, 243, 211, 241, 1, 70, ++ 88, 177, 7, 168, 3, 34, 176, 243, 53, 244, 7, 168, 4, 33, 252, 243, ++ 235, 247, 144, 177, 7, 168, 79, 73, 12, 224, 7, 168, 78, 73, 9, 224, ++ 78, 73, 177, 243, 155, 241, 9, 40, 3, 70, 6, 216, 76, 73, 7, 168, 1, ++ 235, 131, 1, 3, 34, 176, 243, 29, 244, 3, 34, 7, 169, 4, 241, 8, 0, ++ 176, 243, 23, 244, 51, 104, 70, 73, 211, 248, 220, 0, 177, 243, 133, ++ 241, 213, 248, 216, 48, 65, 242, 107, 2, 25, 107, 224, 96, 145, 66, ++ 14, 209, 155, 106, 139, 43, 1, 208, 144, 43, 9, 209, 2, 40, 7, 209, ++ 7, 168, 61, 73, 4, 34, 176, 243, 217, 243, 8, 185, 3, 35, 227, 96, 213, ++ 248, 216, 48, 65, 242, 107, 2, 25, 107, 145, 66, 13, 209, 155, 106, ++ 147, 43, 10, 209, 7, 168, 53, 73, 4, 34, 176, 243, 199, 243, 32, 185, ++ 227, 104, 4, 43, 1, 209, 6, 35, 227, 96, 213, 248, 216, 48, 65, 242, ++ 107, 2, 25, 107, 145, 66, 24, 209, 154, 106, 64, 242, 53, 19, 154, 66, ++ 19, 209, 7, 168, 42, 73, 4, 34, 176, 243, 176, 243, 88, 177, 7, 168, ++ 40, 73, 4, 34, 176, 243, 170, 243, 40, 177, 7, 168, 38, 73, 4, 34, 176, ++ 243, 164, 243, 8, 185, 19, 35, 227, 96, 0, 37, 35, 72, 213, 247, 29, ++ 249, 7, 169, 4, 34, 196, 248, 148, 80, 196, 248, 152, 80, 196, 248, ++ 156, 80, 196, 248, 160, 80, 196, 248, 164, 80, 132, 248, 244, 80, 32, ++ 70, 212, 247, 20, 251, 26, 75, 48, 104, 141, 232, 40, 0, 25, 75, 26, ++ 73, 4, 147, 26, 75, 26, 74, 5, 147, 35, 70, 2, 149, 3, 149, 252, 247, ++ 29, 250, 40, 177, 32, 70, 198, 248, 92, 81, 255, 247, 243, 254, 44, ++ 70, 32, 70, 8, 176, 189, 232, 240, 129, 116, 8, 0, 0, 124, 8, 0, 0, ++ 176, 159, 5, 0, 217, 57, 4, 0, 162, 153, 136, 0, 182, 159, 5, 0, 32, ++ 202, 135, 0, 185, 159, 5, 0, 103, 212, 135, 0, 159, 153, 136, 0, 8, ++ 202, 135, 0, 164, 217, 135, 0, 173, 217, 135, 0, 40, 60, 4, 0, 129, ++ 233, 132, 0, 176, 57, 4, 0, 228, 201, 135, 0, 17, 117, 2, 0, 218, 29, ++ 134, 0, 48, 181, 5, 70, 135, 176, 12, 32, 181, 243, 150, 240, 4, 70, ++ 224, 177, 18, 75, 5, 96, 79, 244, 144, 113, 0, 147, 1, 144, 7, 34, 213, ++ 248, 124, 6, 15, 75, 0, 240, 224, 252, 144, 185, 14, 75, 1, 144, 0, ++ 147, 13, 75, 2, 144, 4, 147, 13, 75, 3, 144, 5, 147, 40, 104, 12, 73, ++ 12, 74, 35, 70, 252, 247, 200, 249, 16, 185, 32, 70, 7, 176, 48, 189, ++ 32, 70, 183, 247, 130, 254, 0, 36, 247, 231, 0, 191, 205, 1, 133, 0, ++ 45, 255, 132, 0, 105, 255, 132, 0, 152, 60, 4, 0, 209, 147, 2, 0, 48, ++ 230, 135, 0, 188, 60, 4, 0, 3, 104, 16, 181, 4, 70, 5, 73, 24, 104, ++ 34, 70, 252, 247, 77, 249, 32, 70, 189, 232, 16, 64, 183, 247, 100, ++ 190, 0, 191, 188, 60, 4, 0, 112, 181, 5, 70, 134, 176, 12, 32, 181, ++ 243, 74, 240, 4, 70, 0, 40, 99, 208, 5, 96, 0, 38, 1, 144, 4, 33, 40, ++ 70, 51, 74, 52, 75, 0, 150, 255, 247, 103, 252, 176, 66, 96, 96, 89, ++ 219, 4, 33, 40, 70, 48, 74, 49, 75, 0, 150, 1, 148, 3, 240, 118, 251, ++ 176, 66, 160, 96, 78, 219, 40, 70, 45, 73, 34, 70, 255, 247, 114, 252, ++ 0, 40, 71, 209, 43, 75, 213, 248, 124, 6, 141, 232, 24, 0, 79, 244, ++ 144, 113, 37, 34, 40, 75, 0, 240, 117, 252, 0, 40, 58, 209, 39, 75, ++ 213, 248, 124, 6, 141, 232, 24, 0, 79, 244, 144, 113, 60, 34, 36, 75, ++ 0, 240, 104, 252, 0, 40, 45, 209, 213, 248, 124, 6, 5, 33, 156, 34, ++ 32, 75, 0, 149, 0, 240, 108, 254, 0, 40, 35, 209, 213, 248, 124, 6, ++ 128, 33, 37, 34, 28, 75, 0, 148, 0, 240, 0, 253, 208, 185, 213, 248, ++ 124, 6, 128, 33, 60, 34, 25, 75, 0, 148, 0, 240, 247, 252, 136, 185, ++ 23, 75, 1, 144, 0, 147, 23, 75, 3, 144, 2, 147, 4, 144, 5, 144, 21, ++ 73, 40, 104, 21, 74, 35, 70, 252, 247, 52, 249, 16, 185, 32, 70, 6, ++ 176, 112, 189, 32, 70, 183, 247, 238, 253, 0, 36, 247, 231, 0, 191, ++ 93, 7, 133, 0, 29, 7, 133, 0, 101, 11, 133, 0, 81, 11, 133, 0, 217, ++ 7, 133, 0, 233, 13, 133, 0, 253, 7, 133, 0, 25, 14, 133, 0, 37, 8, 133, ++ 0, 61, 6, 133, 0, 221, 6, 133, 0, 253, 6, 133, 0, 21, 9, 133, 0, 229, ++ 13, 133, 0, 108, 230, 135, 0, 58, 158, 136, 0, 56, 181, 5, 104, 4, 70, ++ 34, 70, 40, 104, 6, 73, 252, 247, 167, 248, 40, 70, 5, 73, 34, 70, 255, ++ 247, 250, 251, 32, 70, 189, 232, 56, 64, 183, 247, 185, 189, 58, 158, ++ 136, 0, 217, 7, 133, 0, 2, 70, 2, 73, 0, 104, 252, 247, 148, 184, 0, ++ 191, 194, 60, 4, 0, 48, 181, 13, 75, 135, 176, 0, 147, 0, 35, 4, 70, ++ 1, 147, 2, 147, 3, 147, 4, 147, 5, 147, 9, 73, 9, 74, 35, 70, 0, 104, ++ 252, 247, 219, 248, 0, 40, 20, 191, 79, 240, 255, 53, 0, 37, 32, 70, ++ 253, 243, 93, 246, 40, 70, 7, 176, 48, 189, 181, 154, 2, 0, 216, 60, ++ 4, 0, 194, 60, 4, 0, 45, 233, 240, 67, 6, 70, 135, 176, 56, 32, 15, ++ 70, 145, 70, 152, 70, 183, 247, 126, 253, 4, 70, 0, 40, 56, 208, 0, ++ 33, 56, 34, 176, 243, 93, 241, 215, 248, 36, 6, 64, 33, 26, 74, 4, 241, ++ 32, 3, 245, 247, 109, 253, 5, 70, 32, 177, 32, 70, 183, 247, 109, 253, ++ 0, 36, 37, 224, 21, 75, 196, 248, 28, 128, 167, 96, 196, 248, 12, 144, ++ 38, 97, 19, 73, 0, 147, 1, 144, 2, 144, 3, 144, 4, 144, 5, 144, 35, ++ 70, 48, 70, 15, 74, 252, 247, 151, 248, 3, 70, 96, 185, 224, 104, 13, ++ 73, 34, 70, 197, 243, 30, 246, 5, 70, 160, 97, 64, 185, 32, 105, 10, ++ 73, 34, 70, 252, 247, 45, 248, 32, 70, 183, 247, 70, 253, 44, 70, 32, ++ 70, 7, 176, 189, 232, 240, 131, 216, 91, 136, 0, 125, 23, 133, 0, 132, ++ 230, 135, 0, 192, 159, 5, 0, 221, 23, 133, 0, 240, 60, 4, 0, 16, 181, ++ 4, 70, 253, 243, 172, 247, 15, 73, 32, 105, 34, 70, 252, 247, 16, 248, ++ 161, 105, 97, 177, 35, 125, 35, 177, 224, 104, 197, 243, 108, 245, 0, ++ 35, 35, 117, 224, 104, 161, 105, 197, 243, 222, 245, 0, 35, 163, 97, ++ 163, 104, 4, 241, 32, 1, 211, 248, 36, 6, 245, 247, 29, 253, 32, 70, ++ 183, 247, 19, 253, 0, 32, 16, 189, 192, 159, 5, 0, 16, 181, 4, 70, 192, ++ 177, 34, 70, 12, 73, 64, 104, 243, 243, 4, 241, 34, 70, 96, 104, 10, ++ 73, 3, 240, 114, 252, 34, 70, 96, 104, 9, 73, 255, 247, 57, 251, 160, ++ 104, 8, 73, 34, 70, 251, 247, 220, 255, 32, 70, 189, 232, 16, 64, 183, ++ 247, 243, 188, 16, 189, 0, 191, 101, 33, 133, 0, 193, 39, 133, 0, 175, ++ 158, 2, 0, 247, 60, 4, 0, 112, 181, 5, 70, 134, 176, 24, 32, 183, 247, ++ 224, 252, 4, 70, 0, 40, 0, 240, 233, 128, 0, 33, 24, 34, 176, 243, 190, ++ 240, 43, 104, 0, 34, 163, 96, 171, 104, 101, 96, 227, 96, 107, 104, ++ 4, 33, 35, 97, 4, 35, 163, 130, 40, 70, 109, 75, 141, 232, 20, 0, 255, ++ 247, 227, 250, 0, 40, 32, 96, 192, 242, 204, 128, 40, 70, 105, 73, 34, ++ 70, 243, 243, 184, 240, 0, 40, 64, 240, 196, 128, 40, 70, 102, 73, 34, ++ 70, 255, 247, 240, 250, 0, 40, 64, 240, 188, 128, 40, 70, 99, 73, 34, ++ 70, 3, 240, 28, 252, 0, 40, 64, 240, 180, 128, 97, 75, 1, 144, 0, 147, ++ 2, 144, 3, 144, 4, 144, 5, 144, 94, 73, 40, 104, 94, 74, 35, 70, 251, ++ 247, 224, 255, 0, 40, 64, 240, 164, 128, 92, 73, 3, 34, 213, 248, 164, ++ 6, 2, 240, 157, 219, 90, 78, 90, 73, 2, 34, 213, 248, 168, 6, 2, 240, ++ 150, 219, 213, 248, 124, 6, 176, 33, 48, 34, 86, 75, 0, 150, 1, 148, ++ 0, 240, 77, 250, 0, 40, 64, 240, 139, 128, 83, 75, 213, 248, 124, 6, ++ 141, 232, 24, 0, 64, 246, 5, 1, 54, 34, 80, 75, 0, 240, 193, 250, 0, ++ 40, 125, 209, 79, 75, 213, 248, 124, 6, 141, 232, 24, 0, 64, 246, 4, ++ 1, 55, 34, 76, 75, 0, 240, 180, 250, 0, 40, 112, 209, 213, 248, 164, ++ 6, 48, 33, 68, 74, 51, 70, 0, 148, 0, 240, 63, 255, 0, 40, 102, 209, ++ 213, 248, 164, 6, 54, 33, 65, 74, 63, 75, 0, 148, 0, 240, 53, 255, 0, ++ 40, 92, 209, 213, 248, 164, 6, 55, 33, 62, 74, 60, 75, 0, 148, 0, 240, ++ 43, 255, 0, 40, 82, 209, 213, 248, 168, 6, 57, 33, 58, 74, 58, 75, 0, ++ 148, 0, 240, 33, 255, 0, 40, 72, 209, 213, 248, 124, 6, 192, 33, 54, ++ 34, 54, 75, 0, 148, 0, 240, 114, 252, 0, 40, 62, 209, 48, 33, 213, 248, ++ 124, 6, 10, 70, 50, 75, 0, 148, 0, 240, 36, 251, 0, 40, 52, 209, 213, ++ 248, 124, 6, 64, 246, 10, 1, 54, 34, 46, 75, 0, 148, 0, 240, 93, 252, ++ 80, 187, 213, 248, 124, 6, 64, 246, 10, 1, 55, 34, 42, 75, 0, 148, 0, ++ 240, 83, 252, 0, 187, 213, 248, 124, 6, 48, 33, 57, 34, 38, 75, 0, 148, ++ 0, 240, 74, 252, 184, 185, 213, 248, 164, 6, 48, 33, 31, 74, 35, 70, ++ 0, 240, 122, 255, 120, 185, 213, 248, 164, 6, 54, 33, 28, 74, 35, 70, ++ 0, 240, 114, 255, 56, 185, 213, 248, 164, 6, 55, 33, 25, 74, 35, 70, ++ 0, 240, 106, 255, 24, 177, 32, 70, 255, 247, 232, 254, 0, 36, 32, 70, ++ 6, 176, 112, 189, 205, 28, 133, 0, 101, 33, 133, 0, 175, 158, 2, 0, ++ 193, 39, 133, 0, 137, 30, 133, 0, 172, 230, 135, 0, 247, 60, 4, 0, 168, ++ 230, 135, 0, 69, 28, 133, 0, 208, 230, 135, 0, 1, 27, 133, 0, 185, 40, ++ 133, 0, 245, 29, 133, 0, 241, 39, 133, 0, 129, 29, 133, 0, 117, 30, ++ 133, 0, 21, 41, 133, 0, 21, 39, 133, 0, 81, 36, 133, 0, 17, 35, 133, ++ 0, 85, 34, 133, 0, 125, 35, 133, 0, 55, 181, 5, 70, 56, 32, 180, 243, ++ 177, 245, 4, 70, 80, 177, 79, 240, 255, 51, 5, 96, 5, 73, 1, 147, 5, ++ 74, 6, 75, 0, 149, 255, 243, 53, 247, 1, 224, 255, 243, 4, 247, 32, ++ 70, 62, 189, 169, 56, 133, 0, 177, 56, 133, 0, 161, 56, 133, 0, 112, ++ 181, 5, 70, 134, 176, 16, 32, 183, 247, 162, 251, 4, 70, 0, 40, 56, ++ 208, 0, 33, 16, 34, 175, 243, 129, 247, 0, 38, 37, 96, 1, 33, 197, 248, ++ 184, 70, 40, 70, 25, 74, 25, 75, 0, 150, 1, 148, 255, 247, 171, 249, ++ 176, 66, 224, 96, 33, 219, 22, 75, 40, 104, 141, 232, 72, 0, 21, 73, ++ 22, 74, 35, 70, 2, 150, 3, 150, 4, 150, 5, 150, 251, 247, 193, 254, ++ 152, 185, 18, 75, 213, 248, 124, 6, 141, 232, 40, 0, 5, 33, 190, 34, ++ 16, 75, 0, 240, 74, 250, 64, 185, 213, 248, 124, 6, 192, 33, 190, 34, ++ 13, 75, 0, 149, 0, 240, 43, 252, 24, 177, 32, 70, 183, 247, 106, 251, ++ 0, 36, 32, 70, 6, 176, 112, 189, 0, 191, 189, 59, 133, 0, 185, 59, 133, ++ 0, 169, 58, 133, 0, 204, 231, 135, 0, 199, 159, 5, 0, 141, 59, 133, ++ 0, 109, 59, 133, 0, 193, 59, 133, 0, 16, 181, 4, 70, 136, 177, 3, 121, ++ 35, 177, 128, 104, 183, 247, 77, 251, 0, 35, 35, 113, 35, 104, 5, 73, ++ 24, 104, 34, 70, 251, 247, 41, 254, 32, 70, 189, 232, 16, 64, 183, 247, ++ 64, 187, 16, 189, 199, 159, 5, 0, 8, 177, 183, 247, 58, 187, 112, 71, ++ 55, 181, 5, 70, 4, 32, 183, 247, 49, 251, 4, 70, 0, 40, 85, 208, 45, ++ 75, 5, 96, 64, 242, 63, 17, 0, 147, 1, 144, 45, 34, 213, 248, 124, 6, ++ 42, 75, 0, 240, 108, 249, 0, 40, 71, 209, 40, 75, 213, 248, 124, 6, ++ 141, 232, 24, 0, 79, 244, 149, 113, 61, 34, 37, 75, 0, 240, 95, 249, ++ 0, 40, 58, 209, 36, 75, 213, 248, 124, 6, 141, 232, 24, 0, 79, 244, ++ 149, 113, 74, 34, 33, 75, 0, 240, 82, 249, 112, 187, 32, 75, 213, 248, ++ 124, 6, 141, 232, 24, 0, 21, 33, 80, 34, 29, 75, 0, 240, 211, 249, 24, ++ 187, 213, 248, 124, 6, 5, 33, 45, 34, 26, 75, 0, 148, 0, 240, 46, 251, ++ 208, 185, 213, 248, 124, 6, 192, 33, 45, 34, 23, 75, 0, 148, 0, 240, ++ 37, 251, 136, 185, 213, 248, 124, 6, 192, 33, 61, 34, 19, 75, 0, 148, ++ 0, 240, 28, 251, 64, 185, 213, 248, 124, 6, 192, 33, 80, 34, 16, 75, ++ 0, 148, 0, 240, 153, 251, 24, 177, 32, 70, 255, 247, 155, 255, 0, 36, ++ 32, 70, 62, 189, 69, 63, 133, 0, 21, 60, 133, 0, 205, 63, 133, 0, 61, ++ 60, 133, 0, 141, 63, 133, 0, 37, 60, 133, 0, 241, 62, 133, 0, 253, 59, ++ 133, 0, 157, 60, 133, 0, 93, 61, 133, 0, 125, 61, 133, 0, 217, 60, 133, ++ 0, 16, 181, 4, 70, 160, 177, 3, 104, 128, 111, 0, 34, 90, 97, 8, 177, ++ 183, 247, 179, 250, 212, 248, 152, 0, 8, 177, 183, 247, 174, 250, 96, ++ 104, 8, 177, 183, 247, 170, 250, 32, 70, 189, 232, 16, 64, 183, 247, ++ 165, 186, 16, 189, 45, 233, 240, 65, 4, 70, 79, 244, 178, 112, 13, 70, ++ 22, 70, 152, 70, 180, 243, 137, 244, 7, 70, 16, 185, 64, 242, 242, 51, ++ 30, 224, 4, 96, 133, 96, 198, 96, 40, 32, 180, 243, 126, 244, 184, 103, ++ 16, 185, 64, 242, 243, 51, 19, 224, 88, 32, 180, 243, 118, 244, 199, ++ 248, 152, 0, 64, 177, 44, 48, 199, 248, 156, 0, 48, 32, 180, 243, 109, ++ 244, 120, 96, 96, 185, 2, 224, 79, 244, 125, 115, 1, 224, 64, 242, 245, ++ 51, 56, 70, 200, 248, 0, 48, 255, 247, 180, 255, 0, 39, 3, 224, 0, 35, ++ 200, 248, 0, 48, 96, 97, 56, 70, 189, 232, 240, 129, 0, 35, 194, 24, ++ 210, 248, 192, 32, 202, 80, 4, 51, 24, 43, 248, 209, 112, 71, 79, 244, ++ 200, 99, 192, 248, 76, 54, 104, 35, 192, 248, 80, 54, 79, 244, 128, ++ 115, 192, 248, 84, 54, 2, 35, 192, 248, 88, 54, 192, 248, 92, 54, 112, ++ 71, 0, 0, 16, 181, 4, 70, 80, 177, 3, 104, 5, 73, 24, 104, 34, 70, 251, ++ 247, 40, 253, 32, 70, 189, 232, 16, 64, 183, 247, 63, 186, 16, 189, ++ 0, 191, 100, 61, 4, 0, 1, 240, 240, 1, 45, 233, 240, 79, 14, 17, 1, ++ 104, 176, 248, 16, 128, 9, 104, 137, 176, 201, 105, 148, 70, 209, 248, ++ 192, 16, 7, 147, 136, 69, 4, 70, 176, 248, 18, 160, 131, 138, 199, 138, ++ 178, 178, 92, 218, 129, 121, 0, 41, 92, 209, 50, 77, 5, 235, 194, 0, ++ 128, 136, 6, 224, 85, 248, 50, 144, 25, 248, 1, 144, 225, 69, 2, 208, ++ 1, 49, 129, 66, 246, 211, 129, 66, 79, 208, 231, 25, 55, 248, 18, 176, ++ 1, 50, 55, 248, 18, 80, 162, 68, 69, 69, 35, 68, 26, 210, 197, 235, ++ 8, 8, 5, 241, 1, 9, 10, 235, 5, 1, 66, 70, 10, 235, 9, 0, 205, 248, ++ 20, 192, 6, 147, 175, 243, 184, 245, 6, 155, 12, 34, 2, 251, 9, 48, ++ 2, 251, 5, 49, 2, 251, 8, 242, 175, 243, 174, 245, 221, 248, 20, 192, ++ 6, 155, 49, 70, 0, 34, 7, 224, 7, 235, 70, 0, 48, 248, 2, 224, 14, 241, ++ 1, 14, 32, 248, 2, 224, 1, 49, 2, 50, 13, 41, 243, 217, 18, 153, 203, ++ 235, 5, 2, 0, 145, 19, 153, 10, 235, 11, 0, 1, 145, 12, 33, 1, 251, ++ 11, 49, 146, 178, 7, 155, 205, 248, 8, 192, 0, 240, 219, 250, 35, 138, ++ 0, 32, 1, 51, 35, 130, 7, 224, 111, 240, 21, 0, 4, 224, 111, 240, 22, ++ 0, 1, 224, 111, 240, 29, 0, 9, 176, 189, 232, 240, 143, 0, 191, 252, ++ 60, 4, 0, 45, 233, 243, 71, 221, 248, 40, 144, 221, 248, 44, 160, 7, ++ 70, 14, 70, 21, 70, 152, 70, 0, 36, 86, 250, 4, 243, 219, 7, 10, 213, ++ 33, 1, 56, 70, 1, 240, 240, 1, 42, 70, 67, 70, 141, 232, 0, 6, 255, ++ 247, 101, 255, 24, 185, 1, 52, 13, 44, 237, 209, 0, 32, 189, 232, 252, ++ 135, 45, 233, 240, 79, 137, 176, 7, 146, 2, 104, 176, 248, 24, 128, ++ 18, 104, 156, 70, 210, 105, 4, 70, 210, 248, 196, 32, 176, 248, 26, ++ 160, 144, 69, 131, 139, 199, 139, 80, 218, 130, 121, 0, 42, 80, 209, ++ 1, 240, 240, 6, 54, 17, 199, 25, 178, 178, 55, 248, 18, 176, 1, 50, ++ 55, 248, 18, 80, 130, 68, 69, 69, 3, 68, 26, 210, 197, 235, 8, 8, 5, ++ 241, 1, 9, 10, 235, 5, 1, 66, 70, 10, 235, 9, 0, 205, 248, 20, 192, ++ 6, 147, 175, 243, 38, 245, 6, 155, 12, 34, 2, 251, 9, 48, 2, 251, 5, ++ 49, 2, 251, 8, 242, 175, 243, 28, 245, 221, 248, 20, 192, 6, 155, 49, ++ 70, 0, 34, 7, 224, 7, 235, 70, 0, 48, 248, 2, 224, 14, 241, 1, 14, 32, ++ 248, 2, 224, 1, 49, 2, 50, 13, 41, 243, 217, 18, 153, 203, 235, 5, 2, ++ 0, 145, 19, 153, 10, 235, 11, 0, 1, 145, 7, 153, 146, 178, 2, 145, 12, ++ 33, 1, 251, 11, 49, 99, 70, 0, 240, 73, 250, 35, 139, 0, 32, 1, 51, ++ 35, 131, 4, 224, 111, 240, 21, 0, 1, 224, 111, 240, 22, 0, 9, 176, 189, ++ 232, 240, 143, 45, 233, 243, 71, 221, 248, 40, 144, 221, 248, 44, 160, ++ 7, 70, 14, 70, 21, 70, 152, 70, 0, 36, 86, 250, 4, 243, 218, 7, 10, ++ 213, 33, 1, 56, 70, 1, 240, 240, 1, 42, 70, 67, 70, 141, 232, 0, 6, ++ 255, 247, 123, 255, 24, 185, 1, 52, 13, 44, 237, 209, 0, 32, 189, 232, ++ 252, 135, 45, 233, 240, 79, 135, 176, 5, 146, 2, 104, 176, 248, 32, ++ 128, 18, 104, 156, 70, 210, 105, 4, 70, 210, 248, 200, 32, 176, 248, ++ 34, 160, 144, 69, 131, 140, 199, 140, 76, 218, 130, 121, 0, 42, 76, ++ 209, 1, 240, 240, 6, 54, 17, 199, 25, 178, 178, 55, 248, 18, 176, 1, ++ 50, 55, 248, 18, 80, 130, 68, 69, 69, 3, 68, 25, 210, 197, 235, 8, 8, ++ 5, 241, 1, 9, 10, 235, 5, 1, 66, 70, 10, 235, 9, 0, 205, 248, 12, 192, ++ 4, 147, 175, 243, 154, 244, 4, 155, 79, 234, 200, 2, 3, 235, 201, 0, ++ 3, 235, 197, 1, 175, 243, 145, 244, 221, 248, 12, 192, 4, 155, 49, 70, ++ 0, 34, 7, 224, 7, 235, 70, 0, 48, 248, 2, 224, 14, 241, 1, 14, 32, 248, ++ 2, 224, 1, 49, 2, 50, 13, 41, 243, 217, 16, 153, 203, 235, 5, 2, 0, ++ 145, 5, 153, 10, 235, 11, 0, 1, 145, 146, 178, 3, 235, 203, 1, 99, 70, ++ 0, 240, 209, 249, 35, 140, 0, 32, 1, 51, 35, 132, 4, 224, 111, 240, ++ 21, 0, 1, 224, 111, 240, 22, 0, 7, 176, 189, 232, 240, 143, 3, 104, ++ 240, 181, 219, 105, 12, 37, 179, 248, 192, 32, 6, 70, 5, 251, 2, 244, ++ 51, 50, 34, 240, 3, 2, 1, 52, 164, 24, 179, 248, 196, 32, 79, 246, 254, ++ 113, 2, 241, 31, 0, 106, 67, 33, 64, 65, 24, 80, 28, 79, 246, 252, 114, ++ 10, 64, 130, 24, 179, 248, 200, 0, 79, 246, 254, 113, 0, 241, 31, 4, ++ 17, 64, 97, 24, 192, 0, 79, 246, 252, 114, 10, 64, 179, 248, 204, 48, ++ 1, 48, 128, 24, 79, 246, 254, 114, 3, 241, 31, 1, 2, 64, 219, 0, 138, ++ 24, 89, 28, 79, 246, 252, 115, 19, 64, 203, 24, 79, 246, 254, 119, 31, ++ 64, 28, 55, 191, 178, 135, 176, 56, 70, 183, 247, 97, 248, 4, 70, 0, ++ 40, 0, 240, 132, 128, 0, 33, 58, 70, 175, 243, 63, 244, 48, 35, 99, ++ 130, 51, 104, 79, 246, 252, 114, 219, 105, 38, 96, 179, 248, 192, 16, ++ 167, 128, 1, 241, 51, 0, 2, 64, 5, 251, 1, 33, 162, 130, 1, 49, 79, ++ 246, 254, 114, 10, 64, 179, 248, 196, 16, 226, 130, 28, 50, 146, 178, ++ 200, 28, 16, 24, 98, 131, 79, 246, 252, 114, 2, 64, 5, 251, 1, 33, 162, ++ 131, 1, 49, 79, 246, 254, 114, 10, 64, 179, 248, 200, 16, 226, 131, ++ 28, 50, 146, 178, 200, 28, 16, 24, 98, 132, 79, 246, 252, 114, 2, 64, ++ 2, 235, 193, 1, 1, 49, 162, 132, 79, 246, 254, 114, 10, 64, 179, 248, ++ 204, 16, 226, 132, 28, 50, 146, 178, 203, 28, 98, 133, 210, 24, 79, ++ 246, 252, 115, 19, 64, 163, 133, 3, 235, 193, 3, 1, 51, 79, 246, 254, ++ 114, 26, 64, 226, 133, 0, 37, 29, 79, 87, 248, 53, 48, 99, 177, 28, ++ 75, 41, 1, 141, 232, 24, 0, 221, 34, 32, 70, 1, 240, 240, 1, 25, 75, ++ 255, 247, 198, 253, 0, 40, 34, 219, 1, 53, 13, 45, 235, 209, 0, 37, ++ 87, 248, 53, 48, 83, 177, 41, 1, 221, 34, 32, 70, 1, 240, 240, 1, 17, ++ 75, 0, 148, 255, 247, 226, 254, 0, 40, 16, 219, 1, 53, 13, 45, 238, ++ 209, 14, 75, 0, 33, 2, 147, 48, 104, 13, 74, 35, 70, 0, 145, 1, 145, ++ 3, 145, 4, 145, 5, 145, 251, 247, 28, 251, 24, 177, 32, 70, 255, 247, ++ 140, 253, 0, 36, 32, 70, 7, 176, 240, 189, 252, 60, 4, 0, 145, 65, 133, ++ 0, 229, 65, 133, 0, 49, 66, 133, 0, 29, 65, 133, 0, 100, 61, 4, 0, 45, ++ 233, 247, 67, 221, 248, 40, 144, 7, 70, 14, 70, 21, 70, 152, 70, 0, ++ 36, 86, 250, 4, 243, 217, 7, 10, 213, 33, 1, 56, 70, 1, 240, 240, 1, ++ 42, 70, 67, 70, 205, 248, 0, 144, 255, 247, 165, 254, 24, 185, 1, 52, ++ 13, 44, 237, 209, 0, 32, 189, 232, 254, 131, 45, 233, 240, 79, 135, ++ 176, 5, 146, 2, 104, 176, 248, 40, 128, 18, 104, 156, 70, 210, 105, ++ 4, 70, 210, 248, 204, 32, 176, 248, 42, 160, 144, 69, 131, 141, 199, ++ 141, 76, 218, 130, 121, 0, 42, 76, 209, 1, 240, 240, 6, 54, 17, 199, ++ 25, 178, 178, 55, 248, 18, 176, 1, 50, 55, 248, 18, 80, 130, 68, 69, ++ 69, 3, 68, 25, 210, 197, 235, 8, 8, 5, 241, 1, 9, 10, 235, 5, 1, 66, ++ 70, 10, 235, 9, 0, 205, 248, 12, 192, 4, 147, 175, 243, 56, 243, 4, ++ 155, 79, 234, 200, 2, 3, 235, 201, 0, 3, 235, 197, 1, 175, 243, 47, ++ 243, 221, 248, 12, 192, 4, 155, 49, 70, 0, 34, 7, 224, 7, 235, 70, 0, ++ 48, 248, 2, 224, 14, 241, 1, 14, 32, 248, 2, 224, 1, 49, 2, 50, 13, ++ 41, 243, 217, 16, 153, 203, 235, 5, 2, 0, 145, 5, 153, 10, 235, 11, ++ 0, 1, 145, 146, 178, 3, 235, 203, 1, 99, 70, 0, 240, 111, 248, 35, 141, ++ 0, 32, 1, 51, 35, 133, 4, 224, 111, 240, 21, 0, 1, 224, 111, 240, 22, ++ 0, 7, 176, 189, 232, 240, 143, 45, 233, 247, 67, 221, 248, 40, 144, ++ 7, 70, 14, 70, 21, 70, 152, 70, 0, 36, 86, 250, 4, 243, 216, 7, 10, ++ 213, 33, 1, 56, 70, 1, 240, 240, 1, 42, 70, 67, 70, 205, 248, 0, 144, ++ 255, 247, 129, 255, 24, 185, 1, 52, 13, 44, 237, 209, 0, 32, 189, 232, ++ 254, 131, 45, 233, 240, 71, 8, 159, 154, 70, 4, 70, 157, 248, 36, 96, ++ 3, 70, 0, 37, 12, 224, 19, 248, 1, 11, 134, 66, 10, 208, 29, 177, 19, ++ 248, 2, 236, 182, 69, 1, 210, 134, 66, 3, 217, 1, 53, 173, 178, 149, ++ 66, 240, 209, 170, 66, 7, 251, 5, 24, 14, 217, 197, 235, 2, 9, 65, 70, ++ 7, 251, 9, 242, 8, 235, 7, 0, 175, 243, 190, 242, 104, 28, 32, 24, 97, ++ 25, 74, 70, 175, 243, 184, 242, 64, 70, 81, 70, 58, 70, 173, 247, 87, ++ 255, 102, 85, 189, 232, 240, 135, 127, 181, 3, 147, 8, 155, 4, 147, ++ 9, 155, 5, 147, 12, 35, 0, 147, 157, 248, 40, 48, 1, 147, 3, 171, 255, ++ 247, 190, 255, 7, 176, 0, 189, 31, 181, 2, 147, 6, 155, 3, 147, 8, 35, ++ 0, 147, 157, 248, 28, 48, 1, 147, 2, 171, 255, 247, 176, 255, 5, 176, ++ 0, 189, 55, 181, 37, 75, 208, 248, 124, 86, 4, 70, 0, 147, 1, 144, 64, ++ 242, 63, 17, 40, 70, 127, 34, 33, 75, 255, 247, 12, 253, 0, 40, 58, ++ 209, 31, 75, 40, 70, 141, 232, 24, 0, 65, 246, 63, 81, 64, 34, 29, 75, ++ 255, 247, 140, 253, 120, 187, 28, 75, 40, 70, 141, 232, 24, 0, 64, 246, ++ 63, 17, 152, 34, 25, 75, 255, 247, 129, 253, 32, 187, 24, 75, 40, 70, ++ 141, 232, 24, 0, 64, 242, 47, 17, 168, 34, 22, 75, 255, 247, 118, 253, ++ 200, 185, 40, 70, 64, 242, 15, 17, 127, 34, 19, 75, 0, 148, 255, 247, ++ 209, 254, 128, 185, 40, 70, 64, 242, 15, 17, 152, 34, 15, 75, 0, 148, ++ 255, 247, 78, 255, 56, 185, 40, 70, 64, 242, 15, 17, 168, 34, 12, 75, ++ 0, 148, 255, 247, 69, 255, 62, 189, 5, 165, 2, 0, 97, 165, 2, 0, 1, ++ 91, 133, 0, 169, 87, 133, 0, 181, 90, 133, 0, 137, 87, 133, 0, 121, ++ 91, 133, 0, 29, 88, 133, 0, 205, 88, 133, 0, 141, 88, 133, 0, 117, 161, ++ 2, 0, 55, 181, 16, 75, 208, 248, 124, 86, 4, 70, 0, 147, 1, 144, 5, ++ 33, 40, 70, 0, 34, 12, 75, 255, 247, 171, 252, 144, 185, 11, 75, 40, ++ 70, 141, 232, 24, 0, 5, 33, 1, 34, 9, 75, 255, 247, 161, 252, 64, 185, ++ 8, 75, 40, 70, 141, 232, 24, 0, 5, 33, 50, 34, 6, 75, 255, 247, 151, ++ 252, 62, 189, 113, 82, 133, 0, 57, 82, 133, 0, 141, 82, 133, 0, 69, ++ 82, 133, 0, 85, 82, 133, 0, 41, 82, 133, 0, 55, 181, 37, 75, 208, 248, ++ 124, 86, 4, 70, 0, 147, 1, 144, 79, 244, 144, 113, 40, 70, 0, 34, 33, ++ 75, 255, 247, 124, 252, 0, 40, 58, 209, 31, 75, 40, 70, 141, 232, 24, ++ 0, 79, 244, 144, 113, 1, 34, 29, 75, 255, 247, 112, 252, 120, 187, 28, ++ 75, 40, 70, 141, 232, 24, 0, 79, 244, 144, 113, 50, 34, 25, 75, 255, ++ 247, 101, 252, 32, 187, 24, 75, 40, 70, 141, 232, 24, 0, 79, 244, 144, ++ 113, 3, 34, 22, 75, 255, 247, 90, 252, 200, 185, 21, 75, 40, 70, 141, ++ 232, 24, 0, 79, 244, 144, 113, 6, 34, 18, 75, 255, 247, 79, 252, 112, ++ 185, 40, 70, 128, 33, 5, 34, 16, 75, 0, 148, 255, 247, 243, 252, 48, ++ 185, 40, 70, 128, 33, 5, 34, 13, 75, 0, 148, 255, 247, 235, 252, 62, ++ 189, 49, 87, 133, 0, 177, 84, 133, 0, 109, 87, 133, 0, 185, 84, 133, ++ 0, 213, 86, 133, 0, 109, 84, 133, 0, 169, 86, 133, 0, 89, 84, 133, 0, ++ 253, 86, 133, 0, 137, 84, 133, 0, 189, 165, 2, 0, 73, 86, 133, 0, 55, ++ 181, 21, 75, 208, 248, 124, 86, 4, 70, 0, 147, 1, 144, 64, 33, 40, 70, ++ 0, 34, 17, 75, 255, 247, 151, 251, 224, 185, 16, 75, 40, 70, 141, 232, ++ 24, 0, 64, 33, 1, 34, 14, 75, 255, 247, 141, 251, 144, 185, 13, 75, ++ 40, 70, 141, 232, 24, 0, 64, 33, 50, 34, 11, 75, 255, 247, 131, 251, ++ 64, 185, 10, 75, 40, 70, 141, 232, 24, 0, 64, 33, 3, 34, 8, 75, 255, ++ 247, 121, 251, 62, 189, 237, 92, 133, 0, 145, 92, 133, 0, 5, 93, 133, ++ 0, 157, 92, 133, 0, 209, 92, 133, 0, 129, 92, 133, 0, 169, 92, 133, ++ 0, 113, 92, 133, 0, 55, 181, 10, 75, 208, 248, 124, 86, 4, 70, 0, 147, ++ 1, 144, 176, 33, 40, 70, 16, 34, 6, 75, 255, 247, 91, 251, 48, 185, ++ 40, 70, 176, 33, 16, 34, 4, 75, 0, 148, 255, 247, 129, 252, 62, 189, ++ 141, 83, 133, 0, 169, 82, 133, 0, 213, 82, 133, 0, 55, 181, 208, 248, ++ 124, 86, 4, 70, 0, 144, 192, 33, 40, 70, 0, 34, 17, 75, 255, 247, 179, ++ 253, 240, 185, 40, 70, 192, 33, 1, 34, 15, 75, 0, 148, 255, 247, 171, ++ 253, 176, 185, 40, 70, 192, 33, 6, 34, 12, 75, 0, 148, 255, 247, 163, ++ 253, 112, 185, 40, 70, 192, 33, 168, 34, 9, 75, 0, 148, 255, 247, 33, ++ 254, 48, 185, 40, 70, 192, 33, 152, 34, 6, 75, 0, 148, 255, 247, 25, ++ 254, 62, 189, 89, 93, 133, 0, 129, 93, 133, 0, 57, 93, 133, 0, 157, ++ 93, 133, 0, 33, 93, 133, 0, 16, 181, 4, 70, 80, 177, 3, 104, 5, 73, ++ 24, 104, 34, 70, 251, 247, 44, 248, 32, 70, 189, 232, 16, 64, 182, 247, ++ 67, 189, 16, 189, 0, 191, 179, 61, 4, 0, 56, 181, 5, 70, 12, 32, 182, ++ 247, 55, 253, 4, 70, 56, 177, 0, 33, 12, 34, 175, 243, 23, 241, 12, ++ 35, 37, 96, 163, 128, 1, 224, 255, 247, 221, 255, 32, 70, 56, 189, 40, ++ 177, 131, 104, 218, 136, 1, 58, 218, 128, 182, 247, 37, 189, 112, 71, ++ 45, 233, 240, 79, 155, 70, 3, 139, 135, 176, 197, 24, 198, 90, 181, ++ 248, 4, 128, 67, 138, 198, 235, 8, 8, 152, 69, 5, 145, 148, 70, 135, ++ 138, 176, 248, 22, 160, 50, 218, 108, 136, 199, 25, 68, 69, 130, 68, ++ 22, 218, 196, 235, 8, 8, 4, 241, 1, 9, 57, 25, 66, 70, 7, 235, 9, 0, ++ 205, 248, 16, 192, 175, 243, 191, 240, 12, 34, 2, 251, 9, 160, 2, 251, ++ 4, 161, 2, 251, 8, 242, 175, 243, 182, 240, 221, 248, 16, 192, 107, ++ 136, 162, 27, 1, 51, 107, 128, 171, 136, 12, 33, 1, 51, 171, 128, 16, ++ 155, 184, 25, 1, 147, 5, 155, 1, 251, 6, 161, 2, 147, 146, 178, 99, ++ 70, 205, 248, 0, 176, 255, 247, 239, 253, 0, 32, 1, 224, 111, 240, 21, ++ 0, 7, 176, 189, 232, 240, 143, 45, 233, 240, 79, 155, 70, 3, 139, 148, ++ 70, 197, 24, 172, 136, 48, 248, 3, 128, 66, 138, 200, 235, 4, 3, 135, ++ 176, 147, 66, 5, 145, 135, 138, 176, 248, 22, 160, 47, 218, 156, 66, ++ 7, 68, 130, 68, 110, 136, 22, 218, 200, 241, 0, 8, 4, 241, 1, 9, 57, ++ 25, 66, 70, 7, 235, 9, 0, 205, 248, 16, 192, 175, 243, 116, 240, 12, ++ 34, 2, 251, 9, 160, 2, 251, 4, 161, 2, 251, 8, 242, 175, 243, 107, 240, ++ 221, 248, 16, 192, 171, 136, 162, 27, 1, 51, 171, 128, 16, 155, 12, ++ 33, 1, 147, 5, 155, 184, 25, 2, 147, 1, 251, 6, 161, 146, 178, 99, 70, ++ 205, 248, 0, 176, 255, 247, 167, 253, 0, 32, 1, 224, 111, 240, 21, 0, ++ 7, 176, 189, 232, 240, 143, 45, 233, 240, 79, 155, 70, 3, 140, 133, ++ 176, 197, 24, 198, 90, 181, 248, 4, 128, 67, 139, 198, 235, 8, 8, 152, ++ 69, 3, 145, 148, 70, 135, 139, 176, 248, 30, 160, 46, 218, 108, 136, ++ 199, 25, 68, 69, 130, 68, 21, 218, 196, 235, 8, 8, 4, 241, 1, 9, 57, ++ 25, 66, 70, 7, 235, 9, 0, 205, 248, 8, 192, 175, 243, 44, 240, 10, 235, ++ 201, 0, 10, 235, 196, 1, 79, 234, 200, 2, 175, 243, 36, 240, 221, 248, ++ 8, 192, 107, 136, 162, 27, 1, 51, 107, 128, 171, 136, 184, 25, 1, 51, ++ 171, 128, 3, 155, 10, 235, 198, 1, 1, 147, 146, 178, 99, 70, 205, 248, ++ 0, 176, 255, 247, 112, 253, 0, 32, 1, 224, 111, 240, 21, 0, 5, 176, ++ 189, 232, 240, 143, 0, 0, 45, 233, 240, 79, 3, 104, 133, 176, 3, 147, ++ 27, 104, 21, 70, 219, 105, 194, 136, 211, 248, 208, 48, 7, 70, 154, ++ 66, 14, 70, 91, 218, 9, 177, 78, 28, 182, 178, 13, 177, 1, 53, 173, ++ 178, 6, 241, 39, 3, 79, 246, 252, 122, 3, 234, 10, 10, 12, 35, 3, 251, ++ 6, 163, 79, 246, 254, 120, 1, 51, 3, 234, 8, 8, 8, 241, 9, 3, 235, 24, ++ 79, 246, 252, 123, 3, 234, 11, 11, 11, 235, 197, 2, 1, 50, 79, 246, ++ 254, 115, 19, 64, 3, 241, 6, 9, 31, 250, 137, 249, 72, 70, 2, 147, 182, ++ 247, 14, 252, 4, 70, 0, 40, 48, 208, 0, 33, 74, 70, 174, 243, 237, 247, ++ 2, 155, 3, 153, 35, 132, 251, 136, 164, 248, 24, 128, 36, 34, 8, 241, ++ 6, 8, 1, 51, 33, 96, 167, 96, 164, 248, 16, 144, 162, 130, 164, 248, ++ 22, 160, 164, 248, 28, 128, 164, 248, 30, 176, 102, 130, 101, 131, 251, ++ 128, 70, 177, 221, 33, 32, 70, 12, 74, 13, 75, 0, 148, 255, 247, 198, ++ 254, 0, 40, 10, 219, 109, 177, 221, 33, 32, 70, 9, 74, 35, 70, 255, ++ 247, 80, 255, 0, 40, 5, 218, 0, 224, 0, 36, 32, 70, 255, 247, 174, 254, ++ 0, 36, 32, 70, 5, 176, 189, 232, 240, 143, 9, 96, 133, 0, 197, 95, 133, ++ 0, 65, 96, 133, 0, 127, 181, 11, 74, 3, 70, 0, 146, 0, 34, 1, 146, 2, ++ 146, 3, 146, 8, 74, 9, 73, 4, 146, 9, 74, 5, 146, 0, 104, 8, 74, 250, ++ 247, 253, 254, 0, 40, 20, 191, 79, 240, 255, 48, 0, 32, 7, 176, 0, 189, ++ 81, 140, 133, 0, 216, 61, 4, 0, 60, 234, 135, 0, 199, 177, 2, 0, 183, ++ 61, 4, 0, 2, 70, 2, 73, 0, 104, 250, 247, 140, 190, 0, 191, 183, 61, ++ 4, 0, 16, 181, 4, 70, 72, 177, 3, 104, 33, 70, 24, 104, 250, 247, 160, ++ 255, 32, 70, 189, 232, 16, 64, 182, 247, 152, 187, 16, 189, 55, 181, ++ 5, 70, 8, 32, 179, 243, 129, 245, 4, 70, 160, 177, 5, 96, 0, 34, 1, ++ 144, 12, 33, 40, 70, 10, 75, 0, 146, 254, 247, 160, 249, 0, 40, 96, ++ 96, 8, 219, 8, 75, 40, 104, 0, 147, 33, 70, 7, 74, 4, 35, 250, 247, ++ 14, 255, 24, 177, 32, 70, 255, 247, 211, 255, 0, 36, 32, 70, 62, 189, ++ 221, 146, 133, 0, 216, 234, 135, 0, 241, 146, 133, 0, 16, 181, 4, 70, ++ 192, 104, 24, 177, 182, 247, 105, 251, 0, 35, 227, 96, 16, 189, 16, ++ 181, 4, 70, 160, 32, 182, 247, 94, 251, 112, 177, 224, 96, 160, 96, ++ 0, 241, 144, 2, 3, 70, 16, 51, 147, 66, 67, 248, 16, 60, 250, 209, 0, ++ 35, 192, 248, 144, 48, 24, 70, 16, 189, 111, 240, 26, 0, 16, 189, 0, ++ 0, 56, 181, 4, 70, 0, 40, 82, 208, 0, 33, 5, 104, 5, 240, 12, 221, 32, ++ 70, 5, 240, 233, 218, 99, 105, 51, 177, 32, 70, 0, 33, 214, 247, 121, ++ 253, 96, 105, 254, 243, 142, 246, 163, 105, 51, 177, 32, 70, 1, 33, ++ 214, 247, 112, 253, 160, 105, 254, 243, 133, 246, 35, 105, 51, 177, ++ 32, 70, 2, 33, 214, 247, 103, 253, 32, 105, 254, 243, 124, 246, 227, ++ 111, 51, 177, 32, 70, 3, 33, 214, 247, 94, 253, 224, 111, 254, 243, ++ 115, 246, 32, 70, 7, 240, 82, 219, 212, 248, 152, 0, 182, 247, 23, 251, ++ 1, 224, 214, 247, 15, 255, 225, 105, 32, 70, 0, 41, 249, 209, 255, 247, ++ 159, 255, 213, 248, 72, 1, 24, 177, 10, 73, 42, 70, 0, 240, 149, 249, ++ 40, 104, 9, 73, 34, 70, 250, 247, 230, 253, 212, 248, 168, 48, 27, 177, ++ 4, 241, 168, 0, 174, 243, 222, 240, 32, 70, 189, 232, 56, 64, 182, 247, ++ 246, 186, 56, 189, 201, 172, 133, 0, 203, 174, 136, 0, 48, 181, 5, 70, ++ 135, 176, 176, 32, 182, 247, 232, 250, 4, 70, 0, 40, 0, 240, 155, 128, ++ 0, 33, 176, 34, 174, 243, 198, 246, 10, 35, 132, 248, 67, 48, 1, 35, ++ 132, 248, 72, 48, 255, 35, 132, 248, 32, 48, 132, 248, 33, 48, 132, ++ 248, 34, 48, 132, 248, 35, 48, 37, 96, 196, 32, 182, 247, 205, 250, ++ 196, 248, 152, 0, 0, 40, 127, 208, 32, 70, 5, 240, 130, 220, 32, 70, ++ 5, 240, 137, 223, 43, 104, 65, 242, 107, 2, 211, 248, 216, 48, 32, 240, ++ 127, 0, 25, 107, 160, 135, 145, 66, 32, 70, 8, 209, 155, 106, 147, 43, ++ 5, 209, 5, 240, 120, 223, 192, 245, 132, 64, 104, 48, 1, 224, 5, 240, ++ 118, 223, 224, 135, 227, 143, 32, 70, 35, 240, 127, 3, 227, 135, 5, ++ 240, 110, 223, 0, 35, 227, 100, 65, 242, 136, 51, 35, 101, 46, 75, 32, ++ 240, 127, 0, 164, 248, 64, 0, 0, 147, 44, 75, 40, 104, 1, 147, 43, 75, ++ 44, 73, 2, 147, 44, 75, 44, 74, 3, 147, 44, 75, 4, 147, 44, 75, 5, 147, ++ 35, 70, 250, 247, 203, 253, 0, 40, 61, 209, 213, 248, 208, 5, 254, 243, ++ 173, 245, 96, 97, 0, 40, 54, 208, 213, 248, 208, 5, 254, 243, 166, 245, ++ 160, 97, 128, 179, 213, 248, 208, 5, 254, 243, 160, 245, 32, 97, 80, ++ 179, 32, 70, 255, 247, 14, 255, 48, 187, 213, 248, 208, 5, 254, 243, ++ 150, 245, 224, 103, 0, 179, 1, 35, 132, 248, 120, 48, 213, 248, 72, ++ 1, 65, 242, 112, 115, 164, 248, 122, 48, 32, 177, 22, 73, 42, 70, 0, ++ 240, 234, 248, 136, 185, 32, 70, 1, 33, 5, 240, 33, 220, 79, 244, 72, ++ 67, 163, 101, 0, 35, 227, 101, 50, 35, 35, 102, 213, 248, 32, 6, 4, ++ 241, 168, 1, 174, 243, 26, 240, 24, 177, 32, 70, 255, 247, 252, 254, ++ 0, 36, 32, 70, 7, 176, 48, 189, 181, 159, 133, 0, 73, 189, 133, 0, 17, ++ 189, 133, 0, 248, 234, 135, 0, 157, 162, 133, 0, 203, 174, 136, 0, 8, ++ 62, 4, 0, 207, 181, 2, 0, 201, 172, 133, 0, 56, 181, 4, 70, 0, 40, 39, ++ 208, 5, 104, 20, 73, 40, 104, 34, 70, 250, 247, 13, 253, 35, 106, 27, ++ 177, 4, 241, 32, 0, 174, 243, 6, 240, 227, 105, 27, 177, 4, 241, 28, ++ 0, 174, 243, 0, 240, 163, 105, 27, 177, 4, 241, 24, 0, 173, 243, 250, ++ 247, 99, 105, 27, 177, 4, 241, 20, 0, 173, 243, 244, 247, 40, 70, 6, ++ 73, 34, 70, 254, 247, 72, 248, 32, 70, 189, 232, 56, 64, 182, 247, 7, ++ 186, 56, 189, 0, 191, 105, 177, 136, 0, 25, 204, 133, 0, 112, 181, 5, ++ 70, 134, 176, 48, 32, 179, 243, 234, 243, 4, 70, 0, 40, 89, 208, 79, ++ 240, 255, 51, 3, 97, 4, 34, 255, 33, 5, 96, 10, 48, 174, 243, 210, 245, ++ 11, 33, 4, 241, 14, 0, 175, 243, 151, 247, 0, 35, 141, 232, 24, 0, 4, ++ 33, 40, 70, 38, 74, 39, 75, 253, 247, 250, 255, 0, 40, 96, 96, 63, 219, ++ 40, 70, 36, 73, 34, 70, 254, 247, 16, 248, 0, 40, 56, 209, 213, 248, ++ 32, 102, 4, 241, 20, 1, 48, 70, 173, 243, 157, 247, 0, 40, 47, 209, ++ 48, 70, 4, 241, 24, 1, 173, 243, 150, 247, 72, 187, 48, 70, 4, 241, ++ 28, 1, 173, 243, 144, 247, 24, 187, 48, 70, 4, 241, 32, 1, 173, 243, ++ 138, 247, 232, 185, 21, 75, 1, 144, 0, 147, 20, 75, 4, 144, 2, 147, ++ 20, 75, 5, 144, 3, 147, 40, 104, 19, 73, 19, 74, 35, 70, 250, 247, 236, ++ 252, 104, 185, 32, 70, 8, 240, 168, 217, 32, 177, 32, 70, 1, 33, 8, ++ 240, 215, 217, 32, 185, 50, 35, 163, 98, 38, 35, 99, 98, 3, 224, 32, ++ 70, 255, 247, 104, 255, 0, 36, 32, 70, 6, 176, 112, 189, 49, 205, 133, ++ 0, 233, 204, 133, 0, 25, 204, 133, 0, 149, 204, 133, 0, 61, 207, 133, ++ 0, 229, 204, 133, 0, 232, 235, 135, 0, 105, 177, 136, 0, 64, 105, 173, ++ 243, 45, 183, 64, 105, 173, 243, 140, 183, 128, 105, 173, 243, 39, 183, ++ 128, 105, 173, 243, 134, 183, 192, 105, 173, 243, 33, 183, 192, 105, ++ 173, 243, 128, 183, 0, 106, 173, 243, 27, 183, 0, 106, 173, 243, 122, ++ 183, 56, 181, 4, 70, 96, 177, 5, 104, 34, 70, 6, 73, 40, 104, 250, 247, ++ 74, 252, 32, 70, 182, 247, 99, 249, 43, 104, 0, 34, 131, 248, 78, 32, ++ 56, 189, 0, 191, 19, 178, 136, 0, 112, 181, 3, 104, 0, 38, 134, 176, ++ 5, 70, 131, 248, 78, 96, 12, 32, 179, 243, 64, 243, 4, 70, 0, 40, 69, ++ 208, 36, 75, 5, 96, 141, 232, 72, 0, 35, 75, 40, 104, 4, 147, 34, 75, ++ 35, 73, 5, 147, 35, 74, 35, 70, 2, 150, 3, 150, 250, 247, 125, 252, ++ 6, 70, 0, 40, 46, 209, 141, 232, 17, 0, 28, 33, 40, 70, 29, 74, 30, ++ 75, 253, 247, 76, 255, 0, 40, 96, 96, 35, 219, 12, 33, 40, 70, 27, 74, ++ 27, 75, 0, 150, 1, 148, 1, 240, 91, 254, 0, 40, 160, 96, 24, 219, 24, ++ 75, 213, 248, 124, 6, 141, 232, 24, 0, 10, 33, 56, 34, 22, 75, 254, ++ 247, 98, 255, 104, 185, 213, 248, 124, 6, 10, 33, 56, 34, 19, 75, 0, ++ 149, 255, 247, 73, 249, 32, 185, 43, 104, 1, 34, 131, 248, 78, 32, 3, ++ 224, 32, 70, 255, 247, 154, 255, 0, 36, 32, 70, 6, 176, 112, 189, 21, ++ 220, 133, 0, 48, 62, 4, 0, 73, 204, 2, 0, 0, 236, 135, 0, 19, 178, 136, ++ 0, 1, 220, 133, 0, 245, 219, 133, 0, 185, 224, 133, 0, 133, 224, 133, ++ 0, 113, 225, 133, 0, 65, 225, 133, 0, 129, 203, 2, 0, 112, 181, 6, 70, ++ 134, 176, 8, 32, 182, 247, 228, 248, 4, 70, 160, 177, 11, 75, 0, 37, ++ 6, 96, 69, 96, 10, 73, 141, 232, 40, 0, 48, 104, 9, 74, 35, 70, 2, 149, ++ 3, 149, 4, 149, 5, 149, 250, 247, 20, 252, 24, 177, 32, 70, 182, 247, ++ 209, 248, 44, 70, 32, 70, 6, 176, 112, 189, 213, 231, 133, 0, 56, 236, ++ 135, 0, 207, 61, 4, 0, 16, 181, 4, 70, 80, 177, 3, 104, 5, 73, 24, 104, ++ 34, 70, 250, 247, 162, 251, 32, 70, 189, 232, 16, 64, 182, 247, 185, ++ 184, 16, 189, 0, 191, 207, 61, 4, 0, 112, 181, 4, 70, 0, 40, 45, 208, ++ 6, 104, 34, 70, 22, 73, 48, 104, 214, 248, 72, 81, 250, 247, 141, 251, ++ 32, 70, 12, 240, 25, 222, 34, 70, 48, 70, 18, 73, 253, 247, 221, 254, ++ 34, 70, 48, 70, 16, 73, 253, 247, 228, 254, 34, 70, 40, 70, 15, 73, ++ 255, 247, 19, 255, 34, 70, 40, 70, 13, 73, 255, 247, 20, 255, 34, 70, ++ 40, 70, 12, 73, 255, 247, 21, 255, 40, 70, 11, 73, 34, 70, 255, 247, ++ 22, 255, 32, 70, 189, 232, 112, 64, 182, 247, 131, 184, 112, 189, 0, ++ 191, 160, 185, 136, 0, 61, 246, 133, 0, 229, 6, 134, 0, 221, 243, 133, ++ 0, 201, 245, 133, 0, 241, 27, 134, 0, 17, 2, 134, 0, 240, 181, 208, ++ 248, 72, 97, 135, 176, 5, 70, 88, 32, 182, 247, 104, 248, 4, 70, 0, ++ 40, 0, 240, 149, 128, 0, 33, 88, 34, 174, 243, 70, 244, 32, 70, 32, ++ 33, 74, 74, 64, 248, 32, 91, 174, 243, 165, 244, 1, 39, 79, 240, 255, ++ 51, 224, 97, 132, 248, 64, 112, 164, 248, 76, 48, 48, 70, 68, 73, 34, ++ 70, 255, 247, 200, 254, 0, 40, 122, 209, 48, 70, 66, 73, 34, 70, 255, ++ 247, 199, 254, 0, 40, 115, 209, 48, 70, 63, 73, 34, 70, 255, 247, 198, ++ 254, 0, 40, 108, 209, 48, 70, 61, 73, 34, 70, 255, 247, 197, 254, 0, ++ 40, 101, 209, 40, 70, 58, 73, 34, 70, 253, 247, 118, 254, 6, 70, 0, ++ 40, 93, 209, 141, 232, 17, 0, 4, 33, 40, 70, 54, 74, 54, 75, 253, 247, ++ 65, 254, 0, 40, 32, 97, 82, 219, 40, 70, 57, 70, 50, 70, 51, 70, 0, ++ 150, 1, 148, 253, 247, 54, 254, 0, 40, 96, 97, 71, 219, 4, 33, 40, 70, ++ 46, 74, 46, 75, 0, 150, 1, 148, 1, 240, 69, 253, 0, 40, 160, 97, 60, ++ 219, 40, 70, 43, 73, 34, 70, 253, 247, 65, 254, 0, 40, 53, 209, 41, ++ 75, 3, 235, 198, 2, 83, 248, 54, 48, 99, 177, 82, 104, 82, 177, 49, ++ 1, 141, 232, 20, 0, 213, 248, 124, 6, 1, 240, 240, 1, 192, 34, 254, ++ 247, 93, 254, 16, 187, 1, 54, 13, 46, 233, 209, 31, 75, 31, 74, 0, 147, ++ 0, 35, 1, 147, 3, 147, 30, 75, 2, 146, 4, 147, 29, 75, 40, 104, 5, 147, ++ 29, 73, 29, 74, 35, 70, 250, 247, 32, 251, 104, 185, 32, 70, 12, 240, ++ 66, 223, 32, 177, 32, 70, 1, 33, 10, 240, 77, 221, 32, 185, 99, 108, ++ 67, 240, 4, 3, 99, 100, 3, 224, 32, 70, 255, 247, 26, 255, 0, 36, 32, ++ 70, 7, 176, 240, 189, 72, 62, 4, 0, 221, 243, 133, 0, 201, 245, 133, ++ 0, 241, 27, 134, 0, 17, 2, 134, 0, 229, 6, 134, 0, 109, 1, 134, 0, 245, ++ 0, 134, 0, 49, 15, 134, 0, 29, 15, 134, 0, 61, 246, 133, 0, 204, 159, ++ 5, 0, 97, 249, 133, 0, 121, 28, 134, 0, 80, 62, 4, 0, 149, 206, 2, 0, ++ 88, 237, 135, 0, 160, 185, 136, 0, 56, 181, 4, 70, 208, 177, 128, 104, ++ 8, 177, 181, 247, 160, 255, 35, 105, 67, 185, 14, 224, 35, 105, 83, ++ 248, 53, 0, 8, 177, 181, 247, 151, 255, 1, 53, 0, 224, 0, 37, 227, 104, ++ 157, 66, 243, 219, 32, 105, 181, 247, 142, 255, 32, 70, 189, 232, 56, ++ 64, 181, 247, 137, 191, 56, 189, 0, 0, 45, 233, 240, 65, 5, 70, 24, ++ 32, 179, 243, 112, 241, 4, 70, 0, 40, 51, 208, 43, 104, 5, 96, 219, ++ 105, 12, 32, 219, 105, 1, 51, 88, 67, 179, 243, 100, 241, 160, 96, 64, ++ 179, 43, 104, 24, 32, 219, 105, 218, 105, 91, 111, 98, 96, 227, 96, ++ 181, 247, 103, 255, 32, 97, 232, 177, 18, 73, 24, 34, 0, 38, 172, 247, ++ 198, 255, 55, 70, 14, 224, 14, 75, 212, 248, 16, 128, 155, 25, 24, 121, ++ 128, 0, 179, 243, 72, 241, 35, 105, 72, 248, 6, 0, 155, 89, 8, 54, 67, ++ 177, 1, 55, 227, 104, 159, 66, 237, 219, 107, 104, 6, 74, 220, 96, 154, ++ 96, 3, 224, 32, 70, 255, 247, 160, 255, 0, 36, 32, 70, 189, 232, 240, ++ 129, 52, 160, 5, 0, 215, 209, 2, 0, 16, 181, 196, 104, 161, 66, 11, ++ 218, 0, 105, 0, 235, 193, 4, 36, 121, 162, 66, 8, 218, 80, 248, 49, ++ 16, 0, 32, 65, 248, 34, 48, 16, 189, 111, 240, 21, 0, 16, 189, 111, ++ 240, 21, 0, 16, 189, 215, 247, 186, 190, 16, 181, 4, 70, 255, 247, 250, ++ 255, 224, 132, 0, 12, 132, 248, 40, 0, 0, 32, 16, 189, 1, 33, 10, 35, ++ 128, 248, 4, 17, 129, 107, 3, 34, 128, 248, 66, 50, 0, 35, 128, 248, ++ 67, 34, 128, 248, 19, 52, 128, 248, 21, 52, 128, 248, 23, 52, 128, 248, ++ 25, 52, 128, 248, 27, 52, 128, 248, 94, 50, 129, 248, 138, 32, 192, ++ 248, 24, 51, 128, 248, 16, 49, 192, 248, 136, 52, 127, 35, 128, 248, ++ 31, 49, 79, 240, 255, 51, 160, 248, 60, 49, 0, 245, 36, 115, 192, 248, ++ 48, 50, 100, 35, 79, 246, 206, 114, 128, 248, 252, 48, 4, 35, 160, 248, ++ 28, 35, 128, 248, 120, 50, 128, 248, 122, 50, 112, 71, 208, 248, 148, ++ 52, 16, 181, 4, 70, 131, 177, 211, 248, 40, 8, 48, 177, 181, 247, 220, ++ 254, 212, 248, 148, 52, 0, 34, 195, 248, 40, 40, 212, 248, 148, 4, 181, ++ 247, 211, 254, 0, 35, 196, 248, 148, 52, 16, 189, 208, 248, 224, 48, ++ 16, 181, 4, 70, 147, 177, 131, 107, 91, 107, 11, 43, 7, 209, 208, 248, ++ 132, 4, 32, 177, 181, 247, 193, 254, 0, 35, 196, 248, 132, 52, 212, ++ 248, 224, 0, 181, 247, 186, 254, 0, 35, 196, 248, 224, 48, 16, 189, ++ 16, 181, 4, 70, 1, 32, 181, 247, 174, 254, 3, 70, 196, 248, 224, 0, ++ 168, 177, 0, 33, 1, 34, 174, 243, 140, 242, 163, 107, 91, 107, 11, 43, ++ 12, 209, 79, 244, 148, 112, 181, 247, 158, 254, 3, 70, 196, 248, 132, ++ 4, 40, 177, 0, 33, 79, 244, 148, 114, 174, 243, 123, 242, 1, 35, 24, ++ 70, 16, 189, 112, 181, 4, 70, 64, 246, 120, 16, 13, 70, 181, 247, 139, ++ 254, 196, 248, 148, 4, 0, 40, 49, 208, 0, 33, 64, 246, 120, 18, 174, ++ 243, 104, 242, 180, 248, 246, 32, 212, 248, 148, 52, 0, 38, 26, 112, ++ 212, 248, 148, 52, 32, 70, 131, 248, 182, 96, 195, 248, 176, 96, 212, ++ 248, 148, 52, 131, 248, 180, 96, 163, 107, 131, 248, 132, 96, 163, 107, ++ 30, 103, 158, 103, 60, 35, 196, 248, 96, 49, 16, 35, 196, 248, 100, ++ 49, 196, 248, 104, 97, 0, 240, 159, 254, 163, 107, 2, 45, 12, 191, 26, ++ 111, 154, 111, 0, 32, 218, 102, 132, 248, 103, 99, 132, 248, 102, 99, ++ 112, 189, 111, 240, 26, 0, 112, 189, 176, 248, 106, 51, 247, 181, 4, ++ 70, 14, 70, 3, 179, 8, 70, 174, 243, 227, 242, 7, 70, 20, 72, 174, 243, ++ 223, 242, 63, 24, 16, 55, 191, 178, 56, 70, 181, 247, 63, 254, 5, 70, ++ 200, 177, 180, 248, 106, 51, 57, 70, 0, 147, 14, 74, 51, 70, 174, 243, ++ 129, 242, 212, 248, 240, 0, 41, 70, 175, 243, 142, 240, 7, 70, 40, 70, ++ 181, 247, 47, 254, 71, 185, 212, 248, 240, 0, 49, 70, 3, 176, 189, 232, ++ 240, 64, 175, 243, 129, 176, 7, 70, 56, 70, 3, 176, 240, 189, 0, 191, ++ 140, 160, 5, 0, 119, 160, 5, 0, 45, 233, 243, 71, 28, 70, 176, 248, ++ 106, 51, 7, 70, 136, 70, 145, 70, 208, 248, 240, 96, 0, 43, 50, 208, ++ 8, 70, 174, 243, 165, 242, 130, 70, 34, 72, 174, 243, 161, 242, 130, ++ 68, 10, 241, 16, 10, 31, 250, 138, 250, 80, 70, 181, 247, 255, 253, ++ 5, 70, 0, 40, 47, 208, 183, 248, 106, 51, 81, 70, 0, 147, 26, 74, 67, ++ 70, 174, 243, 64, 242, 56, 70, 41, 70, 216, 247, 30, 248, 7, 70, 104, ++ 177, 48, 70, 41, 70, 175, 243, 60, 240, 64, 177, 72, 69, 6, 221, 48, ++ 70, 41, 70, 74, 70, 175, 243, 40, 240, 130, 70, 0, 224, 162, 70, 40, ++ 70, 181, 247, 223, 253, 143, 185, 48, 70, 65, 70, 175, 243, 41, 240, ++ 88, 177, 72, 69, 9, 221, 48, 70, 65, 70, 74, 70, 2, 176, 189, 232, 240, ++ 71, 175, 243, 18, 176, 130, 70, 0, 224, 162, 70, 80, 70, 2, 176, 189, ++ 232, 240, 135, 0, 191, 140, 160, 5, 0, 119, 160, 5, 0, 56, 181, 0, 34, ++ 13, 70, 8, 73, 4, 70, 215, 247, 243, 255, 192, 178, 40, 35, 168, 66, ++ 132, 248, 10, 4, 132, 248, 121, 50, 204, 191, 132, 248, 10, 52, 132, ++ 248, 121, 2, 56, 189, 211, 160, 5, 0, 16, 181, 23, 73, 4, 70, 215, 247, ++ 236, 255, 192, 178, 132, 248, 140, 4, 1, 56, 192, 178, 253, 40, 2, 217, ++ 115, 35, 132, 248, 140, 52, 148, 248, 140, 52, 32, 70, 132, 248, 141, ++ 52, 14, 73, 215, 247, 218, 255, 192, 178, 132, 248, 142, 4, 8, 177, ++ 15, 40, 2, 209, 5, 35, 132, 248, 142, 52, 148, 248, 140, 36, 148, 248, ++ 142, 52, 211, 26, 132, 248, 143, 52, 0, 35, 132, 248, 144, 52, 132, ++ 248, 146, 52, 17, 35, 132, 248, 145, 52, 16, 189, 129, 160, 5, 0, 228, ++ 160, 5, 0, 112, 181, 1, 34, 13, 70, 60, 73, 4, 70, 215, 247, 169, 255, ++ 59, 73, 132, 248, 12, 4, 0, 34, 32, 70, 215, 247, 162, 255, 56, 73, ++ 132, 248, 208, 3, 7, 34, 32, 70, 215, 247, 155, 255, 54, 73, 132, 248, ++ 209, 3, 32, 70, 215, 247, 137, 255, 136, 177, 50, 73, 32, 70, 166, 107, ++ 215, 247, 156, 255, 48, 73, 48, 103, 32, 70, 166, 107, 215, 247, 150, ++ 255, 163, 107, 176, 103, 2, 45, 12, 191, 26, 111, 154, 111, 218, 102, ++ 42, 73, 0, 34, 111, 240, 149, 3, 32, 70, 215, 247, 139, 255, 39, 73, ++ 132, 248, 216, 3, 1, 34, 32, 70, 111, 240, 149, 3, 215, 247, 130, 255, ++ 2, 37, 132, 248, 217, 3, 0, 35, 42, 70, 32, 70, 31, 73, 215, 247, 121, ++ 255, 99, 25, 1, 53, 5, 45, 131, 248, 216, 3, 243, 209, 0, 37, 42, 70, ++ 32, 70, 26, 73, 215, 247, 129, 255, 99, 25, 1, 53, 14, 45, 131, 248, ++ 251, 3, 244, 209, 1, 37, 6, 34, 132, 248, 11, 84, 32, 70, 20, 73, 215, ++ 247, 79, 255, 0, 34, 132, 248, 9, 4, 18, 73, 32, 70, 166, 107, 215, ++ 247, 71, 255, 17, 73, 134, 248, 44, 1, 42, 70, 32, 70, 215, 247, 64, ++ 255, 0, 35, 132, 248, 226, 3, 64, 33, 32, 70, 132, 248, 200, 51, 189, ++ 232, 112, 64, 255, 247, 59, 191, 0, 191, 107, 160, 5, 0, 76, 160, 5, ++ 0, 197, 160, 5, 0, 157, 160, 5, 0, 245, 160, 5, 0, 190, 160, 5, 0, 146, ++ 160, 5, 0, 170, 160, 5, 0, 102, 160, 5, 0, 16, 181, 4, 70, 40, 177, ++ 4, 104, 0, 52, 24, 191, 1, 36, 181, 247, 226, 252, 32, 70, 16, 189, ++ 16, 181, 132, 139, 12, 128, 1, 140, 17, 128, 64, 242, 218, 50, 26, 128, ++ 144, 248, 53, 32, 2, 155, 1, 32, 26, 128, 16, 189, 144, 248, 52, 0, ++ 112, 71, 192, 106, 112, 71, 131, 107, 153, 97, 112, 71, 56, 181, 4, ++ 70, 0, 40, 63, 208, 208, 248, 0, 81, 1, 61, 192, 248, 0, 81, 0, 45, ++ 56, 209, 255, 247, 215, 253, 32, 70, 255, 247, 235, 253, 212, 248, 36, ++ 19, 41, 177, 163, 107, 24, 105, 0, 240, 14, 253, 196, 248, 36, 83, 0, ++ 37, 132, 248, 57, 82, 32, 70, 217, 247, 92, 250, 162, 107, 19, 104, ++ 163, 66, 3, 209, 212, 248, 236, 48, 19, 96, 5, 224, 211, 248, 236, 32, ++ 162, 66, 26, 209, 195, 248, 236, 80, 212, 248, 136, 48, 11, 177, 32, ++ 70, 152, 71, 212, 248, 136, 52, 19, 177, 32, 70, 217, 247, 95, 252, ++ 212, 248, 156, 20, 25, 177, 163, 107, 152, 104, 226, 247, 115, 253, ++ 32, 70, 181, 247, 136, 252, 0, 32, 56, 189, 1, 32, 56, 189, 1, 32, 56, ++ 189, 0, 0, 45, 233, 240, 71, 138, 70, 0, 33, 4, 70, 21, 70, 192, 104, ++ 10, 70, 118, 70, 153, 70, 184, 243, 236, 245, 128, 70, 0, 7, 14, 213, ++ 39, 104, 103, 177, 187, 107, 199, 248, 240, 144, 24, 105, 249, 106, ++ 225, 247, 154, 253, 215, 248, 0, 49, 1, 51, 199, 248, 0, 49, 200, 224, ++ 64, 246, 232, 32, 181, 247, 92, 252, 7, 70, 40, 185, 111, 240, 26, 0, ++ 49, 70, 217, 247, 203, 253, 192, 224, 0, 33, 64, 246, 232, 34, 174, ++ 243, 53, 240, 215, 248, 0, 49, 199, 248, 232, 160, 1, 51, 199, 248, ++ 0, 49, 35, 104, 188, 99, 199, 248, 236, 48, 1, 35, 199, 248, 240, 144, ++ 39, 96, 135, 248, 253, 48, 226, 108, 65, 242, 107, 3, 154, 66, 5, 209, ++ 99, 108, 147, 43, 12, 191, 1, 35, 24, 35, 0, 224, 24, 35, 2, 45, 167, ++ 248, 46, 49, 5, 209, 24, 240, 1, 15, 28, 191, 79, 244, 0, 83, 251, 98, ++ 187, 107, 249, 106, 24, 105, 225, 247, 87, 253, 215, 248, 232, 48, 179, ++ 248, 224, 67, 164, 178, 4, 244, 112, 99, 27, 10, 251, 97, 227, 178, ++ 59, 98, 187, 107, 216, 104, 248, 247, 91, 255, 251, 105, 167, 248, 106, ++ 3, 9, 43, 4, 209, 4, 35, 251, 97, 59, 106, 16, 51, 59, 98, 1, 35, 36, ++ 11, 135, 248, 36, 48, 60, 99, 56, 70, 255, 247, 222, 252, 0, 40, 111, ++ 209, 79, 244, 128, 83, 167, 248, 250, 48, 77, 242, 36, 2, 65, 242, 1, ++ 3, 2, 45, 24, 191, 19, 70, 167, 248, 246, 48, 56, 70, 51, 73, 215, 247, ++ 29, 254, 40, 177, 56, 70, 49, 73, 188, 107, 215, 247, 48, 254, 160, ++ 102, 56, 70, 255, 247, 50, 253, 0, 40, 82, 208, 56, 70, 41, 70, 255, ++ 247, 105, 254, 56, 70, 255, 247, 194, 252, 56, 70, 0, 240, 99, 251, ++ 0, 40, 70, 208, 56, 70, 41, 70, 255, 247, 65, 253, 4, 70, 0, 40, 63, ++ 209, 56, 70, 255, 247, 35, 254, 56, 70, 215, 247, 129, 251, 56, 70, ++ 1, 33, 215, 247, 92, 255, 56, 70, 33, 70, 216, 247, 4, 250, 79, 240, ++ 255, 51, 199, 248, 120, 51, 199, 248, 124, 51, 199, 248, 128, 51, 199, ++ 248, 132, 51, 199, 248, 136, 51, 199, 248, 140, 51, 199, 248, 144, 51, ++ 199, 248, 148, 51, 7, 241, 28, 1, 28, 34, 56, 70, 172, 247, 16, 252, ++ 187, 107, 152, 104, 226, 247, 173, 252, 199, 248, 156, 4, 40, 185, 111, ++ 240, 26, 0, 49, 70, 217, 247, 20, 253, 12, 224, 56, 70, 33, 70, 217, ++ 247, 9, 253, 135, 248, 160, 74, 7, 241, 240, 3, 199, 248, 240, 48, 56, ++ 70, 189, 232, 240, 135, 56, 70, 255, 247, 198, 254, 0, 32, 189, 232, ++ 240, 135, 89, 160, 5, 0, 112, 181, 5, 70, 79, 244, 152, 112, 118, 70, ++ 181, 247, 129, 251, 4, 70, 40, 185, 111, 240, 26, 0, 49, 70, 217, 247, ++ 240, 252, 58, 224, 0, 33, 79, 244, 152, 114, 173, 243, 90, 247, 43, ++ 104, 163, 96, 107, 104, 227, 96, 171, 104, 35, 97, 235, 104, 99, 96, ++ 43, 105, 99, 97, 43, 140, 163, 132, 107, 140, 227, 132, 107, 106, 163, ++ 98, 171, 106, 227, 98, 235, 106, 35, 99, 43, 107, 99, 99, 107, 107, ++ 99, 100, 171, 107, 163, 100, 235, 107, 227, 100, 43, 108, 35, 101, 107, ++ 108, 99, 101, 171, 108, 196, 248, 28, 49, 107, 105, 163, 101, 171, 105, ++ 227, 101, 15, 35, 35, 102, 61, 35, 99, 102, 64, 246, 17, 99, 163, 102, ++ 1, 35, 196, 248, 24, 49, 3, 35, 227, 102, 0, 35, 132, 248, 139, 48, ++ 32, 70, 112, 189, 127, 181, 10, 75, 10, 73, 0, 147, 0, 35, 1, 147, 2, ++ 147, 3, 147, 4, 147, 5, 147, 7, 74, 3, 104, 249, 247, 112, 254, 0, 40, ++ 20, 191, 79, 240, 255, 48, 0, 32, 7, 176, 0, 189, 0, 191, 115, 246, ++ 2, 0, 240, 62, 4, 0, 0, 65, 4, 0, 1, 73, 2, 104, 249, 247, 3, 190, 0, ++ 65, 4, 0, 0, 35, 240, 181, 28, 70, 7, 224, 206, 24, 53, 104, 199, 24, ++ 197, 80, 117, 104, 1, 52, 125, 96, 8, 51, 148, 66, 245, 209, 240, 189, ++ 0, 0, 56, 181, 208, 248, 228, 64, 0, 35, 196, 248, 36, 54, 144, 248, ++ 17, 84, 9, 75, 10, 74, 79, 244, 128, 96, 0, 45, 12, 191, 21, 70, 29, ++ 70, 181, 247, 248, 250, 196, 248, 36, 6, 32, 177, 41, 70, 128, 34, 255, ++ 247, 215, 255, 1, 32, 56, 189, 0, 191, 65, 174, 5, 0, 65, 178, 5, 0, ++ 56, 181, 14, 73, 79, 240, 255, 50, 208, 248, 228, 64, 5, 70, 215, 247, ++ 27, 253, 11, 73, 196, 248, 80, 5, 23, 34, 40, 70, 215, 247, 20, 253, ++ 0, 35, 196, 248, 84, 5, 132, 248, 88, 53, 40, 70, 5, 73, 111, 240, 37, ++ 2, 215, 247, 9, 253, 164, 248, 72, 5, 56, 189, 26, 161, 5, 0, 49, 169, ++ 5, 0, 26, 169, 5, 0, 248, 181, 168, 73, 0, 34, 208, 248, 228, 80, 4, ++ 70, 215, 247, 28, 253, 164, 73, 133, 248, 188, 4, 1, 34, 32, 70, 215, ++ 247, 21, 253, 162, 73, 133, 248, 189, 4, 0, 34, 7, 35, 32, 70, 215, ++ 247, 249, 252, 146, 35, 133, 248, 190, 4, 156, 73, 1, 34, 32, 70, 215, ++ 247, 241, 252, 155, 73, 133, 248, 191, 4, 0, 34, 32, 70, 215, 247, 218, ++ 252, 152, 73, 197, 248, 196, 4, 0, 34, 32, 70, 215, 247, 211, 252, 0, ++ 38, 165, 248, 88, 4, 148, 73, 133, 248, 51, 100, 32, 70, 50, 70, 215, ++ 247, 201, 252, 146, 73, 165, 248, 10, 4, 32, 70, 215, 247, 208, 252, ++ 184, 177, 1, 35, 133, 248, 51, 52, 47, 70, 66, 35, 50, 70, 32, 70, 139, ++ 73, 215, 247, 200, 252, 171, 25, 192, 178, 131, 248, 38, 4, 181, 248, ++ 10, 52, 1, 54, 192, 24, 167, 248, 12, 4, 2, 55, 13, 46, 236, 209, 13, ++ 224, 131, 73, 66, 34, 32, 70, 215, 247, 165, 252, 194, 178, 133, 248, ++ 8, 36, 32, 70, 128, 73, 215, 247, 158, 252, 165, 248, 6, 4, 126, 73, ++ 0, 34, 32, 70, 215, 247, 151, 252, 125, 73, 133, 248, 56, 4, 79, 240, ++ 255, 50, 32, 70, 215, 247, 143, 252, 122, 73, 165, 248, 104, 5, 79, ++ 240, 255, 50, 32, 70, 215, 247, 135, 252, 119, 73, 165, 248, 106, 5, ++ 79, 240, 255, 50, 32, 70, 215, 247, 127, 252, 116, 73, 165, 248, 110, ++ 5, 79, 240, 255, 50, 32, 70, 215, 247, 119, 252, 113, 73, 133, 248, ++ 112, 5, 0, 34, 32, 70, 215, 247, 112, 252, 0, 38, 132, 248, 24, 1, 50, ++ 70, 32, 70, 108, 73, 215, 247, 140, 252, 171, 25, 1, 54, 14, 46, 131, ++ 248, 6, 6, 244, 209, 161, 34, 104, 73, 32, 70, 215, 247, 93, 252, 103, ++ 73, 197, 248, 192, 5, 70, 242, 15, 98, 32, 70, 215, 247, 85, 252, 8, ++ 34, 197, 248, 196, 5, 98, 73, 32, 70, 215, 247, 78, 252, 97, 73, 197, ++ 248, 200, 5, 111, 240, 8, 2, 32, 70, 215, 247, 70, 252, 94, 73, 197, ++ 248, 204, 5, 64, 246, 187, 114, 32, 70, 215, 247, 62, 252, 10, 34, 197, ++ 248, 208, 5, 90, 73, 32, 70, 215, 247, 55, 252, 89, 73, 197, 248, 212, ++ 5, 111, 240, 68, 2, 32, 70, 215, 247, 47, 252, 86, 73, 165, 248, 2, ++ 6, 111, 240, 74, 2, 32, 70, 215, 247, 39, 252, 1, 34, 165, 248, 4, 6, ++ 81, 73, 32, 70, 215, 247, 32, 252, 128, 178, 3, 28, 24, 191, 1, 35, ++ 0, 240, 2, 0, 133, 248, 74, 53, 63, 34, 133, 248, 75, 5, 75, 73, 32, ++ 70, 215, 247, 17, 252, 100, 34, 133, 248, 76, 5, 72, 73, 32, 70, 215, ++ 247, 10, 252, 71, 73, 197, 248, 92, 5, 79, 240, 255, 50, 32, 70, 215, ++ 247, 2, 252, 197, 248, 96, 5, 1, 48, 24, 191, 1, 32, 133, 248, 100, ++ 5, 65, 73, 0, 34, 32, 70, 215, 247, 246, 251, 192, 178, 0, 240, 15, ++ 3, 0, 9, 0, 240, 1, 0, 133, 248, 20, 54, 133, 248, 23, 6, 58, 73, 0, ++ 34, 38, 35, 32, 70, 215, 247, 246, 251, 55, 73, 165, 248, 24, 6, 1, ++ 34, 66, 35, 32, 70, 215, 247, 238, 251, 80, 35, 165, 248, 26, 6, 50, ++ 73, 2, 34, 32, 70, 215, 247, 230, 251, 48, 73, 165, 248, 28, 6, 6, 34, ++ 32, 70, 215, 247, 207, 251, 0, 34, 133, 248, 30, 6, 44, 73, 32, 70, ++ 215, 247, 200, 251, 133, 248, 40, 6, 32, 70, 221, 247, 73, 250, 148, ++ 248, 17, 36, 32, 70, 0, 42, 79, 209, 38, 73, 215, 247, 223, 251, 37, ++ 73, 164, 248, 38, 4, 1, 34, 32, 70, 215, 247, 216, 251, 33, 73, 164, ++ 248, 34, 4, 32, 70, 79, 224, 0, 191, 227, 173, 5, 0, 87, 169, 5, 0, ++ 232, 169, 5, 0, 181, 169, 5, 0, 99, 169, 5, 0, 213, 169, 5, 0, 166, ++ 173, 5, 0, 215, 173, 5, 0, 5, 161, 5, 0, 69, 161, 5, 0, 245, 173, 5, ++ 0, 69, 169, 5, 0, 7, 169, 5, 0, 175, 173, 5, 0, 39, 174, 5, 0, 16, 169, ++ 5, 0, 172, 169, 5, 0, 189, 173, 5, 0, 205, 173, 5, 0, 17, 161, 5, 0, ++ 58, 174, 5, 0, 5, 174, 5, 0, 200, 169, 5, 0, 202, 168, 5, 0, 136, 169, ++ 5, 0, 229, 168, 5, 0, 211, 168, 5, 0, 58, 161, 5, 0, 225, 169, 5, 0, ++ 193, 168, 5, 0, 147, 169, 5, 0, 32, 174, 5, 0, 37, 73, 0, 34, 215, 247, ++ 142, 251, 35, 73, 164, 248, 38, 4, 1, 34, 32, 70, 215, 247, 135, 251, ++ 32, 73, 164, 248, 34, 4, 32, 70, 2, 34, 215, 247, 128, 251, 0, 35, 164, ++ 248, 36, 4, 28, 73, 133, 248, 51, 54, 32, 70, 2, 34, 215, 247, 98, 251, ++ 16, 177, 1, 35, 133, 248, 51, 54, 149, 248, 51, 54, 43, 179, 21, 73, ++ 0, 34, 32, 70, 215, 247, 106, 251, 18, 73, 164, 248, 208, 10, 1, 34, ++ 32, 70, 215, 247, 99, 251, 15, 73, 164, 248, 204, 10, 2, 34, 32, 70, ++ 215, 247, 92, 251, 12, 73, 164, 248, 206, 10, 0, 34, 32, 70, 215, 247, ++ 49, 251, 10, 73, 133, 248, 49, 6, 40, 34, 32, 70, 215, 247, 42, 251, ++ 0, 35, 133, 248, 50, 6, 132, 248, 11, 52, 1, 32, 248, 189, 0, 191, 245, ++ 168, 5, 0, 154, 173, 5, 0, 53, 161, 5, 0, 53, 174, 5, 0, 56, 181, 14, ++ 73, 208, 248, 228, 64, 5, 70, 215, 247, 32, 251, 12, 73, 132, 248, 41, ++ 6, 40, 70, 215, 247, 26, 251, 255, 34, 132, 248, 42, 6, 8, 73, 40, 70, ++ 215, 247, 6, 251, 7, 73, 132, 248, 48, 6, 40, 70, 215, 247, 13, 251, ++ 196, 248, 44, 6, 1, 32, 56, 189, 191, 169, 5, 0, 113, 169, 5, 0, 40, ++ 161, 5, 0, 156, 169, 5, 0, 56, 181, 4, 70, 208, 248, 228, 80, 79, 244, ++ 103, 112, 181, 247, 178, 248, 197, 248, 32, 6, 212, 248, 228, 48, 211, ++ 248, 32, 6, 176, 177, 212, 248, 128, 49, 11, 74, 147, 66, 7, 208, 10, ++ 74, 147, 66, 6, 208, 10, 74, 147, 66, 10, 209, 9, 73, 2, 224, 9, 73, ++ 0, 224, 9, 73, 79, 244, 103, 114, 172, 247, 253, 248, 1, 32, 56, 189, ++ 0, 32, 56, 189, 0, 191, 192, 173, 58, 2, 128, 186, 140, 1, 0, 248, 36, ++ 1, 254, 169, 5, 0, 114, 161, 5, 0, 24, 165, 5, 0, 16, 181, 4, 70, 221, ++ 247, 166, 249, 212, 248, 228, 48, 211, 248, 32, 6, 181, 247, 127, 248, ++ 212, 248, 228, 0, 189, 232, 16, 64, 181, 247, 121, 184, 112, 181, 4, ++ 70, 64, 246, 4, 64, 181, 247, 112, 248, 5, 70, 196, 248, 228, 0, 0, ++ 40, 115, 208, 0, 33, 64, 246, 4, 66, 173, 243, 76, 244, 1, 37, 163, ++ 107, 132, 248, 38, 81, 132, 248, 148, 81, 216, 104, 184, 243, 77, 241, ++ 52, 75, 196, 248, 128, 1, 227, 99, 51, 75, 32, 70, 35, 100, 50, 75, ++ 99, 100, 50, 75, 163, 100, 50, 75, 196, 248, 148, 48, 50, 75, 35, 101, ++ 50, 75, 163, 101, 50, 75, 35, 102, 50, 75, 99, 102, 50, 75, 35, 103, ++ 50, 75, 196, 248, 168, 48, 49, 75, 196, 248, 164, 48, 49, 75, 196, 248, ++ 180, 48, 48, 75, 196, 248, 176, 48, 48, 75, 196, 248, 184, 48, 47, 75, ++ 196, 248, 188, 48, 47, 75, 196, 248, 192, 48, 46, 75, 196, 248, 136, ++ 48, 46, 75, 196, 248, 196, 48, 45, 75, 196, 248, 200, 48, 45, 75, 196, ++ 248, 204, 48, 44, 75, 196, 248, 208, 48, 44, 75, 196, 248, 212, 48, ++ 255, 247, 86, 253, 16, 179, 32, 70, 255, 247, 94, 255, 240, 177, 32, ++ 70, 255, 247, 10, 253, 208, 177, 32, 70, 255, 247, 38, 253, 212, 248, ++ 228, 48, 32, 70, 131, 248, 192, 84, 255, 247, 41, 255, 33, 73, 0, 34, ++ 32, 70, 212, 248, 228, 96, 215, 247, 60, 250, 30, 73, 134, 248, 0, 12, ++ 0, 34, 32, 70, 215, 247, 53, 250, 132, 248, 52, 3, 0, 224, 5, 70, 40, ++ 70, 112, 189, 0, 191, 57, 117, 3, 0, 187, 246, 2, 0, 43, 116, 3, 0, ++ 221, 48, 3, 0, 127, 47, 3, 0, 221, 35, 3, 0, 143, 39, 3, 0, 71, 31, ++ 3, 0, 183, 39, 3, 0, 189, 246, 2, 0, 231, 113, 3, 0, 223, 246, 2, 0, ++ 225, 246, 2, 0, 227, 246, 2, 0, 15, 36, 3, 0, 153, 30, 3, 0, 161, 112, ++ 3, 0, 61, 98, 5, 0, 229, 246, 2, 0, 235, 246, 2, 0, 237, 246, 2, 0, ++ 241, 246, 2, 0, 233, 246, 2, 0, 98, 161, 5, 0, 84, 161, 5, 0, 131, 107, ++ 147, 248, 44, 33, 10, 177, 4, 34, 0, 224, 3, 34, 26, 103, 218, 102, ++ 112, 71, 248, 181, 7, 70, 12, 32, 13, 70, 22, 70, 180, 247, 177, 255, ++ 4, 70, 48, 177, 0, 33, 12, 34, 173, 243, 145, 243, 39, 96, 102, 96, ++ 165, 96, 32, 70, 248, 189, 8, 177, 180, 247, 166, 191, 112, 71, 128, ++ 104, 195, 243, 97, 176, 0, 0, 112, 181, 6, 70, 134, 176, 108, 32, 180, ++ 247, 152, 255, 4, 70, 216, 177, 0, 33, 108, 34, 173, 243, 120, 243, ++ 22, 35, 163, 97, 14, 75, 38, 96, 0, 147, 14, 75, 0, 37, 4, 147, 48, ++ 104, 13, 73, 13, 74, 35, 70, 1, 149, 2, 149, 3, 149, 5, 149, 249, 247, ++ 194, 250, 56, 185, 50, 104, 1, 35, 130, 248, 146, 48, 35, 113, 32, 70, ++ 6, 176, 112, 189, 32, 70, 180, 247, 119, 255, 44, 70, 247, 231, 97, ++ 54, 134, 0, 132, 81, 4, 0, 36, 238, 135, 0, 96, 81, 4, 0, 16, 181, 4, ++ 70, 104, 177, 3, 104, 6, 73, 24, 104, 34, 70, 249, 247, 72, 250, 32, ++ 70, 13, 240, 44, 220, 32, 70, 189, 232, 16, 64, 180, 247, 92, 191, 16, ++ 189, 96, 81, 4, 0, 16, 181, 4, 70, 72, 177, 5, 73, 34, 70, 64, 104, ++ 249, 247, 53, 250, 32, 70, 189, 232, 16, 64, 180, 247, 76, 191, 16, ++ 189, 206, 204, 136, 0, 112, 181, 6, 70, 134, 176, 16, 32, 180, 247, ++ 64, 255, 4, 70, 48, 179, 0, 33, 16, 34, 173, 243, 32, 243, 51, 104, ++ 38, 96, 99, 96, 115, 104, 0, 37, 163, 96, 4, 33, 48, 70, 14, 74, 15, ++ 75, 0, 149, 1, 148, 252, 247, 72, 253, 168, 66, 224, 96, 13, 219, 12, ++ 75, 48, 104, 141, 232, 40, 0, 11, 73, 11, 74, 35, 70, 2, 149, 3, 149, ++ 4, 149, 5, 149, 249, 247, 94, 250, 24, 177, 32, 70, 255, 247, 194, 255, ++ 0, 36, 32, 70, 6, 176, 112, 189, 157, 64, 134, 0, 133, 64, 134, 0, 241, ++ 64, 134, 0, 228, 238, 135, 0, 206, 204, 136, 0, 48, 181, 5, 70, 135, ++ 176, 20, 32, 180, 247, 4, 255, 4, 70, 56, 179, 0, 33, 20, 34, 173, 243, ++ 228, 242, 107, 104, 40, 104, 163, 96, 18, 75, 37, 96, 96, 96, 0, 37, ++ 0, 147, 16, 73, 17, 74, 35, 70, 1, 149, 2, 149, 3, 149, 4, 149, 5, 149, ++ 249, 247, 46, 250, 96, 185, 10, 35, 35, 115, 15, 35, 99, 115, 100, 35, ++ 163, 115, 2, 35, 227, 115, 6, 35, 35, 116, 1, 35, 99, 116, 3, 224, 32, ++ 70, 180, 247, 222, 254, 44, 70, 32, 70, 7, 176, 48, 189, 0, 191, 225, ++ 70, 134, 0, 252, 238, 135, 0, 47, 190, 136, 0, 16, 181, 4, 70, 72, 177, ++ 5, 73, 34, 70, 64, 104, 249, 247, 175, 249, 32, 70, 189, 232, 16, 64, ++ 180, 247, 198, 190, 16, 189, 47, 190, 136, 0, 16, 181, 4, 70, 88, 177, ++ 6, 75, 33, 70, 27, 136, 195, 88, 24, 104, 249, 247, 188, 250, 32, 70, ++ 189, 232, 16, 64, 180, 247, 180, 190, 16, 189, 16, 7, 0, 0, 115, 181, ++ 5, 70, 12, 32, 178, 243, 155, 240, 4, 70, 200, 177, 16, 75, 4, 34, 26, ++ 128, 2, 33, 69, 96, 0, 35, 1, 144, 13, 74, 40, 70, 0, 147, 252, 247, ++ 183, 252, 0, 40, 32, 96, 10, 219, 1, 35, 35, 129, 9, 75, 40, 104, 0, ++ 147, 33, 70, 8, 74, 2, 35, 249, 247, 35, 250, 24, 177, 32, 70, 255, ++ 247, 202, 255, 0, 36, 32, 70, 124, 189, 0, 191, 16, 7, 0, 0, 147, 133, ++ 3, 0, 44, 239, 135, 0, 17, 72, 134, 0, 56, 181, 4, 70, 128, 177, 9, ++ 75, 33, 70, 27, 136, 197, 88, 40, 104, 249, 247, 122, 250, 40, 104, ++ 6, 73, 34, 70, 249, 247, 86, 249, 32, 70, 189, 232, 56, 64, 180, 247, ++ 109, 190, 56, 189, 0, 191, 18, 7, 0, 0, 239, 81, 4, 0, 240, 181, 5, ++ 70, 135, 176, 20, 32, 178, 243, 80, 240, 4, 70, 0, 40, 86, 208, 47, ++ 75, 4, 34, 26, 128, 69, 96, 0, 38, 1, 144, 4, 33, 40, 70, 44, 74, 44, ++ 75, 0, 150, 252, 247, 106, 252, 176, 66, 32, 96, 70, 219, 1, 35, 163, ++ 129, 12, 35, 35, 130, 40, 75, 7, 34, 226, 129, 0, 147, 39, 75, 40, 104, ++ 1, 147, 38, 73, 39, 74, 35, 70, 2, 150, 3, 150, 4, 150, 5, 150, 249, ++ 247, 121, 249, 0, 40, 48, 209, 35, 75, 40, 104, 0, 147, 33, 70, 34, ++ 74, 5, 35, 249, 247, 194, 249, 56, 187, 32, 75, 213, 248, 124, 6, 141, ++ 232, 24, 0, 79, 244, 144, 113, 42, 34, 29, 75, 253, 247, 107, 252, 216, ++ 185, 213, 248, 124, 6, 128, 33, 42, 34, 26, 75, 0, 148, 253, 247, 14, ++ 253, 144, 185, 181, 248, 174, 1, 188, 247, 247, 250, 128, 27, 24, 191, ++ 1, 32, 10, 48, 85, 248, 32, 48, 27, 104, 2, 43, 9, 209, 1, 33, 32, 70, ++ 10, 70, 14, 240, 109, 220, 3, 224, 32, 70, 255, 247, 131, 255, 0, 36, ++ 32, 70, 7, 176, 240, 189, 0, 191, 18, 7, 0, 0, 197, 75, 134, 0, 177, ++ 75, 134, 0, 69, 78, 134, 0, 93, 78, 134, 0, 100, 239, 135, 0, 239, 81, ++ 4, 0, 60, 239, 135, 0, 113, 77, 134, 0, 97, 79, 134, 0, 81, 76, 134, ++ 0, 97, 75, 134, 0, 8, 75, 16, 181, 27, 136, 4, 70, 80, 177, 195, 88, ++ 6, 73, 24, 104, 34, 70, 249, 247, 192, 248, 32, 70, 189, 232, 16, 64, ++ 180, 247, 215, 189, 16, 189, 0, 191, 20, 7, 0, 0, 246, 81, 4, 0, 112, ++ 181, 5, 70, 134, 176, 20, 32, 177, 243, 186, 247, 4, 70, 0, 40, 68, ++ 208, 38, 75, 8, 34, 26, 128, 0, 35, 133, 96, 4, 33, 0, 147, 1, 144, ++ 35, 74, 40, 70, 35, 75, 252, 247, 212, 251, 0, 40, 32, 96, 52, 219, ++ 2, 35, 163, 129, 5, 34, 12, 35, 226, 129, 35, 130, 213, 248, 124, 6, ++ 128, 33, 61, 34, 28, 75, 0, 148, 253, 247, 157, 252, 40, 187, 26, 75, ++ 2, 144, 0, 147, 26, 75, 3, 144, 1, 147, 4, 144, 5, 144, 24, 73, 40, ++ 104, 24, 74, 35, 70, 249, 247, 218, 248, 176, 185, 181, 248, 174, 1, ++ 188, 247, 119, 250, 43, 104, 147, 248, 79, 32, 26, 177, 3, 42, 20, 191, ++ 3, 34, 1, 34, 32, 70, 1, 33, 15, 240, 37, 217, 32, 70, 2, 33, 79, 240, ++ 255, 50, 15, 240, 31, 217, 3, 224, 32, 70, 255, 247, 153, 255, 0, 36, ++ 32, 70, 6, 176, 112, 189, 0, 191, 20, 7, 0, 0, 153, 84, 134, 0, 133, ++ 84, 134, 0, 81, 84, 134, 0, 1, 86, 134, 0, 105, 87, 134, 0, 112, 239, ++ 135, 0, 246, 81, 4, 0, 56, 181, 4, 70, 152, 177, 5, 104, 34, 70, 40, ++ 70, 8, 73, 252, 247, 158, 251, 33, 70, 40, 104, 249, 247, 97, 249, 40, ++ 104, 5, 73, 34, 70, 249, 247, 61, 248, 32, 70, 189, 232, 56, 64, 180, ++ 247, 84, 189, 56, 189, 161, 96, 134, 0, 237, 190, 136, 0, 48, 181, 5, ++ 70, 135, 176, 8, 32, 177, 243, 56, 247, 4, 70, 0, 40, 62, 208, 0, 35, ++ 5, 96, 4, 33, 0, 147, 1, 144, 32, 74, 40, 70, 32, 75, 252, 247, 85, ++ 251, 0, 40, 96, 96, 49, 219, 40, 70, 30, 73, 34, 70, 252, 247, 107, ++ 251, 88, 187, 28, 75, 1, 144, 0, 147, 2, 144, 3, 144, 4, 144, 5, 144, ++ 26, 73, 40, 104, 26, 74, 35, 70, 249, 247, 101, 248, 232, 185, 24, 75, ++ 40, 104, 0, 147, 33, 70, 23, 74, 1, 35, 249, 247, 175, 248, 160, 185, ++ 22, 75, 213, 248, 124, 6, 141, 232, 24, 0, 79, 244, 144, 113, 40, 34, ++ 19, 75, 253, 247, 88, 251, 64, 185, 213, 248, 124, 6, 128, 33, 40, 34, ++ 16, 75, 0, 148, 253, 247, 251, 251, 24, 177, 32, 70, 255, 247, 153, ++ 255, 0, 36, 32, 70, 7, 176, 48, 189, 0, 191, 37, 96, 134, 0, 229, 95, ++ 134, 0, 161, 96, 134, 0, 69, 97, 134, 0, 204, 239, 135, 0, 237, 190, ++ 136, 0, 196, 239, 135, 0, 25, 97, 134, 0, 241, 133, 3, 0, 189, 133, ++ 3, 0, 201, 95, 134, 0, 112, 181, 6, 70, 134, 176, 156, 32, 177, 243, ++ 210, 246, 4, 70, 0, 40, 52, 208, 6, 96, 27, 75, 48, 104, 0, 37, 96, ++ 96, 26, 73, 0, 147, 26, 74, 35, 70, 1, 149, 2, 149, 3, 149, 4, 149, ++ 5, 149, 249, 247, 15, 248, 248, 185, 214, 248, 116, 52, 30, 34, 155, ++ 120, 34, 97, 4, 34, 226, 114, 2, 34, 35, 119, 34, 115, 1, 35, 10, 34, ++ 227, 118, 35, 114, 99, 97, 98, 115, 163, 118, 79, 246, 175, 114, 163, ++ 119, 132, 248, 153, 48, 16, 35, 160, 115, 96, 114, 160, 114, 34, 131, ++ 132, 248, 154, 48, 132, 248, 152, 48, 3, 224, 32, 70, 180, 247, 172, ++ 252, 44, 70, 32, 70, 6, 176, 112, 189, 0, 191, 1, 143, 3, 0, 168, 82, ++ 4, 0, 65, 182, 5, 0, 192, 248, 132, 16, 192, 248, 136, 32, 192, 248, ++ 140, 48, 112, 71, 0, 0, 16, 181, 4, 70, 72, 177, 5, 73, 34, 70, 64, ++ 104, 248, 247, 117, 255, 32, 70, 189, 232, 16, 64, 180, 247, 140, 188, ++ 16, 189, 65, 182, 5, 0, 56, 181, 4, 70, 216, 177, 80, 248, 20, 91, 174, ++ 247, 69, 253, 4, 241, 24, 0, 174, 247, 65, 253, 4, 241, 16, 0, 177, ++ 247, 70, 252, 4, 241, 36, 0, 174, 247, 217, 251, 34, 70, 5, 73, 40, ++ 104, 248, 247, 85, 255, 32, 70, 180, 247, 110, 252, 43, 104, 0, 34, ++ 131, 248, 102, 33, 56, 189, 160, 88, 4, 0, 45, 233, 240, 65, 6, 70, ++ 134, 176, 40, 32, 177, 243, 79, 246, 4, 70, 0, 40, 97, 208, 6, 96, 0, ++ 37, 1, 144, 4, 33, 48, 70, 50, 74, 50, 75, 0, 149, 252, 247, 108, 250, ++ 168, 66, 96, 96, 84, 219, 4, 33, 48, 70, 47, 74, 47, 75, 0, 149, 1, ++ 148, 0, 240, 123, 249, 168, 66, 160, 96, 73, 219, 1, 39, 231, 96, 56, ++ 70, 43, 73, 43, 74, 115, 104, 176, 247, 62, 254, 32, 97, 0, 40, 62, ++ 208, 6, 33, 42, 70, 214, 248, 4, 128, 177, 247, 19, 248, 37, 73, 3, ++ 70, 66, 70, 34, 72, 174, 247, 124, 251, 96, 98, 0, 40, 47, 208, 7, 33, ++ 42, 70, 32, 105, 177, 247, 5, 248, 57, 70, 3, 70, 224, 97, 42, 70, 96, ++ 106, 174, 247, 143, 251, 57, 70, 2, 70, 160, 97, 32, 105, 176, 247, ++ 248, 255, 227, 105, 57, 70, 42, 70, 96, 106, 174, 247, 131, 251, 2, ++ 33, 2, 70, 96, 97, 32, 105, 176, 247, 236, 255, 18, 75, 48, 104, 141, ++ 232, 40, 0, 17, 73, 18, 74, 35, 70, 2, 149, 3, 149, 4, 149, 5, 149, ++ 248, 247, 63, 255, 24, 185, 51, 104, 131, 248, 102, 113, 3, 224, 32, ++ 70, 255, 247, 111, 255, 0, 36, 32, 70, 6, 176, 189, 232, 240, 129, 209, ++ 191, 3, 0, 199, 190, 3, 0, 249, 190, 3, 0, 81, 190, 3, 0, 215, 183, ++ 3, 0, 129, 183, 3, 0, 53, 189, 3, 0, 60, 88, 4, 0, 160, 88, 4, 0, 45, ++ 233, 240, 67, 7, 70, 135, 176, 79, 244, 65, 112, 14, 70, 21, 70, 152, ++ 70, 180, 247, 211, 251, 4, 70, 0, 40, 122, 208, 0, 33, 79, 244, 65, ++ 114, 172, 243, 177, 247, 40, 32, 180, 247, 200, 251, 129, 70, 32, 96, ++ 32, 185, 32, 70, 180, 247, 197, 251, 72, 70, 106, 224, 0, 33, 40, 34, ++ 172, 243, 162, 247, 35, 104, 79, 244, 65, 114, 28, 96, 98, 97, 229, ++ 96, 79, 240, 255, 50, 0, 37, 162, 97, 167, 96, 196, 248, 4, 128, 157, ++ 113, 20, 35, 164, 248, 8, 50, 40, 35, 164, 248, 6, 50, 45, 35, 164, ++ 248, 4, 50, 110, 35, 164, 248, 10, 50, 2, 35, 132, 248, 12, 50, 100, ++ 35, 164, 248, 56, 50, 132, 248, 13, 82, 48, 70, 35, 73, 34, 70, 43, ++ 70, 194, 243, 100, 244, 196, 248, 248, 1, 64, 179, 4, 245, 20, 115, ++ 196, 248, 24, 50, 196, 248, 20, 50, 29, 75, 5, 38, 196, 248, 28, 98, ++ 0, 147, 27, 75, 2, 149, 1, 147, 27, 75, 27, 73, 3, 147, 27, 75, 28, ++ 74, 4, 147, 28, 75, 5, 147, 56, 104, 35, 70, 248, 247, 185, 254, 3, ++ 70, 96, 185, 0, 144, 56, 104, 33, 104, 23, 74, 248, 247, 4, 255, 40, ++ 185, 132, 248, 64, 98, 132, 248, 65, 98, 32, 104, 18, 224, 212, 248, ++ 248, 17, 25, 177, 163, 104, 152, 104, 194, 243, 35, 244, 32, 105, 8, ++ 177, 0, 240, 67, 248, 32, 104, 8, 177, 180, 247, 92, 251, 32, 70, 180, ++ 247, 89, 251, 0, 32, 7, 176, 189, 232, 240, 131, 93, 206, 3, 0, 105, ++ 140, 134, 0, 169, 147, 134, 0, 45, 157, 134, 0, 148, 250, 135, 0, 24, ++ 89, 4, 0, 51, 197, 136, 0, 175, 203, 3, 0, 89, 158, 134, 0, 56, 181, ++ 5, 70, 240, 177, 4, 104, 228, 177, 212, 248, 248, 17, 49, 177, 163, ++ 104, 152, 104, 194, 243, 246, 243, 0, 35, 196, 248, 248, 49, 163, 104, ++ 34, 70, 24, 104, 8, 73, 248, 247, 18, 254, 163, 104, 33, 104, 24, 104, ++ 248, 247, 44, 255, 40, 70, 180, 247, 38, 251, 32, 70, 189, 232, 56, ++ 64, 180, 247, 33, 187, 56, 189, 0, 191, 51, 197, 136, 0, 16, 181, 4, ++ 70, 48, 177, 230, 247, 92, 250, 32, 70, 189, 232, 16, 64, 180, 247, ++ 19, 187, 16, 189, 0, 0, 247, 181, 6, 104, 5, 70, 243, 105, 31, 109, ++ 2, 55, 63, 1, 56, 70, 180, 247, 4, 251, 4, 70, 16, 179, 0, 33, 58, 70, ++ 172, 243, 228, 246, 132, 232, 96, 0, 16, 33, 0, 38, 40, 70, 14, 74, ++ 14, 75, 0, 150, 1, 148, 252, 247, 15, 249, 176, 66, 160, 97, 12, 219, ++ 4, 241, 32, 3, 99, 97, 79, 244, 55, 115, 227, 96, 213, 248, 32, 6, 4, ++ 241, 28, 1, 172, 243, 180, 240, 24, 177, 32, 70, 180, 247, 227, 250, ++ 52, 70, 32, 70, 254, 189, 0, 191, 137, 163, 134, 0, 137, 211, 3, 0, ++ 16, 181, 4, 70, 72, 177, 195, 105, 19, 177, 28, 48, 172, 243, 182, 240, ++ 32, 70, 189, 232, 16, 64, 180, 247, 206, 186, 16, 189, 240, 181, 208, ++ 248, 36, 65, 0, 104, 37, 105, 192, 105, 0, 109, 133, 66, 17, 210, 103, ++ 105, 46, 1, 184, 25, 1, 53, 37, 97, 67, 96, 5, 155, 186, 81, 131, 96, ++ 6, 155, 195, 96, 224, 104, 195, 28, 89, 24, 33, 240, 3, 1, 225, 96, ++ 240, 189, 79, 240, 255, 48, 240, 189, 55, 181, 5, 70, 24, 32, 180, 247, ++ 167, 250, 4, 70, 56, 179, 0, 33, 24, 34, 172, 243, 135, 246, 43, 104, ++ 37, 96, 99, 96, 107, 104, 40, 70, 163, 96, 255, 247, 143, 251, 224, ++ 96, 136, 177, 20, 240, 73, 219, 0, 35, 1, 70, 141, 232, 24, 0, 40, 70, ++ 10, 74, 11, 75, 255, 247, 194, 255, 0, 40, 32, 97, 3, 219, 13, 240, ++ 229, 219, 96, 97, 7, 224, 224, 104, 8, 177, 255, 247, 177, 251, 32, ++ 70, 180, 247, 129, 250, 0, 36, 32, 70, 62, 189, 0, 191, 225, 180, 134, ++ 0, 189, 180, 134, 0, 16, 181, 4, 70, 56, 177, 192, 104, 255, 247, 160, ++ 251, 32, 70, 189, 232, 16, 64, 180, 247, 110, 186, 16, 189, 115, 181, ++ 5, 70, 24, 32, 180, 247, 101, 250, 4, 70, 0, 40, 56, 208, 0, 33, 24, ++ 34, 172, 243, 68, 246, 12, 32, 180, 247, 91, 250, 6, 70, 0, 40, 45, ++ 208, 0, 33, 12, 34, 172, 243, 58, 246, 43, 104, 102, 97, 37, 96, 99, ++ 96, 40, 70, 255, 247, 103, 253, 160, 96, 184, 177, 230, 247, 55, 251, ++ 0, 35, 1, 70, 141, 232, 40, 0, 40, 70, 14, 74, 15, 75, 255, 247, 118, ++ 255, 0, 40, 224, 96, 9, 219, 228, 247, 171, 250, 12, 73, 32, 97, 12, ++ 74, 160, 104, 12, 75, 255, 247, 150, 253, 9, 224, 160, 104, 8, 177, ++ 255, 247, 153, 253, 32, 70, 180, 247, 47, 250, 0, 36, 0, 224, 4, 70, ++ 32, 70, 124, 189, 0, 191, 117, 213, 3, 0, 83, 213, 3, 0, 41, 213, 3, ++ 0, 53, 213, 3, 0, 65, 213, 3, 0, 16, 181, 4, 70, 80, 177, 128, 104, ++ 255, 247, 128, 253, 96, 105, 180, 247, 22, 250, 32, 70, 189, 232, 16, ++ 64, 180, 247, 17, 186, 16, 189, 0, 0, 112, 181, 67, 75, 134, 176, 0, ++ 147, 0, 35, 1, 147, 2, 147, 3, 147, 4, 147, 5, 147, 4, 70, 63, 73, 0, ++ 104, 63, 74, 35, 70, 248, 247, 61, 253, 5, 70, 0, 40, 111, 209, 212, ++ 248, 116, 52, 20, 33, 163, 248, 100, 16, 163, 106, 1, 38, 131, 248, ++ 76, 0, 227, 106, 32, 70, 131, 248, 76, 96, 161, 106, 231, 247, 237, ++ 253, 225, 106, 32, 70, 231, 247, 233, 253, 32, 70, 41, 70, 231, 247, ++ 130, 251, 163, 106, 131, 248, 77, 80, 227, 106, 131, 248, 77, 80, 35, ++ 106, 24, 105, 215, 247, 116, 253, 131, 7, 7, 213, 212, 248, 116, 52, ++ 79, 240, 255, 50, 94, 115, 212, 248, 116, 52, 218, 129, 35, 104, 212, ++ 248, 116, 84, 94, 105, 224, 247, 159, 255, 1, 70, 48, 70, 224, 247, ++ 111, 255, 232, 98, 0, 40, 54, 208, 212, 248, 116, 52, 31, 34, 131, 248, ++ 120, 32, 212, 248, 116, 4, 5, 34, 87, 48, 79, 240, 255, 49, 172, 243, ++ 152, 245, 35, 104, 212, 248, 116, 36, 179, 248, 204, 16, 211, 248, 220, ++ 0, 81, 133, 10, 33, 81, 99, 20, 73, 173, 243, 223, 243, 67, 30, 13, ++ 43, 212, 248, 116, 84, 35, 104, 152, 191, 104, 99, 16, 73, 211, 248, ++ 220, 0, 173, 243, 211, 243, 133, 248, 138, 0, 212, 248, 116, 52, 1, ++ 34, 131, 248, 81, 32, 212, 248, 116, 52, 0, 32, 26, 120, 131, 248, 78, ++ 32, 212, 248, 116, 52, 88, 103, 1, 224, 79, 240, 255, 48, 6, 176, 112, ++ 189, 175, 239, 3, 0, 32, 91, 4, 0, 73, 182, 5, 0, 92, 182, 5, 0, 77, ++ 182, 5, 0, 208, 248, 116, 52, 16, 181, 217, 106, 4, 70, 17, 177, 64, ++ 104, 224, 247, 44, 255, 32, 104, 2, 73, 34, 70, 189, 232, 16, 64, 248, ++ 247, 81, 188, 73, 182, 5, 0, 56, 181, 3, 104, 4, 70, 208, 248, 116, ++ 84, 39, 73, 211, 248, 220, 0, 173, 243, 152, 243, 40, 112, 35, 104, ++ 36, 73, 211, 248, 220, 0, 212, 248, 116, 84, 173, 243, 143, 243, 232, ++ 112, 212, 248, 116, 52, 26, 120, 1, 58, 210, 178, 253, 42, 1, 217, 1, ++ 34, 26, 112, 212, 248, 116, 52, 26, 120, 90, 112, 0, 35, 212, 248, 116, ++ 36, 209, 24, 18, 120, 1, 51, 5, 43, 129, 248, 82, 32, 246, 209, 212, ++ 248, 116, 84, 1, 33, 40, 70, 172, 243, 133, 247, 168, 112, 212, 248, ++ 116, 52, 218, 120, 1, 58, 210, 178, 253, 42, 1, 217, 1, 34, 218, 112, ++ 212, 248, 116, 52, 1, 33, 218, 120, 90, 113, 212, 248, 116, 84, 232, ++ 28, 172, 243, 113, 247, 40, 113, 212, 248, 116, 52, 32, 70, 26, 121, ++ 154, 113, 230, 247, 203, 255, 180, 248, 72, 20, 32, 70, 189, 232, 56, ++ 64, 231, 247, 84, 188, 105, 182, 5, 0, 113, 182, 5, 0, 16, 181, 4, 70, ++ 216, 177, 64, 104, 13, 73, 34, 70, 239, 243, 8, 245, 35, 106, 27, 177, ++ 4, 241, 32, 0, 171, 243, 232, 246, 35, 127, 35, 177, 96, 104, 8, 73, ++ 34, 70, 251, 247, 58, 255, 160, 104, 6, 73, 34, 70, 248, 247, 221, 251, ++ 32, 70, 189, 232, 16, 64, 180, 247, 244, 184, 16, 189, 233, 206, 134, ++ 0, 173, 204, 134, 0, 244, 92, 4, 0, 48, 181, 5, 70, 135, 176, 36, 32, ++ 180, 247, 228, 248, 4, 70, 0, 40, 62, 208, 0, 33, 36, 34, 172, 243, ++ 195, 244, 43, 104, 0, 34, 163, 96, 171, 104, 101, 96, 227, 96, 107, ++ 104, 4, 33, 35, 97, 8, 35, 163, 130, 40, 70, 25, 75, 141, 232, 20, 0, ++ 251, 247, 232, 254, 0, 40, 32, 96, 34, 219, 40, 70, 21, 73, 34, 70, ++ 251, 247, 254, 254, 224, 185, 1, 35, 35, 119, 40, 70, 18, 73, 34, 70, ++ 239, 243, 182, 244, 160, 185, 213, 248, 32, 6, 4, 241, 32, 1, 171, 243, ++ 133, 246, 104, 185, 13, 75, 1, 144, 0, 147, 2, 144, 3, 144, 4, 144, ++ 5, 144, 11, 73, 40, 104, 11, 74, 35, 70, 248, 247, 233, 251, 24, 177, ++ 32, 70, 255, 247, 147, 255, 0, 36, 32, 70, 7, 176, 48, 189, 0, 191, ++ 249, 204, 134, 0, 173, 204, 134, 0, 233, 206, 134, 0, 109, 205, 134, ++ 0, 92, 251, 135, 0, 244, 92, 4, 0, 208, 248, 188, 54, 24, 106, 171, ++ 243, 57, 182, 208, 248, 188, 54, 24, 106, 171, 243, 150, 182, 248, 181, ++ 208, 248, 116, 100, 4, 70, 13, 70, 209, 248, 220, 0, 180, 73, 173, 243, ++ 184, 242, 134, 248, 28, 1, 178, 73, 213, 248, 220, 0, 212, 248, 116, ++ 100, 173, 243, 175, 242, 134, 248, 232, 0, 213, 248, 220, 0, 174, 73, ++ 173, 243, 204, 242, 212, 248, 116, 100, 56, 177, 213, 248, 220, 0, 170, ++ 73, 173, 243, 160, 242, 134, 248, 88, 1, 2, 224, 255, 35, 134, 248, ++ 88, 49, 166, 73, 213, 248, 220, 0, 212, 248, 116, 100, 173, 243, 147, ++ 242, 164, 73, 198, 248, 32, 1, 213, 248, 220, 0, 212, 248, 116, 100, ++ 173, 243, 138, 242, 160, 73, 166, 248, 42, 1, 213, 248, 220, 0, 212, ++ 248, 116, 100, 173, 243, 129, 242, 157, 73, 166, 248, 44, 1, 213, 248, ++ 220, 0, 212, 248, 116, 100, 173, 243, 120, 242, 153, 73, 166, 248, 46, ++ 1, 213, 248, 220, 0, 212, 248, 116, 100, 173, 243, 111, 242, 134, 248, ++ 233, 0, 212, 248, 116, 52, 147, 248, 233, 32, 18, 185, 2, 34, 131, 248, ++ 233, 32, 213, 248, 220, 0, 144, 73, 212, 248, 116, 100, 173, 243, 94, ++ 242, 166, 248, 198, 0, 212, 248, 116, 100, 182, 249, 198, 48, 19, 185, ++ 1, 35, 166, 248, 198, 48, 213, 248, 220, 0, 136, 73, 173, 243, 79, 242, ++ 198, 248, 216, 0, 212, 248, 116, 100, 214, 248, 216, 48, 27, 185, 76, ++ 242, 80, 51, 198, 248, 216, 48, 150, 248, 233, 48, 1, 34, 154, 64, 214, ++ 248, 216, 16, 213, 248, 220, 0, 138, 66, 136, 191, 198, 248, 216, 32, ++ 2, 34, 18, 250, 3, 243, 123, 73, 198, 248, 220, 48, 173, 243, 48, 242, ++ 198, 248, 228, 0, 212, 248, 116, 100, 214, 248, 228, 48, 27, 185, 79, ++ 244, 150, 115, 198, 248, 228, 48, 213, 248, 220, 0, 115, 73, 173, 243, ++ 32, 242, 166, 248, 196, 0, 212, 248, 116, 100, 182, 249, 196, 48, 19, ++ 185, 25, 35, 166, 248, 196, 48, 109, 73, 213, 248, 220, 0, 173, 243, ++ 17, 242, 212, 248, 116, 52, 166, 248, 240, 0, 147, 248, 28, 33, 105, ++ 73, 131, 248, 29, 33, 212, 248, 116, 52, 147, 248, 29, 33, 131, 248, ++ 72, 33, 212, 248, 116, 52, 218, 121, 131, 248, 172, 32, 212, 248, 116, ++ 52, 26, 122, 131, 248, 69, 33, 212, 248, 116, 100, 79, 246, 162, 115, ++ 166, 248, 234, 48, 166, 248, 236, 48, 166, 248, 238, 48, 213, 248, 220, ++ 0, 173, 243, 234, 241, 166, 248, 242, 0, 212, 248, 116, 100, 182, 249, ++ 242, 48, 27, 185, 79, 246, 162, 115, 166, 248, 242, 48, 150, 248, 233, ++ 48, 1, 34, 18, 250, 3, 243, 214, 248, 216, 32, 80, 73, 147, 66, 136, ++ 191, 198, 248, 216, 48, 0, 35, 166, 248, 178, 48, 166, 248, 180, 48, ++ 166, 248, 182, 48, 198, 248, 184, 48, 198, 248, 188, 48, 198, 248, 192, ++ 48, 213, 248, 220, 0, 31, 70, 173, 243, 193, 241, 134, 248, 68, 1, 69, ++ 73, 213, 248, 220, 0, 212, 248, 116, 100, 173, 243, 184, 241, 134, 248, ++ 75, 1, 213, 248, 220, 0, 64, 73, 212, 248, 116, 100, 173, 243, 175, ++ 241, 212, 248, 116, 52, 198, 248, 36, 1, 131, 248, 41, 113, 212, 248, ++ 116, 52, 211, 248, 36, 33, 26, 185, 79, 244, 155, 114, 195, 248, 36, ++ 33, 147, 248, 29, 33, 2, 177, 3, 34, 195, 248, 76, 33, 195, 248, 80, ++ 33, 0, 34, 195, 248, 84, 33, 213, 248, 220, 0, 49, 73, 173, 243, 180, ++ 241, 64, 177, 213, 248, 220, 0, 46, 73, 212, 248, 116, 100, 173, 243, ++ 136, 241, 198, 248, 84, 1, 213, 248, 220, 0, 42, 73, 173, 243, 165, ++ 241, 64, 177, 213, 248, 220, 0, 39, 73, 212, 248, 116, 100, 173, 243, ++ 121, 241, 198, 248, 76, 1, 213, 248, 220, 0, 36, 73, 173, 243, 150, ++ 241, 64, 177, 213, 248, 220, 0, 33, 73, 212, 248, 116, 100, 173, 243, ++ 106, 241, 198, 248, 80, 1, 30, 73, 34, 70, 0, 35, 160, 104, 212, 248, ++ 116, 84, 193, 243, 246, 247, 27, 73, 197, 248, 48, 1, 34, 70, 160, 104, ++ 0, 35, 212, 248, 116, 84, 193, 243, 236, 247, 197, 248, 52, 1, 248, ++ 189, 0, 191, 4, 183, 5, 0, 122, 183, 5, 0, 74, 183, 5, 0, 45, 183, 5, ++ 0, 166, 182, 5, 0, 198, 182, 5, 0, 216, 182, 5, 0, 108, 183, 5, 0, 121, ++ 182, 5, 0, 61, 183, 5, 0, 247, 182, 5, 0, 153, 182, 5, 0, 151, 183, ++ 5, 0, 87, 183, 5, 0, 234, 182, 5, 0, 137, 182, 5, 0, 184, 182, 5, 0, ++ 133, 183, 5, 0, 13, 183, 5, 0, 29, 183, 5, 0, 5, 12, 4, 0, 183, 16, ++ 4, 0, 56, 181, 4, 70, 128, 177, 5, 104, 34, 70, 213, 248, 72, 1, 7, ++ 73, 253, 247, 115, 253, 40, 70, 6, 73, 34, 70, 251, 247, 28, 253, 32, ++ 70, 189, 232, 56, 64, 179, 247, 219, 190, 56, 189, 0, 191, 45, 249, ++ 134, 0, 193, 247, 134, 0, 55, 181, 5, 70, 8, 32, 177, 243, 191, 240, ++ 4, 70, 192, 177, 5, 96, 0, 34, 1, 144, 4, 33, 40, 70, 12, 75, 0, 146, ++ 251, 247, 222, 252, 0, 40, 96, 96, 12, 219, 40, 70, 9, 73, 34, 70, 251, ++ 247, 244, 252, 48, 185, 213, 248, 72, 1, 7, 73, 34, 70, 253, 247, 65, ++ 253, 24, 177, 32, 70, 255, 247, 195, 255, 0, 36, 32, 70, 62, 189, 105, ++ 248, 134, 0, 193, 247, 134, 0, 45, 249, 134, 0, 56, 181, 4, 70, 112, ++ 177, 5, 104, 33, 70, 40, 104, 248, 247, 164, 250, 40, 104, 5, 73, 34, ++ 70, 248, 247, 128, 249, 32, 70, 189, 232, 56, 64, 179, 247, 151, 190, ++ 56, 189, 0, 191, 250, 92, 4, 0, 48, 181, 5, 70, 135, 176, 12, 32, 177, ++ 243, 124, 240, 4, 70, 0, 40, 70, 208, 39, 75, 5, 96, 79, 244, 144, 113, ++ 0, 147, 1, 144, 32, 34, 213, 248, 124, 6, 35, 75, 252, 247, 197, 252, ++ 0, 40, 56, 209, 34, 75, 213, 248, 124, 6, 141, 232, 24, 0, 79, 244, ++ 144, 113, 35, 34, 31, 75, 252, 247, 184, 252, 0, 40, 43, 209, 29, 75, ++ 213, 248, 124, 6, 141, 232, 24, 0, 64, 33, 136, 34, 27, 75, 252, 247, ++ 204, 252, 0, 187, 213, 248, 124, 6, 128, 33, 32, 34, 24, 75, 0, 148, ++ 252, 247, 79, 253, 184, 185, 22, 75, 2, 144, 0, 147, 22, 75, 3, 144, ++ 1, 147, 4, 144, 5, 144, 20, 73, 40, 104, 20, 74, 35, 70, 248, 247, 140, ++ 249, 64, 185, 19, 75, 40, 104, 0, 147, 33, 70, 18, 74, 1, 35, 248, 247, ++ 214, 249, 24, 177, 32, 70, 255, 247, 151, 255, 0, 36, 32, 70, 7, 176, ++ 48, 189, 0, 191, 97, 93, 135, 0, 165, 91, 135, 0, 149, 93, 135, 0, 201, ++ 91, 135, 0, 1, 93, 135, 0, 145, 91, 135, 0, 121, 91, 135, 0, 181, 18, ++ 4, 0, 253, 92, 135, 0, 16, 93, 4, 0, 250, 92, 4, 0, 248, 252, 135, 0, ++ 237, 91, 135, 0, 16, 181, 4, 70, 96, 177, 7, 75, 7, 73, 27, 136, 34, ++ 70, 195, 88, 24, 104, 248, 247, 250, 248, 32, 70, 189, 232, 16, 64, ++ 179, 247, 17, 190, 16, 189, 0, 191, 22, 7, 0, 0, 52, 93, 4, 0, 240, ++ 181, 7, 70, 135, 176, 20, 32, 176, 243, 244, 247, 5, 70, 32, 179, 21, ++ 75, 6, 70, 0, 36, 4, 34, 6, 248, 4, 75, 26, 128, 1, 35, 71, 96, 51, ++ 114, 244, 96, 116, 114, 4, 33, 1, 144, 15, 74, 56, 70, 15, 75, 0, 148, ++ 255, 247, 34, 251, 160, 66, 112, 96, 13, 219, 13, 75, 0, 148, 1, 147, ++ 2, 148, 3, 148, 4, 148, 5, 148, 56, 104, 33, 70, 9, 74, 43, 70, 248, ++ 247, 30, 249, 24, 177, 40, 70, 255, 247, 186, 255, 0, 37, 40, 70, 7, ++ 176, 240, 189, 22, 7, 0, 0, 169, 94, 135, 0, 137, 94, 135, 0, 249, 94, ++ 135, 0, 52, 93, 4, 0, 112, 181, 5, 70, 134, 176, 24, 32, 176, 243, 182, ++ 247, 4, 70, 0, 40, 90, 208, 43, 104, 0, 38, 1, 34, 67, 96, 5, 96, 8, ++ 33, 131, 248, 177, 32, 1, 144, 50, 70, 40, 70, 51, 70, 0, 150, 255, ++ 247, 232, 250, 176, 66, 32, 97, 75, 219, 16, 33, 40, 70, 39, 74, 39, ++ 75, 0, 150, 1, 148, 251, 247, 195, 251, 176, 66, 197, 248, 156, 1, 63, ++ 219, 4, 35, 227, 96, 35, 75, 160, 96, 5, 33, 141, 232, 24, 0, 213, 248, ++ 124, 6, 68, 34, 32, 75, 252, 247, 224, 251, 0, 40, 48, 209, 30, 75, ++ 213, 248, 124, 6, 141, 232, 24, 0, 79, 244, 144, 113, 68, 34, 27, 75, ++ 252, 247, 211, 251, 0, 40, 35, 209, 213, 248, 124, 6, 5, 33, 68, 34, ++ 24, 75, 0, 148, 252, 247, 185, 253, 208, 185, 213, 248, 124, 6, 192, ++ 33, 68, 34, 20, 75, 0, 148, 252, 247, 176, 253, 136, 185, 19, 75, 1, ++ 144, 0, 147, 18, 75, 3, 144, 2, 147, 4, 144, 5, 144, 17, 73, 40, 104, ++ 17, 74, 35, 70, 248, 247, 169, 248, 16, 185, 32, 70, 6, 176, 112, 189, ++ 32, 70, 179, 247, 99, 253, 0, 36, 247, 231, 41, 104, 135, 0, 13, 104, ++ 135, 0, 137, 103, 135, 0, 217, 102, 135, 0, 229, 103, 135, 0, 177, 103, ++ 135, 0, 253, 102, 135, 0, 241, 107, 135, 0, 121, 105, 135, 0, 129, 108, ++ 135, 0, 68, 253, 135, 0, 56, 93, 4, 0, 16, 181, 4, 70, 72, 177, 5, 73, ++ 34, 70, 64, 104, 248, 247, 37, 248, 32, 70, 189, 232, 16, 64, 179, 247, ++ 60, 189, 16, 189, 56, 93, 4, 0, 119, 108, 99, 95, 98, 109, 97, 99, 95, ++ 105, 110, 102, 111, 95, 105, 110, 105, 116, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 100, 101, 97, ++ 100, 109, 97, 110, 95, 116, 111, 0, 114, 97, 109, 115, 116, 98, 121, ++ 100, 105, 115, 0, 100, 101, 97, 100, 109, 97, 110, 95, 116, 111, 0, ++ 115, 112, 105, 95, 112, 117, 95, 101, 110, 97, 98, 0, 83, 68, 73, 79, ++ 68, 69, 86, 0, 103, 115, 112, 105, 100, 119, 111, 114, 100, 0, 80, 67, ++ 77, 67, 73, 65, 68, 69, 86, 0, 115, 100, 95, 111, 111, 98, 111, 110, ++ 108, 121, 0, 115, 100, 95, 103, 112, 111, 117, 116, 0, 71, 83, 80, 73, ++ 32, 68, 119, 111, 114, 100, 32, 77, 111, 100, 101, 32, 101, 110, 97, ++ 98, 108, 101, 100, 10, 0, 115, 100, 95, 103, 112, 100, 99, 0, 115, 100, ++ 95, 103, 112, 118, 97, 108, 0, 37, 115, 58, 32, 66, 114, 111, 97, 100, ++ 99, 111, 109, 32, 83, 68, 80, 67, 77, 68, 32, 67, 68, 67, 32, 100, 114, ++ 105, 118, 101, 114, 10, 0, 115, 100, 112, 99, 109, 100, 99, 100, 99, ++ 37, 100, 0, 83, 68, 73, 79, 0, 10, 82, 84, 69, 32, 40, 37, 115, 45, ++ 37, 115, 37, 115, 37, 115, 41, 32, 37, 115, 32, 111, 110, 32, 66, 67, ++ 77, 37, 115, 32, 114, 37, 100, 32, 64, 32, 37, 100, 46, 37, 100, 47, ++ 37, 100, 46, 37, 100, 47, 37, 100, 46, 37, 100, 77, 72, 122, 10, 0, ++ 0, 67, 68, 67, 0, 110, 111, 99, 114, 99, 0, 110, 111, 116, 105, 102, ++ 95, 99, 0, 110, 111, 116, 105, 102, 95, 115, 0, 111, 102, 100, 109, ++ 50, 103, 112, 111, 61, 48, 120, 37, 120, 0, 112, 97, 37, 100, 103, 119, ++ 37, 100, 97, 37, 100, 61, 48, 120, 37, 120, 0, 112, 97, 49, 104, 105, ++ 98, 48, 61, 37, 100, 0, 112, 97, 49, 104, 105, 98, 49, 61, 37, 100, ++ 0, 112, 97, 49, 104, 105, 98, 50, 61, 37, 100, 0, 103, 97, 105, 110, ++ 99, 116, 114, 108, 115, 112, 104, 61, 37, 100, 0, 112, 97, 49, 109, ++ 97, 120, 112, 119, 114, 61, 37, 100, 0, 109, 101, 97, 115, 112, 111, ++ 119, 101, 114, 37, 100, 61, 48, 120, 37, 120, 0, 114, 120, 103, 97, ++ 105, 110, 115, 37, 100, 103, 37, 99, 116, 114, 101, 108, 110, 97, 98, ++ 121, 112, 97, 37, 100, 61, 37, 100, 0, 112, 97, 50, 103, 97, 37, 100, ++ 61, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 0, ++ 114, 115, 115, 105, 115, 109, 99, 53, 103, 61, 37, 100, 0, 117, 115, ++ 98, 102, 108, 97, 103, 115, 61, 48, 120, 37, 120, 0, 112, 97, 50, 103, ++ 99, 99, 107, 97, 37, 100, 61, 48, 120, 37, 120, 44, 48, 120, 37, 120, ++ 44, 48, 120, 37, 120, 0, 112, 100, 101, 116, 114, 97, 110, 103, 101, ++ 50, 103, 61, 48, 120, 37, 120, 0, 117, 115, 98, 51, 48, 117, 49, 117, ++ 50, 61, 48, 120, 37, 120, 0, 115, 117, 98, 118, 101, 110, 100, 105, ++ 100, 61, 48, 120, 37, 120, 0, 97, 103, 37, 100, 61, 48, 120, 37, 120, ++ 0, 111, 101, 109, 61, 37, 48, 50, 120, 37, 48, 50, 120, 37, 48, 50, ++ 120, 37, 48, 50, 120, 37, 48, 50, 120, 37, 48, 50, 120, 37, 48, 50, ++ 120, 37, 48, 50, 120, 0, 111, 102, 100, 109, 112, 111, 61, 48, 120, ++ 37, 120, 0, 116, 101, 109, 112, 111, 102, 102, 115, 101, 116, 61, 37, ++ 100, 0, 109, 101, 97, 115, 112, 111, 119, 101, 114, 61, 48, 120, 37, ++ 120, 0, 114, 115, 115, 105, 115, 109, 102, 50, 103, 61, 37, 100, 0, ++ 112, 97, 112, 97, 114, 97, 109, 98, 119, 118, 101, 114, 61, 37, 100, ++ 0, 100, 111, 116, 49, 49, 97, 103, 111, 102, 100, 109, 104, 114, 98, ++ 119, 50, 48, 50, 103, 112, 111, 61, 48, 120, 37, 120, 0, 105, 116, 116, ++ 50, 103, 97, 48, 61, 48, 120, 37, 120, 0, 98, 120, 97, 50, 103, 61, ++ 37, 100, 0, 114, 115, 115, 105, 115, 109, 99, 50, 103, 61, 37, 100, ++ 0, 112, 97, 53, 103, 98, 119, 52, 48, 97, 37, 100, 61, 48, 120, 37, ++ 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, ++ 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, ++ 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, ++ 120, 37, 120, 44, 48, 120, 37, 120, 0, 109, 99, 115, 98, 119, 50, 48, ++ 53, 103, 108, 112, 111, 61, 48, 120, 37, 120, 0, 0, 0, 109, 99, 115, ++ 98, 119, 50, 48, 117, 108, 53, 103, 108, 112, 111, 61, 48, 120, 37, ++ 120, 0, 109, 99, 115, 98, 119, 52, 48, 53, 103, 108, 112, 111, 61, 48, ++ 120, 37, 120, 0, 0, 0, 117, 115, 98, 117, 116, 109, 105, 95, 99, 116, ++ 108, 61, 48, 120, 37, 120, 0, 101, 120, 116, 112, 97, 103, 97, 105, ++ 110, 50, 103, 61, 48, 120, 37, 120, 0, 97, 110, 116, 115, 119, 99, 116, ++ 108, 50, 103, 61, 48, 120, 37, 120, 0, 112, 114, 111, 100, 117, 99, ++ 116, 110, 97, 109, 101, 61, 37, 115, 0, 116, 120, 95, 100, 117, 116, ++ 121, 95, 99, 121, 99, 108, 101, 95, 116, 104, 114, 101, 115, 104, 95, ++ 37, 100, 95, 53, 103, 61, 37, 100, 0, 114, 120, 103, 97, 105, 110, 101, ++ 114, 114, 50, 103, 97, 37, 100, 61, 48, 120, 37, 120, 0, 97, 103, 48, ++ 0, 109, 97, 120, 112, 50, 103, 97, 37, 100, 61, 48, 120, 37, 120, 0, ++ 98, 119, 100, 117, 112, 112, 111, 61, 48, 120, 37, 120, 0, 110, 111, ++ 105, 115, 101, 108, 118, 108, 53, 103, 97, 37, 100, 61, 37, 100, 44, ++ 37, 100, 44, 37, 100, 44, 37, 100, 0, 98, 119, 52, 48, 112, 111, 61, ++ 48, 120, 37, 120, 0, 112, 97, 53, 103, 98, 119, 56, 48, 97, 37, 100, ++ 61, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, ++ 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, ++ 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, ++ 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 0, 117, 115, 98, ++ 51, 48, 117, 49, 117, 50, 61, 48, 120, 37, 120, 0, 112, 100, 101, 116, ++ 114, 97, 110, 103, 101, 53, 103, 61, 48, 120, 37, 120, 0, 109, 97, 99, ++ 97, 100, 100, 114, 61, 37, 115, 0, 116, 101, 109, 112, 115, 95, 104, ++ 121, 115, 116, 101, 114, 101, 115, 105, 115, 61, 37, 100, 0, 109, 99, ++ 115, 37, 100, 103, 112, 111, 37, 100, 61, 48, 120, 37, 120, 0, 98, 111, ++ 97, 114, 100, 102, 108, 97, 103, 115, 50, 61, 48, 120, 37, 120, 0, 98, ++ 111, 97, 114, 100, 102, 108, 97, 103, 115, 51, 61, 48, 120, 37, 120, ++ 0, 108, 101, 100, 98, 104, 37, 100, 61, 48, 120, 37, 120, 0, 114, 120, ++ 103, 97, 105, 110, 115, 37, 100, 103, 37, 99, 116, 114, 105, 115, 111, ++ 97, 37, 100, 61, 37, 100, 0, 97, 97, 50, 103, 61, 48, 120, 37, 120, ++ 0, 112, 114, 111, 100, 105, 100, 61, 48, 120, 37, 120, 0, 116, 101, ++ 109, 112, 116, 104, 114, 101, 115, 104, 61, 37, 100, 0, 99, 104, 105, ++ 112, 114, 101, 118, 61, 37, 100, 0, 108, 101, 103, 111, 102, 100, 109, ++ 98, 119, 50, 48, 53, 103, 108, 112, 111, 61, 48, 120, 37, 120, 0, 0, ++ 0, 108, 101, 103, 111, 102, 100, 109, 98, 119, 50, 48, 117, 108, 53, ++ 103, 108, 112, 111, 61, 48, 120, 37, 120, 0, 108, 101, 103, 111, 102, ++ 100, 109, 98, 119, 50, 48, 53, 103, 109, 112, 111, 61, 48, 120, 37, ++ 120, 0, 0, 0, 108, 101, 103, 111, 102, 100, 109, 98, 119, 50, 48, 117, ++ 108, 53, 103, 109, 112, 111, 61, 48, 120, 37, 120, 0, 108, 101, 103, ++ 111, 102, 100, 109, 98, 119, 50, 48, 53, 103, 104, 112, 111, 61, 48, ++ 120, 37, 120, 0, 0, 0, 108, 101, 103, 111, 102, 100, 109, 98, 119, 50, ++ 48, 117, 108, 53, 103, 104, 112, 111, 61, 48, 120, 37, 120, 0, 117, ++ 115, 98, 102, 115, 61, 37, 100, 0, 116, 101, 109, 112, 115, 95, 112, ++ 101, 114, 105, 111, 100, 61, 37, 100, 0, 115, 98, 52, 48, 97, 110, 100, ++ 56, 48, 37, 99, 114, 53, 103, 37, 99, 112, 111, 61, 48, 120, 37, 120, ++ 0, 99, 99, 61, 37, 100, 0, 32, 4, 208, 2, 166, 169, 255, 255, 100, 111, ++ 116, 49, 49, 97, 103, 100, 117, 112, 37, 99, 114, 112, 111, 61, 48, ++ 120, 37, 120, 0, 97, 103, 97, 37, 100, 61, 48, 120, 37, 120, 0, 116, ++ 114, 105, 115, 111, 53, 103, 61, 48, 120, 37, 120, 0, 116, 101, 109, ++ 112, 115, 101, 110, 115, 101, 95, 115, 108, 111, 112, 101, 61, 37, 100, ++ 0, 109, 97, 120, 112, 53, 103, 97, 37, 100, 61, 48, 120, 37, 120, 44, ++ 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 0, 112, ++ 97, 49, 105, 116, 115, 115, 105, 116, 61, 37, 100, 0, 112, 97, 48, 98, ++ 48, 61, 37, 100, 0, 112, 97, 48, 98, 49, 61, 37, 100, 0, 112, 97, 48, ++ 98, 50, 61, 37, 100, 0, 112, 97, 53, 103, 97, 37, 100, 61, 48, 120, ++ 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, ++ 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, ++ 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, ++ 48, 120, 37, 120, 44, 48, 120, 37, 120, 0, 109, 99, 115, 98, 119, 56, ++ 48, 53, 103, 37, 99, 112, 111, 61, 48, 120, 37, 120, 0, 115, 117, 98, ++ 98, 97, 110, 100, 53, 103, 118, 101, 114, 61, 37, 100, 0, 114, 115, ++ 115, 105, 115, 97, 118, 53, 103, 61, 37, 100, 0, 109, 99, 115, 98, 119, ++ 50, 48, 50, 103, 112, 111, 61, 48, 120, 37, 120, 0, 0, 0, 109, 99, 115, ++ 98, 119, 50, 48, 117, 108, 50, 103, 112, 111, 61, 48, 120, 37, 120, ++ 0, 109, 99, 115, 98, 119, 52, 48, 50, 103, 112, 111, 61, 48, 120, 37, ++ 120, 0, 0, 0, 114, 101, 103, 114, 101, 118, 61, 48, 120, 37, 120, 0, ++ 99, 99, 116, 108, 61, 48, 120, 37, 120, 0, 110, 111, 105, 115, 101, ++ 108, 118, 108, 50, 103, 97, 37, 100, 61, 37, 100, 0, 117, 115, 98, 51, ++ 48, 114, 101, 103, 115, 48, 61, 48, 120, 37, 120, 44, 48, 120, 37, 120, ++ 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, ++ 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, ++ 120, 37, 120, 44, 48, 120, 37, 120, 0, 117, 115, 98, 51, 48, 114, 101, ++ 103, 115, 49, 61, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, ++ 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, ++ 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, ++ 44, 48, 120, 37, 120, 0, 99, 99, 107, 112, 111, 61, 48, 120, 37, 120, ++ 0, 116, 114, 105, 53, 103, 61, 37, 100, 0, 99, 99, 107, 100, 105, 103, ++ 102, 105, 108, 116, 116, 121, 112, 101, 61, 37, 100, 0, 118, 101, 110, ++ 100, 105, 100, 61, 48, 120, 37, 120, 0, 102, 101, 109, 99, 116, 114, ++ 108, 61, 37, 100, 0, 117, 115, 98, 51, 48, 114, 101, 103, 115, 37, 100, ++ 61, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, ++ 48, 120, 37, 120, 0, 112, 100, 111, 102, 102, 115, 101, 116, 50, 103, ++ 37, 100, 109, 97, 37, 100, 61, 48, 120, 37, 120, 0, 117, 115, 98, 101, ++ 112, 110, 117, 109, 61, 48, 120, 37, 120, 0, 112, 97, 49, 104, 105, ++ 109, 97, 120, 112, 119, 114, 61, 37, 100, 0, 114, 120, 99, 104, 97, ++ 105, 110, 61, 48, 120, 37, 120, 0, 98, 111, 97, 114, 100, 102, 108, ++ 97, 103, 115, 61, 48, 120, 37, 120, 0, 112, 97, 49, 98, 48, 61, 37, ++ 100, 0, 112, 97, 49, 98, 49, 61, 37, 100, 0, 112, 97, 49, 98, 50, 61, ++ 37, 100, 0, 116, 120, 99, 104, 97, 105, 110, 61, 48, 120, 37, 120, 0, ++ 114, 120, 103, 97, 105, 110, 115, 37, 100, 103, 37, 99, 101, 108, 110, ++ 97, 103, 97, 105, 110, 97, 37, 100, 61, 37, 100, 0, 103, 112, 100, 110, ++ 61, 48, 120, 37, 120, 0, 112, 97, 48, 109, 97, 120, 112, 119, 114, 61, ++ 37, 100, 0, 98, 120, 97, 53, 103, 61, 37, 100, 0, 97, 103, 98, 103, ++ 37, 100, 61, 48, 120, 37, 120, 0, 117, 115, 98, 115, 115, 112, 104, ++ 121, 95, 115, 108, 101, 101, 112, 48, 61, 48, 120, 37, 120, 0, 117, ++ 115, 98, 115, 115, 112, 104, 121, 95, 115, 108, 101, 101, 112, 49, 61, ++ 48, 120, 37, 120, 0, 117, 115, 98, 115, 115, 112, 104, 121, 95, 115, ++ 108, 101, 101, 112, 50, 61, 48, 120, 37, 120, 0, 117, 115, 98, 115, ++ 115, 112, 104, 121, 95, 115, 108, 101, 101, 112, 51, 61, 48, 120, 37, ++ 120, 0, 108, 101, 100, 100, 99, 61, 48, 120, 37, 48, 52, 120, 0, 109, ++ 99, 115, 51, 50, 112, 111, 61, 48, 120, 37, 120, 0, 114, 115, 115, 105, ++ 115, 97, 118, 50, 103, 61, 37, 100, 0, 111, 112, 111, 61, 37, 100, 0, ++ 105, 116, 116, 50, 103, 97, 49, 61, 48, 120, 37, 120, 0, 114, 120, 112, ++ 111, 53, 103, 61, 37, 100, 0, 101, 120, 116, 112, 97, 103, 97, 105, ++ 110, 53, 103, 61, 48, 120, 37, 120, 0, 111, 102, 100, 109, 53, 103, ++ 104, 112, 111, 61, 48, 120, 37, 120, 0, 116, 119, 111, 114, 97, 110, ++ 103, 101, 116, 115, 115, 105, 37, 100, 103, 61, 37, 100, 0, 115, 98, ++ 50, 48, 105, 110, 52, 48, 37, 99, 114, 112, 111, 61, 48, 120, 37, 120, ++ 0, 109, 97, 110, 102, 105, 100, 61, 48, 120, 37, 120, 0, 101, 108, 110, ++ 97, 50, 103, 61, 48, 120, 37, 120, 0, 114, 112, 99, 97, 108, 50, 103, ++ 61, 48, 120, 37, 120, 0, 0, 0, 0, 0, 0, 0, 0, 114, 112, 99, 97, 108, ++ 53, 103, 98, 48, 61, 48, 120, 37, 120, 0, 0, 0, 0, 0, 0, 114, 112, 99, ++ 97, 108, 53, 103, 98, 49, 61, 48, 120, 37, 120, 0, 0, 0, 0, 0, 0, 114, ++ 112, 99, 97, 108, 53, 103, 98, 50, 61, 48, 120, 37, 120, 0, 0, 0, 0, ++ 0, 0, 114, 112, 99, 97, 108, 53, 103, 98, 51, 61, 48, 120, 37, 120, ++ 0, 0, 0, 0, 0, 0, 112, 97, 48, 98, 48, 95, 108, 111, 61, 37, 100, 0, ++ 112, 97, 48, 98, 49, 95, 108, 111, 61, 37, 100, 0, 112, 97, 48, 98, ++ 50, 95, 108, 111, 61, 37, 100, 0, 115, 98, 50, 48, 105, 110, 56, 48, ++ 97, 110, 100, 49, 54, 48, 37, 99, 114, 53, 103, 37, 99, 112, 111, 61, ++ 48, 120, 37, 120, 0, 99, 100, 100, 112, 111, 61, 48, 120, 37, 120, 0, ++ 98, 111, 97, 114, 100, 116, 121, 112, 101, 61, 48, 120, 37, 120, 0, ++ 97, 110, 116, 115, 119, 105, 116, 99, 104, 61, 48, 120, 37, 120, 0, ++ 98, 111, 97, 114, 100, 110, 117, 109, 61, 37, 100, 0, 114, 100, 108, ++ 105, 100, 61, 48, 120, 37, 120, 0, 120, 116, 97, 108, 102, 114, 101, ++ 113, 61, 37, 100, 0, 109, 97, 120, 112, 53, 103, 104, 97, 48, 61, 48, ++ 120, 37, 120, 0, 114, 120, 103, 97, 105, 110, 115, 37, 100, 103, 101, ++ 108, 110, 97, 103, 97, 105, 110, 97, 37, 100, 61, 37, 100, 0, 117, 115, ++ 98, 115, 115, 109, 100, 105, 111, 37, 100, 61, 48, 120, 37, 120, 44, ++ 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 0, 115, ++ 117, 98, 100, 101, 118, 105, 100, 61, 48, 120, 37, 120, 0, 112, 97, ++ 49, 108, 111, 98, 48, 61, 37, 100, 0, 112, 97, 49, 108, 111, 98, 49, ++ 61, 37, 100, 0, 112, 97, 49, 108, 111, 98, 50, 61, 37, 100, 0, 115, ++ 116, 98, 99, 112, 111, 61, 48, 120, 37, 120, 0, 114, 120, 103, 97, 105, ++ 110, 101, 114, 114, 53, 103, 97, 37, 100, 61, 48, 120, 37, 120, 44, ++ 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 0, 112, ++ 97, 49, 108, 111, 109, 97, 120, 112, 119, 114, 61, 37, 100, 0, 112, ++ 100, 111, 102, 102, 115, 101, 116, 37, 100, 109, 97, 37, 100, 61, 48, ++ 120, 37, 120, 0, 116, 101, 109, 112, 99, 111, 114, 114, 120, 61, 37, ++ 100, 0, 111, 102, 100, 109, 53, 103, 112, 111, 61, 48, 120, 37, 120, ++ 0, 117, 115, 98, 110, 111, 115, 115, 61, 48, 120, 37, 120, 0, 97, 97, ++ 53, 103, 61, 48, 120, 37, 120, 0, 99, 117, 115, 116, 111, 109, 118, ++ 97, 114, 37, 100, 61, 48, 120, 37, 120, 0, 116, 120, 95, 100, 117, 116, ++ 121, 95, 99, 121, 99, 108, 101, 95, 111, 102, 100, 109, 95, 37, 100, ++ 95, 53, 103, 61, 37, 100, 0, 117, 117, 105, 100, 61, 37, 115, 0, 117, ++ 115, 98, 100, 101, 115, 99, 95, 99, 111, 109, 112, 111, 115, 105, 116, ++ 101, 61, 48, 120, 37, 120, 0, 116, 101, 109, 112, 115, 101, 110, 115, ++ 101, 95, 111, 112, 116, 105, 111, 110, 61, 37, 100, 0, 112, 97, 112, ++ 100, 99, 97, 112, 37, 100, 103, 61, 37, 100, 0, 108, 101, 103, 111, ++ 102, 100, 109, 98, 119, 50, 48, 50, 103, 112, 111, 61, 48, 120, 37, ++ 120, 0, 0, 0, 108, 101, 103, 111, 102, 100, 109, 98, 119, 50, 48, 117, ++ 108, 50, 103, 112, 111, 61, 48, 120, 37, 120, 0, 112, 100, 103, 97, ++ 105, 110, 37, 100, 103, 61, 37, 100, 0, 109, 97, 120, 112, 53, 103, ++ 97, 48, 61, 48, 120, 37, 120, 0, 109, 97, 120, 112, 53, 103, 97, 49, ++ 61, 48, 120, 37, 120, 0, 109, 99, 115, 37, 100, 103, 37, 99, 112, 111, ++ 37, 100, 61, 48, 120, 37, 120, 0, 112, 104, 121, 99, 97, 108, 95, 116, ++ 101, 109, 112, 100, 101, 108, 116, 97, 61, 37, 100, 0, 112, 97, 37, ++ 100, 103, 37, 99, 119, 37, 100, 97, 37, 100, 61, 48, 120, 37, 120, 0, ++ 99, 99, 111, 100, 101, 61, 48, 120, 48, 0, 114, 101, 103, 119, 105, ++ 110, 100, 111, 119, 115, 122, 61, 37, 100, 0, 111, 102, 100, 109, 108, ++ 114, 98, 119, 50, 48, 50, 103, 112, 111, 61, 48, 120, 37, 120, 0, 119, ++ 111, 119, 108, 95, 103, 112, 105, 111, 112, 111, 108, 61, 37, 100, 0, ++ 97, 110, 116, 115, 119, 99, 116, 108, 53, 103, 61, 48, 120, 37, 120, ++ 0, 99, 99, 107, 50, 103, 112, 111, 61, 48, 120, 37, 120, 0, 116, 114, ++ 105, 50, 103, 61, 37, 100, 0, 99, 99, 107, 98, 119, 50, 48, 50, 103, ++ 112, 111, 61, 48, 120, 37, 120, 0, 0, 0, 99, 99, 107, 98, 119, 50, 48, ++ 117, 108, 50, 103, 112, 111, 61, 48, 120, 37, 120, 0, 105, 116, 116, ++ 53, 103, 97, 48, 61, 48, 120, 37, 120, 0, 105, 116, 116, 53, 103, 97, ++ 49, 61, 48, 120, 37, 120, 0, 109, 99, 115, 108, 114, 53, 103, 37, 99, ++ 112, 111, 61, 48, 120, 37, 120, 0, 112, 100, 111, 102, 102, 115, 101, ++ 116, 50, 103, 37, 100, 109, 118, 97, 108, 105, 100, 61, 48, 120, 37, ++ 120, 0, 114, 120, 103, 97, 105, 110, 115, 37, 100, 103, 116, 114, 101, ++ 108, 110, 97, 98, 121, 112, 97, 37, 100, 61, 37, 100, 0, 98, 111, 97, ++ 114, 100, 114, 101, 118, 61, 48, 120, 37, 120, 0, 114, 97, 119, 116, ++ 101, 109, 112, 115, 101, 110, 115, 101, 61, 48, 120, 37, 120, 0, 117, ++ 115, 98, 115, 115, 112, 104, 121, 95, 117, 116, 109, 105, 95, 99, 116, ++ 108, 48, 61, 48, 120, 37, 120, 0, 117, 115, 98, 115, 115, 112, 104, ++ 121, 95, 117, 116, 109, 105, 95, 99, 116, 108, 49, 61, 48, 120, 37, ++ 120, 0, 117, 115, 98, 115, 115, 112, 104, 121, 95, 117, 116, 109, 105, ++ 95, 99, 116, 108, 50, 61, 48, 120, 37, 120, 0, 0, 0, 0, 0, 0, 111, 102, ++ 100, 109, 53, 103, 108, 112, 111, 61, 48, 120, 37, 120, 0, 112, 97, ++ 48, 105, 116, 115, 115, 105, 116, 61, 37, 100, 0, 116, 115, 115, 105, ++ 112, 111, 115, 53, 103, 61, 48, 120, 37, 120, 0, 114, 120, 112, 111, ++ 50, 103, 61, 37, 100, 0, 116, 115, 115, 105, 112, 111, 115, 115, 108, ++ 111, 112, 101, 37, 100, 103, 61, 37, 100, 0, 116, 114, 105, 53, 103, ++ 104, 61, 37, 100, 0, 109, 97, 110, 102, 61, 37, 115, 0, 116, 114, 105, ++ 53, 103, 108, 61, 37, 100, 0, 109, 99, 115, 98, 119, 50, 48, 53, 103, ++ 104, 112, 111, 61, 48, 120, 37, 120, 0, 0, 0, 109, 99, 115, 98, 119, ++ 50, 48, 117, 108, 53, 103, 104, 112, 111, 61, 48, 120, 37, 120, 0, 109, ++ 99, 115, 98, 119, 52, 48, 53, 103, 104, 112, 111, 61, 48, 120, 37, 120, ++ 0, 0, 0, 115, 114, 111, 109, 114, 101, 118, 61, 37, 100, 0, 108, 101, ++ 103, 111, 102, 100, 109, 52, 48, 100, 117, 112, 112, 111, 61, 48, 120, ++ 37, 120, 0, 109, 97, 120, 112, 53, 103, 104, 97, 49, 61, 48, 120, 37, ++ 120, 0, 100, 101, 118, 105, 100, 61, 48, 120, 37, 120, 0, 114, 120, ++ 103, 97, 105, 110, 115, 37, 100, 103, 116, 114, 105, 115, 111, 97, 37, ++ 100, 61, 37, 100, 0, 109, 97, 120, 112, 53, 103, 108, 97, 48, 61, 48, ++ 120, 37, 120, 0, 109, 97, 120, 112, 53, 103, 108, 97, 49, 61, 48, 120, ++ 37, 120, 0, 101, 112, 97, 103, 97, 105, 110, 37, 100, 103, 61, 37, 100, ++ 0, 119, 112, 115, 103, 112, 105, 111, 61, 37, 100, 0, 119, 111, 119, ++ 108, 95, 103, 112, 105, 111, 61, 37, 100, 0, 114, 115, 115, 105, 115, ++ 109, 102, 53, 103, 61, 37, 100, 0, 116, 114, 105, 115, 111, 50, 103, ++ 61, 48, 120, 37, 120, 0, 116, 115, 115, 105, 112, 111, 115, 50, 103, ++ 61, 48, 120, 37, 120, 0, 119, 112, 115, 108, 101, 100, 61, 37, 100, ++ 0, 101, 108, 110, 97, 53, 103, 61, 48, 120, 37, 120, 0, 112, 97, 53, ++ 103, 98, 119, 52, 48, 56, 48, 97, 37, 100, 61, 48, 120, 37, 120, 44, ++ 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, ++ 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, ++ 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, 120, 44, 48, 120, 37, ++ 120, 44, 48, 120, 37, 120, 0, 109, 99, 115, 98, 119, 50, 48, 53, 103, ++ 109, 112, 111, 61, 48, 120, 37, 120, 0, 0, 0, 109, 99, 115, 98, 119, ++ 50, 48, 117, 108, 53, 103, 109, 112, 111, 61, 48, 120, 37, 120, 0, 109, ++ 99, 115, 98, 119, 52, 48, 53, 103, 109, 112, 111, 61, 48, 120, 37, 120, ++ 0, 0, 0, 99, 99, 111, 100, 101, 61, 37, 99, 37, 99, 0, 109, 99, 115, ++ 98, 119, 49, 54, 48, 53, 103, 37, 99, 112, 111, 61, 48, 120, 37, 120, ++ 0, 73, 110, 118, 97, 108, 105, 100, 47, 85, 110, 115, 117, 112, 112, ++ 111, 114, 116, 101, 100, 32, 120, 116, 97, 108, 32, 118, 97, 108, 117, ++ 101, 32, 37, 100, 0, 114, 109, 105, 110, 0, 99, 108, 100, 111, 95, 98, ++ 117, 114, 115, 116, 0, 112, 108, 108, 37, 100, 0, 108, 110, 108, 100, ++ 111, 49, 0, 114, 37, 100, 100, 0, 114, 37, 100, 116, 0, 120, 116, 97, ++ 108, 102, 114, 101, 113, 0, 0, 0, 0, 12, 0, 0, 0, 2, 0, 22, 0, 2, 0, ++ 0, 0, 4, 0, 13, 0, 7, 0, 0, 0, 1, 0, 10, 0, 8, 0, 0, 0, 4, 0, 13, 0, ++ 10, 0, 0, 0, 4, 0, 13, 0, 13, 0, 0, 0, 1, 0, 7, 0, 23, 0, 0, 0, 4, 0, ++ 4, 0, 27, 0, 0, 0, 4, 0, 1, 0, 28, 0, 0, 0, 1, 0, 7, 0, 0, 0, 0, 0, ++ 2, 0, 2, 0, 1, 0, 0, 0, 1, 0, 1, 0, 3, 0, 0, 0, 2, 0, 2, 0, 4, 0, 0, ++ 0, 1, 0, 1, 0, 5, 0, 0, 0, 1, 0, 1, 0, 6, 0, 0, 0, 1, 0, 1, 0, 9, 0, ++ 0, 0, 1, 0, 5, 0, 11, 0, 0, 0, 1, 0, 1, 0, 12, 0, 0, 0, 2, 0, 48, 0, ++ 14, 0, 0, 0, 1, 0, 1, 0, 15, 0, 0, 0, 1, 0, 1, 0, 16, 0, 0, 0, 1, 0, ++ 1, 0, 17, 0, 0, 0, 1, 0, 1, 0, 18, 0, 0, 0, 3, 0, 3, 0, 19, 0, 0, 0, ++ 1, 0, 1, 0, 20, 0, 0, 0, 1, 0, 1, 0, 21, 0, 0, 0, 1, 0, 1, 0, 22, 0, ++ 0, 0, 1, 0, 1, 0, 24, 0, 0, 0, 2, 0, 19, 0, 25, 0, 0, 0, 2, 0, 19, 0, ++ 26, 0, 0, 0, 2, 0, 19, 0, 29, 0, 0, 0, 1, 0, 1, 0, 30, 0, 0, 0, 1, 0, ++ 1, 0, 12, 0, 0, 0, 2, 0, 48, 0, 114, 109, 97, 120, 0, 0, 0, 75, 0, 7, ++ 144, 101, 0, 12, 24, 146, 0, 15, 108, 112, 108, 100, 111, 49, 0, 0, ++ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, ++ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, ++ 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, ++ 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 0, 0, 87, ++ 17, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 23, 1, 0, 0, 0, 0, 0, ++ 0, 128, 0, 0, 0, 0, 0, 0, 0, 87, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, ++ 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, ++ 0, 0, 0, 0, 0, 7, 4, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 87, ++ 1, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 0, 215, 21, 0, 0, 0, 0, 0, ++ 0, 0, 64, 0, 0, 0, 0, 0, 0, 247, 189, 194, 14, 0, 0, 0, 0, 0, 128, 0, ++ 0, 0, 0, 0, 0, 247, 61, 194, 14, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 247, 61, 192, 14, 0, ++ 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 247, 61, 194, 14, 0, 0, 0, 0, 0, 0, ++ 8, 0, 0, 0, 0, 0, 247, 61, 194, 14, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, ++ 0, 247, 61, 192, 6, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 247, 61, 218, ++ 14, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 247, 61, 0, 6, 0, 0, 0, 0, ++ 0, 0, 128, 0, 0, 0, 0, 0, 247, 61, 64, 6, 0, 0, 0, 0, 0, 0, 0, 1, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 215, 1, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 215, 13, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 8, 0, 0, 0, 0, 247, 61, 192, 6, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, ++ 0, 0, 247, 61, 202, 14, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 247, 61, ++ 202, 30, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 247, 61, 250, 62, 0, 0, ++ 0, 0, 114, 101, 103, 37, 100, 0, 99, 108, 100, 111, 95, 112, 119, 109, ++ 0, 99, 104, 105, 112, 99, 37, 100, 0, 98, 111, 97, 114, 100, 116, 121, ++ 112, 101, 0, 112, 114, 111, 100, 105, 100, 0, 115, 119, 100, 101, 110, ++ 97, 98, 108, 101, 0, 103, 112, 100, 110, 0, 98, 111, 97, 114, 100, 102, ++ 108, 97, 103, 115, 0, 98, 116, 99, 120, 119, 97, 114, 102, 108, 97, ++ 103, 115, 0, 120, 116, 97, 108, 102, 114, 101, 113, 0, 100, 101, 118, ++ 105, 100, 0, 98, 111, 97, 114, 100, 114, 101, 118, 0, 0, 128, 186, 140, ++ 1, 0, 194, 1, 0, 242, 0, 0, 0, 129, 0, 0, 0, 16, 0, 0, 0, 192, 173, ++ 58, 2, 0, 194, 1, 0, 236, 0, 0, 0, 129, 0, 0, 0, 34, 0, 0, 0, 109, 117, ++ 120, 101, 110, 97, 98, 0, 119, 108, 48, 105, 100, 0, 119, 108, 37, 100, ++ 58, 32, 66, 114, 111, 97, 100, 99, 111, 109, 32, 66, 67, 77, 37, 115, ++ 32, 56, 48, 50, 46, 49, 49, 32, 87, 105, 114, 101, 108, 101, 115, 115, ++ 32, 67, 111, 110, 116, 114, 111, 108, 108, 101, 114, 32, 37, 115, 10, ++ 0, 97, 103, 98, 103, 48, 0, 97, 103, 98, 103, 49, 0, 97, 103, 98, 103, ++ 50, 0, 97, 97, 48, 0, 115, 97, 114, 50, 103, 0, 78, 86, 82, 65, 77, ++ 82, 101, 118, 0, 0, 97, 39, 1, 0, 25, 213, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 32, 67, 37, 67, 3, 67, 33, 67, 36, 67, 24, 67, 25, 67, 26, 67, 17, ++ 67, 19, 67, 18, 67, 20, 67, 21, 67, 22, 67, 27, 67, 28, 67, 29, 67, ++ 40, 67, 41, 67, 42, 67, 43, 67, 44, 67, 45, 67, 65, 67, 64, 67, 80, ++ 67, 81, 67, 82, 67, 83, 67, 87, 67, 157, 169, 118, 5, 84, 67, 95, 67, ++ 63, 67, 79, 67, 47, 67, 52, 67, 53, 67, 54, 67, 55, 67, 56, 67, 57, ++ 67, 22, 71, 72, 71, 39, 71, 67, 67, 96, 67, 70, 67, 71, 67, 72, 67, ++ 49, 67, 50, 67, 51, 67, 170, 67, 88, 67, 89, 67, 90, 67, 169, 67, 85, ++ 67, 86, 67, 99, 67, 128, 67, 129, 67, 130, 67, 100, 67, 101, 67, 102, ++ 67, 116, 67, 103, 67, 160, 67, 161, 67, 162, 67, 174, 67, 175, 67, 176, ++ 67, 171, 67, 172, 67, 173, 67, 227, 67, 228, 67, 229, 67, 226, 67, 208, ++ 67, 209, 67, 210, 67, 186, 67, 187, 67, 188, 67, 177, 67, 178, 67, 179, ++ 67, 163, 67, 164, 67, 165, 67, 183, 67, 184, 67, 185, 67, 192, 67, 193, ++ 67, 194, 67, 211, 67, 212, 67, 213, 67, 214, 67, 215, 67, 216, 67, 217, ++ 67, 218, 67, 219, 67, 223, 67, 224, 67, 225, 67, 236, 67, 237, 67, 238, ++ 67, 233, 67, 234, 67, 235, 67, 34, 67, 214, 168, 103, 168, 104, 168, ++ 156, 169, 216, 168, 157, 169, 19, 67, 20, 67, 134, 168, 49, 67, 167, ++ 169, 219, 168, 209, 168, 220, 168, 164, 169, 82, 170, 198, 169, 2, 170, ++ 49, 170, 50, 170, 100, 101, 118, 105, 100, 0, 97, 97, 50, 103, 0, 49, ++ 49, 110, 95, 100, 105, 115, 97, 98, 108, 101, 0, 97, 103, 48, 0, 97, ++ 107, 109, 0, 0, 37, 194, 1, 0, 243, 164, 1, 0, 43, 214, 1, 0, 0, 0, ++ 0, 0, 101, 15, 2, 0, 209, 171, 131, 0, 0, 0, 0, 0, 0, 0, 0, 0, 98, 116, ++ 99, 120, 108, 101, 115, 99, 97, 110, 0, 119, 108, 37, 100, 58, 100, ++ 109, 97, 37, 100, 0, 97, 97, 50, 103, 0, 98, 116, 99, 95, 109, 111, ++ 100, 101, 0, 98, 111, 97, 114, 100, 102, 108, 97, 103, 115, 0, 109, ++ 97, 99, 97, 100, 100, 114, 0, 118, 101, 110, 100, 105, 100, 0, 99, 117, ++ 115, 116, 111, 109, 118, 97, 114, 49, 0, 99, 117, 115, 116, 111, 109, ++ 118, 97, 114, 50, 0, 98, 116, 99, 95, 112, 97, 114, 97, 109, 115, 37, ++ 100, 0, 97, 110, 116, 115, 119, 99, 116, 108, 50, 103, 0, 98, 116, 99, ++ 120, 119, 97, 114, 102, 108, 97, 103, 115, 0, 98, 116, 99, 95, 102, ++ 108, 97, 103, 115, 0, 98, 111, 97, 114, 100, 102, 108, 97, 103, 115, ++ 50, 0, 98, 111, 97, 114, 100, 102, 108, 97, 103, 115, 52, 0, 98, 111, ++ 97, 114, 100, 114, 101, 118, 0, 100, 101, 118, 105, 100, 0, 115, 114, ++ 111, 109, 114, 101, 118, 0, 97, 110, 116, 115, 119, 99, 116, 108, 53, ++ 103, 0, 115, 99, 111, 95, 114, 115, 115, 105, 95, 116, 104, 114, 101, ++ 115, 104, 0, 112, 114, 111, 116, 95, 98, 116, 114, 115, 115, 105, 95, ++ 116, 104, 114, 101, 115, 104, 0, 99, 99, 111, 100, 101, 0, 99, 99, 0, ++ 114, 101, 103, 114, 101, 118, 0, 101, 118, 101, 110, 116, 113, 0, 104, ++ 115, 50, 48, 0, 41, 6, 134, 0, 105, 6, 134, 0, 65, 243, 133, 0, 145, ++ 243, 133, 0, 41, 6, 134, 0, 105, 6, 134, 0, 65, 243, 133, 0, 145, 243, ++ 133, 0, 41, 6, 134, 0, 105, 6, 134, 0, 13, 244, 133, 0, 121, 245, 133, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 244, 133, 0, ++ 121, 245, 133, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 6, 134, 0, 105, 6, 134, ++ 0, 41, 6, 134, 0, 105, 6, 134, 0, 41, 6, 134, 0, 105, 6, 134, 0, 0, ++ 0, 0, 0, 13, 6, 15, 0, 0, 0, 0, 0, 4, 6, 48, 4, 0, 0, 0, 0, 2, 6, 64, ++ 6, 114, 115, 115, 105, 99, 111, 114, 114, 110, 111, 114, 109, 0, 103, ++ 108, 97, 99, 105, 97, 108, 116, 105, 109, 101, 114, 0, 108, 100, 112, ++ 99, 0, 116, 115, 115, 105, 108, 105, 109, 117, 99, 111, 100, 0, 37, ++ 115, 46, 102, 97, 98, 46, 37, 100, 0, 116, 101, 109, 112, 116, 104, ++ 114, 101, 115, 104, 0, 46, 102, 97, 98, 46, 0, 116, 120, 112, 119, 114, ++ 98, 99, 107, 111, 102, 0, 105, 110, 116, 101, 114, 102, 101, 114, 101, ++ 110, 99, 101, 0, 103, 108, 105, 116, 99, 104, 95, 98, 97, 115, 101, ++ 100, 95, 99, 114, 115, 109, 105, 110, 0, 50, 103, 95, 99, 103, 97, 0, ++ 114, 115, 115, 105, 99, 111, 114, 114, 97, 116, 116, 101, 110, 0, 112, ++ 104, 121, 99, 97, 108, 95, 116, 101, 109, 112, 100, 101, 108, 116, 97, ++ 0, 116, 101, 109, 112, 115, 95, 104, 121, 115, 116, 101, 114, 101, 115, ++ 105, 115, 0, 114, 115, 115, 105, 99, 111, 114, 114, 112, 101, 114, 114, ++ 103, 50, 103, 0, 116, 115, 115, 105, 102, 108, 111, 111, 114, 50, 103, ++ 0, 118, 98, 97, 116, 95, 97, 100, 100, 0, 112, 97, 112, 100, 118, 97, ++ 108, 105, 100, 116, 101, 115, 116, 0, 115, 119, 100, 105, 118, 95, 103, ++ 112, 105, 111, 95, 49, 0, 112, 109, 105, 110, 0, 115, 112, 117, 114, ++ 99, 111, 110, 102, 105, 103, 0, 99, 99, 107, 100, 105, 103, 102, 105, ++ 108, 116, 116, 121, 112, 101, 0, 101, 117, 95, 101, 100, 116, 104, 114, ++ 101, 115, 104, 50, 103, 0, 114, 101, 100, 95, 114, 120, 98, 108, 111, ++ 99, 107, 105, 110, 103, 0, 0, 1, 0, 108, 9, 75, 0, 118, 1, 19, 0, 50, ++ 48, 22, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 37, 0, 0, 0, 145, ++ 9, 0, 0, 108, 9, 0, 0, 0, 0, 5, 3, 91, 231, 8, 0, 63, 88, 18, 18, 47, ++ 20, 31, 31, 31, 31, 32, 81, 39, 97, 0, 0, 9, 96, 63, 112, 2, 0, 113, ++ 9, 75, 0, 118, 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, 126, 0, 6, 0, 10, ++ 217, 3, 39, 0, 37, 0, 0, 0, 145, 9, 0, 0, 113, 9, 0, 0, 0, 0, 7, 3, ++ 13, 130, 8, 0, 63, 88, 18, 18, 47, 20, 31, 31, 31, 31, 32, 81, 39, 97, ++ 0, 0, 9, 96, 63, 112, 3, 0, 118, 9, 75, 0, 118, 1, 19, 0, 50, 48, 22, ++ 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 37, 0, 0, 0, 145, 9, 0, ++ 0, 118, 9, 0, 0, 0, 0, 9, 3, 191, 28, 8, 0, 63, 88, 18, 18, 47, 20, ++ 31, 31, 31, 31, 32, 81, 39, 97, 0, 0, 9, 96, 63, 112, 4, 0, 123, 9, ++ 75, 0, 118, 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, ++ 3, 39, 0, 37, 0, 0, 0, 145, 9, 0, 0, 123, 9, 0, 0, 0, 0, 10, 3, 113, ++ 183, 8, 0, 63, 88, 18, 18, 47, 20, 31, 31, 31, 31, 32, 81, 39, 97, 0, ++ 0, 9, 96, 63, 112, 5, 0, 128, 9, 75, 0, 118, 1, 19, 0, 50, 48, 22, 0, ++ 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 37, 0, 0, 0, 145, 9, 0, 0, ++ 128, 9, 0, 0, 0, 0, 12, 3, 35, 82, 8, 0, 63, 88, 18, 18, 47, 20, 31, ++ 31, 31, 31, 33, 81, 39, 97, 0, 0, 9, 96, 63, 112, 6, 0, 133, 9, 75, ++ 0, 118, 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, ++ 39, 0, 37, 0, 0, 0, 145, 9, 0, 0, 133, 9, 0, 0, 0, 0, 13, 3, 213, 236, ++ 8, 0, 63, 88, 18, 18, 47, 20, 31, 31, 31, 31, 33, 81, 39, 97, 0, 0, ++ 9, 96, 63, 112, 7, 0, 138, 9, 75, 0, 118, 1, 19, 0, 50, 48, 22, 0, 3, ++ 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 37, 0, 0, 0, 145, 9, 0, 0, 138, ++ 9, 0, 0, 0, 0, 15, 3, 135, 135, 8, 0, 63, 88, 18, 18, 47, 20, 31, 31, ++ 31, 31, 33, 81, 39, 97, 0, 0, 8, 96, 63, 112, 8, 0, 143, 9, 75, 0, 118, ++ 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, ++ 37, 0, 0, 0, 145, 9, 0, 0, 143, 9, 0, 0, 0, 0, 17, 3, 57, 34, 8, 0, ++ 63, 88, 18, 18, 47, 20, 31, 31, 31, 31, 33, 81, 39, 97, 0, 0, 8, 96, ++ 63, 112, 9, 0, 148, 9, 75, 0, 118, 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, ++ 126, 0, 6, 0, 10, 217, 3, 39, 0, 37, 0, 0, 0, 145, 9, 0, 0, 148, 9, ++ 0, 0, 0, 0, 18, 3, 235, 188, 8, 0, 63, 88, 18, 18, 47, 20, 31, 31, 31, ++ 31, 33, 81, 39, 97, 0, 0, 8, 96, 63, 96, 10, 0, 153, 9, 75, 0, 118, ++ 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, ++ 37, 0, 0, 0, 145, 9, 0, 0, 153, 9, 0, 0, 0, 0, 20, 3, 157, 87, 8, 0, ++ 63, 88, 18, 18, 47, 20, 31, 31, 31, 31, 33, 81, 39, 97, 0, 0, 8, 96, ++ 63, 96, 11, 0, 158, 9, 75, 0, 118, 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, ++ 126, 0, 6, 0, 10, 217, 3, 39, 0, 37, 0, 0, 0, 145, 9, 0, 0, 158, 9, ++ 0, 0, 0, 0, 21, 3, 79, 242, 8, 0, 63, 88, 18, 18, 47, 20, 31, 31, 31, ++ 31, 33, 81, 39, 97, 0, 0, 7, 96, 63, 96, 12, 0, 163, 9, 75, 0, 118, ++ 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, ++ 37, 0, 0, 0, 145, 9, 0, 0, 163, 9, 0, 0, 0, 0, 23, 3, 1, 141, 8, 0, ++ 63, 88, 18, 18, 47, 20, 31, 31, 31, 31, 33, 81, 39, 97, 0, 0, 7, 96, ++ 63, 96, 13, 0, 168, 9, 75, 0, 118, 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, ++ 126, 0, 6, 0, 10, 217, 3, 39, 0, 37, 0, 0, 0, 145, 9, 0, 0, 168, 9, ++ 0, 0, 0, 0, 25, 3, 179, 39, 8, 0, 63, 88, 18, 18, 47, 20, 31, 31, 31, ++ 31, 33, 81, 40, 97, 0, 0, 7, 96, 63, 96, 14, 0, 180, 9, 75, 0, 118, ++ 1, 19, 0, 50, 48, 22, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, ++ 37, 0, 0, 0, 145, 9, 0, 0, 180, 9, 0, 0, 0, 0, 29, 3, 94, 1, 8, 0, 63, ++ 88, 18, 18, 47, 20, 31, 31, 31, 31, 33, 81, 40, 97, 0, 0, 7, 96, 63, ++ 96, 109, 97, 120, 112, 50, 103, 97, 48, 0, 0, 1, 0, 108, 9, 52, 0, 4, ++ 1, 13, 0, 35, 48, 79, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, ++ 26, 0, 0, 0, 162, 9, 0, 0, 108, 9, 0, 0, 0, 0, 178, 8, 39, 118, 8, 0, ++ 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 59, 81, 25, 97, 0, 0, 9, 96, ++ 63, 112, 2, 0, 113, 9, 52, 0, 4, 1, 13, 0, 35, 48, 79, 0, 3, 0, 65, ++ 126, 0, 6, 0, 10, 217, 3, 39, 0, 26, 0, 0, 0, 162, 9, 0, 0, 113, 9, ++ 0, 0, 0, 0, 183, 8, 177, 19, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, ++ 31, 59, 81, 25, 97, 0, 0, 9, 96, 63, 112, 3, 0, 118, 9, 52, 0, 4, 1, ++ 13, 0, 35, 48, 79, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 26, ++ 0, 0, 0, 162, 9, 0, 0, 118, 9, 0, 0, 0, 0, 187, 8, 59, 177, 8, 0, 63, ++ 88, 23, 23, 60, 25, 31, 31, 31, 31, 60, 81, 25, 97, 0, 0, 9, 96, 63, ++ 112, 4, 0, 123, 9, 52, 0, 4, 1, 13, 0, 35, 48, 79, 0, 3, 0, 65, 126, ++ 0, 6, 0, 10, 217, 3, 39, 0, 26, 0, 0, 0, 162, 9, 0, 0, 123, 9, 0, 0, ++ 0, 0, 192, 8, 196, 78, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, ++ 60, 81, 25, 97, 0, 0, 9, 96, 63, 112, 5, 0, 128, 9, 52, 0, 4, 1, 13, ++ 0, 35, 48, 79, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 26, 0, ++ 0, 0, 162, 9, 0, 0, 128, 9, 0, 0, 0, 0, 196, 8, 78, 236, 8, 0, 63, 88, ++ 23, 23, 60, 25, 31, 31, 31, 31, 60, 81, 25, 97, 0, 0, 9, 96, 63, 112, ++ 6, 0, 133, 9, 52, 0, 4, 1, 13, 0, 35, 48, 79, 0, 3, 0, 65, 126, 0, 6, ++ 0, 10, 217, 3, 39, 0, 26, 0, 0, 0, 162, 9, 0, 0, 133, 9, 0, 0, 0, 0, ++ 201, 8, 216, 137, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 60, ++ 81, 25, 97, 0, 0, 9, 96, 63, 112, 7, 0, 138, 9, 52, 0, 4, 1, 13, 0, ++ 35, 48, 79, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 26, 0, 0, ++ 0, 162, 9, 0, 0, 138, 9, 0, 0, 0, 0, 206, 8, 98, 39, 8, 0, 63, 88, 23, ++ 23, 60, 25, 31, 31, 31, 31, 60, 81, 25, 97, 0, 0, 8, 96, 63, 112, 8, ++ 0, 143, 9, 52, 0, 4, 1, 13, 0, 35, 48, 79, 0, 3, 0, 65, 126, 0, 6, 0, ++ 10, 217, 3, 39, 0, 26, 0, 0, 0, 162, 9, 0, 0, 143, 9, 0, 0, 0, 0, 210, ++ 8, 236, 196, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 60, 81, 25, ++ 97, 0, 0, 8, 96, 63, 112, 9, 0, 148, 9, 52, 0, 4, 1, 13, 0, 35, 48, ++ 79, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 26, 0, 0, 0, 162, ++ 9, 0, 0, 148, 9, 0, 0, 0, 0, 215, 8, 118, 98, 8, 0, 63, 88, 23, 23, ++ 60, 25, 31, 31, 31, 31, 60, 81, 25, 97, 0, 0, 8, 96, 63, 96, 10, 0, ++ 153, 9, 52, 0, 4, 1, 13, 0, 35, 48, 79, 0, 3, 0, 65, 126, 0, 6, 0, 10, ++ 217, 3, 39, 0, 26, 0, 0, 0, 162, 9, 0, 0, 153, 9, 0, 0, 0, 0, 220, 8, ++ 0, 0, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 60, 81, 25, 97, ++ 0, 0, 8, 96, 63, 96, 11, 0, 158, 9, 52, 0, 4, 1, 13, 0, 35, 48, 79, ++ 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 26, 0, 0, 0, 162, 9, 0, ++ 0, 158, 9, 0, 0, 0, 0, 224, 8, 137, 157, 8, 0, 63, 88, 23, 23, 60, 25, ++ 31, 31, 31, 31, 61, 81, 25, 97, 0, 0, 7, 96, 63, 96, 12, 0, 163, 9, ++ 52, 0, 4, 1, 13, 0, 35, 48, 79, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, ++ 3, 39, 0, 26, 0, 0, 0, 162, 9, 0, 0, 163, 9, 0, 0, 0, 0, 229, 8, 19, ++ 59, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 61, 81, 25, 97, 0, ++ 0, 7, 96, 63, 96, 13, 0, 168, 9, 52, 0, 4, 1, 13, 0, 35, 48, 79, 0, ++ 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 26, 0, 0, 0, 162, 9, 0, 0, ++ 168, 9, 0, 0, 0, 0, 233, 8, 157, 216, 8, 0, 63, 88, 23, 23, 60, 25, ++ 31, 31, 31, 31, 61, 81, 25, 97, 0, 0, 7, 96, 63, 96, 14, 0, 180, 9, ++ 52, 0, 4, 1, 13, 0, 35, 48, 79, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, ++ 3, 39, 0, 26, 0, 0, 0, 162, 9, 0, 0, 180, 9, 0, 0, 0, 0, 244, 8, 78, ++ 236, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 61, 81, 25, 97, 0, ++ 0, 7, 96, 63, 96, 112, 114, 111, 112, 98, 119, 50, 48, 50, 103, 112, ++ 111, 0, 114, 99, 111, 114, 95, 97, 99, 105, 0, 112, 97, 112, 100, 109, ++ 111, 100, 101, 0, 99, 97, 108, 105, 100, 120, 101, 115, 116, 116, 97, ++ 114, 103, 101, 116, 50, 103, 0, 99, 97, 108, 105, 100, 120, 101, 115, ++ 116, 98, 97, 115, 101, 50, 103, 0, 112, 97, 50, 103, 97, 48, 95, 108, ++ 111, 0, 99, 99, 107, 50, 103, 112, 111, 0, 99, 99, 107, 115, 99, 97, ++ 108, 101, 0, 116, 101, 109, 112, 95, 109, 117, 108, 116, 0, 112, 97, ++ 112, 100, 101, 112, 115, 111, 102, 102, 115, 101, 116, 0, 109, 99, 115, ++ 50, 103, 112, 111, 48, 0, 112, 97, 99, 97, 108, 105, 100, 120, 50, 103, ++ 0, 111, 102, 100, 109, 50, 103, 112, 111, 0, 111, 102, 100, 109, 100, ++ 105, 103, 102, 105, 108, 116, 116, 121, 112, 101, 98, 101, 0, 65, 118, ++ 86, 109, 105, 100, 73, 81, 99, 97, 108, 0, 99, 99, 107, 105, 100, 120, ++ 112, 99, 104, 111, 102, 102, 115, 0, 115, 119, 100, 105, 118, 95, 103, ++ 112, 105, 111, 0, 109, 99, 115, 98, 119, 50, 48, 50, 103, 112, 111, ++ 0, 112, 97, 112, 100, 101, 110, 100, 105, 100, 120, 0, 113, 97, 109, ++ 50, 53, 54, 101, 110, 0, 115, 119, 100, 105, 118, 95, 115, 119, 99, ++ 116, 114, 108, 95, 101, 110, 0, 116, 101, 109, 112, 95, 97, 100, 100, ++ 0, 105, 116, 115, 115, 105, 99, 111, 114, 114, 0, 115, 119, 100, 105, ++ 118, 95, 101, 110, 0, 101, 100, 111, 102, 102, 116, 104, 100, 50, 48, ++ 117, 108, 0, 105, 110, 105, 116, 120, 105, 100, 120, 112, 99, 104, 0, ++ 100, 115, 115, 102, 116, 104, 0, 116, 115, 115, 105, 116, 105, 109, ++ 101, 0, 99, 99, 107, 98, 119, 50, 48, 50, 103, 112, 111, 0, 0, 1, 0, ++ 108, 9, 38, 0, 192, 0, 10, 0, 26, 48, 128, 0, 3, 0, 65, 126, 0, 6, 0, ++ 10, 217, 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, 0, 108, 9, 0, 0, 0, 0, 199, ++ 11, 0, 0, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 80, 81, 25, ++ 97, 0, 0, 9, 96, 63, 112, 2, 0, 113, 9, 38, 0, 192, 0, 10, 0, 26, 48, ++ 128, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 19, 0, 0, 0, 176, ++ 9, 0, 0, 113, 9, 0, 0, 0, 0, 205, 11, 0, 64, 8, 0, 63, 88, 23, 23, 60, ++ 25, 31, 31, 31, 31, 81, 81, 25, 97, 0, 0, 9, 96, 63, 112, 3, 0, 118, ++ 9, 38, 0, 192, 0, 10, 0, 26, 48, 128, 0, 3, 0, 65, 126, 0, 6, 0, 10, ++ 217, 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, 0, 118, 9, 0, 0, 0, 0, 211, 11, ++ 0, 128, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 81, 81, 25, 97, ++ 0, 0, 9, 96, 63, 112, 4, 0, 123, 9, 38, 0, 192, 0, 10, 0, 26, 48, 128, ++ 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, ++ 0, 123, 9, 0, 0, 0, 0, 217, 11, 0, 192, 8, 0, 63, 88, 23, 23, 60, 25, ++ 31, 31, 31, 31, 81, 81, 25, 97, 0, 0, 9, 96, 63, 112, 5, 0, 128, 9, ++ 38, 0, 192, 0, 10, 0, 26, 48, 128, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, ++ 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, 0, 128, 9, 0, 0, 0, 0, 224, 11, 0, ++ 0, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 81, 81, 25, 97, 0, ++ 0, 9, 96, 63, 112, 6, 0, 133, 9, 38, 0, 192, 0, 10, 0, 26, 48, 128, ++ 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, ++ 0, 133, 9, 0, 0, 0, 0, 230, 11, 0, 64, 8, 0, 63, 88, 23, 23, 60, 25, ++ 31, 31, 31, 31, 81, 81, 25, 97, 0, 0, 9, 96, 63, 112, 7, 0, 138, 9, ++ 38, 0, 192, 0, 10, 0, 26, 48, 128, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, ++ 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, 0, 138, 9, 0, 0, 0, 0, 236, 11, 0, ++ 128, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 81, 81, 25, 97, 0, ++ 0, 8, 96, 63, 112, 8, 0, 143, 9, 38, 0, 192, 0, 10, 0, 26, 48, 128, ++ 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, ++ 0, 143, 9, 0, 0, 0, 0, 242, 11, 0, 192, 8, 0, 63, 88, 23, 23, 60, 25, ++ 31, 31, 31, 31, 82, 81, 25, 97, 0, 0, 8, 96, 63, 112, 9, 0, 148, 9, ++ 38, 0, 192, 0, 10, 0, 26, 48, 128, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, ++ 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, 0, 148, 9, 0, 0, 0, 0, 249, 11, 0, ++ 0, 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 82, 81, 25, 97, 0, ++ 0, 8, 96, 63, 96, 10, 0, 153, 9, 38, 0, 192, 0, 10, 0, 26, 48, 128, ++ 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, ++ 0, 153, 9, 0, 0, 0, 0, 255, 11, 0, 64, 8, 0, 63, 88, 23, 23, 60, 25, ++ 31, 31, 31, 31, 82, 81, 25, 97, 0, 0, 8, 96, 63, 96, 11, 0, 158, 9, ++ 38, 0, 192, 0, 10, 0, 26, 48, 128, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, ++ 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, 0, 158, 9, 0, 0, 0, 0, 5, 12, 0, 128, ++ 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 82, 81, 25, 97, 0, 0, ++ 7, 96, 63, 96, 12, 0, 163, 9, 38, 0, 192, 0, 10, 0, 26, 48, 128, 0, ++ 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, 0, ++ 163, 9, 0, 0, 0, 0, 11, 12, 0, 192, 8, 0, 63, 88, 23, 23, 60, 25, 31, ++ 31, 31, 31, 82, 81, 25, 97, 0, 0, 7, 96, 63, 96, 13, 0, 168, 9, 38, ++ 0, 192, 0, 10, 0, 26, 48, 128, 0, 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, ++ 39, 0, 19, 0, 0, 0, 176, 9, 0, 0, 168, 9, 0, 0, 0, 0, 18, 12, 0, 0, ++ 8, 0, 63, 88, 23, 23, 60, 25, 31, 31, 31, 31, 82, 81, 25, 97, 0, 0, ++ 7, 96, 63, 96, 14, 0, 180, 9, 38, 0, 192, 0, 10, 0, 26, 48, 128, 0, ++ 3, 0, 65, 126, 0, 6, 0, 10, 217, 3, 39, 0, 19, 0, 0, 0, 176, 9, 0, 0, ++ 180, 9, 0, 0, 0, 0, 33, 12, 0, 0, 8, 0, 63, 88, 23, 23, 60, 25, 31, ++ 31, 31, 31, 83, 81, 25, 97, 0, 0, 7, 96, 63, 96, 112, 97, 50, 103, 97, ++ 48, 95, 50, 112, 119, 114, 0, 105, 110, 105, 116, 120, 105, 100, 120, ++ 0, 99, 99, 107, 112, 119, 114, 111, 102, 102, 115, 101, 116, 48, 0, ++ 116, 101, 109, 112, 95, 113, 0, 109, 99, 115, 50, 103, 112, 111, 49, ++ 0, 118, 98, 97, 116, 95, 109, 117, 108, 116, 0, 99, 99, 107, 105, 110, ++ 105, 116, 120, 105, 100, 120, 0, 65, 118, 86, 109, 105, 100, 95, 99, ++ 48, 0, 115, 114, 111, 109, 114, 101, 118, 0, 111, 102, 100, 109, 100, ++ 105, 103, 102, 105, 108, 116, 116, 121, 112, 101, 0, 101, 100, 111, ++ 110, 116, 104, 100, 50, 48, 108, 0, 108, 101, 103, 111, 102, 100, 109, ++ 98, 119, 50, 48, 50, 103, 112, 111, 0, 112, 97, 50, 103, 97, 48, 0, ++ 116, 120, 112, 119, 114, 111, 102, 102, 115, 101, 116, 50, 103, 0, 112, ++ 109, 97, 120, 0, 118, 98, 97, 116, 95, 113, 0, 6, 7, 63, 3, 138, 0, ++ 0, 0, 6, 7, 63, 3, 132, 0, 0, 0, 6, 7, 63, 3, 128, 0, 0, 0, 6, 7, 63, ++ 3, 123, 0, 0, 0, 6, 7, 63, 3, 119, 0, 0, 0, 6, 7, 63, 3, 114, 0, 0, ++ 0, 6, 7, 63, 3, 110, 0, 0, 0, 6, 7, 63, 3, 106, 0, 0, 0, 6, 7, 63, 3, ++ 103, 0, 0, 0, 6, 7, 63, 3, 99, 0, 0, 0, 6, 7, 63, 3, 97, 0, 0, 0, 6, ++ 7, 63, 3, 92, 0, 0, 0, 6, 7, 63, 3, 90, 0, 0, 0, 6, 7, 63, 3, 87, 0, ++ 0, 0, 6, 7, 63, 3, 84, 0, 0, 0, 6, 7, 63, 3, 81, 0, 0, 0, 6, 7, 63, ++ 3, 79, 0, 0, 0, 6, 7, 63, 3, 77, 0, 0, 0, 6, 7, 63, 3, 75, 0, 0, 0, ++ 6, 7, 63, 3, 72, 0, 0, 0, 6, 7, 63, 3, 70, 0, 0, 0, 6, 7, 63, 3, 68, ++ 0, 0, 0, 6, 7, 63, 3, 66, 0, 0, 0, 6, 7, 63, 3, 64, 0, 0, 0, 6, 7, 63, ++ 3, 63, 0, 0, 0, 6, 7, 63, 3, 61, 0, 0, 0, 6, 7, 63, 3, 59, 0, 0, 0, ++ 6, 7, 63, 3, 58, 0, 0, 0, 6, 7, 63, 3, 56, 0, 0, 0, 6, 7, 63, 3, 54, ++ 0, 0, 0, 6, 7, 63, 3, 53, 0, 0, 0, 6, 7, 63, 3, 52, 0, 0, 0, 6, 7, 63, ++ 3, 50, 0, 0, 0, 6, 7, 63, 3, 49, 0, 0, 0, 6, 7, 63, 3, 48, 0, 0, 0, ++ 6, 7, 62, 3, 47, 0, 0, 0, 6, 7, 60, 3, 47, 0, 0, 0, 6, 7, 59, 3, 47, ++ 0, 0, 0, 6, 7, 59, 3, 45, 0, 0, 0, 6, 7, 58, 3, 45, 0, 0, 0, 6, 7, 58, ++ 3, 44, 0, 0, 0, 6, 7, 58, 3, 43, 0, 0, 0, 6, 7, 58, 3, 41, 0, 0, 0, ++ 6, 7, 57, 3, 41, 0, 0, 0, 6, 7, 56, 3, 40, 0, 0, 0, 6, 7, 56, 3, 39, ++ 0, 0, 0, 6, 7, 56, 3, 38, 0, 0, 0, 6, 7, 56, 3, 37, 0, 0, 0, 6, 7, 56, ++ 3, 36, 0, 0, 0, 6, 7, 55, 3, 36, 0, 0, 0, 6, 7, 55, 3, 35, 0, 0, 0, ++ 6, 7, 55, 3, 34, 0, 0, 0, 6, 7, 55, 3, 33, 0, 0, 0, 6, 7, 53, 3, 33, ++ 0, 0, 0, 6, 7, 53, 3, 32, 0, 0, 0, 6, 7, 52, 3, 32, 0, 0, 0, 6, 7, 52, ++ 3, 31, 0, 0, 0, 6, 7, 50, 3, 31, 0, 0, 0, 6, 7, 51, 3, 30, 0, 0, 0, ++ 6, 7, 51, 3, 29, 0, 0, 0, 6, 7, 49, 3, 29, 0, 0, 0, 6, 7, 50, 3, 28, ++ 0, 0, 0, 6, 7, 48, 3, 28, 0, 0, 0, 6, 7, 47, 3, 28, 0, 0, 0, 6, 7, 45, ++ 3, 28, 0, 0, 0, 6, 7, 43, 3, 28, 0, 0, 0, 6, 7, 42, 3, 28, 0, 0, 0, ++ 6, 7, 41, 3, 28, 0, 0, 0, 6, 7, 40, 3, 28, 0, 0, 0, 6, 7, 40, 3, 27, ++ 0, 0, 0, 6, 7, 39, 3, 27, 0, 0, 0, 6, 7, 39, 3, 26, 0, 0, 0, 6, 7, 38, ++ 3, 26, 0, 0, 0, 6, 7, 36, 3, 26, 0, 0, 0, 6, 7, 35, 3, 26, 0, 0, 0, ++ 6, 7, 34, 3, 26, 0, 0, 0, 6, 7, 33, 3, 26, 0, 0, 0, 6, 7, 33, 3, 25, ++ 0, 0, 0, 6, 7, 32, 3, 25, 0, 0, 0, 6, 7, 31, 3, 25, 0, 0, 0, 6, 7, 30, ++ 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, ++ 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, ++ 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, ++ 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, ++ 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, ++ 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, ++ 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, ++ 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, ++ 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, ++ 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, ++ 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, ++ 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, ++ 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, ++ 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, ++ 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, ++ 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, ++ 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, ++ 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 7, 30, 3, 25, 0, 0, 0, 6, 15, ++ 63, 255, 98, 0, 0, 0, 6, 15, 63, 255, 94, 0, 0, 0, 6, 15, 63, 255, 89, ++ 0, 0, 0, 6, 15, 63, 255, 85, 0, 0, 0, 6, 15, 63, 255, 81, 0, 0, 0, 6, ++ 15, 63, 255, 77, 0, 0, 0, 6, 15, 63, 255, 74, 0, 0, 0, 6, 15, 63, 255, ++ 71, 0, 0, 0, 6, 15, 63, 255, 68, 0, 0, 0, 6, 15, 63, 255, 65, 0, 0, ++ 0, 6, 15, 63, 255, 62, 0, 0, 0, 6, 15, 63, 255, 60, 0, 0, 0, 6, 15, ++ 63, 255, 58, 0, 0, 0, 6, 15, 63, 255, 55, 0, 0, 0, 6, 15, 63, 255, 53, ++ 0, 0, 0, 6, 15, 63, 255, 51, 0, 0, 0, 6, 15, 63, 255, 50, 0, 0, 0, 6, ++ 15, 63, 255, 48, 0, 0, 0, 6, 15, 63, 255, 46, 0, 0, 0, 6, 15, 61, 255, ++ 46, 0, 0, 0, 6, 15, 57, 255, 47, 0, 0, 0, 6, 15, 58, 255, 45, 0, 0, ++ 0, 6, 15, 57, 255, 44, 0, 0, 0, 6, 15, 55, 255, 44, 0, 0, 0, 6, 15, ++ 54, 255, 43, 0, 0, 0, 6, 15, 54, 255, 42, 0, 0, 0, 6, 15, 53, 255, 41, ++ 0, 0, 0, 6, 15, 53, 255, 40, 0, 0, 0, 6, 15, 51, 255, 40, 0, 0, 0, 6, ++ 15, 49, 255, 40, 0, 0, 0, 6, 15, 48, 255, 39, 0, 0, 0, 6, 15, 47, 255, ++ 39, 0, 0, 0, 6, 15, 45, 255, 39, 0, 0, 0, 6, 15, 46, 255, 37, 0, 0, ++ 0, 6, 15, 44, 255, 37, 0, 0, 0, 6, 15, 43, 255, 37, 0, 0, 0, 6, 15, ++ 41, 255, 37, 0, 0, 0, 6, 15, 40, 255, 36, 0, 0, 0, 6, 15, 38, 255, 37, ++ 0, 0, 0, 6, 15, 36, 255, 38, 0, 0, 0, 6, 15, 34, 255, 38, 0, 0, 0, 6, ++ 15, 33, 255, 38, 0, 0, 0, 6, 15, 33, 255, 37, 0, 0, 0, 6, 15, 34, 255, ++ 35, 0, 0, 0, 6, 15, 32, 255, 35, 0, 0, 0, 6, 15, 31, 255, 35, 0, 0, ++ 0, 6, 15, 31, 255, 34, 0, 0, 0, 6, 15, 31, 255, 33, 0, 0, 0, 6, 15, ++ 28, 255, 34, 0, 0, 0, 6, 15, 28, 255, 33, 0, 0, 0, 6, 15, 28, 255, 32, ++ 0, 0, 0, 6, 15, 28, 255, 31, 0, 0, 0, 6, 15, 28, 255, 30, 0, 0, 0, 6, ++ 15, 26, 255, 31, 0, 0, 0, 6, 15, 26, 255, 30, 0, 0, 0, 6, 15, 25, 255, ++ 30, 0, 0, 0, 6, 15, 25, 255, 29, 0, 0, 0, 6, 15, 24, 255, 29, 0, 0, ++ 0, 6, 15, 24, 255, 28, 0, 0, 0, 6, 15, 22, 255, 29, 0, 0, 0, 6, 15, ++ 22, 255, 28, 0, 0, 0, 6, 15, 23, 255, 27, 0, 0, 0, 6, 15, 23, 255, 26, ++ 0, 0, 0, 6, 15, 23, 255, 25, 0, 0, 0, 6, 15, 22, 255, 25, 0, 0, 0, 6, ++ 15, 21, 255, 25, 0, 0, 0, 6, 15, 20, 255, 25, 0, 0, 0, 6, 15, 22, 255, ++ 23, 0, 0, 0, 6, 15, 21, 255, 23, 0, 0, 0, 6, 15, 23, 255, 21, 0, 0, ++ 0, 6, 15, 22, 255, 21, 0, 0, 0, 6, 15, 21, 255, 21, 0, 0, 0, 6, 15, ++ 20, 255, 21, 0, 0, 0, 6, 15, 21, 255, 20, 0, 0, 0, 6, 15, 20, 255, 20, ++ 0, 0, 0, 6, 15, 20, 255, 19, 0, 0, 0, 6, 15, 21, 255, 18, 0, 0, 0, 6, ++ 15, 18, 255, 19, 0, 0, 0, 6, 15, 19, 255, 18, 0, 0, 0, 6, 15, 18, 255, ++ 18, 0, 0, 0, 6, 15, 17, 255, 18, 0, 0, 0, 6, 15, 16, 255, 18, 0, 0, ++ 0, 6, 15, 13, 255, 20, 0, 0, 0, 6, 15, 15, 255, 18, 0, 0, 0, 6, 15, ++ 14, 255, 18, 0, 0, 0, 6, 15, 12, 255, 19, 0, 0, 0, 6, 15, 13, 255, 18, ++ 0, 0, 0, 6, 15, 12, 255, 18, 0, 0, 0, 6, 15, 11, 255, 19, 0, 0, 0, 6, ++ 15, 12, 255, 17, 0, 0, 0, 6, 15, 8, 255, 20, 0, 0, 0, 6, 15, 9, 255, ++ 19, 0, 0, 0, 6, 15, 8, 255, 19, 0, 0, 0, 6, 15, 10, 255, 17, 0, 0, 0, ++ 6, 15, 8, 255, 18, 0, 0, 0, 6, 15, 7, 255, 19, 0, 0, 0, 6, 15, 8, 255, ++ 17, 0, 0, 0, 6, 15, 7, 255, 18, 0, 0, 0, 6, 15, 7, 255, 17, 0, 0, 0, ++ 6, 15, 5, 255, 19, 0, 0, 0, 6, 15, 8, 255, 15, 0, 0, 0, 6, 15, 9, 255, ++ 14, 0, 0, 0, 6, 15, 8, 255, 14, 0, 0, 0, 6, 15, 7, 255, 15, 0, 0, 0, ++ 6, 15, 4, 255, 17, 0, 0, 0, 6, 15, 5, 255, 16, 0, 0, 0, 6, 15, 3, 255, ++ 18, 0, 0, 0, 6, 15, 4, 255, 16, 0, 0, 0, 6, 15, 1, 255, 20, 0, 0, 0, ++ 6, 15, 2, 255, 18, 0, 0, 0, 6, 15, 1, 255, 19, 0, 0, 0, 6, 15, 2, 255, ++ 17, 0, 0, 0, 6, 15, 1, 255, 18, 0, 0, 0, 6, 15, 2, 255, 16, 0, 0, 0, ++ 6, 15, 1, 255, 17, 0, 0, 0, 6, 15, 1, 255, 16, 0, 0, 0, 6, 15, 1, 255, ++ 16, 0, 0, 0, 6, 15, 1, 255, 16, 0, 0, 0, 6, 15, 1, 255, 16, 0, 0, 0, ++ 6, 15, 1, 255, 16, 0, 0, 0, 6, 15, 1, 255, 16, 0, 0, 0, 6, 15, 1, 255, ++ 16, 0, 0, 0, 6, 15, 1, 255, 16, 0, 0, 0, 6, 15, 1, 255, 16, 0, 0, 0, ++ 6, 15, 1, 255, 16, 0, 0, 0, 6, 15, 1, 255, 16, 0, 0, 0, 6, 15, 1, 255, ++ 16, 0, 0, 0, 6, 15, 1, 255, 16, 0, 0, 0, 114, 97, 116, 101, 115, 101, ++ 108, 0, 115, 116, 102, 0, 99, 99, 107, 95, 111, 110, 101, 99, 111, 114, ++ 101, 95, 116, 120, 0, 116, 101, 109, 112, 115, 95, 112, 101, 114, 105, ++ 111, 100, 0, 116, 120, 99, 104, 97, 105, 110, 0, 114, 120, 99, 104, ++ 97, 105, 110, 0, 115, 119, 100, 105, 118, 95, 115, 110, 114, 116, 104, ++ 114, 101, 115, 104, 0, 115, 119, 100, 105, 118, 95, 116, 120, 95, 119, ++ 101, 105, 103, 104, 116, 0, 115, 119, 100, 105, 118, 95, 115, 110, 114, ++ 108, 105, 109, 0, 115, 119, 100, 105, 118, 95, 115, 119, 99, 116, 114, ++ 108, 95, 109, 97, 115, 107, 0, 115, 119, 100, 105, 118, 95, 116, 105, ++ 109, 101, 111, 117, 116, 0, 115, 119, 100, 105, 118, 95, 115, 119, 99, ++ 116, 114, 108, 95, 97, 110, 116, 48, 0, 115, 119, 100, 105, 118, 95, ++ 115, 119, 99, 116, 114, 108, 95, 97, 110, 116, 49, 0, 115, 119, 100, ++ 105, 118, 95, 119, 101, 105, 103, 104, 116, 0, 115, 119, 100, 105, 118, ++ 95, 115, 101, 116, 116, 108, 101, 0, 115, 119, 100, 105, 118, 95, 101, ++ 110, 0, 115, 119, 100, 105, 118, 95, 114, 120, 95, 112, 111, 108, 105, ++ 99, 121, 0, 115, 119, 100, 105, 118, 95, 116, 120, 95, 112, 111, 108, ++ 105, 99, 121, 0, 115, 119, 100, 105, 118, 95, 115, 119, 99, 116, 114, ++ 108, 95, 101, 110, 0, 115, 119, 100, 105, 118, 95, 116, 104, 114, 101, ++ 115, 104, 0, 115, 119, 100, 105, 118, 95, 103, 112, 105, 111, 95, 49, ++ 0, 115, 119, 100, 105, 118, 95, 99, 99, 107, 110, 111, 105, 115, 101, ++ 101, 115, 116, 108, 105, 109, 0, 115, 119, 100, 105, 118, 95, 108, 111, ++ 103, 50, 97, 118, 103, 0, 115, 119, 100, 105, 118, 95, 103, 112, 105, ++ 111, 0, 115, 119, 100, 105, 118, 95, 99, 101, 108, 108, 95, 112, 111, ++ 108, 105, 99, 121, 0, 115, 119, 100, 105, 118, 95, 99, 99, 107, 115, ++ 110, 114, 99, 111, 114, 114, 0, 115, 181, 67, 105, 22, 70, 0, 34, 47, ++ 43, 4, 70, 13, 70, 1, 146, 8, 221, 51, 43, 6, 208, 19, 70, 1, 33, 175, ++ 247, 141, 254, 131, 5, 155, 13, 7, 224, 0, 33, 32, 70, 10, 70, 175, ++ 247, 200, 254, 6, 75, 3, 64, 27, 12, 27, 2, 32, 70, 51, 96, 1, 169, ++ 42, 70, 0, 240, 5, 248, 1, 152, 124, 189, 0, 191, 0, 0, 255, 3, 248, ++ 181, 4, 70, 14, 70, 21, 70, 178, 243, 40, 247, 64, 246, 18, 1, 0, 34, ++ 7, 70, 32, 70, 179, 243, 97, 242, 32, 70, 178, 243, 38, 247, 32, 70, ++ 57, 70, 179, 243, 104, 242, 2, 75, 51, 96, 79, 244, 200, 99, 43, 96, ++ 248, 189, 116, 101, 6, 0, 11, 70, 192, 111, 17, 70, 26, 70, 255, 247, ++ 184, 191, 16, 181, 1, 33, 4, 70, 192, 111, 175, 247, 250, 254, 224, ++ 111, 179, 243, 125, 242, 0, 32, 16, 189, 55, 181, 0, 36, 105, 70, 1, ++ 170, 5, 70, 0, 148, 1, 148, 255, 247, 230, 255, 157, 232, 6, 0, 3, 70, ++ 40, 70, 234, 243, 174, 247, 32, 70, 62, 189, 56, 181, 4, 70, 192, 111, ++ 175, 247, 233, 254, 72, 177, 32, 70, 255, 247, 230, 255, 5, 70, 56, ++ 185, 32, 70, 255, 247, 214, 255, 40, 70, 56, 189, 79, 240, 255, 48, ++ 56, 189, 0, 32, 56, 189, 45, 233, 255, 65, 7, 70, 79, 244, 178, 112, ++ 14, 70, 21, 70, 152, 70, 175, 247, 77, 253, 4, 70, 0, 40, 50, 208, 0, ++ 33, 79, 244, 178, 114, 168, 243, 43, 241, 10, 155, 56, 70, 0, 147, 4, ++ 241, 128, 3, 1, 147, 4, 241, 132, 3, 2, 147, 49, 70, 42, 70, 67, 70, ++ 243, 247, 175, 249, 224, 103, 192, 177, 1, 35, 99, 116, 64, 246, 18, ++ 1, 0, 34, 179, 243, 242, 241, 12, 33, 0, 34, 196, 248, 136, 0, 224, ++ 111, 178, 243, 159, 246, 32, 70, 246, 247, 160, 252, 32, 70, 255, 247, ++ 181, 255, 224, 111, 242, 247, 84, 255, 0, 37, 0, 224, 11, 37, 32, 70, ++ 175, 247, 27, 253, 0, 224, 30, 37, 40, 70, 4, 176, 189, 232, 240, 129, ++ 75, 172, 0, 0, 1, 188, 96, 3, 0, 16, 78, 3, 191, 222, 2, 240, 14, 85, ++ 2, 128, 193, 39, 0, 0, 4, 3, 191, 222, 2, 240, 16, 82, 3, 168, 94, 2, ++ 240, 0, 18, 3, 166, 94, 2, 240, 0, 18, 2, 130, 94, 83, 0, 0, 18, 2, ++ 133, 94, 175, 0, 0, 18, 2, 2, 0, 191, 0, 0, 15, 3, 168, 94, 2, 240, ++ 0, 18, 2, 130, 222, 187, 0, 0, 18, 2, 130, 222, 179, 0, 0, 18, 2, 132, ++ 94, 183, 0, 0, 18, 2, 132, 94, 179, 0, 0, 18, 2, 134, 0, 199, 0, 0, ++ 18, 2, 132, 128, 195, 0, 0, 18, 1, 188, 99, 255, 31, 240, 64, 0, 0, ++ 128, 0, 0, 0, 0, 3, 91, 94, 2, 240, 0, 20, 1, 188, 96, 19, 0, 16, 67, ++ 0, 1, 94, 2, 240, 0, 0, 0, 2, 94, 2, 240, 24, 62, 2, 2, 0, 191, 0, 0, ++ 180, 2, 4, 94, 255, 0, 0, 27, 0, 107, 68, 101, 86, 128, 27, 1, 132, ++ 96, 2, 247, 247, 191, 1, 188, 96, 3, 0, 10, 166, 0, 2, 94, 2, 240, 18, ++ 48, 2, 2, 222, 255, 0, 0, 32, 0, 107, 68, 101, 85, 32, 32, 1, 130, 224, ++ 2, 247, 247, 191, 3, 191, 222, 2, 240, 6, 196, 2, 1, 172, 123, 0, 0, ++ 37, 0, 232, 68, 101, 97, 119, 161, 1, 188, 96, 127, 8, 23, 162, 0, 109, ++ 94, 134, 244, 64, 37, 0, 168, 44, 123, 1, 11, 30, 0, 104, 43, 79, 0, ++ 0, 42, 2, 128, 222, 255, 0, 0, 180, 0, 107, 68, 101, 90, 96, 180, 1, ++ 132, 224, 6, 245, 119, 171, 0, 2, 94, 2, 240, 21, 155, 2, 4, 128, 199, ++ 0, 0, 44, 2, 129, 128, 199, 0, 0, 46, 1, 128, 96, 2, 247, 247, 191, ++ 1, 188, 96, 3, 0, 10, 218, 0, 144, 43, 227, 0, 215, 162, 0, 224, 43, ++ 222, 244, 87, 163, 0, 109, 68, 106, 244, 96, 50, 0, 176, 43, 215, 0, ++ 10, 240, 1, 135, 96, 2, 247, 247, 191, 0, 104, 43, 191, 0, 0, 58, 0, ++ 233, 68, 101, 93, 247, 163, 0, 232, 196, 105, 94, 119, 162, 0, 104, ++ 222, 139, 0, 0, 58, 0, 109, 222, 141, 94, 0, 58, 2, 134, 171, 211, 0, ++ 0, 58, 1, 135, 96, 6, 247, 247, 191, 2, 7, 222, 255, 0, 0, 63, 0, 232, ++ 68, 101, 90, 55, 162, 0, 109, 94, 137, 90, 0, 63, 1, 135, 224, 2, 247, ++ 247, 191, 1, 188, 96, 3, 0, 10, 209, 0, 104, 44, 111, 0, 0, 69, 1, 188, ++ 97, 247, 0, 23, 161, 0, 232, 68, 101, 99, 119, 162, 0, 109, 94, 138, ++ 244, 32, 69, 1, 188, 96, 3, 0, 11, 27, 0, 168, 44, 123, 0, 43, 30, 0, ++ 104, 42, 231, 0, 0, 81, 0, 232, 68, 101, 87, 55, 161, 0, 109, 222, 133, ++ 86, 64, 76, 0, 104, 43, 35, 0, 0, 81, 0, 232, 68, 101, 89, 23, 161, ++ 0, 109, 222, 133, 86, 64, 78, 3, 191, 222, 2, 240, 0, 81, 1, 188, 96, ++ 3, 0, 10, 186, 1, 188, 96, 3, 0, 10, 185, 1, 188, 96, 3, 0, 10, 200, ++ 1, 188, 96, 3, 0, 10, 192, 0, 168, 44, 123, 0, 75, 30, 2, 2, 222, 179, ++ 0, 0, 84, 2, 0, 66, 3, 0, 0, 84, 0, 2, 94, 2, 240, 13, 40, 2, 3, 197, ++ 115, 0, 0, 87, 2, 132, 94, 179, 0, 0, 180, 0, 104, 170, 239, 0, 0, 180, ++ 2, 132, 222, 183, 0, 0, 89, 2, 1, 128, 199, 0, 0, 121, 0, 176, 42, 171, ++ 0, 23, 162, 2, 128, 43, 211, 0, 0, 96, 0, 176, 43, 3, 0, 23, 161, 0, ++ 109, 222, 133, 91, 224, 171, 0, 104, 94, 135, 0, 0, 96, 0, 104, 43, ++ 231, 0, 0, 96, 0, 176, 43, 231, 0, 23, 162, 0, 104, 42, 235, 0, 0, 102, ++ 0, 232, 68, 101, 87, 87, 161, 1, 133, 96, 6, 245, 215, 174, 0, 109, ++ 222, 134, 244, 64, 171, 0, 224, 94, 133, 84, 247, 161, 0, 109, 222, ++ 134, 244, 64, 171, 1, 133, 96, 2, 245, 215, 174, 2, 2, 222, 187, 0, ++ 0, 121, 0, 104, 42, 155, 0, 0, 121, 0, 232, 68, 101, 85, 215, 161, 0, ++ 224, 42, 155, 1, 87, 162, 0, 110, 222, 134, 244, 64, 114, 1, 130, 224, ++ 2, 245, 215, 174, 1, 129, 96, 1, 99, 203, 30, 1, 188, 96, 3, 0, 10, ++ 234, 1, 188, 96, 3, 0, 10, 166, 1, 188, 96, 3, 0, 10, 229, 3, 191, 222, ++ 2, 240, 0, 121, 0, 110, 170, 154, 244, 32, 120, 0, 232, 42, 154, 244, ++ 55, 161, 0, 144, 42, 155, 0, 55, 162, 0, 110, 42, 158, 244, 64, 119, ++ 0, 176, 42, 159, 0, 23, 162, 0, 105, 222, 134, 244, 64, 121, 3, 191, ++ 222, 2, 240, 0, 171, 2, 132, 222, 183, 0, 0, 158, 2, 136, 129, 171, ++ 0, 0, 156, 2, 4, 94, 183, 0, 0, 180, 2, 4, 128, 199, 0, 0, 133, 0, 104, ++ 42, 247, 0, 32, 133, 0, 104, 42, 247, 0, 128, 133, 0, 104, 42, 223, ++ 0, 0, 132, 0, 104, 42, 247, 2, 224, 130, 0, 104, 170, 247, 8, 96, 132, ++ 0, 232, 68, 101, 86, 55, 161, 0, 109, 94, 133, 86, 224, 180, 2, 0, 94, ++ 255, 0, 0, 156, 2, 128, 128, 191, 0, 0, 156, 0, 104, 43, 35, 0, 0, 139, ++ 2, 128, 43, 211, 0, 0, 139, 0, 176, 43, 43, 0, 23, 187, 0, 110, 43, ++ 2, 247, 96, 180, 3, 191, 222, 2, 240, 0, 156, 2, 5, 222, 183, 0, 0, ++ 142, 0, 104, 42, 247, 8, 96, 180, 3, 191, 222, 2, 240, 0, 156, 2, 132, ++ 0, 199, 0, 0, 144, 2, 134, 0, 199, 0, 0, 146, 0, 104, 42, 235, 0, 0, ++ 156, 2, 129, 44, 39, 0, 0, 156, 0, 232, 68, 101, 86, 55, 161, 2, 6, ++ 171, 211, 0, 0, 150, 0, 232, 69, 201, 90, 247, 162, 3, 191, 222, 2, ++ 240, 0, 151, 0, 232, 69, 137, 90, 247, 162, 2, 134, 171, 211, 0, 0, ++ 154, 0, 232, 94, 134, 244, 87, 161, 0, 105, 222, 133, 87, 0, 156, 0, ++ 108, 196, 101, 86, 96, 180, 2, 133, 94, 183, 0, 0, 180, 0, 2, 94, 2, ++ 240, 21, 197, 3, 191, 222, 2, 240, 0, 180, 2, 133, 171, 211, 0, 0, 165, ++ 2, 6, 171, 211, 0, 0, 163, 1, 188, 99, 255, 31, 247, 161, 0, 104, 69, ++ 198, 244, 32, 156, 3, 191, 222, 2, 240, 0, 165, 1, 188, 99, 255, 31, ++ 247, 161, 0, 104, 69, 134, 244, 32, 156, 2, 3, 197, 115, 0, 0, 171, ++ 2, 133, 94, 183, 0, 0, 171, 2, 1, 0, 199, 0, 0, 180, 0, 107, 68, 101, ++ 86, 128, 180, 0, 32, 227, 254, 20, 96, 180, 2, 130, 222, 187, 0, 0, ++ 180, 2, 2, 44, 39, 0, 0, 174, 2, 130, 222, 187, 0, 0, 174, 3, 191, 222, ++ 2, 240, 0, 156, 2, 136, 129, 171, 0, 0, 180, 2, 130, 222, 179, 0, 0, ++ 180, 2, 128, 128, 191, 0, 0, 180, 2, 132, 222, 175, 0, 0, 180, 2, 130, ++ 94, 187, 0, 0, 180, 0, 2, 94, 2, 240, 21, 248, 1, 128, 96, 2, 13, 144, ++ 108, 3, 89, 94, 2, 240, 0, 182, 3, 216, 94, 2, 240, 0, 183, 3, 216, ++ 222, 2, 240, 0, 184, 1, 188, 97, 131, 0, 17, 41, 0, 176, 0, 123, 0, ++ 17, 43, 1, 188, 99, 3, 0, 17, 35, 3, 18, 94, 2, 240, 12, 171, 3, 151, ++ 94, 2, 240, 13, 60, 3, 208, 94, 2, 240, 3, 145, 3, 208, 222, 2, 240, ++ 6, 65, 3, 213, 222, 2, 240, 12, 93, 3, 145, 94, 2, 240, 6, 156, 3, 150, ++ 222, 2, 240, 12, 88, 2, 136, 193, 115, 0, 1, 35, 3, 196, 94, 2, 240, ++ 8, 17, 3, 199, 94, 2, 240, 8, 51, 3, 220, 222, 2, 240, 22, 63, 3, 170, ++ 94, 2, 240, 8, 163, 3, 134, 222, 2, 240, 12, 156, 2, 135, 192, 55, 0, ++ 12, 156, 3, 131, 94, 2, 240, 10, 79, 2, 6, 128, 199, 0, 0, 208, 2, 2, ++ 176, 195, 0, 0, 208, 0, 108, 48, 202, 35, 32, 208, 1, 130, 224, 1, 134, ++ 12, 48, 1, 188, 96, 127, 31, 247, 162, 1, 224, 94, 138, 16, 112, 131, ++ 3, 145, 222, 2, 240, 7, 33, 2, 6, 128, 199, 0, 1, 7, 2, 6, 1, 171, 0, ++ 0, 227, 2, 0, 48, 195, 0, 0, 227, 0, 104, 222, 75, 6, 32, 227, 2, 0, ++ 66, 3, 0, 0, 227, 2, 132, 69, 35, 0, 0, 227, 2, 128, 176, 195, 0, 0, ++ 227, 0, 110, 69, 23, 0, 32, 227, 1, 188, 96, 3, 0, 16, 128, 0, 168, ++ 65, 35, 0, 240, 72, 3, 208, 222, 2, 240, 0, 220, 3, 208, 94, 2, 240, ++ 0, 221, 3, 213, 222, 2, 240, 0, 222, 0, 224, 1, 223, 0, 32, 119, 1, ++ 128, 224, 5, 134, 12, 48, 1, 188, 96, 3, 0, 12, 49, 0, 2, 94, 2, 240, ++ 24, 25, 0, 2, 94, 2, 240, 24, 45, 2, 14, 1, 171, 0, 0, 240, 2, 132, ++ 69, 35, 0, 0, 240, 2, 1, 48, 195, 0, 0, 240, 0, 224, 1, 227, 0, 32, ++ 120, 1, 129, 96, 1, 134, 12, 48, 1, 128, 224, 1, 134, 12, 48, 1, 12, ++ 129, 67, 0, 23, 166, 0, 104, 222, 155, 0, 96, 237, 1, 188, 96, 3, 0, ++ 76, 49, 3, 191, 222, 2, 240, 0, 239, 0, 104, 222, 155, 0, 64, 239, 1, ++ 188, 96, 3, 0, 44, 49, 0, 2, 94, 2, 240, 24, 25, 2, 6, 129, 171, 0, ++ 1, 7, 2, 2, 48, 195, 0, 0, 251, 2, 128, 66, 3, 0, 0, 251, 2, 132, 69, ++ 35, 0, 0, 251, 3, 145, 94, 2, 240, 6, 156, 0, 224, 1, 235, 0, 32, 122, ++ 1, 128, 224, 5, 134, 12, 48, 1, 130, 96, 1, 134, 12, 48, 1, 188, 96, ++ 3, 0, 12, 49, 0, 2, 94, 2, 240, 24, 25, 0, 2, 94, 2, 240, 24, 45, 2, ++ 1, 176, 195, 0, 0, 254, 0, 108, 48, 206, 35, 32, 254, 1, 129, 224, 1, ++ 134, 12, 48, 2, 3, 48, 195, 0, 1, 7, 0, 108, 48, 210, 35, 33, 7, 1, ++ 131, 96, 1, 134, 12, 48, 2, 0, 66, 3, 0, 1, 7, 0, 104, 94, 75, 4, 65, ++ 5, 0, 104, 94, 75, 0, 65, 5, 3, 191, 222, 2, 240, 1, 7, 1, 130, 96, ++ 6, 9, 16, 72, 1, 188, 96, 3, 0, 17, 69, 3, 194, 222, 2, 240, 13, 3, ++ 0, 2, 94, 2, 240, 18, 47, 3, 212, 222, 2, 240, 7, 186, 3, 163, 222, ++ 2, 240, 0, 2, 3, 200, 94, 2, 240, 5, 255, 2, 4, 222, 179, 0, 1, 16, ++ 2, 1, 69, 35, 0, 1, 16, 1, 132, 224, 2, 245, 151, 172, 0, 2, 94, 2, ++ 240, 6, 59, 2, 1, 197, 35, 0, 1, 18, 1, 135, 224, 2, 245, 119, 171, ++ 0, 2, 94, 2, 240, 14, 168, 0, 2, 94, 2, 240, 17, 112, 2, 24, 46, 3, ++ 0, 1, 22, 0, 2, 94, 2, 240, 17, 131, 3, 162, 94, 2, 240, 1, 32, 3, 86, ++ 94, 2, 240, 1, 29, 1, 134, 96, 6, 9, 16, 72, 3, 31, 94, 2, 240, 1, 29, ++ 0, 106, 94, 35, 0, 1, 28, 0, 176, 0, 39, 0, 23, 136, 0, 232, 94, 35, ++ 0, 55, 136, 3, 166, 94, 2, 240, 1, 142, 0, 2, 94, 2, 240, 17, 241, 0, ++ 40, 96, 14, 8, 225, 180, 3, 196, 222, 2, 240, 13, 115, 0, 32, 194, 3, ++ 0, 33, 188, 3, 191, 222, 2, 240, 2, 13, 3, 129, 94, 2, 240, 1, 37, 3, ++ 0, 222, 2, 240, 0, 195, 1, 136, 224, 2, 11, 144, 92, 3, 191, 222, 2, ++ 240, 3, 142, 2, 135, 64, 99, 0, 1, 39, 1, 142, 224, 14, 244, 48, 24, ++ 2, 135, 64, 99, 0, 1, 41, 0, 2, 222, 2, 240, 0, 0, 2, 135, 64, 99, 0, ++ 1, 43, 0, 176, 94, 139, 0, 16, 25, 1, 142, 224, 10, 244, 48, 24, 0, ++ 2, 222, 2, 240, 0, 0, 1, 188, 96, 99, 0, 16, 123, 1, 188, 96, 27, 0, ++ 16, 122, 1, 172, 96, 126, 244, 112, 117, 2, 135, 65, 215, 0, 1, 50, ++ 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 99, 0, 16, 123, 1, 188, 96, 27, ++ 0, 16, 122, 1, 172, 96, 190, 244, 112, 117, 2, 135, 65, 215, 0, 1, 55, ++ 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 99, 0, 16, 123, 0, 176, 94, 139, ++ 0, 16, 122, 1, 172, 96, 126, 244, 48, 117, 2, 135, 65, 215, 0, 1, 60, ++ 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 99, 0, 16, 123, 0, 176, 94, 139, ++ 0, 16, 122, 1, 172, 96, 190, 244, 48, 117, 2, 135, 65, 215, 0, 1, 65, ++ 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 3, 2, 128, 6, 2, 128, 222, 7, 0, ++ 1, 77, 1, 218, 96, 2, 240, 23, 128, 2, 8, 94, 7, 0, 1, 97, 1, 188, 96, ++ 3, 30, 23, 161, 0, 224, 94, 2, 244, 48, 101, 1, 188, 96, 3, 28, 23, ++ 161, 0, 224, 94, 2, 244, 48, 100, 1, 188, 96, 3, 0, 40, 17, 3, 191, ++ 222, 2, 240, 1, 103, 1, 16, 94, 3, 0, 23, 161, 1, 3, 94, 3, 0, 23, 162, ++ 0, 224, 94, 134, 244, 87, 161, 0, 136, 94, 135, 0, 55, 162, 0, 224, ++ 94, 134, 244, 87, 161, 0, 224, 1, 90, 244, 48, 99, 2, 134, 0, 195, 0, ++ 1, 88, 0, 176, 86, 11, 0, 16, 98, 0, 176, 84, 3, 0, 16, 98, 1, 188, ++ 96, 3, 0, 40, 17, 3, 191, 222, 2, 240, 1, 105, 0, 176, 65, 143, 0, 16, ++ 98, 1, 9, 222, 3, 0, 23, 161, 0, 104, 222, 135, 0, 65, 92, 0, 224, 94, ++ 135, 0, 55, 161, 0, 136, 94, 135, 0, 87, 161, 0, 224, 94, 133, 4, 183, ++ 161, 0, 224, 94, 135, 3, 192, 6, 1, 188, 96, 3, 0, 72, 17, 3, 191, 222, ++ 2, 240, 1, 105, 1, 188, 96, 7, 2, 23, 161, 0, 224, 94, 2, 244, 48, 101, ++ 1, 188, 96, 7, 0, 23, 161, 0, 224, 94, 2, 244, 48, 100, 1, 188, 96, ++ 3, 24, 0, 6, 1, 188, 96, 3, 0, 8, 17, 0, 176, 90, 3, 0, 16, 98, 0, 176, ++ 88, 3, 0, 16, 99, 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 3, 6, 55, 146, ++ 1, 188, 99, 255, 31, 240, 195, 1, 188, 96, 3, 24, 144, 227, 1, 188, ++ 96, 251, 28, 16, 229, 1, 188, 96, 3, 0, 80, 16, 0, 176, 64, 67, 0, 24, ++ 0, 0, 176, 64, 71, 0, 16, 231, 0, 2, 222, 2, 240, 0, 0, 0, 232, 64, ++ 51, 0, 151, 161, 0, 176, 64, 11, 0, 23, 163, 0, 109, 94, 134, 244, 97, ++ 119, 0, 144, 94, 143, 0, 55, 163, 3, 191, 222, 2, 240, 1, 120, 0, 144, ++ 94, 135, 0, 55, 163, 1, 188, 96, 27, 4, 55, 161, 0, 224, 94, 142, 244, ++ 55, 163, 1, 240, 65, 151, 0, 23, 161, 0, 109, 222, 134, 244, 97, 140, ++ 2, 135, 193, 151, 0, 1, 128, 1, 56, 90, 3, 0, 23, 161, 1, 60, 90, 3, ++ 0, 23, 162, 3, 191, 222, 2, 240, 1, 130, 1, 60, 90, 3, 0, 23, 161, 1, ++ 56, 90, 7, 0, 23, 162, 0, 104, 94, 134, 244, 129, 135, 0, 216, 94, 139, ++ 0, 55, 162, 0, 225, 65, 150, 244, 80, 101, 0, 225, 193, 151, 0, 48, ++ 101, 3, 191, 222, 2, 240, 1, 122, 0, 216, 94, 139, 0, 55, 162, 0, 225, ++ 65, 150, 244, 87, 161, 0, 225, 222, 135, 0, 55, 161, 1, 240, 94, 135, ++ 0, 23, 161, 0, 110, 222, 134, 244, 97, 141, 1, 188, 99, 255, 31, 247, ++ 164, 0, 2, 222, 2, 240, 0, 0, 2, 6, 129, 171, 0, 1, 144, 1, 130, 96, ++ 1, 134, 12, 48, 0, 32, 227, 142, 9, 0, 2, 3, 30, 222, 2, 240, 1, 150, ++ 3, 159, 94, 2, 240, 1, 150, 1, 188, 96, 67, 1, 23, 161, 0, 168, 65, ++ 34, 244, 48, 72, 3, 191, 222, 2, 240, 0, 2, 2, 8, 65, 31, 0, 1, 147, ++ 1, 129, 96, 5, 97, 11, 8, 0, 2, 94, 2, 240, 13, 40, 0, 176, 0, 171, ++ 0, 16, 134, 0, 176, 1, 99, 0, 16, 138, 0, 2, 94, 2, 240, 16, 108, 1, ++ 188, 96, 3, 4, 23, 146, 0, 176, 0, 59, 0, 17, 29, 1, 144, 96, 6, 9, ++ 16, 72, 3, 161, 222, 2, 240, 1, 174, 1, 129, 224, 6, 9, 16, 72, 1, 188, ++ 96, 3, 0, 144, 66, 1, 188, 96, 3, 0, 17, 45, 3, 158, 222, 2, 240, 1, ++ 177, 1, 132, 96, 2, 242, 151, 148, 0, 176, 69, 23, 0, 23, 143, 0, 176, ++ 94, 23, 0, 23, 144, 2, 0, 68, 31, 0, 1, 170, 1, 133, 96, 2, 9, 16, 72, ++ 1, 129, 96, 7, 0, 16, 71, 1, 240, 222, 15, 0, 55, 161, 2, 4, 0, 191, ++ 0, 1, 173, 1, 240, 132, 199, 0, 55, 161, 0, 160, 68, 182, 244, 49, 69, ++ 3, 158, 222, 2, 240, 1, 177, 1, 188, 97, 55, 18, 176, 128, 3, 191, 222, ++ 2, 240, 0, 2, 0, 160, 68, 180, 42, 49, 69, 1, 188, 97, 39, 18, 112, ++ 128, 3, 191, 222, 2, 240, 0, 2, 0, 32, 224, 130, 9, 0, 2, 1, 12, 222, ++ 83, 0, 23, 161, 1, 136, 94, 135, 0, 16, 71, 1, 188, 96, 3, 0, 80, 66, ++ 1, 8, 65, 31, 0, 23, 161, 1, 140, 222, 134, 242, 151, 148, 3, 191, 222, ++ 2, 240, 0, 2, 0, 2, 222, 2, 240, 0, 0, 0, 32, 224, 126, 9, 0, 2, 0, ++ 2, 94, 2, 240, 17, 251, 2, 131, 194, 31, 0, 0, 2, 2, 2, 128, 243, 0, ++ 1, 198, 0, 176, 68, 103, 0, 23, 161, 1, 124, 94, 134, 35, 87, 163, 2, ++ 131, 94, 255, 0, 1, 197, 0, 224, 0, 250, 244, 104, 41, 1, 131, 96, 6, ++ 247, 247, 191, 0, 107, 222, 141, 5, 33, 202, 2, 6, 208, 3, 0, 1, 206, ++ 0, 233, 80, 134, 35, 55, 161, 0, 232, 208, 138, 35, 87, 162, 0, 105, ++ 222, 139, 0, 1, 206, 0, 2, 94, 2, 240, 13, 40, 1, 145, 96, 22, 132, ++ 244, 39, 0, 224, 32, 167, 0, 136, 41, 3, 191, 222, 2, 240, 3, 107, 0, ++ 2, 94, 2, 240, 3, 110, 2, 4, 0, 191, 0, 1, 214, 3, 148, 94, 2, 240, ++ 0, 2, 0, 32, 194, 143, 6, 0, 2, 0, 160, 66, 143, 1, 247, 128, 0, 104, ++ 94, 0, 45, 192, 2, 0, 2, 94, 2, 240, 13, 40, 3, 191, 222, 2, 240, 0, ++ 18, 2, 1, 194, 143, 0, 0, 2, 1, 20, 0, 99, 0, 23, 161, 0, 104, 94, 135, ++ 0, 96, 2, 0, 2, 94, 2, 240, 13, 40, 1, 148, 96, 15, 0, 0, 24, 0, 2, ++ 94, 2, 240, 1, 221, 3, 191, 222, 2, 240, 0, 18, 1, 20, 0, 99, 0, 23, ++ 161, 0, 176, 94, 135, 0, 16, 165, 1, 188, 96, 19, 27, 144, 96, 0, 104, ++ 94, 135, 0, 1, 228, 0, 224, 65, 131, 6, 208, 96, 0, 232, 94, 135, 0, ++ 55, 161, 3, 191, 222, 2, 240, 1, 224, 2, 128, 80, 195, 0, 1, 242, 1, ++ 135, 96, 4, 3, 16, 160, 0, 176, 0, 99, 0, 16, 180, 0, 176, 66, 211, ++ 0, 24, 0, 0, 136, 65, 131, 0, 48, 182, 1, 188, 96, 3, 11, 16, 181, 0, ++ 176, 0, 99, 0, 176, 180, 3, 23, 222, 2, 240, 1, 235, 3, 151, 222, 2, ++ 240, 1, 236, 1, 128, 96, 6, 134, 20, 48, 0, 104, 208, 211, 0, 1, 242, ++ 0, 104, 208, 215, 0, 1, 242, 0, 176, 68, 103, 0, 20, 52, 0, 176, 68, ++ 107, 0, 20, 53, 0, 2, 222, 2, 240, 0, 0, 0, 32, 224, 18, 128, 66, 12, ++ 1, 135, 96, 4, 3, 16, 160, 0, 176, 0, 99, 0, 16, 180, 1, 188, 96, 3, ++ 14, 16, 181, 0, 176, 0, 99, 0, 240, 180, 1, 188, 96, 87, 3, 16, 182, ++ 0, 176, 0, 99, 0, 16, 180, 1, 188, 96, 3, 2, 208, 181, 2, 7, 80, 11, ++ 0, 2, 9, 1, 188, 96, 3, 3, 208, 181, 1, 142, 96, 2, 242, 151, 148, 2, ++ 4, 80, 11, 0, 2, 2, 2, 4, 208, 11, 0, 2, 2, 1, 134, 96, 6, 242, 151, ++ 148, 0, 224, 66, 215, 0, 208, 181, 0, 160, 80, 11, 17, 23, 161, 0, 104, ++ 222, 135, 17, 2, 8, 1, 134, 224, 6, 242, 151, 148, 0, 224, 66, 215, ++ 0, 80, 181, 2, 7, 208, 11, 0, 2, 8, 0, 224, 66, 215, 0, 144, 181, 0, ++ 176, 66, 215, 0, 17, 225, 0, 176, 0, 99, 0, 176, 180, 3, 23, 222, 2, ++ 240, 2, 10, 3, 151, 222, 2, 240, 2, 11, 0, 2, 222, 2, 240, 0, 0, 0, ++ 104, 32, 195, 0, 2, 16, 0, 108, 196, 101, 6, 0, 18, 1, 188, 96, 3, 0, ++ 8, 48, 0, 104, 32, 187, 0, 2, 19, 0, 108, 196, 101, 5, 224, 18, 1, 188, ++ 96, 3, 0, 8, 46, 0, 32, 224, 190, 9, 0, 2, 2, 6, 129, 171, 0, 2, 23, ++ 2, 129, 176, 195, 0, 0, 2, 2, 128, 176, 195, 0, 0, 2, 3, 144, 94, 2, ++ 240, 0, 18, 3, 162, 94, 2, 240, 2, 41, 0, 2, 94, 2, 240, 17, 92, 2, ++ 2, 0, 191, 0, 2, 40, 2, 132, 222, 175, 0, 2, 32, 2, 4, 94, 183, 0, 2, ++ 40, 0, 2, 94, 2, 240, 21, 105, 2, 4, 94, 183, 0, 2, 40, 3, 191, 222, ++ 2, 240, 0, 2, 2, 4, 94, 183, 0, 2, 35, 2, 4, 128, 199, 0, 2, 40, 2, ++ 128, 94, 255, 0, 2, 40, 0, 2, 94, 2, 240, 21, 18, 2, 6, 171, 211, 0, ++ 2, 39, 2, 5, 44, 35, 0, 2, 39, 3, 191, 222, 2, 240, 2, 40, 3, 191, 222, ++ 2, 240, 0, 2, 0, 2, 94, 2, 240, 17, 251, 2, 0, 66, 31, 0, 2, 64, 0, ++ 104, 66, 243, 0, 2, 44, 0, 109, 66, 243, 0, 98, 64, 1, 20, 0, 99, 0, ++ 23, 161, 0, 176, 94, 135, 0, 23, 162, 3, 162, 94, 2, 240, 2, 52, 3, ++ 20, 94, 2, 240, 2, 66, 0, 110, 196, 86, 128, 98, 66, 2, 129, 69, 35, ++ 0, 2, 66, 0, 110, 94, 135, 0, 98, 64, 1, 188, 96, 3, 0, 119, 162, 0, ++ 136, 96, 6, 244, 87, 163, 0, 136, 94, 139, 1, 0, 24, 0, 232, 94, 139, ++ 0, 55, 162, 0, 32, 194, 142, 244, 98, 58, 0, 106, 222, 134, 244, 66, ++ 52, 3, 191, 222, 2, 240, 2, 64, 2, 4, 0, 191, 0, 2, 108, 0, 144, 0, ++ 99, 1, 1, 101, 0, 128, 133, 151, 2, 23, 161, 0, 224, 100, 130, 13, 161, ++ 102, 0, 2, 94, 2, 240, 17, 216, 3, 191, 222, 2, 240, 2, 108, 1, 130, ++ 96, 2, 9, 16, 72, 3, 191, 222, 2, 240, 0, 2, 1, 188, 96, 3, 0, 17, 21, ++ 0, 176, 1, 127, 0, 23, 166, 3, 31, 94, 2, 240, 2, 81, 2, 3, 0, 195, ++ 0, 2, 71, 0, 32, 194, 143, 2, 2, 75, 3, 37, 94, 2, 240, 2, 81, 0, 32, ++ 194, 143, 2, 2, 75, 0, 104, 129, 83, 255, 224, 18, 3, 191, 222, 2, 240, ++ 2, 77, 1, 148, 96, 19, 0, 0, 24, 3, 191, 222, 2, 240, 2, 108, 3, 158, ++ 222, 2, 240, 2, 80, 0, 104, 222, 152, 11, 194, 80, 2, 1, 65, 31, 0, ++ 15, 30, 1, 133, 96, 2, 9, 16, 72, 0, 104, 94, 152, 11, 194, 85, 0, 105, ++ 94, 159, 0, 98, 111, 2, 152, 66, 143, 0, 2, 85, 3, 191, 222, 2, 240, ++ 2, 111, 2, 1, 65, 31, 0, 15, 30, 2, 4, 0, 191, 0, 2, 92, 2, 24, 66, ++ 143, 0, 15, 30, 0, 2, 94, 2, 240, 17, 186, 0, 2, 94, 2, 240, 17, 216, ++ 1, 148, 5, 135, 0, 0, 24, 3, 191, 222, 2, 240, 2, 108, 2, 0, 21, 11, ++ 0, 2, 101, 2, 0, 22, 187, 0, 2, 104, 0, 176, 20, 151, 0, 23, 161, 0, ++ 104, 222, 132, 178, 34, 101, 0, 176, 20, 155, 0, 23, 161, 0, 104, 222, ++ 132, 178, 66, 101, 0, 176, 20, 159, 0, 23, 161, 0, 104, 222, 132, 178, ++ 98, 101, 2, 158, 20, 231, 0, 2, 104, 2, 1, 194, 143, 0, 2, 106, 1, 148, ++ 96, 15, 0, 0, 24, 3, 191, 222, 2, 240, 2, 108, 2, 1, 194, 143, 0, 2, ++ 106, 1, 128, 96, 6, 13, 144, 108, 2, 0, 194, 143, 0, 15, 30, 1, 148, ++ 96, 7, 0, 0, 24, 0, 2, 94, 2, 240, 1, 221, 2, 4, 0, 191, 0, 2, 158, ++ 3, 191, 222, 2, 240, 2, 158, 1, 188, 96, 3, 24, 16, 96, 1, 41, 80, 11, ++ 0, 23, 146, 0, 176, 1, 123, 0, 16, 101, 0, 104, 0, 235, 0, 2, 119, 0, ++ 136, 90, 19, 1, 23, 161, 0, 232, 68, 102, 244, 55, 161, 0, 110, 222, ++ 132, 7, 66, 119, 3, 191, 222, 2, 240, 7, 179, 1, 144, 96, 18, 9, 16, ++ 72, 1, 148, 96, 31, 0, 0, 24, 1, 8, 90, 15, 0, 23, 129, 1, 136, 94, ++ 6, 129, 84, 10, 1, 52, 90, 15, 0, 23, 128, 0, 2, 94, 2, 240, 1, 67, ++ 0, 176, 1, 123, 0, 16, 101, 0, 176, 86, 35, 0, 23, 161, 0, 224, 94, ++ 134, 160, 151, 161, 0, 232, 94, 132, 0, 244, 3, 0, 232, 94, 132, 0, ++ 244, 22, 0, 176, 90, 3, 0, 20, 19, 0, 176, 90, 7, 0, 20, 20, 0, 176, ++ 90, 11, 0, 20, 21, 0, 104, 222, 7, 0, 66, 143, 0, 232, 0, 151, 0, 87, ++ 161, 1, 188, 94, 134, 240, 20, 27, 1, 124, 94, 135, 0, 244, 28, 0, 176, ++ 32, 71, 0, 23, 129, 0, 2, 94, 2, 240, 16, 125, 0, 176, 1, 123, 0, 16, ++ 101, 1, 8, 90, 15, 0, 23, 129, 0, 176, 94, 135, 0, 20, 30, 3, 191, 222, ++ 2, 240, 2, 146, 0, 176, 86, 23, 0, 20, 27, 0, 176, 86, 27, 0, 20, 28, ++ 0, 176, 84, 19, 0, 20, 30, 0, 176, 80, 19, 0, 16, 134, 0, 109, 0, 167, ++ 0, 130, 152, 1, 144, 1, 99, 0, 16, 138, 0, 176, 65, 143, 0, 16, 98, ++ 0, 2, 94, 2, 240, 22, 12, 0, 176, 66, 43, 0, 20, 6, 1, 188, 96, 3, 24, ++ 23, 161, 0, 109, 193, 140, 32, 2, 155, 1, 188, 96, 3, 2, 151, 161, 0, ++ 224, 94, 132, 3, 119, 161, 0, 224, 94, 134, 176, 17, 29, 3, 191, 222, ++ 2, 240, 3, 52, 2, 3, 0, 199, 0, 2, 174, 2, 12, 208, 3, 0, 2, 174, 1, ++ 20, 0, 99, 0, 23, 161, 2, 133, 0, 99, 0, 2, 174, 0, 128, 222, 135, 1, ++ 247, 162, 1, 188, 96, 27, 24, 87, 162, 0, 224, 94, 138, 13, 176, 101, ++ 0, 176, 65, 151, 0, 20, 50, 0, 128, 222, 135, 0, 183, 162, 1, 188, 96, ++ 27, 21, 215, 162, 0, 224, 94, 138, 13, 176, 100, 0, 176, 65, 147, 0, ++ 20, 51, 0, 104, 216, 19, 0, 2, 188, 2, 0, 90, 27, 0, 2, 176, 1, 128, ++ 96, 6, 132, 244, 39, 3, 191, 222, 2, 240, 6, 196, 2, 1, 208, 3, 0, 2, ++ 176, 0, 176, 80, 155, 0, 20, 47, 2, 129, 208, 199, 0, 3, 104, 0, 2, ++ 94, 2, 240, 3, 110, 1, 11, 208, 3, 0, 23, 161, 1, 60, 80, 43, 0, 23, ++ 162, 1, 140, 94, 134, 244, 87, 161, 1, 72, 1, 67, 0, 23, 162, 1, 12, ++ 129, 67, 0, 23, 163, 0, 104, 94, 143, 0, 34, 185, 1, 140, 224, 0, 10, ++ 23, 162, 0, 104, 94, 134, 244, 66, 188, 1, 145, 96, 18, 132, 244, 39, ++ 3, 191, 222, 2, 240, 3, 107, 0, 2, 94, 2, 240, 1, 243, 0, 176, 80, 19, ++ 0, 16, 134, 0, 176, 80, 23, 0, 16, 138, 3, 162, 94, 2, 240, 3, 8, 2, ++ 12, 208, 3, 0, 2, 219, 2, 3, 0, 199, 0, 2, 218, 0, 176, 80, 203, 0, ++ 16, 101, 0, 2, 94, 2, 240, 22, 162, 2, 3, 80, 199, 0, 2, 200, 1, 188, ++ 96, 35, 0, 151, 161, 0, 168, 80, 2, 244, 52, 0, 3, 191, 222, 2, 240, ++ 2, 223, 2, 4, 129, 171, 0, 2, 202, 0, 109, 66, 70, 192, 128, 18, 0, ++ 176, 90, 19, 0, 23, 128, 0, 2, 94, 2, 240, 1, 77, 0, 176, 84, 15, 0, ++ 20, 30, 0, 176, 90, 7, 0, 23, 161, 0, 176, 90, 19, 0, 23, 128, 1, 135, ++ 90, 22, 240, 23, 128, 0, 176, 65, 143, 0, 16, 101, 0, 2, 94, 2, 240, ++ 22, 21, 0, 224, 94, 134, 160, 116, 3, 2, 135, 94, 3, 0, 2, 217, 1, 9, ++ 222, 3, 0, 23, 163, 0, 224, 94, 139, 0, 119, 162, 0, 224, 94, 138, 244, ++ 119, 162, 0, 136, 94, 139, 0, 55, 161, 0, 224, 94, 134, 244, 80, 137, ++ 3, 191, 222, 2, 240, 2, 223, 0, 109, 66, 74, 132, 128, 18, 1, 6, 80, ++ 7, 0, 23, 161, 2, 140, 208, 3, 0, 2, 222, 0, 104, 94, 135, 0, 2, 223, ++ 1, 130, 222, 134, 134, 52, 49, 1, 130, 96, 2, 134, 52, 49, 0, 32, 208, ++ 3, 4, 2, 229, 0, 176, 80, 79, 0, 17, 242, 0, 176, 80, 83, 0, 17, 243, ++ 0, 176, 80, 87, 0, 17, 244, 1, 188, 96, 3, 0, 145, 240, 2, 6, 1, 171, ++ 0, 3, 1, 2, 1, 80, 3, 0, 3, 1, 2, 6, 1, 171, 0, 3, 1, 3, 162, 94, 2, ++ 240, 3, 1, 2, 128, 48, 195, 0, 3, 1, 1, 128, 96, 5, 134, 12, 48, 0, ++ 224, 1, 231, 0, 32, 121, 1, 188, 96, 67, 8, 144, 230, 0, 2, 94, 2, 240, ++ 1, 106, 1, 188, 96, 3, 25, 16, 228, 1, 188, 96, 3, 0, 0, 6, 1, 188, ++ 96, 3, 1, 215, 130, 1, 210, 222, 8, 119, 240, 224, 0, 176, 15, 3, 0, ++ 16, 225, 0, 176, 0, 71, 0, 16, 134, 0, 176, 15, 31, 0, 16, 138, 1, 188, ++ 96, 3, 0, 55, 129, 0, 2, 94, 2, 240, 16, 105, 0, 176, 5, 155, 0, 16, ++ 100, 0, 232, 88, 26, 40, 241, 69, 0, 176, 5, 139, 0, 16, 100, 0, 106, ++ 69, 22, 192, 130, 252, 0, 2, 94, 2, 240, 16, 142, 0, 110, 69, 23, 0, ++ 66, 254, 1, 188, 96, 3, 0, 81, 69, 1, 188, 96, 3, 0, 16, 187, 1, 188, ++ 97, 3, 3, 176, 128, 3, 191, 222, 2, 240, 0, 18, 3, 148, 94, 2, 240, ++ 3, 8, 2, 6, 80, 3, 0, 3, 4, 2, 135, 222, 175, 0, 3, 8, 2, 129, 80, 3, ++ 0, 5, 224, 2, 2, 208, 199, 0, 3, 7, 2, 8, 80, 43, 0, 3, 8, 2, 133, 208, ++ 3, 0, 5, 247, 1, 144, 96, 18, 134, 52, 49, 1, 16, 80, 7, 0, 23, 166, ++ 0, 104, 222, 155, 0, 67, 20, 1, 58, 80, 7, 0, 23, 128, 0, 136, 94, 3, ++ 0, 119, 128, 0, 224, 0, 174, 240, 16, 100, 0, 176, 94, 7, 0, 8, 19, ++ 1, 188, 96, 35, 6, 215, 129, 0, 224, 65, 131, 1, 112, 99, 0, 224, 65, ++ 143, 0, 176, 101, 0, 2, 94, 2, 240, 16, 164, 0, 176, 32, 79, 0, 23, ++ 129, 3, 162, 94, 2, 240, 3, 32, 0, 176, 80, 15, 0, 17, 22, 2, 2, 208, ++ 199, 0, 3, 24, 0, 176, 80, 91, 0, 17, 22, 2, 130, 208, 3, 0, 3, 32, ++ 2, 129, 71, 195, 0, 3, 25, 2, 128, 80, 79, 0, 3, 30, 0, 32, 71, 199, ++ 63, 131, 32, 0, 32, 199, 219, 0, 195, 106, 3, 191, 222, 2, 240, 3, 32, ++ 3, 165, 94, 2, 240, 3, 32, 2, 128, 199, 223, 0, 3, 106, 2, 136, 80, ++ 199, 0, 3, 60, 1, 41, 80, 11, 0, 23, 146, 2, 3, 0, 199, 0, 3, 45, 2, ++ 12, 208, 3, 0, 3, 45, 2, 131, 80, 199, 0, 3, 45, 0, 176, 80, 203, 0, ++ 16, 101, 1, 56, 90, 19, 0, 23, 128, 1, 130, 90, 23, 0, 87, 129, 1, 14, ++ 90, 19, 0, 23, 161, 1, 142, 94, 134, 240, 55, 129, 2, 2, 208, 199, 0, ++ 3, 60, 0, 176, 80, 27, 0, 16, 138, 3, 191, 222, 2, 240, 3, 60, 2, 130, ++ 208, 199, 0, 3, 52, 1, 56, 80, 39, 0, 23, 128, 1, 8, 80, 19, 0, 23, ++ 129, 1, 2, 80, 19, 0, 23, 161, 1, 130, 94, 134, 240, 55, 129, 0, 176, ++ 80, 127, 0, 16, 137, 3, 191, 222, 2, 240, 3, 60, 1, 56, 80, 111, 0, ++ 23, 128, 1, 8, 80, 43, 0, 23, 129, 1, 6, 208, 7, 0, 23, 161, 1, 130, ++ 94, 134, 240, 55, 129, 0, 176, 80, 27, 0, 16, 138, 0, 176, 80, 131, ++ 0, 16, 137, 1, 14, 80, 115, 0, 23, 161, 1, 142, 94, 134, 240, 55, 129, ++ 0, 2, 94, 2, 240, 1, 67, 0, 2, 94, 2, 240, 16, 105, 1, 2, 66, 27, 0, ++ 23, 129, 1, 130, 94, 5, 2, 55, 129, 0, 2, 94, 2, 240, 16, 125, 2, 6, ++ 128, 199, 0, 3, 72, 1, 12, 129, 67, 0, 23, 166, 0, 104, 222, 155, 0, ++ 99, 70, 0, 136, 94, 135, 0, 87, 161, 3, 191, 222, 2, 240, 3, 72, 0, ++ 104, 222, 155, 0, 67, 72, 0, 136, 94, 135, 0, 55, 161, 0, 224, 94, 132, ++ 1, 23, 161, 1, 217, 222, 135, 0, 16, 131, 1, 188, 97, 55, 3, 183, 145, ++ 0, 104, 94, 75, 2, 131, 124, 2, 4, 0, 191, 0, 3, 79, 2, 135, 80, 3, ++ 0, 3, 79, 3, 148, 94, 2, 240, 3, 80, 3, 34, 94, 2, 240, 3, 93, 2, 6, ++ 129, 171, 0, 3, 91, 0, 104, 94, 75, 4, 67, 84, 0, 104, 94, 75, 0, 67, ++ 84, 3, 191, 222, 2, 240, 3, 91, 0, 224, 1, 239, 0, 32, 123, 1, 188, ++ 96, 3, 2, 145, 69, 1, 131, 96, 5, 134, 12, 48, 0, 224, 68, 103, 10, ++ 12, 52, 1, 140, 96, 14, 23, 112, 187, 1, 188, 97, 3, 2, 48, 128, 3, ++ 191, 222, 2, 240, 0, 2, 1, 188, 97, 3, 0, 48, 128, 3, 191, 222, 2, 240, ++ 0, 2, 1, 188, 97, 51, 3, 183, 145, 2, 133, 0, 99, 0, 3, 99, 0, 144, ++ 0, 99, 0, 151, 161, 0, 224, 100, 130, 244, 48, 101, 0, 110, 90, 19, ++ 0, 35, 99, 1, 136, 224, 6, 242, 55, 145, 2, 6, 1, 171, 0, 3, 103, 0, ++ 104, 222, 75, 5, 163, 103, 1, 188, 97, 3, 0, 48, 128, 3, 191, 222, 2, ++ 240, 0, 2, 3, 191, 222, 2, 240, 3, 124, 1, 145, 96, 14, 132, 244, 39, ++ 3, 191, 222, 2, 240, 3, 107, 1, 145, 96, 6, 132, 244, 39, 1, 188, 96, ++ 3, 0, 16, 180, 1, 129, 224, 6, 134, 52, 49, 3, 191, 222, 2, 240, 6, ++ 196, 1, 28, 80, 143, 0, 23, 161, 0, 128, 222, 135, 1, 151, 162, 0, 224, ++ 1, 94, 13, 176, 101, 2, 128, 90, 127, 0, 3, 123, 2, 129, 90, 127, 0, ++ 3, 119, 2, 3, 218, 127, 0, 3, 123, 0, 104, 90, 135, 0, 3, 123, 0, 136, ++ 96, 6, 244, 55, 161, 0, 32, 28, 186, 244, 35, 123, 0, 2, 94, 2, 240, ++ 13, 40, 1, 145, 96, 30, 132, 244, 39, 0, 1, 94, 2, 240, 0, 0, 3, 191, ++ 222, 2, 240, 3, 107, 0, 2, 222, 2, 240, 0, 0, 3, 196, 222, 2, 240, 13, ++ 115, 2, 6, 80, 3, 0, 3, 132, 2, 7, 222, 175, 0, 3, 132, 1, 188, 97, ++ 3, 0, 55, 145, 2, 7, 80, 3, 0, 3, 130, 1, 188, 98, 3, 0, 247, 145, 0, ++ 224, 1, 11, 0, 32, 66, 3, 191, 222, 2, 240, 3, 133, 1, 188, 96, 3, 0, ++ 32, 66, 0, 176, 94, 71, 0, 16, 128, 2, 4, 0, 191, 0, 3, 141, 0, 176, ++ 5, 139, 0, 16, 100, 0, 110, 69, 23, 0, 0, 2, 0, 104, 222, 75, 2, 131, ++ 140, 0, 160, 68, 180, 42, 49, 69, 3, 191, 222, 2, 240, 0, 2, 0, 2, 94, ++ 2, 240, 16, 142, 0, 104, 197, 23, 0, 0, 2, 3, 208, 94, 2, 240, 3, 145, ++ 0, 2, 94, 2, 240, 16, 142, 3, 191, 222, 2, 240, 0, 2, 2, 6, 1, 171, ++ 0, 3, 148, 0, 104, 222, 75, 5, 163, 148, 1, 128, 96, 1, 134, 12, 48, ++ 2, 14, 1, 171, 0, 3, 151, 2, 0, 176, 195, 0, 3, 151, 1, 129, 96, 5, ++ 134, 12, 48, 0, 225, 13, 178, 40, 227, 108, 0, 224, 141, 183, 0, 3, ++ 109, 1, 131, 96, 2, 247, 247, 191, 1, 188, 96, 3, 0, 144, 4, 0, 168, ++ 65, 35, 48, 16, 72, 1, 188, 98, 15, 0, 17, 224, 1, 129, 96, 2, 245, ++ 215, 174, 2, 2, 0, 191, 0, 3, 188, 0, 104, 222, 75, 2, 3, 161, 0, 2, ++ 94, 2, 240, 23, 200, 0, 104, 222, 75, 6, 35, 188, 2, 4, 94, 179, 0, ++ 3, 188, 2, 6, 171, 211, 0, 3, 166, 2, 4, 197, 175, 0, 3, 188, 3, 191, ++ 222, 2, 240, 3, 167, 2, 0, 69, 111, 0, 3, 188, 0, 232, 68, 101, 86, ++ 55, 161, 0, 232, 42, 150, 244, 55, 161, 0, 105, 94, 135, 8, 35, 188, ++ 2, 6, 171, 211, 0, 3, 175, 0, 107, 172, 66, 35, 35, 174, 0, 224, 68, ++ 103, 1, 75, 16, 1, 131, 224, 2, 43, 145, 92, 3, 191, 222, 2, 240, 3, ++ 188, 1, 131, 224, 2, 43, 145, 92, 2, 7, 1, 171, 0, 3, 178, 1, 128, 224, ++ 2, 9, 208, 78, 1, 188, 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, 24, 0, ++ 1, 131, 96, 2, 47, 49, 121, 2, 7, 222, 179, 0, 3, 185, 1, 135, 224, ++ 2, 245, 151, 172, 0, 225, 14, 219, 0, 35, 182, 0, 224, 142, 223, 0, ++ 3, 183, 0, 104, 176, 55, 0, 3, 188, 0, 176, 68, 103, 0, 12, 13, 0, 176, ++ 68, 107, 0, 12, 14, 1, 135, 224, 2, 245, 119, 171, 0, 104, 129, 11, ++ 0, 35, 191, 0, 176, 68, 103, 0, 0, 67, 1, 130, 224, 6, 9, 16, 72, 0, ++ 168, 65, 179, 16, 144, 108, 1, 130, 96, 6, 40, 145, 68, 1, 136, 224, ++ 2, 11, 144, 92, 0, 2, 94, 2, 240, 18, 47, 1, 133, 224, 2, 247, 247, ++ 191, 2, 136, 66, 27, 0, 3, 199, 1, 133, 224, 6, 247, 247, 191, 3, 91, ++ 94, 2, 240, 3, 201, 1, 188, 96, 19, 0, 16, 67, 1, 188, 96, 3, 0, 16, ++ 133, 1, 188, 96, 3, 0, 16, 184, 0, 136, 80, 119, 0, 144, 185, 2, 8, ++ 80, 43, 0, 3, 208, 1, 56, 80, 115, 0, 23, 161, 1, 124, 80, 110, 244, ++ 55, 161, 0, 136, 94, 135, 0, 144, 185, 2, 0, 71, 163, 0, 3, 212, 1, ++ 188, 96, 3, 0, 17, 234, 0, 144, 66, 231, 0, 145, 235, 0, 176, 71, 163, ++ 0, 209, 232, 2, 0, 71, 179, 0, 3, 214, 1, 176, 224, 142, 61, 145, 236, ++ 1, 210, 224, 2, 16, 144, 132, 3, 169, 94, 2, 240, 5, 1, 1, 188, 96, ++ 3, 0, 16, 132, 0, 224, 1, 195, 0, 32, 112, 0, 176, 68, 103, 0, 12, 4, ++ 0, 176, 68, 107, 0, 12, 5, 3, 32, 222, 2, 240, 4, 79, 0, 104, 94, 75, ++ 24, 163, 231, 0, 104, 222, 75, 7, 131, 240, 1, 188, 99, 255, 31, 112, ++ 132, 1, 188, 96, 3, 0, 240, 133, 1, 56, 19, 99, 0, 16, 181, 0, 224, ++ 66, 215, 0, 208, 181, 1, 188, 96, 3, 0, 16, 166, 1, 188, 96, 35, 20, ++ 208, 180, 0, 224, 19, 87, 0, 36, 213, 3, 191, 222, 2, 240, 4, 151, 1, ++ 132, 224, 6, 245, 151, 172, 1, 188, 96, 255, 31, 240, 132, 0, 2, 94, ++ 2, 240, 4, 44, 1, 188, 96, 3, 0, 16, 180, 1, 188, 96, 3, 0, 16, 166, ++ 1, 188, 96, 3, 2, 208, 181, 1, 188, 96, 35, 4, 208, 180, 0, 224, 19, ++ 91, 0, 36, 214, 3, 191, 222, 2, 240, 4, 151, 1, 129, 96, 6, 245, 183, ++ 173, 0, 104, 222, 75, 4, 164, 3, 2, 3, 222, 187, 0, 3, 245, 0, 224, ++ 45, 231, 0, 16, 101, 3, 191, 222, 2, 240, 3, 246, 1, 188, 96, 35, 1, ++ 16, 101, 0, 160, 94, 127, 254, 16, 236, 0, 176, 90, 3, 0, 16, 237, 0, ++ 176, 90, 7, 0, 16, 238, 0, 176, 90, 11, 0, 16, 239, 0, 176, 90, 15, ++ 0, 16, 240, 1, 188, 99, 255, 30, 240, 132, 1, 188, 96, 3, 0, 48, 133, ++ 1, 188, 96, 3, 0, 16, 180, 1, 188, 96, 3, 1, 208, 166, 1, 188, 96, 3, ++ 4, 80, 181, 1, 188, 96, 35, 4, 208, 180, 0, 224, 2, 175, 0, 32, 171, ++ 3, 191, 222, 2, 240, 4, 151, 1, 188, 97, 255, 31, 240, 132, 1, 188, ++ 96, 3, 0, 16, 133, 0, 104, 222, 75, 5, 36, 11, 1, 188, 96, 3, 0, 16, ++ 180, 1, 188, 96, 7, 19, 80, 166, 1, 188, 96, 3, 2, 208, 181, 1, 188, ++ 96, 35, 4, 208, 180, 3, 191, 222, 2, 240, 4, 23, 0, 104, 222, 75, 2, ++ 68, 34, 0, 176, 48, 67, 0, 16, 132, 2, 133, 195, 143, 0, 4, 15, 0, 224, ++ 94, 39, 0, 55, 137, 1, 218, 94, 39, 0, 16, 238, 1, 188, 99, 255, 31, ++ 240, 206, 1, 188, 96, 3, 0, 16, 180, 0, 128, 224, 33, 129, 248, 0, 0, ++ 224, 102, 130, 13, 176, 166, 1, 188, 96, 3, 3, 208, 181, 1, 188, 96, ++ 35, 4, 208, 180, 0, 224, 1, 211, 0, 32, 116, 1, 132, 96, 7, 0, 17, 224, ++ 2, 130, 222, 179, 0, 5, 192, 2, 4, 94, 179, 0, 5, 192, 1, 129, 224, ++ 6, 245, 215, 174, 1, 131, 224, 6, 9, 16, 72, 0, 176, 65, 35, 0, 24, ++ 0, 1, 188, 96, 3, 6, 183, 142, 1, 136, 32, 70, 16, 215, 129, 0, 2, 94, ++ 2, 240, 16, 125, 0, 136, 94, 135, 0, 112, 131, 3, 191, 222, 2, 240, ++ 5, 192, 1, 188, 96, 3, 31, 240, 132, 1, 3, 222, 83, 0, 23, 162, 0, 104, ++ 14, 207, 0, 4, 39, 0, 176, 14, 207, 0, 23, 162, 0, 144, 28, 186, 244, ++ 87, 162, 2, 0, 94, 255, 0, 4, 41, 1, 188, 96, 3, 0, 55, 162, 0, 104, ++ 43, 79, 0, 4, 43, 1, 188, 96, 3, 0, 55, 162, 1, 134, 94, 138, 28, 112, ++ 227, 0, 106, 195, 147, 0, 4, 53, 0, 232, 67, 144, 0, 208, 228, 2, 2, ++ 66, 27, 0, 4, 51, 0, 144, 0, 27, 0, 55, 161, 0, 32, 66, 27, 0, 68, 50, ++ 0, 176, 32, 151, 0, 23, 161, 0, 224, 67, 146, 244, 48, 228, 0, 105, ++ 195, 147, 0, 4, 53, 1, 188, 96, 3, 0, 16, 228, 0, 104, 43, 79, 0, 4, ++ 55, 0, 224, 67, 145, 91, 48, 228, 1, 188, 96, 3, 0, 16, 180, 1, 188, ++ 96, 3, 0, 16, 166, 1, 188, 96, 3, 2, 16, 181, 1, 188, 96, 35, 4, 208, ++ 180, 0, 104, 94, 75, 6, 164, 77, 0, 224, 1, 203, 0, 32, 114, 2, 6, 129, ++ 171, 0, 4, 151, 2, 128, 176, 195, 0, 4, 151, 2, 3, 176, 195, 0, 4, 151, ++ 1, 188, 96, 7, 4, 247, 166, 2, 136, 66, 27, 0, 4, 69, 1, 188, 96, 15, ++ 0, 23, 166, 2, 130, 66, 27, 0, 4, 69, 1, 188, 96, 23, 0, 23, 166, 1, ++ 12, 129, 67, 0, 23, 165, 0, 104, 222, 151, 0, 100, 72, 0, 136, 94, 155, ++ 0, 55, 166, 0, 224, 68, 102, 244, 204, 51, 1, 129, 224, 5, 134, 12, ++ 48, 1, 130, 96, 5, 134, 12, 48, 1, 131, 224, 1, 134, 12, 48, 3, 191, ++ 222, 2, 240, 4, 151, 0, 224, 1, 207, 0, 32, 115, 3, 191, 222, 2, 240, ++ 4, 151, 3, 32, 94, 2, 240, 4, 158, 1, 129, 224, 2, 9, 16, 72, 0, 224, ++ 1, 215, 0, 32, 117, 3, 30, 222, 2, 240, 4, 126, 1, 188, 96, 3, 0, 23, ++ 162, 0, 106, 94, 35, 0, 4, 87, 1, 2, 66, 143, 0, 23, 162, 1, 133, 94, ++ 138, 9, 16, 72, 1, 128, 224, 6, 16, 48, 129, 2, 132, 222, 83, 0, 4, ++ 94, 0, 176, 0, 119, 0, 23, 161, 0, 224, 94, 132, 4, 55, 161, 0, 136, ++ 94, 135, 0, 87, 161, 0, 224, 94, 135, 13, 87, 161, 3, 191, 222, 2, 240, ++ 4, 95, 1, 188, 96, 3, 13, 87, 161, 0, 104, 0, 39, 0, 4, 126, 0, 224, ++ 94, 132, 1, 247, 161, 1, 188, 96, 35, 0, 144, 101, 0, 136, 65, 151, ++ 0, 48, 182, 1, 188, 96, 3, 0, 16, 180, 0, 144, 94, 135, 0, 80, 166, ++ 1, 188, 96, 3, 1, 16, 181, 1, 188, 96, 35, 0, 176, 180, 3, 23, 222, ++ 2, 240, 4, 103, 3, 151, 222, 2, 240, 4, 104, 0, 32, 222, 135, 0, 68, ++ 113, 0, 32, 222, 135, 0, 36, 110, 1, 184, 94, 34, 208, 22, 128, 1, 128, ++ 94, 138, 208, 54, 129, 3, 191, 222, 2, 240, 4, 119, 1, 188, 94, 34, ++ 208, 22, 128, 1, 132, 94, 138, 208, 54, 129, 3, 191, 222, 2, 240, 4, ++ 119, 0, 32, 222, 135, 0, 36, 117, 1, 184, 94, 34, 208, 54, 129, 1, 128, ++ 94, 138, 208, 86, 130, 3, 191, 222, 2, 240, 4, 119, 1, 188, 94, 34, ++ 208, 54, 129, 1, 132, 94, 138, 208, 86, 130, 1, 136, 96, 2, 244, 48, ++ 168, 0, 176, 90, 3, 0, 16, 176, 0, 176, 90, 7, 0, 16, 177, 2, 128, 66, ++ 163, 0, 4, 122, 0, 224, 66, 163, 0, 144, 168, 0, 176, 90, 11, 0, 16, ++ 176, 0, 176, 90, 15, 0, 16, 177, 1, 135, 96, 6, 16, 144, 132, 0, 224, ++ 94, 39, 0, 55, 137, 1, 218, 94, 39, 0, 16, 238, 1, 188, 96, 3, 0, 16, ++ 180, 1, 188, 96, 3, 3, 80, 166, 0, 176, 0, 51, 0, 16, 181, 2, 132, 222, ++ 83, 0, 4, 136, 0, 224, 96, 104, 3, 176, 166, 0, 224, 66, 152, 4, 48, ++ 166, 0, 176, 0, 55, 0, 16, 181, 1, 188, 96, 35, 4, 208, 180, 1, 132, ++ 96, 6, 242, 151, 148, 1, 134, 96, 2, 9, 16, 72, 3, 158, 222, 2, 240, ++ 4, 146, 2, 128, 68, 31, 0, 4, 149, 0, 176, 94, 63, 0, 17, 69, 1, 188, ++ 96, 3, 0, 23, 143, 0, 176, 94, 67, 0, 23, 133, 0, 176, 94, 15, 0, 23, ++ 144, 3, 191, 222, 2, 240, 4, 149, 0, 176, 94, 15, 0, 23, 133, 2, 128, ++ 68, 31, 0, 4, 149, 0, 160, 68, 182, 240, 177, 69, 1, 188, 96, 3, 1, ++ 16, 66, 1, 131, 96, 6, 242, 151, 148, 1, 132, 96, 7, 0, 17, 224, 3, ++ 160, 94, 2, 240, 5, 190, 2, 6, 94, 175, 0, 5, 192, 1, 134, 224, 6, 245, ++ 119, 171, 1, 188, 96, 3, 0, 16, 128, 0, 2, 94, 2, 240, 13, 48, 3, 191, ++ 222, 2, 240, 7, 33, 3, 161, 94, 2, 240, 5, 43, 1, 20, 0, 99, 0, 23, ++ 161, 0, 104, 222, 135, 0, 228, 163, 1, 129, 96, 6, 9, 16, 72, 3, 191, ++ 222, 2, 240, 5, 43, 2, 133, 0, 99, 0, 4, 165, 1, 131, 224, 6, 13, 144, ++ 108, 1, 129, 96, 6, 245, 215, 174, 1, 28, 80, 143, 0, 3, 189, 2, 6, ++ 80, 143, 0, 4, 173, 0, 176, 68, 103, 0, 16, 243, 0, 176, 68, 107, 0, ++ 16, 244, 1, 188, 99, 255, 31, 240, 211, 1, 188, 99, 255, 31, 240, 212, ++ 0, 176, 66, 23, 3, 16, 133, 0, 32, 96, 14, 134, 36, 212, 1, 135, 96, ++ 4, 3, 16, 160, 0, 176, 0, 99, 0, 16, 180, 1, 188, 96, 3, 11, 16, 181, ++ 0, 176, 0, 99, 0, 240, 180, 2, 3, 0, 199, 0, 4, 191, 2, 12, 208, 3, ++ 0, 4, 191, 2, 128, 80, 199, 0, 4, 183, 0, 176, 84, 19, 0, 23, 161, 0, ++ 224, 94, 134, 128, 116, 26, 0, 176, 80, 107, 0, 16, 228, 0, 176, 66, ++ 19, 2, 16, 132, 2, 9, 80, 43, 0, 4, 191, 0, 176, 66, 19, 0, 48, 132, ++ 1, 210, 224, 58, 160, 48, 224, 2, 128, 80, 199, 0, 4, 197, 1, 210, 224, ++ 82, 160, 48, 224, 3, 191, 222, 2, 240, 4, 197, 2, 2, 208, 199, 0, 4, ++ 197, 0, 176, 80, 95, 0, 16, 224, 0, 176, 80, 99, 0, 16, 225, 0, 176, ++ 80, 103, 0, 16, 226, 0, 176, 80, 107, 0, 16, 228, 0, 176, 66, 19, 2, ++ 240, 132, 2, 0, 80, 199, 0, 4, 207, 1, 138, 224, 14, 16, 144, 132, 1, ++ 188, 96, 251, 28, 16, 229, 1, 188, 96, 3, 8, 144, 230, 0, 176, 0, 99, ++ 0, 16, 180, 1, 188, 96, 3, 2, 16, 181, 0, 176, 0, 99, 4, 208, 180, 1, ++ 132, 96, 7, 0, 17, 224, 1, 188, 96, 3, 0, 23, 142, 3, 191, 222, 2, 240, ++ 5, 203, 0, 224, 1, 199, 0, 32, 113, 0, 176, 0, 99, 0, 16, 180, 1, 188, ++ 96, 3, 2, 208, 181, 0, 176, 0, 99, 4, 208, 180, 3, 191, 222, 2, 240, ++ 5, 88, 3, 34, 94, 2, 240, 4, 214, 0, 224, 2, 167, 0, 32, 169, 1, 3, ++ 80, 3, 0, 23, 161, 0, 184, 94, 135, 0, 55, 161, 1, 135, 94, 134, 16, ++ 16, 128, 2, 4, 0, 191, 0, 4, 228, 3, 43, 222, 2, 240, 4, 228, 2, 0, ++ 0, 243, 0, 4, 222, 0, 232, 0, 35, 0, 81, 66, 1, 188, 96, 10, 40, 81, ++ 66, 3, 148, 94, 2, 240, 4, 228, 0, 176, 5, 139, 0, 16, 100, 0, 224, ++ 88, 35, 0, 54, 8, 0, 104, 88, 3, 0, 4, 228, 0, 176, 68, 103, 0, 17, ++ 18, 0, 176, 88, 3, 0, 17, 21, 2, 12, 208, 3, 0, 5, 42, 2, 3, 0, 199, ++ 0, 4, 247, 0, 176, 80, 203, 0, 16, 101, 1, 188, 96, 3, 0, 22, 133, 0, ++ 224, 90, 51, 0, 54, 140, 2, 3, 80, 199, 0, 4, 236, 0, 224, 90, 39, 0, ++ 54, 137, 3, 191, 222, 2, 240, 5, 43, 1, 188, 96, 3, 0, 23, 178, 0, 176, ++ 90, 11, 0, 11, 122, 1, 56, 90, 19, 0, 23, 161, 1, 188, 90, 6, 244, 48, ++ 224, 1, 60, 90, 19, 0, 23, 161, 1, 124, 90, 6, 244, 48, 225, 1, 129, ++ 224, 6, 16, 144, 132, 1, 133, 224, 7, 0, 16, 227, 1, 133, 224, 7, 0, ++ 16, 195, 2, 130, 208, 199, 0, 4, 252, 3, 191, 222, 2, 240, 4, 255, 2, ++ 2, 208, 199, 0, 5, 1, 0, 176, 42, 51, 0, 23, 161, 1, 184, 80, 110, 244, ++ 48, 224, 0, 176, 80, 115, 0, 23, 161, 1, 184, 42, 54, 244, 48, 225, ++ 2, 130, 66, 19, 0, 4, 255, 0, 176, 80, 123, 0, 16, 228, 0, 176, 66, ++ 19, 2, 16, 132, 1, 133, 224, 6, 28, 48, 225, 0, 176, 66, 19, 0, 112, ++ 132, 1, 135, 96, 4, 3, 16, 160, 2, 3, 0, 199, 0, 5, 23, 0, 176, 80, ++ 203, 0, 16, 101, 0, 109, 94, 202, 209, 197, 7, 1, 133, 224, 2, 24, 112, ++ 195, 0, 224, 94, 203, 0, 54, 142, 1, 188, 96, 27, 31, 208, 101, 0, 224, ++ 65, 150, 246, 80, 101, 0, 176, 80, 151, 0, 22, 128, 0, 104, 222, 203, ++ 0, 5, 15, 1, 188, 96, 35, 1, 80, 184, 0, 224, 1, 243, 0, 32, 124, 0, ++ 104, 45, 235, 0, 37, 21, 3, 191, 222, 2, 240, 5, 34, 0, 176, 94, 203, ++ 0, 16, 181, 0, 176, 0, 99, 8, 112, 180, 2, 131, 66, 211, 0, 5, 17, 1, ++ 188, 96, 3, 1, 112, 184, 0, 104, 173, 235, 0, 37, 34, 1, 188, 96, 3, ++ 1, 112, 184, 2, 188, 80, 103, 0, 5, 33, 3, 191, 222, 2, 240, 5, 32, ++ 1, 12, 208, 3, 0, 23, 161, 3, 169, 94, 2, 240, 5, 29, 1, 188, 96, 35, ++ 1, 80, 184, 0, 224, 1, 243, 0, 32, 124, 0, 104, 94, 135, 0, 101, 32, ++ 3, 191, 222, 2, 240, 5, 34, 1, 188, 96, 3, 1, 112, 184, 0, 104, 94, ++ 135, 0, 69, 34, 1, 188, 96, 3, 1, 112, 184, 1, 129, 224, 2, 23, 16, ++ 184, 1, 188, 96, 3, 0, 240, 165, 1, 188, 96, 3, 14, 16, 181, 0, 224, ++ 1, 247, 0, 32, 125, 0, 176, 0, 99, 0, 16, 180, 0, 176, 0, 99, 0, 240, ++ 180, 0, 176, 66, 211, 0, 24, 0, 1, 136, 96, 8, 3, 16, 180, 1, 129, 96, ++ 6, 13, 144, 108, 3, 191, 222, 2, 240, 5, 88, 2, 2, 208, 199, 0, 5, 49, ++ 0, 176, 80, 111, 0, 16, 224, 0, 176, 80, 115, 0, 16, 225, 0, 176, 80, ++ 119, 0, 16, 226, 2, 130, 66, 19, 0, 5, 48, 0, 176, 80, 123, 0, 16, 228, ++ 0, 176, 66, 19, 2, 240, 132, 0, 224, 94, 159, 0, 55, 167, 3, 161, 94, ++ 2, 240, 5, 58, 1, 188, 96, 3, 0, 23, 167, 1, 135, 96, 4, 3, 16, 160, ++ 0, 176, 0, 99, 0, 16, 180, 1, 188, 96, 3, 14, 16, 181, 0, 176, 0, 99, ++ 0, 240, 180, 1, 136, 96, 8, 3, 16, 180, 3, 191, 222, 2, 240, 5, 77, ++ 0, 176, 1, 123, 0, 16, 101, 0, 176, 90, 3, 0, 16, 229, 0, 176, 90, 7, ++ 0, 16, 230, 0, 176, 90, 11, 0, 16, 231, 0, 104, 160, 75, 0, 5, 64, 0, ++ 224, 94, 39, 0, 55, 137, 0, 104, 32, 75, 0, 5, 68, 1, 133, 224, 7, 0, ++ 16, 227, 1, 133, 224, 7, 0, 16, 195, 0, 176, 66, 19, 1, 16, 132, 1, ++ 218, 94, 39, 0, 16, 238, 1, 135, 96, 6, 16, 144, 132, 0, 176, 66, 19, ++ 28, 16, 132, 1, 188, 96, 3, 0, 16, 180, 0, 224, 96, 104, 3, 176, 166, ++ 0, 176, 0, 151, 0, 16, 181, 1, 188, 96, 35, 4, 208, 180, 1, 132, 96, ++ 7, 0, 17, 224, 3, 191, 222, 2, 240, 5, 173, 1, 8, 94, 75, 0, 23, 161, ++ 0, 104, 94, 135, 0, 37, 88, 2, 2, 80, 3, 0, 5, 87, 2, 158, 80, 159, ++ 0, 5, 84, 2, 1, 208, 3, 0, 5, 84, 0, 224, 94, 39, 0, 55, 137, 1, 88, ++ 94, 39, 0, 20, 45, 1, 218, 80, 183, 0, 16, 238, 1, 135, 96, 6, 16, 144, ++ 132, 3, 191, 222, 2, 240, 5, 88, 1, 188, 96, 3, 0, 20, 45, 1, 4, 193, ++ 7, 0, 23, 161, 0, 104, 14, 247, 0, 5, 93, 0, 176, 14, 247, 0, 23, 161, ++ 0, 144, 28, 186, 244, 55, 161, 3, 191, 222, 2, 240, 5, 95, 3, 34, 94, ++ 2, 240, 5, 95, 1, 3, 222, 83, 0, 23, 161, 0, 176, 94, 135, 0, 23, 162, ++ 2, 0, 94, 255, 0, 5, 98, 1, 188, 96, 3, 0, 55, 162, 0, 104, 43, 79, ++ 0, 5, 100, 1, 188, 96, 3, 0, 55, 162, 2, 136, 94, 75, 0, 5, 103, 0, ++ 104, 94, 75, 6, 133, 103, 1, 188, 96, 3, 0, 23, 162, 0, 104, 142, 247, ++ 0, 5, 105, 1, 131, 222, 134, 242, 151, 148, 1, 131, 222, 134, 132, 244, ++ 39, 2, 129, 194, 19, 0, 5, 111, 1, 134, 94, 139, 0, 16, 227, 1, 134, ++ 96, 7, 0, 16, 195, 1, 129, 224, 6, 16, 144, 132, 3, 191, 222, 2, 240, ++ 5, 113, 1, 134, 94, 138, 28, 112, 227, 1, 134, 96, 6, 24, 112, 195, ++ 2, 184, 71, 167, 0, 5, 169, 2, 160, 71, 183, 0, 5, 171, 3, 169, 94, ++ 2, 240, 5, 121, 1, 8, 94, 75, 0, 23, 161, 0, 104, 94, 135, 0, 37, 170, ++ 2, 30, 80, 159, 0, 5, 121, 1, 133, 224, 6, 28, 112, 227, 1, 133, 224, ++ 6, 24, 112, 195, 1, 20, 0, 99, 0, 23, 161, 0, 104, 222, 135, 0, 133, ++ 130, 0, 176, 1, 83, 0, 23, 162, 0, 104, 222, 139, 255, 229, 126, 0, ++ 104, 66, 71, 0, 37, 127, 0, 104, 222, 138, 132, 197, 130, 1, 133, 96, ++ 2, 9, 16, 72, 1, 134, 224, 2, 28, 112, 227, 1, 134, 224, 6, 24, 112, ++ 195, 1, 16, 80, 7, 0, 23, 166, 0, 104, 94, 155, 0, 5, 170, 1, 188, 96, ++ 3, 0, 17, 228, 1, 58, 80, 7, 0, 23, 128, 0, 136, 94, 3, 0, 119, 128, ++ 0, 224, 0, 174, 240, 16, 100, 0, 104, 222, 155, 0, 69, 143, 2, 7, 208, ++ 3, 0, 5, 141, 1, 188, 96, 43, 17, 247, 162, 0, 224, 94, 0, 11, 55, 163, ++ 0, 2, 94, 2, 240, 16, 207, 1, 188, 96, 35, 6, 144, 100, 1, 188, 96, ++ 71, 0, 23, 162, 0, 2, 94, 2, 240, 16, 247, 0, 104, 94, 155, 0, 69, 171, ++ 1, 164, 96, 70, 244, 113, 224, 0, 104, 222, 155, 0, 197, 157, 1, 188, ++ 97, 19, 0, 183, 161, 2, 6, 0, 243, 0, 5, 150, 1, 188, 96, 19, 0, 183, ++ 161, 1, 146, 194, 26, 244, 55, 162, 3, 41, 94, 2, 240, 5, 155, 1, 188, ++ 96, 3, 0, 17, 238, 0, 144, 66, 231, 0, 145, 239, 1, 146, 224, 14, 244, ++ 55, 162, 0, 176, 94, 139, 0, 17, 236, 3, 191, 222, 2, 240, 5, 171, 0, ++ 104, 94, 155, 0, 101, 162, 0, 104, 94, 155, 0, 165, 162, 0, 176, 80, ++ 47, 0, 17, 226, 0, 176, 80, 51, 0, 17, 226, 3, 191, 222, 2, 240, 5, ++ 171, 1, 135, 96, 2, 61, 17, 232, 0, 104, 222, 155, 0, 165, 165, 1, 135, ++ 96, 6, 61, 17, 232, 1, 188, 96, 3, 0, 17, 234, 0, 144, 66, 231, 0, 145, ++ 235, 1, 146, 194, 27, 0, 183, 162, 1, 184, 94, 138, 61, 17, 232, 3, ++ 191, 222, 2, 240, 5, 171, 1, 132, 96, 7, 0, 17, 224, 1, 188, 96, 3, ++ 0, 17, 45, 0, 176, 68, 131, 0, 20, 44, 3, 163, 222, 2, 240, 5, 193, ++ 1, 188, 96, 3, 0, 23, 142, 0, 104, 94, 75, 5, 165, 177, 2, 0, 80, 3, ++ 0, 5, 187, 1, 131, 224, 6, 9, 16, 72, 0, 176, 65, 35, 0, 24, 0, 1, 188, ++ 96, 3, 6, 55, 142, 0, 104, 94, 75, 5, 165, 192, 0, 224, 2, 163, 0, 32, ++ 168, 1, 188, 96, 3, 4, 183, 142, 3, 169, 94, 2, 240, 5, 192, 0, 104, ++ 94, 75, 4, 37, 192, 1, 188, 96, 3, 6, 183, 142, 3, 191, 222, 2, 240, ++ 5, 192, 1, 129, 96, 6, 245, 119, 171, 0, 176, 94, 15, 0, 23, 133, 0, ++ 2, 94, 2, 240, 16, 142, 1, 188, 96, 3, 0, 23, 140, 1, 188, 96, 3, 0, ++ 23, 141, 3, 35, 222, 2, 240, 5, 203, 2, 6, 128, 199, 0, 5, 202, 1, 12, ++ 129, 67, 0, 23, 161, 0, 104, 222, 135, 0, 101, 202, 1, 8, 66, 27, 0, ++ 23, 161, 0, 104, 222, 135, 0, 5, 202, 1, 188, 96, 127, 31, 247, 161, ++ 1, 224, 94, 134, 16, 112, 131, 1, 130, 224, 5, 134, 12, 48, 0, 224, ++ 68, 103, 37, 140, 50, 1, 135, 224, 6, 16, 112, 131, 0, 109, 0, 167, ++ 0, 133, 221, 3, 41, 94, 2, 240, 5, 221, 2, 3, 0, 199, 0, 5, 218, 0, ++ 176, 80, 203, 0, 16, 101, 2, 130, 208, 199, 0, 5, 210, 0, 224, 90, 35, ++ 0, 54, 136, 3, 191, 222, 2, 240, 5, 211, 0, 224, 90, 39, 0, 54, 137, ++ 0, 104, 45, 235, 0, 37, 218, 0, 224, 94, 203, 0, 55, 178, 1, 10, 94, ++ 203, 0, 23, 161, 0, 224, 80, 202, 244, 48, 101, 0, 208, 96, 6, 246, ++ 87, 162, 0, 32, 90, 26, 244, 69, 218, 3, 191, 222, 2, 240, 5, 212, 0, ++ 2, 94, 2, 240, 18, 47, 3, 80, 222, 2, 240, 5, 218, 3, 191, 222, 2, 240, ++ 6, 65, 2, 5, 94, 175, 0, 5, 223, 1, 135, 224, 6, 38, 113, 51, 3, 191, ++ 222, 2, 240, 0, 2, 1, 144, 96, 10, 134, 52, 49, 2, 130, 208, 199, 0, ++ 5, 233, 1, 60, 80, 39, 0, 23, 128, 1, 9, 80, 43, 0, 23, 129, 1, 7, 80, ++ 7, 0, 23, 161, 1, 130, 94, 134, 240, 55, 129, 0, 176, 80, 31, 0, 16, ++ 138, 0, 176, 80, 15, 0, 17, 22, 3, 191, 222, 2, 240, 5, 239, 1, 56, ++ 80, 95, 0, 23, 128, 1, 10, 80, 43, 0, 23, 129, 1, 7, 208, 7, 0, 23, ++ 161, 1, 130, 94, 134, 240, 55, 129, 0, 176, 80, 35, 0, 16, 138, 0, 176, ++ 80, 91, 0, 17, 22, 2, 3, 0, 199, 0, 5, 244, 2, 12, 208, 3, 0, 5, 244, ++ 2, 8, 94, 7, 0, 5, 244, 1, 56, 84, 7, 0, 23, 128, 1, 144, 66, 42, 161, ++ 48, 138, 2, 128, 80, 199, 0, 5, 253, 1, 188, 96, 3, 5, 183, 146, 3, ++ 191, 222, 2, 240, 3, 24, 1, 144, 96, 6, 134, 52, 49, 2, 3, 0, 199, 0, ++ 5, 225, 2, 12, 208, 3, 0, 5, 225, 0, 176, 0, 31, 0, 23, 161, 0, 224, ++ 94, 134, 128, 116, 26, 3, 191, 222, 2, 240, 5, 225, 1, 188, 96, 3, 6, ++ 55, 146, 3, 191, 222, 2, 240, 3, 24, 0, 224, 19, 95, 0, 36, 215, 2, ++ 4, 222, 179, 0, 0, 2, 0, 176, 19, 11, 0, 16, 101, 1, 25, 152, 135, 0, ++ 23, 161, 1, 9, 90, 19, 0, 23, 162, 1, 137, 94, 134, 208, 150, 132, 0, ++ 176, 19, 7, 0, 23, 163, 0, 109, 222, 132, 152, 38, 8, 0, 176, 94, 135, ++ 0, 23, 163, 1, 136, 94, 142, 208, 150, 132, 0, 104, 222, 138, 244, 33, ++ 14, 1, 188, 99, 255, 31, 240, 208, 0, 176, 90, 19, 0, 16, 240, 1, 188, ++ 96, 3, 0, 23, 165, 1, 130, 94, 150, 30, 16, 240, 1, 188, 99, 255, 31, ++ 240, 207, 1, 188, 96, 27, 0, 240, 239, 1, 188, 99, 255, 31, 240, 209, ++ 0, 176, 68, 103, 0, 16, 241, 1, 188, 99, 255, 31, 240, 210, 0, 176, ++ 68, 107, 0, 16, 242, 1, 188, 96, 3, 4, 4, 216, 1, 188, 99, 255, 31, ++ 240, 195, 1, 188, 96, 3, 28, 16, 227, 1, 188, 99, 255, 31, 240, 196, ++ 0, 176, 82, 19, 0, 16, 228, 1, 188, 99, 255, 31, 240, 197, 0, 176, 82, ++ 47, 0, 16, 229, 1, 188, 99, 255, 31, 240, 198, 0, 176, 82, 51, 0, 16, ++ 230, 1, 188, 99, 255, 31, 240, 199, 0, 176, 82, 55, 0, 16, 231, 1, 188, ++ 99, 255, 31, 240, 200, 0, 176, 82, 23, 0, 16, 232, 1, 188, 99, 255, ++ 31, 240, 201, 0, 176, 82, 27, 0, 16, 233, 1, 188, 99, 255, 31, 240, ++ 202, 0, 176, 82, 31, 0, 16, 234, 1, 188, 99, 255, 31, 240, 203, 0, 176, ++ 19, 71, 0, 16, 235, 1, 188, 99, 255, 31, 240, 204, 0, 176, 19, 75, 0, ++ 16, 236, 1, 188, 99, 255, 31, 240, 205, 0, 176, 19, 79, 0, 16, 237, ++ 0, 176, 19, 103, 0, 16, 98, 1, 188, 96, 3, 0, 40, 17, 0, 2, 94, 2, 240, ++ 16, 109, 0, 2, 94, 2, 240, 13, 40, 1, 188, 96, 43, 24, 119, 161, 0, ++ 2, 94, 2, 240, 1, 39, 1, 96, 64, 103, 0, 17, 192, 0, 224, 64, 100, 155, ++ 23, 161, 0, 224, 94, 135, 0, 151, 161, 1, 188, 99, 255, 31, 240, 192, ++ 1, 188, 96, 3, 1, 85, 1, 1, 210, 222, 134, 160, 48, 224, 0, 144, 94, ++ 135, 1, 119, 161, 1, 188, 96, 3, 7, 151, 146, 1, 144, 96, 10, 9, 16, ++ 72, 3, 191, 222, 2, 240, 3, 80, 1, 188, 96, 7, 0, 17, 193, 1, 188, 96, ++ 43, 24, 23, 161, 1, 188, 96, 3, 0, 23, 162, 0, 2, 94, 2, 240, 1, 43, ++ 1, 188, 96, 3, 0, 17, 193, 0, 2, 222, 2, 240, 0, 0, 2, 1, 194, 227, ++ 0, 6, 105, 2, 3, 0, 199, 0, 6, 70, 0, 104, 45, 235, 0, 38, 86, 0, 110, ++ 66, 70, 246, 70, 86, 3, 191, 222, 2, 240, 6, 72, 0, 110, 66, 71, 0, ++ 38, 86, 2, 3, 0, 199, 0, 6, 83, 3, 85, 222, 2, 240, 6, 72, 1, 128, 96, ++ 2, 134, 20, 48, 1, 56, 80, 131, 0, 23, 161, 0, 176, 80, 203, 0, 16, ++ 101, 0, 109, 218, 50, 244, 44, 93, 0, 168, 65, 35, 20, 16, 72, 1, 20, ++ 0, 99, 0, 16, 101, 0, 224, 65, 151, 14, 208, 101, 0, 224, 90, 3, 0, ++ 54, 128, 1, 188, 98, 31, 0, 17, 224, 3, 191, 222, 2, 240, 0, 18, 1, ++ 129, 224, 6, 134, 52, 49, 1, 145, 96, 14, 132, 244, 39, 3, 191, 222, ++ 2, 240, 6, 105, 1, 60, 80, 103, 0, 23, 161, 1, 172, 94, 134, 23, 80, ++ 186, 1, 188, 96, 3, 1, 144, 184, 2, 3, 0, 199, 0, 6, 99, 0, 104, 173, ++ 235, 0, 38, 94, 1, 129, 224, 2, 23, 16, 184, 3, 80, 222, 2, 240, 6, ++ 92, 3, 191, 222, 2, 240, 6, 105, 0, 232, 45, 235, 0, 43, 122, 0, 176, ++ 94, 203, 0, 16, 181, 0, 176, 0, 99, 8, 112, 180, 2, 131, 66, 211, 0, ++ 6, 97, 3, 191, 222, 2, 240, 6, 100, 1, 134, 224, 4, 3, 16, 160, 0, 2, ++ 94, 2, 240, 1, 230, 3, 213, 222, 2, 240, 12, 93, 3, 214, 222, 2, 240, ++ 12, 117, 3, 80, 222, 2, 240, 6, 101, 3, 191, 222, 2, 240, 3, 199, 1, ++ 188, 96, 3, 0, 240, 165, 1, 130, 224, 2, 9, 16, 72, 1, 188, 98, 31, ++ 0, 17, 224, 1, 188, 96, 3, 0, 17, 236, 1, 188, 96, 15, 0, 17, 232, 2, ++ 133, 80, 11, 0, 6, 112, 1, 130, 96, 2, 9, 16, 72, 3, 160, 222, 2, 240, ++ 6, 116, 3, 213, 222, 2, 240, 12, 93, 3, 214, 222, 2, 240, 12, 117, 3, ++ 32, 94, 2, 240, 6, 122, 1, 136, 96, 2, 9, 16, 72, 1, 188, 96, 3, 0, ++ 8, 49, 0, 104, 94, 75, 24, 160, 2, 0, 104, 222, 75, 7, 134, 121, 0, ++ 2, 94, 2, 240, 6, 59, 3, 191, 222, 2, 240, 0, 18, 1, 188, 96, 3, 0, ++ 55, 161, 0, 2, 94, 2, 240, 14, 143, 3, 163, 222, 2, 240, 0, 18, 2, 0, ++ 80, 199, 0, 6, 134, 1, 188, 96, 3, 0, 16, 128, 1, 130, 96, 6, 9, 16, ++ 72, 1, 128, 96, 2, 134, 52, 49, 0, 104, 142, 247, 0, 6, 132, 1, 4, 193, ++ 7, 0, 23, 161, 1, 131, 222, 134, 242, 151, 148, 0, 224, 1, 203, 0, 32, ++ 114, 3, 191, 222, 2, 240, 2, 13, 0, 176, 1, 11, 0, 23, 161, 0, 109, ++ 222, 132, 8, 6, 196, 0, 232, 68, 100, 8, 119, 161, 0, 110, 94, 132, ++ 8, 38, 196, 1, 135, 224, 6, 245, 119, 171, 2, 2, 0, 191, 0, 6, 155, ++ 2, 136, 129, 171, 0, 6, 155, 2, 132, 0, 199, 0, 6, 155, 1, 41, 80, 11, ++ 0, 23, 161, 0, 104, 222, 135, 2, 6, 155, 2, 130, 222, 187, 0, 6, 155, ++ 2, 3, 197, 115, 0, 6, 154, 2, 131, 222, 179, 0, 6, 154, 2, 134, 171, ++ 211, 0, 6, 150, 2, 130, 222, 187, 0, 6, 150, 0, 104, 42, 231, 0, 6, ++ 155, 0, 109, 222, 47, 1, 230, 155, 1, 130, 224, 6, 247, 247, 191, 1, ++ 188, 97, 59, 4, 23, 161, 0, 224, 68, 102, 244, 42, 169, 3, 191, 222, ++ 2, 240, 0, 18, 3, 191, 222, 2, 240, 6, 196, 1, 188, 96, 3, 0, 17, 73, ++ 2, 130, 94, 175, 0, 6, 180, 1, 130, 96, 6, 245, 119, 171, 0, 176, 68, ++ 103, 0, 8, 28, 2, 4, 0, 191, 0, 6, 167, 0, 104, 69, 31, 0, 6, 167, 1, ++ 133, 224, 2, 245, 119, 171, 3, 43, 222, 2, 240, 6, 165, 1, 133, 224, ++ 6, 245, 119, 171, 0, 176, 5, 139, 0, 16, 100, 0, 2, 94, 2, 240, 17, ++ 144, 0, 176, 1, 75, 0, 23, 162, 2, 8, 66, 27, 0, 6, 170, 0, 176, 1, ++ 107, 0, 23, 162, 0, 104, 94, 139, 0, 6, 176, 0, 144, 69, 43, 0, 151, ++ 161, 0, 128, 222, 134, 244, 87, 161, 0, 110, 32, 186, 13, 166, 176, ++ 0, 176, 65, 183, 0, 8, 46, 0, 224, 32, 186, 35, 40, 47, 2, 5, 94, 175, ++ 0, 6, 178, 1, 188, 97, 3, 0, 17, 51, 0, 225, 13, 130, 41, 67, 96, 0, ++ 224, 141, 135, 0, 3, 97, 0, 232, 68, 101, 3, 151, 165, 0, 109, 94, 151, ++ 1, 0, 193, 2, 2, 0, 191, 0, 6, 194, 0, 104, 222, 75, 6, 166, 185, 1, ++ 132, 224, 2, 247, 247, 191, 0, 104, 222, 75, 4, 6, 188, 2, 130, 222, ++ 179, 0, 6, 188, 1, 188, 96, 3, 0, 11, 10, 2, 4, 94, 179, 0, 6, 191, ++ 0, 104, 222, 75, 6, 38, 191, 0, 2, 94, 2, 240, 21, 143, 0, 2, 94, 2, ++ 240, 18, 48, 3, 163, 222, 2, 240, 6, 194, 1, 131, 224, 2, 245, 151, ++ 172, 1, 130, 96, 2, 245, 119, 171, 3, 209, 94, 2, 240, 0, 2, 2, 0, 80, ++ 195, 0, 7, 26, 3, 37, 222, 2, 240, 6, 200, 1, 131, 96, 6, 132, 244, ++ 39, 3, 191, 222, 2, 240, 6, 250, 2, 12, 208, 3, 0, 6, 248, 2, 3, 0, ++ 199, 0, 6, 231, 1, 20, 0, 99, 0, 23, 161, 0, 109, 222, 135, 0, 134, ++ 248, 1, 188, 96, 3, 0, 23, 128, 0, 176, 80, 203, 0, 16, 101, 0, 176, ++ 80, 207, 0, 16, 100, 1, 129, 96, 6, 13, 144, 108, 1, 130, 96, 6, 134, ++ 52, 49, 0, 176, 90, 35, 0, 23, 161, 1, 188, 96, 3, 0, 22, 136, 1, 188, ++ 90, 42, 244, 55, 161, 1, 188, 96, 3, 0, 22, 138, 0, 176, 94, 135, 0, ++ 20, 143, 0, 176, 90, 39, 0, 23, 161, 1, 188, 96, 3, 0, 22, 137, 1, 188, ++ 90, 46, 244, 55, 161, 1, 188, 96, 3, 0, 22, 139, 0, 176, 94, 135, 0, ++ 20, 144, 0, 176, 90, 27, 0, 20, 141, 0, 176, 90, 31, 0, 20, 142, 1, ++ 188, 96, 3, 0, 22, 4, 0, 104, 222, 3, 0, 6, 228, 2, 3, 80, 199, 0, 6, ++ 227, 1, 0, 80, 159, 0, 23, 128, 1, 128, 94, 2, 145, 180, 141, 1, 188, ++ 94, 2, 146, 20, 144, 1, 188, 96, 3, 0, 55, 128, 0, 2, 94, 2, 240, 22, ++ 238, 0, 176, 94, 3, 0, 20, 140, 3, 191, 222, 2, 240, 6, 243, 0, 104, ++ 194, 71, 0, 6, 236, 1, 129, 224, 6, 134, 52, 49, 1, 145, 96, 14, 132, ++ 244, 39, 1, 188, 96, 3, 0, 20, 48, 3, 191, 222, 2, 240, 0, 2, 0, 176, ++ 80, 159, 0, 23, 161, 0, 2, 94, 2, 240, 1, 229, 0, 176, 94, 135, 0, 20, ++ 39, 1, 134, 224, 4, 3, 16, 160, 0, 176, 66, 131, 0, 24, 0, 1, 12, 208, ++ 3, 0, 23, 161, 0, 104, 222, 135, 0, 102, 231, 1, 2, 80, 199, 0, 23, ++ 161, 1, 128, 94, 134, 132, 244, 39, 1, 138, 224, 14, 132, 244, 39, 0, ++ 176, 80, 191, 0, 20, 38, 3, 191, 222, 2, 240, 6, 250, 1, 134, 224, 4, ++ 3, 16, 160, 2, 0, 80, 159, 0, 6, 250, 2, 134, 193, 7, 0, 7, 21, 3, 41, ++ 94, 2, 240, 6, 255, 0, 176, 82, 51, 0, 20, 45, 0, 176, 82, 55, 0, 23, ++ 161, 1, 158, 94, 134, 132, 244, 39, 0, 176, 80, 159, 0, 23, 161, 1, ++ 128, 222, 134, 244, 55, 161, 2, 5, 128, 195, 0, 7, 6, 0, 176, 48, 23, ++ 0, 16, 143, 0, 176, 48, 19, 0, 16, 142, 0, 176, 80, 215, 0, 16, 141, ++ 0, 176, 80, 211, 0, 48, 140, 0, 176, 80, 187, 0, 16, 143, 0, 176, 80, ++ 183, 0, 16, 142, 0, 176, 80, 155, 0, 16, 141, 1, 128, 96, 6, 244, 48, ++ 140, 2, 2, 80, 199, 0, 7, 18, 0, 176, 82, 67, 0, 16, 143, 0, 176, 82, ++ 63, 0, 16, 142, 0, 176, 82, 59, 0, 16, 141, 1, 26, 82, 55, 0, 23, 161, ++ 1, 152, 222, 135, 4, 55, 161, 1, 184, 94, 134, 145, 176, 140, 1, 130, ++ 96, 2, 134, 52, 49, 1, 129, 96, 2, 13, 144, 108, 1, 188, 96, 3, 0, 20, ++ 52, 1, 188, 96, 3, 0, 20, 53, 3, 37, 222, 2, 240, 7, 24, 1, 156, 96, ++ 2, 132, 244, 39, 3, 191, 222, 2, 240, 7, 28, 2, 133, 80, 11, 0, 7, 26, ++ 0, 168, 80, 199, 13, 20, 49, 1, 188, 96, 3, 0, 20, 48, 1, 129, 96, 2, ++ 245, 215, 174, 1, 131, 96, 2, 132, 244, 39, 1, 133, 224, 2, 9, 16, 72, ++ 1, 188, 96, 3, 0, 20, 46, 3, 162, 94, 2, 240, 2, 13, 3, 191, 222, 2, ++ 240, 0, 18, 3, 35, 222, 2, 240, 7, 146, 3, 163, 94, 2, 240, 7, 146, ++ 3, 162, 222, 2, 240, 7, 146, 1, 129, 96, 6, 245, 119, 171, 3, 170, 94, ++ 2, 240, 7, 146, 1, 131, 224, 2, 9, 16, 72, 3, 81, 222, 2, 240, 7, 45, ++ 2, 6, 128, 199, 0, 7, 42, 1, 130, 224, 1, 134, 12, 48, 0, 224, 2, 107, ++ 0, 32, 154, 1, 128, 224, 6, 245, 119, 171, 3, 191, 222, 2, 240, 7, 50, ++ 3, 1, 222, 2, 240, 7, 48, 0, 104, 94, 79, 6, 39, 48, 1, 188, 96, 3, ++ 0, 23, 168, 3, 164, 94, 2, 240, 7, 50, 3, 193, 222, 2, 240, 7, 149, ++ 2, 4, 94, 179, 0, 7, 59, 1, 132, 96, 2, 245, 151, 172, 1, 131, 224, ++ 2, 9, 16, 72, 0, 176, 43, 63, 0, 23, 161, 0, 109, 42, 238, 244, 32, ++ 2, 0, 224, 2, 123, 0, 32, 158, 1, 188, 96, 3, 0, 10, 187, 0, 2, 94, ++ 2, 240, 21, 146, 3, 191, 222, 2, 240, 0, 2, 2, 3, 222, 179, 0, 7, 75, ++ 1, 131, 224, 2, 245, 151, 172, 0, 224, 32, 207, 0, 40, 51, 2, 1, 94, ++ 187, 0, 7, 75, 0, 176, 42, 131, 0, 23, 161, 0, 109, 32, 206, 244, 39, ++ 70, 1, 188, 96, 3, 0, 8, 51, 0, 224, 2, 127, 0, 32, 159, 3, 169, 94, ++ 2, 240, 7, 73, 1, 145, 96, 26, 132, 244, 39, 3, 191, 222, 2, 240, 3, ++ 107, 1, 188, 99, 255, 31, 247, 161, 0, 2, 94, 2, 240, 14, 143, 3, 41, ++ 94, 2, 240, 7, 75, 1, 145, 96, 26, 132, 244, 39, 3, 191, 222, 2, 240, ++ 7, 75, 1, 132, 96, 2, 9, 16, 72, 0, 225, 13, 194, 41, 67, 112, 0, 224, ++ 141, 199, 0, 3, 113, 2, 4, 0, 191, 0, 7, 82, 1, 188, 96, 3, 0, 17, 21, ++ 1, 20, 0, 99, 0, 23, 161, 0, 224, 102, 2, 244, 48, 101, 0, 2, 94, 2, ++ 240, 16, 147, 1, 130, 96, 2, 9, 16, 72, 0, 104, 94, 59, 24, 167, 86, ++ 0, 104, 222, 59, 7, 7, 87, 3, 191, 222, 2, 240, 0, 2, 3, 41, 94, 2, ++ 240, 7, 90, 2, 1, 80, 3, 0, 7, 90, 0, 104, 94, 59, 4, 167, 97, 1, 240, ++ 222, 23, 0, 55, 133, 0, 160, 94, 22, 240, 151, 133, 0, 104, 94, 59, ++ 6, 39, 97, 2, 1, 80, 3, 0, 7, 96, 2, 135, 128, 191, 0, 7, 96, 1, 133, ++ 224, 6, 9, 16, 72, 2, 128, 208, 3, 0, 7, 113, 0, 176, 94, 27, 0, 23, ++ 163, 0, 176, 0, 139, 0, 23, 164, 2, 4, 0, 191, 0, 7, 103, 0, 110, 65, ++ 151, 48, 103, 103, 1, 24, 90, 3, 0, 23, 163, 1, 26, 90, 3, 0, 23, 164, ++ 0, 104, 193, 131, 24, 7, 106, 0, 224, 2, 147, 0, 32, 164, 3, 191, 222, ++ 2, 240, 7, 108, 0, 109, 94, 46, 244, 135, 108, 1, 130, 224, 6, 134, ++ 52, 49, 0, 224, 94, 51, 0, 55, 140, 0, 104, 222, 50, 244, 103, 111, ++ 0, 176, 94, 15, 0, 23, 133, 0, 109, 222, 46, 244, 103, 125, 3, 191, ++ 222, 2, 240, 7, 141, 0, 176, 94, 31, 0, 23, 163, 0, 176, 0, 143, 0, ++ 23, 164, 2, 4, 0, 191, 0, 7, 119, 0, 110, 65, 151, 48, 103, 119, 1, ++ 28, 90, 3, 0, 23, 163, 1, 30, 90, 3, 0, 23, 164, 0, 109, 94, 46, 244, ++ 135, 121, 1, 130, 224, 6, 134, 52, 49, 0, 224, 94, 55, 0, 55, 141, 0, ++ 104, 222, 54, 244, 103, 124, 0, 176, 94, 15, 0, 23, 133, 0, 109, 94, ++ 46, 244, 103, 141, 1, 133, 224, 2, 9, 16, 72, 3, 209, 222, 2, 240, 7, ++ 127, 3, 41, 94, 2, 240, 7, 129, 2, 3, 0, 199, 0, 7, 130, 0, 176, 94, ++ 15, 0, 23, 133, 0, 2, 94, 2, 240, 16, 142, 0, 104, 65, 131, 24, 7, 179, ++ 2, 3, 0, 199, 0, 7, 137, 2, 12, 208, 3, 0, 7, 137, 2, 131, 80, 199, ++ 0, 7, 137, 0, 104, 222, 75, 5, 167, 137, 3, 191, 222, 2, 240, 22, 110, ++ 1, 129, 224, 6, 134, 52, 49, 0, 104, 222, 59, 6, 39, 140, 0, 224, 2, ++ 159, 0, 32, 167, 3, 191, 222, 2, 240, 6, 196, 0, 2, 94, 2, 240, 16, ++ 142, 1, 129, 96, 2, 9, 16, 72, 3, 41, 94, 2, 240, 7, 146, 2, 131, 0, ++ 199, 0, 22, 110, 3, 191, 222, 2, 240, 6, 196, 3, 209, 222, 2, 240, 7, ++ 147, 3, 165, 222, 2, 240, 6, 196, 3, 191, 222, 2, 240, 0, 18, 0, 225, ++ 13, 186, 41, 67, 110, 0, 224, 141, 191, 0, 3, 111, 2, 6, 80, 3, 0, 7, ++ 157, 0, 176, 1, 3, 0, 23, 161, 0, 109, 129, 10, 244, 39, 157, 0, 232, ++ 68, 100, 8, 119, 161, 0, 110, 94, 132, 8, 39, 157, 1, 135, 224, 6, 245, ++ 119, 171, 1, 8, 94, 75, 0, 23, 161, 0, 104, 94, 75, 5, 39, 160, 0, 104, ++ 94, 135, 0, 39, 161, 0, 176, 94, 15, 0, 23, 133, 0, 2, 94, 2, 240, 16, ++ 142, 0, 104, 94, 59, 6, 39, 167, 1, 188, 96, 3, 0, 23, 140, 2, 0, 208, ++ 3, 0, 7, 172, 1, 188, 96, 3, 0, 23, 141, 3, 191, 222, 2, 240, 7, 172, ++ 1, 188, 96, 3, 0, 23, 140, 2, 3, 0, 199, 0, 2, 13, 2, 12, 208, 3, 0, ++ 2, 13, 1, 156, 96, 2, 132, 244, 39, 3, 191, 222, 2, 240, 2, 13, 0, 104, ++ 65, 131, 24, 7, 178, 1, 128, 96, 6, 132, 244, 39, 3, 41, 94, 2, 240, ++ 6, 196, 1, 130, 96, 6, 134, 52, 49, 2, 131, 0, 199, 0, 22, 110, 3, 191, ++ 222, 2, 240, 6, 196, 0, 224, 2, 151, 0, 32, 165, 1, 129, 96, 2, 9, 16, ++ 72, 1, 188, 96, 3, 0, 8, 18, 0, 224, 1, 123, 0, 160, 94, 1, 188, 96, ++ 19, 20, 23, 161, 0, 109, 1, 122, 244, 32, 18, 1, 188, 96, 19, 12, 128, ++ 94, 3, 191, 222, 2, 240, 0, 18, 0, 2, 94, 2, 240, 13, 40, 3, 56, 222, ++ 2, 240, 0, 18, 3, 158, 222, 2, 240, 0, 18, 0, 232, 68, 76, 0, 247, 161, ++ 0, 232, 94, 132, 1, 23, 161, 0, 106, 222, 132, 1, 7, 195, 0, 232, 94, ++ 132, 1, 17, 135, 1, 188, 96, 3, 0, 17, 136, 1, 165, 224, 34, 48, 17, ++ 128, 1, 188, 96, 3, 0, 17, 19, 1, 188, 96, 3, 0, 17, 20, 0, 176, 68, ++ 103, 0, 23, 161, 0, 176, 68, 107, 0, 23, 162, 0, 176, 94, 135, 0, 17, ++ 4, 0, 176, 94, 139, 0, 17, 5, 3, 184, 222, 2, 240, 7, 197, 3, 191, 222, ++ 2, 240, 0, 18, 1, 188, 96, 3, 4, 183, 146, 1, 188, 96, 3, 4, 23, 161, ++ 1, 188, 99, 255, 31, 240, 206, 0, 176, 82, 23, 0, 16, 232, 0, 176, 82, ++ 27, 0, 16, 233, 0, 176, 82, 31, 0, 16, 234, 1, 188, 96, 3, 0, 16, 228, ++ 2, 134, 0, 195, 0, 7, 227, 0, 176, 84, 15, 0, 23, 162, 0, 105, 222, ++ 138, 144, 135, 214, 0, 232, 82, 18, 244, 80, 228, 0, 104, 160, 71, 0, ++ 7, 227, 1, 188, 96, 3, 0, 16, 228, 0, 176, 84, 39, 0, 16, 224, 0, 176, ++ 84, 47, 0, 16, 225, 3, 191, 222, 2, 240, 7, 236, 1, 188, 96, 3, 2, 151, ++ 161, 1, 188, 96, 3, 24, 144, 232, 1, 188, 96, 3, 0, 16, 233, 1, 188, ++ 96, 3, 0, 16, 234, 3, 191, 222, 2, 240, 7, 227, 3, 164, 222, 2, 240, ++ 10, 79, 3, 169, 222, 2, 240, 10, 79, 1, 188, 96, 3, 1, 215, 161, 2, ++ 6, 0, 195, 0, 7, 229, 2, 128, 222, 95, 0, 7, 234, 0, 176, 84, 7, 0, ++ 16, 224, 0, 104, 32, 71, 0, 7, 232, 1, 210, 222, 134, 160, 48, 224, ++ 0, 176, 84, 11, 0, 16, 225, 3, 191, 222, 2, 240, 7, 236, 1, 188, 94, ++ 134, 144, 16, 224, 1, 188, 96, 31, 0, 16, 225, 1, 188, 96, 3, 0, 16, ++ 226, 0, 176, 82, 35, 0, 16, 229, 0, 176, 82, 39, 0, 16, 230, 0, 176, ++ 82, 43, 0, 16, 231, 0, 2, 94, 2, 240, 16, 109, 3, 169, 222, 2, 240, ++ 10, 176, 0, 104, 94, 79, 4, 40, 8, 1, 188, 99, 255, 31, 240, 195, 0, ++ 104, 94, 79, 22, 167, 250, 0, 104, 94, 79, 5, 167, 253, 1, 188, 96, ++ 3, 26, 144, 227, 1, 188, 96, 3, 6, 183, 146, 0, 104, 94, 79, 5, 40, ++ 8, 3, 191, 222, 2, 240, 8, 2, 1, 188, 96, 3, 24, 183, 146, 1, 188, 96, ++ 3, 14, 144, 227, 3, 191, 222, 2, 240, 7, 255, 1, 188, 96, 3, 6, 55, ++ 146, 1, 188, 96, 3, 24, 144, 227, 2, 142, 1, 171, 0, 8, 2, 2, 152, 68, ++ 7, 0, 11, 176, 2, 128, 70, 7, 0, 11, 176, 0, 176, 32, 71, 0, 23, 129, ++ 0, 2, 94, 2, 240, 16, 125, 0, 232, 94, 132, 0, 215, 161, 0, 106, 94, ++ 134, 144, 136, 8, 0, 232, 82, 18, 244, 48, 228, 3, 191, 222, 2, 240, ++ 8, 11, 1, 188, 96, 3, 0, 16, 228, 3, 56, 222, 2, 240, 8, 11, 1, 135, ++ 224, 6, 28, 144, 228, 1, 144, 96, 10, 9, 16, 72, 1, 188, 97, 3, 4, 55, ++ 145, 0, 104, 94, 79, 22, 172, 59, 0, 104, 94, 79, 5, 171, 176, 3, 131, ++ 94, 2, 240, 10, 79, 3, 191, 222, 2, 240, 0, 2, 2, 4, 65, 99, 0, 8, 29, ++ 1, 188, 96, 3, 0, 17, 73, 1, 188, 96, 3, 1, 11, 128, 0, 225, 13, 178, ++ 40, 227, 108, 0, 224, 141, 183, 0, 3, 109, 1, 132, 96, 2, 11, 16, 88, ++ 2, 5, 94, 175, 0, 8, 25, 1, 135, 224, 6, 38, 113, 51, 2, 4, 0, 191, ++ 0, 8, 28, 1, 133, 224, 2, 245, 119, 171, 0, 2, 94, 2, 240, 17, 144, ++ 3, 191, 222, 2, 240, 0, 2, 3, 163, 94, 2, 240, 8, 31, 0, 2, 94, 2, 240, ++ 23, 206, 2, 133, 197, 35, 0, 0, 2, 1, 132, 96, 6, 11, 16, 88, 2, 0, ++ 222, 255, 0, 8, 37, 1, 128, 224, 2, 247, 247, 191, 0, 104, 43, 79, 0, ++ 8, 37, 0, 224, 68, 101, 90, 74, 211, 2, 5, 94, 175, 0, 8, 39, 1, 188, ++ 97, 3, 0, 17, 51, 2, 5, 128, 191, 0, 8, 45, 1, 188, 96, 19, 17, 87, ++ 161, 0, 2, 94, 2, 240, 1, 39, 1, 150, 96, 14, 3, 48, 25, 0, 176, 64, ++ 103, 0, 23, 162, 0, 2, 94, 2, 240, 1, 43, 2, 3, 192, 55, 0, 8, 47, 3, ++ 191, 222, 2, 240, 0, 18, 0, 224, 2, 31, 0, 32, 135, 1, 130, 96, 6, 40, ++ 145, 68, 1, 188, 96, 3, 1, 11, 128, 3, 191, 222, 2, 240, 0, 18, 2, 6, ++ 1, 171, 0, 8, 53, 1, 128, 96, 1, 134, 12, 48, 2, 6, 129, 171, 0, 8, ++ 55, 1, 131, 224, 1, 134, 12, 48, 1, 131, 224, 2, 15, 16, 120, 2, 129, ++ 64, 19, 0, 0, 2, 2, 0, 66, 3, 0, 8, 60, 1, 132, 96, 2, 245, 151, 172, ++ 1, 188, 96, 3, 0, 10, 187, 1, 188, 96, 3, 0, 16, 128, 3, 163, 222, 2, ++ 240, 8, 63, 1, 144, 96, 2, 9, 16, 72, 0, 176, 68, 103, 0, 23, 158, 0, ++ 176, 68, 107, 0, 23, 157, 0, 176, 68, 111, 0, 23, 156, 0, 176, 68, 115, ++ 0, 23, 155, 0, 104, 222, 122, 35, 40, 63, 0, 224, 2, 35, 0, 32, 136, ++ 1, 21, 64, 59, 0, 23, 151, 0, 109, 128, 167, 0, 136, 74, 0, 160, 94, ++ 95, 0, 55, 151, 0, 104, 128, 167, 0, 8, 74, 1, 188, 96, 3, 0, 55, 151, ++ 0, 176, 1, 67, 0, 23, 161, 1, 12, 129, 67, 0, 23, 163, 0, 104, 94, 143, ++ 0, 40, 78, 1, 140, 224, 0, 10, 23, 161, 1, 201, 222, 132, 5, 39, 255, ++ 1, 188, 96, 3, 16, 119, 149, 1, 145, 224, 2, 13, 144, 108, 2, 134, 64, ++ 55, 0, 8, 84, 0, 224, 2, 187, 0, 32, 174, 3, 191, 222, 2, 240, 12, 159, ++ 1, 188, 96, 3, 0, 20, 128, 1, 188, 96, 3, 0, 20, 129, 1, 184, 96, 10, ++ 4, 144, 36, 1, 188, 96, 3, 4, 8, 36, 1, 188, 96, 3, 0, 72, 35, 1, 188, ++ 96, 3, 0, 208, 42, 1, 179, 96, 7, 0, 16, 4, 1, 188, 96, 3, 0, 8, 8, ++ 1, 188, 96, 3, 0, 8, 9, 1, 188, 96, 3, 0, 8, 10, 1, 188, 96, 3, 0, 8, ++ 11, 1, 131, 224, 2, 245, 215, 174, 0, 224, 68, 103, 31, 76, 46, 2, 135, ++ 192, 55, 0, 12, 153, 0, 2, 94, 2, 240, 18, 47, 2, 134, 64, 55, 0, 8, ++ 102, 3, 195, 94, 2, 240, 8, 120, 3, 191, 222, 2, 240, 12, 154, 0, 104, ++ 192, 51, 0, 72, 118, 0, 107, 68, 101, 133, 200, 118, 0, 176, 65, 39, ++ 0, 23, 161, 0, 176, 65, 39, 1, 208, 73, 0, 176, 94, 135, 0, 23, 161, ++ 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, ++ 135, 0, 23, 161, 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, 23, ++ 161, 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, 23, 161, 0, 176, ++ 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, ++ 16, 73, 3, 191, 222, 2, 240, 13, 12, 3, 67, 94, 2, 240, 8, 97, 2, 134, ++ 64, 55, 0, 8, 132, 0, 104, 94, 95, 0, 12, 154, 0, 104, 94, 95, 0, 76, ++ 154, 1, 82, 210, 3, 0, 23, 161, 1, 133, 210, 6, 244, 55, 162, 3, 191, ++ 222, 2, 240, 8, 127, 1, 60, 82, 3, 0, 23, 161, 1, 188, 82, 6, 244, 55, ++ 162, 3, 35, 222, 2, 240, 8, 130, 0, 104, 222, 139, 1, 204, 154, 3, 191, ++ 222, 2, 240, 8, 132, 0, 104, 94, 139, 2, 136, 132, 0, 104, 222, 139, ++ 3, 140, 154, 0, 109, 64, 51, 0, 204, 159, 0, 104, 94, 95, 0, 72, 151, ++ 0, 104, 94, 95, 0, 40, 148, 0, 104, 0, 167, 0, 200, 137, 0, 104, 128, ++ 167, 0, 168, 138, 0, 224, 68, 102, 144, 40, 48, 1, 188, 98, 195, 0, ++ 23, 161, 2, 128, 82, 3, 0, 8, 141, 1, 150, 82, 3, 0, 23, 161, 0, 128, ++ 222, 134, 144, 55, 154, 2, 3, 82, 3, 0, 8, 146, 0, 224, 94, 106, 144, ++ 55, 154, 2, 7, 210, 3, 0, 8, 146, 0, 232, 94, 107, 0, 55, 154, 2, 158, ++ 94, 107, 0, 12, 159, 3, 191, 222, 2, 240, 8, 155, 1, 82, 210, 3, 0, ++ 23, 161, 1, 133, 210, 6, 244, 55, 154, 3, 191, 222, 2, 240, 8, 155, ++ 1, 60, 82, 3, 0, 23, 161, 1, 188, 82, 6, 244, 55, 154, 0, 110, 94, 104, ++ 11, 172, 159, 0, 104, 94, 107, 0, 13, 12, 2, 4, 192, 59, 0, 8, 173, ++ 1, 129, 224, 6, 13, 144, 108, 2, 7, 192, 175, 0, 8, 163, 2, 7, 64, 55, ++ 0, 8, 161, 0, 224, 2, 115, 0, 32, 156, 3, 191, 222, 2, 240, 12, 159, ++ 0, 2, 94, 2, 240, 18, 47, 3, 191, 222, 2, 240, 8, 157, 0, 176, 32, 35, ++ 0, 12, 8, 0, 176, 32, 39, 0, 12, 9, 0, 176, 32, 43, 0, 12, 10, 0, 176, ++ 32, 47, 0, 12, 11, 0, 176, 94, 127, 0, 12, 12, 2, 135, 192, 175, 0, ++ 12, 153, 2, 130, 64, 59, 0, 12, 153, 1, 88, 64, 175, 0, 23, 154, 1, ++ 188, 96, 63, 30, 23, 161, 0, 109, 222, 106, 244, 44, 153, 3, 91, 94, ++ 2, 240, 8, 175, 1, 188, 96, 19, 0, 16, 67, 1, 188, 96, 255, 30, 23, ++ 161, 0, 110, 94, 106, 244, 44, 153, 0, 176, 65, 35, 40, 16, 72, 1, 128, ++ 96, 2, 242, 151, 148, 1, 132, 224, 2, 9, 16, 72, 1, 88, 64, 175, 0, ++ 16, 42, 0, 104, 64, 171, 0, 44, 153, 1, 187, 94, 86, 0, 144, 4, 2, 3, ++ 94, 87, 0, 8, 192, 2, 0, 71, 163, 0, 8, 189, 1, 188, 98, 30, 60, 17, ++ 224, 1, 188, 96, 3, 0, 17, 234, 0, 176, 94, 107, 0, 17, 235, 1, 152, ++ 96, 30, 61, 17, 232, 2, 0, 71, 179, 0, 8, 192, 0, 176, 94, 107, 0, 17, ++ 239, 1, 176, 224, 206, 61, 145, 236, 3, 131, 94, 2, 240, 8, 195, 0, ++ 2, 94, 2, 240, 18, 47, 0, 109, 64, 51, 4, 200, 192, 3, 170, 222, 2, ++ 240, 8, 223, 1, 188, 99, 255, 31, 227, 179, 1, 188, 96, 31, 16, 208, ++ 100, 1, 188, 96, 3, 0, 183, 161, 1, 188, 99, 255, 31, 231, 147, 0, 224, ++ 65, 134, 244, 48, 101, 1, 188, 99, 255, 31, 246, 0, 0, 224, 94, 135, ++ 0, 119, 161, 0, 2, 94, 2, 240, 15, 24, 2, 0, 192, 119, 0, 8, 213, 1, ++ 41, 64, 119, 0, 23, 162, 0, 109, 94, 139, 4, 200, 211, 0, 232, 94, 139, ++ 4, 214, 0, 1, 188, 96, 31, 5, 240, 99, 0, 224, 65, 142, 192, 16, 99, ++ 1, 12, 86, 3, 0, 3, 179, 0, 104, 222, 135, 1, 104, 213, 0, 176, 94, ++ 139, 0, 7, 147, 0, 109, 222, 135, 1, 200, 216, 0, 224, 65, 147, 0, 48, ++ 100, 3, 191, 222, 2, 240, 8, 200, 3, 176, 94, 2, 240, 8, 222, 1, 131, ++ 96, 2, 13, 144, 108, 0, 104, 30, 27, 255, 232, 223, 1, 188, 96, 31, ++ 5, 240, 101, 0, 224, 65, 148, 240, 208, 101, 2, 0, 90, 3, 0, 8, 223, ++ 1, 131, 96, 6, 13, 144, 108, 0, 32, 64, 47, 8, 168, 225, 1, 188, 96, ++ 3, 0, 3, 179, 1, 188, 96, 3, 0, 7, 252, 1, 136, 224, 15, 0, 7, 253, ++ 0, 109, 64, 51, 2, 10, 73, 1, 41, 82, 15, 0, 23, 147, 1, 9, 82, 15, ++ 0, 23, 170, 0, 104, 222, 79, 3, 168, 233, 1, 41, 82, 35, 0, 23, 147, ++ 1, 169, 94, 79, 0, 55, 147, 1, 150, 96, 2, 242, 151, 148, 0, 224, 65, ++ 135, 1, 240, 101, 1, 188, 96, 15, 0, 23, 161, 0, 40, 222, 134, 144, ++ 104, 240, 1, 134, 96, 6, 242, 151, 148, 0, 224, 65, 151, 0, 112, 101, ++ 0, 224, 32, 147, 0, 200, 36, 1, 6, 94, 83, 0, 23, 162, 0, 160, 94, 79, ++ 4, 119, 161, 0, 104, 222, 135, 4, 72, 254, 1, 134, 224, 6, 242, 151, ++ 148, 0, 184, 94, 139, 0, 55, 162, 0, 176, 90, 3, 0, 23, 160, 2, 10, ++ 218, 3, 0, 8, 248, 1, 135, 96, 6, 242, 151, 148, 2, 132, 192, 59, 0, ++ 8, 254, 2, 3, 218, 3, 0, 8, 254, 3, 171, 94, 2, 240, 8, 252, 2, 4, 65, ++ 7, 0, 8, 254, 1, 128, 96, 4, 255, 167, 253, 1, 6, 94, 83, 0, 23, 162, ++ 1, 130, 222, 138, 0, 144, 4, 3, 170, 222, 2, 240, 9, 68, 3, 171, 94, ++ 2, 240, 9, 22, 1, 132, 96, 2, 13, 144, 108, 1, 188, 99, 255, 31, 247, ++ 153, 0, 176, 30, 35, 0, 23, 162, 0, 104, 222, 171, 0, 41, 8, 0, 160, ++ 94, 79, 255, 119, 161, 0, 104, 222, 135, 7, 41, 20, 3, 191, 222, 2, ++ 240, 9, 10, 2, 132, 82, 15, 0, 9, 20, 2, 4, 210, 15, 0, 9, 13, 3, 177, ++ 94, 2, 240, 9, 19, 0, 176, 30, 31, 0, 23, 162, 3, 191, 222, 2, 240, ++ 9, 14, 3, 179, 94, 2, 240, 9, 19, 2, 0, 82, 23, 0, 9, 20, 0, 104, 94, ++ 139, 255, 233, 20, 0, 224, 1, 94, 244, 80, 101, 2, 1, 90, 71, 0, 9, ++ 20, 0, 176, 30, 79, 0, 23, 153, 1, 132, 96, 6, 13, 144, 108, 2, 0, 82, ++ 23, 0, 9, 66, 3, 49, 94, 2, 240, 9, 66, 2, 2, 0, 191, 0, 9, 66, 1, 128, ++ 224, 1, 97, 11, 8, 2, 0, 82, 23, 0, 9, 29, 0, 104, 222, 79, 4, 9, 28, ++ 0, 176, 42, 215, 0, 23, 162, 0, 109, 222, 137, 85, 9, 48, 2, 2, 171, ++ 47, 0, 9, 61, 2, 131, 43, 47, 0, 9, 31, 0, 104, 94, 95, 0, 9, 42, 1, ++ 188, 96, 3, 0, 23, 163, 1, 56, 82, 3, 0, 23, 163, 2, 131, 171, 47, 0, ++ 9, 38, 0, 104, 222, 95, 0, 41, 38, 1, 8, 94, 143, 0, 23, 163, 0, 105, ++ 94, 143, 0, 105, 61, 3, 191, 222, 2, 240, 9, 42, 0, 109, 222, 95, 0, ++ 73, 40, 3, 191, 222, 2, 240, 9, 61, 2, 132, 43, 47, 0, 9, 61, 0, 104, ++ 222, 143, 0, 9, 61, 0, 104, 42, 155, 0, 9, 61, 0, 176, 43, 147, 0, 23, ++ 162, 0, 109, 170, 154, 244, 73, 61, 0, 104, 94, 171, 0, 73, 48, 0, 104, ++ 94, 79, 6, 137, 48, 3, 191, 222, 2, 240, 9, 57, 0, 176, 43, 155, 0, ++ 23, 162, 0, 176, 42, 155, 0, 23, 161, 2, 131, 172, 39, 0, 9, 53, 0, ++ 104, 44, 135, 0, 9, 54, 0, 109, 94, 133, 100, 41, 54, 0, 176, 44, 127, ++ 0, 23, 162, 0, 109, 94, 137, 92, 169, 56, 0, 176, 44, 75, 0, 11, 17, ++ 1, 132, 224, 6, 247, 247, 191, 0, 104, 222, 79, 2, 137, 61, 0, 2, 94, ++ 2, 240, 23, 200, 2, 6, 222, 255, 0, 9, 61, 0, 224, 43, 199, 0, 42, 241, ++ 0, 104, 222, 95, 0, 9, 64, 0, 104, 222, 171, 0, 73, 64, 1, 128, 224, ++ 5, 97, 11, 8, 0, 104, 43, 79, 0, 9, 66, 1, 128, 224, 6, 247, 247, 191, ++ 1, 188, 99, 255, 31, 247, 165, 3, 43, 94, 2, 240, 9, 69, 0, 176, 30, ++ 79, 0, 23, 165, 2, 7, 82, 15, 0, 9, 193, 2, 128, 71, 163, 0, 9, 190, ++ 2, 128, 71, 179, 0, 9, 190, 0, 224, 32, 147, 0, 136, 36, 0, 232, 32, ++ 143, 0, 136, 35, 1, 188, 96, 3, 0, 17, 228, 1, 188, 96, 3, 3, 209, 225, ++ 2, 6, 94, 83, 0, 9, 78, 1, 188, 96, 3, 4, 145, 225, 2, 6, 222, 83, 0, ++ 9, 82, 0, 224, 71, 135, 0, 81, 225, 2, 7, 210, 15, 0, 9, 82, 0, 224, ++ 71, 135, 0, 145, 225, 0, 109, 64, 51, 2, 202, 73, 0, 104, 94, 79, 5, ++ 137, 85, 0, 104, 222, 171, 0, 73, 193, 3, 171, 94, 2, 240, 9, 88, 2, ++ 0, 82, 23, 0, 9, 193, 2, 5, 128, 243, 0, 9, 93, 0, 104, 94, 151, 255, ++ 233, 90, 0, 224, 94, 151, 0, 151, 165, 0, 104, 222, 151, 255, 233, 93, ++ 2, 128, 82, 23, 0, 9, 193, 2, 7, 0, 191, 0, 9, 193, 1, 188, 96, 27, ++ 4, 55, 162, 0, 144, 71, 135, 0, 48, 101, 0, 224, 65, 150, 244, 80, 101, ++ 0, 224, 71, 135, 1, 8, 26, 3, 131, 94, 2, 240, 9, 100, 0, 2, 94, 2, ++ 240, 18, 47, 0, 109, 64, 49, 3, 73, 97, 0, 109, 64, 49, 3, 74, 73, 1, ++ 188, 96, 11, 29, 87, 161, 0, 104, 222, 151, 255, 233, 116, 1, 15, 90, ++ 7, 0, 23, 165, 3, 30, 222, 2, 240, 9, 116, 2, 0, 82, 23, 0, 9, 116, ++ 3, 44, 94, 2, 240, 9, 193, 0, 104, 94, 103, 255, 233, 116, 0, 224, 94, ++ 103, 0, 151, 153, 0, 224, 94, 102, 244, 48, 100, 1, 42, 88, 3, 0, 23, ++ 153, 1, 0, 222, 151, 0, 23, 165, 0, 224, 94, 102, 244, 183, 153, 0, ++ 224, 94, 103, 0, 55, 153, 1, 21, 88, 3, 0, 23, 166, 3, 191, 222, 2, ++ 240, 9, 132, 0, 224, 94, 150, 244, 48, 100, 1, 42, 88, 3, 0, 23, 153, ++ 2, 5, 128, 243, 0, 9, 131, 1, 130, 224, 2, 243, 55, 153, 2, 0, 82, 23, ++ 0, 9, 131, 1, 22, 216, 3, 0, 23, 166, 1, 15, 90, 7, 0, 23, 164, 1, 12, ++ 216, 3, 0, 23, 161, 0, 104, 222, 146, 244, 41, 127, 0, 224, 94, 103, ++ 2, 23, 153, 3, 191, 222, 2, 240, 9, 136, 1, 13, 216, 3, 0, 23, 161, ++ 0, 104, 222, 146, 244, 41, 193, 0, 224, 94, 103, 4, 23, 153, 3, 191, ++ 222, 2, 240, 9, 136, 1, 16, 88, 3, 0, 23, 166, 0, 104, 222, 155, 0, ++ 201, 136, 1, 129, 218, 3, 0, 23, 161, 0, 184, 94, 134, 192, 23, 161, ++ 2, 129, 222, 135, 0, 9, 193, 0, 136, 94, 103, 0, 119, 128, 0, 224, 0, ++ 174, 240, 16, 100, 1, 170, 222, 100, 255, 135, 252, 0, 104, 222, 155, ++ 0, 73, 162, 2, 7, 129, 135, 0, 9, 149, 0, 109, 222, 3, 12, 9, 149, 2, ++ 133, 82, 15, 0, 9, 149, 2, 152, 82, 59, 0, 9, 149, 1, 129, 224, 4, 255, ++ 167, 253, 0, 224, 94, 0, 11, 55, 163, 0, 224, 94, 143, 0, 151, 163, ++ 0, 224, 65, 135, 0, 119, 162, 0, 2, 94, 2, 240, 16, 207, 0, 232, 32, ++ 143, 1, 8, 35, 1, 188, 96, 35, 6, 215, 129, 0, 136, 94, 151, 0, 119, ++ 161, 0, 232, 94, 134, 244, 176, 99, 1, 188, 96, 7, 14, 23, 161, 0, 224, ++ 65, 142, 244, 48, 99, 0, 176, 86, 23, 0, 23, 161, 0, 176, 86, 27, 0, ++ 23, 162, 0, 104, 222, 134, 208, 73, 193, 0, 104, 222, 138, 208, 105, ++ 193, 0, 2, 94, 2, 240, 16, 164, 1, 188, 96, 35, 6, 144, 100, 1, 188, ++ 98, 79, 0, 23, 162, 0, 2, 94, 2, 240, 16, 247, 0, 224, 71, 135, 2, 23, ++ 161, 3, 131, 94, 2, 240, 9, 166, 0, 110, 192, 50, 244, 41, 164, 0, 110, ++ 192, 50, 244, 44, 153, 0, 104, 94, 155, 0, 73, 190, 1, 188, 98, 30, ++ 244, 113, 224, 0, 104, 222, 155, 0, 201, 177, 1, 188, 97, 19, 0, 183, ++ 161, 2, 6, 0, 243, 0, 9, 173, 1, 188, 96, 19, 0, 183, 161, 1, 188, 96, ++ 3, 0, 17, 238, 0, 176, 94, 107, 0, 17, 239, 1, 146, 224, 14, 244, 49, ++ 236, 3, 191, 222, 2, 240, 9, 190, 0, 104, 94, 155, 0, 105, 179, 0, 104, ++ 222, 155, 0, 169, 190, 1, 152, 96, 6, 61, 17, 232, 0, 224, 32, 147, ++ 0, 136, 36, 0, 232, 32, 143, 0, 136, 35, 1, 188, 96, 3, 0, 17, 234, ++ 0, 104, 222, 95, 0, 73, 185, 0, 176, 94, 107, 0, 17, 235, 1, 146, 222, ++ 94, 61, 17, 232, 1, 135, 96, 2, 61, 17, 232, 0, 104, 222, 155, 0, 169, ++ 189, 1, 135, 96, 6, 61, 17, 232, 1, 152, 96, 22, 61, 17, 232, 1, 129, ++ 224, 4, 255, 135, 252, 1, 170, 222, 100, 255, 135, 252, 3, 191, 222, ++ 2, 240, 9, 198, 1, 188, 98, 15, 0, 17, 224, 1, 188, 96, 3, 0, 17, 228, ++ 1, 129, 224, 0, 255, 167, 253, 1, 188, 96, 15, 0, 17, 232, 1, 188, 96, ++ 3, 0, 17, 236, 2, 0, 31, 247, 0, 9, 205, 0, 224, 32, 142, 243, 72, 35, ++ 0, 176, 32, 147, 0, 16, 37, 0, 232, 32, 142, 4, 168, 35, 0, 106, 160, ++ 143, 1, 201, 205, 1, 184, 96, 6, 4, 144, 36, 1, 130, 224, 6, 242, 151, ++ 148, 1, 136, 96, 10, 0, 144, 4, 1, 188, 96, 3, 24, 119, 149, 3, 160, ++ 222, 2, 240, 9, 218, 0, 104, 94, 79, 6, 169, 223, 1, 56, 82, 3, 0, 23, ++ 128, 0, 176, 94, 95, 0, 23, 129, 2, 4, 222, 183, 0, 9, 217, 0, 104, ++ 94, 7, 0, 9, 216, 1, 188, 96, 3, 1, 119, 128, 1, 188, 96, 3, 0, 55, ++ 129, 3, 191, 222, 2, 240, 9, 217, 1, 188, 96, 3, 1, 87, 128, 0, 2, 94, ++ 2, 240, 1, 67, 0, 104, 222, 171, 0, 73, 223, 0, 160, 94, 79, 4, 119, ++ 161, 0, 104, 94, 135, 0, 76, 40, 0, 104, 94, 135, 4, 76, 40, 3, 191, ++ 222, 2, 240, 14, 46, 1, 128, 96, 1, 133, 172, 45, 0, 110, 176, 91, 0, ++ 42, 27, 0, 104, 222, 79, 4, 10, 27, 3, 51, 94, 2, 240, 10, 27, 1, 128, ++ 96, 1, 131, 108, 27, 0, 224, 48, 139, 0, 44, 34, 3, 146, 222, 2, 240, ++ 10, 27, 0, 224, 48, 107, 0, 44, 26, 0, 176, 48, 91, 0, 23, 161, 0, 109, ++ 48, 106, 244, 41, 234, 3, 191, 222, 2, 240, 10, 25, 1, 128, 96, 5, 131, ++ 108, 27, 1, 188, 96, 39, 8, 151, 161, 0, 2, 94, 2, 240, 1, 39, 1, 135, ++ 224, 6, 3, 44, 32, 0, 176, 1, 67, 0, 12, 33, 3, 131, 94, 2, 240, 10, ++ 23, 0, 109, 192, 51, 5, 201, 250, 0, 232, 96, 186, 1, 151, 166, 0, 128, ++ 222, 155, 1, 23, 165, 0, 104, 94, 95, 0, 9, 245, 0, 128, 222, 155, 0, ++ 87, 165, 0, 176, 65, 183, 0, 12, 44, 0, 128, 176, 179, 12, 140, 44, ++ 0, 176, 65, 183, 0, 12, 44, 0, 176, 48, 179, 0, 16, 64, 0, 0, 128, 0, ++ 0, 0, 0, 1, 188, 96, 27, 6, 208, 101, 1, 188, 96, 3, 0, 183, 164, 0, ++ 2, 94, 2, 240, 1, 114, 0, 104, 94, 147, 0, 170, 2, 3, 131, 94, 2, 240, ++ 10, 23, 0, 109, 192, 49, 130, 234, 23, 1, 188, 96, 3, 6, 76, 44, 3, ++ 191, 222, 2, 240, 9, 246, 2, 7, 193, 151, 0, 10, 5, 1, 56, 90, 7, 0, ++ 23, 187, 3, 191, 222, 2, 240, 10, 6, 1, 60, 90, 3, 0, 23, 187, 1, 188, ++ 96, 27, 4, 55, 166, 0, 232, 65, 150, 244, 215, 163, 0, 136, 94, 143, ++ 0, 55, 163, 0, 224, 94, 142, 247, 119, 165, 0, 224, 94, 151, 0, 87, ++ 165, 3, 131, 94, 2, 240, 10, 23, 0, 109, 192, 49, 130, 234, 23, 0, 109, ++ 192, 50, 244, 170, 23, 0, 232, 94, 150, 1, 151, 166, 0, 128, 222, 155, ++ 1, 23, 164, 0, 104, 94, 95, 0, 10, 18, 0, 128, 222, 155, 0, 87, 164, ++ 0, 176, 65, 183, 0, 23, 164, 0, 128, 222, 147, 12, 151, 164, 0, 176, ++ 65, 183, 0, 16, 64, 0, 0, 128, 0, 0, 0, 0, 3, 191, 222, 2, 240, 10, ++ 11, 3, 134, 222, 2, 240, 12, 156, 3, 191, 222, 2, 240, 13, 132, 1, 128, ++ 96, 1, 131, 108, 27, 1, 188, 96, 3, 0, 12, 26, 3, 134, 222, 2, 240, ++ 12, 156, 2, 135, 192, 55, 0, 12, 153, 0, 2, 94, 2, 240, 18, 47, 3, 3, ++ 94, 2, 240, 10, 27, 3, 169, 222, 2, 240, 10, 37, 0, 2, 94, 2, 240, 18, ++ 47, 2, 7, 64, 55, 0, 10, 32, 3, 134, 222, 2, 240, 12, 156, 2, 135, 192, ++ 55, 0, 12, 153, 0, 2, 94, 2, 240, 14, 156, 0, 110, 64, 48, 2, 10, 79, ++ 3, 1, 222, 2, 240, 10, 79, 0, 104, 222, 171, 0, 10, 54, 3, 43, 94, 2, ++ 240, 10, 43, 0, 224, 2, 43, 0, 32, 138, 3, 191, 222, 2, 240, 10, 47, ++ 2, 128, 82, 23, 0, 10, 46, 0, 224, 2, 67, 0, 32, 144, 3, 191, 222, 2, ++ 240, 10, 47, 0, 224, 2, 87, 0, 32, 149, 0, 104, 94, 79, 4, 13, 126, ++ 0, 104, 94, 79, 2, 141, 126, 0, 104, 94, 79, 2, 11, 188, 0, 104, 94, ++ 79, 5, 14, 30, 0, 104, 94, 79, 6, 14, 30, 0, 104, 94, 79, 6, 142, 40, ++ 3, 191, 222, 2, 240, 14, 46, 0, 104, 222, 171, 0, 42, 72, 3, 43, 94, ++ 2, 240, 10, 58, 0, 224, 2, 47, 0, 32, 139, 3, 191, 222, 2, 240, 10, ++ 62, 2, 128, 82, 23, 0, 10, 61, 0, 224, 2, 71, 0, 32, 145, 3, 191, 222, ++ 2, 240, 10, 62, 0, 224, 2, 91, 0, 32, 150, 0, 104, 94, 79, 6, 171, 137, ++ 0, 104, 94, 79, 4, 46, 70, 0, 104, 94, 79, 4, 174, 70, 0, 104, 94, 79, ++ 5, 172, 45, 0, 104, 94, 79, 6, 43, 137, 0, 104, 94, 79, 5, 46, 28, 0, ++ 160, 94, 79, 255, 119, 161, 0, 104, 94, 135, 7, 46, 57, 0, 104, 94, ++ 79, 22, 172, 56, 3, 191, 222, 2, 240, 11, 176, 3, 191, 222, 2, 240, ++ 11, 180, 0, 224, 2, 15, 0, 32, 131, 1, 188, 96, 3, 0, 17, 236, 1, 188, ++ 96, 15, 0, 17, 232, 2, 132, 192, 59, 0, 9, 193, 1, 132, 224, 6, 9, 16, ++ 72, 3, 191, 222, 2, 240, 9, 193, 2, 0, 192, 147, 0, 0, 2, 3, 163, 94, ++ 2, 240, 10, 83, 3, 195, 94, 2, 240, 10, 82, 3, 191, 222, 2, 240, 13, ++ 10, 0, 2, 94, 2, 240, 18, 47, 2, 7, 192, 175, 0, 10, 86, 2, 7, 64, 55, ++ 0, 10, 83, 1, 7, 192, 175, 0, 23, 161, 0, 184, 94, 135, 0, 55, 161, ++ 1, 130, 94, 134, 13, 144, 108, 0, 176, 68, 127, 0, 7, 254, 1, 131, 96, ++ 2, 9, 16, 72, 2, 135, 192, 55, 0, 12, 153, 3, 134, 222, 2, 240, 12, ++ 156, 0, 2, 94, 2, 240, 18, 47, 3, 67, 94, 2, 240, 10, 91, 2, 135, 192, ++ 55, 0, 12, 153, 3, 1, 222, 2, 240, 10, 122, 3, 48, 94, 2, 240, 10, 122, ++ 1, 188, 96, 31, 21, 80, 101, 0, 224, 65, 148, 245, 48, 101, 1, 56, 64, ++ 43, 0, 22, 128, 1, 45, 64, 107, 0, 23, 162, 0, 136, 94, 139, 1, 55, ++ 162, 2, 136, 64, 39, 0, 10, 105, 1, 132, 96, 6, 208, 22, 128, 0, 176, ++ 90, 2, 244, 86, 128, 2, 5, 192, 39, 0, 10, 108, 1, 135, 224, 6, 208, ++ 22, 128, 1, 188, 96, 27, 13, 215, 161, 0, 2, 94, 2, 240, 1, 39, 0, 176, ++ 64, 103, 0, 22, 129, 1, 188, 96, 27, 13, 247, 161, 0, 2, 94, 2, 240, ++ 1, 39, 0, 176, 64, 103, 0, 22, 130, 0, 176, 90, 11, 0, 23, 161, 0, 232, ++ 90, 6, 244, 55, 162, 0, 225, 94, 138, 244, 87, 161, 0, 224, 222, 134, ++ 244, 87, 161, 0, 152, 94, 135, 0, 183, 161, 0, 224, 30, 167, 0, 103, ++ 169, 0, 105, 30, 167, 1, 138, 122, 1, 188, 96, 3, 0, 7, 169, 2, 128, ++ 31, 247, 0, 10, 124, 0, 110, 64, 48, 2, 11, 132, 3, 129, 222, 2, 240, ++ 10, 137, 0, 224, 2, 23, 0, 32, 133, 3, 41, 222, 2, 240, 10, 128, 2, ++ 144, 46, 3, 0, 10, 129, 1, 188, 96, 3, 0, 43, 128, 3, 169, 222, 2, 240, ++ 10, 133, 1, 132, 224, 6, 9, 16, 72, 1, 128, 224, 2, 9, 16, 72, 1, 132, ++ 224, 2, 247, 247, 191, 3, 134, 222, 2, 240, 12, 156, 1, 128, 96, 4, ++ 255, 135, 252, 1, 128, 96, 6, 242, 151, 148, 3, 191, 222, 2, 240, 11, ++ 54, 0, 104, 222, 79, 4, 10, 140, 3, 51, 94, 2, 240, 10, 140, 1, 188, ++ 96, 3, 0, 12, 26, 1, 131, 96, 2, 247, 247, 191, 3, 41, 222, 2, 240, ++ 10, 144, 2, 136, 174, 3, 0, 10, 162, 1, 188, 96, 3, 0, 11, 128, 3, 171, ++ 94, 2, 240, 10, 157, 0, 104, 94, 171, 0, 42, 161, 0, 104, 94, 171, 0, ++ 10, 155, 1, 12, 82, 15, 0, 23, 161, 0, 104, 94, 135, 0, 42, 151, 0, ++ 104, 94, 135, 0, 74, 153, 3, 191, 222, 2, 240, 10, 161, 3, 176, 222, ++ 2, 240, 10, 157, 3, 191, 222, 2, 240, 10, 159, 3, 177, 94, 2, 240, 10, ++ 157, 3, 191, 222, 2, 240, 10, 159, 3, 179, 94, 2, 240, 10, 157, 3, 191, ++ 222, 2, 240, 10, 159, 1, 188, 96, 3, 0, 75, 128, 3, 191, 222, 2, 240, ++ 10, 162, 1, 188, 96, 3, 0, 139, 128, 3, 191, 222, 2, 240, 10, 162, 1, ++ 188, 96, 3, 0, 43, 128, 3, 134, 222, 2, 240, 12, 156, 3, 171, 94, 2, ++ 240, 10, 167, 1, 240, 82, 19, 0, 17, 134, 1, 165, 224, 10, 48, 17, 128, ++ 3, 191, 222, 2, 240, 10, 201, 3, 169, 222, 2, 240, 10, 173, 0, 104, ++ 222, 171, 0, 74, 201, 0, 176, 82, 59, 0, 23, 159, 0, 176, 82, 59, 0, ++ 23, 190, 1, 188, 96, 3, 0, 40, 8, 3, 191, 222, 2, 240, 10, 201, 2, 135, ++ 94, 83, 0, 10, 214, 3, 160, 222, 2, 240, 10, 184, 3, 191, 222, 2, 240, ++ 7, 203, 1, 144, 96, 10, 9, 16, 72, 0, 176, 82, 59, 0, 23, 159, 0, 176, ++ 82, 59, 0, 23, 190, 1, 158, 94, 131, 0, 176, 235, 1, 6, 82, 15, 0, 23, ++ 161, 0, 184, 94, 135, 0, 55, 161, 1, 130, 222, 134, 245, 119, 171, 1, ++ 188, 97, 3, 0, 48, 128, 0, 232, 82, 58, 243, 247, 162, 0, 107, 210, ++ 58, 243, 234, 187, 0, 232, 94, 126, 145, 215, 162, 0, 144, 94, 139, ++ 0, 151, 161, 1, 188, 96, 35, 1, 16, 100, 0, 107, 82, 58, 243, 234, 198, ++ 1, 24, 94, 135, 0, 23, 162, 1, 10, 94, 135, 0, 23, 163, 0, 136, 96, ++ 6, 244, 87, 162, 0, 224, 65, 146, 244, 112, 100, 0, 176, 88, 2, 244, ++ 86, 0, 0, 107, 222, 250, 145, 202, 201, 0, 176, 82, 59, 0, 23, 190, ++ 3, 191, 222, 2, 240, 10, 201, 0, 2, 94, 2, 240, 22, 89, 0, 176, 32, ++ 35, 0, 40, 8, 0, 176, 82, 59, 0, 23, 159, 3, 32, 222, 2, 240, 10, 214, ++ 2, 7, 94, 83, 0, 10, 205, 1, 128, 224, 2, 9, 16, 72, 3, 191, 222, 2, ++ 240, 10, 214, 0, 104, 222, 95, 0, 10, 211, 2, 26, 84, 7, 0, 10, 209, ++ 1, 3, 192, 39, 0, 23, 161, 1, 130, 94, 134, 16, 208, 134, 1, 2, 192, ++ 39, 0, 23, 161, 0, 224, 66, 42, 244, 48, 138, 1, 128, 224, 4, 255, 135, ++ 252, 3, 169, 222, 2, 240, 10, 214, 0, 176, 94, 71, 0, 16, 128, 1, 8, ++ 94, 79, 0, 23, 161, 0, 104, 94, 135, 0, 43, 4, 3, 171, 94, 2, 240, 11, ++ 8, 2, 0, 82, 23, 0, 10, 238, 0, 104, 222, 171, 0, 74, 220, 0, 224, 2, ++ 83, 0, 32, 148, 2, 134, 94, 83, 0, 11, 54, 2, 132, 82, 15, 0, 13, 12, ++ 2, 132, 210, 15, 0, 10, 225, 3, 172, 94, 2, 240, 10, 236, 3, 191, 222, ++ 2, 240, 10, 247, 3, 44, 94, 2, 240, 10, 247, 0, 104, 94, 79, 4, 10, ++ 236, 1, 6, 210, 15, 0, 23, 161, 0, 128, 142, 207, 1, 151, 162, 0, 224, ++ 1, 94, 13, 176, 100, 1, 129, 222, 134, 195, 246, 31, 1, 135, 222, 134, ++ 36, 145, 36, 0, 104, 48, 83, 255, 234, 236, 0, 176, 68, 103, 0, 12, ++ 21, 2, 0, 94, 135, 0, 10, 236, 0, 224, 68, 101, 130, 140, 21, 0, 104, ++ 94, 79, 2, 11, 54, 3, 191, 222, 2, 240, 11, 35, 3, 30, 222, 2, 240, ++ 10, 244, 3, 49, 94, 2, 240, 10, 244, 0, 104, 222, 171, 0, 74, 244, 0, ++ 128, 142, 207, 1, 151, 162, 0, 224, 1, 94, 13, 176, 100, 1, 129, 224, ++ 2, 195, 246, 31, 0, 104, 222, 171, 0, 74, 249, 0, 224, 2, 63, 0, 32, ++ 143, 3, 191, 222, 2, 240, 10, 252, 0, 104, 94, 171, 0, 74, 252, 2, 128, ++ 82, 47, 0, 11, 54, 2, 2, 65, 7, 0, 10, 252, 0, 104, 94, 79, 4, 11, 54, ++ 0, 104, 94, 79, 2, 139, 54, 2, 6, 222, 83, 0, 11, 1, 0, 40, 224, 30, ++ 244, 11, 1, 0, 160, 68, 183, 3, 225, 69, 0, 176, 5, 19, 0, 23, 161, ++ 0, 224, 94, 132, 40, 161, 70, 2, 132, 65, 7, 0, 11, 54, 1, 128, 96, ++ 6, 242, 151, 148, 3, 191, 222, 2, 240, 11, 54, 3, 43, 94, 2, 240, 11, ++ 54, 0, 104, 94, 79, 5, 171, 35, 0, 104, 94, 79, 5, 43, 35, 3, 191, 222, ++ 2, 240, 11, 54, 0, 104, 222, 171, 0, 75, 17, 0, 109, 142, 207, 0, 43, ++ 17, 1, 188, 96, 3, 0, 10, 181, 1, 130, 96, 2, 245, 215, 174, 2, 128, ++ 94, 255, 0, 11, 15, 0, 104, 43, 79, 0, 11, 17, 0, 224, 68, 101, 90, ++ 74, 211, 0, 104, 43, 107, 255, 203, 17, 0, 224, 43, 107, 0, 42, 218, ++ 2, 6, 94, 83, 0, 11, 20, 0, 224, 2, 99, 0, 32, 152, 3, 191, 222, 2, ++ 240, 11, 54, 3, 35, 222, 2, 240, 11, 30, 1, 41, 80, 11, 0, 23, 163, ++ 0, 104, 222, 143, 5, 43, 30, 2, 6, 128, 199, 0, 11, 25, 1, 130, 224, ++ 1, 134, 12, 48, 1, 135, 224, 2, 16, 112, 131, 1, 132, 96, 2, 9, 16, ++ 72, 0, 176, 94, 135, 0, 23, 161, 0, 110, 224, 3, 0, 43, 29, 3, 209, ++ 222, 2, 240, 11, 30, 0, 104, 222, 171, 0, 75, 32, 0, 224, 2, 39, 0, ++ 32, 137, 0, 104, 94, 79, 0, 11, 54, 0, 104, 94, 79, 1, 11, 54, 0, 104, ++ 94, 79, 5, 139, 54, 0, 128, 142, 207, 1, 151, 162, 0, 224, 1, 94, 13, ++ 176, 101, 0, 32, 218, 127, 20, 11, 54, 2, 128, 71, 199, 0, 11, 130, ++ 3, 41, 222, 2, 240, 11, 44, 1, 2, 222, 175, 0, 23, 161, 1, 6, 82, 15, ++ 0, 23, 162, 0, 56, 94, 134, 244, 75, 54, 1, 130, 222, 138, 245, 119, ++ 171, 0, 176, 82, 35, 0, 17, 242, 0, 176, 82, 39, 0, 17, 243, 0, 176, ++ 82, 43, 0, 17, 244, 1, 6, 82, 15, 0, 23, 161, 0, 224, 94, 135, 0, 49, ++ 245, 0, 176, 0, 91, 0, 17, 240, 0, 176, 71, 195, 0, 24, 0, 1, 52, 199, ++ 199, 0, 23, 161, 0, 110, 222, 132, 2, 171, 54, 1, 188, 96, 3, 8, 16, ++ 66, 2, 131, 193, 7, 0, 11, 58, 3, 1, 222, 2, 240, 11, 57, 3, 181, 94, ++ 2, 240, 11, 58, 2, 128, 94, 83, 0, 13, 12, 0, 176, 64, 51, 0, 23, 161, ++ 1, 8, 159, 247, 0, 23, 162, 0, 104, 94, 139, 0, 107, 66, 0, 232, 64, ++ 49, 4, 151, 161, 2, 129, 31, 247, 0, 11, 66, 0, 176, 32, 147, 0, 23, ++ 161, 2, 128, 159, 247, 0, 11, 66, 0, 176, 94, 99, 0, 23, 161, 0, 110, ++ 94, 132, 2, 11, 132, 0, 176, 94, 135, 0, 7, 244, 1, 129, 96, 0, 255, ++ 135, 252, 2, 2, 192, 19, 0, 11, 72, 0, 224, 94, 132, 3, 71, 244, 1, ++ 129, 96, 4, 255, 135, 252, 2, 1, 31, 247, 0, 11, 125, 1, 3, 94, 83, ++ 0, 23, 161, 1, 135, 222, 132, 255, 135, 252, 3, 134, 222, 2, 240, 12, ++ 156, 0, 2, 94, 2, 240, 18, 47, 3, 133, 94, 2, 240, 11, 75, 1, 142, 96, ++ 2, 61, 17, 232, 1, 7, 199, 131, 0, 23, 161, 1, 130, 94, 132, 255, 135, ++ 252, 2, 1, 159, 247, 0, 11, 84, 1, 3, 199, 151, 0, 23, 161, 1, 130, ++ 94, 132, 255, 167, 253, 0, 176, 32, 51, 0, 23, 161, 1, 142, 94, 132, ++ 255, 167, 253, 3, 42, 94, 2, 240, 11, 92, 0, 2, 94, 2, 240, 14, 128, ++ 3, 41, 222, 2, 240, 11, 91, 3, 1, 222, 2, 240, 11, 91, 1, 130, 224, ++ 6, 13, 144, 108, 3, 191, 222, 2, 240, 8, 163, 1, 188, 96, 3, 0, 17, ++ 236, 1, 188, 96, 15, 0, 17, 232, 1, 132, 96, 4, 255, 167, 253, 0, 176, ++ 64, 39, 0, 7, 246, 0, 176, 64, 107, 0, 7, 248, 0, 176, 64, 111, 0, 7, ++ 249, 0, 176, 64, 43, 0, 7, 247, 1, 188, 96, 27, 13, 215, 161, 0, 2, ++ 94, 2, 240, 1, 39, 0, 176, 64, 103, 0, 23, 162, 1, 188, 96, 27, 13, ++ 247, 161, 0, 2, 94, 2, 240, 1, 39, 0, 176, 64, 103, 0, 23, 161, 0, 232, ++ 94, 138, 244, 55, 162, 0, 225, 94, 138, 244, 87, 161, 0, 224, 222, 134, ++ 244, 87, 161, 0, 152, 94, 135, 0, 183, 161, 1, 188, 94, 134, 1, 71, ++ 247, 0, 104, 31, 51, 0, 11, 121, 1, 143, 96, 6, 1, 39, 246, 0, 104, ++ 31, 51, 0, 43, 118, 0, 176, 31, 199, 0, 23, 161, 0, 2, 94, 2, 240, 1, ++ 39, 0, 160, 64, 100, 249, 215, 162, 0, 184, 94, 136, 254, 23, 161, 3, ++ 191, 222, 2, 240, 11, 119, 0, 160, 65, 56, 254, 23, 161, 0, 104, 222, ++ 135, 0, 11, 121, 1, 143, 96, 2, 1, 39, 246, 1, 132, 96, 4, 255, 167, ++ 253, 0, 2, 94, 2, 240, 14, 156, 1, 188, 99, 255, 31, 215, 168, 0, 2, ++ 94, 2, 240, 16, 147, 0, 2, 94, 2, 240, 14, 128, 1, 168, 96, 10, 0, 144, ++ 4, 2, 1, 31, 247, 0, 22, 69, 0, 168, 64, 19, 0, 80, 4, 3, 191, 222, ++ 2, 240, 7, 33, 0, 224, 2, 135, 0, 32, 161, 3, 191, 222, 2, 240, 11, ++ 133, 0, 224, 2, 11, 0, 32, 130, 3, 169, 222, 2, 240, 13, 12, 1, 132, ++ 96, 6, 9, 16, 72, 1, 132, 224, 6, 9, 16, 72, 3, 191, 222, 2, 240, 13, ++ 12, 3, 43, 94, 2, 240, 11, 172, 0, 104, 222, 79, 6, 171, 141, 0, 224, ++ 2, 59, 0, 32, 142, 3, 191, 222, 2, 240, 11, 142, 0, 224, 2, 55, 0, 32, ++ 141, 3, 35, 222, 2, 240, 11, 176, 0, 104, 222, 78, 241, 203, 176, 2, ++ 6, 128, 199, 0, 11, 146, 1, 130, 224, 1, 134, 12, 48, 1, 135, 224, 2, ++ 16, 112, 131, 1, 132, 96, 2, 9, 16, 72, 0, 176, 94, 135, 0, 23, 161, ++ 0, 110, 224, 3, 0, 43, 150, 3, 209, 222, 2, 240, 11, 151, 0, 104, 94, ++ 79, 6, 43, 170, 1, 188, 96, 3, 0, 8, 51, 3, 41, 94, 2, 240, 11, 156, ++ 2, 3, 222, 179, 0, 11, 157, 1, 145, 96, 26, 132, 244, 39, 1, 131, 224, ++ 2, 245, 151, 172, 2, 2, 0, 191, 0, 11, 169, 2, 6, 171, 211, 0, 11, 162, ++ 2, 3, 69, 175, 0, 11, 164, 1, 133, 224, 6, 45, 113, 107, 3, 191, 222, ++ 2, 240, 11, 164, 2, 3, 69, 111, 0, 11, 164, 1, 133, 224, 6, 43, 113, ++ 91, 2, 4, 94, 179, 0, 11, 169, 1, 135, 224, 2, 16, 112, 131, 1, 131, ++ 224, 2, 9, 16, 72, 0, 2, 94, 2, 240, 21, 147, 3, 191, 222, 2, 240, 11, ++ 176, 2, 5, 80, 11, 0, 11, 176, 1, 130, 96, 6, 9, 16, 72, 3, 191, 222, ++ 2, 240, 11, 176, 0, 2, 94, 2, 240, 11, 183, 0, 104, 222, 79, 6, 43, ++ 176, 0, 224, 2, 79, 0, 32, 147, 3, 191, 222, 2, 240, 11, 176, 3, 171, ++ 94, 2, 240, 11, 178, 2, 4, 65, 7, 0, 11, 181, 2, 131, 65, 7, 0, 10, ++ 79, 3, 191, 222, 2, 240, 11, 181, 2, 132, 65, 7, 0, 10, 79, 1, 128, ++ 96, 6, 242, 151, 148, 3, 191, 222, 2, 240, 10, 79, 2, 135, 0, 195, 0, ++ 11, 187, 0, 104, 210, 19, 0, 11, 187, 1, 188, 96, 3, 0, 17, 131, 1, ++ 188, 96, 3, 0, 17, 130, 0, 2, 222, 2, 240, 0, 0, 3, 159, 94, 2, 240, ++ 11, 191, 3, 158, 222, 2, 240, 14, 46, 2, 3, 94, 83, 0, 14, 46, 1, 12, ++ 129, 67, 0, 23, 161, 0, 104, 222, 135, 0, 43, 196, 1, 0, 1, 99, 0, 23, ++ 161, 1, 2, 192, 39, 0, 23, 162, 0, 56, 222, 134, 244, 75, 180, 3, 171, ++ 94, 2, 240, 11, 198, 2, 0, 82, 23, 0, 11, 180, 2, 128, 82, 47, 0, 11, ++ 200, 3, 51, 94, 2, 240, 14, 46, 2, 24, 29, 243, 0, 11, 236, 1, 188, ++ 96, 27, 6, 16, 101, 1, 188, 96, 3, 27, 183, 164, 0, 2, 94, 2, 240, 1, ++ 114, 0, 176, 94, 143, 0, 23, 166, 0, 104, 222, 147, 27, 171, 232, 2, ++ 7, 193, 151, 0, 11, 213, 1, 56, 90, 7, 0, 23, 161, 1, 60, 90, 7, 0, ++ 23, 162, 1, 188, 90, 10, 244, 87, 162, 1, 60, 90, 11, 0, 23, 163, 1, ++ 188, 90, 14, 244, 119, 163, 3, 191, 222, 2, 240, 11, 216, 1, 60, 90, ++ 3, 0, 23, 161, 0, 176, 90, 7, 0, 23, 162, 0, 176, 90, 11, 0, 23, 163, ++ 0, 109, 94, 135, 0, 139, 226, 1, 188, 97, 191, 10, 23, 165, 0, 104, ++ 222, 138, 244, 171, 221, 1, 188, 96, 39, 19, 87, 165, 0, 104, 94, 142, ++ 244, 171, 225, 1, 188, 96, 95, 0, 23, 165, 0, 104, 222, 138, 244, 171, ++ 226, 1, 188, 96, 23, 30, 87, 165, 0, 104, 222, 142, 244, 171, 226, 3, ++ 191, 222, 2, 240, 12, 36, 0, 216, 94, 135, 0, 55, 161, 0, 225, 65, 150, ++ 244, 48, 101, 0, 225, 193, 151, 0, 48, 101, 1, 240, 65, 151, 0, 23, ++ 162, 0, 224, 94, 139, 0, 119, 162, 0, 109, 94, 138, 244, 203, 203, 0, ++ 232, 64, 51, 0, 151, 165, 0, 110, 94, 150, 0, 76, 36, 0, 176, 29, 239, ++ 0, 23, 161, 0, 104, 222, 132, 10, 14, 46, 2, 60, 82, 63, 0, 11, 253, ++ 1, 60, 82, 63, 0, 23, 161, 0, 104, 222, 132, 4, 140, 34, 1, 188, 96, ++ 3, 22, 16, 100, 1, 188, 96, 27, 6, 48, 101, 0, 104, 94, 135, 0, 43, ++ 249, 0, 176, 90, 3, 0, 23, 162, 0, 104, 222, 138, 192, 12, 34, 0, 224, ++ 65, 151, 0, 48, 101, 0, 224, 65, 147, 0, 48, 100, 0, 232, 94, 135, 0, ++ 87, 161, 0, 106, 94, 135, 0, 43, 242, 0, 104, 94, 135, 0, 11, 254, 1, ++ 56, 90, 3, 0, 23, 161, 1, 56, 88, 3, 0, 23, 162, 0, 104, 222, 134, 244, ++ 76, 34, 3, 191, 222, 2, 240, 11, 254, 2, 133, 193, 7, 0, 14, 46, 1, ++ 188, 96, 27, 6, 16, 101, 1, 188, 96, 3, 5, 183, 164, 0, 2, 94, 2, 240, ++ 1, 114, 2, 128, 0, 195, 0, 12, 34, 1, 188, 96, 19, 20, 23, 166, 0, 224, ++ 1, 127, 0, 183, 165, 0, 109, 94, 150, 244, 204, 6, 1, 188, 96, 19, 12, ++ 151, 165, 0, 104, 94, 148, 11, 204, 38, 0, 176, 1, 123, 0, 16, 101, ++ 0, 176, 82, 39, 0, 23, 162, 0, 176, 82, 43, 0, 23, 163, 0, 104, 65, ++ 148, 11, 236, 17, 0, 104, 222, 142, 208, 76, 13, 0, 104, 94, 138, 208, ++ 44, 34, 0, 224, 65, 151, 0, 176, 101, 0, 109, 65, 150, 244, 204, 10, ++ 1, 188, 96, 19, 12, 144, 101, 3, 191, 222, 2, 240, 12, 10, 0, 224, 2, ++ 139, 0, 32, 162, 0, 176, 1, 127, 0, 16, 101, 0, 176, 82, 35, 0, 22, ++ 128, 0, 176, 82, 39, 0, 22, 129, 0, 176, 82, 43, 0, 22, 130, 0, 128, ++ 142, 207, 1, 151, 162, 0, 224, 1, 94, 13, 176, 100, 2, 3, 88, 127, 0, ++ 12, 27, 1, 188, 96, 47, 0, 55, 161, 3, 191, 222, 2, 240, 12, 28, 1, ++ 188, 82, 2, 242, 247, 161, 1, 169, 94, 2, 244, 54, 131, 0, 144, 68, ++ 103, 1, 22, 132, 2, 2, 129, 171, 0, 12, 32, 0, 104, 222, 147, 5, 172, ++ 33, 1, 132, 96, 6, 208, 150, 132, 0, 176, 94, 151, 0, 0, 95, 2, 7, 129, ++ 171, 0, 12, 36, 1, 128, 96, 6, 242, 151, 148, 3, 171, 94, 2, 240, 7, ++ 224, 3, 191, 222, 2, 240, 10, 79, 0, 224, 2, 143, 0, 32, 163, 3, 191, ++ 222, 2, 240, 11, 180, 3, 131, 94, 2, 240, 12, 42, 0, 109, 64, 51, 3, ++ 140, 40, 0, 109, 64, 51, 3, 139, 180, 3, 43, 94, 2, 240, 14, 50, 3, ++ 191, 222, 2, 240, 7, 224, 3, 43, 94, 2, 240, 12, 50, 0, 224, 2, 51, ++ 0, 32, 140, 2, 6, 129, 171, 0, 12, 49, 1, 131, 224, 5, 134, 12, 48, ++ 3, 191, 222, 2, 240, 7, 226, 0, 224, 2, 75, 0, 32, 146, 0, 136, 0, 35, ++ 0, 55, 162, 0, 224, 94, 136, 0, 247, 162, 0, 224, 0, 26, 244, 81, 137, ++ 1, 134, 224, 6, 48, 17, 128, 3, 191, 222, 2, 240, 11, 176, 3, 43, 94, ++ 2, 240, 12, 51, 0, 224, 19, 83, 0, 36, 212, 3, 191, 222, 2, 240, 7, ++ 219, 2, 4, 82, 71, 0, 11, 176, 1, 188, 96, 31, 16, 240, 100, 1, 188, ++ 96, 3, 1, 119, 161, 1, 188, 99, 255, 31, 231, 147, 0, 224, 65, 134, ++ 244, 48, 101, 1, 188, 99, 255, 31, 246, 0, 0, 224, 94, 135, 0, 119, ++ 161, 0, 2, 94, 2, 240, 15, 24, 2, 0, 192, 119, 0, 11, 176, 1, 41, 64, ++ 119, 0, 23, 162, 0, 109, 94, 139, 4, 203, 176, 0, 232, 94, 139, 4, 214, ++ 0, 1, 188, 96, 31, 5, 240, 99, 0, 224, 65, 142, 192, 16, 99, 2, 0, 214, ++ 3, 0, 11, 176, 2, 6, 86, 3, 0, 11, 176, 1, 132, 224, 6, 245, 151, 172, ++ 1, 22, 214, 3, 0, 23, 162, 0, 136, 94, 139, 0, 119, 162, 0, 224, 1, ++ 158, 244, 80, 101, 0, 176, 65, 151, 0, 4, 194, 1, 188, 96, 43, 24, 23, ++ 161, 0, 176, 90, 15, 0, 23, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, ++ 43, 24, 55, 161, 0, 176, 90, 19, 0, 23, 162, 0, 2, 94, 2, 240, 1, 43, ++ 0, 176, 65, 139, 0, 4, 217, 3, 191, 222, 2, 240, 11, 176, 3, 162, 222, ++ 2, 240, 0, 194, 3, 163, 222, 2, 240, 12, 117, 0, 224, 1, 255, 0, 32, ++ 127, 1, 188, 96, 3, 0, 23, 163, 3, 191, 222, 2, 240, 12, 119, 1, 135, ++ 96, 4, 3, 16, 160, 1, 188, 96, 3, 0, 81, 228, 0, 176, 71, 147, 0, 24, ++ 0, 1, 188, 96, 3, 2, 144, 4, 1, 188, 98, 15, 0, 17, 224, 1, 188, 96, ++ 15, 1, 49, 232, 0, 176, 71, 163, 0, 24, 0, 1, 188, 96, 15, 0, 17, 232, ++ 1, 188, 96, 3, 1, 49, 236, 0, 176, 71, 179, 0, 24, 0, 1, 188, 96, 3, ++ 0, 17, 236, 1, 132, 96, 6, 9, 16, 72, 0, 32, 96, 30, 9, 12, 108, 0, ++ 224, 1, 251, 0, 32, 126, 3, 191, 222, 2, 240, 12, 128, 1, 188, 96, 3, ++ 14, 215, 161, 1, 20, 0, 99, 0, 23, 162, 0, 224, 94, 134, 244, 80, 101, ++ 0, 224, 90, 3, 0, 54, 128, 2, 3, 0, 199, 0, 12, 114, 3, 169, 94, 2, ++ 240, 12, 119, 2, 145, 80, 159, 0, 12, 118, 1, 145, 96, 26, 132, 244, ++ 39, 3, 191, 222, 2, 240, 12, 118, 0, 224, 1, 255, 0, 32, 127, 1, 188, ++ 96, 3, 0, 55, 163, 3, 35, 222, 2, 240, 12, 128, 1, 131, 224, 2, 9, 16, ++ 72, 1, 132, 96, 2, 245, 151, 172, 1, 188, 96, 3, 0, 10, 187, 1, 188, ++ 96, 3, 0, 23, 142, 2, 6, 128, 199, 0, 12, 126, 1, 130, 224, 1, 134, ++ 12, 48, 1, 135, 224, 2, 16, 112, 131, 1, 130, 96, 2, 9, 16, 72, 3, 208, ++ 222, 2, 240, 12, 129, 3, 208, 94, 2, 240, 12, 130, 1, 130, 224, 2, 9, ++ 16, 72, 3, 213, 222, 2, 240, 12, 132, 1, 188, 96, 3, 0, 16, 180, 1, ++ 188, 96, 3, 0, 247, 161, 0, 104, 0, 167, 0, 12, 136, 1, 133, 66, 26, ++ 244, 55, 161, 0, 2, 94, 2, 240, 1, 39, 0, 176, 64, 103, 0, 23, 165, ++ 1, 188, 99, 255, 31, 247, 162, 0, 2, 94, 2, 240, 1, 43, 0, 136, 96, ++ 7, 1, 87, 164, 0, 184, 94, 134, 244, 151, 161, 0, 2, 94, 2, 240, 1, ++ 43, 2, 131, 194, 31, 0, 12, 143, 0, 2, 94, 2, 240, 17, 69, 2, 132, 69, ++ 35, 0, 12, 145, 3, 208, 222, 2, 240, 12, 147, 0, 104, 94, 143, 0, 0, ++ 2, 0, 32, 224, 30, 9, 12, 151, 0, 176, 94, 151, 0, 20, 46, 3, 191, 222, ++ 2, 240, 3, 107, 0, 168, 65, 35, 0, 240, 72, 3, 191, 222, 2, 240, 0, ++ 2, 1, 131, 96, 2, 9, 16, 72, 0, 224, 2, 19, 0, 32, 132, 3, 191, 222, ++ 2, 240, 12, 159, 1, 188, 96, 7, 0, 16, 66, 0, 110, 64, 48, 2, 12, 159, ++ 0, 224, 2, 119, 0, 32, 157, 0, 2, 94, 2, 240, 23, 20, 3, 163, 94, 2, ++ 240, 10, 79, 3, 198, 222, 2, 240, 12, 162, 3, 42, 222, 2, 240, 12, 169, ++ 0, 176, 48, 35, 0, 8, 8, 0, 176, 48, 39, 0, 8, 9, 0, 176, 48, 43, 0, ++ 8, 10, 0, 176, 48, 47, 0, 8, 11, 0, 176, 48, 51, 0, 23, 159, 3, 191, ++ 222, 2, 240, 13, 12, 1, 132, 224, 6, 9, 16, 72, 3, 191, 222, 2, 240, ++ 13, 12, 2, 6, 129, 171, 0, 12, 174, 2, 129, 176, 195, 0, 0, 189, 2, ++ 131, 48, 195, 0, 0, 189, 2, 132, 69, 35, 0, 0, 189, 3, 32, 222, 2, 240, ++ 12, 182, 0, 104, 160, 199, 0, 12, 179, 1, 188, 96, 159, 2, 23, 161, ++ 0, 224, 68, 102, 244, 40, 49, 0, 107, 68, 101, 6, 44, 183, 0, 32, 225, ++ 2, 9, 0, 189, 0, 2, 94, 2, 240, 13, 40, 1, 188, 96, 3, 0, 8, 49, 0, ++ 32, 227, 138, 9, 0, 189, 2, 132, 69, 35, 0, 0, 189, 0, 176, 94, 135, ++ 0, 23, 161, 3, 145, 94, 2, 240, 0, 189, 3, 150, 222, 2, 240, 0, 189, ++ 3, 150, 94, 2, 240, 0, 189, 0, 2, 94, 2, 240, 13, 40, 0, 225, 13, 178, ++ 40, 227, 108, 0, 224, 141, 183, 0, 3, 109, 1, 188, 96, 3, 0, 17, 71, ++ 1, 188, 96, 3, 0, 96, 32, 0, 104, 1, 115, 0, 12, 210, 1, 188, 96, 19, ++ 8, 144, 230, 0, 2, 94, 2, 240, 1, 106, 0, 176, 1, 115, 0, 16, 228, 1, ++ 188, 96, 3, 0, 0, 6, 1, 188, 96, 3, 0, 0, 92, 1, 188, 96, 3, 1, 215, ++ 130, 1, 210, 222, 8, 119, 240, 224, 0, 176, 15, 3, 0, 16, 225, 0, 176, ++ 0, 71, 0, 16, 134, 0, 176, 15, 31, 0, 16, 138, 1, 188, 96, 3, 0, 55, ++ 129, 0, 2, 94, 2, 240, 16, 105, 1, 144, 96, 10, 9, 16, 72, 1, 188, 97, ++ 3, 0, 48, 128, 3, 191, 222, 2, 240, 0, 2, 1, 188, 96, 3, 0, 48, 66, ++ 1, 135, 224, 2, 36, 113, 35, 0, 2, 94, 2, 240, 20, 216, 3, 151, 94, ++ 2, 240, 13, 60, 3, 18, 94, 2, 240, 12, 213, 1, 188, 96, 3, 0, 64, 32, ++ 1, 188, 96, 3, 0, 11, 128, 1, 188, 96, 3, 0, 17, 73, 1, 188, 97, 131, ++ 0, 17, 37, 0, 176, 0, 123, 0, 17, 39, 1, 188, 96, 19, 12, 128, 94, 1, ++ 188, 96, 19, 12, 128, 95, 1, 128, 224, 6, 245, 215, 174, 1, 7, 193, ++ 7, 0, 23, 161, 1, 128, 94, 134, 245, 119, 171, 1, 188, 96, 15, 0, 17, ++ 232, 1, 188, 98, 15, 0, 17, 224, 0, 2, 94, 2, 240, 12, 240, 1, 188, ++ 97, 207, 12, 16, 92, 1, 188, 96, 3, 0, 16, 93, 1, 188, 97, 207, 1, 240, ++ 94, 1, 188, 96, 59, 10, 240, 95, 0, 2, 94, 2, 240, 20, 70, 1, 188, 96, ++ 3, 0, 8, 46, 2, 3, 0, 199, 0, 0, 18, 1, 188, 96, 3, 0, 6, 178, 1, 188, ++ 96, 3, 0, 6, 183, 1, 188, 96, 3, 0, 6, 188, 1, 188, 96, 3, 0, 6, 193, ++ 3, 191, 222, 2, 240, 0, 18, 1, 188, 96, 67, 0, 23, 187, 0, 160, 65, ++ 34, 247, 112, 72, 1, 188, 99, 255, 31, 240, 84, 1, 188, 99, 255, 31, ++ 240, 85, 1, 188, 99, 191, 31, 240, 86, 1, 188, 99, 255, 15, 240, 87, ++ 0, 2, 94, 2, 240, 23, 20, 1, 135, 224, 6, 36, 113, 35, 1, 188, 96, 3, ++ 0, 16, 84, 1, 188, 96, 3, 0, 16, 85, 1, 188, 96, 3, 0, 16, 86, 1, 188, ++ 96, 3, 0, 16, 87, 1, 188, 96, 15, 0, 32, 23, 1, 6, 193, 7, 0, 23, 161, ++ 1, 130, 94, 132, 2, 224, 23, 1, 7, 65, 7, 0, 23, 161, 0, 184, 94, 135, ++ 0, 55, 161, 1, 128, 222, 135, 0, 0, 22, 0, 2, 222, 2, 240, 0, 0, 2, ++ 133, 192, 55, 0, 0, 2, 0, 2, 94, 2, 240, 18, 47, 2, 134, 64, 55, 0, ++ 13, 3, 0, 224, 2, 27, 0, 32, 134, 1, 188, 96, 3, 1, 11, 128, 3, 134, ++ 222, 2, 240, 12, 156, 2, 135, 192, 55, 0, 12, 156, 0, 2, 94, 2, 240, ++ 23, 226, 3, 191, 222, 2, 240, 0, 18, 1, 184, 96, 10, 4, 144, 36, 3, ++ 170, 94, 2, 240, 13, 15, 1, 88, 96, 3, 0, 16, 42, 1, 188, 96, 3, 2, ++ 144, 4, 0, 176, 64, 19, 0, 24, 0, 1, 131, 96, 2, 9, 16, 72, 1, 128, ++ 96, 0, 255, 167, 253, 0, 2, 94, 2, 240, 18, 47, 3, 133, 94, 2, 240, ++ 13, 19, 1, 188, 98, 15, 0, 17, 224, 1, 188, 96, 15, 1, 49, 232, 0, 176, ++ 71, 163, 0, 24, 0, 1, 188, 96, 15, 0, 17, 232, 1, 188, 96, 3, 1, 87, ++ 161, 0, 232, 94, 135, 0, 55, 161, 0, 104, 222, 135, 0, 13, 26, 1, 188, ++ 96, 3, 2, 144, 4, 0, 176, 64, 19, 0, 24, 0, 1, 188, 96, 3, 1, 49, 236, ++ 0, 176, 71, 179, 0, 24, 0, 1, 188, 96, 3, 0, 17, 236, 3, 36, 222, 2, ++ 240, 7, 33, 1, 134, 96, 6, 245, 119, 171, 0, 2, 94, 2, 240, 13, 40, ++ 1, 128, 96, 6, 16, 48, 129, 0, 176, 94, 135, 0, 23, 161, 1, 128, 96, ++ 2, 16, 48, 129, 3, 191, 222, 2, 240, 7, 33, 2, 6, 1, 171, 0, 13, 42, ++ 1, 128, 96, 1, 134, 12, 48, 1, 188, 97, 3, 0, 16, 128, 0, 176, 66, 3, ++ 0, 24, 0, 0, 110, 224, 3, 0, 45, 45, 3, 80, 94, 2, 240, 13, 48, 0, 1, ++ 94, 2, 240, 0, 0, 3, 191, 222, 2, 240, 3, 145, 1, 132, 96, 2, 245, 151, ++ 172, 1, 188, 96, 3, 0, 10, 187, 0, 168, 65, 35, 4, 240, 72, 1, 130, ++ 96, 2, 9, 16, 72, 2, 6, 222, 175, 0, 13, 55, 3, 213, 222, 2, 240, 13, ++ 55, 3, 80, 222, 2, 240, 13, 53, 1, 188, 96, 3, 0, 16, 180, 2, 132, 199, ++ 131, 0, 13, 58, 1, 188, 96, 11, 0, 17, 224, 1, 142, 96, 2, 245, 119, ++ 171, 0, 2, 222, 2, 240, 0, 0, 3, 162, 222, 2, 240, 0, 189, 2, 188, 66, ++ 135, 0, 13, 67, 1, 188, 96, 3, 0, 55, 164, 1, 188, 96, 3, 31, 247, 163, ++ 1, 20, 0, 99, 0, 23, 162, 0, 136, 96, 6, 244, 87, 162, 3, 191, 222, ++ 2, 240, 13, 72, 0, 136, 96, 7, 1, 23, 164, 1, 188, 99, 255, 0, 23, 163, ++ 1, 20, 0, 99, 0, 23, 162, 0, 224, 94, 139, 1, 23, 162, 0, 136, 96, 6, ++ 244, 87, 162, 1, 188, 96, 19, 27, 144, 101, 1, 188, 96, 27, 24, 80, ++ 100, 1, 188, 96, 3, 0, 23, 165, 0, 32, 194, 134, 244, 141, 82, 0, 224, ++ 65, 151, 6, 208, 101, 0, 224, 65, 147, 1, 240, 100, 0, 224, 94, 151, ++ 0, 55, 165, 0, 136, 94, 147, 0, 55, 164, 0, 32, 94, 146, 244, 109, 113, ++ 3, 191, 222, 2, 240, 13, 75, 0, 104, 222, 146, 244, 77, 87, 0, 104, ++ 0, 131, 0, 109, 87, 3, 160, 222, 2, 240, 13, 87, 0, 32, 193, 35, 22, ++ 13, 76, 0, 2, 94, 2, 240, 13, 40, 0, 109, 222, 147, 32, 13, 109, 2, ++ 3, 0, 199, 0, 13, 97, 0, 109, 222, 151, 0, 141, 97, 1, 188, 96, 3, 0, ++ 22, 8, 1, 188, 96, 3, 0, 22, 9, 1, 188, 96, 3, 0, 22, 10, 1, 188, 96, ++ 3, 0, 22, 11, 1, 188, 96, 3, 0, 22, 12, 1, 188, 96, 3, 0, 22, 13, 1, ++ 188, 96, 3, 0, 22, 14, 2, 0, 90, 195, 0, 13, 108, 2, 60, 90, 159, 0, ++ 13, 108, 0, 104, 0, 131, 0, 109, 108, 3, 133, 222, 2, 240, 0, 189, 3, ++ 133, 94, 2, 240, 0, 189, 3, 162, 222, 2, 240, 0, 189, 3, 163, 222, 2, ++ 240, 0, 189, 3, 151, 222, 2, 240, 0, 189, 0, 176, 65, 151, 0, 16, 96, ++ 1, 145, 96, 10, 132, 244, 39, 3, 191, 222, 2, 240, 3, 107, 1, 128, 96, ++ 2, 214, 22, 176, 0, 176, 94, 147, 0, 16, 161, 1, 131, 96, 2, 247, 247, ++ 191, 1, 188, 96, 3, 0, 48, 67, 3, 191, 222, 2, 240, 13, 76, 0, 104, ++ 128, 131, 0, 96, 189, 3, 191, 222, 2, 240, 12, 214, 2, 131, 194, 31, ++ 0, 0, 2, 0, 176, 94, 135, 0, 23, 161, 3, 208, 222, 2, 240, 6, 65, 1, ++ 188, 96, 3, 4, 16, 66, 3, 158, 222, 2, 240, 0, 18, 0, 176, 94, 63, 0, ++ 17, 69, 1, 188, 96, 3, 0, 23, 143, 0, 176, 94, 67, 0, 23, 133, 0, 176, ++ 94, 15, 0, 23, 144, 0, 2, 94, 2, 240, 13, 40, 3, 191, 222, 2, 240, 0, ++ 18, 0, 109, 64, 51, 5, 139, 181, 3, 172, 94, 2, 240, 13, 131, 0, 104, ++ 94, 79, 2, 141, 228, 0, 224, 2, 103, 0, 32, 153, 3, 191, 222, 2, 240, ++ 13, 228, 0, 104, 94, 79, 2, 141, 228, 2, 128, 48, 183, 0, 13, 135, 0, ++ 224, 2, 95, 0, 32, 151, 1, 128, 96, 5, 133, 172, 45, 0, 2, 94, 2, 240, ++ 14, 168, 1, 134, 96, 2, 245, 183, 173, 1, 130, 96, 2, 245, 215, 174, ++ 1, 188, 96, 3, 0, 10, 181, 3, 158, 222, 2, 240, 13, 153, 3, 33, 222, ++ 2, 240, 13, 153, 0, 224, 2, 111, 0, 32, 155, 0, 2, 94, 2, 240, 13, 40, ++ 1, 134, 96, 2, 9, 16, 72, 0, 168, 65, 35, 1, 48, 72, 1, 188, 96, 3, ++ 2, 16, 66, 2, 128, 68, 31, 0, 13, 152, 0, 176, 94, 63, 0, 17, 69, 1, ++ 188, 96, 3, 0, 23, 143, 0, 176, 94, 67, 0, 23, 133, 0, 176, 94, 15, ++ 0, 23, 144, 3, 191, 222, 2, 240, 13, 153, 0, 160, 68, 182, 240, 113, ++ 69, 2, 130, 0, 195, 0, 13, 228, 0, 176, 0, 115, 0, 23, 161, 0, 224, ++ 94, 134, 176, 23, 161, 0, 225, 94, 122, 244, 55, 158, 0, 225, 222, 119, ++ 0, 23, 157, 0, 225, 222, 115, 0, 23, 156, 0, 224, 222, 111, 0, 23, 155, ++ 3, 158, 222, 2, 240, 13, 168, 0, 110, 94, 110, 146, 78, 26, 0, 109, ++ 94, 110, 146, 77, 168, 0, 110, 94, 114, 146, 46, 26, 0, 109, 94, 114, ++ 146, 45, 168, 0, 110, 94, 118, 146, 14, 26, 0, 109, 94, 118, 146, 13, ++ 168, 0, 109, 222, 122, 145, 238, 26, 2, 0, 48, 111, 0, 13, 173, 0, 176, ++ 94, 123, 0, 12, 40, 0, 176, 94, 119, 0, 12, 41, 0, 176, 94, 115, 0, ++ 12, 42, 0, 176, 94, 111, 0, 12, 43, 2, 130, 1, 171, 0, 13, 190, 0, 176, ++ 68, 103, 0, 8, 45, 0, 176, 68, 107, 0, 8, 44, 0, 176, 68, 111, 0, 8, ++ 43, 0, 176, 68, 115, 0, 8, 42, 0, 104, 160, 182, 35, 45, 168, 0, 233, ++ 32, 182, 243, 215, 158, 0, 233, 160, 178, 243, 183, 157, 0, 233, 160, ++ 174, 243, 151, 156, 0, 232, 160, 170, 243, 119, 155, 0, 225, 94, 122, ++ 145, 247, 161, 0, 176, 94, 135, 0, 17, 25, 0, 225, 222, 118, 146, 17, ++ 26, 0, 225, 222, 114, 146, 49, 27, 0, 224, 222, 110, 146, 81, 28, 0, ++ 104, 222, 134, 35, 45, 183, 3, 191, 222, 2, 240, 13, 228, 0, 233, 82, ++ 62, 243, 215, 161, 0, 233, 210, 66, 243, 183, 162, 0, 233, 210, 70, ++ 243, 151, 163, 0, 232, 210, 74, 243, 119, 164, 0, 136, 14, 207, 0, 87, ++ 165, 0, 224, 1, 94, 244, 176, 100, 0, 233, 94, 134, 201, 167, 129, 0, ++ 233, 222, 138, 201, 199, 130, 0, 233, 222, 142, 201, 231, 131, 0, 232, ++ 222, 146, 202, 7, 132, 0, 128, 142, 207, 1, 151, 165, 1, 188, 96, 31, ++ 7, 119, 128, 0, 224, 94, 2, 13, 176, 101, 0, 136, 90, 15, 0, 247, 165, ++ 0, 176, 94, 151, 8, 23, 165, 1, 52, 218, 15, 0, 23, 166, 0, 233, 94, ++ 148, 240, 55, 165, 0, 232, 222, 152, 240, 87, 166, 1, 123, 222, 150, ++ 244, 215, 165, 0, 104, 94, 150, 208, 109, 228, 0, 232, 94, 150, 208, ++ 119, 166, 0, 176, 94, 151, 0, 22, 131, 0, 104, 90, 19, 0, 13, 214, 0, ++ 224, 90, 22, 244, 214, 133, 0, 104, 90, 27, 0, 13, 216, 0, 224, 90, ++ 30, 244, 214, 135, 0, 136, 94, 155, 0, 247, 161, 1, 52, 222, 155, 0, ++ 23, 162, 1, 188, 96, 3, 0, 23, 163, 1, 188, 96, 3, 0, 23, 164, 0, 105, ++ 222, 155, 0, 13, 224, 1, 188, 99, 255, 31, 247, 163, 1, 188, 99, 255, ++ 31, 247, 164, 1, 195, 222, 142, 244, 87, 162, 0, 233, 89, 54, 244, 54, ++ 77, 0, 233, 217, 58, 244, 86, 78, 0, 233, 217, 62, 244, 118, 79, 0, ++ 232, 217, 66, 244, 150, 80, 3, 30, 222, 2, 240, 14, 26, 3, 159, 94, ++ 2, 240, 14, 26, 0, 104, 94, 79, 2, 142, 26, 3, 44, 94, 2, 240, 14, 26, ++ 1, 188, 96, 27, 6, 208, 101, 1, 188, 96, 3, 0, 183, 164, 0, 2, 94, 2, ++ 240, 1, 114, 2, 0, 48, 111, 0, 13, 239, 0, 104, 94, 147, 0, 173, 239, ++ 0, 224, 48, 159, 0, 44, 39, 3, 191, 222, 2, 240, 24, 150, 0, 104, 222, ++ 147, 0, 174, 26, 2, 7, 193, 151, 0, 13, 245, 1, 60, 90, 7, 0, 23, 187, ++ 1, 60, 90, 11, 0, 23, 161, 1, 56, 90, 7, 0, 12, 28, 3, 191, 222, 2, ++ 240, 13, 248, 1, 56, 90, 7, 0, 23, 187, 1, 56, 90, 11, 0, 23, 161, 1, ++ 60, 90, 3, 0, 12, 28, 0, 176, 94, 135, 0, 12, 29, 0, 128, 142, 207, ++ 1, 151, 162, 0, 224, 1, 94, 13, 176, 100, 0, 176, 94, 239, 0, 22, 40, ++ 1, 129, 222, 134, 195, 246, 31, 0, 104, 48, 79, 255, 238, 1, 2, 0, 94, ++ 135, 0, 14, 1, 0, 136, 48, 79, 0, 113, 38, 0, 144, 48, 79, 1, 177, 40, ++ 0, 104, 48, 83, 255, 238, 5, 0, 176, 68, 103, 0, 12, 21, 2, 0, 94, 135, ++ 0, 14, 5, 0, 224, 68, 101, 130, 140, 21, 1, 135, 222, 134, 36, 145, ++ 36, 2, 6, 128, 243, 0, 14, 9, 1, 129, 224, 2, 195, 246, 31, 1, 135, ++ 224, 2, 36, 145, 36, 2, 0, 48, 111, 0, 14, 26, 0, 224, 48, 143, 0, 44, ++ 35, 2, 134, 128, 243, 0, 14, 13, 2, 129, 216, 127, 0, 14, 24, 0, 176, ++ 48, 119, 0, 23, 161, 0, 2, 94, 2, 240, 15, 1, 2, 128, 94, 139, 0, 14, ++ 24, 0, 232, 94, 105, 131, 151, 161, 0, 104, 94, 133, 131, 46, 20, 0, ++ 224, 48, 151, 0, 44, 37, 3, 191, 222, 2, 240, 14, 24, 0, 224, 48, 147, ++ 0, 44, 36, 1, 188, 96, 3, 0, 12, 27, 1, 188, 96, 7, 0, 16, 67, 3, 191, ++ 222, 2, 240, 13, 12, 0, 232, 94, 105, 131, 140, 25, 3, 191, 222, 2, ++ 240, 24, 150, 3, 171, 94, 2, 240, 7, 224, 3, 191, 222, 2, 240, 10, 79, ++ 3, 43, 94, 2, 240, 11, 180, 3, 191, 222, 2, 240, 7, 224, 3, 171, 94, ++ 2, 240, 14, 33, 3, 44, 94, 2, 240, 11, 180, 3, 191, 222, 2, 240, 14, ++ 50, 0, 176, 82, 35, 0, 17, 242, 0, 176, 82, 39, 0, 17, 243, 0, 176, ++ 82, 43, 0, 17, 244, 1, 188, 96, 3, 0, 145, 245, 1, 188, 96, 3, 8, 16, ++ 66, 0, 176, 0, 91, 0, 17, 240, 3, 191, 222, 2, 240, 7, 224, 1, 56, 82, ++ 63, 0, 23, 161, 2, 6, 94, 83, 0, 14, 43, 1, 56, 82, 75, 0, 23, 161, ++ 0, 104, 222, 135, 0, 142, 46, 3, 171, 94, 2, 240, 7, 224, 3, 191, 222, ++ 2, 240, 10, 79, 0, 104, 222, 79, 2, 14, 49, 2, 7, 129, 171, 0, 14, 49, ++ 1, 128, 96, 6, 242, 151, 148, 3, 171, 94, 2, 240, 7, 224, 2, 0, 0, 243, ++ 0, 14, 55, 2, 6, 222, 83, 0, 14, 55, 1, 24, 94, 131, 0, 23, 161, 0, ++ 104, 222, 135, 0, 174, 55, 1, 188, 96, 11, 2, 81, 66, 2, 0, 82, 23, ++ 0, 11, 180, 3, 191, 222, 2, 240, 10, 79, 1, 188, 96, 3, 0, 17, 131, ++ 1, 188, 96, 3, 0, 17, 130, 3, 44, 94, 2, 240, 14, 62, 1, 153, 224, 6, ++ 32, 17, 0, 3, 191, 222, 2, 240, 14, 66, 1, 25, 64, 47, 0, 23, 161, 0, ++ 104, 94, 135, 0, 11, 176, 1, 153, 222, 134, 32, 17, 0, 3, 49, 94, 2, ++ 240, 11, 176, 0, 160, 94, 59, 0, 151, 162, 0, 32, 94, 78, 244, 75, 176, ++ 1, 132, 96, 2, 9, 16, 72, 3, 191, 222, 2, 240, 11, 176, 3, 171, 94, ++ 2, 240, 14, 73, 0, 2, 94, 2, 240, 11, 183, 3, 191, 222, 2, 240, 11, ++ 176, 0, 104, 222, 79, 4, 46, 77, 0, 176, 82, 51, 0, 23, 159, 0, 176, ++ 82, 47, 0, 16, 235, 2, 129, 82, 47, 0, 7, 203, 0, 224, 2, 171, 0, 32, ++ 170, 2, 129, 82, 47, 0, 11, 142, 3, 41, 94, 2, 240, 14, 83, 2, 3, 222, ++ 179, 0, 14, 83, 1, 145, 96, 26, 132, 244, 39, 1, 131, 224, 2, 245, 151, ++ 172, 2, 8, 82, 47, 0, 7, 224, 3, 191, 222, 2, 240, 10, 79, 1, 188, 96, ++ 3, 0, 16, 103, 1, 188, 96, 3, 0, 16, 70, 1, 128, 224, 6, 9, 48, 73, ++ 2, 130, 193, 31, 0, 14, 93, 1, 188, 96, 63, 31, 240, 101, 1, 188, 96, ++ 3, 0, 22, 128, 0, 232, 65, 151, 0, 48, 101, 0, 105, 193, 151, 0, 14, ++ 90, 1, 188, 96, 11, 0, 23, 148, 1, 188, 96, 3, 0, 23, 171, 1, 188, 96, ++ 3, 0, 23, 172, 1, 188, 96, 3, 0, 23, 173, 1, 188, 96, 3, 0, 23, 174, ++ 1, 188, 96, 3, 0, 23, 191, 1, 188, 99, 255, 31, 247, 181, 1, 188, 96, ++ 3, 0, 32, 32, 1, 188, 96, 3, 0, 23, 161, 0, 2, 94, 2, 240, 1, 39, 1, ++ 56, 64, 103, 0, 0, 40, 1, 28, 64, 103, 0, 0, 41, 1, 188, 96, 3, 0, 80, ++ 73, 1, 188, 96, 3, 0, 23, 167, 1, 188, 96, 3, 0, 23, 168, 1, 188, 96, ++ 3, 0, 23, 169, 1, 188, 96, 3, 0, 23, 172, 1, 188, 96, 3, 0, 23, 173, ++ 1, 130, 224, 6, 15, 16, 120, 2, 6, 193, 227, 0, 14, 112, 0, 104, 128, ++ 167, 0, 14, 115, 3, 191, 222, 2, 240, 14, 116, 0, 104, 128, 167, 0, ++ 142, 116, 1, 188, 96, 19, 2, 96, 0, 1, 188, 96, 35, 11, 32, 1, 1, 188, ++ 98, 55, 22, 128, 2, 1, 188, 96, 3, 0, 0, 3, 1, 188, 96, 3, 0, 0, 4, ++ 1, 188, 96, 67, 5, 32, 5, 1, 188, 96, 27, 4, 48, 97, 1, 188, 96, 23, ++ 2, 80, 96, 1, 188, 96, 3, 0, 8, 34, 0, 176, 94, 15, 0, 23, 133, 0, 160, ++ 68, 182, 240, 113, 69, 3, 191, 222, 2, 240, 12, 190, 1, 131, 224, 6, ++ 15, 16, 120, 1, 136, 94, 92, 254, 199, 246, 1, 188, 96, 31, 30, 144, ++ 7, 1, 188, 96, 3, 1, 144, 8, 1, 136, 96, 6, 0, 144, 4, 3, 134, 222, ++ 2, 240, 12, 156, 3, 5, 222, 2, 240, 14, 133, 3, 134, 222, 2, 240, 12, ++ 156, 3, 133, 222, 2, 240, 14, 135, 0, 176, 94, 135, 0, 23, 161, 0, 110, ++ 224, 3, 0, 46, 139, 3, 134, 222, 2, 240, 12, 156, 0, 110, 192, 20, 111, ++ 238, 142, 1, 188, 96, 7, 0, 16, 66, 0, 2, 222, 2, 240, 0, 0, 3, 33, ++ 94, 2, 240, 14, 147, 0, 224, 32, 74, 244, 40, 18, 0, 176, 32, 75, 0, ++ 23, 139, 3, 191, 222, 2, 240, 14, 155, 2, 129, 80, 199, 0, 14, 152, ++ 1, 28, 80, 159, 0, 23, 139, 0, 224, 94, 46, 244, 55, 139, 1, 156, 94, ++ 46, 132, 244, 39, 3, 191, 222, 2, 240, 14, 155, 1, 30, 80, 159, 0, 23, ++ 139, 0, 224, 94, 46, 244, 55, 139, 1, 158, 94, 46, 132, 244, 39, 0, ++ 2, 222, 2, 240, 0, 0, 0, 104, 0, 167, 0, 142, 161, 1, 2, 192, 39, 0, ++ 8, 33, 0, 104, 128, 167, 0, 174, 167, 0, 224, 32, 135, 0, 40, 33, 0, ++ 2, 222, 2, 240, 0, 0, 1, 188, 96, 3, 0, 40, 33, 1, 188, 64, 43, 0, 23, ++ 161, 0, 152, 94, 135, 1, 23, 161, 0, 152, 64, 43, 1, 23, 162, 0, 106, ++ 222, 138, 244, 46, 167, 1, 188, 96, 3, 0, 136, 33, 0, 2, 222, 2, 240, ++ 0, 0, 2, 130, 128, 191, 0, 15, 0, 0, 176, 65, 143, 0, 8, 19, 0, 176, ++ 65, 139, 0, 8, 20, 0, 176, 68, 103, 0, 23, 162, 1, 123, 222, 138, 35, ++ 87, 161, 1, 188, 96, 31, 7, 112, 101, 1, 188, 96, 3, 0, 23, 162, 1, ++ 188, 96, 31, 3, 208, 100, 1, 188, 96, 31, 17, 80, 99, 0, 104, 90, 3, ++ 0, 14, 247, 1, 188, 96, 31, 15, 176, 98, 0, 224, 65, 138, 244, 80, 98, ++ 0, 144, 84, 3, 0, 247, 166, 0, 107, 94, 134, 208, 110, 205, 0, 176, ++ 90, 3, 0, 23, 163, 0, 224, 90, 14, 244, 213, 128, 0, 224, 90, 14, 244, ++ 118, 131, 0, 232, 90, 47, 0, 54, 139, 0, 105, 218, 47, 0, 14, 188, 0, ++ 232, 90, 7, 0, 54, 139, 0, 108, 218, 14, 244, 46, 183, 0, 232, 90, 14, ++ 244, 55, 164, 0, 144, 90, 3, 0, 119, 165, 0, 110, 222, 146, 244, 174, ++ 195, 1, 188, 96, 3, 0, 54, 0, 1, 188, 96, 11, 0, 16, 67, 1, 188, 96, ++ 3, 0, 39, 137, 0, 32, 90, 11, 8, 14, 198, 1, 188, 96, 3, 0, 39, 146, ++ 3, 191, 222, 2, 240, 14, 205, 0, 32, 90, 11, 20, 14, 205, 0, 32, 44, ++ 39, 8, 14, 201, 0, 32, 90, 11, 4, 14, 205, 1, 134, 96, 6, 245, 183, ++ 173, 0, 136, 0, 155, 0, 209, 38, 0, 144, 0, 155, 1, 81, 40, 1, 188, ++ 99, 3, 0, 17, 36, 0, 107, 94, 134, 176, 14, 213, 0, 104, 90, 19, 0, ++ 14, 210, 1, 136, 96, 6, 208, 86, 130, 0, 176, 86, 3, 0, 23, 164, 0, ++ 224, 94, 146, 208, 150, 133, 0, 224, 90, 14, 244, 213, 128, 0, 32, 90, ++ 11, 8, 14, 213, 1, 188, 96, 3, 0, 7, 146, 0, 104, 90, 19, 0, 14, 221, ++ 0, 107, 94, 134, 208, 174, 221, 1, 136, 96, 10, 208, 86, 130, 0, 176, ++ 86, 3, 0, 23, 164, 0, 224, 94, 146, 208, 150, 133, 1, 188, 96, 3, 0, ++ 54, 1, 1, 188, 96, 11, 0, 16, 67, 1, 188, 96, 3, 0, 39, 137, 0, 104, ++ 90, 27, 0, 14, 247, 0, 107, 94, 134, 208, 238, 247, 2, 1, 90, 11, 0, ++ 14, 236, 0, 232, 90, 27, 0, 54, 134, 0, 176, 90, 39, 0, 23, 163, 0, ++ 224, 90, 30, 244, 118, 135, 1, 188, 96, 31, 17, 208, 98, 0, 224, 65, ++ 138, 244, 80, 98, 0, 176, 90, 43, 0, 23, 163, 0, 224, 84, 2, 244, 117, ++ 0, 2, 3, 212, 3, 0, 14, 234, 0, 224, 90, 31, 0, 54, 135, 1, 48, 84, ++ 3, 0, 21, 0, 1, 129, 96, 2, 208, 86, 130, 3, 191, 222, 2, 240, 14, 239, ++ 0, 176, 90, 35, 0, 23, 163, 0, 224, 90, 30, 244, 118, 135, 1, 129, 96, ++ 6, 208, 86, 130, 0, 104, 90, 27, 0, 14, 241, 0, 108, 218, 30, 244, 46, ++ 223, 2, 1, 90, 11, 0, 14, 244, 1, 188, 96, 3, 0, 54, 2, 3, 191, 222, ++ 2, 240, 14, 245, 1, 188, 96, 3, 0, 54, 3, 1, 188, 96, 11, 0, 16, 67, ++ 1, 188, 96, 3, 0, 39, 137, 0, 224, 65, 151, 1, 144, 101, 0, 224, 94, ++ 139, 0, 55, 162, 0, 224, 65, 147, 0, 144, 100, 0, 224, 65, 143, 0, 48, ++ 99, 0, 109, 94, 139, 0, 142, 177, 2, 152, 29, 243, 0, 14, 254, 1, 188, ++ 96, 3, 0, 7, 146, 0, 176, 32, 79, 0, 16, 99, 0, 176, 32, 83, 0, 16, ++ 98, 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 3, 0, 23, 162, 0, 104, 1, 139, ++ 0, 15, 23, 0, 144, 1, 139, 0, 119, 162, 1, 128, 96, 2, 244, 55, 161, ++ 0, 110, 94, 134, 244, 79, 23, 2, 7, 193, 151, 0, 15, 9, 1, 56, 90, 7, ++ 0, 23, 163, 3, 191, 222, 2, 240, 15, 10, 1, 60, 90, 3, 0, 23, 163, 0, ++ 232, 94, 143, 0, 151, 163, 0, 232, 94, 138, 244, 55, 162, 0, 106, 94, ++ 138, 244, 111, 23, 0, 208, 65, 151, 0, 48, 100, 0, 224, 94, 139, 0, ++ 183, 163, 0, 224, 65, 146, 244, 112, 100, 0, 216, 65, 147, 0, 48, 100, ++ 2, 7, 193, 147, 0, 15, 20, 1, 60, 88, 3, 0, 23, 161, 3, 191, 222, 2, ++ 240, 15, 21, 1, 56, 88, 3, 0, 23, 161, 0, 160, 1, 139, 0, 247, 162, ++ 0, 144, 94, 134, 244, 87, 162, 0, 2, 222, 2, 240, 0, 0, 0, 176, 90, ++ 3, 0, 16, 31, 0, 176, 90, 7, 0, 16, 32, 0, 176, 90, 11, 0, 16, 33, 1, ++ 128, 96, 7, 0, 16, 29, 2, 128, 64, 119, 0, 15, 28, 0, 2, 222, 2, 240, ++ 0, 0, 1, 135, 224, 2, 245, 119, 171, 3, 145, 94, 2, 240, 0, 2, 0, 32, ++ 227, 254, 9, 0, 2, 2, 0, 66, 31, 0, 0, 2, 0, 104, 194, 243, 0, 0, 2, ++ 2, 132, 69, 35, 0, 0, 2, 0, 104, 192, 23, 0, 0, 2, 0, 104, 171, 151, ++ 0, 0, 2, 0, 2, 94, 2, 240, 14, 168, 0, 104, 48, 79, 255, 239, 42, 2, ++ 7, 196, 147, 0, 15, 53, 0, 104, 48, 83, 255, 224, 2, 0, 104, 48, 83, ++ 255, 239, 46, 0, 104, 48, 87, 0, 15, 52, 0, 107, 196, 101, 130, 175, ++ 53, 3, 191, 222, 2, 240, 0, 2, 1, 188, 96, 31, 7, 112, 100, 0, 224, ++ 65, 147, 6, 23, 162, 0, 104, 216, 47, 0, 15, 50, 2, 129, 216, 11, 0, ++ 0, 2, 0, 224, 65, 147, 1, 144, 100, 0, 109, 65, 146, 244, 79, 48, 2, ++ 135, 196, 147, 0, 0, 2, 0, 104, 158, 75, 0, 0, 2, 2, 129, 94, 83, 0, ++ 15, 67, 2, 131, 65, 31, 0, 15, 57, 2, 129, 222, 83, 0, 15, 84, 1, 188, ++ 96, 3, 0, 17, 81, 1, 188, 96, 3, 0, 17, 82, 1, 188, 98, 3, 0, 17, 83, ++ 1, 188, 96, 3, 0, 81, 80, 1, 137, 96, 6, 242, 151, 148, 1, 188, 96, ++ 231, 0, 16, 119, 1, 188, 96, 3, 0, 16, 118, 1, 188, 96, 3, 17, 23, 163, ++ 0, 2, 94, 2, 240, 1, 52, 3, 191, 222, 2, 240, 0, 2, 2, 128, 197, 67, ++ 0, 0, 2, 1, 240, 197, 71, 0, 17, 86, 1, 7, 197, 71, 0, 23, 161, 1, 240, ++ 197, 74, 244, 49, 85, 0, 176, 69, 87, 0, 16, 119, 0, 176, 69, 91, 0, ++ 16, 118, 1, 188, 96, 3, 14, 151, 163, 0, 2, 94, 2, 240, 1, 52, 0, 176, ++ 69, 87, 0, 12, 7, 0, 176, 69, 91, 0, 12, 6, 1, 188, 96, 3, 0, 17, 85, ++ 1, 188, 96, 3, 0, 17, 86, 0, 144, 48, 27, 0, 204, 6, 0, 176, 48, 31, ++ 0, 23, 161, 1, 173, 94, 133, 128, 204, 6, 1, 137, 96, 10, 242, 151, ++ 148, 1, 188, 96, 3, 8, 16, 71, 3, 146, 222, 2, 240, 15, 168, 2, 4, 128, ++ 191, 0, 15, 89, 1, 188, 99, 255, 31, 231, 243, 1, 188, 97, 255, 31, ++ 232, 14, 3, 191, 222, 2, 240, 15, 170, 1, 134, 96, 2, 245, 151, 172, ++ 1, 188, 96, 31, 7, 112, 101, 1, 188, 96, 31, 15, 176, 100, 1, 188, 96, ++ 3, 0, 55, 161, 1, 188, 96, 3, 0, 23, 163, 0, 104, 90, 3, 0, 15, 150, ++ 1, 188, 96, 3, 0, 23, 165, 2, 3, 90, 11, 0, 15, 103, 2, 128, 90, 11, ++ 0, 15, 168, 0, 233, 68, 10, 192, 23, 187, 0, 232, 196, 15, 0, 23, 164, ++ 1, 123, 222, 238, 244, 151, 164, 0, 104, 90, 19, 0, 15, 117, 3, 191, ++ 222, 2, 240, 15, 114, 0, 104, 222, 135, 0, 47, 105, 2, 3, 222, 83, 0, ++ 15, 168, 2, 3, 218, 11, 0, 15, 125, 0, 176, 90, 15, 0, 23, 164, 0, 104, ++ 90, 7, 0, 47, 110, 0, 104, 90, 47, 0, 47, 110, 1, 188, 96, 3, 0, 55, ++ 165, 0, 104, 90, 19, 0, 15, 114, 0, 108, 222, 146, 208, 175, 114, 0, ++ 176, 90, 23, 0, 23, 164, 1, 188, 96, 3, 0, 55, 165, 0, 32, 28, 186, ++ 244, 47, 117, 0, 104, 90, 27, 0, 15, 144, 3, 191, 222, 2, 240, 15, 120, ++ 0, 136, 94, 135, 0, 151, 187, 0, 32, 28, 186, 247, 111, 168, 2, 1, 90, ++ 11, 0, 15, 168, 0, 108, 222, 146, 208, 239, 144, 0, 176, 90, 31, 0, ++ 23, 164, 0, 32, 28, 186, 244, 47, 124, 1, 188, 96, 3, 0, 55, 165, 3, ++ 191, 222, 2, 240, 15, 144, 2, 2, 218, 11, 0, 15, 150, 2, 4, 193, 7, ++ 0, 15, 168, 0, 176, 90, 15, 0, 23, 164, 0, 232, 90, 47, 0, 55, 187, ++ 0, 105, 222, 239, 0, 15, 131, 0, 232, 90, 7, 0, 55, 187, 1, 60, 1, 111, ++ 0, 23, 128, 0, 104, 222, 3, 0, 15, 137, 1, 56, 1, 111, 0, 23, 128, 0, ++ 104, 94, 3, 0, 15, 140, 0, 232, 94, 3, 0, 55, 187, 3, 191, 222, 2, 240, ++ 15, 140, 0, 232, 94, 3, 0, 55, 128, 0, 128, 222, 2, 208, 55, 128, 0, ++ 224, 94, 238, 13, 183, 187, 0, 104, 94, 239, 0, 15, 144, 0, 224, 94, ++ 146, 208, 23, 164, 0, 232, 94, 239, 0, 55, 187, 3, 191, 222, 2, 240, ++ 15, 140, 0, 104, 94, 143, 0, 15, 147, 0, 107, 94, 146, 244, 79, 148, ++ 3, 191, 222, 2, 240, 15, 150, 1, 188, 96, 3, 0, 55, 163, 0, 176, 94, ++ 147, 0, 23, 162, 0, 176, 94, 151, 0, 23, 166, 0, 136, 94, 135, 0, 55, ++ 161, 0, 224, 65, 151, 1, 144, 101, 0, 224, 65, 147, 0, 48, 100, 0, 109, ++ 94, 135, 2, 15, 94, 0, 104, 94, 143, 0, 15, 168, 0, 176, 68, 103, 0, ++ 23, 165, 1, 123, 222, 150, 35, 87, 165, 0, 232, 94, 138, 244, 183, 164, ++ 0, 136, 94, 147, 0, 228, 219, 0, 144, 94, 147, 1, 39, 29, 0, 176, 1, ++ 43, 0, 23, 163, 0, 104, 156, 119, 0, 15, 163, 0, 110, 147, 110, 244, ++ 111, 168, 3, 166, 94, 2, 240, 15, 168, 0, 176, 94, 155, 0, 7, 133, 0, ++ 233, 19, 110, 244, 103, 243, 0, 232, 156, 119, 0, 8, 14, 3, 191, 222, ++ 2, 240, 15, 170, 0, 104, 30, 23, 0, 0, 2, 3, 191, 222, 2, 240, 16, 82, ++ 1, 188, 97, 3, 0, 17, 35, 0, 105, 32, 59, 0, 15, 174, 1, 128, 224, 6, ++ 242, 151, 148, 3, 191, 222, 2, 240, 15, 176, 1, 128, 224, 2, 242, 151, ++ 148, 3, 191, 222, 2, 240, 0, 2, 0, 104, 65, 39, 0, 15, 191, 2, 132, ++ 69, 35, 0, 15, 177, 0, 104, 0, 167, 0, 175, 181, 0, 104, 0, 167, 0, ++ 207, 181, 0, 104, 128, 167, 1, 15, 184, 0, 176, 68, 103, 0, 23, 161, ++ 0, 232, 68, 102, 244, 55, 162, 0, 109, 94, 139, 0, 79, 182, 2, 128, ++ 193, 39, 0, 15, 186, 3, 146, 222, 2, 240, 16, 82, 3, 146, 222, 2, 240, ++ 12, 226, 0, 2, 94, 2, 240, 20, 228, 0, 2, 94, 2, 240, 17, 54, 0, 2, ++ 94, 2, 240, 17, 49, 0, 2, 94, 2, 240, 17, 65, 1, 188, 96, 15, 0, 17, ++ 232, 3, 30, 222, 2, 240, 15, 198, 1, 188, 96, 3, 0, 16, 92, 1, 188, ++ 96, 3, 0, 144, 93, 1, 188, 96, 83, 4, 16, 94, 1, 188, 96, 3, 0, 16, ++ 95, 3, 191, 222, 2, 240, 15, 202, 1, 188, 96, 11, 0, 16, 92, 1, 188, ++ 96, 3, 0, 144, 93, 1, 188, 96, 67, 4, 16, 94, 1, 188, 96, 3, 0, 16, ++ 95, 1, 188, 96, 3, 0, 12, 21, 1, 188, 96, 3, 0, 128, 32, 2, 133, 0, ++ 191, 0, 16, 89, 0, 176, 31, 207, 0, 17, 81, 0, 176, 32, 59, 0, 17, 82, ++ 0, 110, 31, 206, 42, 143, 211, 0, 104, 160, 59, 0, 15, 211, 0, 224, ++ 31, 206, 35, 40, 15, 3, 191, 222, 2, 240, 15, 244, 0, 176, 68, 103, ++ 0, 8, 15, 0, 233, 31, 206, 42, 145, 81, 0, 232, 160, 59, 0, 17, 82, ++ 1, 188, 97, 255, 31, 112, 119, 1, 188, 99, 255, 31, 240, 118, 1, 188, ++ 96, 3, 17, 151, 163, 0, 2, 94, 2, 240, 1, 52, 0, 176, 69, 75, 0, 16, ++ 119, 0, 176, 69, 71, 0, 16, 118, 1, 188, 96, 3, 15, 23, 163, 0, 2, 94, ++ 2, 240, 1, 52, 1, 188, 96, 47, 25, 144, 101, 0, 176, 69, 87, 0, 22, ++ 145, 0, 176, 69, 91, 0, 22, 146, 0, 176, 68, 11, 0, 22, 147, 0, 176, ++ 68, 15, 0, 22, 148, 1, 188, 99, 255, 31, 241, 82, 1, 188, 99, 255, 31, ++ 241, 81, 1, 188, 96, 3, 0, 17, 85, 1, 188, 96, 3, 0, 17, 86, 1, 172, ++ 96, 127, 2, 144, 117, 2, 135, 65, 215, 0, 15, 232, 0, 176, 65, 219, ++ 0, 3, 177, 0, 176, 65, 223, 0, 3, 178, 0, 176, 68, 103, 0, 8, 45, 0, ++ 176, 68, 107, 0, 8, 44, 0, 176, 68, 111, 0, 8, 43, 0, 176, 68, 115, ++ 0, 8, 42, 0, 225, 68, 100, 254, 108, 17, 0, 224, 196, 105, 1, 204, 18, ++ 1, 188, 96, 3, 2, 49, 80, 0, 176, 69, 67, 0, 24, 0, 0, 104, 96, 3, 0, ++ 15, 244, 1, 188, 96, 3, 0, 16, 64, 0, 0, 128, 0, 0, 0, 0, 2, 4, 128, ++ 191, 0, 15, 248, 3, 18, 222, 2, 240, 15, 244, 0, 104, 197, 87, 0, 16, ++ 0, 1, 188, 96, 47, 25, 144, 101, 0, 176, 90, 71, 0, 17, 85, 0, 176, ++ 90, 75, 0, 17, 86, 0, 176, 90, 79, 0, 17, 2, 0, 176, 90, 83, 0, 17, ++ 3, 1, 188, 96, 3, 0, 23, 167, 1, 188, 96, 3, 0, 23, 168, 1, 188, 96, ++ 3, 0, 0, 102, 1, 172, 96, 127, 15, 16, 117, 2, 135, 65, 215, 0, 16, ++ 2, 0, 176, 65, 219, 0, 17, 81, 0, 176, 65, 223, 0, 17, 82, 0, 104, 69, ++ 71, 0, 16, 9, 0, 233, 31, 206, 42, 135, 243, 0, 232, 160, 59, 0, 8, ++ 14, 1, 134, 96, 6, 245, 151, 172, 1, 188, 96, 3, 0, 16, 119, 1, 188, ++ 96, 3, 0, 16, 118, 1, 188, 96, 3, 15, 23, 163, 0, 2, 94, 2, 240, 1, ++ 52, 1, 188, 96, 3, 0, 17, 80, 2, 132, 69, 67, 0, 16, 14, 2, 7, 193, ++ 227, 0, 16, 15, 0, 176, 68, 103, 0, 23, 161, 0, 104, 94, 134, 35, 48, ++ 17, 1, 130, 224, 6, 15, 16, 120, 2, 6, 193, 227, 0, 16, 19, 1, 188, ++ 96, 3, 0, 64, 32, 1, 188, 96, 3, 0, 0, 102, 1, 134, 96, 6, 32, 17, 0, ++ 1, 188, 96, 99, 0, 16, 123, 1, 188, 96, 27, 0, 16, 122, 1, 172, 96, ++ 127, 2, 144, 117, 2, 135, 65, 215, 0, 16, 26, 0, 233, 65, 216, 118, ++ 55, 156, 0, 232, 193, 220, 118, 87, 155, 0, 176, 48, 27, 0, 23, 161, ++ 0, 128, 222, 114, 244, 55, 157, 0, 176, 65, 183, 0, 23, 158, 0, 128, ++ 222, 110, 244, 55, 156, 0, 225, 94, 118, 13, 183, 157, 0, 224, 222, ++ 115, 0, 23, 156, 1, 125, 94, 122, 243, 183, 161, 1, 125, 94, 118, 243, ++ 151, 162, 0, 144, 94, 115, 1, 87, 163, 0, 225, 32, 182, 244, 49, 25, ++ 0, 225, 160, 178, 244, 81, 26, 0, 225, 160, 174, 244, 113, 27, 0, 224, ++ 160, 171, 0, 17, 28, 0, 225, 13, 170, 244, 35, 106, 0, 224, 141, 174, ++ 244, 67, 107, 0, 176, 68, 31, 0, 24, 0, 0, 136, 68, 35, 1, 87, 163, ++ 0, 144, 68, 35, 0, 215, 164, 0, 176, 68, 11, 0, 23, 161, 0, 176, 68, ++ 15, 0, 23, 162, 0, 233, 94, 134, 35, 55, 161, 0, 232, 222, 138, 35, ++ 87, 162, 0, 105, 222, 139, 0, 16, 58, 0, 225, 68, 10, 244, 113, 2, 0, ++ 224, 196, 14, 244, 145, 3, 0, 232, 94, 35, 0, 55, 136, 0, 105, 222, ++ 35, 0, 16, 47, 0, 232, 0, 39, 0, 55, 136, 3, 191, 222, 2, 240, 16, 47, ++ 1, 134, 96, 2, 32, 17, 0, 1, 188, 96, 3, 0, 64, 32, 0, 233, 48, 70, ++ 35, 55, 161, 0, 232, 176, 74, 35, 87, 162, 0, 104, 222, 139, 0, 16, ++ 73, 1, 188, 96, 79, 17, 23, 163, 0, 109, 222, 134, 244, 112, 73, 1, ++ 188, 96, 3, 0, 16, 64, 1, 188, 96, 3, 0, 16, 93, 1, 130, 96, 6, 11, ++ 240, 95, 0, 208, 94, 135, 0, 113, 52, 1, 225, 222, 138, 38, 145, 53, ++ 1, 188, 99, 3, 0, 17, 51, 0, 0, 128, 0, 0, 0, 0, 1, 130, 96, 2, 11, ++ 240, 95, 2, 134, 94, 179, 0, 16, 82, 0, 104, 30, 23, 0, 16, 82, 1, 188, ++ 96, 67, 0, 23, 161, 0, 224, 68, 102, 244, 55, 128, 1, 188, 96, 3, 0, ++ 7, 137, 0, 2, 94, 2, 240, 14, 168, 0, 108, 68, 102, 240, 16, 82, 0, ++ 104, 30, 39, 0, 16, 78, 3, 191, 222, 2, 240, 15, 84, 2, 0, 222, 83, ++ 0, 16, 92, 1, 128, 224, 2, 242, 151, 148, 0, 2, 94, 2, 240, 17, 52, ++ 1, 188, 96, 3, 0, 16, 64, 3, 191, 222, 2, 240, 16, 87, 0, 224, 68, 100, ++ 9, 87, 161, 3, 191, 222, 2, 240, 16, 92, 1, 188, 96, 3, 0, 16, 64, 0, ++ 176, 1, 47, 0, 23, 161, 0, 224, 1, 42, 244, 49, 9, 0, 176, 1, 47, 0, ++ 17, 9, 1, 188, 97, 207, 12, 16, 92, 1, 188, 96, 3, 0, 16, 93, 1, 188, ++ 97, 207, 1, 240, 94, 1, 188, 96, 59, 10, 240, 95, 0, 2, 94, 2, 240, ++ 17, 61, 0, 2, 94, 2, 240, 17, 68, 0, 2, 94, 2, 240, 17, 58, 1, 188, ++ 96, 3, 0, 7, 133, 0, 109, 128, 167, 0, 140, 226, 0, 224, 68, 103, 4, ++ 119, 161, 0, 104, 222, 134, 35, 48, 103, 3, 191, 222, 2, 240, 12, 226, ++ 1, 136, 94, 6, 16, 208, 134, 1, 2, 94, 7, 0, 23, 161, 1, 130, 94, 134, ++ 16, 208, 134, 0, 2, 222, 2, 240, 0, 0, 0, 176, 0, 71, 0, 16, 134, 1, ++ 8, 32, 71, 0, 23, 129, 1, 56, 82, 3, 0, 23, 128, 1, 2, 192, 39, 0, 23, ++ 166, 0, 2, 94, 2, 240, 22, 2, 0, 104, 32, 71, 0, 80, 116, 0, 176, 84, ++ 7, 0, 23, 128, 0, 2, 94, 2, 240, 16, 105, 0, 104, 32, 71, 0, 48, 124, ++ 0, 104, 160, 71, 0, 16, 120, 2, 26, 84, 7, 0, 16, 124, 1, 3, 192, 39, ++ 0, 23, 161, 3, 191, 222, 2, 240, 16, 123, 1, 6, 192, 59, 0, 23, 161, ++ 1, 130, 94, 134, 16, 208, 134, 0, 2, 222, 2, 240, 0, 0, 0, 176, 84, ++ 19, 0, 23, 161, 0, 104, 222, 79, 22, 176, 128, 0, 176, 84, 19, 0, 23, ++ 161, 2, 0, 222, 7, 0, 16, 136, 0, 176, 65, 139, 0, 16, 101, 1, 188, ++ 96, 3, 1, 215, 161, 0, 104, 222, 79, 22, 176, 133, 1, 188, 96, 3, 2, ++ 151, 161, 0, 2, 94, 2, 240, 22, 21, 0, 224, 94, 132, 0, 247, 161, 3, ++ 191, 222, 2, 240, 16, 141, 2, 4, 128, 243, 0, 16, 141, 2, 2, 94, 7, ++ 0, 16, 141, 2, 128, 94, 7, 0, 16, 141, 0, 144, 0, 27, 0, 55, 162, 0, ++ 232, 84, 18, 244, 87, 161, 0, 2, 222, 2, 240, 0, 0, 2, 4, 0, 191, 0, ++ 16, 145, 0, 2, 94, 2, 240, 17, 226, 3, 191, 222, 2, 240, 16, 146, 0, ++ 160, 68, 182, 240, 177, 69, 0, 2, 222, 2, 240, 0, 0, 2, 0, 0, 191, 0, ++ 16, 163, 0, 104, 171, 239, 0, 16, 163, 0, 224, 94, 163, 0, 55, 168, ++ 0, 109, 94, 160, 5, 208, 163, 0, 176, 46, 11, 0, 23, 161, 0, 2, 94, ++ 2, 240, 1, 39, 0, 176, 64, 103, 0, 23, 162, 0, 104, 222, 163, 255, 240, ++ 160, 0, 176, 94, 137, 112, 119, 162, 0, 109, 0, 167, 0, 144, 159, 0, ++ 109, 160, 135, 0, 80, 161, 3, 191, 222, 2, 240, 16, 160, 0, 104, 160, ++ 135, 0, 16, 161, 0, 184, 94, 137, 112, 119, 162, 0, 2, 94, 2, 240, 1, ++ 43, 1, 188, 96, 3, 0, 23, 168, 0, 2, 222, 2, 240, 0, 0, 0, 216, 90, ++ 3, 1, 23, 162, 1, 184, 90, 6, 244, 87, 162, 0, 176, 86, 3, 0, 8, 54, ++ 0, 176, 86, 7, 0, 8, 55, 0, 176, 86, 11, 0, 8, 56, 0, 176, 86, 15, 0, ++ 8, 57, 0, 176, 86, 19, 0, 8, 58, 0, 224, 86, 18, 244, 72, 59, 0, 176, ++ 90, 3, 0, 8, 52, 1, 56, 94, 139, 0, 8, 53, 0, 176, 32, 239, 0, 23, 164, ++ 1, 188, 96, 3, 0, 23, 162, 0, 176, 65, 147, 0, 16, 101, 0, 184, 94, ++ 146, 208, 23, 164, 0, 224, 94, 6, 244, 80, 99, 0, 240, 94, 147, 0, 23, ++ 163, 0, 240, 94, 147, 0, 119, 164, 0, 224, 94, 139, 0, 55, 162, 0, 184, ++ 94, 146, 244, 119, 164, 0, 224, 65, 146, 244, 80, 101, 0, 224, 86, 2, ++ 244, 149, 128, 0, 176, 86, 3, 0, 23, 164, 0, 110, 222, 139, 0, 176, ++ 177, 0, 184, 94, 146, 192, 215, 162, 0, 216, 94, 139, 0, 55, 162, 0, ++ 224, 32, 218, 244, 72, 54, 0, 176, 32, 219, 0, 23, 164, 0, 184, 94, ++ 146, 192, 247, 162, 0, 216, 94, 139, 0, 55, 162, 0, 224, 32, 222, 244, ++ 72, 55, 0, 216, 32, 223, 0, 55, 162, 0, 224, 32, 226, 244, 72, 56, 0, ++ 216, 32, 227, 0, 55, 162, 0, 224, 32, 230, 244, 72, 57, 0, 216, 32, ++ 231, 0, 55, 162, 0, 224, 32, 234, 244, 72, 58, 0, 216, 32, 235, 0, 55, ++ 162, 0, 224, 32, 238, 244, 72, 59, 0, 176, 32, 239, 0, 23, 162, 0, 184, ++ 94, 138, 192, 23, 162, 0, 144, 94, 139, 0, 55, 162, 1, 188, 94, 137, ++ 6, 168, 53, 0, 2, 222, 2, 240, 0, 0, 1, 128, 96, 6, 60, 145, 228, 1, ++ 135, 96, 6, 60, 209, 230, 1, 168, 96, 2, 60, 209, 230, 1, 139, 96, 2, ++ 60, 209, 230, 0, 176, 94, 143, 0, 16, 99, 0, 176, 86, 3, 0, 17, 231, ++ 0, 176, 86, 7, 0, 17, 231, 0, 176, 86, 11, 0, 17, 231, 0, 176, 86, 15, ++ 0, 17, 231, 1, 169, 96, 66, 60, 145, 228, 1, 168, 96, 2, 60, 209, 230, ++ 1, 139, 96, 6, 60, 209, 230, 0, 176, 94, 139, 0, 16, 99, 1, 188, 96, ++ 3, 0, 87, 161, 2, 4, 86, 3, 0, 16, 223, 1, 188, 96, 3, 1, 23, 161, 0, ++ 224, 65, 142, 244, 48, 99, 0, 176, 86, 3, 0, 17, 231, 0, 176, 86, 7, ++ 0, 17, 231, 0, 176, 86, 11, 0, 17, 231, 0, 176, 94, 139, 0, 16, 99, ++ 1, 188, 96, 3, 0, 183, 161, 2, 4, 214, 3, 0, 16, 233, 1, 188, 96, 3, ++ 1, 23, 161, 2, 6, 94, 83, 0, 16, 233, 1, 188, 96, 3, 1, 151, 161, 0, ++ 224, 65, 142, 244, 48, 99, 0, 176, 86, 3, 0, 17, 231, 0, 176, 86, 7, ++ 0, 17, 231, 0, 176, 86, 11, 0, 17, 231, 1, 188, 96, 3, 0, 23, 161, 2, ++ 6, 222, 83, 0, 16, 244, 0, 176, 94, 139, 0, 16, 99, 2, 6, 94, 83, 0, ++ 16, 243, 0, 160, 86, 63, 1, 247, 161, 3, 191, 222, 2, 240, 16, 244, ++ 0, 160, 86, 51, 1, 247, 161, 0, 176, 94, 135, 0, 17, 231, 1, 188, 96, ++ 3, 0, 17, 231, 0, 2, 222, 2, 240, 0, 0, 0, 104, 94, 155, 0, 209, 17, ++ 1, 188, 96, 7, 2, 17, 227, 0, 104, 222, 155, 0, 81, 4, 0, 232, 71, 135, ++ 1, 17, 225, 1, 188, 96, 3, 0, 17, 226, 1, 188, 96, 3, 0, 17, 226, 1, ++ 188, 96, 3, 0, 17, 226, 1, 188, 96, 3, 0, 17, 226, 1, 188, 96, 3, 0, ++ 17, 226, 1, 188, 96, 3, 0, 17, 226, 1, 188, 96, 3, 0, 17, 226, 1, 188, ++ 96, 3, 0, 17, 226, 0, 176, 97, 66, 244, 81, 224, 0, 176, 88, 3, 0, 17, ++ 226, 0, 176, 88, 7, 0, 17, 226, 0, 176, 88, 11, 0, 17, 226, 0, 176, ++ 88, 15, 0, 17, 226, 0, 176, 88, 19, 0, 17, 226, 0, 176, 88, 23, 0, 17, ++ 226, 0, 176, 88, 27, 0, 17, 226, 0, 176, 88, 31, 0, 17, 226, 0, 176, ++ 94, 155, 0, 23, 164, 0, 104, 222, 155, 0, 177, 15, 1, 188, 96, 3, 0, ++ 119, 164, 1, 146, 222, 147, 2, 23, 163, 0, 2, 222, 2, 240, 0, 0, 1, ++ 188, 96, 7, 0, 17, 227, 0, 176, 88, 3, 0, 17, 226, 0, 176, 88, 7, 0, ++ 17, 226, 0, 176, 88, 11, 0, 17, 226, 0, 176, 88, 15, 0, 17, 226, 0, ++ 176, 88, 19, 0, 17, 226, 0, 176, 88, 23, 0, 17, 226, 0, 176, 88, 27, ++ 0, 17, 226, 0, 176, 88, 31, 0, 17, 226, 0, 224, 1, 70, 240, 16, 100, ++ 1, 188, 96, 7, 0, 49, 227, 0, 176, 88, 3, 0, 17, 226, 0, 176, 88, 7, ++ 0, 17, 226, 0, 176, 88, 11, 0, 17, 226, 0, 176, 88, 15, 0, 17, 226, ++ 0, 176, 88, 19, 0, 17, 226, 0, 176, 88, 23, 0, 17, 226, 0, 176, 88, ++ 27, 0, 17, 226, 0, 176, 88, 31, 0, 17, 226, 1, 146, 224, 27, 0, 23, ++ 163, 0, 2, 222, 2, 240, 0, 0, 2, 135, 64, 195, 0, 17, 38, 1, 134, 96, ++ 6, 240, 16, 48, 2, 134, 64, 195, 0, 17, 40, 0, 176, 64, 199, 0, 23, ++ 129, 0, 2, 222, 2, 240, 0, 0, 2, 135, 64, 195, 0, 17, 43, 0, 176, 94, ++ 7, 0, 16, 49, 1, 134, 224, 6, 240, 16, 48, 0, 2, 222, 2, 240, 0, 0, ++ 0, 104, 0, 167, 1, 151, 154, 3, 191, 222, 2, 240, 17, 67, 0, 2, 94, ++ 2, 240, 17, 52, 0, 2, 94, 2, 240, 17, 68, 0, 2, 222, 2, 240, 0, 0, 0, ++ 104, 0, 167, 1, 151, 25, 0, 2, 222, 2, 240, 0, 0, 1, 129, 96, 6, 9, ++ 48, 73, 0, 104, 0, 167, 0, 145, 57, 0, 2, 94, 2, 240, 17, 69, 0, 2, ++ 222, 2, 240, 0, 0, 0, 2, 94, 2, 240, 17, 69, 1, 129, 96, 2, 9, 48, 73, ++ 0, 2, 222, 2, 240, 0, 0, 1, 136, 224, 14, 9, 48, 73, 0, 176, 65, 39, ++ 0, 24, 0, 0, 176, 0, 43, 0, 16, 2, 0, 2, 222, 2, 240, 0, 0, 1, 188, ++ 96, 3, 0, 16, 2, 1, 130, 224, 2, 15, 16, 120, 0, 2, 222, 2, 240, 0, ++ 0, 0, 104, 0, 167, 1, 151, 153, 0, 176, 65, 39, 0, 23, 161, 0, 176, ++ 65, 39, 1, 208, 73, 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, ++ 23, 161, 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, 23, 161, 0, ++ 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, ++ 0, 23, 161, 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, 23, 161, ++ 0, 176, 94, 135, 0, 23, 161, 0, 176, 94, 135, 0, 16, 73, 0, 2, 222, ++ 2, 240, 0, 0, 1, 0, 222, 83, 0, 23, 166, 1, 188, 96, 3, 0, 55, 161, ++ 3, 191, 222, 2, 240, 17, 86, 0, 2, 94, 2, 240, 1, 39, 1, 135, 96, 6, ++ 3, 55, 162, 0, 104, 222, 155, 0, 17, 90, 1, 135, 96, 2, 3, 55, 162, ++ 0, 2, 94, 2, 240, 1, 43, 0, 2, 222, 2, 240, 0, 0, 2, 2, 65, 31, 0, 17, ++ 111, 2, 130, 94, 83, 0, 17, 97, 1, 130, 96, 6, 242, 151, 148, 0, 176, ++ 68, 103, 0, 24, 0, 0, 176, 68, 107, 0, 8, 27, 0, 176, 68, 103, 0, 24, ++ 0, 0, 232, 68, 105, 3, 119, 164, 0, 104, 0, 167, 0, 145, 100, 0, 109, ++ 222, 147, 0, 81, 105, 0, 224, 68, 103, 3, 23, 163, 3, 144, 94, 2, 240, ++ 17, 108, 2, 133, 197, 35, 0, 17, 108, 0, 104, 222, 142, 35, 49, 102, ++ 1, 188, 96, 3, 2, 16, 71, 1, 188, 96, 3, 0, 144, 67, 1, 130, 96, 2, ++ 242, 151, 148, 1, 130, 96, 2, 245, 183, 173, 0, 104, 0, 167, 0, 145, ++ 111, 0, 104, 0, 167, 0, 177, 111, 0, 2, 222, 2, 240, 0, 0, 2, 1, 193, ++ 31, 0, 17, 130, 2, 133, 94, 175, 0, 17, 117, 1, 133, 96, 6, 245, 119, ++ 171, 0, 176, 68, 103, 0, 8, 30, 0, 176, 68, 107, 0, 8, 31, 0, 233, 68, ++ 101, 3, 215, 161, 0, 232, 196, 105, 3, 247, 162, 0, 208, 94, 135, 0, ++ 119, 161, 1, 225, 222, 138, 244, 55, 162, 0, 233, 94, 134, 38, 151, ++ 161, 0, 232, 222, 138, 38, 183, 162, 0, 105, 94, 139, 0, 17, 130, 1, ++ 188, 97, 3, 0, 17, 51, 0, 225, 68, 218, 244, 49, 54, 0, 225, 68, 222, ++ 244, 81, 55, 1, 133, 96, 2, 245, 119, 171, 1, 188, 96, 3, 1, 16, 71, ++ 1, 188, 96, 3, 0, 80, 67, 0, 2, 222, 2, 240, 0, 0, 2, 1, 174, 3, 0, ++ 17, 133, 2, 132, 197, 35, 0, 17, 143, 1, 188, 96, 15, 12, 16, 101, 0, ++ 224, 65, 149, 112, 16, 101, 2, 0, 46, 3, 0, 17, 137, 0, 224, 65, 151, ++ 0, 176, 101, 1, 188, 96, 15, 13, 23, 161, 0, 110, 65, 150, 244, 49, ++ 141, 0, 225, 90, 2, 41, 54, 128, 0, 224, 218, 7, 0, 22, 129, 1, 188, ++ 96, 3, 0, 11, 128, 1, 188, 96, 3, 0, 17, 73, 0, 2, 222, 2, 240, 0, 0, ++ 0, 176, 69, 31, 0, 23, 129, 0, 176, 5, 183, 0, 23, 166, 1, 188, 96, ++ 7, 4, 16, 100, 1, 188, 96, 19, 27, 144, 101, 1, 188, 96, 3, 0, 23, 161, ++ 2, 5, 222, 175, 0, 17, 170, 0, 176, 88, 15, 0, 23, 128, 0, 104, 222, ++ 132, 44, 49, 154, 0, 224, 88, 35, 0, 54, 8, 3, 191, 222, 2, 240, 17, ++ 178, 2, 0, 94, 155, 0, 17, 170, 2, 128, 218, 3, 0, 17, 160, 1, 24, 88, ++ 31, 0, 23, 130, 0, 224, 94, 11, 0, 55, 130, 1, 152, 94, 10, 192, 246, ++ 7, 3, 191, 222, 2, 240, 17, 163, 1, 26, 88, 31, 0, 23, 130, 0, 224, ++ 94, 11, 0, 55, 130, 1, 154, 94, 10, 192, 246, 7, 1, 240, 222, 3, 0, ++ 55, 128, 0, 160, 94, 2, 192, 87, 128, 0, 176, 94, 3, 0, 22, 3, 0, 160, ++ 68, 182, 240, 23, 130, 0, 176, 94, 11, 0, 22, 5, 0, 224, 94, 10, 192, ++ 150, 6, 3, 191, 222, 2, 240, 17, 178, 0, 176, 88, 19, 0, 23, 130, 0, ++ 232, 94, 6, 240, 87, 165, 0, 106, 222, 151, 0, 17, 176, 0, 232, 88, ++ 22, 244, 182, 5, 0, 105, 216, 23, 0, 17, 176, 1, 188, 96, 3, 0, 22, ++ 5, 0, 176, 88, 23, 0, 23, 165, 0, 224, 88, 18, 244, 182, 6, 0, 224, ++ 65, 147, 2, 16, 100, 0, 224, 65, 151, 6, 208, 101, 0, 224, 94, 135, ++ 0, 55, 161, 0, 144, 94, 155, 0, 55, 166, 0, 104, 222, 135, 0, 145, 149, ++ 1, 188, 96, 3, 0, 17, 71, 1, 188, 96, 3, 0, 1, 109, 0, 2, 222, 2, 240, ++ 0, 0, 1, 188, 96, 3, 0, 1, 108, 1, 188, 96, 3, 0, 1, 109, 1, 188, 96, ++ 7, 10, 16, 100, 1, 188, 96, 3, 0, 119, 161, 0, 176, 66, 143, 0, 23, ++ 128, 0, 160, 94, 3, 1, 247, 128, 0, 176, 94, 3, 0, 1, 110, 1, 188, 99, ++ 255, 31, 247, 162, 0, 104, 222, 3, 0, 17, 196, 1, 188, 96, 3, 0, 23, ++ 162, 0, 136, 96, 6, 244, 55, 129, 0, 32, 5, 186, 240, 49, 201, 0, 104, ++ 222, 138, 192, 209, 201, 0, 224, 5, 179, 0, 33, 108, 0, 176, 5, 182, ++ 240, 33, 109, 0, 104, 94, 3, 0, 17, 205, 0, 32, 94, 6, 240, 17, 211, ++ 0, 110, 222, 138, 192, 209, 211, 3, 191, 222, 2, 240, 17, 206, 0, 109, ++ 222, 138, 192, 209, 211, 0, 176, 94, 135, 0, 23, 163, 0, 176, 65, 147, ++ 0, 1, 102, 0, 176, 88, 27, 0, 23, 162, 1, 188, 96, 3, 0, 1, 108, 1, ++ 188, 96, 3, 0, 1, 109, 0, 232, 65, 147, 2, 16, 100, 0, 232, 94, 135, ++ 0, 55, 161, 0, 105, 222, 135, 0, 17, 196, 0, 176, 94, 143, 0, 1, 101, ++ 0, 2, 222, 2, 240, 0, 0, 0, 176, 5, 155, 0, 16, 100, 0, 176, 88, 27, ++ 0, 17, 69, 0, 176, 5, 155, 0, 1, 98, 0, 176, 5, 151, 0, 1, 97, 0, 176, ++ 88, 15, 0, 23, 133, 0, 176, 88, 7, 0, 23, 131, 0, 176, 88, 11, 0, 23, ++ 132, 1, 24, 88, 31, 0, 23, 140, 1, 26, 88, 31, 0, 23, 141, 0, 2, 222, ++ 2, 240, 0, 0, 0, 176, 5, 139, 0, 16, 100, 0, 110, 65, 147, 42, 17, 239, ++ 0, 160, 68, 182, 240, 183, 161, 0, 176, 94, 135, 0, 22, 5, 0, 224, 88, ++ 18, 244, 54, 6, 0, 176, 88, 27, 0, 17, 69, 2, 0, 0, 243, 0, 17, 236, ++ 0, 109, 65, 147, 40, 17, 236, 2, 0, 222, 175, 0, 17, 236, 1, 188, 96, ++ 11, 2, 81, 66, 0, 176, 94, 135, 0, 1, 111, 2, 1, 94, 175, 0, 17, 239, ++ 0, 176, 94, 23, 0, 22, 3, 1, 129, 96, 2, 245, 119, 171, 0, 2, 222, 2, ++ 240, 0, 0, 2, 1, 69, 35, 0, 17, 250, 2, 135, 196, 147, 0, 17, 250, 1, ++ 130, 96, 2, 245, 215, 174, 2, 1, 44, 35, 0, 17, 247, 0, 224, 44, 43, ++ 0, 43, 10, 1, 129, 96, 1, 97, 11, 8, 2, 6, 94, 183, 0, 17, 250, 0, 224, ++ 42, 215, 0, 42, 181, 1, 134, 96, 2, 245, 183, 173, 0, 2, 222, 2, 240, ++ 0, 0, 2, 2, 0, 191, 0, 18, 8, 0, 2, 94, 2, 240, 18, 48, 2, 2, 222, 179, ++ 0, 18, 0, 0, 104, 66, 143, 0, 15, 30, 3, 191, 222, 2, 240, 0, 2, 2, ++ 136, 129, 171, 0, 18, 8, 2, 132, 94, 255, 0, 17, 254, 2, 132, 94, 179, ++ 0, 17, 254, 2, 130, 222, 255, 0, 17, 254, 2, 130, 43, 47, 0, 18, 6, ++ 0, 104, 42, 155, 0, 18, 8, 2, 132, 222, 175, 0, 17, 254, 2, 132, 94, ++ 183, 0, 17, 254, 0, 176, 94, 135, 0, 23, 161, 0, 2, 222, 2, 240, 0, ++ 0, 1, 130, 224, 2, 245, 151, 172, 2, 3, 222, 255, 0, 18, 18, 2, 132, ++ 69, 35, 0, 18, 18, 2, 1, 43, 47, 0, 18, 18, 1, 128, 224, 6, 242, 151, ++ 148, 0, 2, 94, 2, 240, 17, 69, 1, 128, 224, 2, 242, 151, 148, 0, 2, ++ 94, 2, 240, 17, 69, 1, 128, 224, 2, 242, 151, 148, 2, 1, 172, 35, 0, ++ 17, 47, 1, 129, 224, 1, 97, 11, 8, 3, 191, 222, 2, 240, 17, 49, 2, 4, ++ 0, 199, 0, 18, 32, 2, 6, 171, 211, 0, 18, 26, 2, 132, 197, 175, 0, 18, ++ 46, 3, 191, 222, 2, 240, 18, 27, 2, 132, 197, 111, 0, 18, 46, 2, 132, ++ 69, 35, 0, 18, 29, 2, 0, 66, 3, 0, 18, 46, 0, 104, 94, 75, 4, 178, 46, ++ 0, 104, 94, 75, 6, 178, 46, 0, 104, 94, 75, 6, 50, 46, 1, 130, 224, ++ 6, 245, 151, 172, 2, 132, 69, 35, 0, 18, 35, 3, 35, 222, 2, 240, 18, ++ 36, 1, 131, 224, 6, 245, 151, 172, 1, 128, 224, 6, 242, 151, 148, 2, ++ 132, 0, 199, 0, 17, 47, 0, 176, 42, 215, 0, 23, 162, 0, 109, 222, 137, ++ 85, 17, 47, 2, 135, 43, 47, 0, 18, 43, 2, 0, 94, 255, 0, 17, 47, 2, ++ 7, 171, 47, 0, 17, 47, 1, 129, 224, 5, 97, 11, 8, 3, 191, 222, 2, 240, ++ 17, 49, 3, 191, 222, 2, 240, 17, 47, 0, 2, 222, 2, 240, 0, 0, 2, 2, ++ 0, 191, 0, 20, 55, 2, 6, 171, 211, 0, 18, 61, 1, 4, 193, 7, 0, 23, 161, ++ 1, 133, 94, 133, 97, 11, 8, 2, 4, 44, 35, 0, 18, 61, 1, 132, 96, 1, ++ 97, 11, 8, 1, 188, 96, 55, 0, 23, 162, 1, 188, 96, 3, 20, 23, 161, 0, ++ 176, 69, 227, 0, 24, 0, 0, 176, 69, 227, 0, 24, 0, 0, 176, 69, 227, ++ 0, 24, 0, 1, 188, 98, 3, 0, 16, 119, 1, 188, 96, 3, 27, 80, 118, 0, ++ 2, 94, 2, 240, 1, 62, 0, 104, 42, 235, 0, 18, 66, 0, 232, 68, 101, 87, ++ 87, 161, 1, 188, 99, 247, 29, 23, 162, 0, 109, 94, 134, 244, 82, 66, ++ 0, 232, 68, 102, 244, 74, 186, 0, 108, 196, 101, 86, 114, 68, 0, 232, ++ 68, 103, 0, 42, 179, 2, 6, 171, 211, 0, 18, 73, 0, 109, 196, 103, 1, ++ 82, 71, 1, 188, 96, 3, 0, 11, 16, 2, 132, 197, 175, 0, 18, 172, 3, 191, ++ 222, 2, 240, 18, 74, 2, 128, 69, 111, 0, 18, 172, 2, 7, 1, 171, 0, 18, ++ 76, 1, 128, 96, 2, 9, 208, 78, 1, 135, 224, 2, 245, 151, 172, 2, 4, ++ 222, 183, 0, 20, 55, 1, 132, 224, 2, 245, 183, 173, 1, 132, 224, 1, ++ 97, 11, 8, 2, 2, 222, 179, 0, 18, 106, 2, 6, 171, 211, 0, 18, 92, 0, ++ 104, 170, 247, 0, 146, 84, 0, 104, 43, 3, 0, 18, 85, 3, 191, 222, 2, ++ 240, 18, 90, 1, 139, 96, 14, 43, 145, 92, 2, 135, 171, 211, 0, 18, 89, ++ 1, 130, 96, 2, 9, 208, 78, 3, 191, 222, 2, 240, 18, 90, 1, 130, 96, ++ 6, 9, 208, 78, 0, 2, 94, 2, 240, 18, 10, 3, 191, 222, 2, 240, 18, 94, ++ 1, 131, 96, 6, 43, 145, 92, 0, 2, 94, 2, 240, 18, 10, 2, 130, 222, 187, ++ 0, 18, 106, 0, 104, 170, 247, 0, 146, 98, 1, 6, 171, 23, 0, 23, 187, ++ 0, 104, 222, 239, 0, 18, 102, 2, 132, 128, 199, 0, 18, 106, 0, 104, ++ 170, 247, 0, 50, 101, 0, 108, 196, 101, 86, 114, 105, 0, 104, 170, 247, ++ 0, 146, 106, 0, 104, 43, 3, 0, 18, 106, 0, 232, 69, 137, 90, 247, 161, ++ 0, 109, 94, 133, 96, 82, 106, 1, 132, 96, 2, 245, 183, 173, 2, 131, ++ 94, 187, 0, 18, 112, 2, 6, 171, 211, 0, 18, 110, 0, 232, 69, 201, 90, ++ 247, 161, 3, 191, 222, 2, 240, 18, 111, 0, 232, 69, 137, 90, 247, 161, ++ 0, 110, 94, 133, 84, 178, 141, 2, 5, 222, 183, 0, 18, 137, 0, 224, 43, ++ 151, 0, 42, 229, 1, 188, 96, 3, 0, 10, 231, 0, 104, 44, 71, 0, 18, 117, ++ 0, 232, 44, 71, 0, 43, 17, 1, 134, 96, 2, 245, 183, 173, 2, 4, 222, ++ 255, 0, 18, 127, 0, 176, 43, 155, 0, 23, 162, 0, 176, 42, 155, 0, 23, ++ 161, 2, 131, 172, 39, 0, 18, 124, 0, 104, 44, 135, 0, 18, 125, 0, 109, ++ 94, 133, 100, 50, 125, 0, 176, 44, 127, 0, 23, 162, 0, 109, 43, 150, ++ 244, 82, 127, 1, 132, 224, 2, 247, 247, 191, 2, 6, 222, 255, 0, 18, ++ 137, 0, 224, 43, 199, 2, 10, 241, 0, 176, 68, 103, 0, 10, 252, 1, 24, ++ 43, 199, 0, 23, 161, 1, 26, 43, 199, 0, 23, 162, 0, 110, 94, 135, 0, ++ 18, 135, 0, 109, 222, 137, 94, 82, 135, 3, 191, 222, 2, 240, 18, 137, ++ 1, 188, 96, 3, 0, 10, 241, 1, 134, 224, 2, 247, 247, 191, 2, 2, 94, ++ 255, 0, 20, 55, 0, 104, 170, 235, 0, 20, 55, 0, 176, 42, 199, 0, 10, ++ 186, 3, 191, 222, 2, 240, 20, 55, 1, 130, 224, 2, 247, 247, 191, 2, ++ 2, 94, 255, 0, 18, 150, 2, 6, 0, 199, 0, 18, 147, 2, 128, 43, 211, 0, ++ 18, 147, 0, 176, 43, 43, 0, 23, 187, 0, 110, 43, 2, 247, 116, 55, 2, ++ 2, 94, 255, 0, 18, 150, 0, 176, 68, 103, 0, 10, 186, 3, 191, 222, 2, ++ 240, 20, 55, 2, 5, 222, 183, 0, 18, 164, 0, 104, 42, 247, 8, 114, 153, ++ 0, 232, 68, 101, 85, 202, 182, 0, 104, 44, 71, 0, 18, 155, 0, 232, 44, ++ 71, 0, 43, 17, 0, 224, 43, 159, 0, 42, 231, 0, 176, 43, 163, 0, 23, ++ 161, 0, 176, 42, 155, 0, 23, 162, 2, 131, 172, 39, 0, 18, 161, 0, 104, ++ 44, 135, 0, 18, 162, 0, 109, 94, 137, 100, 50, 162, 0, 176, 44, 131, ++ 0, 23, 161, 0, 109, 43, 158, 244, 50, 164, 1, 188, 96, 3, 0, 10, 229, ++ 0, 104, 170, 247, 0, 178, 167, 0, 176, 68, 103, 0, 10, 239, 0, 176, ++ 68, 107, 0, 10, 243, 0, 104, 170, 247, 1, 50, 171, 0, 176, 68, 103, ++ 0, 11, 11, 2, 6, 43, 211, 0, 18, 171, 0, 176, 44, 123, 1, 11, 30, 3, ++ 191, 222, 2, 240, 20, 55, 2, 7, 1, 171, 0, 18, 174, 1, 128, 96, 6, 9, ++ 208, 78, 2, 4, 222, 183, 0, 18, 181, 2, 130, 222, 179, 0, 20, 55, 2, ++ 3, 197, 115, 0, 19, 250, 0, 232, 68, 101, 86, 55, 161, 0, 109, 94, 133, ++ 85, 180, 55, 1, 131, 96, 6, 245, 215, 174, 3, 191, 222, 2, 240, 20, ++ 55, 1, 135, 224, 6, 245, 151, 172, 0, 225, 14, 211, 0, 35, 180, 0, 224, ++ 142, 215, 0, 3, 181, 2, 6, 171, 211, 0, 18, 191, 1, 188, 96, 3, 0, 10, ++ 215, 0, 109, 69, 199, 31, 82, 188, 0, 176, 69, 199, 0, 10, 215, 0, 224, ++ 68, 101, 90, 247, 187, 0, 232, 94, 238, 46, 42, 177, 3, 191, 222, 2, ++ 240, 18, 196, 1, 188, 96, 3, 0, 10, 215, 0, 109, 69, 135, 31, 82, 194, ++ 0, 176, 69, 135, 0, 10, 215, 0, 224, 68, 101, 90, 247, 187, 0, 232, ++ 94, 238, 44, 42, 177, 1, 131, 96, 2, 245, 215, 174, 1, 132, 224, 6, ++ 245, 183, 173, 1, 133, 224, 2, 245, 183, 173, 1, 130, 96, 2, 247, 247, ++ 191, 1, 133, 96, 2, 245, 183, 173, 2, 6, 171, 211, 0, 18, 204, 1, 1, ++ 69, 175, 0, 23, 161, 3, 191, 222, 2, 240, 18, 205, 1, 1, 69, 111, 0, ++ 23, 161, 1, 135, 94, 134, 245, 119, 171, 1, 188, 96, 3, 0, 11, 5, 0, ++ 232, 68, 101, 86, 55, 161, 0, 109, 94, 133, 93, 210, 207, 0, 109, 94, ++ 133, 85, 178, 211, 0, 224, 43, 99, 0, 42, 216, 0, 176, 42, 147, 0, 23, ++ 179, 2, 6, 171, 211, 0, 18, 226, 1, 188, 96, 3, 1, 145, 120, 0, 176, ++ 69, 227, 0, 24, 0, 0, 176, 69, 231, 0, 10, 196, 1, 188, 96, 3, 1, 177, ++ 120, 0, 176, 69, 227, 0, 24, 0, 0, 176, 69, 231, 0, 10, 197, 1, 188, ++ 96, 3, 1, 209, 120, 0, 176, 69, 227, 0, 24, 0, 0, 176, 69, 231, 0, 10, ++ 198, 1, 188, 96, 3, 1, 241, 120, 0, 176, 69, 227, 0, 24, 0, 0, 176, ++ 69, 231, 0, 10, 199, 3, 191, 222, 2, 240, 18, 238, 1, 188, 96, 3, 0, ++ 17, 120, 0, 176, 69, 227, 0, 24, 0, 0, 176, 69, 231, 0, 10, 196, 1, ++ 188, 96, 3, 0, 49, 120, 0, 176, 69, 227, 0, 24, 0, 0, 176, 69, 231, ++ 0, 10, 197, 1, 188, 96, 3, 0, 81, 120, 0, 176, 69, 227, 0, 24, 0, 0, ++ 176, 69, 231, 0, 10, 198, 1, 188, 96, 3, 0, 113, 120, 0, 176, 69, 227, ++ 0, 24, 0, 0, 176, 69, 231, 0, 10, 199, 1, 130, 224, 1, 97, 11, 8, 2, ++ 7, 171, 27, 0, 18, 241, 1, 130, 224, 5, 97, 11, 8, 0, 176, 43, 23, 0, ++ 23, 187, 1, 40, 94, 239, 0, 10, 189, 1, 188, 96, 19, 28, 87, 187, 2, ++ 24, 43, 27, 0, 18, 248, 1, 24, 43, 27, 0, 23, 166, 0, 128, 222, 154, ++ 247, 119, 187, 0, 176, 65, 183, 0, 23, 179, 2, 3, 43, 211, 0, 19, 0, ++ 0, 104, 42, 247, 2, 210, 251, 0, 104, 170, 247, 2, 179, 0, 1, 188, 96, ++ 19, 28, 87, 187, 2, 52, 171, 23, 0, 19, 0, 1, 52, 171, 23, 0, 23, 166, ++ 0, 128, 222, 154, 247, 119, 187, 0, 176, 65, 183, 0, 23, 179, 2, 2, ++ 44, 39, 0, 19, 2, 1, 134, 96, 5, 96, 171, 5, 0, 110, 42, 247, 1, 243, ++ 6, 0, 136, 96, 5, 87, 183, 187, 0, 32, 222, 237, 92, 83, 9, 3, 191, ++ 222, 2, 240, 19, 12, 0, 232, 42, 247, 2, 23, 187, 0, 136, 96, 6, 247, ++ 119, 187, 0, 32, 94, 237, 92, 115, 12, 1, 133, 96, 6, 245, 183, 173, ++ 2, 4, 128, 195, 0, 19, 12, 1, 132, 224, 5, 96, 171, 5, 0, 110, 42, 247, ++ 1, 243, 19, 0, 136, 96, 5, 87, 183, 187, 0, 32, 94, 239, 1, 147, 17, ++ 1, 134, 96, 1, 96, 171, 5, 0, 104, 172, 71, 0, 19, 23, 0, 32, 222, 237, ++ 90, 147, 22, 3, 191, 222, 2, 240, 19, 23, 0, 232, 42, 247, 2, 23, 187, ++ 0, 136, 96, 6, 247, 119, 187, 0, 32, 94, 237, 90, 179, 23, 1, 132, 96, ++ 5, 96, 171, 5, 0, 104, 170, 247, 2, 243, 32, 1, 13, 171, 23, 0, 23, ++ 161, 1, 14, 171, 23, 0, 23, 162, 0, 104, 94, 135, 0, 19, 32, 0, 224, ++ 94, 134, 244, 87, 161, 0, 224, 94, 135, 8, 10, 189, 1, 134, 96, 1, 96, ++ 171, 5, 0, 104, 44, 71, 0, 19, 32, 1, 132, 96, 1, 96, 171, 5, 2, 3, ++ 43, 211, 0, 19, 44, 1, 131, 96, 1, 90, 170, 213, 0, 104, 42, 247, 2, ++ 211, 39, 0, 104, 170, 247, 2, 179, 60, 0, 104, 170, 231, 0, 19, 42, ++ 0, 104, 171, 35, 0, 19, 42, 2, 130, 222, 187, 0, 19, 42, 2, 7, 43, 27, ++ 0, 19, 42, 1, 132, 96, 5, 96, 171, 5, 3, 191, 222, 2, 240, 19, 60, 2, ++ 131, 197, 115, 0, 19, 60, 0, 2, 94, 2, 240, 21, 197, 0, 104, 170, 247, ++ 2, 179, 60, 1, 131, 96, 5, 90, 170, 213, 0, 224, 44, 143, 0, 43, 35, ++ 1, 133, 96, 2, 245, 183, 173, 0, 104, 170, 231, 0, 19, 60, 0, 104, 171, ++ 35, 0, 19, 60, 2, 130, 222, 187, 0, 19, 60, 0, 176, 42, 195, 0, 23, ++ 162, 1, 52, 43, 27, 0, 23, 161, 0, 110, 222, 135, 6, 19, 55, 0, 176, ++ 42, 191, 0, 23, 162, 0, 110, 94, 137, 100, 115, 60, 1, 188, 96, 3, 0, ++ 11, 35, 1, 188, 96, 3, 0, 10, 218, 1, 133, 96, 6, 245, 183, 173, 1, ++ 132, 224, 5, 97, 11, 8, 0, 104, 170, 247, 0, 179, 70, 2, 7, 94, 255, ++ 0, 19, 70, 1, 52, 43, 27, 0, 23, 163, 0, 109, 222, 141, 96, 51, 70, ++ 0, 104, 94, 143, 0, 19, 70, 2, 131, 171, 23, 0, 19, 68, 1, 131, 96, ++ 5, 96, 171, 5, 3, 191, 222, 2, 240, 19, 70, 0, 176, 43, 219, 0, 10, ++ 240, 0, 176, 68, 107, 0, 10, 247, 0, 104, 170, 247, 1, 51, 85, 2, 2, ++ 172, 39, 0, 19, 73, 1, 134, 224, 5, 96, 171, 5, 2, 129, 171, 211, 0, ++ 19, 85, 1, 188, 96, 3, 0, 10, 218, 0, 104, 44, 47, 0, 19, 85, 0, 232, ++ 68, 101, 97, 119, 161, 0, 109, 94, 133, 97, 147, 82, 0, 176, 44, 51, ++ 0, 23, 162, 0, 224, 94, 137, 97, 183, 162, 0, 109, 222, 134, 244, 83, ++ 84, 2, 0, 172, 35, 0, 19, 85, 1, 133, 96, 5, 96, 171, 5, 3, 191, 222, ++ 2, 240, 19, 85, 1, 128, 224, 1, 97, 11, 8, 0, 104, 170, 247, 1, 19, ++ 88, 0, 176, 42, 199, 0, 10, 209, 1, 135, 224, 6, 247, 247, 191, 2, 7, ++ 222, 255, 0, 19, 90, 1, 129, 224, 5, 96, 171, 5, 0, 104, 42, 247, 0, ++ 51, 95, 0, 104, 42, 247, 1, 243, 95, 2, 133, 43, 211, 0, 19, 94, 0, ++ 104, 42, 247, 3, 19, 95, 0, 104, 170, 247, 0, 147, 112, 1, 130, 96, ++ 6, 247, 247, 191, 0, 176, 42, 199, 0, 10, 185, 0, 104, 170, 247, 3, ++ 19, 102, 0, 104, 43, 35, 0, 19, 102, 0, 176, 0, 19, 0, 10, 189, 0, 176, ++ 43, 127, 0, 10, 192, 3, 191, 222, 2, 240, 19, 111, 0, 104, 170, 247, ++ 0, 147, 112, 1, 28, 43, 23, 0, 10, 192, 1, 6, 171, 23, 0, 23, 187, 0, ++ 104, 94, 239, 0, 19, 109, 1, 188, 96, 3, 0, 106, 195, 0, 176, 44, 123, ++ 0, 75, 30, 3, 191, 222, 2, 240, 19, 111, 0, 168, 44, 123, 0, 75, 30, ++ 1, 188, 96, 3, 0, 138, 195, 0, 176, 42, 199, 0, 10, 200, 2, 2, 222, ++ 187, 0, 19, 125, 2, 132, 222, 255, 0, 19, 115, 2, 6, 222, 255, 0, 19, ++ 125, 0, 176, 42, 215, 0, 23, 162, 0, 109, 222, 137, 85, 19, 124, 0, ++ 176, 43, 155, 0, 23, 162, 0, 176, 42, 155, 0, 23, 161, 2, 131, 172, ++ 39, 0, 19, 122, 0, 104, 44, 135, 0, 19, 123, 0, 109, 94, 133, 100, 51, ++ 123, 0, 176, 44, 127, 0, 23, 162, 0, 109, 171, 150, 244, 83, 125, 1, ++ 130, 224, 5, 96, 171, 5, 2, 134, 171, 211, 0, 19, 139, 0, 136, 96, 5, ++ 87, 183, 161, 0, 32, 222, 133, 99, 147, 131, 0, 232, 42, 247, 2, 23, ++ 161, 0, 136, 96, 6, 244, 55, 161, 0, 32, 94, 133, 99, 179, 137, 0, 104, ++ 44, 111, 0, 19, 137, 1, 52, 43, 27, 0, 23, 162, 0, 110, 94, 139, 2, ++ 147, 136, 0, 176, 44, 123, 0, 43, 30, 3, 191, 222, 2, 240, 19, 137, ++ 0, 168, 44, 123, 0, 43, 30, 0, 104, 170, 247, 2, 243, 139, 0, 176, 68, ++ 103, 0, 11, 27, 0, 224, 94, 205, 84, 183, 179, 1, 130, 96, 2, 245, 215, ++ 174, 0, 176, 44, 43, 0, 23, 161, 0, 176, 42, 215, 0, 23, 162, 0, 109, ++ 94, 137, 85, 19, 146, 2, 134, 94, 183, 0, 19, 163, 3, 191, 222, 2, 240, ++ 19, 148, 0, 109, 94, 133, 95, 243, 168, 2, 129, 44, 35, 0, 19, 163, ++ 1, 188, 96, 31, 7, 112, 101, 1, 188, 96, 31, 17, 80, 100, 1, 188, 96, ++ 31, 17, 215, 164, 0, 104, 90, 3, 0, 19, 159, 0, 136, 88, 3, 0, 247, ++ 163, 1, 52, 216, 3, 0, 23, 162, 0, 233, 94, 142, 35, 55, 163, 1, 195, ++ 224, 2, 35, 87, 165, 0, 232, 222, 138, 244, 183, 162, 0, 104, 222, 139, ++ 0, 19, 159, 0, 110, 222, 142, 246, 115, 163, 0, 224, 65, 147, 0, 48, ++ 100, 0, 224, 65, 151, 1, 144, 101, 0, 109, 65, 146, 244, 147, 151, 3, ++ 191, 222, 2, 240, 19, 168, 0, 104, 42, 247, 0, 147, 168, 0, 104, 42, ++ 247, 0, 83, 168, 0, 104, 42, 247, 0, 115, 168, 1, 130, 96, 6, 245, 215, ++ 174, 0, 2, 94, 2, 240, 21, 197, 1, 188, 96, 19, 28, 87, 187, 1, 52, ++ 43, 27, 0, 23, 162, 0, 128, 222, 138, 247, 119, 187, 0, 176, 65, 183, ++ 0, 23, 162, 0, 104, 42, 247, 0, 83, 181, 0, 104, 42, 247, 2, 83, 181, ++ 0, 104, 42, 247, 2, 115, 181, 0, 104, 42, 247, 0, 115, 181, 0, 104, ++ 42, 247, 8, 83, 181, 0, 104, 42, 247, 8, 115, 181, 0, 104, 42, 247, ++ 8, 147, 181, 0, 104, 42, 247, 3, 211, 181, 3, 191, 222, 2, 240, 19, ++ 196, 1, 133, 224, 6, 245, 183, 173, 0, 104, 94, 139, 0, 19, 191, 0, ++ 176, 94, 139, 0, 10, 166, 1, 130, 224, 6, 245, 215, 174, 0, 104, 44, ++ 139, 0, 19, 188, 0, 110, 94, 137, 100, 83, 188, 1, 129, 96, 5, 99, 203, ++ 30, 0, 224, 43, 171, 0, 42, 234, 0, 110, 94, 137, 96, 19, 191, 1, 130, ++ 96, 5, 96, 171, 5, 0, 232, 68, 101, 86, 55, 161, 0, 176, 68, 103, 0, ++ 23, 163, 0, 104, 42, 247, 8, 147, 195, 0, 232, 94, 142, 244, 42, 174, ++ 1, 132, 96, 2, 247, 247, 191, 2, 130, 222, 179, 0, 20, 55, 2, 3, 197, ++ 115, 0, 19, 250, 0, 176, 42, 171, 0, 23, 162, 0, 176, 42, 179, 0, 23, ++ 163, 0, 104, 170, 247, 0, 147, 212, 2, 128, 43, 211, 0, 19, 212, 0, ++ 176, 43, 3, 0, 23, 161, 0, 109, 94, 133, 88, 115, 208, 1, 128, 224, ++ 5, 96, 171, 5, 0, 104, 43, 79, 0, 19, 208, 1, 188, 96, 3, 0, 10, 188, ++ 0, 2, 94, 2, 240, 21, 155, 0, 104, 94, 135, 0, 19, 212, 0, 104, 43, ++ 231, 0, 19, 212, 0, 176, 43, 231, 0, 23, 162, 0, 176, 43, 235, 0, 23, ++ 163, 0, 104, 94, 143, 0, 19, 221, 0, 104, 42, 235, 0, 19, 221, 0, 232, ++ 68, 101, 87, 87, 161, 0, 224, 94, 142, 244, 87, 162, 0, 109, 94, 134, ++ 244, 83, 221, 1, 129, 96, 5, 96, 171, 5, 0, 104, 43, 79, 0, 19, 221, ++ 1, 188, 96, 3, 0, 10, 188, 0, 2, 94, 2, 240, 21, 155, 2, 129, 171, 47, ++ 0, 19, 226, 2, 0, 94, 255, 0, 19, 226, 2, 4, 69, 35, 0, 19, 226, 3, ++ 160, 222, 2, 240, 19, 226, 1, 131, 224, 5, 96, 171, 5, 2, 129, 172, ++ 39, 0, 19, 250, 2, 134, 44, 23, 0, 20, 55, 2, 134, 172, 23, 0, 20, 55, ++ 2, 128, 128, 191, 0, 20, 55, 2, 130, 94, 187, 0, 20, 55, 2, 130, 43, ++ 211, 0, 19, 250, 2, 129, 172, 23, 0, 19, 250, 2, 128, 172, 23, 0, 19, ++ 250, 2, 129, 44, 23, 0, 19, 250, 2, 130, 44, 23, 0, 19, 250, 2, 136, ++ 129, 171, 0, 19, 250, 2, 130, 172, 23, 0, 19, 243, 2, 131, 43, 23, 0, ++ 19, 250, 2, 131, 44, 23, 0, 19, 243, 2, 133, 44, 23, 0, 19, 243, 2, ++ 132, 44, 23, 0, 19, 250, 2, 132, 172, 23, 0, 19, 250, 2, 131, 172, 23, ++ 0, 19, 250, 2, 132, 94, 183, 0, 19, 249, 2, 4, 222, 175, 0, 19, 249, ++ 2, 129, 222, 187, 0, 19, 249, 1, 132, 224, 2, 245, 119, 171, 0, 2, 94, ++ 2, 240, 21, 159, 3, 191, 222, 2, 240, 20, 55, 0, 232, 68, 101, 86, 55, ++ 161, 0, 109, 222, 133, 84, 180, 13, 2, 6, 171, 211, 0, 19, 255, 1, 131, ++ 224, 2, 43, 145, 92, 3, 191, 222, 2, 240, 20, 55, 1, 131, 224, 2, 43, ++ 145, 92, 2, 7, 1, 171, 0, 20, 2, 1, 128, 224, 2, 9, 208, 78, 1, 188, ++ 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, 24, 0, 1, 131, 96, 2, 47, 49, ++ 121, 2, 7, 222, 179, 0, 20, 9, 1, 135, 224, 2, 245, 151, 172, 0, 225, ++ 14, 219, 0, 35, 182, 0, 224, 142, 223, 0, 3, 183, 0, 104, 176, 55, 0, ++ 20, 12, 0, 176, 68, 103, 0, 12, 13, 0, 176, 68, 107, 0, 12, 14, 3, 191, ++ 222, 2, 240, 20, 55, 2, 129, 1, 171, 0, 20, 17, 2, 0, 129, 171, 0, 20, ++ 28, 2, 132, 44, 23, 0, 20, 28, 2, 128, 172, 23, 0, 20, 28, 2, 6, 171, ++ 211, 0, 20, 26, 0, 107, 172, 66, 35, 52, 21, 0, 224, 68, 103, 1, 75, ++ 16, 1, 139, 96, 2, 43, 145, 92, 2, 135, 171, 211, 0, 20, 24, 1, 130, ++ 96, 6, 9, 208, 78, 3, 191, 222, 2, 240, 20, 25, 1, 130, 96, 2, 9, 208, ++ 78, 3, 191, 222, 2, 240, 20, 27, 1, 131, 96, 2, 43, 145, 92, 3, 191, ++ 222, 2, 240, 20, 55, 2, 6, 171, 211, 0, 20, 37, 0, 107, 172, 66, 35, ++ 52, 32, 0, 224, 68, 103, 1, 75, 16, 1, 139, 96, 2, 43, 145, 92, 2, 135, ++ 171, 211, 0, 20, 35, 1, 130, 96, 6, 9, 208, 78, 3, 191, 222, 2, 240, ++ 20, 36, 1, 130, 96, 2, 9, 208, 78, 3, 191, 222, 2, 240, 20, 48, 1, 139, ++ 96, 2, 43, 145, 92, 1, 188, 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, ++ 24, 0, 1, 131, 96, 2, 47, 49, 121, 2, 7, 222, 179, 0, 20, 45, 1, 135, ++ 224, 2, 245, 151, 172, 0, 225, 14, 219, 0, 35, 182, 0, 224, 142, 223, ++ 0, 3, 183, 0, 104, 176, 55, 0, 20, 48, 0, 176, 68, 103, 0, 12, 13, 0, ++ 176, 68, 107, 0, 12, 14, 0, 2, 94, 2, 240, 18, 22, 2, 132, 94, 183, ++ 0, 20, 55, 2, 131, 43, 211, 0, 20, 52, 0, 104, 42, 247, 2, 180, 55, ++ 1, 132, 224, 6, 245, 119, 171, 0, 224, 43, 39, 0, 42, 201, 3, 191, 222, ++ 2, 240, 21, 135, 0, 2, 222, 2, 240, 0, 0, 1, 133, 224, 2, 245, 183, ++ 173, 1, 131, 96, 2, 245, 215, 174, 1, 130, 224, 2, 245, 215, 174, 1, ++ 130, 224, 2, 247, 247, 191, 1, 132, 224, 2, 247, 247, 191, 1, 188, 96, ++ 3, 0, 10, 211, 1, 188, 96, 3, 0, 10, 200, 1, 188, 96, 3, 0, 10, 192, ++ 1, 188, 96, 3, 0, 10, 234, 1, 135, 96, 1, 95, 106, 251, 0, 176, 68, ++ 103, 0, 12, 13, 0, 176, 68, 107, 0, 12, 14, 1, 129, 96, 1, 99, 203, ++ 30, 0, 2, 222, 2, 240, 0, 0, 2, 2, 0, 191, 0, 20, 165, 2, 131, 222, ++ 255, 0, 20, 215, 1, 131, 224, 6, 247, 247, 191, 1, 133, 96, 6, 11, 112, ++ 91, 1, 133, 96, 6, 11, 240, 95, 2, 6, 171, 211, 0, 20, 80, 1, 188, 96, ++ 3, 2, 17, 109, 0, 176, 42, 151, 0, 17, 110, 2, 128, 69, 171, 0, 20, ++ 105, 3, 191, 222, 2, 240, 20, 83, 1, 188, 96, 3, 2, 17, 93, 0, 176, ++ 42, 151, 0, 17, 94, 2, 128, 69, 107, 0, 20, 105, 2, 6, 171, 211, 0, ++ 20, 93, 0, 107, 172, 66, 35, 52, 87, 0, 224, 68, 103, 1, 75, 16, 1, ++ 139, 96, 2, 43, 145, 92, 2, 135, 171, 211, 0, 20, 90, 1, 130, 96, 6, ++ 9, 208, 78, 3, 191, 222, 2, 240, 20, 91, 1, 130, 96, 2, 9, 208, 78, ++ 1, 136, 96, 14, 45, 81, 106, 3, 191, 222, 2, 240, 20, 105, 1, 139, 96, ++ 2, 43, 145, 92, 1, 188, 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, 24, ++ 0, 1, 131, 96, 2, 47, 49, 121, 2, 7, 222, 179, 0, 20, 101, 1, 135, 224, ++ 2, 245, 151, 172, 0, 225, 14, 219, 0, 35, 182, 0, 224, 142, 223, 0, ++ 3, 183, 0, 104, 176, 55, 0, 20, 104, 0, 176, 68, 103, 0, 12, 13, 0, ++ 176, 68, 107, 0, 12, 14, 1, 136, 96, 14, 43, 81, 90, 0, 176, 65, 63, ++ 31, 240, 79, 0, 104, 42, 187, 0, 20, 111, 1, 132, 96, 6, 247, 247, 191, ++ 1, 188, 96, 47, 23, 23, 163, 0, 224, 68, 102, 244, 106, 180, 1, 188, ++ 96, 3, 0, 10, 174, 0, 2, 94, 2, 240, 20, 56, 0, 232, 68, 105, 95, 215, ++ 161, 0, 110, 222, 135, 0, 52, 121, 0, 176, 43, 215, 0, 10, 240, 1, 188, ++ 96, 3, 0, 10, 239, 0, 104, 42, 235, 0, 20, 121, 0, 176, 68, 103, 0, ++ 10, 185, 0, 232, 68, 101, 85, 74, 186, 0, 176, 42, 179, 0, 23, 161, ++ 0, 232, 42, 234, 244, 42, 186, 2, 128, 128, 191, 0, 20, 134, 2, 129, ++ 222, 187, 0, 20, 155, 2, 6, 171, 211, 0, 20, 126, 2, 4, 197, 175, 0, ++ 20, 134, 3, 191, 222, 2, 240, 20, 127, 2, 0, 69, 111, 0, 20, 134, 2, ++ 131, 197, 115, 0, 20, 134, 2, 6, 171, 211, 0, 20, 132, 1, 188, 99, 255, ++ 31, 247, 161, 0, 104, 197, 198, 244, 52, 155, 3, 191, 222, 2, 240, 20, ++ 134, 1, 188, 99, 255, 31, 247, 161, 0, 104, 197, 134, 244, 52, 155, ++ 2, 6, 171, 211, 0, 20, 141, 1, 139, 96, 14, 43, 145, 92, 2, 135, 171, ++ 211, 0, 20, 139, 1, 130, 96, 2, 9, 208, 78, 3, 191, 222, 2, 240, 20, ++ 140, 1, 130, 96, 6, 9, 208, 78, 3, 191, 222, 2, 240, 20, 151, 1, 139, ++ 96, 14, 43, 145, 92, 1, 188, 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, ++ 24, 0, 1, 139, 43, 46, 47, 49, 121, 0, 104, 48, 55, 0, 20, 151, 0, 233, ++ 68, 101, 129, 183, 166, 0, 232, 196, 105, 129, 215, 187, 0, 225, 14, ++ 226, 244, 195, 184, 0, 224, 142, 230, 247, 99, 185, 1, 188, 96, 3, 0, ++ 12, 13, 1, 132, 224, 2, 245, 183, 173, 1, 132, 224, 2, 245, 119, 171, ++ 1, 133, 224, 1, 97, 11, 8, 3, 191, 222, 2, 240, 21, 146, 2, 6, 171, ++ 211, 0, 20, 158, 0, 2, 94, 2, 240, 18, 22, 3, 191, 222, 2, 240, 20, ++ 160, 1, 131, 96, 2, 43, 145, 92, 0, 2, 94, 2, 240, 18, 22, 1, 132, 224, ++ 6, 245, 183, 173, 1, 132, 224, 6, 245, 119, 171, 2, 6, 171, 211, 0, ++ 20, 164, 1, 132, 96, 5, 97, 11, 8, 3, 191, 222, 2, 240, 21, 146, 1, ++ 141, 96, 2, 11, 240, 95, 2, 6, 171, 211, 0, 20, 169, 1, 136, 96, 14, ++ 45, 81, 106, 3, 191, 222, 2, 240, 20, 170, 1, 136, 96, 14, 43, 81, 90, ++ 2, 129, 129, 171, 0, 20, 192, 2, 6, 171, 211, 0, 20, 180, 0, 107, 172, ++ 66, 35, 52, 175, 0, 224, 68, 103, 1, 75, 16, 1, 139, 96, 6, 43, 145, ++ 92, 2, 135, 171, 211, 0, 20, 178, 1, 130, 96, 2, 9, 208, 78, 3, 191, ++ 222, 2, 240, 20, 179, 1, 130, 96, 6, 9, 208, 78, 3, 191, 222, 2, 240, ++ 20, 212, 1, 139, 96, 6, 43, 145, 92, 1, 188, 96, 3, 24, 81, 120, 0, ++ 176, 69, 227, 0, 24, 0, 1, 131, 96, 2, 47, 49, 121, 2, 7, 222, 179, ++ 0, 20, 188, 1, 135, 224, 2, 245, 151, 172, 0, 225, 14, 219, 0, 35, 182, ++ 0, 224, 142, 223, 0, 3, 183, 0, 104, 176, 55, 0, 20, 191, 0, 176, 68, ++ 103, 0, 12, 13, 0, 176, 68, 107, 0, 12, 14, 3, 191, 222, 2, 240, 20, ++ 212, 2, 6, 171, 211, 0, 20, 201, 0, 107, 172, 66, 35, 52, 196, 0, 224, ++ 68, 103, 1, 75, 16, 1, 139, 96, 2, 43, 145, 92, 2, 135, 171, 211, 0, ++ 20, 199, 1, 130, 96, 6, 9, 208, 78, 3, 191, 222, 2, 240, 20, 200, 1, ++ 130, 96, 2, 9, 208, 78, 3, 191, 222, 2, 240, 20, 212, 1, 139, 96, 2, ++ 43, 145, 92, 1, 188, 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, 24, 0, ++ 1, 131, 96, 2, 47, 49, 121, 2, 7, 222, 179, 0, 20, 209, 1, 135, 224, ++ 2, 245, 151, 172, 0, 225, 14, 219, 0, 35, 182, 0, 224, 142, 223, 0, ++ 3, 183, 0, 104, 176, 55, 0, 20, 212, 0, 176, 68, 103, 0, 12, 13, 0, ++ 176, 68, 107, 0, 12, 14, 1, 132, 224, 2, 245, 183, 173, 1, 132, 224, ++ 2, 245, 119, 171, 0, 2, 94, 2, 240, 20, 56, 0, 2, 222, 2, 240, 0, 0, ++ 0, 176, 68, 107, 0, 10, 254, 2, 2, 222, 179, 0, 20, 228, 2, 6, 171, ++ 211, 0, 20, 226, 1, 131, 96, 6, 43, 145, 92, 2, 135, 171, 211, 0, 20, ++ 223, 1, 130, 96, 2, 9, 208, 78, 3, 191, 222, 2, 240, 20, 224, 1, 130, ++ 96, 6, 9, 208, 78, 0, 2, 94, 2, 240, 18, 10, 3, 191, 222, 2, 240, 20, ++ 228, 1, 131, 96, 6, 43, 145, 92, 0, 2, 94, 2, 240, 18, 10, 2, 2, 0, ++ 191, 0, 21, 17, 1, 131, 224, 2, 247, 247, 191, 2, 3, 197, 115, 0, 20, ++ 252, 2, 0, 128, 191, 0, 20, 252, 2, 6, 171, 211, 0, 20, 241, 0, 107, ++ 172, 66, 35, 52, 236, 0, 224, 68, 103, 1, 75, 16, 1, 139, 96, 14, 43, ++ 145, 92, 2, 135, 171, 211, 0, 20, 239, 1, 130, 96, 2, 9, 208, 78, 3, ++ 191, 222, 2, 240, 20, 240, 1, 130, 96, 6, 9, 208, 78, 3, 191, 222, 2, ++ 240, 21, 16, 1, 139, 96, 14, 43, 145, 92, 1, 188, 96, 3, 24, 81, 120, ++ 0, 176, 69, 227, 0, 24, 0, 1, 139, 43, 46, 47, 49, 121, 0, 104, 48, ++ 55, 0, 20, 251, 0, 233, 68, 101, 129, 183, 166, 0, 232, 196, 105, 129, ++ 215, 187, 0, 225, 14, 226, 244, 195, 184, 0, 224, 142, 230, 247, 99, ++ 185, 1, 188, 96, 3, 0, 12, 13, 3, 191, 222, 2, 240, 21, 16, 2, 6, 171, ++ 211, 0, 21, 5, 0, 224, 68, 103, 0, 183, 187, 0, 108, 196, 102, 247, ++ 116, 254, 1, 139, 96, 2, 43, 145, 92, 2, 135, 171, 211, 0, 21, 3, 1, ++ 130, 96, 6, 9, 208, 78, 3, 191, 222, 2, 240, 21, 4, 1, 130, 96, 2, 9, ++ 208, 78, 3, 191, 222, 2, 240, 21, 16, 1, 139, 96, 2, 43, 145, 92, 1, ++ 188, 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, 24, 0, 1, 131, 96, 2, 47, ++ 49, 121, 2, 7, 222, 179, 0, 21, 13, 1, 135, 224, 2, 245, 151, 172, 0, ++ 225, 14, 219, 0, 35, 182, 0, 224, 142, 223, 0, 3, 183, 0, 104, 176, ++ 55, 0, 21, 16, 0, 176, 68, 103, 0, 12, 13, 0, 176, 68, 107, 0, 12, 14, ++ 1, 130, 224, 2, 245, 151, 172, 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, ++ 3, 0, 55, 162, 0, 32, 227, 254, 9, 21, 104, 0, 32, 224, 66, 13, 149, ++ 104, 2, 132, 94, 179, 0, 21, 104, 2, 128, 66, 3, 0, 21, 104, 2, 132, ++ 69, 35, 0, 21, 104, 3, 145, 94, 2, 240, 21, 104, 0, 104, 171, 79, 0, ++ 21, 104, 2, 130, 222, 255, 0, 21, 104, 0, 104, 42, 187, 0, 21, 30, 0, ++ 232, 68, 101, 85, 215, 185, 0, 232, 42, 154, 247, 55, 185, 2, 128, 94, ++ 255, 0, 21, 155, 2, 1, 128, 199, 0, 21, 146, 0, 176, 42, 215, 0, 23, ++ 161, 0, 109, 222, 133, 85, 21, 146, 2, 130, 222, 179, 0, 21, 104, 2, ++ 4, 128, 199, 0, 21, 77, 2, 3, 197, 115, 0, 21, 77, 0, 104, 94, 139, ++ 0, 21, 50, 2, 2, 171, 211, 0, 21, 40, 2, 133, 94, 187, 0, 21, 41, 2, ++ 130, 222, 187, 0, 21, 77, 0, 176, 43, 131, 0, 23, 161, 0, 110, 171, ++ 106, 244, 53, 50, 2, 3, 197, 115, 0, 21, 77, 0, 104, 42, 155, 0, 21, ++ 48, 0, 104, 42, 187, 0, 21, 50, 0, 106, 222, 229, 84, 245, 77, 0, 106, ++ 222, 229, 90, 85, 77, 2, 132, 172, 35, 0, 21, 50, 0, 104, 42, 231, 0, ++ 21, 77, 2, 148, 29, 243, 0, 21, 53, 2, 3, 222, 83, 0, 21, 58, 3, 191, ++ 222, 2, 240, 21, 56, 1, 20, 29, 243, 0, 23, 166, 0, 144, 28, 186, 244, ++ 215, 166, 2, 0, 94, 155, 0, 21, 58, 0, 176, 43, 135, 0, 10, 167, 3, ++ 191, 222, 2, 240, 21, 146, 1, 188, 96, 3, 2, 87, 146, 1, 188, 99, 255, ++ 31, 240, 195, 1, 188, 96, 3, 9, 16, 227, 1, 134, 94, 138, 28, 112, 227, ++ 1, 132, 96, 6, 28, 112, 227, 0, 104, 42, 239, 0, 21, 65, 1, 133, 224, ++ 6, 28, 112, 227, 1, 188, 96, 3, 3, 151, 130, 0, 2, 94, 2, 240, 21, 114, ++ 0, 176, 84, 19, 0, 16, 228, 0, 224, 67, 145, 91, 48, 228, 1, 188, 96, ++ 3, 0, 16, 238, 1, 188, 99, 255, 31, 240, 206, 0, 224, 42, 239, 0, 42, ++ 187, 1, 188, 97, 3, 0, 119, 166, 1, 20, 29, 243, 0, 23, 162, 0, 176, ++ 94, 139, 0, 12, 15, 1, 188, 97, 3, 3, 236, 16, 3, 191, 222, 2, 240, ++ 21, 98, 2, 132, 94, 183, 0, 21, 104, 1, 188, 96, 35, 8, 144, 230, 0, ++ 2, 94, 2, 240, 1, 106, 0, 176, 94, 207, 0, 16, 228, 0, 104, 170, 247, ++ 0, 53, 86, 2, 5, 172, 35, 0, 21, 86, 0, 232, 42, 206, 35, 55, 163, 0, ++ 109, 222, 142, 28, 149, 86, 0, 176, 94, 143, 0, 16, 228, 0, 104, 42, ++ 155, 0, 21, 94, 0, 176, 42, 219, 0, 16, 228, 2, 6, 171, 211, 0, 21, ++ 91, 2, 132, 197, 175, 0, 21, 94, 3, 191, 222, 2, 240, 21, 92, 2, 128, ++ 69, 111, 0, 21, 94, 0, 105, 94, 231, 0, 21, 94, 0, 224, 94, 229, 86, ++ 208, 228, 1, 188, 96, 3, 1, 215, 130, 0, 2, 94, 2, 240, 21, 114, 1, ++ 188, 97, 3, 0, 119, 166, 3, 191, 222, 2, 240, 21, 98, 0, 176, 0, 71, ++ 0, 16, 134, 0, 2, 94, 2, 240, 22, 2, 0, 2, 94, 2, 240, 16, 105, 1, 144, ++ 96, 10, 9, 16, 72, 1, 132, 96, 6, 245, 151, 172, 0, 176, 94, 155, 0, ++ 16, 128, 0, 2, 222, 2, 240, 0, 0, 2, 128, 94, 255, 0, 21, 109, 2, 129, ++ 222, 187, 0, 21, 109, 2, 1, 128, 199, 0, 21, 146, 2, 4, 128, 199, 0, ++ 21, 146, 1, 128, 96, 2, 247, 247, 191, 2, 128, 194, 143, 0, 21, 147, ++ 2, 1, 222, 187, 0, 21, 147, 1, 188, 96, 3, 0, 23, 162, 3, 191, 222, ++ 2, 240, 21, 19, 0, 104, 94, 75, 6, 53, 121, 2, 133, 222, 255, 0, 21, ++ 128, 0, 176, 43, 55, 0, 23, 161, 0, 109, 170, 238, 244, 53, 128, 1, ++ 188, 96, 3, 1, 55, 128, 0, 176, 43, 59, 0, 23, 161, 0, 109, 42, 238, ++ 244, 53, 123, 2, 129, 43, 211, 0, 21, 123, 1, 188, 96, 3, 1, 119, 128, ++ 1, 188, 96, 3, 0, 55, 129, 0, 2, 94, 2, 240, 1, 67, 1, 210, 222, 10, ++ 160, 48, 224, 0, 176, 84, 11, 0, 16, 225, 3, 191, 222, 2, 240, 21, 134, ++ 2, 128, 171, 211, 0, 21, 121, 1, 188, 96, 3, 1, 87, 128, 1, 188, 96, ++ 3, 0, 23, 129, 0, 2, 94, 2, 240, 1, 67, 0, 176, 84, 7, 0, 16, 224, 0, ++ 136, 94, 11, 0, 112, 225, 0, 2, 222, 2, 240, 0, 0, 0, 104, 42, 243, ++ 0, 21, 146, 2, 4, 222, 175, 0, 21, 146, 0, 232, 68, 101, 87, 151, 164, ++ 0, 110, 94, 145, 84, 245, 146, 0, 136, 94, 147, 0, 55, 164, 0, 109, ++ 94, 145, 84, 245, 146, 0, 2, 94, 2, 240, 21, 237, 3, 191, 222, 2, 240, ++ 21, 159, 0, 232, 68, 101, 87, 151, 164, 0, 136, 94, 147, 0, 55, 164, ++ 0, 2, 94, 2, 240, 21, 237, 3, 191, 222, 2, 240, 21, 159, 2, 132, 222, ++ 175, 0, 21, 150, 1, 129, 224, 2, 245, 215, 174, 3, 191, 222, 2, 240, ++ 21, 159, 0, 104, 43, 103, 0, 21, 155, 0, 224, 68, 101, 91, 42, 211, ++ 0, 104, 43, 107, 0, 21, 154, 0, 224, 68, 101, 90, 74, 211, 0, 2, 222, ++ 2, 240, 0, 0, 1, 128, 96, 6, 247, 247, 191, 0, 104, 42, 243, 0, 21, ++ 159, 0, 232, 68, 101, 87, 151, 164, 0, 2, 94, 2, 240, 21, 237, 1, 132, ++ 96, 2, 245, 151, 172, 1, 188, 96, 3, 0, 10, 188, 1, 188, 96, 3, 0, 10, ++ 211, 1, 188, 96, 3, 0, 10, 187, 1, 4, 222, 175, 0, 23, 161, 1, 132, ++ 94, 134, 245, 183, 173, 2, 132, 222, 175, 0, 21, 168, 1, 128, 96, 6, ++ 13, 144, 108, 0, 2, 222, 2, 240, 0, 0, 2, 133, 172, 35, 0, 21, 196, ++ 2, 3, 197, 115, 0, 21, 196, 0, 176, 42, 143, 0, 23, 163, 2, 2, 172, ++ 35, 0, 21, 173, 0, 176, 42, 175, 0, 23, 163, 2, 2, 222, 187, 0, 21, ++ 175, 0, 176, 42, 139, 0, 23, 163, 0, 224, 68, 102, 244, 106, 179, 1, ++ 133, 224, 5, 97, 11, 8, 0, 176, 68, 103, 0, 11, 3, 2, 6, 171, 211, 0, ++ 21, 183, 0, 107, 172, 66, 35, 53, 182, 0, 224, 68, 103, 1, 75, 16, 1, ++ 131, 224, 2, 43, 145, 92, 3, 191, 222, 2, 240, 21, 196, 1, 131, 224, ++ 2, 43, 145, 92, 2, 7, 1, 171, 0, 21, 186, 1, 128, 224, 2, 9, 208, 78, ++ 1, 188, 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, 24, 0, 1, 131, 96, 2, ++ 47, 49, 121, 2, 7, 222, 179, 0, 21, 193, 1, 135, 224, 2, 245, 151, 172, ++ 0, 225, 14, 219, 0, 35, 182, 0, 224, 142, 223, 0, 3, 183, 0, 104, 176, ++ 55, 0, 21, 196, 0, 176, 68, 103, 0, 12, 13, 0, 176, 68, 107, 0, 12, ++ 14, 0, 2, 222, 2, 240, 0, 0, 2, 2, 222, 179, 0, 21, 208, 2, 6, 171, ++ 211, 0, 21, 206, 1, 139, 96, 14, 43, 145, 92, 2, 135, 171, 211, 0, 21, ++ 203, 1, 130, 96, 2, 9, 208, 78, 3, 191, 222, 2, 240, 21, 204, 1, 130, ++ 96, 6, 9, 208, 78, 0, 2, 94, 2, 240, 18, 10, 3, 191, 222, 2, 240, 21, ++ 230, 1, 131, 96, 6, 43, 145, 92, 0, 2, 94, 2, 240, 18, 10, 2, 3, 197, ++ 115, 0, 21, 213, 2, 132, 222, 175, 0, 21, 213, 2, 129, 222, 187, 0, ++ 21, 213, 2, 128, 94, 255, 0, 21, 213, 2, 4, 94, 183, 0, 21, 236, 2, ++ 6, 171, 211, 0, 21, 220, 1, 139, 96, 14, 43, 145, 92, 2, 135, 171, 211, ++ 0, 21, 218, 1, 130, 96, 2, 9, 208, 78, 3, 191, 222, 2, 240, 21, 219, ++ 1, 130, 96, 6, 9, 208, 78, 3, 191, 222, 2, 240, 21, 230, 1, 139, 96, ++ 14, 43, 145, 92, 1, 188, 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, 24, ++ 0, 1, 139, 43, 46, 47, 49, 121, 0, 104, 48, 55, 0, 21, 230, 0, 233, ++ 68, 101, 129, 183, 166, 0, 232, 196, 105, 129, 215, 187, 0, 225, 14, ++ 226, 244, 195, 184, 0, 224, 142, 230, 247, 99, 185, 1, 188, 96, 3, 0, ++ 12, 13, 1, 131, 224, 1, 97, 11, 8, 1, 132, 96, 6, 245, 183, 173, 1, ++ 132, 224, 2, 245, 119, 171, 1, 188, 96, 3, 0, 10, 187, 1, 132, 96, 2, ++ 245, 151, 172, 1, 133, 224, 1, 97, 11, 8, 0, 2, 222, 2, 240, 0, 0, 0, ++ 104, 43, 91, 0, 21, 239, 0, 176, 43, 91, 0, 23, 164, 0, 109, 94, 145, ++ 85, 85, 241, 0, 176, 42, 171, 0, 23, 164, 0, 136, 43, 7, 0, 55, 165, ++ 0, 232, 43, 10, 244, 170, 194, 0, 136, 94, 147, 0, 55, 164, 0, 224, ++ 43, 10, 244, 138, 194, 0, 144, 43, 11, 0, 170, 193, 0, 176, 43, 7, 0, ++ 10, 167, 0, 2, 222, 2, 240, 0, 0, 3, 160, 222, 2, 240, 21, 251, 2, 0, ++ 66, 3, 0, 21, 251, 0, 2, 94, 2, 240, 13, 40, 1, 131, 224, 5, 97, 11, ++ 8, 1, 132, 96, 2, 245, 183, 173, 1, 132, 224, 6, 245, 119, 171, 1, 188, ++ 96, 3, 0, 10, 187, 1, 132, 96, 2, 245, 151, 172, 0, 176, 68, 103, 0, ++ 10, 188, 0, 2, 222, 2, 240, 0, 0, 1, 12, 129, 67, 0, 23, 161, 1, 188, ++ 96, 3, 0, 80, 138, 0, 104, 94, 7, 0, 22, 12, 0, 104, 222, 135, 0, 54, ++ 12, 1, 188, 96, 3, 0, 176, 138, 0, 104, 94, 7, 0, 54, 12, 2, 130, 222, ++ 3, 0, 22, 12, 1, 188, 96, 3, 0, 144, 138, 2, 131, 222, 3, 0, 22, 12, ++ 0, 224, 96, 10, 244, 208, 138, 0, 104, 94, 7, 0, 22, 20, 1, 144, 66, ++ 42, 161, 48, 138, 0, 104, 94, 7, 0, 54, 20, 1, 144, 66, 42, 160, 16, ++ 138, 1, 9, 222, 3, 0, 23, 162, 1, 143, 94, 138, 17, 80, 138, 0, 104, ++ 94, 139, 0, 22, 20, 1, 145, 224, 14, 17, 80, 138, 0, 2, 222, 2, 240, ++ 0, 0, 1, 9, 222, 3, 0, 23, 164, 0, 224, 90, 6, 244, 151, 165, 0, 144, ++ 94, 150, 244, 151, 165, 2, 3, 222, 3, 0, 22, 28, 2, 130, 222, 3, 0, ++ 22, 28, 1, 188, 97, 239, 8, 87, 166, 0, 128, 222, 150, 244, 215, 165, ++ 1, 22, 222, 135, 0, 23, 163, 0, 136, 94, 135, 0, 119, 161, 0, 225, 94, ++ 135, 2, 215, 161, 0, 224, 222, 143, 0, 23, 163, 1, 188, 96, 3, 0, 23, ++ 162, 2, 14, 94, 3, 0, 22, 35, 1, 188, 96, 3, 0, 55, 162, 0, 144, 94, ++ 150, 244, 87, 165, 0, 128, 222, 150, 244, 55, 161, 0, 225, 65, 183, ++ 255, 247, 166, 0, 225, 222, 135, 1, 247, 161, 0, 128, 222, 150, 244, ++ 119, 163, 0, 225, 222, 134, 13, 183, 161, 0, 224, 222, 143, 0, 23, 163, ++ 1, 122, 94, 134, 244, 119, 161, 0, 136, 94, 134, 244, 87, 161, 0, 176, ++ 94, 135, 0, 23, 162, 2, 135, 222, 3, 0, 22, 48, 0, 136, 94, 135, 0, ++ 87, 161, 3, 191, 222, 2, 240, 22, 61, 2, 135, 94, 3, 0, 22, 55, 1, 188, ++ 99, 155, 12, 215, 165, 0, 128, 222, 134, 244, 183, 161, 0, 225, 65, ++ 183, 255, 247, 165, 0, 224, 222, 135, 0, 23, 161, 0, 136, 94, 135, 0, ++ 87, 161, 3, 191, 222, 2, 240, 22, 61, 0, 136, 94, 135, 0, 87, 161, 1, ++ 188, 99, 155, 12, 247, 165, 0, 128, 222, 134, 244, 183, 161, 1, 188, ++ 98, 3, 0, 23, 165, 0, 225, 65, 182, 244, 183, 165, 0, 224, 222, 135, ++ 0, 23, 161, 0, 224, 94, 132, 0, 215, 161, 0, 2, 222, 2, 240, 0, 0, 2, ++ 0, 31, 247, 0, 0, 18, 2, 130, 222, 83, 0, 22, 69, 1, 136, 96, 2, 4, ++ 144, 36, 0, 224, 32, 146, 243, 8, 36, 0, 232, 32, 142, 243, 8, 35, 3, ++ 191, 222, 2, 240, 11, 54, 1, 184, 96, 22, 4, 144, 36, 1, 188, 96, 3, ++ 1, 208, 37, 3, 5, 94, 2, 240, 22, 86, 2, 135, 192, 55, 0, 12, 153, 3, ++ 134, 222, 2, 240, 12, 156, 0, 2, 94, 2, 240, 18, 47, 3, 92, 222, 2, ++ 240, 22, 71, 0, 216, 64, 155, 1, 23, 161, 0, 224, 94, 135, 2, 55, 152, ++ 0, 168, 94, 99, 0, 119, 152, 1, 2, 222, 83, 0, 23, 161, 1, 130, 224, ++ 2, 242, 151, 148, 1, 136, 222, 132, 255, 167, 253, 0, 110, 160, 142, ++ 243, 22, 86, 0, 232, 94, 99, 1, 208, 37, 1, 184, 96, 6, 4, 144, 36, ++ 3, 191, 222, 2, 240, 0, 2, 1, 129, 96, 4, 255, 167, 253, 1, 184, 96, ++ 10, 4, 144, 36, 3, 191, 222, 2, 240, 0, 2, 2, 40, 94, 135, 0, 22, 108, ++ 0, 176, 65, 147, 0, 23, 164, 0, 224, 65, 147, 0, 112, 100, 1, 10, 94, ++ 135, 0, 23, 162, 0, 232, 65, 146, 244, 80, 99, 1, 24, 94, 135, 0, 23, ++ 161, 0, 232, 96, 66, 244, 55, 162, 0, 136, 86, 2, 244, 54, 0, 0, 104, ++ 65, 142, 244, 150, 104, 0, 232, 65, 143, 0, 48, 99, 0, 232, 65, 147, ++ 0, 48, 100, 0, 104, 94, 139, 2, 22, 96, 0, 144, 86, 2, 244, 87, 163, ++ 0, 176, 88, 6, 244, 118, 1, 3, 191, 222, 2, 240, 22, 96, 0, 104, 65, ++ 146, 244, 150, 108, 0, 232, 65, 147, 0, 48, 100, 1, 188, 96, 3, 0, 22, ++ 0, 3, 191, 222, 2, 240, 22, 104, 0, 176, 94, 135, 0, 23, 161, 0, 2, ++ 222, 2, 240, 0, 0, 1, 128, 96, 2, 134, 20, 48, 0, 176, 80, 203, 0, 16, ++ 101, 1, 56, 80, 131, 0, 23, 161, 0, 104, 222, 59, 6, 54, 116, 0, 224, ++ 90, 51, 0, 54, 140, 0, 110, 218, 50, 244, 32, 18, 0, 176, 90, 11, 0, ++ 23, 162, 1, 188, 99, 255, 31, 247, 163, 0, 176, 80, 207, 0, 16, 100, ++ 0, 110, 218, 50, 244, 54, 121, 0, 176, 90, 55, 0, 23, 163, 0, 176, 88, ++ 19, 0, 23, 130, 1, 188, 96, 3, 0, 22, 4, 1, 188, 96, 27, 31, 215, 182, ++ 1, 2, 208, 199, 0, 23, 161, 0, 224, 65, 150, 244, 48, 101, 0, 224, 80, ++ 203, 0, 208, 100, 1, 188, 96, 3, 0, 23, 180, 1, 188, 96, 3, 0, 23, 128, ++ 1, 188, 96, 3, 0, 55, 129, 1, 135, 96, 4, 3, 16, 160, 0, 144, 82, 51, ++ 0, 151, 164, 0, 224, 65, 135, 1, 183, 181, 0, 104, 94, 210, 240, 86, ++ 160, 0, 224, 94, 218, 246, 144, 99, 0, 32, 216, 2, 240, 54, 148, 2, ++ 2, 80, 199, 0, 22, 154, 0, 144, 86, 3, 0, 151, 161, 0, 232, 94, 134, ++ 244, 151, 161, 1, 158, 96, 2, 244, 55, 161, 0, 109, 222, 135, 8, 22, ++ 154, 1, 10, 94, 135, 0, 23, 162, 1, 218, 96, 2, 244, 55, 161, 0, 224, ++ 94, 214, 244, 80, 99, 0, 136, 96, 6, 244, 55, 161, 0, 32, 86, 2, 244, ++ 54, 154, 0, 176, 88, 2, 240, 54, 0, 0, 224, 90, 43, 0, 54, 138, 0, 106, ++ 222, 210, 244, 118, 150, 0, 104, 222, 210, 240, 22, 155, 0, 224, 94, ++ 3, 0, 55, 128, 0, 104, 94, 3, 0, 54, 155, 1, 134, 224, 4, 3, 16, 160, ++ 3, 191, 222, 2, 240, 22, 155, 0, 106, 222, 210, 244, 118, 150, 0, 224, ++ 94, 211, 0, 55, 180, 0, 208, 94, 7, 0, 55, 129, 2, 152, 94, 211, 0, ++ 22, 133, 0, 224, 65, 147, 0, 48, 100, 3, 191, 222, 2, 240, 22, 133, ++ 0, 104, 94, 3, 0, 0, 18, 3, 191, 222, 2, 240, 6, 205, 2, 130, 208, 199, ++ 0, 22, 170, 0, 176, 42, 55, 0, 23, 161, 1, 184, 42, 50, 244, 54, 132, ++ 1, 2, 80, 19, 0, 22, 133, 1, 60, 80, 131, 0, 23, 161, 0, 176, 80, 167, ++ 0, 23, 164, 0, 109, 90, 50, 244, 54, 179, 1, 130, 224, 6, 134, 52, 49, ++ 2, 136, 80, 43, 0, 22, 175, 0, 176, 90, 51, 0, 23, 161, 1, 158, 94, ++ 134, 132, 244, 39, 1, 131, 96, 6, 134, 52, 49, 0, 2, 222, 2, 240, 0, ++ 0, 0, 176, 80, 115, 0, 23, 161, 1, 184, 80, 110, 244, 54, 132, 1, 6, ++ 208, 7, 0, 22, 133, 0, 176, 80, 171, 0, 23, 164, 0, 208, 96, 6, 192, ++ 151, 128, 0, 224, 65, 151, 0, 215, 181, 1, 10, 88, 19, 0, 23, 161, 0, ++ 224, 94, 214, 244, 55, 181, 0, 176, 88, 15, 0, 16, 99, 1, 22, 86, 3, ++ 0, 23, 129, 0, 104, 216, 19, 0, 22, 200, 1, 20, 0, 99, 0, 23, 161, 0, ++ 104, 222, 135, 0, 22, 190, 0, 136, 1, 59, 1, 22, 128, 3, 191, 222, 2, ++ 240, 22, 195, 0, 104, 222, 135, 0, 118, 193, 0, 160, 1, 59, 224, 22, ++ 128, 3, 191, 222, 2, 240, 22, 195, 0, 224, 94, 135, 9, 112, 98, 0, 136, ++ 84, 3, 1, 22, 128, 0, 232, 90, 3, 48, 22, 128, 1, 188, 96, 3, 0, 22, ++ 129, 1, 188, 96, 3, 0, 22, 130, 1, 188, 96, 3, 0, 22, 131, 3, 191, 222, ++ 2, 240, 22, 205, 0, 224, 65, 142, 192, 144, 99, 0, 110, 193, 142, 192, ++ 54, 205, 0, 232, 65, 142, 192, 48, 99, 0, 232, 88, 3, 0, 55, 161, 0, ++ 224, 65, 142, 244, 48, 99, 1, 56, 80, 163, 0, 23, 165, 0, 104, 88, 19, ++ 3, 246, 232, 0, 104, 65, 142, 192, 86, 232, 0, 109, 218, 10, 244, 182, ++ 232, 1, 22, 86, 3, 0, 23, 161, 0, 104, 222, 134, 240, 54, 232, 1, 88, ++ 86, 3, 0, 23, 161, 0, 224, 94, 135, 13, 215, 162, 0, 176, 94, 215, 0, ++ 16, 98, 0, 32, 222, 2, 160, 22, 223, 0, 224, 94, 134, 208, 55, 163, ++ 0, 224, 94, 142, 208, 119, 163, 0, 109, 90, 2, 244, 86, 232, 0, 110, ++ 94, 142, 244, 150, 232, 0, 232, 96, 2, 244, 54, 131, 0, 176, 94, 143, ++ 0, 22, 129, 0, 160, 90, 15, 0, 118, 131, 0, 224, 90, 11, 0, 54, 130, ++ 0, 232, 90, 2, 244, 86, 128, 0, 208, 94, 3, 0, 55, 128, 0, 224, 88, ++ 19, 0, 54, 4, 0, 224, 65, 143, 0, 48, 99, 2, 152, 88, 19, 0, 22, 229, ++ 0, 224, 94, 215, 0, 55, 181, 0, 110, 193, 142, 192, 54, 206, 0, 176, ++ 88, 3, 0, 16, 99, 3, 191, 222, 2, 240, 22, 206, 0, 176, 88, 19, 0, 23, ++ 161, 0, 104, 218, 55, 0, 22, 235, 0, 176, 94, 135, 0, 22, 141, 0, 109, ++ 222, 134, 209, 182, 237, 0, 176, 94, 135, 0, 22, 141, 0, 2, 222, 2, ++ 240, 0, 0, 1, 188, 96, 3, 0, 23, 161, 1, 135, 96, 4, 3, 16, 160, 1, ++ 188, 96, 3, 9, 144, 181, 0, 176, 0, 99, 0, 240, 180, 1, 188, 96, 87, ++ 3, 16, 182, 1, 188, 96, 3, 0, 144, 181, 0, 176, 0, 99, 0, 176, 180, ++ 0, 176, 66, 211, 0, 24, 0, 3, 23, 222, 2, 240, 22, 246, 3, 151, 222, ++ 2, 240, 22, 247, 0, 176, 42, 51, 0, 20, 47, 1, 142, 224, 12, 3, 16, ++ 160, 0, 109, 222, 2, 209, 182, 253, 0, 232, 90, 54, 240, 22, 141, 3, ++ 191, 222, 2, 240, 22, 255, 1, 188, 96, 3, 0, 22, 140, 1, 188, 96, 3, ++ 0, 22, 141, 0, 110, 90, 58, 240, 23, 2, 1, 188, 96, 3, 0, 22, 142, 3, ++ 191, 222, 2, 240, 23, 3, 0, 232, 90, 58, 240, 22, 142, 0, 176, 88, 7, ++ 0, 23, 161, 0, 224, 88, 14, 240, 22, 3, 0, 110, 216, 14, 244, 55, 9, ++ 0, 232, 94, 134, 192, 23, 161, 0, 232, 88, 14, 244, 54, 3, 0, 232, 88, ++ 15, 0, 54, 3, 1, 24, 94, 3, 0, 23, 161, 0, 109, 222, 3, 2, 23, 17, 0, ++ 232, 96, 66, 244, 55, 162, 0, 144, 90, 26, 244, 54, 134, 0, 136, 90, ++ 30, 244, 87, 162, 0, 144, 90, 30, 244, 54, 135, 0, 176, 90, 26, 244, ++ 86, 134, 3, 191, 222, 2, 240, 23, 19, 0, 144, 90, 30, 244, 54, 134, ++ 1, 188, 96, 3, 0, 22, 135, 0, 2, 222, 2, 240, 0, 0, 1, 88, 96, 3, 0, ++ 16, 42, 1, 184, 96, 10, 4, 144, 36, 1, 188, 96, 3, 2, 144, 4, 1, 137, ++ 224, 2, 13, 144, 108, 0, 2, 222, 2, 240, 0, 0, 2, 0, 222, 83, 0, 23, ++ 35, 1, 188, 96, 23, 7, 119, 161, 0, 2, 94, 2, 240, 1, 39, 0, 176, 64, ++ 103, 0, 23, 162, 0, 176, 94, 139, 0, 87, 162, 0, 2, 94, 2, 240, 1, 43, ++ 1, 188, 96, 3, 3, 55, 128, 1, 188, 96, 3, 0, 23, 129, 0, 2, 94, 2, 240, ++ 17, 43, 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 3, 3, 55, 128, 0, 2, 94, ++ 2, 240, 17, 38, 1, 131, 224, 6, 240, 55, 129, 1, 129, 224, 6, 240, 55, ++ 129, 0, 2, 94, 2, 240, 17, 43, 0, 176, 94, 7, 0, 23, 162, 0, 224, 68, ++ 103, 11, 87, 161, 0, 107, 68, 102, 244, 55, 42, 1, 188, 96, 3, 17, 55, ++ 128, 0, 2, 94, 2, 240, 17, 38, 1, 128, 96, 6, 240, 55, 129, 0, 2, 94, ++ 2, 240, 17, 43, 1, 188, 96, 3, 0, 151, 128, 0, 2, 94, 2, 240, 17, 38, ++ 1, 128, 96, 6, 240, 55, 129, 0, 2, 94, 2, 240, 17, 43, 0, 224, 68, 103, ++ 1, 87, 161, 0, 107, 68, 102, 244, 55, 52, 1, 188, 96, 3, 3, 55, 128, ++ 1, 160, 96, 126, 244, 87, 129, 0, 2, 94, 2, 240, 17, 43, 0, 224, 68, ++ 103, 7, 151, 161, 0, 107, 68, 102, 244, 55, 57, 1, 188, 96, 3, 17, 87, ++ 128, 0, 2, 94, 2, 240, 17, 38, 1, 132, 96, 6, 240, 55, 129, 0, 2, 94, ++ 2, 240, 17, 43, 0, 176, 94, 7, 0, 23, 162, 1, 188, 96, 3, 10, 55, 128, ++ 0, 2, 94, 2, 240, 17, 38, 1, 128, 96, 2, 240, 55, 129, 0, 2, 94, 2, ++ 240, 17, 43, 0, 224, 68, 103, 0, 55, 161, 0, 107, 68, 102, 244, 55, ++ 68, 1, 128, 96, 6, 240, 55, 129, 0, 2, 94, 2, 240, 17, 43, 1, 188, 96, ++ 3, 8, 87, 128, 0, 2, 94, 2, 240, 17, 38, 1, 138, 96, 2, 240, 55, 129, ++ 0, 2, 94, 2, 240, 17, 43, 0, 224, 68, 103, 0, 55, 161, 0, 107, 68, 102, ++ 244, 55, 76, 1, 138, 96, 14, 240, 55, 129, 0, 2, 94, 2, 240, 17, 43, ++ 0, 224, 68, 103, 6, 87, 161, 0, 107, 68, 102, 244, 55, 80, 1, 188, 96, ++ 3, 12, 183, 128, 0, 2, 94, 2, 240, 17, 38, 2, 128, 222, 7, 0, 23, 58, ++ 1, 188, 96, 3, 17, 87, 128, 1, 132, 96, 2, 244, 87, 129, 0, 2, 94, 2, ++ 240, 17, 43, 1, 188, 96, 3, 0, 55, 163, 2, 6, 171, 211, 0, 23, 91, 2, ++ 132, 197, 175, 0, 23, 103, 3, 191, 222, 2, 240, 23, 92, 2, 128, 69, ++ 111, 0, 23, 103, 1, 188, 96, 3, 0, 23, 163, 1, 139, 96, 14, 43, 145, ++ 92, 1, 188, 96, 3, 24, 81, 120, 0, 176, 69, 227, 0, 24, 0, 1, 139, 43, ++ 46, 47, 49, 121, 0, 104, 48, 55, 0, 23, 103, 0, 233, 68, 101, 129, 183, ++ 166, 0, 232, 196, 105, 129, 215, 187, 0, 225, 14, 226, 244, 195, 184, ++ 0, 224, 142, 230, 247, 99, 185, 1, 188, 96, 3, 0, 12, 13, 1, 188, 96, ++ 23, 7, 119, 161, 0, 2, 94, 2, 240, 1, 39, 0, 176, 64, 103, 0, 23, 162, ++ 0, 168, 94, 139, 0, 87, 162, 0, 2, 94, 2, 240, 1, 43, 0, 224, 68, 103, ++ 1, 87, 161, 0, 107, 68, 102, 244, 55, 109, 1, 188, 96, 3, 1, 183, 161, ++ 1, 188, 96, 3, 4, 119, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 19, ++ 10, 247, 161, 1, 188, 96, 3, 0, 23, 162, 0, 2, 94, 2, 240, 1, 43, 1, ++ 188, 96, 3, 1, 23, 164, 0, 232, 94, 147, 0, 55, 164, 1, 188, 96, 3, ++ 1, 215, 161, 0, 176, 94, 147, 0, 23, 162, 0, 2, 94, 2, 240, 1, 43, 1, ++ 188, 96, 19, 10, 215, 161, 1, 188, 96, 3, 0, 23, 162, 0, 2, 94, 2, 240, ++ 1, 43, 0, 104, 222, 147, 0, 23, 117, 0, 104, 94, 143, 0, 23, 127, 0, ++ 2, 222, 2, 240, 0, 0, 1, 188, 96, 39, 12, 183, 161, 1, 188, 96, 3, 1, ++ 151, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 39, 14, 183, 161, 1, ++ 188, 96, 3, 1, 55, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 3, 6, 87, ++ 164, 1, 188, 96, 3, 0, 119, 163, 1, 188, 96, 19, 9, 87, 161, 0, 2, 94, ++ 2, 240, 1, 39, 1, 128, 96, 6, 3, 55, 162, 0, 2, 94, 2, 240, 1, 43, 1, ++ 128, 96, 2, 244, 87, 162, 0, 2, 94, 2, 240, 1, 43, 0, 224, 68, 102, ++ 244, 151, 161, 0, 107, 68, 102, 244, 55, 142, 0, 232, 94, 143, 0, 55, ++ 163, 0, 104, 94, 143, 0, 23, 149, 1, 188, 96, 3, 3, 23, 164, 1, 188, ++ 96, 39, 15, 23, 161, 0, 2, 94, 2, 240, 1, 39, 0, 104, 192, 103, 31, ++ 247, 135, 1, 188, 96, 39, 14, 183, 161, 1, 188, 96, 3, 1, 247, 162, ++ 0, 2, 94, 2, 240, 1, 43, 0, 2, 222, 2, 240, 0, 0, 0, 2, 222, 2, 240, ++ 0, 0, 2, 0, 222, 83, 0, 23, 171, 1, 188, 96, 19, 14, 119, 161, 0, 2, ++ 94, 2, 240, 1, 39, 0, 160, 64, 103, 63, 236, 53, 1, 188, 96, 19, 20, ++ 151, 161, 0, 2, 94, 2, 240, 1, 39, 1, 150, 224, 2, 3, 55, 162, 0, 2, ++ 94, 2, 240, 1, 43, 1, 188, 96, 19, 9, 183, 161, 0, 2, 94, 2, 240, 1, ++ 39, 1, 135, 96, 2, 3, 55, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, ++ 19, 9, 151, 161, 0, 2, 94, 2, 240, 1, 39, 1, 135, 96, 6, 3, 55, 162, ++ 0, 2, 94, 2, 240, 1, 43, 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 115, 0, ++ 23, 163, 1, 188, 96, 19, 20, 151, 161, 0, 2, 94, 2, 240, 1, 39, 0, 160, ++ 64, 102, 244, 119, 164, 1, 150, 224, 30, 244, 151, 163, 0, 176, 94, ++ 141, 134, 183, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 19, 9, 183, ++ 161, 0, 2, 94, 2, 240, 1, 39, 1, 135, 96, 6, 3, 55, 162, 0, 2, 94, 2, ++ 240, 1, 43, 1, 188, 96, 19, 9, 151, 161, 0, 2, 94, 2, 240, 1, 39, 1, ++ 135, 96, 6, 3, 55, 162, 0, 2, 94, 2, 240, 1, 43, 0, 2, 222, 2, 240, ++ 0, 0, 0, 104, 222, 147, 0, 23, 191, 0, 224, 94, 3, 0, 87, 162, 1, 9, ++ 94, 139, 0, 23, 161, 3, 191, 222, 2, 240, 23, 199, 0, 104, 222, 147, ++ 0, 55, 195, 1, 16, 94, 3, 0, 23, 162, 0, 224, 94, 139, 0, 151, 161, ++ 3, 191, 222, 2, 240, 23, 199, 1, 48, 94, 3, 0, 23, 162, 0, 224, 94, ++ 139, 1, 151, 161, 0, 109, 94, 135, 5, 151, 199, 1, 188, 96, 3, 5, 151, ++ 161, 0, 2, 222, 2, 240, 0, 0, 0, 104, 43, 203, 0, 23, 205, 0, 176, 43, ++ 243, 0, 23, 161, 0, 224, 94, 133, 95, 183, 161, 0, 107, 222, 134, 35, ++ 55, 205, 1, 134, 224, 6, 247, 247, 191, 0, 2, 222, 2, 240, 0, 0, 0, ++ 104, 31, 51, 0, 23, 221, 2, 6, 171, 211, 0, 23, 210, 2, 132, 197, 175, ++ 0, 23, 221, 3, 191, 222, 2, 240, 23, 211, 2, 128, 69, 111, 0, 23, 221, ++ 2, 133, 197, 35, 0, 23, 221, 0, 104, 31, 51, 0, 55, 219, 0, 176, 31, ++ 199, 0, 23, 161, 0, 2, 94, 2, 240, 1, 39, 0, 168, 64, 100, 249, 215, ++ 162, 0, 176, 94, 136, 249, 183, 162, 0, 2, 94, 2, 240, 1, 43, 3, 191, ++ 222, 2, 240, 23, 221, 0, 168, 65, 56, 249, 215, 161, 0, 176, 94, 132, ++ 249, 176, 78, 0, 2, 222, 2, 240, 0, 0, 2, 6, 171, 211, 0, 23, 225, 2, ++ 132, 197, 175, 0, 23, 221, 3, 191, 222, 2, 240, 23, 226, 2, 128, 69, ++ 111, 0, 23, 221, 1, 88, 96, 3, 0, 16, 42, 1, 137, 224, 2, 13, 144, 108, ++ 1, 188, 96, 3, 0, 144, 4, 0, 176, 64, 19, 0, 23, 161, 0, 2, 222, 2, ++ 240, 0, 0, 1, 130, 96, 6, 15, 16, 120, 2, 7, 193, 227, 0, 23, 232, 1, ++ 188, 96, 3, 12, 23, 163, 1, 188, 96, 3, 0, 144, 118, 1, 188, 96, 3, ++ 0, 16, 119, 0, 2, 94, 2, 240, 1, 52, 1, 188, 96, 3, 12, 151, 163, 0, ++ 2, 94, 2, 240, 1, 47, 0, 136, 96, 17, 134, 55, 161, 1, 188, 94, 134, ++ 14, 240, 119, 0, 2, 94, 2, 240, 1, 52, 1, 188, 96, 3, 12, 23, 163, 1, ++ 188, 96, 3, 0, 176, 118, 1, 188, 96, 3, 0, 16, 119, 0, 2, 94, 2, 240, ++ 1, 52, 1, 188, 96, 3, 12, 151, 163, 0, 2, 94, 2, 240, 1, 47, 0, 136, ++ 96, 5, 134, 55, 161, 1, 188, 94, 134, 14, 208, 118, 0, 2, 94, 2, 240, ++ 1, 52, 1, 188, 96, 3, 0, 23, 163, 0, 2, 94, 2, 240, 1, 47, 1, 133, 96, ++ 6, 14, 208, 118, 0, 2, 94, 2, 240, 1, 52, 1, 188, 96, 3, 12, 23, 163, ++ 1, 188, 96, 3, 0, 48, 118, 1, 188, 96, 3, 0, 16, 119, 0, 2, 94, 2, 240, ++ 1, 52, 1, 188, 96, 3, 12, 151, 163, 0, 2, 94, 2, 240, 1, 47, 1, 172, ++ 96, 162, 14, 240, 119, 0, 2, 94, 2, 240, 1, 52, 1, 188, 96, 3, 0, 23, ++ 163, 0, 2, 94, 2, 240, 1, 47, 1, 133, 96, 6, 14, 208, 118, 0, 2, 94, ++ 2, 240, 1, 52, 1, 188, 96, 3, 12, 23, 163, 1, 188, 96, 3, 0, 48, 118, ++ 1, 188, 96, 3, 0, 16, 119, 0, 2, 94, 2, 240, 1, 52, 1, 188, 96, 3, 12, ++ 151, 163, 0, 2, 94, 2, 240, 1, 47, 1, 172, 96, 2, 14, 240, 119, 0, 2, ++ 94, 2, 240, 1, 52, 1, 188, 96, 3, 0, 23, 163, 0, 2, 94, 2, 240, 1, 47, ++ 1, 133, 96, 6, 14, 208, 118, 0, 2, 94, 2, 240, 1, 52, 1, 130, 96, 2, ++ 15, 16, 120, 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 19, 8, 23, 161, 0, ++ 2, 94, 2, 240, 1, 39, 1, 128, 96, 2, 3, 55, 162, 0, 2, 94, 2, 240, 1, ++ 43, 1, 188, 96, 3, 0, 55, 161, 0, 2, 94, 2, 240, 1, 39, 1, 136, 96, ++ 14, 3, 55, 162, 0, 104, 176, 199, 0, 24, 34, 1, 136, 96, 10, 3, 55, ++ 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 27, 6, 87, 161, 0, 2, 94, ++ 2, 240, 1, 39, 1, 136, 48, 198, 3, 55, 162, 0, 2, 94, 2, 240, 1, 43, ++ 0, 2, 94, 2, 240, 23, 231, 1, 188, 96, 19, 8, 23, 161, 0, 2, 94, 2, ++ 240, 1, 39, 1, 128, 96, 6, 3, 55, 162, 0, 2, 94, 2, 240, 1, 43, 0, 2, ++ 222, 2, 240, 0, 0, 1, 188, 96, 67, 8, 144, 230, 0, 2, 94, 2, 240, 1, ++ 106, 1, 188, 96, 79, 17, 16, 228, 1, 144, 96, 10, 9, 16, 72, 1, 188, ++ 96, 3, 0, 0, 6, 1, 188, 96, 3, 1, 215, 130, 1, 210, 222, 8, 119, 240, ++ 224, 0, 176, 15, 3, 0, 16, 225, 0, 176, 0, 71, 0, 16, 134, 0, 176, 15, ++ 31, 0, 16, 138, 1, 188, 96, 3, 0, 55, 129, 0, 2, 94, 2, 240, 16, 105, ++ 1, 188, 96, 3, 0, 16, 187, 1, 188, 97, 3, 0, 16, 128, 1, 130, 96, 6, ++ 16, 48, 129, 3, 208, 94, 2, 240, 3, 145, 0, 2, 222, 2, 240, 0, 0, 0, ++ 104, 31, 131, 0, 24, 148, 2, 128, 66, 3, 0, 24, 148, 2, 133, 197, 35, ++ 0, 24, 148, 0, 104, 31, 143, 0, 56, 148, 0, 104, 31, 139, 0, 56, 113, ++ 1, 188, 96, 19, 8, 23, 161, 0, 2, 94, 2, 240, 1, 39, 1, 128, 96, 2, ++ 3, 55, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 27, 27, 87, 161, 0, ++ 2, 94, 2, 240, 1, 39, 0, 176, 64, 103, 0, 12, 54, 1, 130, 224, 6, 3, ++ 55, 162, 0, 2, 94, 2, 240, 1, 43, 1, 132, 96, 6, 244, 87, 162, 0, 2, ++ 94, 2, 240, 1, 43, 1, 188, 96, 39, 15, 55, 161, 0, 2, 94, 2, 240, 1, ++ 39, 0, 176, 64, 103, 0, 12, 55, 1, 136, 96, 6, 3, 55, 162, 0, 2, 94, ++ 2, 240, 1, 43, 1, 188, 96, 39, 21, 151, 161, 0, 2, 94, 2, 240, 1, 39, ++ 0, 176, 64, 103, 0, 12, 56, 1, 155, 96, 22, 3, 55, 162, 1, 128, 96, ++ 6, 244, 87, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 19, 16, 119, 161, ++ 1, 188, 96, 11, 0, 23, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 19, ++ 16, 87, 161, 0, 2, 94, 2, 240, 1, 39, 1, 184, 96, 130, 3, 55, 162, 0, ++ 2, 94, 2, 240, 1, 43, 1, 188, 96, 19, 16, 55, 161, 0, 2, 94, 2, 240, ++ 1, 39, 1, 128, 224, 2, 3, 55, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, ++ 96, 3, 0, 7, 226, 1, 188, 96, 3, 0, 7, 227, 0, 104, 48, 239, 0, 24, ++ 105, 0, 224, 68, 101, 135, 103, 225, 3, 191, 222, 2, 240, 24, 106, 0, ++ 224, 68, 103, 8, 7, 225, 1, 188, 96, 19, 16, 55, 161, 0, 2, 94, 2, 240, ++ 1, 39, 1, 128, 96, 6, 3, 55, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, ++ 3, 0, 39, 226, 0, 2, 94, 2, 240, 1, 39, 2, 0, 64, 103, 0, 24, 133, 2, ++ 128, 66, 3, 0, 24, 133, 2, 133, 197, 35, 0, 24, 133, 1, 188, 96, 19, ++ 16, 55, 161, 0, 2, 94, 2, 240, 1, 39, 2, 0, 64, 103, 0, 24, 120, 0, ++ 108, 196, 100, 252, 56, 113, 0, 224, 48, 231, 0, 44, 57, 0, 224, 48, ++ 235, 0, 44, 58, 1, 188, 96, 19, 16, 247, 161, 0, 2, 94, 2, 240, 1, 39, ++ 0, 176, 64, 103, 0, 1, 132, 1, 188, 96, 19, 16, 215, 161, 0, 2, 94, ++ 2, 240, 1, 39, 0, 176, 64, 103, 0, 1, 133, 1, 188, 96, 43, 19, 87, 161, ++ 0, 2, 94, 2, 240, 1, 39, 0, 176, 64, 103, 0, 1, 134, 1, 188, 96, 19, ++ 17, 23, 161, 0, 2, 94, 2, 240, 1, 39, 0, 176, 64, 103, 0, 1, 135, 1, ++ 188, 96, 39, 21, 151, 161, 0, 176, 48, 227, 0, 23, 162, 0, 2, 94, 2, ++ 240, 1, 43, 1, 188, 96, 39, 15, 55, 161, 0, 176, 48, 223, 0, 23, 162, ++ 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 27, 27, 87, 161, 0, 176, 48, 219, ++ 0, 23, 162, 0, 2, 94, 2, 240, 1, 43, 1, 188, 96, 19, 8, 23, 161, 0, ++ 2, 94, 2, 240, 1, 39, 1, 128, 96, 6, 3, 55, 162, 0, 2, 94, 2, 240, 1, ++ 43, 1, 188, 96, 3, 0, 7, 226, 1, 188, 96, 3, 0, 7, 224, 0, 176, 94, ++ 135, 0, 23, 161, 0, 2, 222, 2, 240, 0, 0, 1, 188, 96, 3, 0, 12, 27, ++ 0, 176, 48, 163, 0, 23, 158, 0, 176, 48, 167, 0, 23, 157, 0, 176, 48, ++ 171, 0, 23, 156, 0, 176, 48, 175, 0, 23, 155, 3, 191, 222, 2, 240, 10, ++ 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 126, 192, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 126, 192, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 32, 0, 0, 0, 64, 17, 1, 0, 0, 0, 0, 0, 128, 22, 1, 0, ++ 128, 0, 0, 0, 128, 22, 1, 0, 128, 3, 0, 0, 128, 22, 0, 0, 0, 64, 0, ++ 0, 128, 26, 33, 0, 224, 3, 0, 0, 128, 22, 0, 2, 0, 64, 0, 0, 128, 26, ++ 16, 2, 0, 64, 0, 0, 128, 26, 16, 2, 2, 64, 0, 0, 128, 26, 97, 0, 224, ++ 3, 0, 0, 128, 22, 16, 2, 0, 64, 0, 0, 128, 26, 97, 1, 224, 19, 0, 0, ++ 128, 22, 48, 2, 0, 64, 0, 0, 128, 26, 16, 2, 0, 64, 0, 0, 128, 26, 28, ++ 2, 0, 64, 0, 0, 128, 26, 0, 2, 0, 0, 0, 0, 128, 26, 28, 10, 0, 64, 0, ++ 0, 128, 26, 28, 10, 32, 64, 0, 0, 128, 26, 31, 202, 32, 64, 0, 0, 128, ++ 26, 31, 202, 32, 64, 0, 0, 128, 26, 1, 0, 0, 0, 0, 0, 128, 30, 9, 0, ++ 0, 0, 0, 0, 128, 30, 0, 0, 0, 0, 0, 0, 128, 2, 0, 0, 0, 0, 0, 0, 128, ++ 2, 0, 0, 0, 0, 0, 0, 128, 2, 8, 0, 0, 0, 0, 0, 128, 30, 0, 0, 0, 0, ++ 0, 0, 128, 30, 1, 0, 0, 0, 0, 0, 128, 30, 17, 0, 0, 0, 0, 0, 128, 30, ++ 31, 202, 32, 192, 0, 0, 128, 26, 31, 202, 32, 192, 0, 0, 128, 26, 95, ++ 202, 32, 192, 0, 0, 128, 26, 176, 100, 0, 0, 0, 0, 128, 14, 0, 0, 40, ++ 0, 0, 0, 128, 18, 17, 0, 0, 0, 0, 0, 128, 30, 0, 0, 0, 0, 200, 37, 66, ++ 133, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, ++ 0, 64, 1, 95, 202, 32, 64, 0, 0, 64, 25, 31, 202, 32, 64, 0, 0, 64, ++ 25, 1, 0, 0, 0, 0, 0, 64, 29, 1, 0, 0, 0, 0, 0, 64, 29, 1, 0, 0, 0, ++ 0, 0, 64, 29, 9, 0, 0, 0, 0, 0, 64, 29, 31, 194, 32, 64, 0, 0, 64, 25, ++ 15, 0, 0, 0, 0, 0, 64, 29, 31, 194, 32, 192, 0, 0, 64, 25, 27, 194, ++ 32, 192, 0, 0, 64, 25, 32, 125, 0, 0, 0, 0, 64, 13, 0, 0, 32, 0, 0, ++ 0, 64, 17, 0, 0, 0, 0, 51, 4, 66, 137, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, ++ 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 27, 194, 32, 64, 0, 0, 64, ++ 25, 9, 0, 0, 0, 0, 0, 64, 29, 27, 194, 32, 64, 0, 0, 64, 25, 1, 0, 0, ++ 0, 0, 0, 64, 29, 0, 0, 0, 0, 0, 0, 64, 29, 31, 194, 32, 64, 0, 0, 64, ++ 25, 1, 0, 0, 0, 0, 0, 64, 29, 9, 0, 0, 0, 0, 0, 64, 29, 31, 194, 32, ++ 64, 0, 0, 64, 25, 11, 1, 0, 0, 0, 0, 64, 29, 31, 194, 32, 192, 0, 0, ++ 64, 25, 27, 194, 32, 192, 0, 0, 64, 25, 192, 119, 0, 0, 0, 0, 64, 13, ++ 0, 0, 40, 0, 0, 0, 64, 17, 0, 0, 0, 0, 51, 28, 66, 137, 0, 0, 0, 0, ++ 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 31, 194, ++ 32, 192, 0, 0, 64, 25, 31, 194, 32, 192, 0, 0, 64, 25, 97, 0, 224, 19, ++ 0, 0, 64, 21, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, ++ 0, 0, 0, 0, 64, 1, 97, 1, 224, 19, 0, 0, 64, 21, 19, 194, 32, 192, 0, ++ 0, 64, 25, 97, 1, 128, 19, 0, 0, 64, 21, 10, 1, 0, 0, 0, 0, 64, 29, ++ 19, 194, 32, 192, 0, 0, 64, 25, 8, 4, 0, 0, 0, 0, 0, 248, 0, 0, 0, 0, ++ 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, ++ 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 19, 194, 32, 64, 0, 0, 64, ++ 25, 11, 1, 0, 0, 0, 0, 64, 29, 19, 194, 32, 192, 0, 0, 64, 25, 0, 0, ++ 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 3, 1, 0, 0, 0, 0, 64, 29, ++ 19, 194, 32, 64, 0, 0, 64, 25, 0, 0, 8, 0, 0, 0, 64, 17, 97, 1, 128, ++ 19, 0, 0, 64, 21, 97, 1, 128, 19, 0, 0, 64, 21, 97, 1, 128, 19, 0, 0, ++ 64, 21, 31, 194, 32, 64, 0, 0, 64, 25, 31, 194, 32, 64, 0, 0, 64, 25, ++ 31, 194, 32, 64, 0, 0, 64, 25, 11, 1, 0, 0, 0, 0, 64, 29, 11, 1, 0, ++ 0, 0, 0, 64, 29, 31, 194, 32, 192, 0, 0, 64, 25, 27, 194, 32, 192, 0, ++ 0, 64, 25, 195, 119, 0, 0, 0, 0, 64, 13, 0, 0, 8, 0, 0, 0, 64, 17, 0, ++ 0, 0, 0, 19, 28, 66, 136, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, ++ 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 27, 194, 32, 64, 0, 0, 64, 25, 9, 0, ++ 0, 0, 0, 0, 64, 29, 27, 202, 32, 64, 0, 0, 64, 25, 31, 202, 32, 64, ++ 0, 0, 64, 25, 9, 0, 0, 0, 0, 0, 64, 29, 31, 194, 32, 64, 0, 0, 64, 25, ++ 15, 0, 0, 0, 0, 0, 64, 29, 31, 194, 32, 192, 0, 0, 64, 25, 27, 194, ++ 32, 192, 0, 0, 64, 25, 35, 125, 0, 0, 0, 0, 64, 13, 0, 0, 0, 0, 0, 0, ++ 64, 17, 0, 0, 0, 0, 19, 4, 66, 136, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, 0, ++ 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 27, 194, 32, 64, 0, 0, 64, ++ 25, 9, 0, 0, 0, 0, 0, 64, 29, 27, 202, 32, 64, 0, 0, 64, 25, 1, 0, 0, ++ 0, 0, 0, 64, 29, 31, 202, 32, 64, 0, 0, 64, 25, 17, 0, 0, 0, 0, 0, 64, ++ 29, 31, 202, 32, 64, 0, 0, 64, 25, 31, 202, 32, 192, 0, 0, 64, 25, 31, ++ 202, 32, 192, 0, 0, 64, 25, 31, 202, 32, 192, 0, 0, 64, 25, 95, 202, ++ 32, 192, 0, 0, 64, 25, 176, 100, 0, 0, 0, 0, 64, 13, 0, 0, 8, 0, 0, ++ 0, 64, 17, 17, 0, 0, 0, 0, 0, 64, 29, 0, 0, 0, 0, 184, 37, 66, 132, ++ 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, 64, 1, 0, 0, 0, 0, 0, 0, ++ 64, 1, 95, 202, 32, 64, 0, 0, 64, 25, 1, 0, 0, 0, 0, 0, 64, 29, 31, ++ 202, 32, 64, 0, 0, 64, 25, 31, 202, 32, 64, 0, 0, 64, 25, 0, 0, 0, 0, ++ 0, 0, 64, 29, 28, 10, 32, 64, 0, 0, 0, 24, 28, 10, 32, 64, 0, 0, 0, ++ 24, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 28, 97, 1, 128, 19, ++ 0, 0, 0, 20, 28, 10, 32, 64, 0, 0, 0, 24, 97, 1, 128, 3, 0, 0, 0, 20, ++ 16, 10, 32, 64, 0, 0, 0, 24, 0, 10, 32, 64, 0, 0, 0, 24, 0, 10, 0, 64, ++ 0, 0, 0, 24, 65, 1, 128, 3, 0, 0, 0, 20, 0, 8, 0, 64, 0, 0, 0, 24, 0, ++ 0, 16, 0, 0, 0, 0, 16, 0, 8, 2, 64, 0, 0, 0, 24, 0, 8, 3, 64, 0, 0, ++ 0, 24, 0, 8, 2, 64, 0, 0, 0, 24, 0, 8, 0, 64, 0, 0, 0, 24, 0, 0, 0, ++ 0, 0, 0, 0, 16, 0, 8, 0, 64, 0, 0, 0, 24, 0, 8, 0, 64, 0, 0, 0, 24, ++ 65, 1, 128, 0, 0, 0, 0, 20, 65, 1, 0, 0, 0, 0, 0, 20, 64, 1, 0, 0, 0, ++ 0, 0, 20, 0, 8, 2, 64, 0, 0, 0, 24, 0, 1, 0, 0, 0, 0, 0, 20, 0, 8, 0, ++ 64, 0, 0, 0, 24, 0, 8, 0, 192, 0, 0, 0, 24, 8, 12, 0, 0, 0, 0, 0, 4, ++ 8, 8, 0, 0, 0, 0, 0, 252, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 89, 109, 72, 25, 7, 45, 98, 95, 153, 190, ++ 51, 94, 0, 91, 35, 75, 69, 37, 36, 71, 40, 8, 0, 0, 0, 0, 0, 30, 140, ++ 252, 90, 19, 1, 189, 50, 8, 1, 0, 52, 51, 52, 51, 48, 97, 49, 45, 114, ++ 111, 109, 108, 47, 115, 100, 105, 111, 45, 103, 45, 112, 111, 111, 108, ++ 45, 112, 50, 112, 45, 105, 100, 115, 117, 112, 45, 105, 100, 97, 117, ++ 116, 104, 45, 112, 107, 116, 102, 105, 108, 116, 101, 114, 45, 107, ++ 101, 101, 112, 97, 108, 105, 118, 101, 45, 97, 111, 101, 45, 108, 112, ++ 99, 45, 115, 119, 100, 105, 118, 45, 115, 114, 102, 97, 115, 116, 45, ++ 102, 117, 97, 114, 116, 45, 98, 116, 99, 120, 104, 121, 98, 114, 105, ++ 100, 104, 119, 45, 110, 111, 99, 108, 109, 105, 110, 99, 45, 99, 108, ++ 109, 95, 109, 105, 110, 45, 102, 98, 116, 45, 109, 102, 112, 45, 115, ++ 97, 101, 45, 116, 107, 111, 32, 86, 101, 114, 115, 105, 111, 110, 58, ++ 32, 55, 46, 52, 53, 46, 57, 56, 46, 57, 53, 32, 40, 114, 55, 50, 52, ++ 51, 48, 51, 32, 67, 89, 41, 32, 67, 82, 67, 58, 32, 101, 54, 98, 55, ++ 57, 50, 97, 54, 32, 68, 97, 116, 101, 58, 32, 84, 104, 117, 32, 50, ++ 48, 50, 48, 45, 48, 49, 45, 51, 48, 32, 50, 49, 58, 52, 51, 58, 53, ++ 51, 32, 80, 83, 84, 32, 85, 99, 111, 100, 101, 32, 86, 101, 114, 58, ++ 32, 49, 48, 52, 51, 46, 50, 49, 51, 55, 32, 70, 87, 73, 68, 32, 48, ++ 49, 45, 53, 97, 102, 99, 56, 99, 49, 101, 0, 254, 0, 68, 86, 73, 68, ++ 32, 48, 49, 45, 101, 100, 48, 100, 55, 97, 53, 54 ++}; ++resource_hnd_t wifi_firmware_image = { RESOURCE_IN_EXTERNAL_STORAGE, 421098, {.fs = { 0, "/wlan/4343WA1.BIN" }}}; ++ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c +new file mode 100644 +index 0000000000..616bdedf2e +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c +@@ -0,0 +1,400 @@ ++/* ++ * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved ++ * SPDX-License-Identifier: LicenseRef-PBL ++ * ++ * This file and the related binary are licensed under the ++ * Permissive Binary License, Version 1.0 (the "License"); ++ * you may not use these files except in compliance with the License. ++ * ++ * You may obtain a copy of the License here: ++ * LICENSE-permissive-binary-license-1.0.txt and at ++ * https://www.mbed.com/licenses/PBL-1.0 ++ * ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++#include "wiced_resource.h" ++ ++#if defined(CY_STORAGE_WIFI_DATA) ++CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) ++#endif ++const unsigned char wifi_firmware_clm_blob_image_data[7222] = { ++ 66, 76, 79, 66, 60, 0, 0, 0, 132, 159, 16, 216, 1, 0, 0, 0, 2, 0, 0, ++ 0, 0, 0, 0, 0, 60, 0, 0, 0, 246, 27, 0, 0, 183, 10, 32, 40, 0, 0, 0, ++ 0, 0, 0, 0, 0, 50, 28, 0, 0, 4, 0, 0, 0, 42, 255, 237, 159, 0, 0, 0, ++ 0, 67, 76, 77, 32, 68, 65, 84, 65, 0, 0, 12, 0, 2, 0, 57, 46, 49, 48, ++ 46, 51, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 46, 50, 57, 46, ++ 52, 0, 0, 0, 0, 0, 0, 0, 0, 184, 10, 0, 0, 67, 108, 109, 73, 109, 112, ++ 111, 114, 116, 58, 32, 49, 46, 51, 54, 46, 51, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 66, 114, 111, 97, 100, 99, 111, 109, 45, 48, 46, 48, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 49, 0, 81, 50, 0, 3, 3, 3, 9, 3, 11, ++ 4, 4, 4, 7, 4, 8, 4, 10, 4, 11, 5, 7, 8, 8, 9, 9, 9, 11, 11, 11, 38, ++ 38, 38, 46, 38, 62, 38, 110, 38, 118, 38, 134, 38, 142, 38, 159, 38, ++ 175, 46, 46, 54, 54, 54, 62, 54, 134, 62, 62, 102, 102, 102, 110, 102, ++ 134, 102, 142, 102, 159, 110, 126, 110, 134, 110, 142, 134, 134, 134, ++ 159, 142, 142, 151, 151, 151, 159, 151, 175, 159, 159, 65, 69, 1, 65, ++ 82, 1, 65, 84, 1, 65, 85, 2, 66, 69, 1, 66, 71, 1, 66, 78, 1, 67, 65, ++ 2, 67, 72, 1, 67, 89, 1, 67, 90, 1, 68, 69, 3, 68, 75, 1, 69, 69, 1, ++ 69, 83, 1, 70, 73, 1, 70, 82, 1, 71, 66, 1, 71, 82, 1, 72, 82, 1, 72, ++ 85, 1, 73, 68, 5, 73, 69, 1, 73, 83, 1, 73, 84, 1, 74, 80, 3, 75, 82, ++ 4, 75, 87, 1, 76, 73, 1, 76, 84, 1, 76, 85, 1, 76, 86, 1, 77, 65, 1, ++ 77, 84, 1, 77, 88, 1, 78, 76, 1, 78, 79, 1, 80, 76, 1, 80, 84, 1, 80, ++ 89, 1, 82, 79, 1, 82, 85, 5, 83, 69, 1, 83, 73, 1, 83, 75, 1, 84, 82, ++ 7, 84, 87, 2, 85, 83, 26, 1, 0, 255, 1, 30, 2, 0, 3, 76, 1, 3, 76, 2, ++ 1, 66, 12, 3, 1, 0, 255, 1, 30, 2, 0, 7, 72, 0, 1, 58, 0, 3, 68, 6, ++ 3, 74, 8, 1, 74, 10, 3, 68, 11, 3, 66, 12, 3, 1, 0, 255, 1, 30, 2, 0, ++ 2, 64, 2, 1, 56, 2, 3, 1, 0, 255, 1, 30, 2, 0, 5, 72, 0, 1, 76, 1, 3, ++ 76, 7, 1, 72, 12, 1, 66, 12, 3, 1, 0, 255, 1, 30, 2, 0, 4, 58, 0, 3, ++ 68, 2, 1, 66, 7, 3, 58, 12, 3, 1, 0, 255, 1, 30, 2, 0, 5, 92, 0, 1, ++ 86, 0, 3, 126, 7, 0, 92, 12, 1, 86, 12, 3, 1, 0, 255, 1, 30, 2, 0, 5, ++ 70, 0, 3, 80, 1, 1, 80, 7, 3, 76, 12, 1, 72, 12, 3, 2, 4, 255, 1, 20, ++ 4, 2, 1, 76, 4, 0, 2, 0, 3, 1, 20, 4, 2, 1, 76, 4, 1, 2, 0, 255, 1, ++ 20, 4, 0, 1, 76, 4, 0, 3, 0, 4, 1, 20, 5, 2, 5, 76, 1, 3, 76, 4, 1, ++ 70, 12, 3, 76, 14, 3, 54, 17, 1, 3, 0, 4, 1, 20, 5, 0, 6, 60, 0, 3, ++ 68, 2, 1, 64, 8, 3, 48, 14, 1, 44, 14, 3, 64, 17, 1, 3, 0, 4, 1, 20, ++ 5, 0, 3, 64, 3, 3, 64, 5, 1, 46, 16, 3, 2, 0, 3, 1, 20, 4, 0, 3, 64, ++ 2, 0, 48, 14, 1, 44, 14, 3, 3, 0, 4, 1, 20, 5, 0, 6, 62, 0, 3, 66, 4, ++ 1, 66, 7, 3, 62, 12, 3, 66, 14, 3, 42, 17, 1, 3, 0, 255, 1, 20, 5, 2, ++ 2, 84, 4, 3, 78, 5, 1, 1, 0, 255, 1, 20, 2, 0, 2, 69, 2, 1, 79, 2, 3, ++ 3, 0, 255, 1, 30, 5, 0, 1, 120, 5, 0, 0, 0, 255, 0, 0, 0, 2, 0, 255, ++ 1, 23, 4, 2, 1, 92, 4, 0, 2, 0, 255, 1, 36, 4, 2, 1, 100, 4, 0, 2, 4, ++ 3, 1, 20, 4, 2, 1, 76, 4, 0, 1, 0, 255, 1, 20, 2, 2, 1, 76, 2, 0, 2, ++ 0, 255, 1, 20, 4, 4, 3, 56, 0, 3, 64, 9, 3, 56, 16, 3, 2, 1, 76, 4, ++ 1, 74, 48, 0, 74, 49, 0, 74, 50, 0, 74, 51, 0, 74, 52, 0, 74, 53, 0, ++ 74, 54, 0, 74, 55, 0, 74, 56, 0, 74, 57, 0, 0, 0, 4, 0, 0, 0, 37, 4, ++ 0, 0, 12, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 4, 0, 1, 2, 3, 8, 12, ++ 13, 14, 15, 16, 17, 18, 19, 8, 4, 5, 6, 7, 8, 9, 10, 11, 1, 1, 1, 10, ++ 1, 11, 1, 12, 1, 13, 1, 14, 2, 2, 2, 10, 2, 11, 2, 12, 3, 9, 10, 10, ++ 11, 11, 12, 12, 12, 13, 12, 14, 13, 13, 14, 14, 34, 46, 36, 48, 36, ++ 64, 36, 116, 36, 140, 36, 144, 36, 161, 36, 165, 36, 177, 52, 60, 52, ++ 64, 52, 124, 52, 140, 52, 144, 52, 165, 56, 64, 64, 64, 64, 100, 100, ++ 100, 100, 116, 100, 140, 100, 144, 100, 165, 104, 128, 104, 140, 104, ++ 165, 132, 140, 132, 144, 132, 165, 149, 149, 149, 161, 149, 165, 149, ++ 177, 153, 161, 165, 165, 0, 1, 2, 1, 4, 1, 5, 1, 18, 2, 18, 19, 4, 18, ++ 19, 29, 48, 2, 18, 20, 2, 18, 22, 1, 19, 3, 19, 28, 49, 3, 19, 30, 49, ++ 3, 19, 31, 50, 2, 19, 32, 2, 19, 49, 1, 20, 2, 20, 38, 2, 20, 40, 2, ++ 20, 44, 2, 20, 48, 2, 20, 49, 2, 21, 46, 1, 22, 2, 22, 49, 2, 23, 49, ++ 1, 24, 1, 25, 1, 26, 3, 28, 38, 49, 2, 28, 49, 3, 33, 38, 49, 2, 33, ++ 49, 1, 38, 1, 48, 1, 49, 69, 48, 0, 88, 65, 0, 88, 85, 0, 65, 85, 2, ++ 74, 80, 1, 0, 0, 3, 0, 0, 0, 124, 10, 0, 0, 16, 4, 5, 6, 7, 8, 9, 10, ++ 11, 12, 13, 14, 15, 16, 17, 18, 19, 34, 46, 4, 36, 64, 4, 100, 144, ++ 4, 149, 177, 4, 50, 48, 50, 48, 45, 48, 49, 45, 51, 48, 32, 50, 49, ++ 58, 51, 48, 58, 48, 53, 0, 4, 2, 64, 19, 0, 64, 49, 0, 1, 2, 40, 14, ++ 0, 40, 39, 0, 4, 4, 56, 19, 0, 58, 28, 0, 60, 39, 0, 70, 49, 0, 1, 3, ++ 52, 15, 0, 64, 30, 0, 72, 39, 0, 4, 3, 60, 20, 0, 60, 38, 0, 60, 49, ++ 0, 1, 3, 56, 14, 0, 60, 25, 0, 60, 39, 0, 6, 1, 84, 20, 0, 3, 1, 84, ++ 15, 0, 4, 1, 60, 20, 0, 1, 1, 56, 15, 0, 6, 1, 84, 20, 0, 3, 1, 88, ++ 15, 0, 6, 2, 84, 20, 0, 84, 49, 0, 3, 2, 84, 15, 0, 84, 39, 0, 0, 0, ++ 4, 2, 66, 20, 0, 66, 48, 0, 1, 2, 54, 15, 0, 54, 39, 0, 6, 2, 92, 20, ++ 0, 80, 49, 0, 3, 2, 88, 15, 0, 76, 39, 0, 4, 2, 66, 20, 0, 64, 49, 0, ++ 1, 2, 56, 15, 0, 56, 39, 0, 4, 1, 56, 19, 0, 1, 1, 48, 14, 0, 4, 1, ++ 60, 19, 0, 1, 1, 56, 14, 0, 4, 1, 60, 19, 0, 1, 1, 56, 14, 0, 6, 2, ++ 84, 23, 0, 112, 49, 0, 3, 2, 88, 19, 0, 116, 39, 0, 4, 5, 56, 19, 0, ++ 70, 27, 0, 58, 34, 0, 68, 38, 0, 70, 49, 0, 1, 7, 52, 13, 0, 66, 22, ++ 0, 68, 23, 0, 52, 26, 0, 62, 27, 0, 72, 33, 0, 74, 39, 0, 4, 4, 58, ++ 19, 0, 80, 47, 0, 80, 51, 0, 80, 52, 0, 1, 4, 58, 13, 0, 66, 22, 0, ++ 72, 38, 0, 80, 41, 0, 4, 6, 56, 19, 0, 68, 27, 0, 56, 34, 0, 68, 36, ++ 0, 68, 42, 0, 68, 49, 0, 1, 6, 48, 14, 0, 68, 23, 0, 48, 26, 0, 62, ++ 27, 0, 74, 33, 0, 72, 39, 0, 4, 5, 56, 19, 0, 78, 27, 0, 64, 34, 0, ++ 68, 36, 0, 78, 43, 0, 1, 10, 62, 13, 0, 62, 22, 0, 78, 23, 0, 50, 26, ++ 0, 56, 27, 0, 78, 32, 0, 78, 35, 0, 78, 37, 0, 60, 38, 0, 78, 41, 0, ++ 4, 1, 120, 26, 0, 1, 1, 120, 21, 0, 4, 1, 120, 25, 0, 1, 1, 120, 20, ++ 0, 4, 4, 56, 19, 0, 70, 27, 0, 58, 34, 0, 70, 49, 0, 1, 4, 48, 14, 0, ++ 62, 23, 0, 48, 26, 0, 60, 39, 0, 4, 4, 56, 19, 0, 66, 27, 0, 60, 34, ++ 0, 66, 49, 0, 1, 3, 56, 14, 0, 60, 24, 0, 60, 39, 0, 6, 2, 84, 20, 0, ++ 84, 49, 0, 3, 2, 88, 15, 0, 88, 39, 0, 4, 4, 56, 19, 0, 70, 27, 0, 58, ++ 34, 0, 70, 49, 0, 1, 4, 48, 14, 0, 62, 23, 0, 48, 26, 0, 60, 39, 0, ++ 4, 2, 60, 28, 0, 68, 49, 0, 1, 2, 56, 24, 0, 56, 39, 0, 6, 2, 112, 28, ++ 0, 112, 49, 0, 3, 2, 112, 24, 0, 112, 39, 0, 0, 2, 64, 18, 0, 64, 20, ++ 0, 4, 4, 48, 18, 0, 48, 19, 0, 60, 29, 0, 60, 48, 0, 1, 2, 48, 17, 0, ++ 48, 39, 0, 4, 2, 56, 19, 0, 68, 49, 0, 1, 2, 48, 14, 0, 60, 39, 0, 4, ++ 6, 62, 19, 0, 90, 27, 0, 80, 35, 0, 90, 41, 0, 86, 45, 0, 118, 50, 0, ++ 1, 6, 74, 14, 0, 98, 23, 0, 66, 26, 0, 74, 27, 0, 98, 34, 0, 118, 40, ++ 0, 6, 1, 84, 24, 0, 3, 1, 88, 20, 0, 6, 1, 84, 24, 0, 3, 1, 88, 20, ++ 0, 4, 2, 56, 19, 0, 60, 49, 0, 1, 2, 48, 14, 0, 60, 39, 0, 6, 2, 72, ++ 20, 0, 72, 44, 0, 3, 2, 76, 15, 0, 76, 35, 0, 4, 2, 60, 20, 0, 60, 38, ++ 0, 1, 2, 56, 15, 0, 64, 29, 0, 4, 2, 60, 20, 0, 60, 38, 0, 1, 1, 56, ++ 18, 0, 4, 2, 84, 20, 0, 84, 38, 0, 1, 1, 56, 18, 0, 6, 1, 84, 22, 0, ++ 3, 1, 88, 18, 0, 6, 1, 84, 22, 0, 3, 1, 88, 18, 0, 6, 2, 84, 20, 0, ++ 112, 38, 0, 3, 2, 68, 15, 0, 96, 29, 0, 4, 2, 66, 20, 0, 66, 38, 0, ++ 1, 2, 42, 15, 0, 64, 29, 0, 4, 2, 62, 20, 0, 66, 38, 0, 1, 2, 42, 15, ++ 0, 64, 29, 0, 4, 2, 60, 20, 0, 60, 38, 0, 1, 2, 56, 15, 0, 64, 29, 0, ++ 0, 0, 4, 4, 60, 20, 0, 60, 37, 0, 60, 44, 0, 60, 49, 0, 1, 4, 56, 15, ++ 0, 60, 28, 0, 60, 35, 0, 60, 39, 0, 6, 2, 84, 21, 0, 84, 46, 0, 3, 2, ++ 88, 16, 0, 88, 36, 0, 4, 2, 60, 20, 0, 60, 49, 0, 1, 2, 56, 15, 0, 60, ++ 39, 0, 0, 2, 60, 20, 0, 60, 49, 0, 6, 1, 84, 25, 0, 3, 1, 84, 20, 0, ++ 6, 1, 84, 25, 0, 3, 1, 88, 20, 0, 6, 2, 84, 20, 0, 112, 40, 0, 3, 2, ++ 88, 15, 0, 116, 31, 0, 4, 3, 60, 20, 0, 60, 38, 0, 60, 49, 0, 1, 3, ++ 56, 15, 0, 64, 29, 0, 60, 39, 0, 4, 1, 60, 49, 0, 1, 1, 52, 39, 0, 6, ++ 1, 80, 49, 0, 3, 1, 80, 39, 0, 6, 1, 80, 49, 0, 3, 1, 80, 39, 0, 6, ++ 2, 80, 19, 0, 80, 49, 0, 3, 2, 80, 14, 0, 80, 39, 0, 6, 1, 76, 49, 0, ++ 3, 1, 76, 39, 0, 6, 1, 76, 48, 0, 3, 1, 68, 39, 0, 4, 1, 60, 49, 0, ++ 1, 1, 60, 39, 0, 6, 1, 84, 49, 0, 3, 1, 88, 39, 0, 4, 1, 78, 49, 0, ++ 1, 1, 78, 39, 0, 4, 3, 56, 33, 0, 68, 38, 0, 68, 49, 0, 1, 4, 48, 26, ++ 0, 62, 27, 0, 74, 33, 0, 72, 39, 0, 4, 3, 56, 28, 0, 58, 38, 0, 62, ++ 49, 0, 1, 4, 46, 23, 0, 48, 26, 0, 56, 29, 0, 56, 39, 0, 4, 2, 68, 33, ++ 0, 68, 49, 0, 1, 2, 66, 26, 0, 60, 39, 0, 2, 1, 84, 48, 0, 65, 69, 1, ++ 65, 82, 1, 65, 84, 1, 65, 85, 2, 66, 69, 1, 66, 71, 1, 66, 78, 1, 67, ++ 65, 2, 67, 72, 1, 67, 89, 1, 67, 90, 1, 68, 69, 3, 68, 75, 1, 69, 69, ++ 1, 69, 83, 1, 70, 73, 1, 70, 82, 1, 71, 66, 1, 71, 82, 1, 72, 82, 1, ++ 72, 85, 1, 73, 68, 5, 73, 69, 1, 73, 83, 1, 73, 84, 1, 74, 80, 3, 75, ++ 82, 4, 75, 87, 1, 76, 73, 1, 76, 84, 1, 76, 85, 1, 76, 86, 1, 77, 65, ++ 1, 77, 84, 1, 77, 88, 1, 78, 76, 1, 78, 79, 1, 80, 76, 1, 80, 84, 1, ++ 80, 89, 1, 82, 79, 1, 82, 85, 5, 83, 69, 1, 83, 73, 1, 83, 75, 1, 84, ++ 87, 2, 85, 83, 25, 4, 5, 76, 0, 2, 76, 6, 2, 76, 10, 2, 76, 11, 2, 66, ++ 12, 2, 1, 4, 62, 0, 0, 66, 4, 0, 62, 9, 0, 58, 10, 0, 4, 3, 58, 0, 2, ++ 66, 7, 2, 58, 12, 2, 1, 5, 42, 0, 0, 50, 3, 0, 60, 8, 0, 54, 9, 0, 46, ++ 10, 0, 4, 1, 56, 2, 2, 1, 1, 32, 1, 0, 4, 5, 58, 0, 2, 68, 6, 2, 74, ++ 10, 2, 68, 11, 2, 66, 12, 2, 1, 5, 48, 0, 0, 58, 3, 0, 66, 8, 0, 58, ++ 9, 0, 54, 10, 0, 4, 3, 86, 0, 2, 126, 7, 2, 86, 12, 2, 1, 3, 78, 0, ++ 0, 126, 5, 0, 78, 10, 0, 4, 5, 70, 0, 2, 80, 6, 2, 80, 10, 2, 80, 11, ++ 2, 72, 12, 2, 1, 5, 58, 0, 0, 68, 3, 0, 80, 8, 0, 68, 9, 0, 60, 10, ++ 0, 4, 1, 64, 4, 2, 1, 1, 64, 2, 0, 4, 1, 76, 4, 2, 1, 1, 72, 2, 0, 0, ++ 1, 64, 4, 2, 4, 4, 60, 0, 2, 64, 8, 2, 44, 13, 2, 44, 16, 2, 1, 3, 40, ++ 0, 0, 52, 5, 0, 46, 11, 0, 0, 2, 64, 3, 2, 46, 16, 2, 4, 2, 64, 2, 2, ++ 44, 14, 2, 1, 3, 54, 0, 0, 64, 6, 0, 52, 12, 0, 6, 1, 76, 4, 2, 3, 1, ++ 76, 2, 0, 6, 1, 76, 4, 2, 3, 1, 76, 2, 0, 6, 1, 76, 4, 2, 3, 1, 76, ++ 2, 0, 6, 1, 76, 4, 2, 3, 1, 128, 2, 0, 4, 1, 64, 4, 2, 1, 1, 64, 2, ++ 0, 6, 1, 84, 4, 2, 3, 1, 72, 2, 0, 0, 1, 79, 2, 2, 4, 2, 120, 4, 2, ++ 120, 17, 2, 1, 1, 120, 2, 0, 0, 0, 0, 1, 64, 4, 2, 4, 1, 80, 4, 2, 1, ++ 1, 64, 2, 0, 4, 1, 88, 4, 2, 1, 1, 60, 2, 0, 6, 1, 100, 4, 2, 3, 1, ++ 88, 2, 0, 4, 1, 64, 2, 2, 1, 1, 52, 1, 0, 4, 3, 56, 0, 2, 64, 9, 2, ++ 56, 16, 2, 1, 2, 46, 0, 0, 52, 7, 0, 68, 69, 0, 0, 3, 0, 0, 0, 251, ++ 3, 0, 0, 74, 80, 0, 0, 10, 0, 0, 0, 228, 2, 0, 0, 85, 83, 0, 0, 2, 0, ++ 0, 0, 104, 0, 0, 0, 8, 12, 13, 14, 15, 16, 17, 18, 19, 8, 4, 5, 6, 7, ++ 8, 9, 10, 11, 1, 14, 1, 0, 0, 0, 112, 11, 0, 0, 4, 3, 0, 0, 48, 3, 0, ++ 0, 229, 27, 0, 0, 154, 3, 0, 0, 160, 10, 0, 0, 82, 1, 0, 0, 67, 24, ++ 0, 0, 0, 9, 0, 0, 69, 4, 0, 0, 156, 11, 0, 0, 12, 4, 0, 0, 204, 27, ++ 0, 0, 127, 178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 110, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 212, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 3, 0, 0, 20, ++ 4, 0, 0, 49, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, ++ 0, 0, 0, 178, 10, 0, 0, 88, 65, 0, 0, 2, 0, 0, 0, 4, 4, 0, 0, 88, 84, ++ 0, 0, 47, 0, 0, 0, 115, 8, 0, 0, 88, 86, 0, 0, 48, 0, 0, 0, 194, 0, ++ 0, 0, 103, 1, 0, 0, 164, 11, 0, 0, 35, 97, 0, 17, 18, 19, 19, 0, 0, ++ 35, 110, 0, 18, 8, 255, 255, 240, 0, 35, 114, 0, 17, 19, 19, 20, 0, ++ 0, 48, 65, 0, 7, 8, 255, 255, 240, 16, 48, 66, 0, 0, 14, 0, 17, 0, 16, ++ 48, 67, 0, 7, 6, 13, 5, 0, 16, 65, 67, 0, 18, 8, 255, 255, 240, 16, ++ 65, 68, 0, 7, 33, 14, 39, 0, 48, 65, 69, 0, 7, 8, 6, 7, 0, 32, 65, 69, ++ 1, 7, 33, 6, 43, 0, 32, 65, 70, 0, 7, 33, 14, 39, 0, 48, 65, 71, 0, ++ 7, 41, 6, 47, 0, 32, 65, 73, 0, 6, 15, 5, 18, 0, 16, 65, 76, 0, 7, 33, ++ 6, 43, 0, 32, 65, 77, 0, 7, 5, 13, 3, 0, 0, 65, 78, 0, 7, 14, 6, 17, ++ 0, 32, 65, 79, 0, 7, 8, 255, 255, 240, 16, 65, 81, 0, 18, 8, 255, 255, ++ 240, 16, 65, 82, 0, 7, 25, 6, 25, 0, 0, 65, 82, 1, 7, 14, 6, 17, 0, ++ 0, 65, 83, 0, 6, 15, 5, 18, 0, 16, 65, 84, 0, 7, 33, 6, 43, 0, 32, 65, ++ 84, 1, 7, 37, 6, 36, 0, 32, 65, 85, 0, 20, 42, 24, 46, 0, 0, 65, 85, ++ 2, 20, 42, 23, 45, 0, 0, 65, 87, 0, 7, 34, 6, 31, 0, 0, 65, 88, 0, 18, ++ 8, 255, 255, 240, 16, 65, 90, 0, 7, 14, 6, 17, 0, 32, 66, 65, 0, 7, ++ 33, 6, 43, 0, 32, 66, 66, 0, 7, 22, 13, 23, 0, 16, 66, 68, 0, 7, 46, ++ 6, 59, 0, 0, 66, 69, 0, 7, 33, 6, 43, 0, 32, 66, 69, 1, 7, 37, 6, 36, ++ 0, 32, 66, 70, 0, 7, 33, 14, 39, 0, 16, 66, 71, 0, 7, 33, 6, 43, 0, ++ 32, 66, 71, 1, 7, 37, 6, 36, 0, 32, 66, 72, 0, 7, 21, 6, 22, 0, 0, 66, ++ 73, 0, 7, 33, 14, 39, 0, 16, 66, 74, 0, 7, 33, 14, 39, 0, 48, 66, 76, ++ 0, 18, 8, 255, 255, 240, 16, 66, 77, 0, 6, 15, 5, 18, 0, 16, 66, 78, ++ 0, 7, 8, 255, 255, 240, 0, 66, 78, 1, 19, 41, 22, 47, 0, 0, 66, 79, ++ 0, 7, 15, 13, 18, 0, 32, 66, 81, 0, 18, 8, 255, 255, 240, 16, 66, 82, ++ 0, 7, 43, 6, 52, 0, 32, 66, 83, 0, 20, 21, 23, 22, 0, 0, 66, 84, 0, ++ 7, 8, 13, 7, 0, 48, 66, 86, 0, 18, 8, 255, 255, 240, 16, 66, 87, 0, ++ 7, 45, 13, 51, 0, 48, 66, 89, 0, 7, 33, 255, 255, 240, 0, 66, 90, 0, ++ 7, 15, 13, 18, 0, 16, 67, 65, 0, 0, 21, 0, 22, 0, 0, 67, 65, 2, 6, 15, ++ 5, 18, 0, 16, 67, 67, 0, 18, 8, 255, 255, 240, 16, 67, 68, 0, 7, 33, ++ 14, 39, 0, 48, 67, 70, 0, 7, 33, 14, 39, 0, 16, 67, 71, 0, 7, 33, 14, ++ 39, 0, 48, 67, 72, 0, 7, 33, 6, 43, 0, 32, 67, 72, 1, 7, 37, 6, 36, ++ 0, 32, 67, 73, 0, 7, 33, 14, 39, 0, 48, 67, 75, 0, 7, 44, 13, 50, 0, ++ 16, 67, 76, 0, 7, 7, 6, 6, 0, 0, 67, 77, 0, 7, 33, 14, 39, 0, 16, 67, ++ 78, 0, 23, 49, 26, 53, 0, 0, 67, 79, 0, 7, 13, 6, 11, 0, 32, 67, 80, ++ 0, 18, 8, 255, 255, 240, 16, 67, 82, 0, 7, 14, 6, 15, 0, 32, 67, 85, ++ 0, 7, 8, 14, 255, 192, 48, 67, 86, 0, 7, 33, 14, 39, 0, 16, 67, 87, ++ 0, 18, 8, 255, 255, 240, 16, 67, 88, 0, 20, 42, 23, 46, 0, 16, 67, 89, ++ 0, 7, 33, 6, 43, 0, 32, 67, 89, 1, 7, 37, 6, 36, 0, 32, 67, 90, 0, 7, ++ 33, 6, 43, 0, 32, 67, 90, 1, 7, 37, 6, 36, 0, 32, 68, 69, 0, 7, 33, ++ 6, 43, 0, 32, 68, 69, 3, 7, 37, 6, 36, 0, 32, 68, 74, 0, 7, 8, 255, ++ 255, 240, 16, 68, 75, 0, 7, 33, 6, 43, 0, 32, 68, 75, 1, 7, 37, 6, 36, ++ 0, 32, 68, 77, 0, 7, 15, 13, 18, 0, 16, 68, 79, 0, 7, 15, 13, 18, 0, ++ 16, 68, 90, 0, 7, 5, 6, 4, 0, 32, 69, 48, 0, 7, 12, 6, 13, 0, 32, 69, ++ 67, 0, 7, 14, 6, 17, 0, 32, 69, 69, 0, 7, 33, 6, 43, 0, 32, 69, 69, ++ 1, 7, 37, 6, 36, 0, 32, 69, 71, 0, 7, 41, 21, 48, 0, 0, 69, 72, 0, 7, ++ 6, 13, 5, 0, 16, 69, 82, 0, 7, 8, 255, 255, 240, 16, 69, 83, 0, 7, 33, ++ 6, 43, 0, 32, 69, 83, 1, 7, 37, 6, 36, 0, 32, 69, 84, 0, 7, 33, 6, 43, ++ 0, 0, 70, 73, 0, 7, 33, 6, 43, 0, 32, 70, 73, 1, 7, 37, 6, 36, 0, 32, ++ 70, 74, 0, 7, 42, 13, 46, 0, 16, 70, 75, 0, 7, 33, 14, 39, 0, 16, 70, ++ 77, 0, 6, 15, 5, 18, 0, 16, 70, 79, 0, 7, 33, 14, 39, 0, 48, 70, 82, ++ 0, 7, 33, 6, 43, 0, 32, 70, 82, 1, 7, 37, 6, 36, 0, 32, 71, 65, 0, 7, ++ 33, 14, 39, 0, 16, 71, 66, 0, 7, 33, 6, 43, 0, 32, 71, 66, 1, 7, 37, ++ 6, 36, 0, 32, 71, 68, 0, 7, 43, 6, 52, 0, 0, 71, 69, 0, 7, 33, 14, 39, ++ 0, 48, 71, 70, 0, 7, 33, 6, 43, 0, 0, 71, 71, 0, 7, 33, 14, 39, 0, 16, ++ 71, 72, 0, 7, 33, 14, 39, 0, 48, 71, 73, 0, 7, 33, 14, 39, 0, 16, 71, ++ 76, 0, 18, 8, 255, 255, 240, 16, 71, 77, 0, 7, 33, 14, 39, 0, 16, 71, ++ 78, 0, 7, 33, 14, 39, 0, 48, 71, 80, 0, 7, 33, 6, 43, 0, 0, 71, 81, ++ 0, 7, 33, 14, 39, 0, 16, 71, 82, 0, 7, 33, 6, 43, 0, 32, 71, 82, 1, ++ 7, 37, 6, 36, 0, 32, 71, 83, 0, 18, 8, 255, 255, 240, 16, 71, 84, 0, ++ 7, 14, 12, 17, 0, 16, 71, 85, 0, 0, 14, 0, 17, 0, 0, 71, 87, 0, 7, 33, ++ 14, 39, 0, 16, 71, 89, 0, 7, 46, 13, 54, 0, 16, 72, 75, 0, 20, 43, 24, ++ 52, 0, 0, 72, 77, 0, 18, 8, 255, 255, 240, 16, 72, 78, 0, 7, 47, 13, ++ 61, 0, 0, 72, 82, 0, 7, 33, 6, 43, 0, 32, 72, 82, 1, 7, 37, 6, 36, 0, ++ 32, 72, 84, 0, 7, 46, 13, 54, 0, 0, 72, 85, 0, 7, 33, 6, 43, 0, 32, ++ 72, 85, 1, 7, 37, 6, 36, 0, 32, 73, 68, 0, 7, 8, 6, 7, 0, 0, 73, 68, ++ 5, 7, 55, 14, 65, 0, 16, 73, 69, 0, 7, 33, 6, 43, 0, 32, 73, 69, 1, ++ 7, 37, 6, 36, 0, 32, 73, 76, 0, 7, 5, 6, 4, 0, 32, 73, 77, 0, 7, 33, ++ 14, 39, 0, 16, 73, 78, 0, 19, 41, 22, 47, 0, 32, 73, 79, 0, 7, 33, 14, ++ 39, 0, 16, 73, 81, 0, 7, 33, 14, 39, 0, 16, 73, 82, 0, 7, 8, 14, 255, ++ 192, 48, 73, 83, 0, 7, 33, 6, 43, 0, 32, 73, 83, 1, 7, 37, 6, 36, 0, ++ 32, 73, 84, 0, 7, 33, 6, 43, 0, 32, 73, 84, 1, 7, 37, 6, 36, 0, 32, ++ 74, 48, 0, 7, 38, 16, 42, 0, 0, 74, 49, 0, 15, 12, 255, 255, 240, 0, ++ 74, 50, 0, 15, 5, 255, 255, 240, 0, 74, 51, 0, 15, 38, 255, 255, 240, ++ 0, 74, 52, 0, 15, 24, 255, 255, 240, 0, 74, 53, 0, 15, 27, 255, 255, ++ 240, 0, 74, 54, 0, 15, 28, 255, 255, 240, 0, 74, 55, 0, 15, 29, 255, ++ 255, 240, 0, 74, 56, 0, 15, 40, 255, 255, 240, 0, 74, 57, 0, 7, 28, ++ 16, 27, 0, 0, 74, 69, 0, 7, 33, 14, 39, 0, 16, 74, 77, 0, 7, 46, 14, ++ 60, 0, 16, 74, 79, 0, 7, 1, 6, 0, 0, 32, 74, 80, 0, 15, 39, 17, 40, ++ 0, 0, 74, 80, 1, 15, 28, 16, 27, 0, 0, 74, 80, 3, 15, 39, 16, 41, 0, ++ 0, 74, 80, 88, 16, 8, 18, 7, 0, 0, 75, 65, 0, 22, 17, 25, 16, 0, 0, ++ 75, 67, 0, 22, 46, 25, 54, 0, 0, 75, 68, 0, 7, 51, 6, 58, 0, 0, 75, ++ 69, 0, 7, 33, 6, 38, 0, 32, 75, 71, 0, 7, 33, 14, 39, 0, 16, 75, 72, ++ 0, 7, 43, 6, 52, 0, 0, 75, 73, 0, 20, 42, 23, 46, 0, 16, 75, 75, 0, ++ 22, 8, 25, 7, 0, 0, 75, 77, 0, 7, 33, 14, 39, 0, 16, 75, 78, 0, 7, 15, ++ 13, 18, 0, 16, 75, 80, 0, 18, 8, 255, 255, 240, 16, 75, 82, 0, 18, 55, ++ 20, 44, 0, 0, 75, 82, 4, 23, 30, 26, 28, 0, 16, 75, 87, 0, 7, 8, 6, ++ 7, 0, 32, 75, 87, 1, 7, 5, 6, 4, 0, 32, 75, 88, 0, 7, 48, 6, 56, 0, ++ 0, 75, 89, 0, 8, 8, 8, 7, 0, 0, 75, 90, 0, 7, 36, 13, 34, 0, 0, 76, ++ 65, 0, 7, 34, 6, 31, 0, 0, 76, 66, 0, 7, 46, 6, 59, 0, 32, 76, 67, 0, ++ 7, 15, 13, 18, 0, 16, 76, 73, 0, 7, 33, 6, 43, 0, 0, 76, 73, 1, 7, 37, ++ 6, 36, 0, 0, 76, 75, 0, 19, 43, 22, 52, 0, 0, 76, 82, 0, 7, 43, 21, ++ 50, 0, 16, 76, 83, 0, 7, 33, 6, 43, 0, 0, 76, 84, 0, 7, 33, 6, 43, 0, ++ 32, 76, 84, 1, 7, 37, 6, 36, 0, 32, 76, 85, 0, 7, 33, 6, 43, 0, 32, ++ 76, 85, 1, 7, 37, 6, 36, 0, 32, 76, 86, 0, 7, 33, 6, 43, 0, 32, 76, ++ 86, 1, 7, 37, 6, 36, 0, 32, 76, 89, 0, 7, 8, 15, 255, 192, 16, 77, 65, ++ 0, 7, 12, 21, 12, 0, 32, 77, 65, 1, 7, 5, 21, 4, 0, 32, 77, 67, 0, 7, ++ 33, 6, 43, 0, 0, 77, 68, 0, 7, 33, 6, 43, 0, 32, 77, 69, 0, 7, 33, 6, ++ 43, 0, 32, 77, 70, 0, 7, 45, 13, 51, 0, 16, 77, 71, 0, 7, 33, 14, 39, ++ 0, 48, 77, 72, 0, 18, 8, 255, 255, 240, 16, 77, 75, 0, 7, 33, 6, 43, ++ 0, 32, 77, 76, 0, 7, 33, 14, 39, 0, 16, 77, 77, 0, 7, 33, 14, 39, 0, ++ 16, 77, 78, 0, 7, 14, 12, 17, 0, 32, 77, 79, 0, 7, 50, 6, 59, 0, 0, ++ 77, 80, 0, 6, 15, 5, 18, 0, 16, 77, 81, 0, 7, 33, 6, 43, 0, 0, 77, 82, ++ 0, 7, 33, 6, 43, 0, 0, 77, 83, 0, 7, 33, 14, 39, 0, 48, 77, 84, 0, 7, ++ 33, 6, 43, 0, 32, 77, 84, 1, 7, 37, 6, 36, 0, 32, 77, 85, 0, 7, 33, ++ 6, 43, 0, 32, 77, 86, 0, 7, 10, 6, 10, 0, 32, 77, 87, 0, 7, 46, 6, 59, ++ 0, 32, 77, 88, 0, 7, 5, 6, 4, 0, 0, 77, 88, 1, 7, 21, 6, 22, 0, 0, 77, ++ 89, 0, 19, 41, 22, 47, 0, 0, 77, 90, 0, 7, 16, 13, 14, 0, 16, 78, 65, ++ 0, 7, 16, 13, 14, 0, 16, 78, 67, 0, 7, 33, 14, 39, 0, 16, 78, 69, 0, ++ 7, 33, 14, 39, 0, 16, 78, 70, 0, 7, 42, 12, 45, 0, 0, 78, 71, 0, 7, ++ 26, 14, 26, 0, 48, 78, 73, 0, 7, 14, 6, 17, 0, 32, 78, 76, 0, 7, 33, ++ 6, 43, 0, 32, 78, 76, 1, 7, 37, 6, 36, 0, 32, 78, 79, 0, 7, 33, 6, 43, ++ 0, 32, 78, 79, 1, 7, 37, 6, 36, 0, 32, 78, 80, 0, 19, 9, 22, 8, 0, 0, ++ 78, 82, 0, 7, 33, 14, 39, 0, 16, 78, 85, 0, 7, 14, 255, 255, 240, 16, ++ 78, 90, 0, 7, 43, 6, 52, 0, 32, 79, 77, 0, 7, 33, 6, 43, 0, 32, 80, ++ 65, 0, 19, 0, 22, 24, 0, 32, 80, 69, 0, 7, 14, 6, 17, 0, 32, 80, 70, ++ 0, 7, 33, 14, 39, 0, 16, 80, 71, 0, 7, 2, 6, 0, 0, 0, 80, 72, 0, 7, ++ 43, 6, 52, 0, 32, 80, 75, 0, 7, 50, 12, 55, 0, 32, 80, 76, 0, 7, 33, ++ 6, 43, 0, 32, 80, 76, 1, 7, 37, 6, 36, 0, 32, 80, 77, 0, 7, 33, 14, ++ 39, 0, 16, 80, 78, 0, 18, 8, 255, 255, 240, 16, 80, 82, 0, 0, 14, 0, ++ 17, 0, 0, 80, 83, 0, 18, 8, 255, 255, 240, 0, 80, 84, 0, 7, 33, 6, 43, ++ 0, 32, 80, 84, 1, 7, 37, 6, 36, 0, 32, 80, 87, 0, 7, 15, 13, 18, 0, ++ 16, 80, 89, 0, 7, 46, 6, 59, 0, 0, 80, 89, 1, 7, 43, 6, 52, 0, 0, 81, ++ 49, 0, 2, 8, 2, 7, 0, 0, 81, 50, 0, 0, 31, 0, 29, 0, 0, 81, 65, 0, 7, ++ 50, 14, 57, 0, 48, 82, 69, 0, 7, 33, 6, 43, 0, 0, 82, 79, 0, 7, 33, ++ 6, 43, 0, 32, 82, 79, 1, 7, 37, 6, 36, 0, 32, 82, 83, 0, 7, 33, 6, 43, ++ 0, 32, 82, 85, 0, 7, 8, 255, 255, 240, 0, 82, 85, 5, 7, 11, 12, 9, 0, ++ 0, 82, 87, 0, 7, 33, 14, 39, 0, 48, 83, 65, 0, 7, 34, 6, 32, 0, 32, ++ 83, 66, 0, 7, 8, 255, 255, 240, 16, 83, 67, 0, 7, 45, 13, 51, 0, 16, ++ 83, 68, 0, 7, 8, 14, 255, 192, 48, 83, 69, 0, 7, 33, 6, 43, 0, 32, 83, ++ 69, 1, 7, 37, 6, 36, 0, 32, 83, 71, 0, 19, 44, 22, 50, 0, 32, 83, 72, ++ 0, 18, 8, 255, 255, 240, 16, 83, 73, 0, 7, 33, 6, 43, 0, 32, 83, 73, ++ 1, 7, 37, 6, 36, 0, 32, 83, 74, 0, 18, 8, 255, 255, 240, 16, 83, 75, ++ 0, 7, 33, 6, 43, 0, 32, 83, 75, 1, 7, 37, 6, 36, 0, 32, 83, 76, 0, 7, ++ 33, 14, 39, 0, 16, 83, 77, 0, 7, 33, 14, 39, 0, 16, 83, 78, 0, 7, 33, ++ 6, 43, 0, 32, 83, 79, 0, 7, 8, 255, 255, 240, 16, 83, 82, 0, 7, 33, ++ 14, 39, 0, 16, 83, 84, 0, 7, 33, 14, 39, 0, 16, 83, 86, 0, 7, 14, 12, ++ 17, 0, 32, 83, 88, 0, 18, 8, 255, 255, 240, 16, 83, 89, 0, 18, 8, 255, ++ 255, 240, 16, 83, 90, 0, 7, 33, 14, 39, 0, 16, 84, 65, 0, 18, 8, 255, ++ 255, 240, 16, 84, 67, 0, 7, 33, 14, 39, 0, 16, 84, 68, 0, 7, 33, 14, ++ 39, 0, 16, 84, 70, 0, 7, 33, 14, 39, 0, 16, 84, 71, 0, 7, 33, 14, 39, ++ 0, 16, 84, 72, 0, 7, 43, 6, 52, 0, 32, 84, 74, 0, 7, 33, 14, 39, 0, ++ 16, 84, 75, 0, 18, 8, 255, 255, 240, 16, 84, 76, 0, 7, 33, 14, 39, 0, ++ 48, 84, 77, 0, 7, 33, 14, 39, 0, 16, 84, 78, 0, 7, 5, 6, 4, 0, 32, 84, ++ 79, 0, 7, 8, 255, 255, 240, 16, 84, 82, 0, 7, 5, 6, 4, 0, 32, 84, 82, ++ 7, 7, 33, 14, 39, 0, 48, 84, 84, 0, 7, 43, 6, 52, 0, 32, 84, 86, 0, ++ 7, 8, 255, 255, 240, 16, 84, 87, 0, 0, 52, 0, 64, 0, 0, 84, 87, 2, 0, ++ 53, 0, 62, 0, 0, 84, 90, 0, 7, 33, 14, 39, 0, 16, 85, 65, 0, 7, 8, 255, ++ 255, 240, 0, 85, 71, 0, 7, 34, 6, 31, 0, 32, 85, 77, 0, 0, 14, 0, 17, ++ 0, 0, 85, 83, 0, 5, 32, 4, 30, 0, 0, 85, 83, 25, 12, 8, 10, 7, 0, 0, ++ 85, 83, 26, 4, 8, 1, 7, 0, 0, 85, 89, 0, 20, 43, 23, 52, 0, 0, 85, 90, ++ 0, 7, 33, 14, 39, 0, 16, 86, 65, 0, 7, 33, 6, 43, 0, 0, 86, 67, 0, 7, ++ 15, 13, 18, 0, 16, 86, 69, 0, 7, 41, 6, 47, 0, 0, 86, 71, 0, 7, 33, ++ 6, 43, 0, 0, 86, 73, 0, 0, 14, 0, 17, 0, 0, 86, 78, 0, 7, 5, 6, 4, 0, ++ 0, 86, 85, 0, 7, 43, 13, 49, 0, 16, 87, 70, 0, 7, 33, 13, 43, 0, 16, ++ 87, 83, 0, 7, 43, 12, 49, 0, 16, 88, 48, 0, 3, 20, 0, 21, 0, 0, 88, ++ 49, 0, 7, 41, 6, 47, 0, 0, 88, 50, 0, 21, 3, 6, 2, 0, 0, 88, 51, 0, ++ 7, 33, 6, 35, 0, 32, 88, 65, 0, 7, 3, 255, 255, 240, 0, 88, 66, 0, 0, ++ 23, 255, 255, 240, 0, 88, 82, 0, 1, 54, 3, 63, 0, 0, 88, 83, 0, 13, ++ 4, 11, 1, 0, 32, 88, 84, 0, 12, 8, 10, 7, 0, 32, 88, 85, 0, 9, 37, 7, ++ 37, 0, 32, 88, 86, 0, 11, 8, 9, 7, 0, 32, 88, 87, 0, 22, 35, 25, 33, ++ 0, 32, 88, 88, 0, 10, 33, 255, 255, 240, 32, 88, 89, 0, 7, 33, 6, 43, ++ 0, 32, 88, 90, 0, 14, 8, 255, 255, 240, 32, 89, 49, 0, 0, 14, 255, 255, ++ 240, 16, 89, 50, 0, 0, 14, 255, 255, 240, 16, 89, 51, 0, 0, 14, 255, ++ 255, 240, 16, 89, 52, 0, 0, 14, 255, 255, 240, 16, 89, 53, 0, 0, 14, ++ 255, 255, 240, 16, 89, 54, 0, 0, 14, 255, 255, 240, 16, 89, 55, 0, 0, ++ 14, 255, 255, 240, 16, 89, 69, 0, 7, 45, 13, 51, 0, 16, 89, 84, 0, 7, ++ 33, 6, 43, 0, 0, 89, 89, 0, 18, 8, 255, 255, 240, 0, 90, 49, 0, 18, ++ 8, 255, 255, 240, 16, 90, 50, 0, 18, 8, 255, 255, 240, 16, 90, 51, 0, ++ 18, 8, 255, 255, 240, 16, 90, 52, 0, 18, 8, 255, 255, 240, 16, 90, 53, ++ 0, 18, 8, 255, 255, 240, 16, 90, 54, 0, 18, 8, 255, 255, 240, 16, 90, ++ 55, 0, 18, 8, 255, 255, 240, 16, 90, 56, 0, 18, 8, 255, 255, 240, 16, ++ 90, 57, 0, 18, 8, 255, 255, 240, 16, 90, 65, 0, 7, 33, 6, 43, 0, 32, ++ 90, 77, 0, 19, 41, 22, 47, 0, 0, 90, 87, 0, 7, 33, 14, 39, 0, 48, 10, ++ 2, 255, 3, 17, 19, 24, 28, 30, 49, 0, 4, 56, 19, 1, 70, 27, 1, 58, 34, ++ 1, 70, 49, 1, 14, 0, 255, 2, 23, 19, 23, 49, 2, 2, 84, 19, 1, 84, 49, ++ 1, 14, 0, 255, 2, 23, 19, 23, 49, 0, 2, 66, 19, 1, 66, 49, 1, 23, 1, ++ 1, 4, 23, 19, 17, 28, 23, 38, 30, 49, 2, 2, 84, 22, 1, 84, 49, 1, 24, ++ 1, 5, 2, 23, 23, 30, 49, 0, 4, 56, 19, 1, 58, 28, 1, 60, 39, 1, 70, ++ 49, 1, 15, 1, 255, 1, 23, 20, 2, 1, 84, 20, 1, 15, 1, 255, 1, 23, 20, ++ 2, 1, 84, 20, 1, 20, 1, 255, 2, 21, 20, 21, 49, 2, 2, 84, 20, 1, 84, ++ 49, 1, 0, 0, 255, 0, 0, 0, 19, 1, 255, 2, 23, 20, 23, 48, 0, 2, 66, ++ 20, 1, 66, 48, 1, 20, 1, 255, 2, 23, 20, 20, 49, 0, 2, 66, 20, 1, 64, ++ 49, 1, 20, 1, 255, 2, 23, 20, 20, 49, 2, 2, 92, 20, 1, 80, 49, 1, 9, ++ 0, 255, 1, 23, 19, 2, 1, 84, 19, 1, 9, 0, 255, 1, 20, 19, 0, 1, 56, ++ 19, 1, 11, 2, 255, 3, 17, 19, 24, 30, 30, 49, 0, 5, 56, 19, 1, 70, 27, ++ 1, 58, 34, 1, 68, 38, 1, 70, 49, 1, 13, 2, 255, 3, 17, 19, 24, 31, 30, ++ 49, 0, 5, 56, 19, 1, 78, 27, 1, 64, 34, 1, 68, 36, 1, 78, 43, 1, 26, ++ 1, 255, 2, 23, 20, 30, 40, 2, 2, 84, 23, 1, 112, 49, 1, 14, 2, 255, ++ 2, 17, 19, 30, 49, 0, 2, 58, 19, 1, 80, 49, 1, 27, 0, 255, 1, 30, 26, ++ 0, 1, 120, 26, 1, 26, 2, 255, 1, 30, 25, 0, 1, 120, 25, 1, 10, 2, 2, ++ 3, 17, 19, 24, 28, 30, 49, 0, 4, 56, 19, 1, 70, 27, 1, 58, 34, 1, 70, ++ 49, 1, 10, 2, 255, 3, 17, 19, 24, 28, 30, 49, 0, 4, 56, 19, 1, 66, 27, ++ 1, 60, 34, 1, 66, 49, 1, 20, 2, 255, 2, 23, 20, 33, 49, 2, 2, 84, 20, ++ 1, 84, 49, 1, 10, 2, 1, 3, 17, 19, 24, 28, 30, 49, 0, 4, 56, 19, 1, ++ 70, 27, 1, 58, 34, 1, 70, 49, 1, 32, 2, 255, 1, 30, 38, 2, 1, 84, 38, ++ 1, 29, 2, 255, 2, 21, 28, 30, 49, 0, 2, 60, 28, 1, 68, 49, 1, 29, 1, ++ 255, 2, 30, 28, 30, 49, 2, 2, 112, 28, 1, 112, 49, 1, 5, 2, 0, 2, 23, ++ 18, 23, 19, 2, 2, 84, 18, 1, 84, 19, 1, 7, 2, 0, 2, 23, 18, 23, 20, ++ 2, 2, 84, 18, 1, 84, 20, 1, 8, 2, 0, 3, 23, 18, 23, 20, 30, 38, 2, 2, ++ 84, 18, 1, 84, 22, 1, 6, 1, 255, 4, 14, 18, 14, 19, 20, 29, 20, 48, ++ 0, 4, 48, 18, 1, 48, 19, 1, 60, 29, 1, 60, 48, 1, 14, 0, 255, 2, 17, ++ 19, 30, 49, 0, 2, 56, 19, 1, 68, 49, 1, 12, 2, 255, 3, 17, 19, 24, 31, ++ 30, 50, 0, 6, 62, 19, 1, 90, 27, 1, 80, 35, 1, 90, 41, 1, 86, 45, 1, ++ 118, 50, 1, 22, 1, 255, 2, 23, 20, 30, 38, 2, 1, 84, 22, 1, 25, 1, 255, ++ 1, 23, 24, 2, 1, 84, 24, 1, 14, 0, 6, 2, 17, 19, 20, 49, 0, 2, 56, 19, ++ 1, 60, 49, 1, 18, 1, 255, 2, 20, 20, 20, 44, 2, 2, 72, 20, 1, 72, 44, ++ 1, 22, 1, 255, 2, 23, 20, 30, 38, 2, 1, 84, 22, 1, 22, 2, 255, 1, 20, ++ 22, 0, 2, 62, 20, 1, 66, 38, 1, 16, 2, 255, 2, 20, 20, 28, 38, 2, 2, ++ 84, 20, 1, 112, 38, 1, 4, 0, 255, 1, 23, 18, 2, 1, 84, 18, 1, 20, 1, ++ 255, 2, 23, 20, 30, 49, 2, 2, 84, 20, 1, 84, 49, 1, 21, 1, 255, 3, 23, ++ 20, 30, 37, 30, 46, 2, 2, 84, 21, 1, 84, 46, 1, 26, 1, 255, 3, 23, 20, ++ 24, 39, 30, 49, 2, 1, 84, 25, 1, 26, 1, 255, 3, 23, 20, 24, 39, 30, ++ 49, 2, 1, 84, 25, 1, 17, 1, 255, 2, 23, 20, 30, 40, 2, 2, 84, 20, 1, ++ 112, 40, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 30, ++ 49, 0, 1, 78, 49, 1, 14, 0, 255, 2, 27, 19, 27, 49, 2, 2, 84, 19, 1, ++ 84, 49, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 20, ++ 49, 2, 1, 76, 49, 1, 33, 0, 255, 1, 20, 48, 2, 1, 76, 48, 1, 31, 2, ++ 255, 2, 17, 33, 30, 49, 0, 2, 68, 33, 1, 68, 49, 1, 30, 2, 255, 3, 17, ++ 33, 24, 38, 30, 49, 0, 3, 56, 33, 1, 68, 38, 1, 68, 49, 1, 28, 2, 255, ++ 3, 17, 28, 24, 38, 30, 49, 0, 3, 56, 28, 1, 58, 38, 1, 62, 49, 1, 33, ++ 0, 255, 1, 27, 48, 2, 1, 84, 48, 1, 0, 0, 3, 0, 0, 0, 120, 11, 0, 0, ++ 16, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1, 18, ++ 1, 255, 1, 52, 1, 14, 1, 15, 3, 28, 39, 49, 2, 19, 49, 166, 169, 0, ++ 0 ++}; ++const resource_hnd_t wifi_firmware_clm_blob = { RESOURCE_IN_MEMORY, 7222, {.mem = { (const char *) wifi_firmware_clm_blob_image_data }}}; ++ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h +new file mode 100644 +index 0000000000..01bad9226f +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h +@@ -0,0 +1,30 @@ ++/* ++ * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved ++ * SPDX-License-Identifier: LicenseRef-PBL ++ * ++ * This file and the related binary are licensed under the ++ * Permissive Binary License, Version 1.0 (the "License"); ++ * you may not use these files except in compliance with the License. ++ * ++ * You may obtain a copy of the License here: ++ * LICENSE-permissive-binary-license-1.0.txt and at ++ * https://www.mbed.com/licenses/PBL-1.0 ++ * ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++/* Automatically generated file - this comment ensures resources.h file creation */ ++/* Auto-generated header file. Do not edit */ ++#ifndef INCLUDED_RESOURCES_H_ ++#define INCLUDED_RESOURCES_H_ ++#include "wiced_resource.h" ++#include "wiced_filesystem.h" ++ ++extern wiced_filesystem_t resource_fs_handle; ++ ++extern const resource_hnd_t wifi_firmware_image; ++extern const unsigned char wifi_firmware_image_data[421098]; ++extern const resource_hnd_t wifi_firmware_clm_blob; ++extern const unsigned char wifi_firmware_clm_blob_image_data[7222]; ++ ++#endif /* ifndef INCLUDED_RESOURCES_H_ */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h +new file mode 100644 +index 0000000000..3f2279c2be +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h +@@ -0,0 +1,87 @@ ++/* ++ * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved ++ * SPDX-License-Identifier: LicenseRef-PBL ++ * ++ * This file and the related binary are licensed under the ++ * Permissive Binary License, Version 1.0 (the "License"); ++ * you may not use these files except in compliance with the License. ++ * ++ * You may obtain a copy of the License here: ++ * LICENSE-permissive-binary-license-1.0.txt and at ++ * https://www.mbed.com/licenses/PBL-1.0 ++ * ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * NVRAM file for CY8CKIT-062-WiFi-BT (PSoC6 WiFi-BT Pioneer Kit) using ++ * Murata's Type 1DX module - Copied from bcm94343wwcd1.txt on 08/04/2019 ++ * # 2.4 GHz, 20 MHz BW mode; No Antenna Diversity ++ */ ++ ++#ifndef INCLUDED_NVRAM_IMAGE_H_ ++#define INCLUDED_NVRAM_IMAGE_H_ ++ ++#include ++#include ++#include "generated_mac_address.txt" ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** ++ * Character array of NVRAM image ++ * ++ * Generated from cyw94343cy8ckit-062-wifi-bt.txt ++ */ ++ ++static const char wifi_nvram_image[] = ++ "manfid=0x2d0" "\x00" ++ "prodid=0x0726" "\x00" ++ "vendid=0x14e4" "\x00" ++ "devid=0x43e2" "\x00" ++ "boardtype=0x0726" "\x00" ++ "boardrev=0x1202" "\x00" ++ "boardnum=22" "\x00" ++ NVRAM_GENERATED_MAC_ADDRESS "\x00" ++ "sromrev=11" "\x00" ++ "boardflags=0x00404201" "\x00" ++ "boardflags3=0x04000000" "\x00" ++ "xtalfreq=37400" "\x00" ++ "nocrc=1" "\x00" ++ "ag0=0" "\x00" ++ "aa2g=1" "\x00" ++ "ccode=ALL" "\x00" ++ "extpagain2g=0" "\x00" ++ "pa2ga0=-145,6667,-751" "\x00" ++ "AvVmid_c0=0x0,0xc8" "\x00" ++ "cckpwroffset0=2" "\x00" ++ "maxp2ga0=74" "\x00" ++ "cckbw202gpo=0" "\x00" ++ "legofdmbw202gpo=0x88888888" "\x00" ++ "mcsbw202gpo=0xaaaaaaaa" "\x00" ++ "propbw202gpo=0xdd" "\x00" ++ "ofdmdigfilttype=18" "\x00" ++ "ofdmdigfilttypebe=18" "\x00" ++ "papdmode=1" "\x00" ++ "papdvalidtest=1" "\x00" ++ "pacalidx2g=48" "\x00" ++ "papdepsoffset=-22" "\x00" ++ "papdendidx=58" "\x00" ++ "il0"NVRAM_GENERATED_MAC_ADDRESS "\x00" ++ "wl0id=0x431b" "\x00" ++ "muxenab=0x10" "\x00" ++ "\x00\x00"; ++ ++#ifdef __cplusplus ++} /* extern "C" */ ++#endif ++ ++#else /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ ++ ++#error Wi-Fi NVRAM image included twice ++ ++#endif /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/whd_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/whd_config.h +new file mode 100644 +index 0000000000..4b320b9dee +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/whd_config.h +@@ -0,0 +1,61 @@ ++/* ++ * Copyright 2020 Arduino SA ++ * SPDX-License-Identifier: Apache-2.0 ++ * ++ * Licensed under the Apache License, Version 2.0 (the "License"); ++ * you may not use this file except in compliance with the License. ++ * You may obtain a copy of the License at ++ * ++ * http://www.apache.org/licenses/LICENSE-2.0 ++ * ++ * Unless required by applicable law or agreed to in writing, software ++ * distributed under the License is distributed on an "AS IS" BASIS, ++ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++ * See the License for the specific language governing permissions and ++ * limitations under the License. ++ */ ++ ++/** @file ++ * Provides configuration for WHD driver on Arduino Portenta H7 ++ */ ++ ++#ifndef __WHD_CONFIG__ ++#define __WHD_CONFIG__ ++ ++#include "whd_types.h" ++#include "stm32h7xx_hal.h" ++#include ++ ++/* disable WPRINT_MACRO */ ++#define WHD_PRINT_DISABLE ++ ++/* please define your configuration , either SDIO or SPI */ ++#define CY_WHD_CONFIG_USE_SDIO ++//#define CY_WHD_CONFIG_USE_SPI ++ ++/* select resource implementation */ ++#define USES_RESOURCE_GENERIC_FILESYSTEM ++ ++/* if not defined default value is 2 */ ++#define CY_WIFI_OOB_INTR_PRIORITY 0 ++ ++#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_FALL ++#define CYBSP_WIFI_HOST_WAKE CYBSP_SDIO_OOB_IRQ ++ ++#define BSP_LED1 {GPIOK,{.Pin= GPIO_PIN_5 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} ++#define BSP_LED2 {GPIOK,{.Pin= GPIO_PIN_6 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} ++#define BSP_LED3 {GPIOK,{.Pin= GPIO_PIN_7 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} ++ ++/* power pin */ ++#define WIFI_WL_REG_ON {GPIOB,{.Pin= GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} ++//#define WIFI_32K_CLK {GPIOA,{.Pin= GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW , .Alternate = GPIO_AF0_MCO}} ++ ++#define WIFI_SDIO_CMD {GPIOD,{.Pin= GPIO_PIN_2 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} ++#define WIFI_SDIO_CLK {GPIOC,{.Pin= GPIO_PIN_12 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} ++#define WIFI_SDIO_D0 {GPIOC,{.Pin= GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} ++#define WIFI_SDIO_D1 {GPIOC,{.Pin= GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} ++#define WIFI_SDIO_D2 {GPIOC,{.Pin= GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} ++#define WIFI_SDIO_D3 {GPIOC,{.Pin= GPIO_PIN_11 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} ++#define WIFI_SDIO_OOB_IRQ {GPIOI,{.Pin= GPIO_PIN_8 , .Mode = GPIO_MODE_IT_FALLING , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH}} ++ ++#endif +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PeripheralPins.c +new file mode 100644 +index 0000000000..34b73f5f20 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PeripheralPins.c +@@ -0,0 +1,578 @@ ++/* mbed Microcontroller Library ++ * SPDX-License-Identifier: BSD-3-Clause ++ ****************************************************************************** ++ * ++ * Copyright (c) 2016-2020 STMicroelectronics. ++ * All rights reserved. ++ * ++ * This software component is licensed by ST under BSD 3-Clause license, ++ * the "License"; You may not use this file except in compliance with the ++ * License. You may obtain a copy of the License at: ++ * opensource.org/licenses/BSD-3-Clause ++ * ++ ****************************************************************************** ++ * ++ * Automatically generated from STM32CubeMX/db/mcu/STM32H747XIHx.xml ++ */ ++ ++#include "PeripheralPins.h" ++#include "mbed_toolchain.h" ++ ++//============================================================================== ++// Notes ++// ++// - The pins mentioned Px_y_ALTz are alternative possibilities which use other ++// HW peripheral instances. You can use them the same way as any other "normal" ++// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board ++// pinout image on mbed.org. ++// ++// - The pins which are connected to other components present on the board have ++// the comment "Connected to xxx". The pin function may not work properly in this ++// case. These pins may not be displayed on the board pinout image on mbed.org. ++// Please read the board reference manual and schematic for more information. ++// ++// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented ++// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. ++// ++//============================================================================== ++ ++ ++//*** ADC *** ++ ++MBED_WEAK const PinMap PinMap_ADC[] = { ++ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 ++ {PA_0C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 ++ {PA_0C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 ++ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 ++ {PA_1C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 ++ {PA_1C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 ++ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 ++ {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 ++ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 ++ {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 ++ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 ++ {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 ++ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 ++ {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 ++ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 ++ {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 ++ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 ++ {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 ++ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 ++ {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 ++ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 ++ {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 ++ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 ++ {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 ++ {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 ++ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 ++ {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 ++ {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 ++ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 ++ {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 ++ {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12 ++ {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 ++ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 ++ {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 ++ {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 ++ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 ++ {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 ++ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 ++ {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 ++ {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 ++ {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 ++ {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 ++ {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 ++ {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 ++ {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 ++ {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 ++ {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 ++ {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 ++ {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 ++ {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 ++ {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 ++ {PH_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 ++ {PH_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 ++ {PH_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 ++ {PH_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_ADC_Internal[] = { ++ {ADC_TEMP, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC3_INP18 ++ {ADC_VREF, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC3_INP19 ++ {ADC_VBAT, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC3_INP17 ++ {NC, NC, 0} ++}; ++ ++//*** DAC *** ++ ++MBED_WEAK const PinMap PinMap_DAC[] = { ++ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 ++ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 ++ {NC, NC, 0} ++}; ++ ++//*** I2C *** ++ ++MBED_WEAK const PinMap PinMap_I2C_SDA[] = { ++ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, ++ {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, ++ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, ++ {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, ++ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, ++ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, ++ {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, ++ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, ++ {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, ++ {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, ++ {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, ++ {PH_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_I2C_SCL[] = { ++ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, ++ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, ++ {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, ++ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, ++ {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, ++ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, ++ {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, ++ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, ++ {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, ++ {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, ++ {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, ++ {PH_11, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, ++ {NC, NC, 0} ++}; ++ ++//*** PWM *** ++ ++// TIM5 cannot be used because already used by the us_ticker ++// TIM2 cannot be used because already used by the us_ticker (DUAL_CORE) ++MBED_WEAK const PinMap PinMap_PWM[] = { ++// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 ++// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 ++// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 ++// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 ++ {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N ++// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 ++// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 ++ {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 ++// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 ++// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 ++ {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 ++// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 ++ {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N ++ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 ++ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 ++ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N ++ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 ++ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N ++ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 ++// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 ++// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 ++// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 ++ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 ++// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 ++ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N ++ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 ++ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N ++ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N ++ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 ++ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N ++// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 ++ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 ++ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 ++ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 ++ {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N ++ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 ++ {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N ++ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 ++ {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 ++ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 ++ {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 ++// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 ++// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 ++ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N ++ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N ++ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N ++ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 ++ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N ++ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N ++ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 ++ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 ++ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 ++ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 ++ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 ++ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 ++ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 ++ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 ++ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 ++ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 ++ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 ++ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 ++ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 ++ {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N ++ {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 ++ {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 ++ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N ++ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 ++ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N ++ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 ++ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N ++ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 ++ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 ++ {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 ++ {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 ++ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 ++ {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N ++ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 ++ {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N ++ {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 ++ {PH_9, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 ++// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 ++// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 ++// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 ++ {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N ++ {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N ++ {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N ++// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 ++ {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 ++ {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 ++ {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 ++ {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 ++ {PJ_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 ++ {PJ_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N ++ {PJ_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N ++ {PJ_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 ++ {PJ_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 ++ {PJ_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N ++ {PJ_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N ++ {PJ_10_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 ++ {PJ_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 ++ {PJ_11_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N ++ {PK_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N ++ {PK_0_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 ++ {PK_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 ++ {PK_1_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N ++ {NC, NC, 0} ++}; ++//*** PWM_HRTIM *** ++ ++MBED_WEAK const PinMap PinMap_PWM_HRTIM[] = { ++ {PA_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHB, 1)}, // HRTIM_CHB2 ++ {PA_9, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 0)}, // HRTIM_CHC1 ++ {PA_10, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 1)}, // HRTIM_CHC2 ++ {PA_11, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 0)}, // HRTIM_CHD1 ++ {PA_12, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 1)}, // HRTIM_CHD2 ++ {PC_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 0)}, // HRTIM_CHA1 ++ {PC_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 1)}, // HRTIM_CHA2 ++ {PC_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHB, 0)}, // HRTIM_CHB1 ++ {PG_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 0)}, // HRTIM_CHE1 ++ {PG_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 1)}, // HRTIM_CHE2 ++ {NC, NC, 0} ++}; ++ ++ ++//*** SERIAL *** ++ ++MBED_WEAK const PinMap PinMap_UART_TX[] = { ++ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, ++ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, ++ {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, ++ {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, ++ {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, ++ {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, ++ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, ++ {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, ++ {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, ++ {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, ++ {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, ++ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, ++ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, ++ {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, ++ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, ++ {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, ++ {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, ++ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, ++ {PH_13, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PJ_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_UART_RX[] = { ++ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, ++ {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, ++ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, ++ {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, ++ {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, ++ {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, ++ {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, ++ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, ++ {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, ++ {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, ++ {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, ++ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, ++ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, ++ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, ++ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, ++ {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, ++ {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, ++ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, ++ {PH_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PI_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PJ_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_UART_RTS[] = { ++ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, ++ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, ++ {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, ++ {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, ++ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, ++ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, ++ {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, ++ {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, ++ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, ++ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_UART_CTS[] = { ++ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, ++ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, ++ {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, ++ {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, ++ {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, ++ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, ++ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, ++ {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, ++ {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, ++ {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, ++ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, ++ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, ++ {NC, NC, 0} ++}; ++ ++//*** SPI *** ++ ++MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { ++ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, ++ {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, ++ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, ++ {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, ++ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, ++ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, ++ {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, ++ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, ++ {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, ++ {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PJ_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_SPI_MISO[] = { ++ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, ++ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, ++ {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, ++ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, ++ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, ++ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, ++ {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, ++ {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PJ_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { ++ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, ++// {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, ++ {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, ++ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, ++ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, ++ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, ++ {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, ++ {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PK_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { ++ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, ++ {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, ++ {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, ++ {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, ++ {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, ++ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, ++ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, ++ {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, ++ {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, ++ {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, ++ {PK_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, ++ {NC, NC, 0} ++}; ++ ++//*** CAN *** ++ ++MBED_WEAK const PinMap PinMap_CAN_RD[] = { ++ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, ++ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, ++ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, ++ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, ++ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, ++ {PH_14, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, ++ {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_CAN_TD[] = { ++ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, ++ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, ++ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, ++ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, ++ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, ++ {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, ++ {NC, NC, 0} ++}; ++ ++//*** QUADSPI *** ++ ++MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { ++ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 ++ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 ++ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { ++ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 ++ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 ++ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { ++ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 ++ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { ++ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 ++ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 ++ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { ++ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK ++ {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK ++ {NC, NC, 0} ++}; ++ ++MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { ++ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS ++ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS ++ {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS ++ {NC, NC, 0} ++}; ++ ++//*** USBDEVICE *** ++ ++MBED_WEAK const PinMap PinMap_USB_FS[] = { ++// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF ++// {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS ++// {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID ++ {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM ++ {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP ++ {NC, NC, 0} ++}; ++ ++//*** USBDEVICE *** ++ ++MBED_WEAK const PinMap PinMap_USB_HS[] = { ++#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) ++// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF ++ {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID ++ {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS ++ {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM ++ {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP ++#else /* MBED_CONF_TARGET_USB_SPEED */ ++ {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 ++ {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK ++ {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 ++ {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 ++ {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 ++ {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 ++ {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 ++ {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 ++ {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 ++ {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP ++ {PH_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT ++ {PI_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR ++#endif /* MBED_CONF_TARGET_USB_SPEED */ ++ {NC, NC, 0} ++}; ++ ++ ++#if defined (CORE_CM4) ++void HSEM2_IRQHandler(void) ++{ ++ HAL_HSEM_IRQHandler(); ++} ++#endif +\ No newline at end of file +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PinNames.h +new file mode 100644 +index 0000000000..97d48334d7 +--- /dev/null ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PinNames.h +@@ -0,0 +1,356 @@ ++/* mbed Microcontroller Library ++ ******************************************************************************* ++ * Copyright (c) 2018, STMicroelectronics ++ * Copyright (c) 2020, Arduino SA ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * 3. Neither the name of STMicroelectronics nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ++ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ******************************************************************************* ++ */ ++ ++/* MBED TARGET LIST: GIGA */ ++ ++#ifndef MBED_PINNAMES_H ++#define MBED_PINNAMES_H ++ ++#include "cmsis.h" ++#include "PinNamesTypes.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#define DUAL_PAD 0xF00 ++ ++typedef enum { ++ ALT0 = 0x100, ++ ALT1 = 0x200, ++ ALT2 = 0x300, ++ ALT3 = 0x400, ++ ALT4 = 0x500, ++} ALTx; ++ ++typedef enum { ++ PA_0 = 0x00, ++ PA_0C = PA_0 | DUAL_PAD, // dual pad ++ PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW ++ PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW ++ PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW ++ PA_1 = 0x01, ++ PA_1C = PA_1 | DUAL_PAD, // dual pad ++ PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW ++ PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW ++ PA_2 = 0x02, ++ PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW ++ PA_3 = 0x03, ++ PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW ++ PA_4 = 0x04, ++ PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW ++ PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW ++ PA_5 = 0x05, ++ PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW ++ PA_5_ALT1 = PA_5 | ALT1, // same pin used for alternate HW ++ PA_5_ALT2 = PA_5 | ALT2, // same pin used for alternate HW ++ PA_6 = 0x06, ++ PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW ++ PA_7 = 0x07, ++ PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW ++ PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW ++ PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW ++ PA_8 = 0x08, ++ PA_9 = 0x09, ++ PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW ++ PA_10 = 0x0A, ++ PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW ++ PA_11 = 0x0B, ++ PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW ++ PA_12 = 0x0C, ++ PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW ++ PA_13 = 0x0D, ++ PA_14 = 0x0E, ++ PA_15 = 0x0F, ++ PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW ++ PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW ++ PB_0 = 0x10, ++ PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW ++ PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW ++ PB_0_ALT2 = PB_0 | ALT2, // same pin used for alternate HW ++ PB_1 = 0x11, ++ PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW ++ PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW ++ PB_2 = 0x12, ++ PB_3 = 0x13, ++ PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW ++ PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW ++ PB_4 = 0x14, ++ PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW ++ PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW ++ PB_5 = 0x15, ++ PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW ++ PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW ++ PB_6 = 0x16, ++ PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW ++ PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW ++ PB_7 = 0x17, ++ PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW ++ PB_8 = 0x18, ++ PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW ++ PB_9 = 0x19, ++ PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW ++ PB_10 = 0x1A, ++ PB_11 = 0x1B, ++ PB_12 = 0x1C, ++ PB_13 = 0x1D, ++ PB_14 = 0x1E, ++ PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW ++ PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW ++ PB_15 = 0x1F, ++ PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW ++ PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW ++ PC_0 = 0x20, ++ PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW ++ PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW ++ PC_1 = 0x21, ++ PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW ++ PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW ++ PC_1_ALT2 = PC_1 | ALT2, // same pin used for alternate HW ++ PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW ++ PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW ++ PC_2 = 0x22, ++ PC_2C = PC_2 | DUAL_PAD, // dual pad ++ PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW ++ PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW ++ PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW ++ PC_2_ALT2 = PC_2 | ALT2, // same pin used for alternate HW ++ PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW ++ PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW ++ PC_3 = 0x23, ++ PC_3C = PC_3 | DUAL_PAD, // dual pad ++ PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW ++ PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW ++ PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW ++ PC_4 = 0x24, ++ PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW ++ PC_5 = 0x25, ++ PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW ++ PC_5_ALT1 = PC_5 | ALT1, // same pin used for alternate HW ++ PC_5_ALT2 = PC_5 | ALT2, // same pin used for alternate HW ++ PC_6 = 0x26, ++ PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW ++ PC_7 = 0x27, ++ PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW ++ PC_8 = 0x28, ++ PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW ++ PC_9 = 0x29, ++ PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW ++ PC_10 = 0x2A, ++ PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW ++ PC_11 = 0x2B, ++ PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW ++ PC_12 = 0x2C, ++ PC_13 = 0x2D, ++ PC_14 = 0x2E, ++ PC_15 = 0x2F, ++ PD_0 = 0x30, ++ PD_1 = 0x31, ++ PD_2 = 0x32, ++ PD_3 = 0x33, ++ PD_4 = 0x34, ++ PD_5 = 0x35, ++ PD_6 = 0x36, ++ PD_7 = 0x37, ++ PD_8 = 0x38, ++ PD_9 = 0x39, ++ PD_10 = 0x3A, ++ PD_11 = 0x3B, ++ PD_12 = 0x3C, ++ PD_13 = 0x3D, ++ PD_14 = 0x3E, ++ PD_15 = 0x3F, ++ PE_0 = 0x40, ++ PE_1 = 0x41, ++ PE_2 = 0x42, ++ PE_3 = 0x43, ++ PE_4 = 0x44, ++ PE_5 = 0x45, ++ PE_6 = 0x46, ++ PE_7 = 0x47, ++ PE_8 = 0x48, ++ PE_9 = 0x49, ++ PE_10 = 0x4A, ++ PE_11 = 0x4B, ++ PE_12 = 0x4C, ++ PE_13 = 0x4D, ++ PE_14 = 0x4E, ++ PE_15 = 0x4F, ++ PF_0 = 0x50, ++ PF_1 = 0x51, ++ PF_2 = 0x52, ++ PF_3 = 0x53, ++ PF_4 = 0x54, ++ PF_4_ALT0 = PF_4 | ALT0, // same pin used for alternate HW ++ PF_5 = 0x55, ++ PF_6 = 0x56, ++ PF_6_ALT0 = PF_6 | ALT0, // same pin used for alternate HW ++ PF_7 = 0x57, ++ PF_8 = 0x58, ++ PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW ++ PF_9 = 0x59, ++ PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW ++ PF_10 = 0x5A, ++ PF_10_ALT0 = PF_10 | ALT0, // same pin used for alternate HW ++ PF_11 = 0x5B, ++ PF_12 = 0x5C, ++ PF_12_ALT0 = PF_12 | ALT0, // same pin used for alternate HW ++ PF_13 = 0x5D, ++ PF_14 = 0x5E, ++ PF_14_ALT0 = PF_14 | ALT0, // same pin used for alternate HW ++ PF_15 = 0x5F, ++ PG_0 = 0x60, ++ PG_1 = 0x61, ++ PG_2 = 0x62, ++ PG_3 = 0x63, ++ PG_4 = 0x64, ++ PG_5 = 0x65, ++ PG_6 = 0x66, ++ PG_7 = 0x67, ++ PG_8 = 0x68, ++ PG_9 = 0x69, ++ PG_10 = 0x6A, ++ PG_11 = 0x6B, ++ PG_12 = 0x6C, ++ PG_13 = 0x6D, ++ PG_14 = 0x6E, ++ PG_15 = 0x6F, ++ PH_0 = 0x70, ++ PH_1 = 0x71, ++ PH_2 = 0x72, ++ PH_3 = 0x73, ++ PH_3_ALT0 = PH_3 | ALT0, // same pin used for alternate HW ++ PH_4 = 0x74, ++ PH_4_ALT0 = PH_4 | ALT0, // same pin used for alternate HW ++ PH_5 = 0x75, ++ PH_5_ALT0 = PH_5 | ALT0, // same pin used for alternate HW ++ PH_6 = 0x76, ++ PH_7 = 0x77, ++ PH_8 = 0x78, ++ PH_9 = 0x79, ++ PH_10 = 0x7A, ++ PH_11 = 0x7B, ++ PH_12 = 0x7C, ++ PH_13 = 0x7D, ++ PH_14 = 0x7E, ++ PH_15 = 0x7F, ++ PI_0 = 0x80, ++ PI_1 = 0x81, ++ PI_2 = 0x82, ++ PI_3 = 0x83, ++ PI_4 = 0x84, ++ PI_5 = 0x85, ++ PI_6 = 0x86, ++ PI_7 = 0x87, ++ PI_8 = 0x88, ++ PI_9 = 0x89, ++ PI_10 = 0x8A, ++ PI_11 = 0x8B, ++ PI_12 = 0x8C, ++ PI_13 = 0x8D, ++ PI_14 = 0x8E, ++ PI_15 = 0x8F, ++ PJ_0 = 0x90, ++ PJ_1 = 0x91, ++ PJ_2 = 0x92, ++ PJ_3 = 0x93, ++ PJ_4 = 0x94, ++ PJ_5 = 0x95, ++ PJ_6 = 0x96, ++ PJ_7 = 0x97, ++ PJ_8 = 0x98, ++ PJ_8_ALT0 = PJ_8 | ALT0, // same pin used for alternate HW ++ PJ_9 = 0x99, ++ PJ_9_ALT0 = PJ_9 | ALT0, // same pin used for alternate HW ++ PJ_10 = 0x9A, ++ PJ_10_ALT0 = PJ_10 | ALT0, // same pin used for alternate HW ++ PJ_11 = 0x9B, ++ PJ_11_ALT0 = PJ_11 | ALT0, // same pin used for alternate HW ++ PJ_12 = 0x9C, ++ PJ_13 = 0x9D, ++ PJ_14 = 0x9E, ++ PJ_15 = 0x9F, ++ PK_0 = 0xA0, ++ PK_0_ALT0 = PK_0 | ALT0, // same pin used for alternate HW ++ PK_1 = 0xA1, ++ PK_1_ALT0 = PK_1 | ALT0, // same pin used for alternate HW ++ PK_2 = 0xA2, ++ PK_3 = 0xA3, ++ PK_4 = 0xA4, ++ PK_5 = 0xA5, ++ PK_6 = 0xA6, ++ PK_7 = 0xA7, ++ ++ ADC_TEMP = 0xF0, // Internal pin virtual value ++ ADC_VREF = 0xF1, // Internal pin virtual value ++ ADC_VBAT = 0xF2, // Internal pin virtual value ++ ++ // Not connected ++ NC = (int)0xFFFFFFFF, ++ ++ CONSOLE_TX = NC, ++ CONSOLE_RX = NC, ++ ++ WL_REG_ON = NC, ++ WL_HOST_WAKE = NC, ++ WL_SDIO_0 = NC, ++ WL_SDIO_1 = NC, ++ WL_SDIO_2 = NC, ++ WL_SDIO_3 = NC, ++ WL_SDIO_CMD = NC, ++ WL_SDIO_CLK = NC, ++ ++ CYBSP_BT_UART_RX = NC, ++ CYBSP_BT_UART_TX = NC, ++ CYBSP_BT_UART_RTS = NC, ++ CYBSP_BT_UART_CTS = NC, ++ ++ CYBSP_BT_POWER = NC, ++ CYBSP_BT_HOST_WAKE = NC, ++ CYBSP_BT_DEVICE_WAKE = NC, ++ ++ /**** QSPI FLASH pins ****/ ++ QSPI_FLASH1_IO0 = NC, ++ QSPI_FLASH1_IO1 = NC, ++ QSPI_FLASH1_IO2 = NC, ++ QSPI_FLASH1_IO3 = NC, ++ QSPI_FLASH1_SCK = NC, ++ QSPI_FLASH1_CSN = NC ++ ++} PinName; ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +diff --git a/targets/targets.json b/targets/targets.json +index dac2c94ddc..9a12422336 100644 +--- a/targets/targets.json ++++ b/targets/targets.json +@@ -3711,23 +3711,49 @@ + ], + "device_name": "STM32H747XIHx" + }, +- "PORTENTA_H7_M4": { +- "inherits": ["PORTENTA_H7"], +- "core": "Cortex-M4F", +- "mbed_rom_start": "0x08100000", +- "mbed_rom_size" : "0x100000", +- "mbed_ram_start": "0x10000000", +- "mbed_ram_size" : "0x48000", +- "extra_labels_add": [ +- "STM32H747xI_CM4" +- ], ++ "GENERIC_STM32H747_M4": { ++ "inherits": ["MCU_STM32H747xI_CM4"], ++ "config": { ++ "usb_speed": { ++ "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", ++ "value": "USE_USB_OTG_HS" ++ } ++ }, + "macros_add": [ ++ "MBEDTLS_FS_IO", ++ "MBEDTLS_SHA1_C", ++ "CM4_BOOT_BY_APPLICATION", + "CORE_CM4", +- "MBED_MPU_CUSTOM" ++ "MBED_MPU_CUSTOM", ++ "CYW43XXX_UNBUFFERED_UART" + ], + "device_has_remove": [ + "MPU" +- ] ++ ], ++ "components_add": [ ++ "QSPIF", ++ "WHD", ++ "4343W_FS", ++ "CYW43XXX" ++ ], ++ "device_has_add": [ ++ "USBDEVICE", ++ "QSPI" ++ ], ++ "extra_labels_add": [ ++ "CORDIO", ++ "GENERIC_STM32H747_M4" ++ ], ++ "features": [ ++ "BLE" ++ ], ++ "overrides": { ++ "system_power_supply": "PWR_LDO_SUPPLY", ++ "clock_source": "USE_PLL_HSI", ++ "lse_available": 0, ++ "lpticker_delay_ticks": 0, ++ "i2c_timing_value_algo": true ++ } + }, + "PORTENTA_X8": { + "inherits": ["MCU_STM32H747xI_CM4"], +-- +2.42.0 + diff --git a/patches/0214-stm32h7-adc-use-CLKP-as-clock-source.patch b/patches/0214-stm32h7-adc-use-CLKP-as-clock-source.patch new file mode 100644 index 000000000..9b327a7aa --- /dev/null +++ b/patches/0214-stm32h7-adc-use-CLKP-as-clock-source.patch @@ -0,0 +1,49 @@ +From 10ac121c7e63d7abb856ec795b124dedf8dd9f49 Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Thu, 2 Nov 2023 13:49:35 +0100 +Subject: [PATCH] stm32h7: adc: use CLKP as clock source + +Fixes analogRead() interferring with DSI/SDRAM +--- + .../TARGET_STM32H7/analogin_device.c | 25 +------------------ + 1 file changed, 1 insertion(+), 24 deletions(-) + +diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +index be16b16cda..8b617e307a 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c ++++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +@@ -36,30 +36,7 @@ void analogin_pll_configuration(void) + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; +- if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) { +- PeriphClkInitStruct.PLL2.PLL2M = 16; +- PeriphClkInitStruct.PLL2.PLL2N = 120; +- } else { +- #if HSE_VALUE==8000000 +- PeriphClkInitStruct.PLL2.PLL2M = 2; +- PeriphClkInitStruct.PLL2.PLL2N = 120; +- #elif HSE_VALUE==16000000 +- PeriphClkInitStruct.PLL2.PLL2M = 2; +- PeriphClkInitStruct.PLL2.PLL2N = 60; +- #elif HSE_VALUE==25000000 +- PeriphClkInitStruct.PLL2.PLL2M = 5; +- PeriphClkInitStruct.PLL2.PLL2N = 96; +- #else +- error("HSE not configured properly"); +- #endif +- } +- PeriphClkInitStruct.PLL2.PLL2P = 3; +- PeriphClkInitStruct.PLL2.PLL2Q = 4; +- PeriphClkInitStruct.PLL2.PLL2R = 2; +- PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_1; +- PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; +- PeriphClkInitStruct.PLL2.PLL2FRACN = 0; +- PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; ++ PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + error("analogin_init HAL_RCCEx_PeriphCLKConfig"); + } +-- +2.42.0 + diff --git a/patches/0215-Gemalto-Cinterion-Cellular-Disable-urcs-while-readin.patch b/patches/0215-Gemalto-Cinterion-Cellular-Disable-urcs-while-readin.patch new file mode 100644 index 000000000..b0ba08c8e --- /dev/null +++ b/patches/0215-Gemalto-Cinterion-Cellular-Disable-urcs-while-readin.patch @@ -0,0 +1,109 @@ +From ae470a5d61a27ec11fea588fa53a1f4f1ddac1cb Mon Sep 17 00:00:00 2001 +From: pennam +Date: Tue, 7 Nov 2023 10:38:21 +0100 +Subject: [PATCH 215/221] Gemalto Cinterion Cellular: Disable urcs while + reading + +--- + .../GEMALTO_CINTERION_CellularStack.cpp | 23 +++++++++++-------- + 1 file changed, 14 insertions(+), 9 deletions(-) + +diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +index 33a73bf9a3..fc2e8985d7 100644 +--- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp ++++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +@@ -524,6 +524,9 @@ sisw_retry: + return (_at.get_last_error() == NSAPI_ERROR_OK) ? accept_len : NSAPI_ERROR_DEVICE_ERROR; + } + ++#define DISABLE_URCs _at.at_cmd_discard("^SCFG", "=", "%s%s","Tcp/WithURCs","off") ++#define RESTORE_URCs_AND_RETURN(ret) do { _at.at_cmd_discard("^SCFG", "=", "%s%s","Tcp/WithURCs","on"); return ret; } while(0) ++ + nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(CellularSocket *socket, SocketAddress *address, + void *buffer, nsapi_size_t size) + { +@@ -531,13 +534,15 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell + // open on the modem, assert here to catch a programming error + MBED_ASSERT(socket->id != -1); + ++ DISABLE_URCs; ++ + // we must use this flag, otherwise ^SISR URC can come while we are reading response and there is + // no way to detect if that is really an URC or response + if (!socket->pending_bytes) { + _at.process_oob(); // check for ^SISR URC + if (!socket->pending_bytes) { + tr_debug("Socket %d recv would block", socket->id); +- return NSAPI_ERROR_WOULD_BLOCK; ++ RESTORE_URCs_AND_RETURN(NSAPI_ERROR_WOULD_BLOCK); + } + } + +@@ -552,7 +557,7 @@ sisr_retry: + _at.resp_start("^SISR:"); + if (!_at.info_resp()) { + tr_error("Socket %d not responding", socket->id); +- return NSAPI_ERROR_DEVICE_ERROR; ++ RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); + } + + int socket_id = _at.read_int(); +@@ -564,24 +569,24 @@ sisr_retry: + goto sisr_retry; + } + tr_error("Socket recvfrom id %d != %d", socket_id, socket->id); +- return NSAPI_ERROR_DEVICE_ERROR; ++ RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); + } + + nsapi_size_or_error_t len = _at.read_int(); + if (len == 0) { + tr_warn("Socket %d no data", socket->id); + _at.resp_stop(); +- return NSAPI_ERROR_WOULD_BLOCK; ++ RESTORE_URCs_AND_RETURN(NSAPI_ERROR_WOULD_BLOCK); + } + if (len == -1) { + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleTX62 && _at.get_last_read_error() == -2) { + _at.process_oob(); + tr_error("Socket %d recvfrom finished!", socket->id); + socket->pending_bytes = 0; +- return NSAPI_ERROR_OK; ++ RESTORE_URCs_AND_RETURN(NSAPI_ERROR_OK); + } + tr_error("Socket %d recvfrom failed!", socket->id); +- return NSAPI_ERROR_DEVICE_ERROR; ++ RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); + } + if (len >= (nsapi_size_or_error_t)size) { + len = (nsapi_size_or_error_t)size; +@@ -606,7 +611,7 @@ sisr_retry: + int len = _at.read_bytes(at_buf + ip_len, 1); + if (len <= 0) { + tr_error("Socket %d recvfrom addr (len %d)", socket->id, ip_len); +- return NSAPI_ERROR_DEVICE_ERROR; ++ RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); + } + ip_len += len; + } while (ip_len < ip_address_len && at_buf[ip_len - 2] != '\r' && at_buf[ip_len - 1] != '\n'); +@@ -629,7 +634,7 @@ sisr_retry: + int ip_len = _at.read_string(ip_address, sizeof(ip_address)); + if (ip_len <= 0) { + tr_error("Socket %d recvfrom addr (len %d)", socket->id, ip_len); +- return NSAPI_ERROR_DEVICE_ERROR; ++ RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); + } + } + +@@ -671,7 +676,7 @@ sisr_retry: + + _at.resp_stop(); + +- return (_at.get_last_error() == NSAPI_ERROR_OK) ? (recv_len ? recv_len : NSAPI_ERROR_WOULD_BLOCK) : NSAPI_ERROR_DEVICE_ERROR; ++ RESTORE_URCs_AND_RETURN((_at.get_last_error() == NSAPI_ERROR_OK) ? (recv_len ? recv_len : NSAPI_ERROR_WOULD_BLOCK) : NSAPI_ERROR_DEVICE_ERROR); + } + + // setup internet connection profile for sockets +-- +2.42.0 + diff --git a/patches/0216-AT_CellularContext-Fix-SCFG-commands-to-configure-ba.patch b/patches/0216-AT_CellularContext-Fix-SCFG-commands-to-configure-ba.patch new file mode 100644 index 000000000..656fabd77 --- /dev/null +++ b/patches/0216-AT_CellularContext-Fix-SCFG-commands-to-configure-ba.patch @@ -0,0 +1,49 @@ +From 8dd642cb19e16ae9169fa52f26f4b1a6abc489d8 Mon Sep 17 00:00:00 2001 +From: pennam +Date: Tue, 7 Nov 2023 14:10:31 +0100 +Subject: [PATCH 216/221] AT_CellularContext: Fix ^SCFG commands to configure + bands and URCs + +--- + .../source/framework/AT/AT_CellularContext.cpp | 15 +++++---------- + 1 file changed, 5 insertions(+), 10 deletions(-) + +diff --git a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +index 087846e9b5..e876e384c9 100644 +--- a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp ++++ b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +@@ -452,26 +452,21 @@ void AT_CellularContext::enable_access_technology() + { + case CATM1: + _at.at_cmd_discard("^SXRAT", "=","%d", _rat); +- _at.cmd_start_stop("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); +- _at.resp_start("^SCFG"); +- _at.cmd_start_stop("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); +- _at.resp_start("^SCFG"); ++ _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); ++ _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); + break; + + case CATNB: + _at.at_cmd_discard("^SXRAT", "=","%d", _rat); +- _at.cmd_start_stop("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); +- _at.resp_start("^SCFG"); +- _at.cmd_start_stop("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); +- _at.resp_start("^SCFG"); ++ _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); ++ _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); + break; + + default: + break; + } + +- _at.cmd_start_stop("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); +- _at.resp_start("^SCFG"); ++ _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); + free(buffer); + + } +-- +2.42.0 + diff --git a/patches/0217-AT_CellularContext-move-enable_access_technology-at-.patch b/patches/0217-AT_CellularContext-move-enable_access_technology-at-.patch new file mode 100644 index 000000000..233e71ddf --- /dev/null +++ b/patches/0217-AT_CellularContext-move-enable_access_technology-at-.patch @@ -0,0 +1,123 @@ +From 822f1b2b855afd1f332dc3c8e490c1f7b08923b5 Mon Sep 17 00:00:00 2001 +From: pennam +Date: Fri, 10 Nov 2023 10:30:12 +0100 +Subject: [PATCH 217/221] AT_CellularContext: move enable_access_technology() + at commands into GEMALTO_CINTERION_CellularContext + +--- + .../framework/AT/AT_CellularContext.h | 4 +-- + .../framework/AT/AT_CellularContext.cpp | 25 +---------------- + .../GEMALTO_CINTERION_CellularContext.cpp | 28 +++++++++++++++++++ + .../GEMALTO_CINTERION_CellularContext.h | 1 + + 4 files changed, 32 insertions(+), 26 deletions(-) + +diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +index eb3bf5afdd..2f68f1f97b 100644 +--- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h ++++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +@@ -135,8 +135,6 @@ private: + + PinName _dcd_pin; + bool _active_high; +- RadioAccessTechnologyType _rat; +- FrequencyBand _band; + + protected: + char _found_apn[MAX_APN_LENGTH]; +@@ -144,6 +142,8 @@ protected: + bool _cp_req; + bool _is_connected; + ATHandler &_at; ++ RadioAccessTechnologyType _rat; ++ FrequencyBand _band; + }; + + } // namespace mbed +diff --git a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +index e876e384c9..c05fc386e0 100644 +--- a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp ++++ b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +@@ -445,30 +445,7 @@ bool AT_CellularContext::set_new_context(int cid) + + void AT_CellularContext::enable_access_technology() + { +- char *buffer = new char [8]; +- memset(buffer, 0, 8); +- sprintf(buffer,"%08X", _band); +- switch (_rat) +- { +- case CATM1: +- _at.at_cmd_discard("^SXRAT", "=","%d", _rat); +- _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); +- _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); +- break; +- +- case CATNB: +- _at.at_cmd_discard("^SXRAT", "=","%d", _rat); +- _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); +- _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); +- break; +- +- default: +- break; +- } +- +- _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); +- free(buffer); +- ++ enable_access_technology(); + } + + nsapi_error_t AT_CellularContext::do_activate_context() +diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +index 7ee2c8e53c..bc2b1d514c 100644 +--- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp ++++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +@@ -148,4 +148,32 @@ NetworkStack *GEMALTO_CINTERION_CellularContext::get_stack() + } + #endif // NSAPI_PPP_AVAILABLE + ++void GEMALTO_CINTERION_CellularContext::enable_access_technology() ++{ ++ char *buffer = new char [8]; ++ memset(buffer, 0, 8); ++ sprintf(buffer,"%08X", _band); ++ switch (_rat) ++ { ++ case CATM1: ++ _at.at_cmd_discard("^SXRAT", "=","%d", _rat); ++ _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); ++ _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); ++ break; ++ ++ case CATNB: ++ _at.at_cmd_discard("^SXRAT", "=","%d", _rat); ++ _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); ++ _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); ++ break; ++ ++ default: ++ break; ++ } ++ ++ _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); ++ free(buffer); ++ ++} ++ + } /* namespace mbed */ +diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h +index 0645b2b87c..cd9aef0222 100644 +--- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h ++++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h +@@ -34,6 +34,7 @@ protected: + virtual NetworkStack *get_stack(); + #endif // NSAPI_PPP_AVAILABLE + virtual nsapi_error_t do_user_authentication(); ++ virtual void enable_access_technology(); + }; + + } /* namespace mbed */ +-- +2.42.0 + diff --git a/patches/0218-GEMALTO_CINTERION_CellularContext-do-not-disable-all.patch b/patches/0218-GEMALTO_CINTERION_CellularContext-do-not-disable-all.patch new file mode 100644 index 000000000..e0904957c --- /dev/null +++ b/patches/0218-GEMALTO_CINTERION_CellularContext-do-not-disable-all.patch @@ -0,0 +1,32 @@ +From 915ad28bd3e9d369128691e8558c4626bc65fb82 Mon Sep 17 00:00:00 2001 +From: pennam +Date: Fri, 10 Nov 2023 10:30:54 +0100 +Subject: [PATCH 218/221] GEMALTO_CINTERION_CellularContext: do not disable all + bands + + * Switching rat AT command fails and should not be necessary to disable bands since we do not use a fallback rat +--- + .../GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +index bc2b1d514c..bf7522621b 100644 +--- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp ++++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +@@ -158,13 +158,11 @@ void GEMALTO_CINTERION_CellularContext::enable_access_technology() + case CATM1: + _at.at_cmd_discard("^SXRAT", "=","%d", _rat); + _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); +- _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); + break; + + case CATNB: + _at.at_cmd_discard("^SXRAT", "=","%d", _rat); + _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); +- _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); + break; + + default: +-- +2.42.0 + diff --git a/patches/0219-GEMALTO_CINTERION_CellularContext-add-return-value-t.patch b/patches/0219-GEMALTO_CINTERION_CellularContext-add-return-value-t.patch new file mode 100644 index 000000000..8c1ad17ab --- /dev/null +++ b/patches/0219-GEMALTO_CINTERION_CellularContext-add-return-value-t.patch @@ -0,0 +1,108 @@ +From 64e0c1f45702e5e2d11a667176c12582c3a36bdf Mon Sep 17 00:00:00 2001 +From: pennam +Date: Fri, 10 Nov 2023 10:58:37 +0100 +Subject: [PATCH 219/221] GEMALTO_CINTERION_CellularContext: add return value + to enable_access_technology() + +--- + .../framework/AT/AT_CellularContext.h | 2 +- + .../framework/AT/AT_CellularContext.cpp | 4 +-- + .../GEMALTO_CINTERION_CellularContext.cpp | 25 +++++++++++-------- + .../GEMALTO_CINTERION_CellularContext.h | 2 +- + 4 files changed, 19 insertions(+), 14 deletions(-) + +diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +index 2f68f1f97b..6291bb11d7 100644 +--- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h ++++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +@@ -109,7 +109,7 @@ protected: + * @return NIDD context text, e.g. Non-IP or NONIP + */ + virtual const char *get_nonip_context_type_str(); +- virtual void enable_access_technology(); ++ virtual nsapi_error_t enable_access_technology(); + virtual void set_cid(int cid); + + private: +diff --git a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +index c05fc386e0..f5e69aac80 100644 +--- a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp ++++ b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +@@ -443,9 +443,9 @@ bool AT_CellularContext::set_new_context(int cid) + return success; + } + +-void AT_CellularContext::enable_access_technology() ++nsapi_error_t AT_CellularContext::enable_access_technology() + { +- enable_access_technology(); ++ return enable_access_technology(); + } + + nsapi_error_t AT_CellularContext::do_activate_context() +diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +index bf7522621b..bbd5c4c4b5 100644 +--- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp ++++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +@@ -148,30 +148,35 @@ NetworkStack *GEMALTO_CINTERION_CellularContext::get_stack() + } + #endif // NSAPI_PPP_AVAILABLE + +-void GEMALTO_CINTERION_CellularContext::enable_access_technology() ++nsapi_error_t GEMALTO_CINTERION_CellularContext::enable_access_technology() + { +- char *buffer = new char [8]; +- memset(buffer, 0, 8); +- sprintf(buffer,"%08X", _band); ++ nsapi_error_t error = NSAPI_ERROR_OK; ++ char buffer[9] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; ++ ++ snprintf(buffer, 9, "%08X", _band); + switch (_rat) + { + case CATM1: +- _at.at_cmd_discard("^SXRAT", "=","%d", _rat); +- _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); ++ error = _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM", buffer); + break; + + case CATNB: +- _at.at_cmd_discard("^SXRAT", "=","%d", _rat); +- _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); ++ error = _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB", buffer); + break; + + default: + break; + } ++ if (error != NSAPI_ERROR_OK) { ++ return error; ++ } + +- _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); +- free(buffer); ++ error = _at.at_cmd_discard("^SXRAT", "=","%d", _rat); ++ if (error != NSAPI_ERROR_OK) { ++ return error; ++ } + ++ return _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); + } + + } /* namespace mbed */ +diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h +index cd9aef0222..24ff87bc08 100644 +--- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h ++++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h +@@ -34,7 +34,7 @@ protected: + virtual NetworkStack *get_stack(); + #endif // NSAPI_PPP_AVAILABLE + virtual nsapi_error_t do_user_authentication(); +- virtual void enable_access_technology(); ++ virtual nsapi_error_t enable_access_technology(); + }; + + } /* namespace mbed */ +-- +2.42.0 + diff --git a/patches/0220-GEMALTO_CINTERION_CellularContext-connect-check-retu.patch b/patches/0220-GEMALTO_CINTERION_CellularContext-connect-check-retu.patch new file mode 100644 index 000000000..0b4784e27 --- /dev/null +++ b/patches/0220-GEMALTO_CINTERION_CellularContext-connect-check-retu.patch @@ -0,0 +1,64 @@ +From b5d44a4f3be3938045c185d5f1753cbade22a6f9 Mon Sep 17 00:00:00 2001 +From: pennam +Date: Fri, 10 Nov 2023 17:06:53 +0100 +Subject: [PATCH 220/221] GEMALTO_CINTERION_CellularContext::connect check + return codes and print errors + +--- + .../GEMALTO_CINTERION_CellularContext.cpp | 29 +++++++++++++++---- + 1 file changed, 24 insertions(+), 5 deletions(-) + +diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +index bbd5c4c4b5..0af08a786d 100644 +--- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp ++++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +@@ -33,22 +33,41 @@ GEMALTO_CINTERION_CellularContext::~GEMALTO_CINTERION_CellularContext() + nsapi_error_t GEMALTO_CINTERION_CellularContext::connect(const char *sim_pin, const char *apn, const char *uname, + const char *pwd) + { ++ nsapi_error_t error = NSAPI_ERROR_OK; ++ + set_sim_pin(sim_pin); + set_credentials(apn, uname, pwd); + +- set_device_ready(); ++ error = set_device_ready(); ++ if ((error != NSAPI_ERROR_OK) && (error != NSAPI_ERROR_ALREADY)) { ++ tr_error("Failure connecting to GEMALTO CINTERION modem"); ++ return error; ++ } + + _at.lock(); + bool valid_context = get_context(); + _at.unlock(); + +- if(!valid_context) { +- set_new_context(_cid); ++ if (!valid_context) { ++ valid_context = set_new_context(_cid); ++ } ++ ++ if (!valid_context) { ++ tr_error("Invalid AT cellular context %d", _cid); ++ return NSAPI_ERROR_DEVICE_ERROR; + } + +- do_user_authentication(); ++ error = do_user_authentication(); ++ if (error != NSAPI_ERROR_OK) { ++ tr_error("Failure during user authentication"); ++ return error; ++ } + +- enable_access_technology(); ++ error = enable_access_technology(); ++ if (error != NSAPI_ERROR_OK) { ++ tr_error("Failure enabling access technology"); ++ return error; ++ } + + return AT_CellularContext::connect(); + } +-- +2.42.0 + diff --git a/patches/0221-TLSSocketWrapper-allow-appending-ca_cert-to-an-empty.patch b/patches/0221-TLSSocketWrapper-allow-appending-ca_cert-to-an-empty.patch new file mode 100644 index 000000000..d2655ce38 --- /dev/null +++ b/patches/0221-TLSSocketWrapper-allow-appending-ca_cert-to-an-empty.patch @@ -0,0 +1,31 @@ +From e69150d098a78a9f4d10f5f993dee29602cd076a Mon Sep 17 00:00:00 2001 +From: pennam +Date: Mon, 13 Nov 2023 16:22:14 +0100 +Subject: [PATCH 221/221] TLSSocketWrapper: allow appending ca_cert to an empty + chain + +--- + connectivity/netsocket/source/TLSSocketWrapper.cpp | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp +index 6665f64cc0..1fb9c21769 100644 +--- a/connectivity/netsocket/source/TLSSocketWrapper.cpp ++++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp +@@ -145,10 +145,11 @@ nsapi_error_t TLSSocketWrapper::append_root_ca_cert(const void *root_ca, size_t + + crt = get_ca_chain(); + if (!crt) { +- return NSAPI_ERROR_NO_MEMORY; ++ /* In no chain is configured create a new one */ ++ return set_root_ca_cert(root_ca, len); + } + +- /* Parse CA certification */ ++ /* Append root_ca to the crt chain */ + int ret; + if ((ret = mbedtls_x509_crt_parse(crt, static_cast(root_ca), + len)) != 0) { +-- +2.42.0 + diff --git a/patches/0222-STM32H7-fix-DUAL_PAD-value-to-avoid-ALTx-conflict.patch b/patches/0222-STM32H7-fix-DUAL_PAD-value-to-avoid-ALTx-conflict.patch new file mode 100644 index 000000000..b975906fd --- /dev/null +++ b/patches/0222-STM32H7-fix-DUAL_PAD-value-to-avoid-ALTx-conflict.patch @@ -0,0 +1,123 @@ +From 2e1da01300f14f12b39c24434fe7fe5488258353 Mon Sep 17 00:00:00 2001 +From: Leonardo Cavagnis +Date: Mon, 13 Nov 2023 17:14:02 +0100 +Subject: [PATCH] STM32H7: fix DUAL_PAD value to avoid ALTx conflict + +--- + .../TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h | 2 +- + .../TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h | 2 +- + .../TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h | 2 +- + .../TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h | 2 +- + .../TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h | 2 +- + .../TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h | 2 +- + .../TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h | 2 +- + .../TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h | 2 +- + 8 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h +index 9e4001b55a..01e4e1b98a 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h +@@ -27,7 +27,7 @@ + extern "C" { + #endif + +-#define DUAL_PAD 0xF00 ++#define DUAL_PAD 0x800 + + typedef enum { + ALT0 = 0x100, +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h +index 1fb109f69c..fbda341823 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h +@@ -27,7 +27,7 @@ + extern "C" { + #endif + +-#define DUAL_PAD 0xF00 ++#define DUAL_PAD 0x800 + + typedef enum { + ALT0 = 0x100, +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h +index 1a6dccb193..d68ecb2c25 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h +@@ -27,7 +27,7 @@ + extern "C" { + #endif + +-#define DUAL_PAD 0xF00 ++#define DUAL_PAD 0x800 + + typedef enum { + ALT0 = 0x100, +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h +index e5463fe093..f7314dbace 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h +@@ -43,7 +43,7 @@ + extern "C" { + #endif + +-#define DUAL_PAD 0xF00 ++#define DUAL_PAD 0x800 + + typedef enum { + ALT0 = 0x100, +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h +index 93baf9ee19..efe0f63b29 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h +@@ -43,7 +43,7 @@ + extern "C" { + #endif + +-#define DUAL_PAD 0xF00 ++#define DUAL_PAD 0x800 + + typedef enum { + ALT0 = 0x100, +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h +index 585fb0ea8f..0c088c81e6 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h +@@ -43,7 +43,7 @@ + extern "C" { + #endif + +-#define DUAL_PAD 0xF00 ++#define DUAL_PAD 0x800 + + typedef enum { + ALT0 = 0x100, +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h +index 1cce05b2e2..96f611cde5 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h +@@ -43,7 +43,7 @@ + extern "C" { + #endif + +-#define DUAL_PAD 0xF00 ++#define DUAL_PAD 0x800 + + typedef enum { + ALT0 = 0x100, +diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h +index 94ccfc23fa..a44c8620cd 100644 +--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h ++++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h +@@ -27,7 +27,7 @@ + extern "C" { + #endif + +-#define DUAL_PAD 0xF00 ++#define DUAL_PAD 0x800 + + typedef enum { + ALT0 = 0x100, +-- +2.42.0 + diff --git a/patches/0223-CellularDevice-avoid-callback-data-is-changed-before.patch b/patches/0223-CellularDevice-avoid-callback-data-is-changed-before.patch new file mode 100644 index 000000000..432846512 --- /dev/null +++ b/patches/0223-CellularDevice-avoid-callback-data-is-changed-before.patch @@ -0,0 +1,41 @@ +From 0611201dfb21fcc36e0d37e283a7e8bb44664ec8 Mon Sep 17 00:00:00 2001 +From: pennam +Date: Fri, 17 Nov 2023 17:25:50 +0100 +Subject: [PATCH 223/226] CellularDevice: avoid callback data is changed before + attached callback is changed + +--- + .../source/framework/device/CellularDevice.cpp | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/connectivity/cellular/source/framework/device/CellularDevice.cpp b/connectivity/cellular/source/framework/device/CellularDevice.cpp +index 50d900e14a..1f53b33e61 100644 +--- a/connectivity/cellular/source/framework/device/CellularDevice.cpp ++++ b/connectivity/cellular/source/framework/device/CellularDevice.cpp +@@ -180,6 +180,11 @@ void CellularDevice::stm_callback(nsapi_event_t ev, intptr_t ptr) + + void CellularDevice::cellular_callback(nsapi_event_t ev, intptr_t ptr, CellularContext *ctx) + { ++ // forward to callback function if set by attach(...). ++ if (_status_cb) { ++ _status_cb(ev, ptr); ++ } ++ + if (ev >= NSAPI_EVENT_CELLULAR_STATUS_BASE && ev <= NSAPI_EVENT_CELLULAR_STATUS_END) { + cellular_connection_status_t cell_ev = (cellular_connection_status_t)ev; + cell_callback_data_t *ptr_data = (cell_callback_data_t *)ptr; +@@ -220,11 +225,6 @@ void CellularDevice::cellular_callback(nsapi_event_t ev, intptr_t ptr, CellularC + } + curr = curr->_next; + } +- +- // forward to callback function if set by attach(...). +- if (_status_cb) { +- _status_cb(ev, ptr); +- } + } + + nsapi_error_t CellularDevice::shutdown() +-- +2.42.0 + diff --git a/patches/0224-ATHandler-do-not-temporarily-change-debug-options-to.patch b/patches/0224-ATHandler-do-not-temporarily-change-debug-options-to.patch new file mode 100644 index 000000000..2cd99db2b --- /dev/null +++ b/patches/0224-ATHandler-do-not-temporarily-change-debug-options-to.patch @@ -0,0 +1,30 @@ +From 973a19b25200a2d11746ea8196a8403f189e13a7 Mon Sep 17 00:00:00 2001 +From: pennam +Date: Fri, 17 Nov 2023 17:29:39 +0100 +Subject: [PATCH 224/226] ATHandler: do not temporarily change debug options to + partially trace AT commands + +--- + connectivity/cellular/source/framework/device/ATHandler.cpp | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/connectivity/cellular/source/framework/device/ATHandler.cpp b/connectivity/cellular/source/framework/device/ATHandler.cpp +index f305fd8af5..36d21243f8 100644 +--- a/connectivity/cellular/source/framework/device/ATHandler.cpp ++++ b/connectivity/cellular/source/framework/device/ATHandler.cpp +@@ -1244,12 +1244,7 @@ void ATHandler::handle_start(const char *cmd, const char *cmd_chr) + } + _cmd_buffer[len] = '\0'; + +- const bool temp_state = get_debug(); +- set_debug(true); +- + cmd_start(_cmd_buffer); +- +- set_debug(temp_state); + } + + void ATHandler::cmd_start_stop(const char *cmd, const char *cmd_chr, const char *format, ...) +-- +2.42.0 + diff --git a/patches/0225-CellularStateMachine-add-state-data-to-timeout-and-r.patch b/patches/0225-CellularStateMachine-add-state-data-to-timeout-and-r.patch new file mode 100644 index 000000000..813262e59 --- /dev/null +++ b/patches/0225-CellularStateMachine-add-state-data-to-timeout-and-r.patch @@ -0,0 +1,97 @@ +From 1e2795ce9a47146d8c87e4ff957ac3784482e075 Mon Sep 17 00:00:00 2001 +From: pennam +Date: Fri, 17 Nov 2023 17:57:49 +0100 +Subject: [PATCH 225/226] CellularStateMachine: add state data to timeout and + retry callbacks + +--- + .../framework/common/CellularCommon.h | 20 +++++++++++++++++++ + .../framework/device/CellularStateMachine.h | 2 ++ + .../framework/device/CellularStateMachine.cpp | 11 +++++++--- + 3 files changed, 30 insertions(+), 3 deletions(-) + +diff --git a/connectivity/cellular/include/cellular/framework/common/CellularCommon.h b/connectivity/cellular/include/cellular/framework/common/CellularCommon.h +index f0466e88cf..96e25dc991 100644 +--- a/connectivity/cellular/include/cellular/framework/common/CellularCommon.h ++++ b/connectivity/cellular/include/cellular/framework/common/CellularCommon.h +@@ -47,6 +47,26 @@ struct cell_signal_quality_t { + } + }; + ++struct cell_timeout_cb_t { ++ int timeout; /* configured timeout */ ++ int state; /* cellular state */ ++ cell_timeout_cb_t() ++ { ++ timeout = -1; ++ state = -1; ++ } ++}; ++ ++struct cell_retry_cb_t { ++ int retry_count; /* retry count */ ++ int state; /* cellular state */ ++ cell_retry_cb_t() ++ { ++ retry_count = -1; ++ state = -1; ++ } ++}; ++ + /** + * Cellular specific event changes. + * Connect and disconnect are handled via NSAPI_EVENT_CONNECTION_STATUS_CHANGE +diff --git a/connectivity/cellular/include/cellular/framework/device/CellularStateMachine.h b/connectivity/cellular/include/cellular/framework/device/CellularStateMachine.h +index 67912e463c..aed9d615ce 100644 +--- a/connectivity/cellular/include/cellular/framework/device/CellularStateMachine.h ++++ b/connectivity/cellular/include/cellular/framework/device/CellularStateMachine.h +@@ -189,6 +189,8 @@ private: + bool _command_success; + bool _is_retry; + cell_callback_data_t _cb_data; ++ cell_timeout_cb_t _timeout_cb_data; ++ cell_retry_cb_t _retry_cb_data; + cellular_connection_status_t _current_event; + int _status; + PlatformMutex _mutex; +diff --git a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp +index 833f1d2239..37416ca72e 100644 +--- a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp ++++ b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp +@@ -61,7 +61,7 @@ CellularStateMachine::CellularStateMachine(CellularDevice &device, events::Event + _start_time(rand() % (MBED_CONF_CELLULAR_RANDOM_MAX_START_DELAY)), + #endif // MBED_CONF_CELLULAR_RANDOM_MAX_START_DELAY + _event_timeout(-1s), _event_id(-1), _plmn(0), _command_success(false), +- _is_retry(false), _cb_data(), _current_event(CellularDeviceReady), _status(0) ++ _is_retry(false), _cb_data(), _timeout_cb_data(), _retry_cb_data(), _current_event(CellularDeviceReady), _status(0) + { + + // set initial retry values in seconds +@@ -289,8 +289,10 @@ void CellularStateMachine::retry_state_or_fail() + if (_retry_count < _retry_array_length) { + tr_debug("%s: retry %d/%d", get_state_string(_state), _retry_count, _retry_array_length); + // send info to application/driver about error logic so it can implement proper error logic ++ _retry_cb_data.retry_count = _retry_count; ++ _retry_cb_data.state = _state; + _cb_data.status_data = _current_event; +- _cb_data.data = &_retry_count; ++ _cb_data.data = &_retry_cb_data; + _cb_data.error = NSAPI_ERROR_OK; + send_event_cb(CellularStateRetryEvent); + +@@ -680,8 +682,11 @@ void CellularStateMachine::send_event_cb(cellular_connection_status_t status) + + void CellularStateMachine::change_timeout(const std::chrono::duration &timeout) + { ++ _timeout_cb_data.timeout = timeout.count(); ++ _timeout_cb_data.state = _state; ++ + _cb_data.status_data = _current_event; +- _cb_data.data = &timeout; ++ _cb_data.data = &_timeout_cb_data; + _cb_data.error = NSAPI_ERROR_OK; + // event callback is a preferred method to communicate to CellularDevice, + // for example calling CellularDevice::set_timeout would call back to this class +-- +2.42.0 + diff --git a/patches/0226-Gemalto-Cinterion-improve-trace-output.patch b/patches/0226-Gemalto-Cinterion-improve-trace-output.patch new file mode 100644 index 000000000..4bcc28293 --- /dev/null +++ b/patches/0226-Gemalto-Cinterion-improve-trace-output.patch @@ -0,0 +1,68 @@ +From aa22f048ae886adcc032ba2fefc7e1f90aa2b693 Mon Sep 17 00:00:00 2001 +From: pennam +Date: Tue, 21 Nov 2023 14:50:08 +0100 +Subject: [PATCH 226/226] Gemalto Cinterion: improve trace output + + * Do not flood serial monitor with tr_info prints + * Align usage of "\n" +--- + .../CINTERION/GEMALTO_CINTERION_CellularContext.cpp | 2 +- + .../GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +index 7ee2c8e53c..d4ae578f09 100644 +--- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp ++++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +@@ -122,7 +122,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularContext::do_user_authentication() + return NSAPI_ERROR_AUTH_FAILURE; + } + } else { +- tr_info("Empty pwd and username fields: no need for authentication\n"); ++ tr_info("Empty pwd and username fields: no need for authentication"); + } + + return NSAPI_ERROR_OK; +diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +index fc2e8985d7..ac2a54282a 100644 +--- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp ++++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +@@ -284,7 +284,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::gethostbyname(const char *host, S + _at.resp_stop(); + if (size > 0) { + //Valid string received +- tr_info("Read %d bytes. Valid string: %s\n", size, ipAddress); ++ tr_info("Read %d bytes. Valid string: %s", size, ipAddress); + // _at.restore_at_timeout(); + if (!address->set_ip_address(ipAddress)) { + _at.unlock(); +@@ -292,7 +292,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::gethostbyname(const char *host, S + } + } else { + //Null string received +- tr_info("Read %d bytes. Null string\n", size); ++ tr_info("Read %d bytes. Null string", size); + return NSAPI_ERROR_NO_ADDRESS; + } + } +@@ -550,7 +550,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell + size = UDP_PACKET_SIZE; + } + +- tr_info("requesting %d bytes\n", size); ++ tr_debug("requesting %d bytes\n", size); + _at.cmd_start_stop("^SISR", "=", "%d%d", socket->id, size); + + sisr_retry: +@@ -574,7 +574,7 @@ sisr_retry: + + nsapi_size_or_error_t len = _at.read_int(); + if (len == 0) { +- tr_warn("Socket %d no data", socket->id); ++ tr_debug("Socket %d no data", socket->id); + _at.resp_stop(); + RESTORE_URCs_AND_RETURN(NSAPI_ERROR_WOULD_BLOCK); + } +-- +2.42.0 + diff --git a/platform.txt b/platform.txt index a8cae2a71..0e7193624 100644 --- a/platform.txt +++ b/platform.txt @@ -204,12 +204,25 @@ tools.adb.upload.params.quiet= tools.adb.upload.pattern="{path}/{cmd}" push "{build.path}/{build.project_name}.elf" "/tmp/arduino/m4-user-sketch.elf" # -# GDB (Debugger) +# Debugger # -# EXPERIMENTAL feature: debug.pattern -# - this is alpha and may be subject to change without notice tools.gdb.path={runtime.tools.arm-none-eabi-gcc-7-2017q4.path}/bin/ tools.gdb.cmd=arm-none-eabi-gdb tools.gdb.cmd.windows=arm-none-eabi-gdb.exe -tools.gdb.debug.pattern="{path}/{cmd}" --interpreter=mi2 -ex "set pagination off" --baud 115200 -ex "set target-charset ASCII" -ex "target remote {debug.port}" {build.path}/{build.project_name}.elf + +debug.executable={build.path}/{build.project_name}.elf +debug.toolchain=gcc +debug.toolchain.path={runtime.tools.arm-none-eabi-gcc-7-2017q4.path}/bin/ +debug.toolchain.prefix=arm-none-eabi +debug.server=openocd +debug.server.openocd.path={runtime.tools.openocd-0.11.0-arduino2.path}/bin/openocd +debug.server.openocd.scripts_dir={runtime.tools.openocd-0.11.0-arduino2.path}/share/openocd/scripts/ + +debug.cortex-debug.custom.postAttachCommands.0=set remote hardware-watchpoint-limit 2 +debug.cortex-debug.custom.postAttachCommands.1=monitor reset halt +debug.cortex-debug.custom.postAttachCommands.2=monitor gdb_sync +debug.cortex-debug.custom.postAttachCommands.3=c +debug.cortex-debug.custom.overrideRestartCommands.0=monitor reset halt +debug.cortex-debug.custom.overrideRestartCommands.1=monitor gdb_sync +debug.cortex-debug.custom.overrideRestartCommands.2=c diff --git a/portenta.variables b/portenta.variables index 8ae4b3f2b..2c07268fb 100644 --- a/portenta.variables +++ b/portenta.variables @@ -1,5 +1,5 @@ export FLAVOUR="portenta" -export VARIANTS=("PORTENTA_H7_M7 PORTENTA_H7_M4 PORTENTA_X8") +export VARIANTS=("PORTENTA_H7_M7 GENERIC_STM32H747_M4 PORTENTA_X8") export FQBNS=("envie_m7 portenta_x8") export LIBRARIES=("doom Ethernet MRI Portenta_SDRAM SPI WiFi ea_malloc openamp_arduino STM32H747_System ThreadDebug Himax_HM01B0 Himax_HM0360 PDM Arduino_H7_Video USBAudio KernelDebug Portenta_Audio RPC USBHID Wire Portenta_lvgl Camera rpclib USBHOST mbed-memory-status Portenta_SDCARD Scheduler USBMSD USBMIDI SocketWrapper GSM GPS MCUboot Arduino_CAN") export BOOTLOADERS=("PORTENTA_H7") diff --git a/programmers.txt b/programmers.txt index d3f75cea1..06ecd7f09 100644 --- a/programmers.txt +++ b/programmers.txt @@ -5,6 +5,8 @@ cmsis-dap.program.protocol= cmsis-dap.program.tool=openocd cmsis-dap.program.tool.default=openocd cmsis-dap.program.extra_params= +cmsis-dap.programmer.protocol=cmsis-dap +cmsis-dap.programmer.transport_script={runtime.platform.path}/debugger/select_swd.cfg stlink.name=STMicroelectronics STLINK stlink.communication=USB @@ -12,4 +14,25 @@ stlink.protocol= stlink.program.protocol= stlink.program.tool=openocd stlink.program.tool.default=openocd -stlink.program.extra_params= \ No newline at end of file +stlink.program.extra_params= +stlink.programmer.protocol=stlink +stlink.programmer.transport_script={runtime.platform.path}/debugger/select_hla.cfg + +jlink.name=JLink +jlink.communication=USB +jlink.protocol= +jlink.program.protocol= +jlink.program.tool=openocd +jlink.program.tool.default=openocd +jlink.program.extra_params= +jlink.programmer.protocol=jlink +jlink.programmer.transport_script={runtime.platform.path}/debugger/select_swd.cfg + +blackmagic.name=BlackMagic +blackmagic.communication=USB +blackmagic.protocol= +blackmagic.program.protocol= +blackmagic.program.tool= +blackmagic.program.tool.default= +blackmagic.program.extra_params= +blackmagic.debug.server=blackmagic diff --git a/svd/STM32H747_CM4.svd b/svd/STM32H747_CM4.svd new file mode 100644 index 000000000..e65915289 --- /dev/null +++ b/svd/STM32H747_CM4.svd @@ -0,0 +1,109474 @@ + + + STM32H747_CM4 + 1.2 + STM32H747_CM4 + + CM4 + r0p1 + little + true + true + 4 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + COMP1 + COMP1 + COMP1 + 0x58003800 + + 0x0 + 0x400 + registers + + + COMP + COMP1 and COMP2 + 137 + + + + SR + SR + Comparator status register + 0x0 + 0x20 + read-only + 0x00000000 + + + C1VAL + COMP channel 1 output status + bit + 0 + 1 + + + C2VAL + COMP channel 2 output status + bit + 1 + 1 + + + C1IF + COMP channel 1 Interrupt + Flag + 16 + 1 + + + C2IF + COMP channel 2 Interrupt + Flag + 17 + 1 + + + + + ICFR + ICFR + Comparator interrupt clear flag + register + 0x4 + 0x20 + write-only + 0x00000000 + + + CC1IF + Clear COMP channel 1 Interrupt + Flag + 16 + 1 + + + CC2IF + Clear COMP channel 2 Interrupt + Flag + 17 + 1 + + + + + OR + OR + Comparator option register + 0x8 + 0x20 + read-write + 0x00000000 + + + AFOP + Selection of source for alternate + function of output ports + 0 + 11 + + + OR + Option Register + 11 + 21 + + + + + CFGR1 + CFGR1 + Comparator configuration register + 1 + 0xC + 0x20 + read-write + 0x00000000 + + + EN + COMP channel 1 enable bit + 0 + 1 + + + BRGEN + Scaler bridge enable + 1 + 1 + + + SCALEN + Voltage scaler enable bit + 2 + 1 + + + POLARITY + COMP channel 1 polarity selection + bit + 3 + 1 + + + ITEN + COMP channel 1 interrupt + enable + 6 + 1 + + + HYST + COMP channel 1 hysteresis selection + bits + 8 + 2 + + + PWRMODE + Power Mode of the COMP channel + 1 + 12 + 2 + + + INMSEL + COMP channel 1 inverting input selection + field + 16 + 3 + + + INPSEL + COMP channel 1 non-inverting input + selection bit + 20 + 1 + + + BLANKING + COMP channel 1 blanking source selection + bits + 24 + 4 + + + LOCK + Lock bit + 31 + 1 + + + + + CFGR2 + CFGR2 + Comparator configuration register + 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + EN + COMP channel 1 enable bit + 0 + 1 + + + BRGEN + Scaler bridge enable + 1 + 1 + + + SCALEN + Voltage scaler enable bit + 2 + 1 + + + POLARITY + COMP channel 1 polarity selection + bit + 3 + 1 + + + WINMODE + Window comparator mode selection + bit + 4 + 1 + + + ITEN + COMP channel 1 interrupt + enable + 6 + 1 + + + HYST + COMP channel 1 hysteresis selection + bits + 8 + 2 + + + PWRMODE + Power Mode of the COMP channel + 1 + 12 + 2 + + + INMSEL + COMP channel 1 inverting input selection + field + 16 + 3 + + + INPSEL + COMP channel 1 non-inverting input + selection bit + 20 + 1 + + + BLANKING + COMP channel 1 blanking source selection + bits + 24 + 4 + + + LOCK + Lock bit + 31 + 1 + + + + + + + CRS + CRS + CRS + 0x40008400 + + 0x0 + 0x400 + registers + + + CRS + Clock Recovery System globa + 144 + + + + CR + CR + CRS control register + 0x0 + 0x20 + 0x00002000 + + + SYNCOKIE + SYNC event OK interrupt + enable + 0 + 1 + read-write + + + SYNCWARNIE + SYNC warning interrupt + enable + 1 + 1 + read-write + + + ERRIE + Synchronization or trimming error + interrupt enable + 2 + 1 + read-write + + + ESYNCIE + Expected SYNC interrupt + enable + 3 + 1 + read-write + + + CEN + Frequency error counter enable This bit + enables the oscillator clock for the frequency error + counter. When this bit is set, the CRS_CFGR register + is write-protected and cannot be + modified. + 5 + 1 + read-write + + + AUTOTRIMEN + Automatic trimming enable This bit + enables the automatic hardware adjustment of TRIM + bits according to the measured frequency error + between two SYNC events. If this bit is set, the TRIM + bits are read-only. The TRIM value can be adjusted by + hardware by one or two steps at a time, depending on + the measured frequency error value. Refer to + Section7.3.4: Frequency error evaluation and + automatic trimming for more details. + 6 + 1 + read-write + + + SWSYNC + Generate software SYNC event This bit is + set by software in order to generate a software SYNC + event. It is automatically cleared by + hardware. + 7 + 1 + read-only + + + TRIM + HSI48 oscillator smooth trimming These + bits provide a user-programmable trimming value to + the HSI48 oscillator. They can be programmed to + adjust to variations in voltage and temperature that + influence the frequency of the HSI48. The default + value is 32, which corresponds to the middle of the + trimming interval. The trimming step is around 67 kHz + between two consecutive TRIM steps. A higher TRIM + value corresponds to a higher output frequency. When + the AUTOTRIMEN bit is set, this field is controlled + by hardware and is read-only. + 8 + 6 + read-write + + + + + CFGR + CFGR + This register can be written only when the + frequency error counter is disabled (CEN bit is cleared + in CRS_CR). When the counter is enabled, this register is + write-protected. + 0x4 + 0x20 + read-write + 0x2022BB7F + + + RELOAD + Counter reload value RELOAD is the value + to be loaded in the frequency error counter with each + SYNC event. Refer to Section7.3.3: Frequency error + measurement for more details about counter + behavior. + 0 + 16 + + + FELIM + Frequency error limit FELIM contains the + value to be used to evaluate the captured frequency + error value latched in the FECAP[15:0] bits of the + CRS_ISR register. Refer to Section7.3.4: Frequency + error evaluation and automatic trimming for more + details about FECAP evaluation. + 16 + 8 + + + SYNCDIV + SYNC divider These bits are set and + cleared by software to control the division factor of + the SYNC signal. + 24 + 3 + + + SYNCSRC + SYNC signal source selection These bits + are set and cleared by software to select the SYNC + signal source. Note: When using USB LPM (Link Power + Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. + No SYNC signal will therefore be provided to the CRS + to calibrate the HSI48 on the run. To guarantee the + required clock precision after waking up from Sleep + mode, the LSE or reference clock on the GPIOs should + be used as SYNC signal. + 28 + 2 + + + SYNCPOL + SYNC polarity selection This bit is set + and cleared by software to select the input polarity + for the SYNC signal source. + 31 + 1 + + + + + ISR + ISR + CRS interrupt and status + register + 0x8 + 0x20 + read-only + 0x00000000 + + + SYNCOKF + SYNC event OK flag This flag is set by + hardware when the measured frequency error is smaller + than FELIM * 3. This means that either no adjustment + of the TRIM value is needed or that an adjustment by + one trimming step is enough to compensate the + frequency error. An interrupt is generated if the + SYNCOKIE bit is set in the CRS_CR register. It is + cleared by software by setting the SYNCOKC bit in the + CRS_ICR register. + 0 + 1 + + + SYNCWARNF + SYNC warning flag This flag is set by + hardware when the measured frequency error is greater + than or equal to FELIM * 3, but smaller than FELIM * + 128. This means that to compensate the frequency + error, the TRIM value must be adjusted by two steps + or more. An interrupt is generated if the SYNCWARNIE + bit is set in the CRS_CR register. It is cleared by + software by setting the SYNCWARNC bit in the CRS_ICR + register. + 1 + 1 + + + ERRF + Error flag This flag is set by hardware + in case of any synchronization or trimming error. It + is the logical OR of the TRIMOVF, SYNCMISS and + SYNCERR bits. An interrupt is generated if the ERRIE + bit is set in the CRS_CR register. It is cleared by + software in reaction to setting the ERRC bit in the + CRS_ICR register, which clears the TRIMOVF, SYNCMISS + and SYNCERR bits. + 2 + 1 + + + ESYNCF + Expected SYNC flag This flag is set by + hardware when the frequency error counter reached a + zero value. An interrupt is generated if the ESYNCIE + bit is set in the CRS_CR register. It is cleared by + software by setting the ESYNCC bit in the CRS_ICR + register. + 3 + 1 + + + SYNCERR + SYNC error This flag is set by hardware + when the SYNC pulse arrives before the ESYNC event + and the measured frequency error is greater than or + equal to FELIM * 128. This means that the frequency + error is too big (internal frequency too low) to be + compensated by adjusting the TRIM value, and that + some other action should be taken. An interrupt is + generated if the ERRIE bit is set in the CRS_CR + register. It is cleared by software by setting the + ERRC bit in the CRS_ICR register. + 8 + 1 + + + SYNCMISS + SYNC missed This flag is set by hardware + when the frequency error counter reached value FELIM + * 128 and no SYNC was detected, meaning either that a + SYNC pulse was missed or that the frequency error is + too big (internal frequency too high) to be + compensated by adjusting the TRIM value, and that + some other action should be taken. At this point, the + frequency error counter is stopped (waiting for a + next SYNC) and an interrupt is generated if the ERRIE + bit is set in the CRS_CR register. It is cleared by + software by setting the ERRC bit in the CRS_ICR + register. + 9 + 1 + + + TRIMOVF + Trimming overflow or underflow This flag + is set by hardware when the automatic trimming tries + to over- or under-flow the TRIM value. An interrupt + is generated if the ERRIE bit is set in the CRS_CR + register. It is cleared by software by setting the + ERRC bit in the CRS_ICR register. + 10 + 1 + + + FEDIR + Frequency error direction FEDIR is the + counting direction of the frequency error counter + latched in the time of the last SYNC event. It shows + whether the actual frequency is below or above the + target. + 15 + 1 + + + FECAP + Frequency error capture FECAP is the + frequency error counter value latched in the time of + the last SYNC event. Refer to Section7.3.4: Frequency + error evaluation and automatic trimming for more + details about FECAP usage. + 16 + 16 + + + + + ICR + ICR + CRS interrupt flag clear + register + 0xC + 0x20 + read-write + 0x00000000 + + + SYNCOKC + SYNC event OK clear flag Writing 1 to + this bit clears the SYNCOKF flag in the CRS_ISR + register. + 0 + 1 + + + SYNCWARNC + SYNC warning clear flag Writing 1 to + this bit clears the SYNCWARNF flag in the CRS_ISR + register. + 1 + 1 + + + ERRC + Error clear flag Writing 1 to this bit + clears TRIMOVF, SYNCMISS and SYNCERR bits and + consequently also the ERRF flag in the CRS_ISR + register. + 2 + 1 + + + ESYNCC + Expected SYNC clear flag Writing 1 to + this bit clears the ESYNCF flag in the CRS_ISR + register. + 3 + 1 + + + + + + + DAC + DAC + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CR + CR + DAC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable This bit is set and + cleared by software to enable/disable DAC + channel1. + 0 + 1 + + + TEN1 + DAC channel1 trigger + enable + 1 + 1 + + + TSEL1 + DAC channel1 trigger selection These + bits select the external event used to trigger DAC + channel1. Note: Only used if bit TEN1 = 1 (DAC + channel1 trigger enabled). + 2 + 3 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable These bits are set and cleared by + software. Note: Only used if bit TEN1 = 1 (DAC + channel1 trigger enabled). + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude selector + These bits are written by software to select mask in + wave generation mode or amplitude in triangle + generation mode. = 1011: Unmask bits[11:0] of LFSR/ + triangle amplitude equal to 4095 + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable This bit is set + and cleared by software. + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable This bit is set and cleared by + software. + 13 + 1 + + + CEN1 + DAC Channel 1 calibration enable This + bit is set and cleared by software to enable/disable + DAC channel 1 calibration, it can be written only if + bit EN1=0 into DAC_CR (the calibration mode can be + entered/exit only when the DAC channel is disabled) + Otherwise, the write operation is + ignored. + 14 + 1 + + + EN2 + DAC channel2 enable This bit is set and + cleared by software to enable/disable DAC + channel2. + 16 + 1 + + + TEN2 + DAC channel2 trigger + enable + 17 + 1 + + + TSEL2 + DAC channel2 trigger selection These + bits select the external event used to trigger DAC + channel2 Note: Only used if bit TEN2 = 1 (DAC + channel2 trigger enabled). + 18 + 3 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable These bits are set/reset by + software. 1x: Triangle wave generation enabled Note: + Only used if bit TEN2 = 1 (DAC channel2 trigger + enabled) + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude selector + These bits are written by software to select mask in + wave generation mode or amplitude in triangle + generation mode. = 1011: Unmask bits[11:0] of LFSR/ + triangle amplitude equal to 4095 + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable This bit is set + and cleared by software. + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable This bit is set and cleared by + software. + 29 + 1 + + + CEN2 + DAC Channel 2 calibration enable This + bit is set and cleared by software to enable/disable + DAC channel 2 calibration, it can be written only if + bit EN2=0 into DAC_CR (the calibration mode can be + entered/exit only when the DAC channel is disabled) + Otherwise, the write operation is + ignored. + 30 + 1 + + + + + SWTRGR + SWTRGR + DAC software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software trigger This bit + is set by software to trigger the DAC in software + trigger mode. Note: This bit is cleared by hardware + (one APB1 clock cycle later) once the DAC_DHR1 + register value has been loaded into the DAC_DOR1 + register. + 0 + 1 + + + SWTRIG2 + DAC channel2 software trigger This bit + is set by software to trigger the DAC in software + trigger mode. Note: This bit is cleared by hardware + (one APB1 clock cycle later) once the DAC_DHR2 + register value has been loaded into the DAC_DOR2 + register. + 1 + 1 + + + + + DHR12R1 + DHR12R1 + DAC channel1 12-bit right-aligned data + holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 0 + 12 + + + + + DHR12L1 + DHR12L1 + DAC channel1 12-bit left aligned data + holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 4 + 12 + + + + + DHR8R1 + DHR8R1 + DAC channel1 8-bit right aligned data + holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel1. + 0 + 8 + + + + + DHR12R2 + DHR12R2 + DAC channel2 12-bit right aligned data + holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel2. + 0 + 12 + + + + + DHR12L2 + DHR12L2 + DAC channel2 12-bit left aligned data + holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + These bits are written by software which specify + 12-bit data for DAC channel2. + 4 + 12 + + + + + DHR8R2 + DHR8R2 + DAC channel2 8-bit right-aligned data + holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel2. + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel2. + 16 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel2. + 20 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel1. + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel2. + 8 + 8 + + + + + DOR1 + DOR1 + DAC channel1 data output + register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output These bits are + read-only, they contain data output for DAC + channel1. + 0 + 12 + + + + + DOR2 + DOR2 + DAC channel2 data output + register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output These bits are + read-only, they contain data output for DAC + channel2. + 0 + 12 + + + + + SR + SR + DAC status register + 0x34 + 0x20 + 0x00000000 + + + DMAUDR1 + DAC channel1 DMA underrun flag This bit + is set by hardware and cleared by software (by + writing it to 1). + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset status + This bit is set and cleared by hardware + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time + flag This bit is systematically set just after Sample + & Hold mode enable and is set each time the + software writes the register DAC_SHSR1, It is cleared + by hardware when the write operation of DAC_SHSR1 is + complete. (It takes about 3LSI periods of + synchronization). + 15 + 1 + read-only + + + DMAUDR2 + DAC channel2 DMA underrun flag This bit + is set by hardware and cleared by software (by + writing it to 1). + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset status + This bit is set and cleared by hardware + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time + flag This bit is systematically set just after Sample + & Hold mode enable and is set each time the + software writes the register DAC_SHSR2, It is cleared + by hardware when the write operation of DAC_SHSR2 is + complete. (It takes about 3 LSI periods of + synchronization). + 31 + 1 + read-only + + + + + CCR + CCR + DAC calibration control + register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming + value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming + value + 16 + 5 + + + + + MCR + MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode These bits can be + written only when the DAC is disabled and not in the + calibration mode (when bit EN1=0 and bit CEN1 =0 in + the DAC_CR register). If EN1=1 or CEN1 =1 the write + operation is ignored. They can be set and cleared by + software to select the DAC Channel 1 mode: DAC + Channel 1 in normal Mode DAC Channel 1 in sample + &amp; hold mode + 0 + 3 + + + MODE2 + DAC Channel 2 mode These bits can be + written only when the DAC is disabled and not in the + calibration mode (when bit EN2=0 and bit CEN2 =0 in + the DAC_CR register). If EN2=1 or CEN2 =1 the write + operation is ignored. They can be set and cleared by + software to select the DAC Channel 2 mode: DAC + Channel 2 in normal Mode DAC Channel 2 in sample + &amp; hold mode + 16 + 3 + + + + + SHSR1 + SHSR1 + DAC Sample and Hold sample time register + 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time (only valid in + sample &amp; hold mode) These bits can be written + when the DAC channel1 is disabled or also during + normal operation. in the latter case, the write can + be done only when BWSTx of DAC_SR register is low, If + BWSTx=1, the write operation is + ignored. + 0 + 10 + + + + + SHSR2 + SHSR2 + DAC Sample and Hold sample time register + 2 + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time (only valid in + sample &amp; hold mode) These bits can be written + when the DAC channel2 is disabled or also during + normal operation. in the latter case, the write can + be done only when BWSTx of DAC_SR register is low, if + BWSTx=1, the write operation is + ignored. + 0 + 10 + + + + + SHHR + SHHR + DAC Sample and Hold hold time + register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time (only valid in + sample &amp; hold mode) Hold time= (THOLD[9:0]) x + T LSI + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time (only valid in + sample &amp; hold mode). Hold time= (THOLD[9:0]) + x T LSI + 16 + 10 + + + + + SHRR + SHRR + DAC Sample and Hold refresh time + register + 0x4C + 0x20 + read-write + 0x00010001 + + + TREFRESH1 + DAC Channel 1 refresh Time (only valid + in sample &amp; hold mode) Refresh time= + (TREFRESH[7:0]) x T LSI + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time (only valid + in sample &amp; hold mode) Refresh time= + (TREFRESH[7:0]) x T LSI + 16 + 8 + + + + + + + BDMA + BDMA + BDMA + 0x58025400 + + 0x0 + 0x400 + registers + + + BDMA_CH1 + BDMA channel 1 interrupt + 129 + + + BDMA_CH2 + BDMA channel 2 interrupt + 130 + + + BDMA_CH3 + BDMA channel 3 interrupt + 131 + + + BDMA_CH4 + BDMA channel 4 interrupt + 132 + + + BDMA_CH5 + BDMA channel 5 interrupt + 133 + + + BDMA_CH6 + BDMA channel 6 interrupt + 134 + + + BDMA_CH7 + BDMA channel 7 interrupt + 135 + + + BDMA_CH8 + BDMA channel 8 interrupt + 136 + + + + ISR + ISR + DMA interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 0 + 1 + + + TCIF1 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 1 + 1 + + + HTIF1 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 2 + 1 + + + TEIF1 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 3 + 1 + + + GIF2 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 4 + 1 + + + TCIF2 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 5 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 6 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 7 + 1 + + + GIF3 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 8 + 1 + + + TCIF3 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 9 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 10 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 11 + 1 + + + GIF4 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 12 + 1 + + + TCIF4 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 13 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 14 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 15 + 1 + + + GIF5 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 16 + 1 + + + TCIF5 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 17 + 1 + + + HTIF5 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 18 + 1 + + + TEIF5 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 19 + 1 + + + GIF6 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 20 + 1 + + + TCIF6 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 21 + 1 + + + HTIF6 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 22 + 1 + + + TEIF6 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 23 + 1 + + + GIF7 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 24 + 1 + + + TCIF7 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 25 + 1 + + + HTIF7 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 26 + 1 + + + TEIF7 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 27 + 1 + + + GIF8 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 28 + 1 + + + TCIF8 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 29 + 1 + + + HTIF8 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 30 + 1 + + + TEIF8 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 31 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear + register + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel x global interrupt clear This + bit is set and cleared by software. + 0 + 1 + + + CTCIF1 + Channel x transfer complete clear This + bit is set and cleared by software. + 1 + 1 + + + CHTIF1 + Channel x half transfer clear This bit + is set and cleared by software. + 2 + 1 + + + CTEIF1 + Channel x transfer error clear This bit + is set and cleared by software. + 3 + 1 + + + CGIF2 + Channel x global interrupt clear This + bit is set and cleared by software. + 4 + 1 + + + CTCIF2 + Channel x transfer complete clear This + bit is set and cleared by software. + 5 + 1 + + + CHTIF2 + Channel x half transfer clear This bit + is set and cleared by software. + 6 + 1 + + + CTEIF2 + Channel x transfer error clear This bit + is set and cleared by software. + 7 + 1 + + + CGIF3 + Channel x global interrupt clear This + bit is set and cleared by software. + 8 + 1 + + + CTCIF3 + Channel x transfer complete clear This + bit is set and cleared by software. + 9 + 1 + + + CHTIF3 + Channel x half transfer clear This bit + is set and cleared by software. + 10 + 1 + + + CTEIF3 + Channel x transfer error clear This bit + is set and cleared by software. + 11 + 1 + + + CGIF4 + Channel x global interrupt clear This + bit is set and cleared by software. + 12 + 1 + + + CTCIF4 + Channel x transfer complete clear This + bit is set and cleared by software. + 13 + 1 + + + CHTIF4 + Channel x half transfer clear This bit + is set and cleared by software. + 14 + 1 + + + CTEIF4 + Channel x transfer error clear This bit + is set and cleared by software. + 15 + 1 + + + CGIF5 + Channel x global interrupt clear This + bit is set and cleared by software. + 16 + 1 + + + CTCIF5 + Channel x transfer complete clear This + bit is set and cleared by software. + 17 + 1 + + + CHTIF5 + Channel x half transfer clear This bit + is set and cleared by software. + 18 + 1 + + + CTEIF5 + Channel x transfer error clear This bit + is set and cleared by software. + 19 + 1 + + + CGIF6 + Channel x global interrupt clear This + bit is set and cleared by software. + 20 + 1 + + + CTCIF6 + Channel x transfer complete clear This + bit is set and cleared by software. + 21 + 1 + + + CHTIF6 + Channel x half transfer clear This bit + is set and cleared by software. + 22 + 1 + + + CTEIF6 + Channel x transfer error clear This bit + is set and cleared by software. + 23 + 1 + + + CGIF7 + Channel x global interrupt clear This + bit is set and cleared by software. + 24 + 1 + + + CTCIF7 + Channel x transfer complete clear This + bit is set and cleared by software. + 25 + 1 + + + CHTIF7 + Channel x half transfer clear This bit + is set and cleared by software. + 26 + 1 + + + CTEIF7 + Channel x transfer error clear This bit + is set and cleared by software. + 27 + 1 + + + CGIF8 + Channel x global interrupt clear This + bit is set and cleared by software. + 28 + 1 + + + CTCIF8 + Channel x transfer complete clear This + bit is set and cleared by software. + 29 + 1 + + + CHTIF8 + Channel x half transfer clear This bit + is set and cleared by software. + 30 + 1 + + + CTEIF8 + Channel x transfer error clear This bit + is set and cleared by software. + 31 + 1 + + + + + CCR1 + CCR1 + DMA channel x configuration + register + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel x number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR1 + CPAR1 + This register must not be written when the + channel is enabled. + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR1 + CMAR1 + This register must not be written when the + channel is enabled. + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel x configuration + register + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel x number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR2 + CPAR2 + This register must not be written when the + channel is enabled. + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR2 + CMAR2 + This register must not be written when the + channel is enabled. + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel x configuration + register + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel x number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR3 + CPAR3 + This register must not be written when the + channel is enabled. + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR3 + CMAR3 + This register must not be written when the + channel is enabled. + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR4 + CCR4 + DMA channel x configuration + register + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR4 + CNDTR4 + DMA channel x number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR4 + CPAR4 + This register must not be written when the + channel is enabled. + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR4 + CMAR4 + This register must not be written when the + channel is enabled. + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR5 + CCR5 + DMA channel x configuration + register + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR5 + CNDTR5 + DMA channel x number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR5 + CPAR5 + This register must not be written when the + channel is enabled. + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR5 + CMAR5 + This register must not be written when the + channel is enabled. + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR6 + CCR6 + DMA channel x configuration + register + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR6 + CNDTR6 + DMA channel x number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR6 + CPAR6 + This register must not be written when the + channel is enabled. + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR6 + CMAR6 + This register must not be written when the + channel is enabled. + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR7 + CCR7 + DMA channel x configuration + register + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR7 + CNDTR7 + DMA channel x number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR7 + CPAR7 + This register must not be written when the + channel is enabled. + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR7 + CMAR7 + This register must not be written when the + channel is enabled. + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR8 + CCR8 + DMA channel x configuration + register + 0x94 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR8 + CNDTR8 + DMA channel x number of data + register + 0x98 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR8 + CPAR8 + This register must not be written when the + channel is enabled. + 0x9C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR8 + CMAR8 + This register must not be written when the + channel is enabled. + 0xA0 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + + + DMA2D + DMA2D + DMA2D + 0x52001000 + + 0x0 + 0x400 + registers + + + DMA2D + DMA2D global interrupt + 90 + + + + CR + CR + DMA2D control register + 0x0 + 0x20 + read-write + 0x00000000 + + + START + Start This bit can be used to launch the + DMA2D according to the parameters loaded in the + various configuration registers + 0 + 1 + + + SUSP + Suspend This bit can be used to suspend + the current transfer. This bit is set and reset by + software. It is automatically reset by hardware when + the START bit is reset. + 1 + 1 + + + ABORT + Abort This bit can be used to abort the + current transfer. This bit is set by software and is + automatically reset by hardware when the START bit is + reset. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 8 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 9 + 1 + + + TWIE + Transfer watermark interrupt enable This + bit is set and cleared by software. + 10 + 1 + + + CAEIE + CLUT access error interrupt enable This + bit is set and cleared by software. + 11 + 1 + + + CTCIE + CLUT transfer complete interrupt enable + This bit is set and cleared by + software. + 12 + 1 + + + CEIE + Configuration Error Interrupt Enable + This bit is set and cleared by + software. + 13 + 1 + + + MODE + DMA2D mode This bit is set and cleared + by software. It cannot be modified while a transfer + is ongoing. + 16 + 2 + + + + + ISR + ISR + DMA2D Interrupt Status + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + TEIF + Transfer error interrupt flag This bit + is set when an error occurs during a DMA transfer + (data transfer or automatic CLUT + loading). + 0 + 1 + + + TCIF + Transfer complete interrupt flag This + bit is set when a DMA2D transfer operation is + complete (data transfer only). + 1 + 1 + + + TWIF + Transfer watermark interrupt flag This + bit is set when the last pixel of the watermarked + line has been transferred. + 2 + 1 + + + CAEIF + CLUT access error interrupt flag This + bit is set when the CPU accesses the CLUT while the + CLUT is being automatically copied from a system + memory to the internal DMA2D. + 3 + 1 + + + CTCIF + CLUT transfer complete interrupt flag + This bit is set when the CLUT copy from a system + memory area to the internal DMA2D memory is + complete. + 4 + 1 + + + CEIF + Configuration error interrupt flag This + bit is set when the START bit of DMA2D_CR, + DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong + configuration has been programmed. + 5 + 1 + + + + + IFCR + IFCR + DMA2D interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTEIF + Clear Transfer error interrupt flag + Programming this bit to 1 clears the TEIF flag in the + DMA2D_ISR register + 0 + 1 + + + CTCIF + Clear transfer complete interrupt flag + Programming this bit to 1 clears the TCIF flag in the + DMA2D_ISR register + 1 + 1 + + + CTWIF + Clear transfer watermark interrupt flag + Programming this bit to 1 clears the TWIF flag in the + DMA2D_ISR register + 2 + 1 + + + CAECIF + Clear CLUT access error interrupt flag + Programming this bit to 1 clears the CAEIF flag in + the DMA2D_ISR register + 3 + 1 + + + CCTCIF + Clear CLUT transfer complete interrupt + flag Programming this bit to 1 clears the CTCIF flag + in the DMA2D_ISR register + 4 + 1 + + + CCEIF + Clear configuration error interrupt flag + Programming this bit to 1 clears the CEIF flag in the + DMA2D_ISR register + 5 + 1 + + + + + FGMAR + FGMAR + DMA2D foreground memory address + register + 0xC + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the foreground image. This register can only be + written when data transfers are disabled. Once the + data transfer has started, this register is + read-only. The address alignment must match the image + format selected e.g. a 32-bit per pixel format must + be 32-bit aligned, a 16-bit per pixel format must be + 16-bit aligned and a 4-bit per pixel format must be + 8-bit aligned. + 0 + 32 + + + + + FGOR + FGOR + DMA2D foreground offset + register + 0x10 + 0x20 + read-write + 0x00000000 + + + LO + Line offset Line offset used for the + foreground expressed in pixel. This value is used to + generate the address. It is added at the end of each + line to determine the starting address of the next + line. These bits can only be written when data + transfers are disabled. Once a data transfer has + started, they become read-only. If the image format + is 4-bit per pixel, the line offset must be + even. + 0 + 14 + + + + + BGMAR + BGMAR + DMA2D background memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the background image. This register can only be + written when data transfers are disabled. Once a data + transfer has started, this register is read-only. The + address alignment must match the image format + selected e.g. a 32-bit per pixel format must be + 32-bit aligned, a 16-bit per pixel format must be + 16-bit aligned and a 4-bit per pixel format must be + 8-bit aligned. + 0 + 32 + + + + + BGOR + BGOR + DMA2D background offset + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LO + Line offset Line offset used for the + background image (expressed in pixel). This value is + used for the address generation. It is added at the + end of each line to determine the starting address of + the next line. These bits can only be written when + data transfers are disabled. Once data transfer has + started, they become read-only. If the image format + is 4-bit per pixel, the line offset must be + even. + 0 + 14 + + + + + FGPFCCR + FGPFCCR + DMA2D foreground PFC control + register + 0x1C + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits defines the color + format of the foreground image. They can only be + written when data transfers are disabled. Once the + transfer has started, they are read-only. others: + meaningless + 0 + 4 + + + CCM + CLUT color mode This bit defines the + color format of the CLUT. It can only be written when + the transfer is disabled. Once the CLUT transfer has + started, this bit is read-only. + 4 + 1 + + + START + Start This bit can be set to start the + automatic loading of the CLUT. It is automatically + reset: ** at the end of the transfer ** when the + transfer is aborted by the user application by + setting the ABORT bit in DMA2D_CR ** when a transfer + error occurs ** when the transfer has not started due + to a configuration error or another transfer + operation already ongoing (data transfer or automatic + background CLUT transfer). + 5 + 1 + + + CS + CLUT size These bits define the size of + the CLUT used for the foreground image. Once the CLUT + transfer has started, this field is read-only. The + number of CLUT entries is equal to CS[7:0] + + 1. + 8 + 8 + + + AM + Alpha mode These bits select the alpha + channel value to be used for the foreground image. + They can only be written data the transfer are + disabled. Once the transfer has started, they become + read-only. other configurations are + meaningless + 16 + 2 + + + CSS + Chroma Sub-Sampling These bits define + the chroma sub-sampling mode for YCbCr color mode. + Once the transfer has started, these bits are + read-only. others: meaningless + 18 + 2 + + + AI + Alpha Inverted This bit inverts the + alpha value. Once the transfer has started, this bit + is read-only. + 20 + 1 + + + RBS + Red Blue Swap This bit allows to swap + the R &amp; B to support BGR or ABGR color + formats. Once the transfer has started, this bit is + read-only. + 21 + 1 + + + ALPHA + Alpha value These bits define a fixed + alpha channel value which can replace the original + alpha value or be multiplied by the original alpha + value according to the alpha mode selected through + the AM[1:0] bits. These bits can only be written when + data transfers are disabled. Once a transfer has + started, they become read-only. + 24 + 8 + + + + + FGCOLR + FGCOLR + DMA2D foreground color + register + 0x20 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits defines the blue + value for the A4 or A8 mode of the foreground image. + They can only be written when data transfers are + disabled. Once the transfer has started, They are + read-only. + 0 + 8 + + + GREEN + Green Value These bits defines the green + value for the A4 or A8 mode of the foreground image. + They can only be written when data transfers are + disabled. Once the transfer has started, They are + read-only. + 8 + 8 + + + RED + Red Value These bits defines the red + value for the A4 or A8 mode of the foreground image. + They can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 16 + 8 + + + + + BGPFCCR + BGPFCCR + DMA2D background PFC control + register + 0x24 + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits define the color + format of the foreground image. These bits can only + be written when data transfers are disabled. Once the + transfer has started, they are read-only. others: + meaningless + 0 + 4 + + + CCM + CLUT Color mode These bits define the + color format of the CLUT. This register can only be + written when the transfer is disabled. Once the CLUT + transfer has started, this bit is + read-only. + 4 + 1 + + + START + Start This bit is set to start the + automatic loading of the CLUT. This bit is + automatically reset: ** at the end of the transfer ** + when the transfer is aborted by the user application + by setting the ABORT bit in the DMA2D_CR ** when a + transfer error occurs ** when the transfer has not + started due to a configuration error or another + transfer operation already on going (data transfer or + automatic BackGround CLUT transfer). + 5 + 1 + + + CS + CLUT size These bits define the size of + the CLUT used for the BG. Once the CLUT transfer has + started, this field is read-only. The number of CLUT + entries is equal to CS[7:0] + 1. + 8 + 8 + + + AM + Alpha mode These bits define which alpha + channel value to be used for the background image. + These bits can only be written when data transfers + are disabled. Once the transfer has started, they are + read-only. others: meaningless + 16 + 2 + + + AI + Alpha Inverted This bit inverts the + alpha value. Once the transfer has started, this bit + is read-only. + 20 + 1 + + + RBS + Red Blue Swap This bit allows to swap + the R &amp; B to support BGR or ABGR color + formats. Once the transfer has started, this bit is + read-only. + 21 + 1 + + + ALPHA + Alpha value These bits define a fixed + alpha channel value which can replace the original + alpha value or be multiplied with the original alpha + value according to the alpha mode selected with bits + AM[1: 0]. These bits can only be written when data + transfers are disabled. Once the transfer has + started, they are read-only. + 24 + 8 + + + + + BGCOLR + BGCOLR + DMA2D background color + register + 0x28 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits define the blue + value for the A4 or A8 mode of the background. These + bits can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 0 + 8 + + + GREEN + Green Value These bits define the green + value for the A4 or A8 mode of the background. These + bits can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 8 + 8 + + + RED + Red Value These bits define the red + value for the A4 or A8 mode of the background. These + bits can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 16 + 8 + + + + + FGCMAR + FGCMAR + DMA2D foreground CLUT memory address + register + 0x2C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address Address of the data used + for the CLUT address dedicated to the foreground + image. This register can only be written when no + transfer is ongoing. Once the CLUT transfer has + started, this register is read-only. If the + foreground CLUT format is 32-bit, the address must be + 32-bit aligned. + 0 + 32 + + + + + BGCMAR + BGCMAR + DMA2D background CLUT memory address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the CLUT address dedicated to the background + image. This register can only be written when no + transfer is on going. Once the CLUT transfer has + started, this register is read-only. If the + background CLUT format is 32-bit, the address must be + 32-bit aligned. + 0 + 32 + + + + + OPFCCR + OPFCCR + DMA2D output PFC control + register + 0x34 + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits define the color + format of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are read-only. others: + meaningless + 0 + 3 + + + AI + Alpha Inverted This bit inverts the + alpha value. Once the transfer has started, this bit + is read-only. + 20 + 1 + + + RBS + Red Blue Swap This bit allows to swap + the R &amp; B to support BGR or ABGR color + formats. Once the transfer has started, this bit is + read-only. + 21 + 1 + + + + + OCOLR + OCOLR + DMA2D output color register + 0x38 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits define the blue + value of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 0 + 8 + + + GREEN + Green Value These bits define the green + value of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 8 + 8 + + + RED + Red Value These bits define the red + value of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 16 + 8 + + + ALPHA + Alpha Channel Value These bits define + the alpha channel of the output color. These bits can + only be written when data transfers are disabled. + Once the transfer has started, they are + read-only. + 24 + 8 + + + + + OMAR + OMAR + DMA2D output memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address Address of the data used + for the output FIFO. These bits can only be written + when data transfers are disabled. Once the transfer + has started, they are read-only. The address + alignment must match the image format selected e.g. a + 32-bit per pixel format must be 32-bit aligned and a + 16-bit per pixel format must be 16-bit + aligned. + 0 + 32 + + + + + OOR + OOR + DMA2D output offset register + 0x40 + 0x20 + read-write + 0x00000000 + + + LO + Line Offset Line offset used for the + output (expressed in pixels). This value is used for + the address generation. It is added at the end of + each line to determine the starting address of the + next line. These bits can only be written when data + transfers are disabled. Once the transfer has + started, they are read-only. + 0 + 14 + + + + + NLR + NLR + DMA2D number of line register + 0x44 + 0x20 + read-write + 0x00000000 + + + NL + Number of lines Number of lines of the + area to be transferred. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 0 + 16 + + + PL + Pixel per lines Number of pixels per + lines of the area to be transferred. These bits can + only be written when data transfers are disabled. + Once the transfer has started, they are read-only. If + any of the input image format is 4-bit per pixel, + pixel per lines must be even. + 16 + 14 + + + + + LWR + LWR + DMA2D line watermark register + 0x48 + 0x20 + read-write + 0x00000000 + + + LW + Line watermark These bits allow to + configure the line watermark for interrupt + generation. An interrupt is raised when the last + pixel of the watermarked line has been transferred. + These bits can only be written when data transfers + are disabled. Once the transfer has started, they are + read-only. + 0 + 16 + + + + + AMTCR + AMTCR + DMA2D AXI master timer configuration + register + 0x4C + 0x20 + read-write + 0x00000000 + + + EN + Enable Enables the dead time + functionality. + 0 + 1 + + + DT + Dead Time Dead time value in the AXI + clock cycle inserted between two consecutive accesses + on the AXI master port. These bits represent the + minimum guaranteed number of cycles between two + consecutive AXI accesses. + 8 + 8 + + + + + + + DMAMUX2 + DMAMUX + DMAMUX + 0x58025800 + + 0x0 + 0x400 + registers + + + DMAMUX2_OVR + DMAMUX2 overrun interrupt + 128 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer + channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer + channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer + channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer + channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer + channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer + channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer + channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer + channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x + control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x + control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x + control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x + control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG4CR + RG4CR + DMAMux - DMA request generator channel x + control register + 0x110 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG5CR + RG5CR + DMAMux - DMA request generator channel x + control register + 0x114 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG6CR + RG6CR + DMAMux - DMA request generator channel x + control register + 0x118 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG7CR + RG7CR + DMAMux - DMA request generator channel x + control register + 0x11C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is + set when a trigger event occurs on DMA request + generator channel x, while the DMA request generator + counter value is lower than GNBREQ. The flag is + cleared by writing 1 to the corresponding COFx bit in + DMAMUX_RGCFR register. + 0 + 8 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag + register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon + setting, this bit clears the corresponding overrun + flag OFx in the DMAMUX_RGCSR register. + 0 + 8 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt + channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event + flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt + clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event + flag + 0 + 16 + + + + + + + FMC + FMC + FMC + 0x52004000 + + 0x0 + 0x400 + registers + + + FMC + FMC global interrupt + 48 + + + + BCR1 + BCR1 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x0 + 0x20 + read-write + 0x000030DB + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR1 + BTR1 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BCR2 + BCR2 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x8 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR2 + BTR2 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 1. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BCR3 + BCR3 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x10 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR3 + BTR3 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + &#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BCR4 + BCR4 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x18 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR4 + BTR4 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + &#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + PCR + PCR + NAND Flash control registers + 0x80 + 0x20 + read-write + 0x00000018 + + + PWAITEN + Wait feature enable bit. This bit + enables the Wait feature for the NAND Flash memory + bank: + 1 + 1 + + + PBKEN + NAND Flash memory bank enable bit. This + bit enables the memory bank. Accessing a disabled + memory bank causes an ERROR on AXI bus + 2 + 1 + + + PWID + Data bus width. These bits define the + external memory device width. + 4 + 2 + + + ECCEN + ECC computation logic enable + bit + 6 + 1 + + + TCLR + CLE to RE delay. These bits set time + from CLE low to RE low in number of KCK_FMC clock + cycles. The time is give by the following formula: + t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is + the KCK_FMC clock period Note: Set is MEMSET or + ATTSET according to the addressed + space. + 9 + 4 + + + TAR + ALE to RE delay. These bits set time + from ALE low to RE low in number of KCK_FMC clock + cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC + where TKCK_FMC is the FMC clock period Note: Set is + MEMSET or ATTSET according to the addressed + space. + 13 + 4 + + + ECCPS + ECC page size. These bits define the + page size for the extended ECC: + 17 + 3 + + + + + SR + SR + This register contains information about the + FIFO status and interrupt. The FMC features a FIFO that + is used when writing to memories to transfer up to 16 + words of data.This is used to quickly write to the FIFO + and free the AXI bus for transactions to peripherals + other than the FMC, while the FMC is draining its FIFO + into the memory. One of these register bits indicates the + status of the FIFO, for ECC purposes.The ECC is + calculated while the data are written to the memory. To + read the correct ECC, the software must consequently wait + until the FIFO is empty. + 0x84 + 0x20 + 0x00000040 + + + IRS + Interrupt rising edge status The flag is + set by hardware and reset by software. Note: If this + bit is written by software to 1 it will be + set. + 0 + 1 + read-write + + + ILS + Interrupt high-level status The flag is + set by hardware and reset by software. + 1 + 1 + read-write + + + IFS + Interrupt falling edge status The flag + is set by hardware and reset by software. Note: If + this bit is written by software to 1 it will be + set. + 2 + 1 + read-write + + + IREN + Interrupt rising edge detection enable + bit + 3 + 1 + read-write + + + ILEN + Interrupt high-level detection enable + bit + 4 + 1 + read-write + + + IFEN + Interrupt falling edge detection enable + bit + 5 + 1 + read-write + + + FEMPT + FIFO empty. Read-only bit that provides + the status of the FIFO + 6 + 1 + read-only + + + + + PMEM + PMEM + The FMC_PMEM read/write register contains + the timing information for NAND Flash memory bank. This + information is used to access either the common memory + space of the NAND Flash for command, address write access + and data read/write access. + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMSET + Common memory x setup time These bits + define the number of KCK_FMC (+1) clock cycles to set + up the address before the command assertion (NWE, + NOE), for NAND Flash read or write access to common + memory space: + 0 + 8 + + + MEMWAIT + Common memory wait time These bits + define the minimum number of KCK_FMC (+1) clock + cycles to assert the command (NWE, NOE), for NAND + Flash read or write access to common memory space. + The duration of command assertion is extended if the + wait signal (NWAIT) is active (low) at the end of the + programmed value of KCK_FMC: + 8 + 8 + + + MEMHOLD + Common memory hold time These bits + define the number of KCK_FMC clock cycles for write + accesses and KCK_FMC+1 clock cycles for read accesses + during which the address is held (and data for write + accesses) after the command is de-asserted (NWE, + NOE), for NAND Flash read or write access to common + memory space: + 16 + 8 + + + MEMHIZ + Common memory x data bus Hi-Z time These + bits define the number of KCK_FMC clock cycles during + which the data bus is kept Hi-Z after the start of a + NAND Flash write access to common memory space. This + is only valid for write transactions: + 24 + 8 + + + + + PATT + PATT + The FMC_PATT read/write register contains + the timing information for NAND Flash memory bank. It is + used for 8-bit accesses to the attribute memory space of + the NAND Flash for the last address write access if the + timing must differ from that of previous accesses (for + Ready/Busy management, refer to Section20.8.5: NAND Flash + prewait feature). + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTSET + Attribute memory setup time These bits + define the number of KCK_FMC (+1) clock cycles to set + up address before the command assertion (NWE, NOE), + for NAND Flash read or write access to attribute + memory space: + 0 + 8 + + + ATTWAIT + Attribute memory wait time These bits + define the minimum number of x KCK_FMC (+1) clock + cycles to assert the command (NWE, NOE), for NAND + Flash read or write access to attribute memory space. + The duration for command assertion is extended if the + wait signal (NWAIT) is active (low) at the end of the + programmed value of KCK_FMC: + 8 + 8 + + + ATTHOLD + Attribute memory hold time These bits + define the number of KCK_FMC clock cycles during + which the address is held (and data for write access) + after the command de-assertion (NWE, NOE), for NAND + Flash read or write access to attribute memory + space: + 16 + 8 + + + ATTHIZ + Attribute memory data bus Hi-Z time + These bits define the number of KCK_FMC clock cycles + during which the data bus is kept in Hi-Z after the + start of a NAND Flash write access to attribute + memory space on socket. Only valid for writ + transaction: + 24 + 8 + + + + + ECCR + ECCR + This register contain the current error + correction code value computed by the ECC computation + modules of the FMC NAND controller. When the CPU + reads/writes the data from a NAND Flash memory page at + the correct address (refer to Section20.8.6: Computation + of the error correction code (ECC) in NAND Flash memory), + the data read/written from/to the NAND Flash memory are + processed automatically by the ECC computation module. + When X bytes have been read (according to the ECCPS field + in the FMC_PCR registers), the CPU must read the computed + ECC value from the FMC_ECC registers. It then verifies if + these computed parity data are the same as the parity + value recorded in the spare area, to determine whether a + page is valid, and, to correct it otherwise. The FMC_ECCR + register should be cleared after being read by setting + the ECCEN bit to 0. To compute a new data block, the + ECCEN bit must be set to 1. + 0x94 + 0x20 + read-only + 0x00000000 + + + ECC + ECC result This field contains the value + computed by the ECC computation logic. Table167 + describes the contents of these bit + fields. + 0 + 32 + + + + + BWTR1 + BWTR1 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BWTR2 + BWTR2 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BWTR3 + BWTR3 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BWTR4 + BWTR4 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + SDCR1 + SDCR1 + This register contains the control + parameters for each SDRAM memory bank + 0x140 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address bits These bits + define the number of bits of a column + address. + 0 + 2 + + + NR + Number of row address bits These bits + define the number of bits of a row + address. + 2 + 2 + + + MWID + Memory data bus width. These bits define + the memory device width. + 4 + 2 + + + NB + Number of internal banks This bit sets + the number of internal banks. + 6 + 1 + + + CAS + CAS Latency This bits sets the SDRAM CAS + latency in number of memory clock + cycles + 7 + 2 + + + WP + Write protection This bit enables write + mode access to the SDRAM bank. + 9 + 1 + + + SDCLK + SDRAM clock configuration These bits + define the SDRAM clock period for both SDRAM banks + and allow disabling the clock before changing the + frequency. In this case the SDRAM must be + re-initialized. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 10 + 2 + + + RBURST + Burst read This bit enables burst read + mode. The SDRAM controller anticipates the next read + commands during the CAS latency and stores data in + the Read FIFO. Note: The corresponding bit in the + FMC_SDCR2 register is read only. + 12 + 1 + + + RPIPE + Read pipe These bits define the delay, + in KCK_FMC clock cycles, for reading data after CAS + latency. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 13 + 2 + + + + + SDCR2 + SDCR2 + This register contains the control + parameters for each SDRAM memory bank + 0x144 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address bits These bits + define the number of bits of a column + address. + 0 + 2 + + + NR + Number of row address bits These bits + define the number of bits of a row + address. + 2 + 2 + + + MWID + Memory data bus width. These bits define + the memory device width. + 4 + 2 + + + NB + Number of internal banks This bit sets + the number of internal banks. + 6 + 1 + + + CAS + CAS Latency This bits sets the SDRAM CAS + latency in number of memory clock + cycles + 7 + 2 + + + WP + Write protection This bit enables write + mode access to the SDRAM bank. + 9 + 1 + + + SDCLK + SDRAM clock configuration These bits + define the SDRAM clock period for both SDRAM banks + and allow disabling the clock before changing the + frequency. In this case the SDRAM must be + re-initialized. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 10 + 2 + + + RBURST + Burst read This bit enables burst read + mode. The SDRAM controller anticipates the next read + commands during the CAS latency and stores data in + the Read FIFO. Note: The corresponding bit in the + FMC_SDCR2 register is read only. + 12 + 1 + + + RPIPE + Read pipe These bits define the delay, + in KCK_FMC clock cycles, for reading data after CAS + latency. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 13 + 2 + + + + + SDTR1 + SDTR1 + This register contains the timing parameters + of each SDRAM bank + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to Active These bits + define the delay between a Load Mode Register command + and an Active or Refresh command in number of memory + clock cycles. .... + 0 + 4 + + + TXSR + Exit Self-refresh delay These bits + define the delay from releasing the Self-refresh + command to issuing the Activate command in number of + memory clock cycles. .... Note: If two SDRAM devices + are used, the FMC_SDTR1 and FMC_SDTR2 must be + programmed with the same TXSR timing corresponding to + the slowest SDRAM device. + 4 + 4 + + + TRAS + Self refresh time These bits define the + minimum Self-refresh period in number of memory clock + cycles. .... + 8 + 4 + + + TRC + Row cycle delay These bits define the + delay between the Refresh command and the Activate + command, as well as the delay between two consecutive + Refresh commands. It is expressed in number of memory + clock cycles. The TRC timing is only configured in + the FMC_SDTR1 register. If two SDRAM devices are + used, the TRC must be programmed with the timings of + the slowest device. .... Note: TRC must match the TRC + and TRFC (Auto Refresh period) timings defined in the + SDRAM device datasheet. Note: The corresponding bits + in the FMC_SDTR2 register are dont + care. + 12 + 4 + + + TWR + Recovery delay These bits define the + delay between a Write and a Precharge command in + number of memory clock cycles. .... Note: TWR must be + programmed to match the write recovery time (tWR) + defined in the SDRAM datasheet, and to guarantee + that: TWR &#8805; TRAS - TRCD and TWR + &#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles, + TRCD= 2 cycles. So, TWR &gt;= 2 cycles. TWR must + be programmed to 0x1. If two SDRAM devices are used, + the FMC_SDTR1 and FMC_SDTR2 must be programmed with + the same TWR timing corresponding to the slowest + SDRAM device. + 16 + 4 + + + TRP + Row precharge delay These bits define + the delay between a Precharge command and another + command in number of memory clock cycles. The TRP + timing is only configured in the FMC_SDTR1 register. + If two SDRAM devices are used, the TRP must be + programmed with the timing of the slowest device. + .... Note: The corresponding bits in the FMC_SDTR2 + register are dont care. + 20 + 4 + + + TRCD + Row to column delay These bits define + the delay between the Activate command and a + Read/Write command in number of memory clock cycles. + .... + 24 + 4 + + + + + SDTR2 + SDTR2 + This register contains the timing parameters + of each SDRAM bank + 0x14C + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to Active These bits + define the delay between a Load Mode Register command + and an Active or Refresh command in number of memory + clock cycles. .... + 0 + 4 + + + TXSR + Exit Self-refresh delay These bits + define the delay from releasing the Self-refresh + command to issuing the Activate command in number of + memory clock cycles. .... Note: If two SDRAM devices + are used, the FMC_SDTR1 and FMC_SDTR2 must be + programmed with the same TXSR timing corresponding to + the slowest SDRAM device. + 4 + 4 + + + TRAS + Self refresh time These bits define the + minimum Self-refresh period in number of memory clock + cycles. .... + 8 + 4 + + + TRC + Row cycle delay These bits define the + delay between the Refresh command and the Activate + command, as well as the delay between two consecutive + Refresh commands. It is expressed in number of memory + clock cycles. The TRC timing is only configured in + the FMC_SDTR1 register. If two SDRAM devices are + used, the TRC must be programmed with the timings of + the slowest device. .... Note: TRC must match the TRC + and TRFC (Auto Refresh period) timings defined in the + SDRAM device datasheet. Note: The corresponding bits + in the FMC_SDTR2 register are dont + care. + 12 + 4 + + + TWR + Recovery delay These bits define the + delay between a Write and a Precharge command in + number of memory clock cycles. .... Note: TWR must be + programmed to match the write recovery time (tWR) + defined in the SDRAM datasheet, and to guarantee + that: TWR &#8805; TRAS - TRCD and TWR + &#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles, + TRCD= 2 cycles. So, TWR &gt;= 2 cycles. TWR must + be programmed to 0x1. If two SDRAM devices are used, + the FMC_SDTR1 and FMC_SDTR2 must be programmed with + the same TWR timing corresponding to the slowest + SDRAM device. + 16 + 4 + + + TRP + Row precharge delay These bits define + the delay between a Precharge command and another + command in number of memory clock cycles. The TRP + timing is only configured in the FMC_SDTR1 register. + If two SDRAM devices are used, the TRP must be + programmed with the timing of the slowest device. + .... Note: The corresponding bits in the FMC_SDTR2 + register are dont care. + 20 + 4 + + + TRCD + Row to column delay These bits define + the delay between the Activate command and a + Read/Write command in number of memory clock cycles. + .... + 24 + 4 + + + + + SDCMR + SDCMR + This register contains the command issued + when the SDRAM device is accessed. This register is used + to initialize the SDRAM device, and to activate the + Self-refresh and the Power-down modes. As soon as the + MODE field is written, the command will be issued only to + one or to both SDRAM banks according to CTB1 and CTB2 + command bits. This register is the same for both SDRAM + banks. + 0x150 + 0x20 + read-write + 0x00000000 + + + MODE + Command mode These bits define the + command issued to the SDRAM device. Note: When a + command is issued, at least one Command Target Bank + bit ( CTB1 or CTB2) must be set otherwise the command + will be ignored. Note: If two SDRAM banks are used, + the Auto-refresh and PALL command must be issued + simultaneously to the two devices with CTB1 and CTB2 + bits set otherwise the command will be ignored. Note: + If only one SDRAM bank is used and a command is + issued with its associated CTB bit set, the other CTB + bit of the unused bank must be kept to + 0. + 0 + 3 + + + CTB2 + Command Target Bank 2 This bit indicates + whether the command will be issued to SDRAM Bank 2 or + not. + 3 + 1 + + + CTB1 + Command Target Bank 1 This bit indicates + whether the command will be issued to SDRAM Bank 1 or + not. + 4 + 1 + + + NRFS + Number of Auto-refresh These bits define + the number of consecutive Auto-refresh commands + issued when MODE = 011. .... + 5 + 4 + + + MRD + Mode Register definition This 14-bit + field defines the SDRAM Mode Register content. The + Mode Register is programmed using the Load Mode + Register command. The MRD[13:0] bits are also used to + program the extended mode register for mobile + SDRAM. + 9 + 14 + + + + + SDRTR + SDRTR + This register sets the refresh rate in + number of SDCLK clock cycles between the refresh cycles + by configuring the Refresh Timer Count value.Examplewhere + 64 ms is the SDRAM refresh period.The refresh rate must + be increased by 20 SDRAM clock cycles (as in the above + example) to obtain a safe margin if an internal refresh + request occurs when a read request has been accepted. It + corresponds to a COUNT value of 0000111000000 (448). This + 13-bit field is loaded into a timer which is decremented + using the SDRAM clock. This timer generates a refresh + pulse when zero is reached. The COUNT value must be set + at least to 41 SDRAM clock cycles.As soon as the + FMC_SDRTR register is programmed, the timer starts + counting. If the value programmed in the register is 0, + no refresh is carried out. This register must not be + reprogrammed after the initialization procedure to avoid + modifying the refresh rate.Each time a refresh pulse is + generated, this 13-bit COUNT field is reloaded into the + counter.If a memory access is in progress, the + Auto-refresh request is delayed. However, if the memory + access and Auto-refresh requests are generated + simultaneously, the Auto-refresh takes precedence. If the + memory access occurs during a refresh operation, the + request is buffered to be processed when the refresh is + complete.This register is common to SDRAM bank 1 and bank + 2. + 0x154 + 0x20 + 0x00000000 + + + CRE + Clear Refresh error flag This bit is + used to clear the Refresh Error Flag (RE) in the + Status Register. + 0 + 1 + write-only + + + COUNT + Refresh Timer Count This 13-bit field + defines the refresh rate of the SDRAM device. It is + expressed in number of memory clock cycles. It must + be set at least to 41 SDRAM clock cycles (0x29). + Refresh rate = (COUNT + 1) x SDRAM frequency clock + COUNT = (SDRAM refresh period / Number of rows) - + 20 + 1 + 13 + read-write + + + REIE + RES Interrupt Enable + 14 + 1 + read-write + + + + + SDSR + SDSR + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + RE + Refresh error flag An interrupt is + generated if REIE = 1 and RE = 1 + 0 + 1 + + + MODES1 + Status Mode for Bank 1 These bits define + the Status Mode of SDRAM Bank 1. + 1 + 2 + + + MODES2 + Status Mode for Bank 2 These bits define + the Status Mode of SDRAM Bank 2. + 3 + 2 + + + + + + + CEC + CEC + CEC + 0x40006C00 + + 0x0 + 0x400 + registers + + + CEC + HDMI-CEC global interrupt + 94 + + + + CR + CR + CEC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CECEN + CEC Enable The CECEN bit is set and + cleared by software. CECEN=1 starts message reception + and enables the TXSOM control. CECEN=0 disables the + CEC peripheral, clears all bits of CEC_CR register + and aborts any on-going reception or + transmission. + 0 + 1 + + + TXSOM + Tx Start Of Message TXSOM is set by + software to command transmission of the first byte of + a CEC message. If the CEC message consists of only + one byte, TXEOM must be set before of TXSOM. + Start-Bit is effectively started on the CEC line + after SFT is counted. If TXSOM is set while a message + reception is ongoing, transmission will start after + the end of reception. TXSOM is cleared by hardware + after the last byte of the message is sent with a + positive acknowledge (TXEND=1), in case of + transmission underrun (TXUDR=1), negative acknowledge + (TXACKE=1), and transmission error (TXERR=1). It is + also cleared by CECEN=0. It is not cleared and + transmission is automatically retried in case of + arbitration lost (ARBLST=1). TXSOM can be also used + as a status bit informing application whether any + transmission request is pending or under execution. + The application can abort a transmission request at + any time by clearing the CECEN bit. Note: TXSOM must + be set when CECEN=1 TXSOM must be set when + transmission data is available into TXDR HEADERs + first four bits containing own peripheral address are + taken from TXDR[7:4], not from CEC_CFGR.OAR which is + used only for reception + 1 + 1 + + + TXEOM + Tx End Of Message The TXEOM bit is set + by software to command transmission of the last byte + of a CEC message. TXEOM is cleared by hardware at the + same time and under the same conditions as for TXSOM. + Note: TXEOM must be set when CECEN=1 TXEOM must be + set before writing transmission data to TXDR If TXEOM + is set when TXSOM=0, transmitted message will consist + of 1 byte (HEADER) only (PING message) + 2 + 1 + + + + + CFGR + CFGR + This register is used to configure the + HDMI-CEC controller. It is mandatory to write CEC_CFGR + only when CECEN=0. + 0x4 + 0x20 + read-write + 0x00000000 + + + SFT + Signal Free Time SFT bits are set by + software. In the SFT=0x0 configuration the number of + nominal data bit periods waited before transmission + is ruled by hardware according to the transmission + history. In all the other configurations the SFT + number is determined by software. * 0x0 ** 2.5 + Data-Bit periods if CEC is the last bus initiator + with unsuccessful transmission (ARBLST=1, TXERR=1, + TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is + the new bus initiator ** 6 Data-Bit periods if CEC is + the last bus initiator with successful transmission + (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: + 1.5 nominal data bit periods * 0x3: 2.5 nominal data + bit periods * 0x4: 3.5 nominal data bit periods * + 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal + data bit periods * 0x7: 6.5 nominal data bit + periods + 0 + 3 + + + RXTOL + Rx-Tolerance The RXTOL bit is set and + cleared by software. ** Start-Bit, +/- 200 s rise, + +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 + s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall + ** Data-Bit: +/-300 s rise, +/- 500 s + fall + 3 + 1 + + + BRESTP + Rx-Stop on Bit Rising Error The BRESTP + bit is set and cleared by software. + 4 + 1 + + + BREGEN + Generate Error-Bit on Bit Rising Error + The BREGEN bit is set and cleared by software. Note: + If BRDNOGEN=0, an Error-bit is generated upon BRE + detection with BRESTP=1 in broadcast even if + BREGEN=0 + 5 + 1 + + + LBPEGEN + Generate Error-Bit on Long Bit Period + Error The LBPEGEN bit is set and cleared by software. + Note: If BRDNOGEN=0, an Error-bit is generated upon + LBPE detection in broadcast even if + LBPEGEN=0 + 6 + 1 + + + BRDNOGEN + Avoid Error-Bit Generation in Broadcast + The BRDNOGEN bit is set and cleared by + software. + 7 + 1 + + + SFTOPT + SFT Option Bit The SFTOPT bit is set and + cleared by software. + 8 + 1 + + + OAR + Own addresses configuration The OAR bits + are set by software to select which destination + logical addresses has to be considered in receive + mode. Each bit, when set, enables the CEC logical + address identified by the given bit position. At the + end of HEADER reception, the received destination + address is compared with the enabled addresses. In + case of matching address, the incoming message is + acknowledged and received. In case of non-matching + address, the incoming message is received only in + listen mode (LSTN=1), but without acknowledge sent. + Broadcast messages are always received. Example: OAR + = 0b000 0000 0010 0001 means that CEC acknowledges + addresses 0x0 and 0x5. Consequently, each message + directed to one of these addresses is + received. + 16 + 15 + + + LSTN + Listen mode LSTN bit is set and cleared + by software. + 31 + 1 + + + + + TXDR + TXDR + CEC Tx data register + 0x8 + 0x20 + write-only + 0x00000000 + + + TXD + Tx Data register. TXD is a write-only + register containing the data byte to be transmitted. + Note: TXD must be written when + TXSTART=1 + 0 + 8 + + + + + RXDR + RXDR + CEC Rx Data Register + 0xC + 0x20 + read-only + 0x00000000 + + + RXD + Rx Data register. RXD is read-only and + contains the last data byte which has been received + from the CEC line. + 0 + 8 + + + + + ISR + ISR + CEC Interrupt and Status + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RXBR + Rx-Byte Received The RXBR bit is set by + hardware to inform application that a new byte has + been received from the CEC line and stored into the + RXD buffer. RXBR is cleared by software write at + 1. + 0 + 1 + + + RXEND + End Of Reception RXEND is set by + hardware to inform application that the last byte of + a CEC message is received from the CEC line and + stored into the RXD buffer. RXEND is set at the same + time of RXBR. RXEND is cleared by software write at + 1. + 1 + 1 + + + RXOVR + Rx-Overrun RXOVR is set by hardware if + RXBR is not yet cleared at the time a new byte is + received on the CEC line and stored into RXD. RXOVR + assertion stops message reception so that no + acknowledge is sent. In case of broadcast, a negative + acknowledge is sent. RXOVR is cleared by software + write at 1. + 2 + 1 + + + BRE + Rx-Bit Rising Error BRE is set by + hardware in case a Data-Bit waveform is detected with + Bit Rising Error. BRE is set either at the time the + misplaced rising edge occurs, or at the end of the + maximum BRE tolerance allowed by RXTOL, in case + rising edge is still longing. BRE stops message + reception if BRESTP=1. BRE generates an Error-Bit on + the CEC line if BREGEN=1. BRE is cleared by software + write at 1. + 3 + 1 + + + SBPE + Rx-Short Bit Period Error SBPE is set by + hardware in case a Data-Bit waveform is detected with + Short Bit Period Error. SBPE is set at the time the + anticipated falling edge occurs. SBPE generates an + Error-Bit on the CEC line. SBPE is cleared by + software write at 1. + 4 + 1 + + + LBPE + Rx-Long Bit Period Error LBPE is set by + hardware in case a Data-Bit waveform is detected with + Long Bit Period Error. LBPE is set at the end of the + maximum bit-extension tolerance allowed by RXTOL, in + case falling edge is still longing. LBPE always stops + reception of the CEC message. LBPE generates an + Error-Bit on the CEC line if LBPEGEN=1. In case of + broadcast, Error-Bit is generated even in case of + LBPEGEN=0. LBPE is cleared by software write at + 1. + 5 + 1 + + + RXACKE + Rx-Missing Acknowledge In receive mode, + RXACKE is set by hardware to inform application that + no acknowledge was seen on the CEC line. RXACKE + applies only for broadcast messages and in listen + mode also for not directly addressed messages + (destination address not enabled in OAR). RXACKE + aborts message reception. RXACKE is cleared by + software write at 1. + 6 + 1 + + + ARBLST + Arbitration Lost ARBLST is set by + hardware to inform application that CEC device is + switching to reception due to arbitration lost event + following the TXSOM command. ARBLST can be due either + to a contending CEC device starting earlier or + starting at the same time but with higher HEADER + priority. After ARBLST assertion TXSOM bit keeps + pending for next transmission attempt. ARBLST is + cleared by software write at 1. + 7 + 1 + + + TXBR + Tx-Byte Request TXBR is set by hardware + to inform application that the next transmission data + has to be written to TXDR. TXBR is set when the 4th + bit of currently transmitted byte is sent. + Application must write the next byte to TXDR within 6 + nominal data-bit periods before transmission underrun + error occurs (TXUDR). TXBR is cleared by software + write at 1. + 8 + 1 + + + TXEND + End of Transmission TXEND is set by + hardware to inform application that the last byte of + the CEC message has been successfully transmitted. + TXEND clears the TXSOM and TXEOM control bits. TXEND + is cleared by software write at 1. + 9 + 1 + + + TXUDR + Tx-Buffer Underrun In transmission mode, + TXUDR is set by hardware if application was not in + time to load TXDR before of next byte transmission. + TXUDR aborts message transmission and clears TXSOM + and TXEOM control bits. TXUDR is cleared by software + write at 1 + 10 + 1 + + + TXERR + Tx-Error In transmission mode, TXERR is + set by hardware if the CEC initiator detects low + impedance on the CEC line while it is released. TXERR + aborts message transmission and clears TXSOM and + TXEOM controls. TXERR is cleared by software write at + 1. + 11 + 1 + + + TXACKE + Tx-Missing Acknowledge Error In + transmission mode, TXACKE is set by hardware to + inform application that no acknowledge was received. + In case of broadcast transmission, TXACKE informs + application that a negative acknowledge was received. + TXACKE aborts message transmission and clears TXSOM + and TXEOM controls. TXACKE is cleared by software + write at 1. + 12 + 1 + + + + + IER + IER + CEC interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + RXBRIE + Rx-Byte Received Interrupt Enable The + RXBRIE bit is set and cleared by + software. + 0 + 1 + + + RXENDIE + End Of Reception Interrupt Enable The + RXENDIE bit is set and cleared by + software. + 1 + 1 + + + RXOVRIE + Rx-Buffer Overrun Interrupt Enable The + RXOVRIE bit is set and cleared by + software. + 2 + 1 + + + BREIE + Bit Rising Error Interrupt Enable The + BREIE bit is set and cleared by + software. + 3 + 1 + + + SBPEIE + Short Bit Period Error Interrupt Enable + The SBPEIE bit is set and cleared by + software. + 4 + 1 + + + LBPEIE + Long Bit Period Error Interrupt Enable + The LBPEIE bit is set and cleared by + software. + 5 + 1 + + + RXACKIE + Rx-Missing Acknowledge Error Interrupt + Enable The RXACKIE bit is set and cleared by + software. + 6 + 1 + + + ARBLSTIE + Arbitration Lost Interrupt Enable The + ARBLSTIE bit is set and cleared by + software. + 7 + 1 + + + TXBRIE + Tx-Byte Request Interrupt Enable The + TXBRIE bit is set and cleared by + software. + 8 + 1 + + + TXENDIE + Tx-End Of Message Interrupt Enable The + TXENDIE bit is set and cleared by + software. + 9 + 1 + + + TXUDRIE + Tx-Underrun Interrupt Enable The TXUDRIE + bit is set and cleared by software. + 10 + 1 + + + TXERRIE + Tx-Error Interrupt Enable The TXERRIE + bit is set and cleared by software. + 11 + 1 + + + TXACKIE + Tx-Missing Acknowledge Error Interrupt + Enable The TXACKEIE bit is set and cleared by + software. + 12 + 1 + + + + + + + HSEM + HSEM + HSEM + 0x58026400 + + 0x0 + 0x400 + registers + + + HSEM0 + HSEM global interrupt 1 + 125 + + + + HSEM_R0 + HSEM_R0 + HSEM register HSEM_R0 HSEM_R31 + 0x0 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R1 + HSEM_R1 + HSEM register HSEM_R0 HSEM_R31 + 0x4 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R2 + HSEM_R2 + HSEM register HSEM_R0 HSEM_R31 + 0x8 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R3 + HSEM_R3 + HSEM register HSEM_R0 HSEM_R31 + 0xC + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R4 + HSEM_R4 + HSEM register HSEM_R0 HSEM_R31 + 0x10 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R5 + HSEM_R5 + HSEM register HSEM_R0 HSEM_R31 + 0x14 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R6 + HSEM_R6 + HSEM register HSEM_R0 HSEM_R31 + 0x18 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R7 + HSEM_R7 + HSEM register HSEM_R0 HSEM_R31 + 0x1C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R8 + HSEM_R8 + HSEM register HSEM_R0 HSEM_R31 + 0x20 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R9 + HSEM_R9 + HSEM register HSEM_R0 HSEM_R31 + 0x24 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R10 + HSEM_R10 + HSEM register HSEM_R0 HSEM_R31 + 0x28 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R11 + HSEM_R11 + HSEM register HSEM_R0 HSEM_R31 + 0x2C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R12 + HSEM_R12 + HSEM register HSEM_R0 HSEM_R31 + 0x30 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R13 + HSEM_R13 + HSEM register HSEM_R0 HSEM_R31 + 0x34 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R14 + HSEM_R14 + HSEM register HSEM_R0 HSEM_R31 + 0x38 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R15 + HSEM_R15 + HSEM register HSEM_R0 HSEM_R31 + 0x3C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R16 + HSEM_R16 + HSEM register HSEM_R0 HSEM_R31 + 0x40 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R17 + HSEM_R17 + HSEM register HSEM_R0 HSEM_R31 + 0x44 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R18 + HSEM_R18 + HSEM register HSEM_R0 HSEM_R31 + 0x48 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R19 + HSEM_R19 + HSEM register HSEM_R0 HSEM_R31 + 0x4C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R20 + HSEM_R20 + HSEM register HSEM_R0 HSEM_R31 + 0x50 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R21 + HSEM_R21 + HSEM register HSEM_R0 HSEM_R31 + 0x54 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R22 + HSEM_R22 + HSEM register HSEM_R0 HSEM_R31 + 0x58 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R23 + HSEM_R23 + HSEM register HSEM_R0 HSEM_R31 + 0x5C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R24 + HSEM_R24 + HSEM register HSEM_R0 HSEM_R31 + 0x60 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R25 + HSEM_R25 + HSEM register HSEM_R0 HSEM_R31 + 0x64 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R26 + HSEM_R26 + HSEM register HSEM_R0 HSEM_R31 + 0x68 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R27 + HSEM_R27 + HSEM register HSEM_R0 HSEM_R31 + 0x6C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R28 + HSEM_R28 + HSEM register HSEM_R0 HSEM_R31 + 0x70 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R29 + HSEM_R29 + HSEM register HSEM_R0 HSEM_R31 + 0x74 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R30 + HSEM_R30 + HSEM register HSEM_R0 HSEM_R31 + 0x78 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R31 + HSEM_R31 + HSEM register HSEM_R0 HSEM_R31 + 0x7C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR0 + HSEM_RLR0 + HSEM Read lock register + 0x80 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR1 + HSEM_RLR1 + HSEM Read lock register + 0x84 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR2 + HSEM_RLR2 + HSEM Read lock register + 0x88 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR3 + HSEM_RLR3 + HSEM Read lock register + 0x8C + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR4 + HSEM_RLR4 + HSEM Read lock register + 0x90 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR5 + HSEM_RLR5 + HSEM Read lock register + 0x94 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR6 + HSEM_RLR6 + HSEM Read lock register + 0x98 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR7 + HSEM_RLR7 + HSEM Read lock register + 0x9C + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR8 + HSEM_RLR8 + HSEM Read lock register + 0xA0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR9 + HSEM_RLR9 + HSEM Read lock register + 0xA4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR10 + HSEM_RLR10 + HSEM Read lock register + 0xA8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR11 + HSEM_RLR11 + HSEM Read lock register + 0xAC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR12 + HSEM_RLR12 + HSEM Read lock register + 0xB0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR13 + HSEM_RLR13 + HSEM Read lock register + 0xB4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR14 + HSEM_RLR14 + HSEM Read lock register + 0xB8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR15 + HSEM_RLR15 + HSEM Read lock register + 0xBC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR16 + HSEM_RLR16 + HSEM Read lock register + 0xC0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR17 + HSEM_RLR17 + HSEM Read lock register + 0xC4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR18 + HSEM_RLR18 + HSEM Read lock register + 0xC8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR19 + HSEM_RLR19 + HSEM Read lock register + 0xCC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR20 + HSEM_RLR20 + HSEM Read lock register + 0xD0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR21 + HSEM_RLR21 + HSEM Read lock register + 0xD4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR22 + HSEM_RLR22 + HSEM Read lock register + 0xD8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR23 + HSEM_RLR23 + HSEM Read lock register + 0xDC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR24 + HSEM_RLR24 + HSEM Read lock register + 0xE0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR25 + HSEM_RLR25 + HSEM Read lock register + 0xE4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR26 + HSEM_RLR26 + HSEM Read lock register + 0xE8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR27 + HSEM_RLR27 + HSEM Read lock register + 0xEC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR28 + HSEM_RLR28 + HSEM Read lock register + 0xF0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR29 + HSEM_RLR29 + HSEM Read lock register + 0xF4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR30 + HSEM_RLR30 + HSEM Read lock register + 0xF8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR31 + HSEM_RLR31 + HSEM Read lock register + 0xFC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_IER + HSEM_IER + HSEM Interrupt enable register + 0x100 + 0x20 + read-write + 0x00000000 + + + ISEM0 + Interrupt semaphore n enable + bit + 0 + 1 + + + ISEM1 + Interrupt semaphore n enable + bit + 1 + 1 + + + ISEM2 + Interrupt semaphore n enable + bit + 2 + 1 + + + ISEM3 + Interrupt semaphore n enable + bit + 3 + 1 + + + ISEM4 + Interrupt semaphore n enable + bit + 4 + 1 + + + ISEM5 + Interrupt semaphore n enable + bit + 5 + 1 + + + ISEM6 + Interrupt semaphore n enable + bit + 6 + 1 + + + ISEM7 + Interrupt semaphore n enable + bit + 7 + 1 + + + ISEM8 + Interrupt semaphore n enable + bit + 8 + 1 + + + ISEM9 + Interrupt semaphore n enable + bit + 9 + 1 + + + ISEM10 + Interrupt semaphore n enable + bit + 10 + 1 + + + ISEM11 + Interrupt semaphore n enable + bit + 11 + 1 + + + ISEM12 + Interrupt semaphore n enable + bit + 12 + 1 + + + ISEM13 + Interrupt semaphore n enable + bit + 13 + 1 + + + ISEM14 + Interrupt semaphore n enable + bit + 14 + 1 + + + ISEM15 + Interrupt semaphore n enable + bit + 15 + 1 + + + ISEM16 + Interrupt semaphore n enable + bit + 16 + 1 + + + ISEM17 + Interrupt semaphore n enable + bit + 17 + 1 + + + ISEM18 + Interrupt semaphore n enable + bit + 18 + 1 + + + ISEM19 + Interrupt semaphore n enable + bit + 19 + 1 + + + ISEM20 + Interrupt semaphore n enable + bit + 20 + 1 + + + ISEM21 + Interrupt semaphore n enable + bit + 21 + 1 + + + ISEM22 + Interrupt semaphore n enable + bit + 22 + 1 + + + ISEM23 + Interrupt semaphore n enable + bit + 23 + 1 + + + ISEM24 + Interrupt semaphore n enable + bit + 24 + 1 + + + ISEM25 + Interrupt semaphore n enable + bit + 25 + 1 + + + ISEM26 + Interrupt semaphore n enable + bit + 26 + 1 + + + ISEM27 + Interrupt semaphore n enable + bit + 27 + 1 + + + ISEM28 + Interrupt semaphore n enable + bit + 28 + 1 + + + ISEM29 + Interrupt semaphore n enable + bit + 29 + 1 + + + ISEM30 + Interrupt semaphore n enable + bit + 30 + 1 + + + ISEM31 + Interrupt(N) semaphore n enable + bit. + 31 + 1 + + + + + HSEM_ICR + HSEM_ICR + HSEM Interrupt clear register + 0x104 + 0x20 + read-only + 0x00000000 + + + ISEM0 + Interrupt(N) semaphore n clear + bit + 0 + 1 + + + ISEM1 + Interrupt(N) semaphore n clear + bit + 1 + 1 + + + ISEM2 + Interrupt(N) semaphore n clear + bit + 2 + 1 + + + ISEM3 + Interrupt(N) semaphore n clear + bit + 3 + 1 + + + ISEM4 + Interrupt(N) semaphore n clear + bit + 4 + 1 + + + ISEM5 + Interrupt(N) semaphore n clear + bit + 5 + 1 + + + ISEM6 + Interrupt(N) semaphore n clear + bit + 6 + 1 + + + ISEM7 + Interrupt(N) semaphore n clear + bit + 7 + 1 + + + ISEM8 + Interrupt(N) semaphore n clear + bit + 8 + 1 + + + ISEM9 + Interrupt(N) semaphore n clear + bit + 9 + 1 + + + ISEM10 + Interrupt(N) semaphore n clear + bit + 10 + 1 + + + ISEM11 + Interrupt(N) semaphore n clear + bit + 11 + 1 + + + ISEM12 + Interrupt(N) semaphore n clear + bit + 12 + 1 + + + ISEM13 + Interrupt(N) semaphore n clear + bit + 13 + 1 + + + ISEM14 + Interrupt(N) semaphore n clear + bit + 14 + 1 + + + ISEM15 + Interrupt(N) semaphore n clear + bit + 15 + 1 + + + ISEM16 + Interrupt(N) semaphore n clear + bit + 16 + 1 + + + ISEM17 + Interrupt(N) semaphore n clear + bit + 17 + 1 + + + ISEM18 + Interrupt(N) semaphore n clear + bit + 18 + 1 + + + ISEM19 + Interrupt(N) semaphore n clear + bit + 19 + 1 + + + ISEM20 + Interrupt(N) semaphore n clear + bit + 20 + 1 + + + ISEM21 + Interrupt(N) semaphore n clear + bit + 21 + 1 + + + ISEM22 + Interrupt(N) semaphore n clear + bit + 22 + 1 + + + ISEM23 + Interrupt(N) semaphore n clear + bit + 23 + 1 + + + ISEM24 + Interrupt(N) semaphore n clear + bit + 24 + 1 + + + ISEM25 + Interrupt(N) semaphore n clear + bit + 25 + 1 + + + ISEM26 + Interrupt(N) semaphore n clear + bit + 26 + 1 + + + ISEM27 + Interrupt(N) semaphore n clear + bit + 27 + 1 + + + ISEM28 + Interrupt(N) semaphore n clear + bit + 28 + 1 + + + ISEM29 + Interrupt(N) semaphore n clear + bit + 29 + 1 + + + ISEM30 + Interrupt(N) semaphore n clear + bit + 30 + 1 + + + ISEM31 + Interrupt(N) semaphore n clear + bit + 31 + 1 + + + + + HSEM_ISR + HSEM_ISR + HSEM Interrupt status register + 0x108 + 0x20 + read-only + 0x00000000 + + + ISEM0 + Interrupt(N) semaphore n status bit + before enable (mask) + 0 + 1 + + + ISEM1 + Interrupt(N) semaphore n status bit + before enable (mask) + 1 + 1 + + + ISEM2 + Interrupt(N) semaphore n status bit + before enable (mask) + 2 + 1 + + + ISEM3 + Interrupt(N) semaphore n status bit + before enable (mask) + 3 + 1 + + + ISEM4 + Interrupt(N) semaphore n status bit + before enable (mask) + 4 + 1 + + + ISEM5 + Interrupt(N) semaphore n status bit + before enable (mask) + 5 + 1 + + + ISEM6 + Interrupt(N) semaphore n status bit + before enable (mask) + 6 + 1 + + + ISEM7 + Interrupt(N) semaphore n status bit + before enable (mask) + 7 + 1 + + + ISEM8 + Interrupt(N) semaphore n status bit + before enable (mask) + 8 + 1 + + + ISEM9 + Interrupt(N) semaphore n status bit + before enable (mask) + 9 + 1 + + + ISEM10 + Interrupt(N) semaphore n status bit + before enable (mask) + 10 + 1 + + + ISEM11 + Interrupt(N) semaphore n status bit + before enable (mask) + 11 + 1 + + + ISEM12 + Interrupt(N) semaphore n status bit + before enable (mask) + 12 + 1 + + + ISEM13 + Interrupt(N) semaphore n status bit + before enable (mask) + 13 + 1 + + + ISEM14 + Interrupt(N) semaphore n status bit + before enable (mask) + 14 + 1 + + + ISEM15 + Interrupt(N) semaphore n status bit + before enable (mask) + 15 + 1 + + + ISEM16 + Interrupt(N) semaphore n status bit + before enable (mask) + 16 + 1 + + + ISEM17 + Interrupt(N) semaphore n status bit + before enable (mask) + 17 + 1 + + + ISEM18 + Interrupt(N) semaphore n status bit + before enable (mask) + 18 + 1 + + + ISEM19 + Interrupt(N) semaphore n status bit + before enable (mask) + 19 + 1 + + + ISEM20 + Interrupt(N) semaphore n status bit + before enable (mask) + 20 + 1 + + + ISEM21 + Interrupt(N) semaphore n status bit + before enable (mask) + 21 + 1 + + + ISEM22 + Interrupt(N) semaphore n status bit + before enable (mask) + 22 + 1 + + + ISEM23 + Interrupt(N) semaphore n status bit + before enable (mask) + 23 + 1 + + + ISEM24 + Interrupt(N) semaphore n status bit + before enable (mask) + 24 + 1 + + + ISEM25 + Interrupt(N) semaphore n status bit + before enable (mask) + 25 + 1 + + + ISEM26 + Interrupt(N) semaphore n status bit + before enable (mask) + 26 + 1 + + + ISEM27 + Interrupt(N) semaphore n status bit + before enable (mask) + 27 + 1 + + + ISEM28 + Interrupt(N) semaphore n status bit + before enable (mask) + 28 + 1 + + + ISEM29 + Interrupt(N) semaphore n status bit + before enable (mask) + 29 + 1 + + + ISEM30 + Interrupt(N) semaphore n status bit + before enable (mask) + 30 + 1 + + + ISEM31 + Interrupt(N) semaphore n status bit + before enable (mask) + 31 + 1 + + + + + HSEM_MISR + HSEM_MISR + HSEM Masked interrupt status + register + 0x10C + 0x20 + read-only + 0x00000000 + + + ISEM0 + masked interrupt(N) semaphore n status + bit after enable (mask) + 0 + 1 + + + ISEM1 + masked interrupt(N) semaphore n status + bit after enable (mask) + 1 + 1 + + + ISEM2 + masked interrupt(N) semaphore n status + bit after enable (mask) + 2 + 1 + + + ISEM3 + masked interrupt(N) semaphore n status + bit after enable (mask) + 3 + 1 + + + ISEM4 + masked interrupt(N) semaphore n status + bit after enable (mask) + 4 + 1 + + + ISEM5 + masked interrupt(N) semaphore n status + bit after enable (mask) + 5 + 1 + + + ISEM6 + masked interrupt(N) semaphore n status + bit after enable (mask) + 6 + 1 + + + ISEM7 + masked interrupt(N) semaphore n status + bit after enable (mask) + 7 + 1 + + + ISEM8 + masked interrupt(N) semaphore n status + bit after enable (mask) + 8 + 1 + + + ISEM9 + masked interrupt(N) semaphore n status + bit after enable (mask) + 9 + 1 + + + ISEM10 + masked interrupt(N) semaphore n status + bit after enable (mask) + 10 + 1 + + + ISEM11 + masked interrupt(N) semaphore n status + bit after enable (mask) + 11 + 1 + + + ISEM12 + masked interrupt(N) semaphore n status + bit after enable (mask) + 12 + 1 + + + ISEM13 + masked interrupt(N) semaphore n status + bit after enable (mask) + 13 + 1 + + + ISEM14 + masked interrupt(N) semaphore n status + bit after enable (mask) + 14 + 1 + + + ISEM15 + masked interrupt(N) semaphore n status + bit after enable (mask) + 15 + 1 + + + ISEM16 + masked interrupt(N) semaphore n status + bit after enable (mask) + 16 + 1 + + + ISEM17 + masked interrupt(N) semaphore n status + bit after enable (mask) + 17 + 1 + + + ISEM18 + masked interrupt(N) semaphore n status + bit after enable (mask) + 18 + 1 + + + ISEM19 + masked interrupt(N) semaphore n status + bit after enable (mask) + 19 + 1 + + + ISEM20 + masked interrupt(N) semaphore n status + bit after enable (mask) + 20 + 1 + + + ISEM21 + masked interrupt(N) semaphore n status + bit after enable (mask) + 21 + 1 + + + ISEM22 + masked interrupt(N) semaphore n status + bit after enable (mask) + 22 + 1 + + + ISEM23 + masked interrupt(N) semaphore n status + bit after enable (mask) + 23 + 1 + + + ISEM24 + masked interrupt(N) semaphore n status + bit after enable (mask) + 24 + 1 + + + ISEM25 + masked interrupt(N) semaphore n status + bit after enable (mask) + 25 + 1 + + + ISEM26 + masked interrupt(N) semaphore n status + bit after enable (mask) + 26 + 1 + + + ISEM27 + masked interrupt(N) semaphore n status + bit after enable (mask) + 27 + 1 + + + ISEM28 + masked interrupt(N) semaphore n status + bit after enable (mask) + 28 + 1 + + + ISEM29 + masked interrupt(N) semaphore n status + bit after enable (mask) + 29 + 1 + + + ISEM30 + masked interrupt(N) semaphore n status + bit after enable (mask) + 30 + 1 + + + ISEM31 + masked interrupt(N) semaphore n status + bit after enable (mask) + 31 + 1 + + + + + HSEM_CR + HSEM_CR + HSEM Clear register + 0x140 + 0x20 + read-write + 0x00000000 + + + MASTERID + MasterID of semaphores to be + cleared + 8 + 8 + + + KEY + Semaphore clear Key + 16 + 16 + + + + + HSEM_KEYR + HSEM_KEYR + HSEM Interrupt clear register + 0x144 + 0x20 + read-write + 0x00000000 + + + KEY + Semaphore Clear Key + 16 + 16 + + + + + + + I2C1 + I2C + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + + CR1 + CR1 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable Note: When PE=0, the + I2C SCL and SDA lines are released. Internal state + machines and status bits are put back to their reset + value. When cleared, PE must be kept low for at least + 3 APB clock cycles. + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match Interrupt enable (slave + only) + 3 + 1 + + + NACKIE + Not acknowledge received Interrupt + enable + 4 + 1 + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + + + TCIE + Transfer Complete interrupt enable Note: + Any of these events will generate an interrupt: + Transfer Complete (TC) Transfer Complete Reload + (TCR) + 6 + 1 + + + ERRIE + Error interrupts enable Note: Any of + these errors generate an interrupt: Arbitration Loss + (ARLO) Bus Error detection (BERR) Overrun/Underrun + (OVR) Timeout detection (TIMEOUT) PEC error detection + (PECERR) Alert pin event detection + (ALERT) + 7 + 1 + + + DNF + Digital noise filter These bits are used + to configure the digital noise filter on SDA and SCL + input. The digital filter will filter spikes with a + length of up to DNF[3:0] * tI2CCLK ... Note: If the + analog filter is also enabled, the digital filter is + added to the analog filter. This filter can only be + programmed when the I2C is disabled (PE = + 0). + 8 + 4 + + + ANFOFF + Analog noise filter OFF Note: This bit + can only be programmed when the I2C is disabled (PE = + 0). + 12 + 1 + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + + + SBC + Slave byte control This bit is used to + enable hardware byte control in slave + mode. + 16 + 1 + + + NOSTRETCH + Clock stretching disable This bit is + used to disable clock stretching in slave mode. It + must be kept cleared in master mode. Note: This bit + can only be programmed when the I2C is disabled (PE = + 0). + 17 + 1 + + + WUPEN + Wakeup from Stop mode enable Note: If + the Wakeup from Stop mode feature is not supported, + this bit is reserved and forced by hardware to 0. + Please refer to Section25.3: I2C implementation. + Note: WUPEN can be set only when DNF = + 0000 + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable Note: If the + SMBus feature is not supported, this bit is reserved + and forced by hardware to 0. Please refer to + Section25.3: I2C implementation. + 20 + 1 + + + SMBDEN + SMBus Device Default address enable + Note: If the SMBus feature is not supported, this bit + is reserved and forced by hardware to 0. Please refer + to Section25.3: I2C implementation. + 21 + 1 + + + ALERTEN + SMBus alert enable Device mode + (SMBHEN=0): Host mode (SMBHEN=1): Note: When + ALERTEN=0, the SMBA pin can be used as a standard + GPIO. If the SMBus feature is not supported, this bit + is reserved and forced by hardware to 0. Please refer + to Section25.3: I2C implementation. + 22 + 1 + + + PECEN + PEC enable Note: If the SMBus feature is + not supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 23 + 1 + + + + + CR2 + CR2 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x4 + 0x20 + read-write + 0x00000000 + + + SADD0 + Slave address bit 0 (master mode) In + 7-bit addressing mode (ADD10 = 0): This bit is dont + care In 10-bit addressing mode (ADD10 = 1): This bit + should be written with bit 0 of the slave address to + be sent Note: Changing these bits when the START bit + is set is not allowed. + 0 + 1 + + + SADD1 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 1 + 1 + + + SADD2 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 2 + 1 + + + SADD3 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 3 + 1 + + + SADD4 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 4 + 1 + + + SADD5 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 5 + 1 + + + SADD6 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 6 + 1 + + + SADD7 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 7 + 1 + + + SADD8 + Slave address bit 9:8 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits are + dont care In 10-bit addressing mode (ADD10 = 1): + These bits should be written with bits 9:8 of the + slave address to be sent Note: Changing these bits + when the START bit is set is not + allowed. + 8 + 1 + + + SADD9 + Slave address bit 9:8 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits are + dont care In 10-bit addressing mode (ADD10 = 1): + These bits should be written with bits 9:8 of the + slave address to be sent Note: Changing these bits + when the START bit is set is not + allowed. + 9 + 1 + + + RD_WRN + Transfer direction (master mode) Note: + Changing this bit when the START bit is set is not + allowed. + 10 + 1 + + + ADD10 + 10-bit addressing mode (master mode) + Note: Changing this bit when the START bit is set is + not allowed. + 11 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) Note: Changing this + bit when the START bit is set is not + allowed. + 12 + 1 + + + START + Start generation This bit is set by + software, and cleared by hardware after the Start + followed by the address sequence is sent, by an + arbitration loss, by a timeout error detection, or + when PE = 0. It can also be cleared by software by + writing 1 to the ADDRCF bit in the I2C_ICR register. + If the I2C is already in master mode with AUTOEND = + 0, setting this bit generates a Repeated Start + condition when RELOAD=0, after the end of the NBYTES + transfer. Otherwise setting this bit will generate a + START condition once the bus is free. Note: Writing 0 + to this bit has no effect. The START bit can be set + even if the bus is BUSY or I2C is in slave mode. This + bit has no effect when RELOAD is set. + 13 + 1 + + + STOP + Stop generation (master mode) The bit is + set by software, cleared by hardware when a Stop + condition is detected, or when PE = 0. In Master + Mode: Note: Writing 0 to this bit has no + effect. + 14 + 1 + + + NACK + NACK generation (slave mode) The bit is + set by software, cleared by hardware when the NACK is + sent, or when a STOP condition or an Address matched + is received, or when PE=0. Note: Writing 0 to this + bit has no effect. This bit is used in slave mode + only: in master receiver mode, NACK is automatically + generated after last byte preceding STOP or RESTART + condition, whatever the NACK bit value. When an + overrun occurs in slave receiver NOSTRETCH mode, a + NACK is automatically generated whatever the NACK bit + value. When hardware PEC checking is enabled + (PECBYTE=1), the PEC acknowledge value does not + depend on the NACK value. + 15 + 1 + + + NBYTES + Number of bytes The number of bytes to + be transmitted/received is programmed there. This + field is dont care in slave mode with SBC=0. Note: + Changing these bits when the START bit is set is not + allowed. + 16 + 8 + + + RELOAD + NBYTES reload mode This bit is set and + cleared by software. + 24 + 1 + + + AUTOEND + Automatic end mode (master mode) This + bit is set and cleared by software. Note: This bit + has no effect in slave mode or when the RELOAD bit is + set. + 25 + 1 + + + PECBYTE + Packet error checking byte This bit is + set by software, and cleared by hardware when the PEC + is transferred, or when a STOP condition or an + Address matched is received, also when PE=0. Note: + Writing 0 to this bit has no effect. This bit has no + effect when RELOAD is set. This bit has no effect is + slave mode when SBC=0. If the SMBus feature is not + supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 26 + 1 + + + + + OAR1 + OAR1 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address 7-bit addressing mode: + dont care 10-bit addressing mode: bits 9:8 of address + Note: These bits can be written only when OA1EN=0. + OA1[7:1]: Interface address Bits 7:1 of address Note: + These bits can be written only when OA1EN=0. OA1[0]: + Interface address 7-bit addressing mode: dont care + 10-bit addressing mode: bit 0 of address Note: This + bit can be written only when OA1EN=0. + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode Note: This bit + can be written only when OA1EN=0. + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address bits 7:1 of address + Note: These bits can be written only when + OA2EN=0. + 1 + 7 + + + OA2MSK + Own Address 2 masks Note: These bits can + be written only when OA2EN=0. As soon as OA2MSK is + not equal to 0, the reserved I2C addresses (0b0000xxx + and 0b1111xxx) are not acknowledged even if the + comparison matches. + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Access: No wait states + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) This field + is used to generate the SCL low period in master + mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also + used to generate tBUF and tSU:STA + timings. + 0 + 8 + + + SCLH + SCL high period (master mode) This field + is used to generate the SCL high period in master + mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also + used to generate tSU:STO and tHD:STA + timing. + 8 + 8 + + + SDADEL + Data hold time This field is used to + generate the delay tSDADEL between SCL falling edge + and SDA edge. In master mode and in slave mode with + NOSTRETCH = 0, the SCL line is stretched low during + tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is + used to generate tHD:DAT timing. + 16 + 4 + + + SCLDEL + Data setup time This field is used to + generate a delay tSCLDEL between SDA edge and SCL + rising edge. In master mode and in slave mode with + NOSTRETCH = 0, the SCL line is stretched low during + tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL + is used to generate tSU:DAT timing. + 20 + 4 + + + PRESC + Timing prescaler This field is used to + prescale I2CCLK in order to generate the clock period + tPRESC used for data setup and hold counters (refer + to I2C timings on page9) and for SCL high and low + level counters (refer to I2C master initialization on + page24). tPRESC = (PRESC+1) x tI2CCLK + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus Timeout A This field is used to + configure: The SCL low timeout condition tTIMEOUT + when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK + The bus idle condition (both SCL and SDA high) when + TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These + bits can be written only when + TIMOUTEN=0. + 0 + 12 + + + TIDLE + Idle clock timeout detection Note: This + bit can be written only when + TIMOUTEN=0. + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B This field is used to + configure the cumulative clock extension timeout: In + master mode, the master cumulative clock low extend + time (tLOW:MEXT) is detected In slave mode, the slave + cumulative clock low extend time (tLOW:SEXT) is + detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK + Note: These bits can be written only when + TEXTEN=0. + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Access: No wait states + 0x18 + 0x20 + 0x00000001 + + + TXE + Transmit data register empty + (transmitters) This bit is set by hardware when the + I2C_TXDR register is empty. It is cleared when the + next data to be sent is written in the I2C_TXDR + register. This bit can be written to 1 by software in + order to flush the transmit data register I2C_TXDR. + Note: This bit is set by hardware when + PE=0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) + This bit is set by hardware when the I2C_TXDR + register is empty and the data to be transmitted must + be written in the I2C_TXDR register. It is cleared + when the next data to be sent is written in the + I2C_TXDR register. This bit can be written to 1 by + software when NOSTRETCH=1 only, in order to generate + a TXIS event (interrupt if TXIE=1 or DMA request if + TXDMAEN=1). Note: This bit is cleared by hardware + when PE=0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty + (receivers) This bit is set by hardware when the + received data is copied into the I2C_RXDR register, + and is ready to be read. It is cleared when I2C_RXDR + is read. Note: This bit is cleared by hardware when + PE=0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) This bit is + set by hardware as soon as the received slave address + matched with one of the enabled slave addresses. It + is cleared by software by setting ADDRCF bit. Note: + This bit is cleared by hardware when + PE=0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag This flag + is set by hardware when a NACK is received after a + byte transmission. It is cleared by software by + setting the NACKCF bit. Note: This bit is cleared by + hardware when PE=0. + 4 + 1 + read-only + + + STOPF + Stop detection flag This flag is set by + hardware when a Stop condition is detected on the bus + and the peripheral is involved in this transfer: + either as a master, provided that the STOP condition + is generated by the peripheral. or as a slave, + provided that the peripheral has been addressed + previously during this transfer. It is cleared by + software by setting the STOPCF bit. Note: This bit is + cleared by hardware when PE=0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) This + flag is set by hardware when RELOAD=0, AUTOEND=0 and + NBYTES data have been transferred. It is cleared by + software when START bit or STOP bit is set. Note: + This bit is cleared by hardware when + PE=0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload This flag is + set by hardware when RELOAD=1 and NBYTES data have + been transferred. It is cleared by software when + NBYTES is written to a non-zero value. Note: This bit + is cleared by hardware when PE=0. This flag is only + for master mode, or for slave mode when the SBC bit + is set. + 7 + 1 + read-only + + + BERR + Bus error This flag is set by hardware + when a misplaced Start or Stop condition is detected + whereas the peripheral is involved in the transfer. + The flag is not set during the address phase in slave + mode. It is cleared by software by setting BERRCF + bit. Note: This bit is cleared by hardware when + PE=0. + 8 + 1 + read-only + + + ARLO + Arbitration lost This flag is set by + hardware in case of arbitration loss. It is cleared + by software by setting the ARLOCF bit. Note: This bit + is cleared by hardware when PE=0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) This flag + is set by hardware in slave mode with NOSTRETCH=1, + when an overrun/underrun error occurs. It is cleared + by software by setting the OVRCF bit. Note: This bit + is cleared by hardware when PE=0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception This flag is set + by hardware when the received PEC does not match with + the PEC register content. A NACK is automatically + sent after the wrong PEC reception. It is cleared by + software by setting the PECCF bit. Note: This bit is + cleared by hardware when PE=0. If the SMBus feature + is not supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or tLOW detection flag This flag + is set by hardware when a timeout or extended clock + timeout occurred. It is cleared by software by + setting the TIMEOUTCF bit. Note: This bit is cleared + by hardware when PE=0. If the SMBus feature is not + supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert This flag is set by hardware + when SMBHEN=1 (SMBus host configuration), ALERTEN=1 + and a SMBALERT event (falling edge) is detected on + SMBA pin. It is cleared by software by setting the + ALERTCF bit. Note: This bit is cleared by hardware + when PE=0. If the SMBus feature is not supported, + this bit is reserved and forced by hardware to 0. + Please refer to Section25.3: I2C + implementation. + 13 + 1 + read-only + + + BUSY + Bus busy This flag indicates that a + communication is in progress on the bus. It is set by + hardware when a START condition is detected. It is + cleared by hardware when a Stop condition is + detected, or when PE=0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) This + flag is updated when an address match event occurs + (ADDR=1). + 16 + 1 + read-only + + + ADDCODE + Address match code (Slave mode) These + bits are updated with the received address when an + address match event occurs (ADDR = 1). In the case of + a 10-bit address, ADDCODE provides the 10-bit header + followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + ICR + ICR + Access: No wait states + 0x1C + 0x20 + write-only + 0x00000000 + + + ADDRCF + Address matched flag clear Writing 1 to + this bit clears the ADDR flag in the I2C_ISR + register. Writing 1 to this bit also clears the START + bit in the I2C_CR2 register. + 3 + 1 + + + NACKCF + Not Acknowledge flag clear Writing 1 to + this bit clears the ACKF flag in I2C_ISR + register. + 4 + 1 + + + STOPCF + Stop detection flag clear Writing 1 to + this bit clears the STOPF flag in the I2C_ISR + register. + 5 + 1 + + + BERRCF + Bus error flag clear Writing 1 to this + bit clears the BERRF flag in the I2C_ISR + register. + 8 + 1 + + + ARLOCF + Arbitration Lost flag clear Writing 1 to + this bit clears the ARLO flag in the I2C_ISR + register. + 9 + 1 + + + OVRCF + Overrun/Underrun flag clear Writing 1 to + this bit clears the OVR flag in the I2C_ISR + register. + 10 + 1 + + + PECCF + PEC Error flag clear Writing 1 to this + bit clears the PECERR flag in the I2C_ISR register. + Note: If the SMBus feature is not supported, this bit + is reserved and forced by hardware to 0. Please refer + to Section25.3: I2C implementation. + 11 + 1 + + + TIMOUTCF + Timeout detection flag clear Writing 1 + to this bit clears the TIMEOUT flag in the I2C_ISR + register. Note: If the SMBus feature is not + supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 12 + 1 + + + ALERTCF + Alert flag clear Writing 1 to this bit + clears the ALERT flag in the I2C_ISR register. Note: + If the SMBus feature is not supported, this bit is + reserved and forced by hardware to 0. Please refer to + Section25.3: I2C implementation. + 13 + 1 + + + + + PECR + PECR + Access: No wait states + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register This + field contains the internal PEC when PECEN=1. The PEC + is cleared by hardware when PE=0. + 0 + 8 + + + + + RXDR + RXDR + Access: No wait states + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data Data byte received + from the I2C bus. + 0 + 8 + + + + + TXDR + TXDR + Access: No wait states + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data Data byte to be + transmitted to the I2C bus. Note: These bits can be + written only when TXE=1. + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + + I2C4 + 0x58001C00 + + I2C4_EV + I2C4 event interrupt + 95 + + + I2C4_ER + I2C4 error interrupt + 96 + + + + GPIOA + GPIO + GPIO + 0x58020000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xABFFFFFF + + + MODE0 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 0 + 2 + + + MODE1 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 2 + 2 + + + MODE2 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 4 + 2 + + + MODE3 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 6 + 2 + + + MODE4 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 8 + 2 + + + MODE5 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 10 + 2 + + + MODE6 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 12 + 2 + + + MODE7 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 14 + 2 + + + MODE8 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 16 + 2 + + + MODE9 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 18 + 2 + + + MODE10 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 20 + 2 + + + MODE11 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 22 + 2 + + + MODE12 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 24 + 2 + + + MODE13 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 26 + 2 + + + MODE14 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 28 + 2 + + + MODE15 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 30 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 0 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 1 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 2 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 3 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 4 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 5 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 6 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 7 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 8 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 9 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 10 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 11 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 12 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 13 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 14 + 1 + + + OT15 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 15 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEED0 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 0 + 2 + + + OSPEED1 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 2 + 2 + + + OSPEED2 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 4 + 2 + + + OSPEED3 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 6 + 2 + + + OSPEED4 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 8 + 2 + + + OSPEED5 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 10 + 2 + + + OSPEED6 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 12 + 2 + + + OSPEED7 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 14 + 2 + + + OSPEED8 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 16 + 2 + + + OSPEED9 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 18 + 2 + + + OSPEED10 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 20 + 2 + + + OSPEED11 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 22 + 2 + + + OSPEED12 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 24 + 2 + + + OSPEED13 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 26 + 2 + + + OSPEED14 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 28 + 2 + + + OSPEED15 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 30 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x12100000 + + + PUPD0 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 0 + 2 + + + PUPD1 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 2 + 2 + + + PUPD2 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 4 + 2 + + + PUPD3 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 6 + 2 + + + PUPD4 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 8 + 2 + + + PUPD5 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 10 + 2 + + + PUPD6 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 12 + 2 + + + PUPD7 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 14 + 2 + + + PUPD8 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 16 + 2 + + + PUPD9 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 18 + 2 + + + PUPD10 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 20 + 2 + + + PUPD11 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 22 + 2 + + + PUPD12 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 24 + 2 + + + PUPD13 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 26 + 2 + + + PUPD14 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 28 + 2 + + + PUPD15 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 30 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 0 + 1 + + + ID1 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 1 + 1 + + + ID2 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 2 + 1 + + + ID3 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 3 + 1 + + + ID4 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 4 + 1 + + + ID5 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 5 + 1 + + + ID6 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 6 + 1 + + + ID7 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 7 + 1 + + + ID8 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 8 + 1 + + + ID9 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 9 + 1 + + + ID10 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 10 + 1 + + + ID11 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 11 + 1 + + + ID12 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 12 + 1 + + + ID13 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 13 + 1 + + + ID14 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 14 + 1 + + + ID15 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 15 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 0 + 1 + + + OD1 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 1 + 1 + + + OD2 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 2 + 1 + + + OD3 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 3 + 1 + + + OD4 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 4 + 1 + + + OD5 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 5 + 1 + + + OD6 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 6 + 1 + + + OD7 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 7 + 1 + + + OD8 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 8 + 1 + + + OD9 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 9 + 1 + + + OD10 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 10 + 1 + + + OD11 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 11 + 1 + + + OD12 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 12 + 1 + + + OD13 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 13 + 1 + + + OD14 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 14 + 1 + + + OD15 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 15 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 0 + 1 + + + BS1 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 1 + 1 + + + BS2 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 2 + 1 + + + BS3 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 3 + 1 + + + BS4 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 4 + 1 + + + BS5 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 5 + 1 + + + BS6 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 6 + 1 + + + BS7 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 7 + 1 + + + BS8 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 8 + 1 + + + BS9 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 9 + 1 + + + BS10 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 10 + 1 + + + BS11 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 11 + 1 + + + BS12 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 12 + 1 + + + BS13 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 13 + 1 + + + BS14 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 14 + 1 + + + BS15 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 15 + 1 + + + BR0 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 16 + 1 + + + BR1 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 17 + 1 + + + BR2 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 18 + 1 + + + BR3 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 19 + 1 + + + BR4 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 20 + 1 + + + BR5 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 21 + 1 + + + BR6 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 22 + 1 + + + BR7 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 23 + 1 + + + BR8 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 24 + 1 + + + BR9 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 25 + 1 + + + BR10 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 26 + 1 + + + BR11 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 27 + 1 + + + BR12 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 28 + 1 + + + BR13 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 29 + 1 + + + BR14 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 30 + 1 + + + BR15 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 31 + 1 + + + + + LCKR + LCKR + This register is used to lock the + configuration of the port bits when a correct write + sequence is applied to bit 16 (LCKK). The value of bits + [15:0] is used to lock the configuration of the GPIO. + During the write sequence, the value of LCKR[15:0] must + not change. When the LOCK sequence has been applied on a + port bit, the value of this port bit can no longer be + modified until the next MCU reset or peripheral reset.A + specific write sequence is used to write to the + GPIOx_LCKR register. Only word access (32-bit long) is + allowed during this locking sequence.Each lock bit + freezes a specific configuration register (control and + alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 0 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 1 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 2 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 3 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 4 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 5 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 6 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 7 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 8 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 9 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 10 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 11 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 12 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 13 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 14 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 15 + 1 + + + LCKK + Lock key This bit can be read any time. + It can only be modified using the lock key write + sequence. LOCK key write sequence: WR LCKR[16] = 1 + + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = + 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read + operation is optional but it confirms that the lock + is active) Note: During the LOCK key write sequence, + the value of LCK[15:0] must not change. Any error in + the lock sequence aborts the lock. After the first + lock sequence on any bit of the port, any read access + on the LCKK bit will return 1 until the next MCU + reset or peripheral reset. + 16 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 0 + 4 + + + AFSEL1 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 4 + 4 + + + AFSEL2 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 8 + 4 + + + AFSEL3 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 12 + 4 + + + AFSEL4 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 16 + 4 + + + AFSEL5 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 20 + 4 + + + AFSEL6 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 24 + 4 + + + AFSEL7 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 28 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 0 + 4 + + + AFSEL9 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 4 + 4 + + + AFSEL10 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 8 + 4 + + + AFSEL11 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 12 + 4 + + + AFSEL12 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 16 + 4 + + + AFSEL13 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 20 + 4 + + + AFSEL14 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 24 + 4 + + + AFSEL15 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 28 + 4 + + + + + + + GPIOB + 0x58020400 + + + GPIOC + 0x58020800 + + + GPIOD + 0x58020C00 + + + GPIOE + 0x58021000 + + + GPIOF + 0x58021400 + + + GPIOG + 0x58021800 + + + GPIOH + 0x58021C00 + + + GPIOI + 0x58022000 + + + GPIOJ + 0x58022400 + + + GPIOK + 0x58022800 + + + JPEG + JPEG + JPEG + 0x52003000 + + 0x0 + 0x400 + registers + + + JPEG + JPEG global interrupt + 121 + + + + CONFR0 + CONFR0 + JPEG codec control register + 0x0 + 0x20 + write-only + 0x00000000 + + + START + Start This bit start or stop the + encoding or decoding process. Read this register + always return 0. + 0 + 1 + + + + + CONFR1 + CONFR1 + JPEG codec configuration register + 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + NF + Number of color components This field + defines the number of color components minus + 1. + 0 + 2 + + + DE + Decoding Enable This bit selects the + coding or decoding process + 3 + 1 + + + COLORSPACE + Color Space This filed defines the + number of quantization tables minus 1 to insert in + the output stream. + 4 + 2 + + + NS + Number of components for Scan This field + defines the number of components minus 1 for scan + header marker segment. + 6 + 2 + + + HDR + Header Processing This bit enable the + header processing (generation/parsing). + 8 + 1 + + + YSIZE + Y Size This field defines the number of + lines in source image. + 16 + 16 + + + + + CONFR2 + CONFR2 + JPEG codec configuration register + 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + NMCU + Number of MCU For encoding: this field + defines the number of MCU units minus 1 to encode. + For decoding: this field indicates the number of + complete MCU units minus 1 to be decoded (this field + is updated after the JPEG header parsing). If the + decoded image size has not a X or Y size multiple of + 8 or 16 (depending on the sub-sampling process), the + resulting incomplete or empty MCU must be added to + this value to get the total number of MCU + generated. + 0 + 26 + + + + + CONFR3 + CONFR3 + JPEG codec configuration register + 3 + 0xC + 0x20 + read-write + 0x00000000 + + + XSIZE + X size This field defines the number of + pixels per line. + 16 + 16 + + + + + CONFRN1 + CONFRN1 + JPEG codec configuration register + 4-7 + 0x10 + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CONFRN2 + CONFRN2 + JPEG codec configuration register + 4-7 + 0x14 + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CONFRN3 + CONFRN3 + JPEG codec configuration register + 4-7 + 0x18 + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CONFRN4 + CONFRN4 + JPEG codec configuration register + 4-7 + 0x1C + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CR + CR + JPEG control register + 0x30 + 0x20 + read-write + 0x00000000 + + + JCEN + JPEG Core Enable Enable the JPEG codec + Core. + 0 + 1 + + + IFTIE + Input FIFO Threshold Interrupt Enable + This bit enables the interrupt generation when input + FIFO reach the threshold. + 1 + 1 + + + IFNFIE + Input FIFO Not Full Interrupt Enable + This bit enables the interrupt generation when input + FIFO is not empty. + 2 + 1 + + + OFTIE + Output FIFO Threshold Interrupt Enable + This bit enables the interrupt generation when output + FIFO reach the threshold. + 3 + 1 + + + OFNEIE + Output FIFO Not Empty Interrupt Enable + This bit enables the interrupt generation when output + FIFO is not empty. + 4 + 1 + + + EOCIE + End of Conversion Interrupt Enable This + bit enables the interrupt generation on the end of + conversion. + 5 + 1 + + + HPDIE + Header Parsing Done Interrupt Enable + This bit enables the interrupt generation on the + Header Parsing Operation. + 6 + 1 + + + IDMAEN + Input DMA Enable Enable the DMA request + generation for the input FIFO. + 11 + 1 + + + ODMAEN + Output DMA Enable Enable the DMA request + generation for the output FIFO. + 12 + 1 + + + IFF + Input FIFO Flush This bit flush the + input FIFO. This bit is always read as + 0. + 13 + 1 + + + OFF + Output FIFO Flush This bit flush the + output FIFO. This bit is always read as + 0. + 14 + 1 + + + + + SR + SR + JPEG status register + 0x34 + 0x20 + read-only + 0x00000006 + + + IFTF + Input FIFO Threshold Flag This bit is + set when the input FIFO is not full and is bellow its + threshold. + 1 + 1 + + + IFNFF + Input FIFO Not Full Flag This bit is set + when the input FIFO is not full (a data can be + written). + 2 + 1 + + + OFTF + Output FIFO Threshold Flag This bit is + set when the output FIFO is not empty and has reach + its threshold. + 3 + 1 + + + OFNEF + Output FIFO Not Empty Flag This bit is + set when the output FIFO is not empty (a data is + available). + 4 + 1 + + + EOCF + End of Conversion Flag This bit is set + when the JPEG codec core has finished the encoding or + the decoding process and than last data has been sent + to the output FIFO. + 5 + 1 + + + HPDF + Header Parsing Done Flag This bit is set + in decode mode when the JPEG codec has finished the + parsing of the headers and the internal registers + have been updated. + 6 + 1 + + + COF + Codec Operation Flag This bit is set + when when a JPEG codec operation is on going + (encoding or decoding). + 7 + 1 + + + + + CFR + CFR + JPEG clear flag register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEOCF + Clear End of Conversion Flag Writing 1 + clears the End of Conversion Flag of the JPEG Status + Register. + 5 + 1 + + + CHPDF + Clear Header Parsing Done Flag Writing 1 + clears the Header Parsing Done Flag of the JPEG + Status Register. + 6 + 1 + + + + + DIR + DIR + JPEG data input register + 0x40 + 0x20 + write-only + 0x00000000 + + + DATAIN + Data Input FIFO Input FIFO data + register. + 0 + 32 + + + + + DOR + DOR + JPEG data output register + 0x44 + 0x20 + read-only + 0x00000000 + + + DATAOUT + Data Output FIFO Output FIFO data + register. + 0 + 32 + + + + + + + MDMA + MDMA + MDMA + 0x52000000 + + 0x0 + 0x1000 + registers + + + MDMA + MDMA + 122 + + + + MDMA_GISR0 + MDMA_GISR0 + MDMA Global Interrupt/Status + Register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 0 + 1 + + + GIF1 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 1 + 1 + + + GIF2 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 2 + 1 + + + GIF3 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 3 + 1 + + + GIF4 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 4 + 1 + + + GIF5 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 5 + 1 + + + GIF6 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 6 + 1 + + + GIF7 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 7 + 1 + + + GIF8 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 8 + 1 + + + GIF9 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 9 + 1 + + + GIF10 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 10 + 1 + + + GIF11 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 11 + 1 + + + GIF12 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 12 + 1 + + + GIF13 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 13 + 1 + + + GIF14 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 14 + 1 + + + GIF15 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 15 + 1 + + + + + MDMA_C0ISR + MDMA_C0ISR + MDMA channel x interrupt/status + register + 0x40 + 0x20 + read-only + 0x00000000 + + + TEIF0 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF0 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF0 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF0 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF0 + channel x buffer transfer + complete + 4 + 1 + + + CRQA0 + channel x request active + flag + 16 + 1 + + + + + MDMA_C0IFCR + MDMA_C0IFCR + MDMA channel x interrupt flag clear + register + 0x44 + 0x20 + write-only + 0x00000000 + + + CTEIF0 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF0 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF0 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF0 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF0 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C0ESR + MDMA_C0ESR + MDMA Channel x error status + register + 0x48 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C0CR + MDMA_C0CR + This register is used to control the + concerned channel. + 0x4C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C0TCR + MDMA_C0TCR + This register is used to configure the + concerned channel. + 0x50 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C0BNDTR + MDMA_C0BNDTR + MDMA Channel x block number of data + register + 0x54 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C0SAR + MDMA_C0SAR + MDMA channel x source address + register + 0x58 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C0DAR + MDMA_C0DAR + MDMA channel x destination address + register + 0x5C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C0BRUR + MDMA_C0BRUR + MDMA channel x Block Repeat address Update + register + 0x60 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C0LAR + MDMA_C0LAR + MDMA channel x Link Address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C0TBR + MDMA_C0TBR + MDMA channel x Trigger and Bus selection + Register + 0x68 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C0MAR + MDMA_C0MAR + MDMA channel x Mask address + register + 0x70 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C0MDR + MDMA_C0MDR + MDMA channel x Mask Data + register + 0x74 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C1ISR + MDMA_C1ISR + MDMA channel x interrupt/status + register + 0x80 + 0x20 + read-only + 0x00000000 + + + TEIF1 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF1 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF1 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF1 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF1 + channel x buffer transfer + complete + 4 + 1 + + + CRQA1 + channel x request active + flag + 16 + 1 + + + + + MDMA_C1IFCR + MDMA_C1IFCR + MDMA channel x interrupt flag clear + register + 0x84 + 0x20 + write-only + 0x00000000 + + + CTEIF1 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF1 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF1 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF1 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF1 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C1ESR + MDMA_C1ESR + MDMA Channel x error status + register + 0x88 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C1CR + MDMA_C1CR + This register is used to control the + concerned channel. + 0x8C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C1TCR + MDMA_C1TCR + This register is used to configure the + concerned channel. + 0x90 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C1BNDTR + MDMA_C1BNDTR + MDMA Channel x block number of data + register + 0x94 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C1SAR + MDMA_C1SAR + MDMA channel x source address + register + 0x98 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C1DAR + MDMA_C1DAR + MDMA channel x destination address + register + 0x9C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C1BRUR + MDMA_C1BRUR + MDMA channel x Block Repeat address Update + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C1LAR + MDMA_C1LAR + MDMA channel x Link Address + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C1TBR + MDMA_C1TBR + MDMA channel x Trigger and Bus selection + Register + 0xA8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C1MAR + MDMA_C1MAR + MDMA channel x Mask address + register + 0xB0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C1MDR + MDMA_C1MDR + MDMA channel x Mask Data + register + 0xB4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C2ISR + MDMA_C2ISR + MDMA channel x interrupt/status + register + 0xC0 + 0x20 + read-only + 0x00000000 + + + TEIF2 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF2 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF2 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF2 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF2 + channel x buffer transfer + complete + 4 + 1 + + + CRQA2 + channel x request active + flag + 16 + 1 + + + + + MDMA_C2IFCR + MDMA_C2IFCR + MDMA channel x interrupt flag clear + register + 0xC4 + 0x20 + write-only + 0x00000000 + + + CTEIF2 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF2 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF2 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF2 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF2 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C2ESR + MDMA_C2ESR + MDMA Channel x error status + register + 0xC8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C2CR + MDMA_C2CR + This register is used to control the + concerned channel. + 0xCC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C2TCR + MDMA_C2TCR + This register is used to configure the + concerned channel. + 0xD0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C2BNDTR + MDMA_C2BNDTR + MDMA Channel x block number of data + register + 0xD4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C2SAR + MDMA_C2SAR + MDMA channel x source address + register + 0xD8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C2DAR + MDMA_C2DAR + MDMA channel x destination address + register + 0xDC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C2BRUR + MDMA_C2BRUR + MDMA channel x Block Repeat address Update + register + 0xE0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C2LAR + MDMA_C2LAR + MDMA channel x Link Address + register + 0xE4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C2TBR + MDMA_C2TBR + MDMA channel x Trigger and Bus selection + Register + 0xE8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C2MAR + MDMA_C2MAR + MDMA channel x Mask address + register + 0xF0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C2MDR + MDMA_C2MDR + MDMA channel x Mask Data + register + 0xF4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C3ISR + MDMA_C3ISR + MDMA channel x interrupt/status + register + 0x100 + 0x20 + read-only + 0x00000000 + + + TEIF3 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF3 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF3 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF3 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF3 + channel x buffer transfer + complete + 4 + 1 + + + CRQA3 + channel x request active + flag + 16 + 1 + + + + + MDMA_C3IFCR + MDMA_C3IFCR + MDMA channel x interrupt flag clear + register + 0x104 + 0x20 + write-only + 0x00000000 + + + CTEIF3 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF3 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF3 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF3 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF3 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C3ESR + MDMA_C3ESR + MDMA Channel x error status + register + 0x108 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C3CR + MDMA_C3CR + This register is used to control the + concerned channel. + 0x10C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C3TCR + MDMA_C3TCR + This register is used to configure the + concerned channel. + 0x110 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C3BNDTR + MDMA_C3BNDTR + MDMA Channel x block number of data + register + 0x114 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C3SAR + MDMA_C3SAR + MDMA channel x source address + register + 0x118 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C3DAR + MDMA_C3DAR + MDMA channel x destination address + register + 0x11C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C3BRUR + MDMA_C3BRUR + MDMA channel x Block Repeat address Update + register + 0x120 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C3LAR + MDMA_C3LAR + MDMA channel x Link Address + register + 0x124 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C3TBR + MDMA_C3TBR + MDMA channel x Trigger and Bus selection + Register + 0x128 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C3MAR + MDMA_C3MAR + MDMA channel x Mask address + register + 0x130 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C3MDR + MDMA_C3MDR + MDMA channel x Mask Data + register + 0x134 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C4ISR + MDMA_C4ISR + MDMA channel x interrupt/status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + TEIF4 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF4 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF4 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF4 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF4 + channel x buffer transfer + complete + 4 + 1 + + + CRQA4 + channel x request active + flag + 16 + 1 + + + + + MDMA_C4IFCR + MDMA_C4IFCR + MDMA channel x interrupt flag clear + register + 0x144 + 0x20 + write-only + 0x00000000 + + + CTEIF4 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF4 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF4 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF4 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF4 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C4ESR + MDMA_C4ESR + MDMA Channel x error status + register + 0x148 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C4CR + MDMA_C4CR + This register is used to control the + concerned channel. + 0x14C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C4TCR + MDMA_C4TCR + This register is used to configure the + concerned channel. + 0x150 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C4BNDTR + MDMA_C4BNDTR + MDMA Channel x block number of data + register + 0x154 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C4SAR + MDMA_C4SAR + MDMA channel x source address + register + 0x158 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C4DAR + MDMA_C4DAR + MDMA channel x destination address + register + 0x15C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C4BRUR + MDMA_C4BRUR + MDMA channel x Block Repeat address Update + register + 0x160 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C4LAR + MDMA_C4LAR + MDMA channel x Link Address + register + 0x164 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C4TBR + MDMA_C4TBR + MDMA channel x Trigger and Bus selection + Register + 0x168 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C4MAR + MDMA_C4MAR + MDMA channel x Mask address + register + 0x170 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C4MDR + MDMA_C4MDR + MDMA channel x Mask Data + register + 0x174 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C5ISR + MDMA_C5ISR + MDMA channel x interrupt/status + register + 0x180 + 0x20 + read-only + 0x00000000 + + + TEIF5 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF5 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF5 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF5 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF5 + channel x buffer transfer + complete + 4 + 1 + + + CRQA5 + channel x request active + flag + 16 + 1 + + + + + MDMA_C5IFCR + MDMA_C5IFCR + MDMA channel x interrupt flag clear + register + 0x184 + 0x20 + write-only + 0x00000000 + + + CTEIF5 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF5 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF5 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF5 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF5 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C5ESR + MDMA_C5ESR + MDMA Channel x error status + register + 0x188 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C5CR + MDMA_C5CR + This register is used to control the + concerned channel. + 0x18C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C5TCR + MDMA_C5TCR + This register is used to configure the + concerned channel. + 0x190 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C5BNDTR + MDMA_C5BNDTR + MDMA Channel x block number of data + register + 0x194 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C5SAR + MDMA_C5SAR + MDMA channel x source address + register + 0x198 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C5DAR + MDMA_C5DAR + MDMA channel x destination address + register + 0x19C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C5BRUR + MDMA_C5BRUR + MDMA channel x Block Repeat address Update + register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C5LAR + MDMA_C5LAR + MDMA channel x Link Address + register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C5TBR + MDMA_C5TBR + MDMA channel x Trigger and Bus selection + Register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C5MAR + MDMA_C5MAR + MDMA channel x Mask address + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C5MDR + MDMA_C5MDR + MDMA channel x Mask Data + register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C6ISR + MDMA_C6ISR + MDMA channel x interrupt/status + register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + TEIF6 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF6 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF6 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF6 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF6 + channel x buffer transfer + complete + 4 + 1 + + + CRQA6 + channel x request active + flag + 16 + 1 + + + + + MDMA_C6IFCR + MDMA_C6IFCR + MDMA channel x interrupt flag clear + register + 0x1C4 + 0x20 + write-only + 0x00000000 + + + CTEIF6 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF6 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF6 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF6 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF6 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C6ESR + MDMA_C6ESR + MDMA Channel x error status + register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C6CR + MDMA_C6CR + This register is used to control the + concerned channel. + 0x1CC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C6TCR + MDMA_C6TCR + This register is used to configure the + concerned channel. + 0x1D0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C6BNDTR + MDMA_C6BNDTR + MDMA Channel x block number of data + register + 0x1D4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0 + 20 + 12 + + + + + MDMA_C6SAR + MDMA_C6SAR + MDMA channel x source address + register + 0x1D8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C6DAR + MDMA_C6DAR + MDMA channel x destination address + register + 0x1DC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C6BRUR + MDMA_C6BRUR + MDMA channel x Block Repeat address Update + register + 0x1E0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C6LAR + MDMA_C6LAR + MDMA channel x Link Address + register + 0x1E4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C6TBR + MDMA_C6TBR + MDMA channel x Trigger and Bus selection + Register + 0x1E8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C6MAR + MDMA_C6MAR + MDMA channel x Mask address + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C6MDR + MDMA_C6MDR + MDMA channel x Mask Data + register + 0x1F4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C7ISR + MDMA_C7ISR + MDMA channel x interrupt/status + register + 0x200 + 0x20 + read-only + 0x00000000 + + + TEIF7 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF7 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF7 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF7 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF7 + channel x buffer transfer + complete + 4 + 1 + + + CRQA7 + channel x request active + flag + 16 + 1 + + + + + MDMA_C7IFCR + MDMA_C7IFCR + MDMA channel x interrupt flag clear + register + 0x204 + 0x20 + write-only + 0x00000000 + + + CTEIF7 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF7 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF7 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF7 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF7 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C7ESR + MDMA_C7ESR + MDMA Channel x error status + register + 0x208 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C7CR + MDMA_C7CR + This register is used to control the + concerned channel. + 0x20C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C7TCR + MDMA_C7TCR + This register is used to configure the + concerned channel. + 0x210 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C7BNDTR + MDMA_C7BNDTR + MDMA Channel x block number of data + register + 0x214 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C7SAR + MDMA_C7SAR + MDMA channel x source address + register + 0x218 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C7DAR + MDMA_C7DAR + MDMA channel x destination address + register + 0x21C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C7BRUR + MDMA_C7BRUR + MDMA channel x Block Repeat address Update + register + 0x220 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C7LAR + MDMA_C7LAR + MDMA channel x Link Address + register + 0x224 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C7TBR + MDMA_C7TBR + MDMA channel x Trigger and Bus selection + Register + 0x228 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C7MAR + MDMA_C7MAR + MDMA channel x Mask address + register + 0x230 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C7MDR + MDMA_C7MDR + MDMA channel x Mask Data + register + 0x234 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C8ISR + MDMA_C8ISR + MDMA channel x interrupt/status + register + 0x240 + 0x20 + read-only + 0x00000000 + + + TEIF8 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF8 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF8 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF8 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF8 + channel x buffer transfer + complete + 4 + 1 + + + CRQA8 + channel x request active + flag + 16 + 1 + + + + + MDMA_C8IFCR + MDMA_C8IFCR + MDMA channel x interrupt flag clear + register + 0x244 + 0x20 + write-only + 0x00000000 + + + CTEIF8 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF8 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF8 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF8 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF8 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C8ESR + MDMA_C8ESR + MDMA Channel x error status + register + 0x248 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C8CR + MDMA_C8CR + This register is used to control the + concerned channel. + 0x24C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C8TCR + MDMA_C8TCR + This register is used to configure the + concerned channel. + 0x250 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C8BNDTR + MDMA_C8BNDTR + MDMA Channel x block number of data + register + 0x254 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C8SAR + MDMA_C8SAR + MDMA channel x source address + register + 0x258 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C8DAR + MDMA_C8DAR + MDMA channel x destination address + register + 0x25C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C8BRUR + MDMA_C8BRUR + MDMA channel x Block Repeat address Update + register + 0x260 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C8LAR + MDMA_C8LAR + MDMA channel x Link Address + register + 0x264 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C8TBR + MDMA_C8TBR + MDMA channel x Trigger and Bus selection + Register + 0x268 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C8MAR + MDMA_C8MAR + MDMA channel x Mask address + register + 0x270 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C8MDR + MDMA_C8MDR + MDMA channel x Mask Data + register + 0x274 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C9ISR + MDMA_C9ISR + MDMA channel x interrupt/status + register + 0x280 + 0x20 + read-only + 0x00000000 + + + TEIF9 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF9 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF9 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF9 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF9 + channel x buffer transfer + complete + 4 + 1 + + + CRQA9 + channel x request active + flag + 16 + 1 + + + + + MDMA_C9IFCR + MDMA_C9IFCR + MDMA channel x interrupt flag clear + register + 0x284 + 0x20 + write-only + 0x00000000 + + + CTEIF9 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF9 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF9 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF9 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF9 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C9ESR + MDMA_C9ESR + MDMA Channel x error status + register + 0x288 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C9CR + MDMA_C9CR + This register is used to control the + concerned channel. + 0x28C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C9TCR + MDMA_C9TCR + This register is used to configure the + concerned channel. + 0x290 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C9BNDTR + MDMA_C9BNDTR + MDMA Channel x block number of data + register + 0x294 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C9SAR + MDMA_C9SAR + MDMA channel x source address + register + 0x298 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C9DAR + MDMA_C9DAR + MDMA channel x destination address + register + 0x29C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C9BRUR + MDMA_C9BRUR + MDMA channel x Block Repeat address Update + register + 0x2A0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C9LAR + MDMA_C9LAR + MDMA channel x Link Address + register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C9TBR + MDMA_C9TBR + MDMA channel x Trigger and Bus selection + Register + 0x2A8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C9MAR + MDMA_C9MAR + MDMA channel x Mask address + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C9MDR + MDMA_C9MDR + MDMA channel x Mask Data + register + 0x2B4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C10ISR + MDMA_C10ISR + MDMA channel x interrupt/status + register + 0x2C0 + 0x20 + read-only + 0x00000000 + + + TEIF10 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF10 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF10 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF10 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF10 + channel x buffer transfer + complete + 4 + 1 + + + CRQA10 + channel x request active + flag + 16 + 1 + + + + + MDMA_C10IFCR + MDMA_C10IFCR + MDMA channel x interrupt flag clear + register + 0x2C4 + 0x20 + write-only + 0x00000000 + + + CTEIF10 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF10 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF10 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF10 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF10 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C10ESR + MDMA_C10ESR + MDMA Channel x error status + register + 0x2C8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C10CR + MDMA_C10CR + This register is used to control the + concerned channel. + 0x2CC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C10TCR + MDMA_C10TCR + This register is used to configure the + concerned channel. + 0x2D0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C10BNDTR + MDMA_C10BNDTR + MDMA Channel x block number of data + register + 0x2D4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C10SAR + MDMA_C10SAR + MDMA channel x source address + register + 0x2D8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C10DAR + MDMA_C10DAR + MDMA channel x destination address + register + 0x2DC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C10BRUR + MDMA_C10BRUR + MDMA channel x Block Repeat address Update + register + 0x2E0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C10LAR + MDMA_C10LAR + MDMA channel x Link Address + register + 0x2E4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C10TBR + MDMA_C10TBR + MDMA channel x Trigger and Bus selection + Register + 0x2E8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C10MAR + MDMA_C10MAR + MDMA channel x Mask address + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C10MDR + MDMA_C10MDR + MDMA channel x Mask Data + register + 0x2F4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C11ISR + MDMA_C11ISR + MDMA channel x interrupt/status + register + 0x300 + 0x20 + read-only + 0x00000000 + + + TEIF11 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF11 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF11 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF11 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF11 + channel x buffer transfer + complete + 4 + 1 + + + CRQA11 + channel x request active + flag + 16 + 1 + + + + + MDMA_C11IFCR + MDMA_C11IFCR + MDMA channel x interrupt flag clear + register + 0x304 + 0x20 + write-only + 0x00000000 + + + CTEIF11 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF11 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF11 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF11 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF11 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C11ESR + MDMA_C11ESR + MDMA Channel x error status + register + 0x308 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C11CR + MDMA_C11CR + This register is used to control the + concerned channel. + 0x30C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C11TCR + MDMA_C11TCR + This register is used to configure the + concerned channel. + 0x310 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C11BNDTR + MDMA_C11BNDTR + MDMA Channel x block number of data + register + 0x314 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C11SAR + MDMA_C11SAR + MDMA channel x source address + register + 0x318 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C11DAR + MDMA_C11DAR + MDMA channel x destination address + register + 0x31C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C11BRUR + MDMA_C11BRUR + MDMA channel x Block Repeat address Update + register + 0x320 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C11LAR + MDMA_C11LAR + MDMA channel x Link Address + register + 0x324 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C11TBR + MDMA_C11TBR + MDMA channel x Trigger and Bus selection + Register + 0x328 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C11MAR + MDMA_C11MAR + MDMA channel x Mask address + register + 0x330 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C11MDR + MDMA_C11MDR + MDMA channel x Mask Data + register + 0x334 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C12ISR + MDMA_C12ISR + MDMA channel x interrupt/status + register + 0x340 + 0x20 + read-only + 0x00000000 + + + TEIF12 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF12 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF12 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF12 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF12 + channel x buffer transfer + complete + 4 + 1 + + + CRQA12 + channel x request active + flag + 16 + 1 + + + + + MDMA_C12IFCR + MDMA_C12IFCR + MDMA channel x interrupt flag clear + register + 0x344 + 0x20 + write-only + 0x00000000 + + + CTEIF12 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF12 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF12 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF12 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF12 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C12ESR + MDMA_C12ESR + MDMA Channel x error status + register + 0x348 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C12CR + MDMA_C12CR + This register is used to control the + concerned channel. + 0x34C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C12TCR + MDMA_C12TCR + This register is used to configure the + concerned channel. + 0x350 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C12BNDTR + MDMA_C12BNDTR + MDMA Channel x block number of data + register + 0x354 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C12SAR + MDMA_C12SAR + MDMA channel x source address + register + 0x358 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C12DAR + MDMA_C12DAR + MDMA channel x destination address + register + 0x35C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C12BRUR + MDMA_C12BRUR + MDMA channel x Block Repeat address Update + register + 0x360 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C12LAR + MDMA_C12LAR + MDMA channel x Link Address + register + 0x364 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C12TBR + MDMA_C12TBR + MDMA channel x Trigger and Bus selection + Register + 0x368 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C12MAR + MDMA_C12MAR + MDMA channel x Mask address + register + 0x370 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C12MDR + MDMA_C12MDR + MDMA channel x Mask Data + register + 0x374 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C13ISR + MDMA_C13ISR + MDMA channel x interrupt/status + register + 0x380 + 0x20 + read-only + 0x00000000 + + + TEIF13 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF13 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF13 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF13 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF13 + channel x buffer transfer + complete + 4 + 1 + + + CRQA13 + channel x request active + flag + 16 + 1 + + + + + MDMA_C13IFCR + MDMA_C13IFCR + MDMA channel x interrupt flag clear + register + 0x384 + 0x20 + write-only + 0x00000000 + + + CTEIF13 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF13 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF13 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF13 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF13 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C13ESR + MDMA_C13ESR + MDMA Channel x error status + register + 0x388 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C13CR + MDMA_C13CR + This register is used to control the + concerned channel. + 0x38C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C13TCR + MDMA_C13TCR + This register is used to configure the + concerned channel. + 0x390 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C13BNDTR + MDMA_C13BNDTR + MDMA Channel x block number of data + register + 0x394 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C13SAR + MDMA_C13SAR + MDMA channel x source address + register + 0x398 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C13DAR + MDMA_C13DAR + MDMA channel x destination address + register + 0x39C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C13BRUR + MDMA_C13BRUR + MDMA channel x Block Repeat address Update + register + 0x3A0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C13LAR + MDMA_C13LAR + MDMA channel x Link Address + register + 0x3A4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C13TBR + MDMA_C13TBR + MDMA channel x Trigger and Bus selection + Register + 0x3A8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C13MAR + MDMA_C13MAR + MDMA channel x Mask address + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C13MDR + MDMA_C13MDR + MDMA channel x Mask Data + register + 0x3B4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C14ISR + MDMA_C14ISR + MDMA channel x interrupt/status + register + 0x3C0 + 0x20 + read-only + 0x00000000 + + + TEIF14 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF14 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF14 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF14 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF14 + channel x buffer transfer + complete + 4 + 1 + + + CRQA14 + channel x request active + flag + 16 + 1 + + + + + MDMA_C14IFCR + MDMA_C14IFCR + MDMA channel x interrupt flag clear + register + 0x3C4 + 0x20 + write-only + 0x00000000 + + + CTEIF14 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF14 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF14 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF14 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF14 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C14ESR + MDMA_C14ESR + MDMA Channel x error status + register + 0x3C8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C14CR + MDMA_C14CR + This register is used to control the + concerned channel. + 0x3CC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C14TCR + MDMA_C14TCR + This register is used to configure the + concerned channel. + 0x3D0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C14BNDTR + MDMA_C14BNDTR + MDMA Channel x block number of data + register + 0x3D4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C14SAR + MDMA_C14SAR + MDMA channel x source address + register + 0x3D8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C14DAR + MDMA_C14DAR + MDMA channel x destination address + register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C14BRUR + MDMA_C14BRUR + MDMA channel x Block Repeat address Update + register + 0x3E0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C14LAR + MDMA_C14LAR + MDMA channel x Link Address + register + 0x3E4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C14TBR + MDMA_C14TBR + MDMA channel x Trigger and Bus selection + Register + 0x3E8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C14MAR + MDMA_C14MAR + MDMA channel x Mask address + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C14MDR + MDMA_C14MDR + MDMA channel x Mask Data + register + 0x3F4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C15ISR + MDMA_C15ISR + MDMA channel x interrupt/status + register + 0x400 + 0x20 + read-only + 0x00000000 + + + TEIF15 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF15 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF15 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF15 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF15 + channel x buffer transfer + complete + 4 + 1 + + + CRQA15 + channel x request active + flag + 16 + 1 + + + + + MDMA_C15IFCR + MDMA_C15IFCR + MDMA channel x interrupt flag clear + register + 0x404 + 0x20 + write-only + 0x00000000 + + + CTEIF15 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF15 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF15 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF15 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF15 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C15ESR + MDMA_C15ESR + MDMA Channel x error status + register + 0x408 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C15CR + MDMA_C15CR + This register is used to control the + concerned channel. + 0x40C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C15TCR + MDMA_C15TCR + This register is used to configure the + concerned channel. + 0x410 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C15BNDTR + MDMA_C15BNDTR + MDMA Channel x block number of data + register + 0x414 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C15SAR + MDMA_C15SAR + MDMA channel x source address + register + 0x418 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C15DAR + MDMA_C15DAR + MDMA channel x destination address + register + 0x41C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C15BRUR + MDMA_C15BRUR + MDMA channel x Block Repeat address Update + register + 0x420 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C15LAR + MDMA_C15LAR + MDMA channel x Link Address + register + 0x424 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C15TBR + MDMA_C15TBR + MDMA channel x Trigger and Bus selection + Register + 0x428 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C15MAR + MDMA_C15MAR + MDMA channel x Mask address + register + 0x430 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C15MDR + MDMA_C15MDR + MDMA channel x Mask Data + register + 0x434 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + + + QUADSPI + QUADSPI + QUADSPI + 0x52005000 + + 0x0 + 0x400 + registers + + + QUADSPI + QuadSPI global interrupt + 92 + + + + CR + CR + QUADSPI control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + Enable Enable the QUADSPI. + 0 + 1 + + + ABORT + Abort request This bit aborts the + on-going command sequence. It is automatically reset + once the abort is complete. This bit stops the + current transfer. In polling mode or memory-mapped + mode, this bit also reset the APM bit or the DM + bit. + 1 + 1 + + + DMAEN + DMA enable In indirect mode, DMA can be + used to input or output data via the QUADSPI_DR + register. DMA transfers are initiated when the FIFO + threshold flag, FTF, is set. + 2 + 1 + + + TCEN + Timeout counter enable This bit is valid + only when memory-mapped mode (FMODE = 11) is + selected. Activating this bit causes the chip select + (nCS) to be released (and thus reduces consumption) + if there has not been an access after a certain + amount of time, where this time is defined by + TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout + counter. By default, the QUADSPI never stops its + prefetch operation, keeping the previous read + operation active with nCS maintained low, even if no + access to the Flash memory occurs for a long time. + Since Flash memories tend to consume more when nCS is + held low, the application might want to activate the + timeout counter (TCEN = 1, QUADSPI_CR[3]) so that nCS + is released after a period of TIMEOUT[15:0] + (QUADSPI_LPTR) cycles have elapsed without an access + since when the FIFO becomes full with prefetch data. + This bit can be modified only when BUSY = + 0. + 3 + 1 + + + SSHIFT + Sample shift By default, the QUADSPI + samples data 1/2 of a CLK cycle after the data is + driven by the Flash memory. This bit allows the data + is to be sampled later in order to account for + external signal delays. Firmware must assure that + SSHIFT = 0 when in DDR mode (when DDRM = 1). This + field can be modified only when BUSY = + 0. + 4 + 1 + + + DFM + Dual-flash mode This bit activates + dual-flash mode, where two external Flash memories + are used simultaneously to double throughput and + capacity. This bit can be modified only when BUSY = + 0. + 6 + 1 + + + FSEL + Flash memory selection This bit selects + the Flash memory to be addressed in single flash mode + (when DFM = 0). This bit can be modified only when + BUSY = 0. This bit is ignored when DFM = + 1. + 7 + 1 + + + FTHRES + FIFO threshold level Defines, in + indirect mode, the threshold number of bytes in the + FIFO that will cause the FIFO threshold flag (FTF, + QUADSPI_SR[2]) to be set. In indirect write mode + (FMODE = 00): ... In indirect read mode (FMODE = 01): + ... If DMAEN = 1, then the DMA controller for the + corresponding channel must be disabled before + changing the FTHRES value. + 8 + 5 + + + TEIE + Transfer error interrupt enable This bit + enables the transfer error interrupt. + 16 + 1 + + + TCIE + Transfer complete interrupt enable This + bit enables the transfer complete + interrupt. + 17 + 1 + + + FTIE + FIFO threshold interrupt enable This bit + enables the FIFO threshold interrupt. + 18 + 1 + + + SMIE + Status match interrupt enable This bit + enables the status match interrupt. + 19 + 1 + + + TOIE + TimeOut interrupt enable This bit + enables the TimeOut interrupt. + 20 + 1 + + + APMS + Automatic poll mode stop This bit + determines if automatic polling is stopped after a + match. This bit can be modified only when BUSY = + 0. + 22 + 1 + + + PMM + Polling match mode This bit indicates + which method should be used for determining a match + during automatic polling mode. This bit can be + modified only when BUSY = 0. + 23 + 1 + + + PRESCALER + clock prescaler + 24 + 8 + + + + + DCR + DCR + QUADSPI device configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + CKMODE + indicates the level that clk takes + between command + 0 + 1 + + + CSHT + Chip select high time CSHT+1 defines the + minimum number of CLK cycles which the chip select + (nCS) must remain high between commands issued to the + Flash memory. ... This field can be modified only + when BUSY = 0. + 8 + 3 + + + FSIZE + Flash memory size This field defines the + size of external memory using the following formula: + Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 + is effectively the number of address bits required to + address the Flash memory. The Flash memory capacity + can be up to 4GB (addressed using 32 bits) in + indirect mode, but the addressable space in + memory-mapped mode is limited to 256MB. If DFM = 1, + FSIZE indicates the total capacity of the two Flash + memories together. This field can be modified only + when BUSY = 0. + 16 + 5 + + + + + SR + SR + QUADSPI status register + 0x8 + 0x20 + read-only + 0x00000000 + + + TEF + Transfer error flag This bit is set in + indirect mode when an invalid address is being + accessed in indirect mode. It is cleared by writing 1 + to CTEF. + 0 + 1 + + + TCF + Transfer complete flag This bit is set + in indirect mode when the programmed number of data + has been transferred or in any mode when the transfer + has been aborted.It is cleared by writing 1 to + CTCF. + 1 + 1 + + + FTF + FIFO threshold flag In indirect mode, + this bit is set when the FIFO threshold has been + reached, or if there is any data left in the FIFO + after reads from the Flash memory are complete. It is + cleared automatically as soon as threshold condition + is no longer true. In automatic polling mode this bit + is set every time the status register is read, and + the bit is cleared when the data register is + read. + 2 + 1 + + + SMF + Status match flag This bit is set in + automatic polling mode when the unmasked received + data matches the corresponding bits in the match + register (QUADSPI_PSMAR). It is cleared by writing 1 + to CSMF. + 3 + 1 + + + TOF + Timeout flag This bit is set when + timeout occurs. It is cleared by writing 1 to + CTOF. + 4 + 1 + + + BUSY + Busy This bit is set when an operation + is on going. This bit clears automatically when the + operation with the Flash memory is finished and the + FIFO is empty. + 5 + 1 + + + FLEVEL + FIFO level This field gives the number + of valid bytes which are being held in the FIFO. + FLEVEL = 0 when the FIFO is empty, and 16 when it is + full. In memory-mapped mode and in automatic status + polling mode, FLEVEL is zero. + 8 + 6 + + + + + FCR + FCR + QUADSPI flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTEF + Clear transfer error flag Writing 1 + clears the TEF flag in the QUADSPI_SR + register + 0 + 1 + + + CTCF + Clear transfer complete flag Writing 1 + clears the TCF flag in the QUADSPI_SR + register + 1 + 1 + + + CSMF + Clear status match flag Writing 1 clears + the SMF flag in the QUADSPI_SR register + 3 + 1 + + + CTOF + Clear timeout flag Writing 1 clears the + TOF flag in the QUADSPI_SR register + 4 + 1 + + + + + DLR + DLR + QUADSPI data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length Number of data to be + retrieved (value+1) in indirect and status-polling + modes. A value no greater than 3 (indicating 4 bytes) + should be used for status-polling mode. All 1s in + indirect mode means undefined length, where QUADSPI + will continue until the end of memory, as defined by + FSIZE. 0x0000_0000: 1 byte is to be transferred + 0x0000_0001: 2 bytes are to be transferred + 0x0000_0002: 3 bytes are to be transferred + 0x0000_0003: 4 bytes are to be transferred ... + 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be + transferred 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes + are to be transferred 0xFFFF_FFFF: undefined length + -- all bytes until the end of Flash memory (as + defined by FSIZE) are to be transferred. Continue + reading indefinitely if FSIZE = 0x1F. DL[0] is stuck + at 1 in dual-flash mode (DFM = 1) even when 0 is + written to this bit, thus assuring that each access + transfers an even number of bytes. This field has no + effect when in memory-mapped mode (FMODE = 10). This + field can be written only when BUSY = + 0. + 0 + 32 + + + + + CCR + CCR + QUADSPI communication configuration + register + 0x14 + 0x20 + read-write + 0x00000000 + + + INSTRUCTION + Instruction Instruction to be send to + the external SPI device. This field can be written + only when BUSY = 0. + 0 + 8 + + + IMODE + Instruction mode This field defines the + instruction phase mode of operation: This field can + be written only when BUSY = 0. + 8 + 2 + + + ADMODE + Address mode This field defines the + address phase mode of operation: This field can be + written only when BUSY = 0. + 10 + 2 + + + ADSIZE + Address size This bit defines address + size: This field can be written only when BUSY = + 0. + 12 + 2 + + + ABMODE + Alternate bytes mode This field defines + the alternate-bytes phase mode of operation: This + field can be written only when BUSY = + 0. + 14 + 2 + + + ABSIZE + Alternate bytes size This bit defines + alternate bytes size: This field can be written only + when BUSY = 0. + 16 + 2 + + + DCYC + Number of dummy cycles This field + defines the duration of the dummy phase. In both SDR + and DDR modes, it specifies a number of CLK cycles + (0-31). This field can be written only when BUSY = + 0. + 18 + 5 + + + DMODE + Data mode This field defines the data + phases mode of operation: This field also determines + the dummy phase mode of operation. This field can be + written only when BUSY = 0. + 24 + 2 + + + FMODE + Functional mode This field defines the + QUADSPI functional mode of operation. If DMAEN = 1 + already, then the DMA controller for the + corresponding channel must be disabled before + changing the FMODE value. This field can be written + only when BUSY = 0. + 26 + 2 + + + SIOO + Send instruction only once mode See + Section15.3.11: Sending the instruction only once on + page13. This bit has no effect when IMODE = 00. This + field can be written only when BUSY = + 0. + 28 + 1 + + + DHHC + DDR hold Delay the data output by 1/4 of + the QUADSPI output clock cycle in DDR mode: This + feature is only active in DDR mode. This field can be + written only when BUSY = 0. + 30 + 1 + + + DDRM + Double data rate mode This bit sets the + DDR mode for the address, alternate byte and data + phase: This field can be written only when BUSY = + 0. + 31 + 1 + + + + + AR + AR + QUADSPI address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + [31 0]: Address Address to be send to + the external Flash memory Writes to this field are + ignored when BUSY = 0 or when FMODE = 11 + (memory-mapped mode). In dual flash mode, ADDRESS[0] + is automatically stuck to 0 as the address should + always be even + 0 + 32 + + + + + ABR + ABR + QUADSPI alternate bytes + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + Alternate Bytes Optional data to be send + to the external SPI device right after the address. + This field can be written only when BUSY = + 0. + 0 + 32 + + + + + DR + DR + QUADSPI data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data Data to be sent/received to/from + the external SPI device. In indirect write mode, data + written to this register is stored on the FIFO before + it is sent to the Flash memory during the data phase. + If the FIFO is too full, a write operation is stalled + until the FIFO has enough space to accept the amount + of data being written. In indirect read mode, reading + this register gives (via the FIFO) the data which was + received from the Flash memory. If the FIFO does not + have as many bytes as requested by the read operation + and if BUSY=1, the read operation is stalled until + enough data is present or until the transfer is + complete, whichever happens first. In automatic + polling mode, this register contains the last data + read from the Flash memory (without masking). Word, + halfword, and byte accesses to this register are + supported. In indirect write mode, a byte write adds + 1 byte to the FIFO, a halfword write 2, and a word + write 4. Similarly, in indirect read mode, a byte + read removes 1 byte from the FIFO, a halfword read 2, + and a word read 4. Accesses in indirect mode must be + aligned to the bottom of this register: a byte read + must read DATA[7:0] and a halfword read must read + DATA[15:0]. + 0 + 32 + + + + + PSMKR + PSMKR + QUADSPI polling status mask + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask Mask to be applied to the + status bytes received in polling mode. For bit n: + This field can be written only when BUSY = + 0. + 0 + 32 + + + + + PSMAR + PSMAR + QUADSPI polling status match + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match Value to be compared with + the masked status register to get a match. This field + can be written only when BUSY = 0. + 0 + 32 + + + + + PIR + PIR + QUADSPI polling interval + register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval Number of CLK cycles + between to read during automatic polling phases. This + field can be written only when BUSY = + 0. + 0 + 16 + + + + + LPTR + LPTR + QUADSPI low-power timeout + register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period After each access in + memory-mapped mode, the QUADSPI prefetches the + subsequent bytes and holds these bytes in the FIFO. + This field indicates how many CLK cycles the QUADSPI + waits after the FIFO becomes full until it raises + nCS, putting the Flash memory in a lower-consumption + state. This field can be written only when BUSY = + 0. + 0 + 16 + + + + + + + RNG + RNG + RNG + 0x48021800 + + 0x0 + 0x400 + registers + + + + CR + CR + RNG control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RNGEN + Random number generator + enable + 2 + 1 + + + IE + Interrupt enable + 3 + 1 + + + CED + Clock error detection Note: The clock + error detection can be used only when ck_rc48 or + ck_pll1_q (ck_pll1_q = 48MHz) source is selected + otherwise, CED bit must be equal to 1. The clock + error detection cannot be enabled nor disabled on the + fly when RNG peripheral is enabled, to enable or + disable CED the RNG must be disabled. + 5 + 1 + + + + + SR + SR + RNG status register + 0x4 + 0x20 + 0x00000000 + + + DRDY + Data ready Note: If IE=1 in RNG_CR, an + interrupt is generated when DRDY=1. It can rise when + the peripheral is disabled. When the output buffer + becomes empty (after reading RNG_DR), this bit + returns to 0 until a new random value is + generated. + 0 + 1 + read-only + + + CECS + Clock error current status Note: This + bit is meaningless if CED (Clock error detection) bit + in RNG_CR is equal to 1. + 1 + 1 + read-only + + + SECS + Seed error current status ** More than + 64 consecutive bits at the same value (0 or 1) ** + More than 32 consecutive alternances of 0 and 1 + (0101010101...01) + 2 + 1 + read-only + + + CEIS + Clock error interrupt status This bit is + set at the same time as CECS. It is cleared by + writing it to 0. An interrupt is pending if IE = 1 in + the RNG_CR register. Note: This bit is meaningless if + CED (Clock error detection) bit in RNG_CR is equal to + 1. + 5 + 1 + read-write + + + SEIS + Seed error interrupt status This bit is + set at the same time as SECS. It is cleared by + writing it to 0. ** More than 64 consecutive bits at + the same value (0 or 1) ** More than 32 consecutive + alternances of 0 and 1 (0101010101...01) An interrupt + is pending if IE = 1 in the RNG_CR + register. + 6 + 1 + read-write + + + + + DR + DR + The RNG_DR register is a read-only register + that delivers a 32-bit random value when read. The + content of this register is valid when DRDY= 1, even if + RNGEN=0. + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data 32-bit random data which are + valid when DRDY=1. + 0 + 32 + + + + + + + RTC + RTC + RTC + 0x58004000 + + 0x0 + 0x400 + registers + + + RTC_TAMP_STAMP_CSS_LSE + RTC tamper, timestamp + 2 + + + RTC_WKUP + RTC Wakeup interrupt + 3 + + + RTC_ALARM + RTC alarms (A and B) + 41 + + + + RTC_TR + RTC_TR + The RTC_TR is the calendar time shadow + register. This register must be written in initialization + mode only. Refer to Calendar initialization and + configuration on page9 and Reading the calendar on + page10.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x0 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + RTC_DR + RTC_DR + The RTC_DR is the calendar date shadow + register. This register must be written in initialization + mode only. Refer to Calendar initialization and + configuration on page9 and Reading the calendar on + page10.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x4 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format + 0 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + MU + Month units in BCD format + 8 + 4 + + + MT + Month tens in BCD format + 12 + 1 + + + WDU + Week day units + 13 + 3 + + + YU + Year units in BCD format + 16 + 4 + + + YT + Year tens in BCD format + 20 + 4 + + + + + RTC_CR + RTC_CR + RTC control register + 0x8 + 0x20 + 0x00000000 + + + WUCKSEL + Wakeup clock selection + 0 + 3 + read-write + + + TSEDGE + Time-stamp event active edge TSE must be + reset when TSEDGE is changed to avoid unwanted TSF + setting. + 3 + 1 + read-write + + + REFCKON + RTC_REFIN reference clock detection + enable (50 or 60Hz) Note: PREDIV_S must be + 0x00FF. + 4 + 1 + read-write + + + BYPSHAD + Bypass the shadow registers Note: If the + frequency of the APB clock is less than seven times + the frequency of RTCCLK, BYPSHAD must be set to + 1. + 5 + 1 + read-write + + + FMT + Hour format + 6 + 1 + read-write + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + WUTE + Wakeup timer enable + 10 + 1 + read-write + + + TSE + timestamp enable + 11 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + read-write + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + read-write + + + ADD1H + Add 1 hour (summer time change) When + this bit is set outside initialization mode, 1 hour + is added to the calendar time. This bit is always + read as 0. + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) + When this bit is set outside initialization mode, 1 + hour is subtracted to the calendar time if the + current hour is not 0. This bit is always read as 0. + Setting this bit has no effect when current hour is + 0. + 17 + 1 + write-only + + + BKP + Backup This bit can be written by the + user to memorize whether the daylight saving time + change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection When COE=1, + this bit selects which signal is output on RTC_CALIB. + These frequencies are valid for RTCCLK at 32.768 kHz + and prescalers at their default values (PREDIV_A=127 + and PREDIV_S=255). Refer to Section24.3.15: + Calibration clock output + 19 + 1 + read-write + + + POL + Output polarity This bit is used to + configure the polarity of RTC_ALARM + output + 20 + 1 + read-write + + + OSEL + Output selection These bits are used to + select the flag to be routed to RTC_ALARM + output + 21 + 2 + read-write + + + COE + Calibration output enable This bit + enables the RTC_CALIB output + 23 + 1 + read-write + + + ITSE + timestamp on internal event + enable + 24 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + This register is write protected (except for + RTC_ISR[13:8] bits). The write access procedure is + described in RTC register write protection on + page9. + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag This bit is set by + hardware when Alarm A values can be changed, after + the ALRAE bit has been set to 0 in RTC_CR. It is + cleared by hardware in initialization + mode. + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag This bit is set by + hardware when Alarm B values can be changed, after + the ALRBE bit has been set to 0 in RTC_CR. It is + cleared by hardware in initialization + mode. + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag This bit is set + by hardware up to 2 RTCCLK cycles after the WUTE bit + has been set to 0 in RTC_CR, and is cleared up to 2 + RTCCLK cycles after the WUTE bit has been set to 1. + The wakeup timer values can be changed when WUTE bit + is cleared and WUTWF is set. + 2 + 1 + read-only + + + SHPF + Shift operation pending This flag is set + by hardware as soon as a shift operation is initiated + by a write to the RTC_SHIFTR register. It is cleared + by hardware when the corresponding shift operation + has been executed. Writing to the SHPF bit has no + effect. + 3 + 1 + read-only + + + INITS + Initialization status flag This bit is + set by hardware when the calendar year field is + different from 0 (Backup domain reset + state). + 4 + 1 + read-only + + + RSF + Registers synchronization flag This bit + is set by hardware each time the calendar registers + are copied into the shadow registers (RTC_SSRx, + RTC_TRx and RTC_DRx). This bit is cleared by hardware + in initialization mode, while a shift operation is + pending (SHPF=1), or when in bypass shadow register + mode (BYPSHAD=1). This bit can also be cleared by + software. It is cleared either by software or by + hardware in initialization mode. + 5 + 1 + read-write + + + INITF + Initialization flag When this bit is set + to 1, the RTC is in initialization state, and the + time, date and prescaler registers can be + updated. + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag This flag is set by + hardware when the time/date registers (RTC_TR and + RTC_DR) match the Alarm A register (RTC_ALRMAR). This + flag is cleared by software by writing + 0. + 8 + 1 + read-write + + + ALRBF + Alarm B flag This flag is set by + hardware when the time/date registers (RTC_TR and + RTC_DR) match the Alarm B register (RTC_ALRMBR). This + flag is cleared by software by writing + 0. + 9 + 1 + read-write + + + WUTF + Wakeup timer flag This flag is set by + hardware when the wakeup auto-reload counter reaches + 0. This flag is cleared by software by writing 0. + This flag must be cleared by software at least 1.5 + RTCCLK periods before WUTF is set to 1 + again. + 10 + 1 + read-write + + + TSF + Time-stamp flag This flag is set by + hardware when a time-stamp event occurs. This flag is + cleared by software by writing 0. + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag This flag is + set by hardware when a time-stamp event occurs while + TSF is already set. This flag is cleared by software + by writing 0. It is recommended to check and then + clear TSOVF only after clearing the TSF bit. + Otherwise, an overflow might not be noticed if a + time-stamp event occurs immediately before the TSF + bit is cleared. + 12 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag This flag is + set by hardware when a tamper detection event is + detected on the RTC_TAMP1 input. It is cleared by + software writing 0 + 13 + 1 + read-write + + + TAMP2F + RTC_TAMP2 detection flag This flag is + set by hardware when a tamper detection event is + detected on the RTC_TAMP2 input. It is cleared by + software writing 0 + 14 + 1 + read-write + + + TAMP3F + RTC_TAMP3 detection flag This flag is + set by hardware when a tamper detection event is + detected on the RTC_TAMP3 input. It is cleared by + software writing 0 + 15 + 1 + read-write + + + RECALPF + Recalibration pending Flag The RECALPF + status flag is automatically set to 1 when software + writes to the RTC_CALR register, indicating that the + RTC_CALR register is blocked. When the new + calibration settings are taken into account, this bit + returns to 0. Refer to Re-calibration + on-the-fly. + 16 + 1 + read-only + + + ITSF + Internal tTime-stamp flag + 17 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + This register must be written in + initialization mode only. The initialization must be + performed in two separate write accesses. Refer to + Calendar initialization and configuration on page9.This + register is write protected. The write access procedure + is described in RTC register write protection on + page9. + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor This is the + synchronous division factor: ck_spre frequency = + ck_apre frequency/(PREDIV_S+1) + 0 + 15 + + + PREDIV_A + Asynchronous prescaler factor This is + the asynchronous division factor: ck_apre frequency = + RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + + + + + RTC_WUTR + RTC_WUTR + This register can be written only when WUTWF + is set to 1 in RTC_ISR.This register is write protected. + The write access procedure is described in RTC register + write protection on page9. + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits When the + wakeup timer is enabled (WUTE set to 1), the WUTF + flag is set every (WUT[15:0] + 1) ck_wut cycles. The + ck_wut period is selected through WUCKSEL[2:0] bits + of the RTC_CR register When WUCKSEL[2] = 1, the + wakeup timer becomes 17-bits and WUCKSEL[1] + effectively becomes WUT[16] the most-significant bit + to be reloaded into the timer. The first assertion of + WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. + Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 + (RTCCLK/2) is forbidden. + 0 + 16 + + + + + RTC_ALRMAR + RTC_ALRMAR + This register can be written only when + ALRAWF is set to 1 in RTC_ISR, or in initialization + mode.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD + format. + 0 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + HU + Hour units in BCD format. + 16 + 4 + + + HT + Hour tens in BCD format. + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + DU + Date units or day in BCD + format. + 24 + 4 + + + DT + Date tens in BCD format. + 28 + 2 + + + WDSEL + Week day selection + 30 + 1 + + + MSK4 + Alarm A date mask + 31 + 1 + + + + + RTC_ALRMBR + RTC_ALRMBR + This register can be written only when + ALRBWF is set to 1 in RTC_ISR, or in initialization + mode.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x20 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + DU + Date units or day in BCD + format + 24 + 4 + + + DT + Date tens in BCD format + 28 + 2 + + + WDSEL + Week day selection + 30 + 1 + + + MSK4 + Alarm B date mask + 31 + 1 + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key This byte is + written by software. Reading this byte always returns + 0x00. Refer to RTC register write protection for a + description of how to unlock RTC register write + protection. + 0 + 8 + + + + + RTC_SSR + RTC_SSR + RTC sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value SS[15:0] is the value + in the synchronous prescaler counter. The fraction of + a second is given by the formula below: Second + fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS + can be larger than PREDIV_S only after a shift + operation. In that case, the correct time/date is one + second less than as indicated by + RTC_TR/RTC_DR. + 0 + 16 + + + + + RTC_SHIFTR + RTC_SHIFTR + This register is write protected. The write + access procedure is described in RTC register write + protection on page9. + 0x2C + 0x20 + write-only + 0x00000000 + + + SUBFS + Subtract a fraction of a second These + bits are write only and is always read as zero. + Writing to this bit has no effect when a shift + operation is pending (when SHPF=1, in RTC_ISR). The + value which is written to SUBFS is added to the + synchronous prescaler counter. Since this counter + counts down, this operation effectively subtracts + from (delays) the clock by: Delay (seconds) = SUBFS / + (PREDIV_S + 1) A fraction of a second can effectively + be added to the clock (advancing the clock) when the + ADD1S function is used in conjunction with SUBFS, + effectively advancing the clock by: Advance (seconds) + = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to + SUBFS causes RSF to be cleared. Software can then + wait until RSF=1 to be sure that the shadow registers + have been updated with the shifted + time. + 0 + 15 + + + ADD1S + Add one second This bit is write only + and is always read as zero. Writing to this bit has + no effect when a shift operation is pending (when + SHPF=1, in RTC_ISR). This function is intended to be + used with SUBFS (see description below) in order to + effectively add a fraction of a second to the clock + in an atomic operation. + 31 + 1 + + + + + RTC_TSTR + RTC_TSTR + The content of this register is valid only + when TSF is set to 1 in RTC_ISR. It is cleared when TSF + bit is reset. + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD + format. + 0 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + HU + Hour units in BCD format. + 16 + 4 + + + HT + Hour tens in BCD format. + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + RTC_TSDR + RTC_TSDR + The content of this register is valid only + when TSF is set to 1 in RTC_ISR. It is cleared when TSF + bit is reset. + 0x34 + 0x20 + read-only + 0x00000000 + + + DU + Date units in BCD format + 0 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + MU + Month units in BCD format + 8 + 4 + + + MT + Month tens in BCD format + 12 + 1 + + + WDU + Week day units + 13 + 3 + + + + + RTC_TSSSR + RTC_TSSSR + The content of this register is valid only + when RTC_ISR/TSF is set. It is cleared when the + RTC_ISR/TSF bit is reset. + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value SS[15:0] is the value + of the synchronous prescaler counter when the + timestamp event occurred. + 0 + 16 + + + + + RTC_CALR + RTC_CALR + This register is write protected. The write + access procedure is described in RTC register write + protection on page9. + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus The frequency of the + calendar is reduced by masking CALM out of 220 RTCCLK + pulses (32 seconds if the input frequency is 32768 + Hz). This decreases the frequency of the calendar + with a resolution of 0.9537 ppm. To increase the + frequency of the calendar, this feature should be + used in conjunction with CALP. See Section24.3.12: + RTC smooth digital calibration on + page13. + 0 + 9 + + + CALW16 + Use a 16-second calibration cycle period + When CALW16 is set to 1, the 16-second calibration + cycle period is selected.This bit must not be set to + 1 if CALW8=1. Note: CALM[0] is stuck at 0 when + CALW16= 1. Refer to Section24.3.12: RTC smooth + digital calibration. + 13 + 1 + + + CALW8 + Use an 8-second calibration cycle period + When CALW8 is set to 1, the 8-second calibration + cycle period is selected. Note: CALM[1:0] are stuck + at 00; when CALW8= 1. Refer to Section24.3.12: RTC + smooth digital calibration. + 14 + 1 + + + CALP + Increase frequency of RTC by 488.5 ppm + This feature is intended to be used in conjunction + with CALM, which lowers the frequency of the calendar + with a fine resolution. if the input frequency is + 32768 Hz, the number of RTCCLK pulses added during a + 32-second window is calculated as follows: (512 * + CALP) - CALM. Refer to Section24.3.12: RTC smooth + digital calibration. + 15 + 1 + + + + + RTC_TAMPCR + RTC_TAMPCR + RTC tamper and alternate function + configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + RTC_TAMP1 input detection + enable + 0 + 1 + + + TAMP1TRG + Active level for RTC_TAMP1 input If + TAMPFLT != 00 if TAMPFLT = 00: + 1 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP2E + RTC_TAMP2 input detection + enable + 3 + 1 + + + TAMP2TRG + Active level for RTC_TAMP2 input if + TAMPFLT != 00: if TAMPFLT = 00: + 4 + 1 + + + TAMP3E + RTC_TAMP3 detection enable + 5 + 1 + + + TAMP3TRG + Active level for RTC_TAMP3 input if + TAMPFLT != 00: if TAMPFLT = 00: + 6 + 1 + + + TAMPTS + Activate timestamp on tamper detection + event TAMPTS is valid even if TSE=0 in the RTC_CR + register. + 7 + 1 + + + TAMPFREQ + Tamper sampling frequency Determines the + frequency at which each of the RTC_TAMPx inputs are + sampled. + 8 + 3 + + + TAMPFLT + RTC_TAMPx filter count These bits + determines the number of consecutive samples at the + specified level (TAMP*TRG) needed to activate a + Tamper event. TAMPFLT is valid for each of the + RTC_TAMPx inputs. + 11 + 2 + + + TAMPPRCH + RTC_TAMPx precharge duration These bit + determines the duration of time during which the + pull-up/is activated before each sample. TAMPPRCH is + valid for each of the RTC_TAMPx inputs. + 13 + 2 + + + TAMPPUDIS + RTC_TAMPx pull-up disable This bit + determines if each of the RTC_TAMPx pins are + pre-charged before each sample. + 15 + 1 + + + TAMP1IE + Tamper 1 interrupt enable + 16 + 1 + + + TAMP1NOERASE + Tamper 1 no erase + 17 + 1 + + + TAMP1MF + Tamper 1 mask flag + 18 + 1 + + + TAMP2IE + Tamper 2 interrupt enable + 19 + 1 + + + TAMP2NOERASE + Tamper 2 no erase + 20 + 1 + + + TAMP2MF + Tamper 2 mask flag + 21 + 1 + + + TAMP3IE + Tamper 3 interrupt enable + 22 + 1 + + + TAMP3NOERASE + Tamper 3 no erase + 23 + 1 + + + TAMP3MF + Tamper 3 mask flag + 24 + 1 + + + + + RTC_ALRMASSR + RTC_ALRMASSR + This register can be written only when ALRAE + is reset in RTC_CR register, or in initialization + mode.This register is write protected. The write access + procedure is described in RTC register write protection + on page9 + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value This value is compared + with the contents of the synchronous prescaler + counter to determine if Alarm A is to be activated. + Only bits 0 up MASKSS-1 are compared. + 0 + 15 + + + MASKSS + Mask the most-significant bits starting + at this bit ... The overflow bits of the synchronous + counter (bits 15) is never compared. This bit can be + different from 0 only after a shift + operation. + 24 + 4 + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + This register can be written only when ALRBE + is reset in RTC_CR register, or in initialization + mode.This register is write protected.The write access + procedure is described in Section: RTC register write + protection. + 0x48 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value This value is compared + with the contents of the synchronous prescaler + counter to determine if Alarm B is to be activated. + Only bits 0 up to MASKSS-1 are + compared. + 0 + 15 + + + MASKSS + Mask the most-significant bits starting + at this bit ... The overflow bits of the synchronous + counter (bits 15) is never compared. This bit can be + different from 0 only after a shift + operation. + 24 + 4 + + + + + RTC_BKP0R + RTC_BKP0R + RTC backup registers + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP1R + RTC_BKP1R + RTC backup registers + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP2R + RTC_BKP2R + RTC backup registers + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP3R + RTC_BKP3R + RTC backup registers + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP4R + RTC_BKP4R + RTC backup registers + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP5R + RTC_BKP5R + RTC backup registers + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP6R + RTC_BKP6R + RTC backup registers + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP7R + RTC_BKP7R + RTC backup registers + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP8R + RTC_BKP8R + RTC backup registers + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP9R + RTC_BKP9R + RTC backup registers + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP10R + RTC_BKP10R + RTC backup registers + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP11R + RTC_BKP11R + RTC backup registers + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP12R + RTC_BKP12R + RTC backup registers + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP13R + RTC_BKP13R + RTC backup registers + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP14R + RTC_BKP14R + RTC backup registers + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP15R + RTC_BKP15R + RTC backup registers + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_OR + RTC_OR + RTC option register + 0x4C + 0x20 + read-write + 0x00000000 + + + RTC_ALARM_TYPE + RTC_ALARM output type on + PC13 + 0 + 1 + + + RTC_OUT_RMP + RTC_OUT remap + 1 + 1 + + + + + RTC_BKP16R + RTC_BKP16R + RTC backup registers + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP17R + RTC_BKP17R + RTC backup registers + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP18R + RTC_BKP18R + RTC backup registers + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP19R + RTC_BKP19R + RTC backup registers + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP20R + RTC_BKP20R + RTC backup registers + 0xA0 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP21R + RTC_BKP21R + RTC backup registers + 0xA4 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP22R + RTC_BKP22R + RTC backup registers + 0xA8 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP23R + RTC_BKP23R + RTC backup registers + 0xAC + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP24R + RTC_BKP24R + RTC backup registers + 0xB0 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP25R + RTC_BKP25R + RTC backup registers + 0xB4 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP26R + RTC_BKP26R + RTC backup registers + 0xB8 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP27R + RTC_BKP27R + RTC backup registers + 0xBC + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP28R + RTC_BKP28R + RTC backup registers + 0xC0 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP29R + RTC_BKP29R + RTC backup registers + 0xC4 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP30R + RTC_BKP30R + RTC backup registers + 0xC8 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP31R + RTC_BKP31R + RTC backup registers + 0xCC + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + + + SAI4 + SAI + SAI + 0x58005400 + + 0x0 + 0x400 + registers + + + SAI4 + SAI4 global interrupt + 146 + + + + SAI_GCR + SAI_GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCOUT + Synchronization outputs These bits are + set and cleared by software. + 4 + 2 + + + SYNCIN + Synchronization inputs + 0 + 2 + + + + + SAI_ACR1 + SAI_ACR1 + Configuration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MODE + SAIx audio block mode + immediately + 0 + 2 + + + PRTCFG + Protocol configuration. These bits are + set and cleared by software. These bits have to be + configured when the audio block is + disabled. + 2 + 2 + + + DS + Data size. These bits are set and + cleared by software. These bits are ignored when the + SPDIF protocols are selected (bit PRTCFG[1:0]), + because the frame and the data size are fixed in such + case. When the companding mode is selected through + COMP[1:0] bits, DS[1:0] are ignored since the data + size is fixed to 8 bits by the algorithm. These bits + must be configured when the audio block is + disabled. + 5 + 3 + + + LSBFIRST + Least significant bit first. This bit is + set and cleared by software. It must be configured + when the audio block is disabled. This bit has no + meaning in AC97 audio protocol since AC97 data are + always transferred with the MSB first. This bit has + no meaning in SPDIF audio protocol since in SPDIF + data are always transferred with LSB + first. + 8 + 1 + + + CKSTR + Clock strobing edge. This bit is set and + cleared by software. It must be configured when the + audio block is disabled. This bit has no meaning in + SPDIF audio protocol. + 9 + 1 + + + SYNCEN + Synchronization enable. These bits are + set and cleared by software. They must be configured + when the audio sub-block is disabled. Note: The audio + sub-block should be configured as asynchronous when + SPDIF mode is enabled. + 10 + 2 + + + MONO + Mono mode. This bit is set and cleared + by software. It is meaningful only when the number of + slots is equal to 2. When the mono mode is selected, + slot 0 data are duplicated on slot 1 when the audio + block operates as a transmitter. In reception mode, + the slot1 is discarded and only the data received + from slot 0 are stored. Refer to Section: Mono/stereo + mode for more details. + 12 + 1 + + + OUTDRIV + Output drive. This bit is set and + cleared by software. Note: This bit has to be set + before enabling the audio block and after the audio + block configuration. + 13 + 1 + + + SAIXEN + Audio block enable where x is A or B. + This bit is set by software. To switch off the audio + block, the application software must program this bit + to 0 and poll the bit till it reads back 0, meaning + that the block is completely disabled. Before setting + this bit to 1, check that it is set to 0, otherwise + the enable command will not be taken into account. + This bit allows to control the state of SAIx audio + block. If it is disabled when an audio frame transfer + is ongoing, the ongoing transfer completes and the + cell is fully disabled at the end of this audio frame + transfer. Note: When SAIx block is configured in + master mode, the clock must be present on the input + of SAIx before setting SAIXEN bit. + 16 + 1 + + + DMAEN + DMA enable. This bit is set and cleared + by software. Note: Since the audio block defaults to + operate as a transmitter after reset, the MODE[1:0] + bits must be configured before setting DMAEN to avoid + a DMA request in receiver mode. + 17 + 1 + + + NOMCK + No divider + 19 + 1 + + + MCKDIV + Master clock divider. These bits are set + and cleared by software. These bits are meaningless + when the audio block operates in slave mode. They + have to be configured when the audio block is + disabled. Others: the master clock frequency is + calculated accordingly to the following + formula: + 20 + 4 + + + OSR + Oversampling ratio for master + clock + 26 + 1 + + + + + SAI_ACR2 + SAI_ACR2 + Configuration register 2 + 0x8 + 0x20 + 0x00000000 + + + FTH + FIFO threshold. This bit is set and + cleared by software. + 0 + 3 + read-write + + + FFLUSH + FIFO flush. This bit is set by software. + It is always read as 0. This bit should be configured + when the SAI is disabled. + 3 + 1 + write-only + + + TRIS + Tristate management on data line. This + bit is set and cleared by software. It is meaningful + only if the audio block is configured as a + transmitter. This bit is not used when the audio + block is configured in SPDIF mode. It should be + configured when SAI is disabled. Refer to Section: + Output data line management on an inactive slot for + more details. + 4 + 1 + read-write + + + MUTE + Mute. This bit is set and cleared by + software. It is meaningful only when the audio block + operates as a transmitter. The MUTE value is linked + to value of MUTEVAL if the number of slots is lower + or equal to 2, or equal to 0 if it is greater than 2. + Refer to Section: Mute mode for more details. Note: + This bit is meaningless and should not be used for + SPDIF audio blocks. + 5 + 1 + read-write + + + MUTEVAL + Mute value. This bit is set and cleared + by software.It must be written before enabling the + audio block: SAIXEN. This bit is meaningful only when + the audio block operates as a transmitter, the number + of slots is lower or equal to 2 and the MUTE bit is + set. If more slots are declared, the bit value sent + during the transmission in mute mode is equal to 0, + whatever the value of MUTEVAL. if the number of slot + is lower or equal to 2 and MUTEVAL = 1, the MUTE + value transmitted for each slot is the one sent + during the previous frame. Refer to Section: Mute + mode for more details. Note: This bit is meaningless + and should not be used for SPDIF audio + blocks. + 6 + 1 + read-write + + + MUTECNT + Mute counter. These bits are set and + cleared by software. They are used only in reception + mode. The value set in these bits is compared to the + number of consecutive mute frames detected in + reception. When the number of mute frames is equal to + this value, the flag MUTEDET will be set and an + interrupt will be generated if bit MUTEDETIE is set. + Refer to Section: Mute mode for more + details. + 7 + 6 + read-write + + + CPL + Complement bit. This bit is set and + cleared by software. It defines the type of + complement to be used for companding mode Note: This + bit has effect only when the companding mode is -Law + algorithm or A-Law algorithm. + 13 + 1 + read-write + + + COMP + Companding mode. These bits are set and + cleared by software. The -Law and the A-Law log are a + part of the CCITT G.711 recommendation, the type of + complement that will be used depends on CPL bit. The + data expansion or data compression are determined by + the state of bit MODE[0]. The data compression is + applied if the audio block is configured as a + transmitter. The data expansion is automatically + applied when the audio block is configured as a + receiver. Refer to Section: Companding mode for more + details. Note: Companding mode is applicable only + when TDM is selected. + 14 + 2 + read-write + + + + + SAI_AFRCR + SAI_AFRCR + This register has no meaning in AC97 and + SPDIF audio protocol + 0xC + 0x20 + 0x00000007 + + + FRL + Frame length. These bits are set and + cleared by software. They define the audio frame + length expressed in number of SCK clock cycles: the + number of bits in the frame is equal to FRL[7:0] + 1. + The minimum number of bits to transfer in an audio + frame must be equal to 8, otherwise the audio block + will behaves in an unexpected way. This is the case + when the data size is 8 bits and only one slot 0 is + defined in NBSLOT[4:0] of SAI_xSLOTR register + (NBSLOT[3:0] = 0000). In master mode, if the master + clock (available on MCLK_x pin) is used, the frame + length should be aligned with a number equal to a + power of 2, ranging from 8 to 256. When the master + clock is not used (NODIV = 1), it is recommended to + program the frame length to an value ranging from 8 + to 256. These bits are meaningless and are not used + in AC97 or SPDIF audio block + configuration. + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length. These bits are set and cleared by software. + They specify the length in number of bit clock (SCK) + + 1 (FSALL[6:0] + 1) of the active level of the FS + signal in the audio frame These bits are meaningless + and are not used in AC97 or SPDIF audio block + configuration. They must be configured when the audio + block is disabled. + 8 + 7 + read-write + + + FSDEF + Frame synchronization definition. This + bit is set and cleared by software. When the bit is + set, the number of slots defined in the SAI_xSLOTR + register has to be even. It means that half of this + number of slots will be dedicated to the left channel + and the other slots for the right channel (e.g: this + bit has to be set for I2S or MSB/LSB-justified + protocols...). This bit is meaningless and is not + used in AC97 or SPDIF audio block configuration. It + must be configured when the audio block is + disabled. + 16 + 1 + read-only + + + FSPOL + Frame synchronization polarity. This bit + is set and cleared by software. It is used to + configure the level of the start of frame on the FS + signal. It is meaningless and is not used in AC97 or + SPDIF audio block configuration. This bit must be + configured when the audio block is + disabled. + 17 + 1 + read-write + + + FSOFF + Frame synchronization offset. This bit + is set and cleared by software. It is meaningless and + is not used in AC97 or SPDIF audio block + configuration. This bit must be configured when the + audio block is disabled. + 18 + 1 + read-write + + + + + SAI_ASLOTR + SAI_ASLOTR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x10 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset These bits are set and + cleared by software. The value set in this bitfield + defines the position of the first data transfer bit + in the slot. It represents an offset value. In + transmission mode, the bits outside the data field + are forced to 0. In reception mode, the extra + received bits are discarded. These bits must be set + when the audio block is disabled. They are ignored in + AC97 or SPDIF mode. + 0 + 5 + + + SLOTSZ + Slot size This bits is set and cleared + by software. The slot size must be higher or equal to + the data size. If this condition is not respected, + the behavior of the SAI will be undetermined. Refer + to Section: Output data line management on an + inactive slot for information on how to drive SD + line. These bits must be set when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 6 + 2 + + + NBSLOT + Number of slots in an audio frame. These + bits are set and cleared by software. The value set + in this bitfield represents the number of slots + 1 + in the audio frame (including the number of inactive + slots). The maximum number of slots is 16. The number + of slots should be even if FSDEF bit in the SAI_xFRCR + register is set. The number of slots must be + configured when the audio block is disabled. They are + ignored in AC97 or SPDIF mode. + 8 + 4 + + + SLOTEN + Slot enable. These bits are set and + cleared by software. Each SLOTEN bit corresponds to a + slot position from 0 to 15 (maximum 16 slots). The + slot must be enabled when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 16 + 16 + + + + + SAI_AIM + SAI_AIM + Interrupt mask register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the OVRUDR bit in + the SAI_xSR register is set. + 0 + 1 + + + MUTEDETIE + Mute detection interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the MUTEDET bit in + the SAI_xSR register is set. This bit has a meaning + only if the audio block is configured in receiver + mode. + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable. This bit is set and cleared by software. This + bit is taken into account only if the audio block is + configured as a master (MODE[1] = 0) and NODIV = 0. + It generates an interrupt if the WCKCFG flag in the + SAI_xSR register is set. Note: This bit is used only + in TDM mode and is meaningless in other + modes. + 2 + 1 + + + FREQIE + FIFO request interrupt enable. This bit + is set and cleared by software. When this bit is set, + an interrupt is generated if the FREQ bit in the + SAI_xSR register is set. Since the audio block + defaults to operate as a transmitter after reset, the + MODE bit must be configured before setting FREQIE to + avoid a parasitic interruption in receiver + mode, + 3 + 1 + + + CNRDYIE + Codec not ready interrupt enable (AC97). + This bit is set and cleared by software. When the + interrupt is enabled, the audio block detects in the + slot 0 (tag0) of the AC97 frame if the Codec + connected to this line is ready or not. If it is not + ready, the CNRDY flag in the SAI_xSR register is set + and an interruption i generated. This bit has a + meaning only if the AC97 mode is selected through + PRTCFG[1:0] bits and the audio block is operates as a + receiver. + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable. This bit is set and + cleared by software. When this bit is set, an + interrupt will be generated if the AFSDET bit in the + SAI_xSR register is set. This bit is meaningless in + AC97, SPDIF mode or when the audio block operates as + a master. + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable. This bit is set and cleared by + software. When this bit is set, an interrupt will be + generated if the LFSDET bit is set in the SAI_xSR + register. This bit is meaningless in AC97, SPDIF mode + or when the audio block operates as a + master. + 6 + 1 + + + + + SAI_ASR + SAI_ASR + Status register + 0x18 + 0x20 + read-only + 0x00000008 + + + OVRUDR + Overrun / underrun. This bit is read + only. The overrun and underrun conditions can occur + only when the audio block is configured as a receiver + and a transmitter, respectively. It can generate an + interrupt if OVRUDRIE bit is set in SAI_xIM register. + This flag is cleared when the software sets COVRUDR + bit in SAI_xCLRFR register. + 0 + 1 + + + MUTEDET + Mute detection. This bit is read only. + This flag is set if consecutive 0 values are received + in each slot of a given audio frame and for a + consecutive number of audio frames (set in the + MUTECNT bit in the SAI_xCR2 register). It can + generate an interrupt if MUTEDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets bit CMUTEDET in the SAI_xCLRFR + register. + 1 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit + is read only. This bit is used only when the audio + block operates in master mode (MODE[1] = 0) and NODIV + = 0. It can generate an interrupt if WCKCFGIE bit is + set in SAI_xIM register. This flag is cleared when + the software sets CWCKCFG bit in SAI_xCLRFR + register. + 2 + 1 + + + FREQ + FIFO request. This bit is read only. The + request depends on the audio block configuration: If + the block is configured in transmission mode, the + FIFO request is related to a write request operation + in the SAI_xDR. If the block configured in reception, + the FIFO request related to a read request operation + from the SAI_xDR. This flag can generate an interrupt + if FREQIE bit is set in SAI_xIM + register. + 3 + 1 + + + CNRDY + Codec not ready. This bit is read only. + This bit is used only when the AC97 audio protocol is + selected in the SAI_xCR1 register and configured in + receiver mode. It can generate an interrupt if + CNRDYIE bit is set in SAI_xIM register. This flag is + cleared when the software sets CCNRDY bit in + SAI_xCLRFR register. + 4 + 1 + + + AFSDET + Anticipated frame synchronization + detection. This bit is read only. This flag can be + set only if the audio block is configured in slave + mode. It is not used in AC97or SPDIF mode. It can + generate an interrupt if AFSDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets CAFSDET bit in SAI_xCLRFR + register. + 5 + 1 + + + LFSDET + Late frame synchronization detection. + This bit is read only. This flag can be set only if + the audio block is configured in slave mode. It is + not used in AC97 or SPDIF mode. It can generate an + interrupt if LFSDETIE bit is set in the SAI_xIM + register. This flag is cleared when the software sets + bit CLFSDET in SAI_xCLRFR register + 6 + 1 + + + FLVL + FIFO level threshold. This bit is read + only. The FIFO level threshold flag is managed only + by hardware and its setting depends on SAI block + configuration (transmitter or receiver mode). If the + SAI block is configured as transmitter: If SAI block + is configured as receiver: + 16 + 3 + + + + + SAI_ACLRFR + SAI_ACLRFR + Clear flag register + 0x1C + 0x20 + write-only + 0x00000000 + + + COVRUDR + Clear overrun / underrun. This bit is + write only. Programming this bit to 1 clears the + OVRUDR flag in the SAI_xSR register. Reading this bit + always returns the value 0. + 0 + 1 + + + CMUTEDET + Mute detection flag. This bit is write + only. Programming this bit to 1 clears the MUTEDET + flag in the SAI_xSR register. Reading this bit always + returns the value 0. + 1 + 1 + + + CWCKCFG + Clear wrong clock configuration flag. + This bit is write only. Programming this bit to 1 + clears the WCKCFG flag in the SAI_xSR register. This + bit is used only when the audio block is set as + master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 + register. Reading this bit always returns the value + 0. + 2 + 1 + + + CCNRDY + Clear Codec not ready flag. This bit is + write only. Programming this bit to 1 clears the + CNRDY flag in the SAI_xSR register. This bit is used + only when the AC97 audio protocol is selected in the + SAI_xCR1 register. Reading this bit always returns + the value 0. + 4 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the AFSDET flag in the SAI_xSR + register. It is not used in AC97or SPDIF mode. + Reading this bit always returns the value + 0. + 5 + 1 + + + CLFSDET + Clear late frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the LFSDET flag in the SAI_xSR + register. This bit is not used in AC97or SPDIF mode + Reading this bit always returns the value + 0. + 6 + 1 + + + + + SAI_ADR + SAI_ADR + Data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data A write to this register loads the + FIFO provided the FIFO is not full. A read from this + register empties the FIFO if the FIFO is not + empty. + 0 + 32 + + + + + SAI_BCR1 + SAI_BCR1 + Configuration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MODE + SAIx audio block mode + immediately + 0 + 2 + + + PRTCFG + Protocol configuration. These bits are + set and cleared by software. These bits have to be + configured when the audio block is + disabled. + 2 + 2 + + + DS + Data size. These bits are set and + cleared by software. These bits are ignored when the + SPDIF protocols are selected (bit PRTCFG[1:0]), + because the frame and the data size are fixed in such + case. When the companding mode is selected through + COMP[1:0] bits, DS[1:0] are ignored since the data + size is fixed to 8 bits by the algorithm. These bits + must be configured when the audio block is + disabled. + 5 + 3 + + + LSBFIRST + Least significant bit first. This bit is + set and cleared by software. It must be configured + when the audio block is disabled. This bit has no + meaning in AC97 audio protocol since AC97 data are + always transferred with the MSB first. This bit has + no meaning in SPDIF audio protocol since in SPDIF + data are always transferred with LSB + first. + 8 + 1 + + + CKSTR + Clock strobing edge. This bit is set and + cleared by software. It must be configured when the + audio block is disabled. This bit has no meaning in + SPDIF audio protocol. + 9 + 1 + + + SYNCEN + Synchronization enable. These bits are + set and cleared by software. They must be configured + when the audio sub-block is disabled. Note: The audio + sub-block should be configured as asynchronous when + SPDIF mode is enabled. + 10 + 2 + + + MONO + Mono mode. This bit is set and cleared + by software. It is meaningful only when the number of + slots is equal to 2. When the mono mode is selected, + slot 0 data are duplicated on slot 1 when the audio + block operates as a transmitter. In reception mode, + the slot1 is discarded and only the data received + from slot 0 are stored. Refer to Section: Mono/stereo + mode for more details. + 12 + 1 + + + OUTDRIV + Output drive. This bit is set and + cleared by software. Note: This bit has to be set + before enabling the audio block and after the audio + block configuration. + 13 + 1 + + + SAIXEN + Audio block enable where x is A or B. + This bit is set by software. To switch off the audio + block, the application software must program this bit + to 0 and poll the bit till it reads back 0, meaning + that the block is completely disabled. Before setting + this bit to 1, check that it is set to 0, otherwise + the enable command will not be taken into account. + This bit allows to control the state of SAIx audio + block. If it is disabled when an audio frame transfer + is ongoing, the ongoing transfer completes and the + cell is fully disabled at the end of this audio frame + transfer. Note: When SAIx block is configured in + master mode, the clock must be present on the input + of SAIx before setting SAIXEN bit. + 16 + 1 + + + DMAEN + DMA enable. This bit is set and cleared + by software. Note: Since the audio block defaults to + operate as a transmitter after reset, the MODE[1:0] + bits must be configured before setting DMAEN to avoid + a DMA request in receiver mode. + 17 + 1 + + + NOMCK + No divider + 19 + 1 + + + MCKDIV + Master clock divider. These bits are set + and cleared by software. These bits are meaningless + when the audio block operates in slave mode. They + have to be configured when the audio block is + disabled. Others: the master clock frequency is + calculated accordingly to the following + formula: + 20 + 4 + + + OSR + Oversampling ratio for master + clock + 26 + 1 + + + + + SAI_BCR2 + SAI_BCR2 + Configuration register 2 + 0x28 + 0x20 + 0x00000000 + + + FTH + FIFO threshold. This bit is set and + cleared by software. + 0 + 3 + read-write + + + FFLUSH + FIFO flush. This bit is set by software. + It is always read as 0. This bit should be configured + when the SAI is disabled. + 3 + 1 + write-only + + + TRIS + Tristate management on data line. This + bit is set and cleared by software. It is meaningful + only if the audio block is configured as a + transmitter. This bit is not used when the audio + block is configured in SPDIF mode. It should be + configured when SAI is disabled. Refer to Section: + Output data line management on an inactive slot for + more details. + 4 + 1 + read-write + + + MUTE + Mute. This bit is set and cleared by + software. It is meaningful only when the audio block + operates as a transmitter. The MUTE value is linked + to value of MUTEVAL if the number of slots is lower + or equal to 2, or equal to 0 if it is greater than 2. + Refer to Section: Mute mode for more details. Note: + This bit is meaningless and should not be used for + SPDIF audio blocks. + 5 + 1 + read-write + + + MUTEVAL + Mute value. This bit is set and cleared + by software.It must be written before enabling the + audio block: SAIXEN. This bit is meaningful only when + the audio block operates as a transmitter, the number + of slots is lower or equal to 2 and the MUTE bit is + set. If more slots are declared, the bit value sent + during the transmission in mute mode is equal to 0, + whatever the value of MUTEVAL. if the number of slot + is lower or equal to 2 and MUTEVAL = 1, the MUTE + value transmitted for each slot is the one sent + during the previous frame. Refer to Section: Mute + mode for more details. Note: This bit is meaningless + and should not be used for SPDIF audio + blocks. + 6 + 1 + read-write + + + MUTECNT + Mute counter. These bits are set and + cleared by software. They are used only in reception + mode. The value set in these bits is compared to the + number of consecutive mute frames detected in + reception. When the number of mute frames is equal to + this value, the flag MUTEDET will be set and an + interrupt will be generated if bit MUTEDETIE is set. + Refer to Section: Mute mode for more + details. + 7 + 6 + read-write + + + CPL + Complement bit. This bit is set and + cleared by software. It defines the type of + complement to be used for companding mode Note: This + bit has effect only when the companding mode is -Law + algorithm or A-Law algorithm. + 13 + 1 + read-write + + + COMP + Companding mode. These bits are set and + cleared by software. The -Law and the A-Law log are a + part of the CCITT G.711 recommendation, the type of + complement that will be used depends on CPL bit. The + data expansion or data compression are determined by + the state of bit MODE[0]. The data compression is + applied if the audio block is configured as a + transmitter. The data expansion is automatically + applied when the audio block is configured as a + receiver. Refer to Section: Companding mode for more + details. Note: Companding mode is applicable only + when TDM is selected. + 14 + 2 + read-write + + + + + SAI_BFRCR + SAI_BFRCR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x2C + 0x20 + 0x00000007 + + + FRL + Frame length. These bits are set and + cleared by software. They define the audio frame + length expressed in number of SCK clock cycles: the + number of bits in the frame is equal to FRL[7:0] + 1. + The minimum number of bits to transfer in an audio + frame must be equal to 8, otherwise the audio block + will behaves in an unexpected way. This is the case + when the data size is 8 bits and only one slot 0 is + defined in NBSLOT[4:0] of SAI_xSLOTR register + (NBSLOT[3:0] = 0000). In master mode, if the master + clock (available on MCLK_x pin) is used, the frame + length should be aligned with a number equal to a + power of 2, ranging from 8 to 256. When the master + clock is not used (NODIV = 1), it is recommended to + program the frame length to an value ranging from 8 + to 256. These bits are meaningless and are not used + in AC97 or SPDIF audio block + configuration. + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length. These bits are set and cleared by software. + They specify the length in number of bit clock (SCK) + + 1 (FSALL[6:0] + 1) of the active level of the FS + signal in the audio frame These bits are meaningless + and are not used in AC97 or SPDIF audio block + configuration. They must be configured when the audio + block is disabled. + 8 + 7 + read-write + + + FSDEF + Frame synchronization definition. This + bit is set and cleared by software. When the bit is + set, the number of slots defined in the SAI_xSLOTR + register has to be even. It means that half of this + number of slots will be dedicated to the left channel + and the other slots for the right channel (e.g: this + bit has to be set for I2S or MSB/LSB-justified + protocols...). This bit is meaningless and is not + used in AC97 or SPDIF audio block configuration. It + must be configured when the audio block is + disabled. + 16 + 1 + read-only + + + FSPOL + Frame synchronization polarity. This bit + is set and cleared by software. It is used to + configure the level of the start of frame on the FS + signal. It is meaningless and is not used in AC97 or + SPDIF audio block configuration. This bit must be + configured when the audio block is + disabled. + 17 + 1 + read-write + + + FSOFF + Frame synchronization offset. This bit + is set and cleared by software. It is meaningless and + is not used in AC97 or SPDIF audio block + configuration. This bit must be configured when the + audio block is disabled. + 18 + 1 + read-write + + + + + SAI_BSLOTR + SAI_BSLOTR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x30 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset These bits are set and + cleared by software. The value set in this bitfield + defines the position of the first data transfer bit + in the slot. It represents an offset value. In + transmission mode, the bits outside the data field + are forced to 0. In reception mode, the extra + received bits are discarded. These bits must be set + when the audio block is disabled. They are ignored in + AC97 or SPDIF mode. + 0 + 5 + + + SLOTSZ + Slot size This bits is set and cleared + by software. The slot size must be higher or equal to + the data size. If this condition is not respected, + the behavior of the SAI will be undetermined. Refer + to Section: Output data line management on an + inactive slot for information on how to drive SD + line. These bits must be set when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 6 + 2 + + + NBSLOT + Number of slots in an audio frame. These + bits are set and cleared by software. The value set + in this bitfield represents the number of slots + 1 + in the audio frame (including the number of inactive + slots). The maximum number of slots is 16. The number + of slots should be even if FSDEF bit in the SAI_xFRCR + register is set. The number of slots must be + configured when the audio block is disabled. They are + ignored in AC97 or SPDIF mode. + 8 + 4 + + + SLOTEN + Slot enable. These bits are set and + cleared by software. Each SLOTEN bit corresponds to a + slot position from 0 to 15 (maximum 16 slots). The + slot must be enabled when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 16 + 16 + + + + + SAI_BIM + SAI_BIM + Interrupt mask register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the OVRUDR bit in + the SAI_xSR register is set. + 0 + 1 + + + MUTEDETIE + Mute detection interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the MUTEDET bit in + the SAI_xSR register is set. This bit has a meaning + only if the audio block is configured in receiver + mode. + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable. This bit is set and cleared by software. This + bit is taken into account only if the audio block is + configured as a master (MODE[1] = 0) and NODIV = 0. + It generates an interrupt if the WCKCFG flag in the + SAI_xSR register is set. Note: This bit is used only + in TDM mode and is meaningless in other + modes. + 2 + 1 + + + FREQIE + FIFO request interrupt enable. This bit + is set and cleared by software. When this bit is set, + an interrupt is generated if the FREQ bit in the + SAI_xSR register is set. Since the audio block + defaults to operate as a transmitter after reset, the + MODE bit must be configured before setting FREQIE to + avoid a parasitic interruption in receiver + mode, + 3 + 1 + + + CNRDYIE + Codec not ready interrupt enable (AC97). + This bit is set and cleared by software. When the + interrupt is enabled, the audio block detects in the + slot 0 (tag0) of the AC97 frame if the Codec + connected to this line is ready or not. If it is not + ready, the CNRDY flag in the SAI_xSR register is set + and an interruption i generated. This bit has a + meaning only if the AC97 mode is selected through + PRTCFG[1:0] bits and the audio block is operates as a + receiver. + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable. This bit is set and + cleared by software. When this bit is set, an + interrupt will be generated if the AFSDET bit in the + SAI_xSR register is set. This bit is meaningless in + AC97, SPDIF mode or when the audio block operates as + a master. + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable. This bit is set and cleared by + software. When this bit is set, an interrupt will be + generated if the LFSDET bit is set in the SAI_xSR + register. This bit is meaningless in AC97, SPDIF mode + or when the audio block operates as a + master. + 6 + 1 + + + + + SAI_BSR + SAI_BSR + Status register + 0x38 + 0x20 + read-only + 0x00000008 + + + OVRUDR + Overrun / underrun. This bit is read + only. The overrun and underrun conditions can occur + only when the audio block is configured as a receiver + and a transmitter, respectively. It can generate an + interrupt if OVRUDRIE bit is set in SAI_xIM register. + This flag is cleared when the software sets COVRUDR + bit in SAI_xCLRFR register. + 0 + 1 + + + MUTEDET + Mute detection. This bit is read only. + This flag is set if consecutive 0 values are received + in each slot of a given audio frame and for a + consecutive number of audio frames (set in the + MUTECNT bit in the SAI_xCR2 register). It can + generate an interrupt if MUTEDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets bit CMUTEDET in the SAI_xCLRFR + register. + 1 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit + is read only. This bit is used only when the audio + block operates in master mode (MODE[1] = 0) and NODIV + = 0. It can generate an interrupt if WCKCFGIE bit is + set in SAI_xIM register. This flag is cleared when + the software sets CWCKCFG bit in SAI_xCLRFR + register. + 2 + 1 + + + FREQ + FIFO request. This bit is read only. The + request depends on the audio block configuration: If + the block is configured in transmission mode, the + FIFO request is related to a write request operation + in the SAI_xDR. If the block configured in reception, + the FIFO request related to a read request operation + from the SAI_xDR. This flag can generate an interrupt + if FREQIE bit is set in SAI_xIM + register. + 3 + 1 + + + CNRDY + Codec not ready. This bit is read only. + This bit is used only when the AC97 audio protocol is + selected in the SAI_xCR1 register and configured in + receiver mode. It can generate an interrupt if + CNRDYIE bit is set in SAI_xIM register. This flag is + cleared when the software sets CCNRDY bit in + SAI_xCLRFR register. + 4 + 1 + + + AFSDET + Anticipated frame synchronization + detection. This bit is read only. This flag can be + set only if the audio block is configured in slave + mode. It is not used in AC97or SPDIF mode. It can + generate an interrupt if AFSDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets CAFSDET bit in SAI_xCLRFR + register. + 5 + 1 + + + LFSDET + Late frame synchronization detection. + This bit is read only. This flag can be set only if + the audio block is configured in slave mode. It is + not used in AC97 or SPDIF mode. It can generate an + interrupt if LFSDETIE bit is set in the SAI_xIM + register. This flag is cleared when the software sets + bit CLFSDET in SAI_xCLRFR register + 6 + 1 + + + FLVL + FIFO level threshold. This bit is read + only. The FIFO level threshold flag is managed only + by hardware and its setting depends on SAI block + configuration (transmitter or receiver mode). If the + SAI block is configured as transmitter: If SAI block + is configured as receiver: + 16 + 3 + + + + + SAI_BCLRFR + SAI_BCLRFR + Clear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + COVRUDR + Clear overrun / underrun. This bit is + write only. Programming this bit to 1 clears the + OVRUDR flag in the SAI_xSR register. Reading this bit + always returns the value 0. + 0 + 1 + + + CMUTEDET + Mute detection flag. This bit is write + only. Programming this bit to 1 clears the MUTEDET + flag in the SAI_xSR register. Reading this bit always + returns the value 0. + 1 + 1 + + + CWCKCFG + Clear wrong clock configuration flag. + This bit is write only. Programming this bit to 1 + clears the WCKCFG flag in the SAI_xSR register. This + bit is used only when the audio block is set as + master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 + register. Reading this bit always returns the value + 0. + 2 + 1 + + + CCNRDY + Clear Codec not ready flag. This bit is + write only. Programming this bit to 1 clears the + CNRDY flag in the SAI_xSR register. This bit is used + only when the AC97 audio protocol is selected in the + SAI_xCR1 register. Reading this bit always returns + the value 0. + 4 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the AFSDET flag in the SAI_xSR + register. It is not used in AC97or SPDIF mode. + Reading this bit always returns the value + 0. + 5 + 1 + + + CLFSDET + Clear late frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the LFSDET flag in the SAI_xSR + register. This bit is not used in AC97or SPDIF mode + Reading this bit always returns the value + 0. + 6 + 1 + + + + + SAI_BDR + SAI_BDR + Data register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data A write to this register loads the + FIFO provided the FIFO is not full. A read from this + register empties the FIFO if the FIFO is not + empty. + 0 + 32 + + + + + SAI_PDMCR + SAI_PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDM enable + 0 + 1 + + + MICNBR + Number of microphones + 4 + 2 + + + CKEN1 + Clock enable of bitstream clock number + 1 + 8 + 1 + + + CKEN2 + Clock enable of bitstream clock number + 2 + 9 + 1 + + + CKEN3 + Clock enable of bitstream clock number + 3 + 10 + 1 + + + CKEN4 + Clock enable of bitstream clock number + 4 + 11 + 1 + + + + + SAI_PDMDLY + SAI_PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + Delay line adjust for first microphone + of pair 1 + 0 + 3 + + + DLYM1R + Delay line adjust for second microphone + of pair 1 + 4 + 3 + + + DLYM2L + Delay line for first microphone of pair + 2 + 8 + 3 + + + DLYM2R + Delay line for second microphone of pair + 2 + 12 + 3 + + + DLYM3L + Delay line for first microphone of pair + 3 + 16 + 3 + + + DLYM3R + Delay line for second microphone of pair + 3 + 20 + 3 + + + DLYM4L + Delay line for first microphone of pair + 4 + 24 + 3 + + + DLYM4R + Delay line for second microphone of pair + 4 + 28 + 3 + + + + + + + SAI1 + 0x40015800 + + SAI1 + SAI1 global interrupt + 87 + + + + SAI2 + 0x40015C00 + + SAI2 + SAI2 global interrupt + 91 + + + + SAI3 + 0x40016000 + + SAI3 + SAI3 global interrupt + 114 + + + + SDMMC1 + SDMMC1 + SDMMC + 0x52007000 + + 0x0 + 0x100 + registers + + + SDMMC1 + SDMMC global interrupt + 49 + + + SDMMC + SDMMC global interrupt + 124 + + + + POWER + POWER + SDMMC power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + SDMMC state control bits. These bits can + only be written when the SDMMC is not in the power-on + state (PWRCTRL?11). These bits are used to define the + functional state of the SDMMC signals: Any further + write will be ignored, PWRCTRL value will keep + 11. + 0 + 2 + + + VSWITCH + Voltage switch sequence start. This bit + is used to start the timing critical section of the + voltage switch sequence: + 2 + 1 + + + VSWITCHEN + Voltage switch procedure enable. This + bit can only be written by firmware when CPSM is + disabled (CPSMEN = 0). This bit is used to stop the + SDMMC_CK after the voltage switch command + response: + 3 + 1 + + + DIRPOL + Data and command direction signals + polarity selection. This bit can only be written when + the SDMMC is in the power-off state (PWRCTRL = + 00). + 4 + 1 + + + + + CLKCR + CLKCR + The SDMMC_CLKCR register controls the + SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, + and the bus width. + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock divide factor This bit can only be + written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0). This field defines the + divide factor between the input clock (SDMMCCLK) and + the output clock (SDMMC_CK): SDMMC_CK frequency = + SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: + etc.. + 0 + 10 + + + PWRSAV + Power saving configuration bit This bit + can only be written when the CPSM and DPSM are not + active (CPSMACT = 0 and DPSMACT = 0) For power + saving, the SDMMC_CK clock output can be disabled + when the bus is idle by setting PWRSAV: + 12 + 1 + + + WIDBUS + Wide bus mode enable bit This bit can + only be written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0) + 14 + 2 + + + NEGEDGE + SDMMC_CK dephasing selection bit for + data and Command. This bit can only be written when + the CPSM and DPSM are not active (CPSMACT = 0 and + DPSMACT = 0). When clock division = 1 (CLKDIV = 0), + this bit has no effect. Data and Command change on + SDMMC_CK falling edge. When clock division &gt;1 + (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK + edge occurs on SDMMCCLK rising edge. When clock + division >1 (CLKDIV > 0) & DDR = 1: - Data + changed on the SDMMCCLK falling edge succeeding a + SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK + rising edge. - Data changed on the SDMMC_CK falling + edge succeeding a SDMMC_CK edge. - SDMMC_CK edge + occurs on SDMMCCLK rising edge. + 16 + 1 + + + HWFC_EN + Hardware flow control enable This bit + can only be written when the CPSM and DPSM are not + active (CPSMACT = 0 and DPSMACT = 0) When Hardware + flow control is enabled, the meaning of the TXFIFOE + and RXFIFOF flags change, please see SDMMC status + register definition in Section56.8.11. + 17 + 1 + + + DDR + Data rate signaling selection This bit + can only be written when the CPSM and DPSM are not + active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall + only be selected with 4-bit or 8-bit wide bus mode. + (WIDBUS &gt; 00). DDR = 1 has no effect when + WIDBUS = 00 (1-bit wide bus). DDR rate shall only be + selected with clock division &gt;1. (CLKDIV + &gt; 0) + 18 + 1 + + + BUSSPEED + Bus speed mode selection between DS, HS, + SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can + only be written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0) + 19 + 1 + + + SELCLKRX + Receive clock selection. These bits can + only be written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0) + 20 + 2 + + + + + ARGR + ARGR + The SDMMC_ARGR register contains a 32-bit + command argument, which is sent to a card as part of a + command message. + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument. These bits can only be + written by firmware when CPSM is disabled (CPSMEN = + 0). Command argument sent to a card as part of a + command message. If a command contains an argument, + it must be loaded into this register before writing a + command to the command register. + 0 + 32 + + + + + CMDR + CMDR + The SDMMC_CMDR register contains the command + index and command type bits. The command index is sent to + a card as part of a command message. The command type + bits control the command path state machine + (CPSM). + 0xC + 0x20 + read-write + 0x00000000 + + + CMDINDEX + Command index. This bit can only be + written by firmware when CPSM is disabled (CPSMEN = + 0). The command index is sent to the card as part of + a command message. + 0 + 6 + + + CMDTRANS + The CPSM treats the command as a data + transfer command, stops the interrupt period, and + signals DataEnable to the DPSM This bit can only be + written by firmware when CPSM is disabled (CPSMEN = + 0). If this bit is set, the CPSM issues an end of + interrupt period and issues DataEnable signal to the + DPSM when the command is sent. + 6 + 1 + + + CMDSTOP + The CPSM treats the command as a Stop + Transmission command and signals Abort to the DPSM. + This bit can only be written by firmware when CPSM is + disabled (CPSMEN = 0). If this bit is set, the CPSM + issues the Abort signal to the DPSM when the command + is sent. + 7 + 1 + + + WAITRESP + Wait for response bits. This bit can + only be written by firmware when CPSM is disabled + (CPSMEN = 0). They are used to configure whether the + CPSM is to wait for a response, and if yes, which + kind of response. + 8 + 2 + + + WAITINT + CPSM waits for interrupt request. If + this bit is set, the CPSM disables command timeout + and waits for an card interrupt request (Response). + If this bit is cleared in the CPSM Wait state, will + cause the abort of the interrupt mode. + 10 + 1 + + + WAITPEND + CPSM Waits for end of data transfer + (CmdPend internal signal) from DPSM. This bit when + set, the CPSM waits for the end of data transfer + trigger before it starts sending a command. WAITPEND + is only taken into account when DTMODE = MMC stream + data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT + = 1 and DTDIR = from host to card. + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable + bit This bit is written 1 by firmware, and cleared by + hardware when the CPSM enters the Idle state. If this + bit is set, the CPSM is enabled. When DTEN = 1, no + command will be transfered nor boot procedure will be + started. CPSMEN is cleared to 0. + 12 + 1 + + + DTHOLD + Hold new data block transmission and + reception in the DPSM. If this bit is set, the DPSM + will not move from the Wait_S state to the Send state + or from the Wait_R state to the Receive + state. + 13 + 1 + + + BOOTMODE + Select the boot mode procedure to be + used. This bit can only be written by firmware when + CPSM is disabled (CPSMEN = 0) + 14 + 1 + + + BOOTEN + Enable boot mode + procedure. + 15 + 1 + + + CMDSUSPEND + The CPSM treats the command as a Suspend + or Resume command and signals interrupt period + start/end. This bit can only be written by firmware + when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 + and CMDTRANS = 0 Suspend command, start interrupt + period when response bit BS=0. CMDSUSPEND = 1 and + CMDTRANS = 1 Resume command with data, end interrupt + period when response bit DF=1. + 16 + 1 + + + + + RESP1R + RESP1R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + see Table 432 + 0 + 32 + + + + + RESP2R + RESP2R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + see Table404. + 0 + 32 + + + + + RESP3R + RESP3R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + see Table404. + 0 + 32 + + + + + RESP4R + RESP4R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + see Table404. + 0 + 32 + + + + + DTIMER + DTIMER + The SDMMC_DTIMER register contains the data + timeout period, in card bus clock periods. A counter + loads the value from the SDMMC_DTIMER register, and + starts decrementing when the data path state machine + (DPSM) enters the Wait_R or Busy state. If the timer + reaches 0 while the DPSM is in either of these states, + the timeout status flag is set. + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data and R1b busy timeout period This + bit can only be written when the CPSM and DPSM are + not active (CPSMACT = 0 and DPSMACT = 0). Data and + R1b busy timeout period expressed in card bus clock + periods. + 0 + 32 + + + + + DLENR + DLENR + The SDMMC_DLENR register contains the number + of data bytes to be transferred. The value is loaded into + the data counter when data transfer starts. + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value This register can only + be written by firmware when DPSM is inactive (DPSMACT + = 0). Number of data bytes to be transferred. When + DDR = 1 DATALENGTH is truncated to a multiple of 2. + (The last odd byte is not transfered) When DATALENGTH + = 0 no data will be transfered, when requested by a + CPSMEN and CMDTRANS = 1 also no command will be + transfered. DTEN and CPSMEN are cleared to + 0. + 0 + 25 + + + + + DCTRL + DCTRL + The SDMMC_DCTRL register control the data + path state machine (DPSM). + 0x2C + 0x20 + read-write + 0x00000000 + + + DTEN + Data transfer enable bit This bit can + only be written by firmware when DPSM is inactive + (DPSMACT = 0). This bit is cleared by Hardware when + data transfer completes. This bit shall only be used + to transfer data when no associated data transfer + command is used, i.e. shall not be used with SD or + eMMC cards. + 0 + 1 + + + DTDIR + Data transfer direction selection This + bit can only be written by firmware when DPSM is + inactive (DPSMACT = 0). + 1 + 1 + + + DTMODE + Data transfer mode selection. This bit + can only be written by firmware when DPSM is inactive + (DPSMACT = 0). + 2 + 2 + + + DBLOCKSIZE + Data block size This bit can only be + written by firmware when DPSM is inactive (DPSMACT = + 0). Define the data block length when the block data + transfer mode is selected: When DATALENGTH is not a + multiple of DBLOCKSIZE, the transfered data is + truncated at a multiple of DBLOCKSIZE. (Any remain + data will not be transfered.) When DDR = 1, + DBLOCKSIZE = 0000 shall not be used. (No data will be + transfered) + 4 + 4 + + + RWSTART + Read wait start. If this bit is set, + read wait operation starts. + 8 + 1 + + + RWSTOP + Read wait stop This bit is written by + firmware and auto cleared by hardware when the DPSM + moves from the READ_WAIT state to the WAIT_R or IDLE + state. + 9 + 1 + + + RWMOD + Read wait mode. This bit can only be + written by firmware when DPSM is inactive (DPSMACT = + 0). + 10 + 1 + + + SDIOEN + SD I/O interrupt enable functions This + bit can only be written by firmware when DPSM is + inactive (DPSMACT = 0). If this bit is set, the DPSM + enables the SD I/O card specific interrupt + operation. + 11 + 1 + + + BOOTACKEN + Enable the reception of the boot + acknowledgment. This bit can only be written by + firmware when DPSM is inactive (DPSMACT = + 0). + 12 + 1 + + + FIFORST + FIFO reset, will flush any remaining + data. This bit can only be written by firmware when + IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit + will only take effect when a transfer error or + transfer hold occurs. + 13 + 1 + + + + + DCNTR + DCNTR + The SDMMC_DCNTR register loads the value + from the data length register (see SDMMC_DLENR) when the + DPSM moves from the Idle state to the Wait_R or Wait_S + state. As data is transferred, the counter decrements the + value until it reaches 0. The DPSM then moves to the Idle + state and when there has been no error, the data status + end flag (DATAEND) is set. + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value When read, the number + of remaining data bytes to be transferred is + returned. Write has no effect. + 0 + 25 + + + + + STAR + STAR + The SDMMC_STAR register is a read-only + register. It contains two types of flag:Static flags + (bits [29,21,11:0]): these bits remain asserted until + they are cleared by writing to the SDMMC interrupt Clear + register (see SDMMC_ICR)Dynamic flags (bits [20:12]): + these bits change state depending on the state of the + underlying logic (for example, FIFO full and empty flags + are asserted and de-asserted as data while written to the + FIFO) + 0x34 + 0x20 + read-only + 0x00000000 + + + CCRCFAIL + Command response received (CRC check + failed). Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 0 + 1 + + + DCRCFAIL + Data block sent/received (CRC check + failed). Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 1 + 1 + + + CTIMEOUT + Command response timeout. Interrupt flag + is cleared by writing corresponding interrupt clear + bit in SDMMC_ICR. The Command Timeout period has a + fixed value of 64 SDMMC_CK clock + periods. + 2 + 1 + + + DTIMEOUT + Data timeout. Interrupt flag is cleared + by writing corresponding interrupt clear bit in + SDMMC_ICR. + 3 + 1 + + + TXUNDERR + Transmit FIFO underrun error or IDMA + read transfer error. Interrupt flag is cleared by + writing corresponding interrupt clear bit in + SDMMC_ICR. + 4 + 1 + + + RXOVERR + Received FIFO overrun error or IDMA + write transfer error. Interrupt flag is cleared by + writing corresponding interrupt clear bit in + SDMMC_ICR. + 5 + 1 + + + CMDREND + Command response received (CRC check + passed, or no CRC). Interrupt flag is cleared by + writing corresponding interrupt clear bit in + SDMMC_ICR. + 6 + 1 + + + CMDSENT + Command sent (no response required). + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 7 + 1 + + + DATAEND + Data transfer ended correctly. (data + counter, DATACOUNT is zero and no errors occur). + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 8 + 1 + + + DHOLD + Data transfer Hold. Interrupt flag is + cleared by writing corresponding interrupt clear bit + in SDMMC_ICR. + 9 + 1 + + + DBCKEND + Data block sent/received. (CRC check + passed) and DPSM moves to the READWAIT state. + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 10 + 1 + + + DABORT + Data transfer aborted by CMD12. + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 11 + 1 + + + DPSMACT + Data path state machine active, i.e. not + in Idle state. This is a hardware status flag only, + does not generate an interrupt. + 12 + 1 + + + CPSMACT + Command path state machine active, i.e. + not in Idle state. This is a hardware status flag + only, does not generate an interrupt. + 13 + 1 + + + TXFIFOHE + Transmit FIFO half empty At least half + the number of words can be written into the FIFO. + This bit is cleared when the FIFO becomes half+1 + full. + 14 + 1 + + + RXFIFOHF + Receive FIFO half full There are at + least half the number of words in the FIFO. This bit + is cleared when the FIFO becomes half+1 + empty. + 15 + 1 + + + TXFIFOF + Transmit FIFO full This is a hardware + status flag only, does not generate an interrupt. + This bit is cleared when one FIFO location becomes + empty. + 16 + 1 + + + RXFIFOF + Receive FIFO full This bit is cleared + when one FIFO location becomes empty. + 17 + 1 + + + TXFIFOE + Transmit FIFO empty This bit is cleared + when one FIFO location becomes full. + 18 + 1 + + + RXFIFOE + Receive FIFO empty This is a hardware + status flag only, does not generate an interrupt. + This bit is cleared when one FIFO location becomes + full. + 19 + 1 + + + BUSYD0 + Inverted value of SDMMC_D0 line (Busy), + sampled at the end of a CMD response and a second + time 2 SDMMC_CK cycles after the CMD response. This + bit is reset to not busy when the SDMMCD0 line + changes from busy to not busy. This bit does not + signal busy due to data transfer. This is a hardware + status flag only, it does not generate an + interrupt. + 20 + 1 + + + BUSYD0END + end of SDMMC_D0 Busy following a CMD + response detected. This indicates only end of busy + following a CMD response. This bit does not signal + busy due to data transfer. Interrupt flag is cleared + by writing corresponding interrupt clear bit in + SDMMC_ICR. + 21 + 1 + + + SDIOIT + SDIO interrupt received. Interrupt flag + is cleared by writing corresponding interrupt clear + bit in SDMMC_ICR. + 22 + 1 + + + ACKFAIL + Boot acknowledgment received (boot + acknowledgment check fail). Interrupt flag is cleared + by writing corresponding interrupt clear bit in + SDMMC_ICR. + 23 + 1 + + + ACKTIMEOUT + Boot acknowledgment timeout. Interrupt + flag is cleared by writing corresponding interrupt + clear bit in SDMMC_ICR. + 24 + 1 + + + VSWEND + Voltage switch critical timing section + completion. Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 25 + 1 + + + CKSTOP + SDMMC_CK stopped in Voltage switch + procedure. Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 26 + 1 + + + IDMATE + IDMA transfer error. Interrupt flag is + cleared by writing corresponding interrupt clear bit + in SDMMC_ICR. + 27 + 1 + + + IDMABTC + IDMA buffer transfer complete. interrupt + flag is cleared by writing corresponding interrupt + clear bit in SDMMC_ICR. + 28 + 1 + + + + + ICR + ICR + The SDMMC_ICR register is a write-only + register. Writing a bit with 1 clears the corresponding + bit in the SDMMC_STAR status register. + 0x38 + 0x20 + read-write + 0x00000000 + + + CCRCFAILC + CCRCFAIL flag clear bit Set by software + to clear the CCRCFAIL flag. + 0 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit Set by software + to clear the DCRCFAIL flag. + 1 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit Set by software + to clear the CTIMEOUT flag. + 2 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit Set by software + to clear the DTIMEOUT flag. + 3 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit Set by software + to clear TXUNDERR flag. + 4 + 1 + + + RXOVERRC + RXOVERR flag clear bit Set by software + to clear the RXOVERR flag. + 5 + 1 + + + CMDRENDC + CMDREND flag clear bit Set by software + to clear the CMDREND flag. + 6 + 1 + + + CMDSENTC + CMDSENT flag clear bit Set by software + to clear the CMDSENT flag. + 7 + 1 + + + DATAENDC + DATAEND flag clear bit Set by software + to clear the DATAEND flag. + 8 + 1 + + + DHOLDC + DHOLD flag clear bit Set by software to + clear the DHOLD flag. + 9 + 1 + + + DBCKENDC + DBCKEND flag clear bit Set by software + to clear the DBCKEND flag. + 10 + 1 + + + DABORTC + DABORT flag clear bit Set by software to + clear the DABORT flag. + 11 + 1 + + + BUSYD0ENDC + BUSYD0END flag clear bit Set by software + to clear the BUSYD0END flag. + 21 + 1 + + + SDIOITC + SDIOIT flag clear bit Set by software to + clear the SDIOIT flag. + 22 + 1 + + + ACKFAILC + ACKFAIL flag clear bit Set by software + to clear the ACKFAIL flag. + 23 + 1 + + + ACKTIMEOUTC + ACKTIMEOUT flag clear bit Set by + software to clear the ACKTIMEOUT flag. + 24 + 1 + + + VSWENDC + VSWEND flag clear bit Set by software to + clear the VSWEND flag. + 25 + 1 + + + CKSTOPC + CKSTOP flag clear bit Set by software to + clear the CKSTOP flag. + 26 + 1 + + + IDMATEC + IDMA transfer error clear bit Set by + software to clear the IDMATE flag. + 27 + 1 + + + IDMABTCC + IDMA buffer transfer complete clear bit + Set by software to clear the IDMABTC + flag. + 28 + 1 + + + + + MASKR + MASKR + The interrupt mask register determines which + status flags generate an interrupt request by setting the + corresponding bit to 1. + 0x3C + 0x20 + read-write + 0x00000000 + + + CCRCFAILIE + Command CRC fail interrupt enable Set + and cleared by software to enable/disable interrupt + caused by command CRC failure. + 0 + 1 + + + DCRCFAILIE + Data CRC fail interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data CRC failure. + 1 + 1 + + + CTIMEOUTIE + Command timeout interrupt enable Set and + cleared by software to enable/disable interrupt + caused by command timeout. + 2 + 1 + + + DTIMEOUTIE + Data timeout interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data timeout. + 3 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt enable + Set and cleared by software to enable/disable + interrupt caused by Tx FIFO underrun + error. + 4 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt enable + Set and cleared by software to enable/disable + interrupt caused by Rx FIFO overrun + error. + 5 + 1 + + + CMDRENDIE + Command response received interrupt + enable Set and cleared by software to enable/disable + interrupt caused by receiving command + response. + 6 + 1 + + + CMDSENTIE + Command sent interrupt enable Set and + cleared by software to enable/disable interrupt + caused by sending command. + 7 + 1 + + + DATAENDIE + Data end interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data end. + 8 + 1 + + + DHOLDIE + Data hold interrupt enable Set and + cleared by software to enable/disable the interrupt + generated when sending new data is hold in the DPSM + Wait_S state. + 9 + 1 + + + DBCKENDIE + Data block end interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data block end. + 10 + 1 + + + DABORTIE + Data transfer aborted interrupt enable + Set and cleared by software to enable/disable + interrupt caused by a data transfer being + aborted. + 11 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt enable Set + and cleared by software to enable/disable interrupt + caused by Tx FIFO half empty. + 14 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt enable Set + and cleared by software to enable/disable interrupt + caused by Rx FIFO half full. + 15 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt enable Set and + cleared by software to enable/disable interrupt + caused by Rx FIFO full. + 17 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt enable Set and + cleared by software to enable/disable interrupt + caused by Tx FIFO empty. + 18 + 1 + + + BUSYD0ENDIE + BUSYD0END interrupt enable Set and + cleared by software to enable/disable the interrupt + generated when SDMMC_D0 signal changes from busy to + NOT busy following a CMD response. + 21 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable Set and cleared by software to enable/disable + the interrupt generated when receiving the SDIO mode + interrupt. + 22 + 1 + + + ACKFAILIE + Acknowledgment Fail interrupt enable Set + and cleared by software to enable/disable interrupt + caused by acknowledgment Fail. + 23 + 1 + + + ACKTIMEOUTIE + Acknowledgment timeout interrupt enable + Set and cleared by software to enable/disable + interrupt caused by acknowledgment + timeout. + 24 + 1 + + + VSWENDIE + Voltage switch critical timing section + completion interrupt enable Set and cleared by + software to enable/disable the interrupt generated + when voltage switch critical timing section + completion. + 25 + 1 + + + CKSTOPIE + Voltage Switch clock stopped interrupt + enable Set and cleared by software to enable/disable + interrupt caused by Voltage Switch clock + stopped. + 26 + 1 + + + IDMABTCIE + IDMA buffer transfer complete interrupt + enable Set and cleared by software to enable/disable + the interrupt generated when the IDMA has transferred + all data belonging to a memory buffer. + 28 + 1 + + + + + ACKTIMER + ACKTIMER + The SDMMC_ACKTIMER register contains the + acknowledgment timeout period, in SDMMC_CK bus clock + periods. A counter loads the value from the + SDMMC_ACKTIMER register, and starts decrementing when the + data path state machine (DPSM) enters the Wait_Ack state. + If the timer reaches 0 while the DPSM is in this states, + the acknowledgment timeout status flag is + set. + 0x40 + 0x20 + read-write + 0x00000000 + + + ACKTIME + Boot acknowledgment timeout period This + bit can only be written by firmware when CPSM is + disabled (CPSMEN = 0). Boot acknowledgment timeout + period expressed in card bus clock + periods. + 0 + 25 + + + + + IDMACTRLR + IDMACTRLR + The receive and transmit FIFOs can be read + or written as 32-bit wide registers. The FIFOs contain 32 + entries on 32 sequential addresses. This allows the CPU + to use its load and store multiple operands to read + from/write to the FIFO. + 0x50 + 0x20 + read-write + 0x00000000 + + + IDMAEN + IDMA enable This bit can only be written + by firmware when DPSM is inactive (DPSMACT = + 0). + 0 + 1 + + + IDMABMODE + Buffer mode selection. This bit can only + be written by firmware when DPSM is inactive (DPSMACT + = 0). + 1 + 1 + + + IDMABACT + Double buffer mode active buffer + indication This bit can only be written by firmware + when DPSM is inactive (DPSMACT = 0). When IDMA is + enabled this bit is toggled by + hardware. + 2 + 1 + + + + + IDMABSIZER + IDMABSIZER + The SDMMC_IDMABSIZER register contains the + buffers size when in double buffer + configuration. + 0x54 + 0x20 + read-write + 0x00000000 + + + IDMABNDT + Number of transfers per buffer. This + 8-bit value shall be multiplied by 8 to get the size + of the buffer in 32-bit words and by 32 to get the + size of the buffer in bytes. Example: IDMABNDT = + 0x01: buffer size = 8 words = 32 bytes. These bits + can only be written by firmware when DPSM is inactive + (DPSMACT = 0). + 5 + 8 + + + + + IDMABASE0R + IDMABASE0R + The SDMMC_IDMABASE0R register contains the + memory buffer base address in single buffer configuration + and the buffer 0 base address in double buffer + configuration. + 0x58 + 0x20 + read-write + 0x00000000 + + + IDMABASE0 + Buffer 0 memory base address bits + [31:2], shall be word aligned (bit [1:0] are always 0 + and read only). This register can be written by + firmware when DPSM is inactive (DPSMACT = 0), and can + dynamically be written by firmware when DPSM active + (DPSMACT = 1) and memory buffer 0 is inactive + (IDMABACT = 1). + 0 + 32 + + + + + IDMABASE1R + IDMABASE1R + The SDMMC_IDMABASE1R register contains the + double buffer configuration second buffer memory base + address. + 0x5C + 0x20 + read-write + 0x00000000 + + + IDMABASE1 + Buffer 1 memory base address, shall be + word aligned (bit [1:0] are always 0 and read only). + This register can be written by firmware when DPSM is + inactive (DPSMACT = 0), and can dynamically be + written by firmware when DPSM active (DPSMACT = 1) + and memory buffer 1 is inactive (IDMABACT = + 0). + 0 + 32 + + + + + FIFOR + FIFOR + The receive and transmit FIFOs can be only + read or written as word (32-bit) wide registers. The + FIFOs contain 16 entries on sequential addresses. This + allows the CPU to use its load and store multiple + operands to read from/write to the FIFO.When accessing + SDMMC_FIFOR with half word or byte access an AHB bus + fault is generated. + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data This + register can only be read or written by firmware when + the DPSM is active (DPSMACT=1). The FIFO data + occupies 16 entries of 32-bit words. + 0 + 32 + + + + + RESPCMDR + RESPCMDR + SDMMC command response + register + 0x10 + 0x20 + read-only + 0xA3C5DD01 + + + RESPCMD + Response command index + 0 + 6 + + + + + + + SDMMC2 + 0x48022400 + + + VREFBUF + VREFBUF + VREFBUF + 0x58003C00 + + 0x0 + 0x400 + registers + + + + CSR + CSR + VREFBUF control and status + register + 0x0 + 0x20 + 0x00000002 + + + ENVR + Voltage reference buffer mode enable + This bit is used to enable the voltage reference + buffer mode. + 0 + 1 + read-write + + + HIZ + High impedance mode This bit controls + the analog switch to connect or not the VREF+ pin. + Refer to Table196: VREF buffer modes for the mode + descriptions depending on ENVR bit + configuration. + 1 + 1 + read-write + + + VRR + Voltage reference buffer + ready + 3 + 1 + read-only + + + VRS + Voltage reference scale These bits + select the value generated by the voltage reference + buffer. Other: Reserved + 4 + 3 + read-write + + + + + CCR + CCR + VREFBUF calibration control + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIM + Trimming code These bits are + automatically initialized after reset with the + trimming value stored in the Flash memory during the + production test. Writing into these bits allows to + tune the internal reference buffer + voltage. + 0 + 6 + + + + + + + IWDG1 + IWDG + IWDG + 0x58004800 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0x0000) + These bits must be written by software at regular + intervals with the key value 0xAAAA, otherwise the + watchdog generates a reset when the counter reaches + 0. Writing the key value 0x5555 to enable access to + the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see + Section23.3.6: Register access protection) Writing + the key value CCCCh starts the watchdog (except if + the hardware watchdog option is + selected) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider These bits are write + access protected see Section23.3.6: Register access + protection. They are written by software to select + the prescaler divider feeding the counter clock. PVU + bit of IWDG_SR must be reset in order to be able to + change the prescaler divider. Note: Reading this + register returns the prescaler value from the VDD + voltage domain. This value may not be up to + date/valid if a write operation to this register is + ongoing. For this reason the value read from this + register is valid only when the PVU bit in the + IWDG_SR register is reset. + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value These bits + are write access protected see Section23.3.6. They + are written by software to define the value to be + loaded in the watchdog counter each time the value + 0xAAAA is written in the IWDG_KR register. The + watchdog counter counts down from this value. The + timeout period is a function of this value and the + clock prescaler. Refer to the datasheet for the + timeout information. The RVU bit in the IWDG_SR + register must be reset in order to be able to change + the reload value. Note: Reading this register returns + the reload value from the VDD voltage domain. This + value may not be up to date/valid if a write + operation to this register is ongoing on this + register. For this reason the value read from this + register is valid only when the RVU bit in the + IWDG_SR register is reset. + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update This bit + is set by hardware to indicate that an update of the + prescaler value is ongoing. It is reset by hardware + when the prescaler update operation is completed in + the VDD voltage domain (takes up to 5 RC 40 kHz + cycles). Prescaler value can be updated only when PVU + bit is reset. + 0 + 1 + + + RVU + Watchdog counter reload value update + This bit is set by hardware to indicate that an + update of the reload value is ongoing. It is reset by + hardware when the reload value update operation is + completed in the VDD voltage domain (takes up to 5 RC + 40 kHz cycles). Reload value can be updated only when + RVU bit is reset. + 1 + 1 + + + WVU + Watchdog counter window value update + This bit is set by hardware to indicate that an + update of the window value is ongoing. It is reset by + hardware when the reload value update operation is + completed in the VDD voltage domain (takes up to 5 RC + 40 kHz cycles). Window value can be updated only when + WVU bit is reset. This bit is generated only if + generic window = 1 + 2 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value These bits + are write access protected see Section23.3.6. These + bits contain the high limit of the window value to be + compared to the downcounter. To prevent a reset, the + downcounter must be reloaded when its value is lower + than the window register value and greater than 0x0 + The WVU bit in the IWDG_SR register must be reset in + order to be able to change the reload value. Note: + Reading this register returns the reload value from + the VDD voltage domain. This value may not be valid + if a write operation to this register is ongoing. For + this reason the value read from this register is + valid only when the WVU bit in the IWDG_SR register + is reset. + 0 + 12 + + + + + + + IWDG2 + 0x58004C00 + + + WWDG1 + WWDG + WWDG + 0x50003000 + + 0x0 + 0x400 + registers + + + WWDG1_RST + Window Watchdog interrupt + 143 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + T + 7-bit counter (MSB to LSB) These bits + contain the value of the watchdog counter. It is + decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A + reset is produced when it is decremented from 0x40 to + 0x3F (T6 becomes cleared). + 0 + 7 + + + WDGA + Activation bit This bit is set by + software and only cleared by hardware after a reset. + When WDGA=1, the watchdog can generate a + reset. + 7 + 1 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + W + 7-bit window value These bits contain + the window value to be compared to the + downcounter. + 0 + 7 + + + WDGTB + Timer base The time base of the + prescaler can be modified as follows: + 11 + 2 + + + EWI + Early wakeup interrupt When set, an + interrupt occurs whenever the counter reaches the + value 0x40. This interrupt is only cleared by + hardware after a reset. + 9 + 1 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag This bit is + set by hardware when the counter has reached the + value 0x40. It must be cleared by software by writing + 0. A write of 1 has no effect. This bit is also set + if the interrupt is not enabled. + 0 + 1 + + + + + + + WWDG2 + 0x40002C00 + + WWDG2 + Window Watchdog interrupt + 0 + + + + PWR + PWR + PWR + 0x58024800 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + PWR control register 1 + 0x0 + 0x20 + read-write + 0xF000C000 + + + LPDS + Low-power Deepsleep with SVOS3 (SVOS4 + and SVOS5 always use low-power, regardless of the + setting of this bit) + 0 + 1 + + + PVDE + Programmable voltage detector + enable + 4 + 1 + + + PLS + Programmable voltage detector level + selection These bits select the voltage threshold + detected by the PVD. Note: Refer to Section + Electrical characteristics of the product datasheet + for more details. + 5 + 3 + + + DBP + Disable backup domain write protection + In reset state, the RCC_BDCR register, the RTC + registers (including the backup registers), BREN and + MOEN bits in PWR_CR2 register, are protected against + parasitic write access. This bit must be set to + enable write access to these registers. + 8 + 1 + + + FLPS + Flash low-power mode in DStop mode This + bit allows to obtain the best trade-off between + low-power consumption and restart time when exiting + from DStop mode. When it is set, the Flash memory + enters low-power mode when D1 domain is in DStop + mode. + 9 + 1 + + + SVOS + System Stop mode voltage scaling + selection These bits control the VCORE voltage level + in system Stop mode, to obtain the best trade-off + between power consumption and + performance. + 14 + 2 + + + AVDEN + Peripheral voltage monitor on VDDA + enable + 16 + 1 + + + ALS + Analog voltage detector level selection + These bits select the voltage threshold detected by + the AVD. + 17 + 2 + + + + + CSR1 + CSR1 + PWR control status register 1 + 0x4 + 0x20 + read-only + 0x00004000 + + + PVDO + Programmable voltage detect output This + bit is set and cleared by hardware. It is valid only + if the PVD has been enabled by the PVDE bit. Note: + since the PVD is disabled in Standby mode, this bit + is equal to 0 after Standby or reset until the PVDE + bit is set. + 4 + 1 + + + ACTVOSRDY + Voltage levels ready bit for currently + used VOS and SDLEVEL This bit is set to 1 by hardware + when the voltage regulator and the SD converter are + both disabled and Bypass mode is selected in PWR + control register 3 (PWR_CR3). + 13 + 1 + + + ACTVOS + VOS currently applied for VCORE voltage + scaling selection. These bits reflect the last VOS + value applied to the PMU. + 14 + 2 + + + AVDO + Analog voltage detector output on VDDA + This bit is set and cleared by hardware. It is valid + only if AVD on VDDA is enabled by the AVDEN bit. + Note: Since the AVD is disabled in Standby mode, this + bit is equal to 0 after Standby or reset until the + AVDEN bit is set. + 16 + 1 + + + + + CR2 + CR2 + This register is not reset by wakeup from + Standby mode, RESET signal and VDD POR. It is only reset + by VSW POR and VSWRST reset. This register shall not be + accessed when VSWRST bit in RCC_BDCR register resets the + VSW domain.After reset, PWR_CR2 register is + write-protected. Prior to modifying its content, the DBP + bit in PWR_CR1 register must be set to disable the write + protection. + 0x8 + 0x20 + 0x00000000 + + + BREN + Backup regulator enable When set, the + Backup regulator (used to maintain the backup RAM + content in Standby and VBAT modes) is enabled. If + BREN is reset, the backup regulator is switched off. + The backup RAM can still be used in Run and Stop + modes. However, its content will be lost in Standby + and VBAT modes. If BREN is set, the application must + wait till the Backup Regulator Ready flag (BRRDY) is + set to indicate that the data written into the SRAM + will be maintained in Standby and VBAT + modes. + 0 + 1 + read-write + + + MONEN + VBAT and temperature monitoring enable + When set, the VBAT supply and temperature monitoring + is enabled. + 4 + 1 + read-write + + + BRRDY + Backup regulator ready This bit is set + by hardware to indicate that the Backup regulator is + ready. + 16 + 1 + read-only + + + VBATL + VBAT level monitoring versus low + threshold + 20 + 1 + read-only + + + VBATH + VBAT level monitoring versus high + threshold + 21 + 1 + read-only + + + TEMPL + Temperature level monitoring versus low + threshold + 22 + 1 + read-only + + + TEMPH + Temperature level monitoring versus high + threshold + 23 + 1 + read-only + + + + + CR3 + CR3 + Reset only by POR only, not reset by wakeup + from Standby mode and RESET pad. The lower byte of this + register is written once after POR and shall be written + before changing VOS level or ck_sys clock frequency. No + limitation applies to the upper bytes.Programming data + corresponding to an invalid combination of SDLEVEL, + SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be + ignored: data will not be written, the written-once + mechanism will lock the register and any further write + access will be ignored. The default supply configuration + will be kept and the ACTVOSRDY bit in PWR control status + register 1 (PWR_CSR1) will go on indicating invalid + voltage levels. The system shall be power cycled before + writing a new value. + 0xC + 0x20 + 0x00000006 + + + BYPASS + Power management unit + bypass + 0 + 1 + read-write + + + LDOEN + Low drop-out regulator + enable + 1 + 1 + read-write + + + SDEN + SD converter Enable + 2 + 1 + read-write + + + VBE + VBAT charging enable + 8 + 1 + read-write + + + VBRS + VBAT charging resistor + selection + 9 + 1 + read-write + + + USB33DEN + VDD33USB voltage level detector + enable. + 24 + 1 + write-only + + + USBREGEN + USB regulator enable. + 25 + 1 + read-write + + + USB33RDY + USB supply ready. + 26 + 1 + read-only + + + + + CPUCR + CPUCR + This register allows controlling CPU1 + power. + 0x10 + 0x20 + 0x00000000 + + + PDDS_D1 + D1 domain Power Down Deepsleep + selection. This bit allows CPU1 to define the + Deepsleep mode for D1 domain. + 0 + 1 + read-write + + + PDDS_D2 + D2 domain Power Down Deepsleep. This bit + allows CPU1 to define the Deepsleep mode for D2 + domain. + 1 + 1 + read-write + + + PDDS_D3 + System D3 domain Power Down Deepsleep. + This bit allows CPU1 to define the Deepsleep mode for + System D3 domain. + 2 + 1 + read-write + + + STOPF + STOP flag This bit is set by hardware + and cleared only by any reset or by setting the CPU1 + CSSF bit. + 5 + 1 + read-only + + + SBF + System Standby flag This bit is set by + hardware and cleared only by a POR (Power-on Reset) + or by setting the CPU1 CSSF bit + 6 + 1 + read-only + + + SBF_D1 + D1 domain DStandby flag This bit is set + by hardware and cleared by any system reset or by + setting the CPU1 CSSF bit. Once set, this bit can be + cleared only when the D1 domain is no longer in + DStandby mode. + 7 + 1 + read-only + + + SBF_D2 + D2 domain DStandby flag This bit is set + by hardware and cleared by any system reset or by + setting the CPU1 CSSF bit. Once set, this bit can be + cleared only when the D2 domain is no longer in + DStandby mode. + 8 + 1 + read-only + + + CSSF + Clear D1 domain CPU1 Standby, Stop and + HOLD flags (always read as 0) This bit is cleared to + 0 by hardware. + 9 + 1 + read-write + + + RUN_D3 + Keep system D3 domain in Run mode + regardless of the CPU sub-systems modes + 11 + 1 + read-write + + + + + D3CR + D3CR + This register allows controlling D3 domain + power.Following reset VOSRDY will be read 1 by + software + 0x18 + 0x20 + 0x00004000 + + + VOSRDY + VOS Ready bit for VCORE voltage scaling + output selection. This bit is set to 1 by hardware + when Bypass mode is selected in PWR control register + 3 (PWR_CR3). + 13 + 1 + read-only + + + VOS + Voltage scaling selection according to + performance These bits control the VCORE voltage + level and allow to obtains the best trade-off between + power consumption and performance: When increasing + the performance, the voltage scaling shall be changed + before increasing the system frequency. When + decreasing performance, the system frequency shall + first be decreased before changing the voltage + scaling. + 14 + 2 + read-write + + + + + WKUPCR + WKUPCR + reset only by system reset, not reset by + wakeup from Standby mode5 wait states are required when + writing this register (when clearing a WKUPF bit in + PWR_WKUPFR, the AHB write access will complete after the + WKUPF has been cleared). + 0x20 + 0x20 + read-write + 0x00000000 + + + WKUPC + Clear Wakeup pin flag for WKUP. These + bits are always read as 0. + 0 + 6 + + + + + WKUPFR + WKUPFR + reset only by system reset, not reset by + wakeup from Standby mode + 0x24 + 0x20 + read-write + 0x00000000 + + + WKUPF1 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 0 + 1 + + + WKUPF2 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 1 + 1 + + + WKUPF3 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 2 + 1 + + + WKUPF4 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 3 + 1 + + + WKUPF5 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 4 + 1 + + + WKUPF6 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 5 + 1 + + + + + WKUPEPR + WKUPEPR + Reset only by system reset, not reset by + wakeup from Standby mode + 0x28 + 0x20 + read-write + 0x00000000 + + + WKUPEN1 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 0 + 1 + + + WKUPEN2 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 1 + 1 + + + WKUPEN3 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 2 + 1 + + + WKUPEN4 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 3 + 1 + + + WKUPEN5 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 4 + 1 + + + WKUPEN6 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 5 + 1 + + + WKUPP1 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 8 + 1 + + + WKUPP2 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 9 + 1 + + + WKUPP3 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 10 + 1 + + + WKUPP4 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 11 + 1 + + + WKUPP5 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 12 + 1 + + + WKUPP6 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 13 + 1 + + + WKUPPUPD1 + Wakeup pin pull + configuration + 16 + 2 + + + WKUPPUPD2 + Wakeup pin pull + configuration + 18 + 2 + + + WKUPPUPD3 + Wakeup pin pull + configuration + 20 + 2 + + + WKUPPUPD4 + Wakeup pin pull + configuration + 22 + 2 + + + WKUPPUPD5 + Wakeup pin pull + configuration + 24 + 2 + + + WKUPPUPD6 + Wakeup pin pull configuration for + WKUP(truncate(n/2)-7) These bits define the I/O pad + pull configuration used when WKUPEN(truncate(n/2)-7) + = 1. The associated GPIO port pull configuration + shall be set to the same value or to 00. The Wakeup + pin pull configuration is kept in Standby + mode. + 26 + 2 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + 0x00000000 + + + IOLOCK + Locking the AF configuration of + associated IOs + 16 + 1 + read-only + + + TCRCI + CRC calculation initialization pattern + control for transmitter + 15 + 1 + read-write + + + RCRCI + CRC calculation initialization pattern + control for receiver + 14 + 1 + read-write + + + CRC33_17 + 32-bit CRC polynomial + configuration + 13 + 1 + read-write + + + SSI + Internal SS signal input + level + 12 + 1 + read-write + + + HDDIR + Rx/Tx direction at Half-duplex + mode + 11 + 1 + read-write + + + CSUSP + Master SUSPend request + 10 + 1 + write-only + + + CSTART + Master transfer start + 9 + 1 + read-only + + + MASRX + Master automatic SUSP in Receive + mode + 8 + 1 + read-write + + + SPE + Serial Peripheral Enable + 0 + 1 + read-write + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + 0x00000000 + + + TSER + Number of data transfer extension to be + reload into TSIZE just when a previous + 16 + 16 + read-only + + + TSIZE + Number of data at current + transfer + 0 + 16 + read-write + + + + + CFG1 + CFG1 + configuration register 1 + 0x8 + 0x20 + read-write + 0x00070007 + + + MBR + Master baud rate + 28 + 3 + + + CRCEN + Hardware CRC computation + enable + 22 + 1 + + + CRCSIZE + Length of CRC frame to be transacted and + compared + 16 + 5 + + + TXDMAEN + Tx DMA stream enable + 15 + 1 + + + RXDMAEN + Rx DMA stream enable + 14 + 1 + + + UDRDET + Detection of underrun condition at slave + transmitter + 11 + 2 + + + UDRCFG + Behavior of slave transmitter at + underrun condition + 9 + 2 + + + FTHVL + threshold level + 5 + 4 + + + DSIZE + Number of bits in at single SPI data + frame + 0 + 5 + + + + + CFG2 + CFG2 + configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + AFCNTR + Alternate function GPIOs + control + 31 + 1 + + + SSOM + SS output management in master + mode + 30 + 1 + + + SSOE + SS output enable + 29 + 1 + + + SSIOP + SS input/output polarity + 28 + 1 + + + SSM + Software management of SS signal + input + 26 + 1 + + + CPOL + Clock polarity + 25 + 1 + + + CPHA + Clock phase + 24 + 1 + + + LSBFRST + Data frame format + 23 + 1 + + + MASTER + SPI Master + 22 + 1 + + + SP + Serial Protocol + 19 + 3 + + + COMM + SPI Communication Mode + 17 + 2 + + + IOSWP + Swap functionality of MISO and MOSI + pins + 15 + 1 + + + MIDI + Master Inter-Data Idleness + 4 + 4 + + + MSSI + Master SS Idleness + 0 + 4 + + + + + IER + IER + Interrupt Enable Register + 0x10 + 0x20 + 0x00000000 + + + TSERFIE + Additional number of transactions reload + interrupt enable + 10 + 1 + read-write + + + MODFIE + Mode Fault interrupt + enable + 9 + 1 + read-write + + + TIFREIE + TIFRE interrupt enable + 8 + 1 + read-write + + + CRCEIE + CRC Interrupt enable + 7 + 1 + read-write + + + OVRIE + OVR interrupt enable + 6 + 1 + read-write + + + UDRIE + UDR interrupt enable + 5 + 1 + read-write + + + TXTFIE + TXTFIE interrupt enable + 4 + 1 + read-write + + + EOTIE + EOT, SUSP and TXC interrupt + enable + 3 + 1 + read-write + + + DPXPIE + DXP interrupt enabled + 2 + 1 + read-only + + + TXPIE + TXP interrupt enable + 1 + 1 + read-only + + + RXPIE + RXP Interrupt Enable + 0 + 1 + read-write + + + + + SR + SR + Status Register + 0x14 + 0x20 + read-only + 0x00001002 + + + CTSIZE + Number of data frames remaining in + current TSIZE session + 16 + 16 + + + RXWNE + RxFIFO Word Not Empty + 15 + 1 + + + RXPLVL + RxFIFO Packing LeVeL + 13 + 2 + + + TXC + TxFIFO transmission + complete + 12 + 1 + + + SUSP + SUSPend + 11 + 1 + + + TSERF + Additional number of SPI data to be + transacted was reload + 10 + 1 + + + MODF + Mode Fault + 9 + 1 + + + TIFRE + TI frame format error + 8 + 1 + + + CRCE + CRC Error + 7 + 1 + + + OVR + Overrun + 6 + 1 + + + UDR + Underrun at slave transmission + mode + 5 + 1 + + + TXTF + Transmission Transfer + Filled + 4 + 1 + + + EOT + End Of Transfer + 3 + 1 + + + DXP + Duplex Packet + 2 + 1 + + + TXP + Tx-Packet space available + 1 + 1 + + + RXP + Rx-Packet available + 0 + 1 + + + + + IFCR + IFCR + Interrupt/Status Flags Clear + Register + 0x18 + 0x20 + write-only + 0x00000000 + + + SUSPC + SUSPend flag clear + 11 + 1 + + + TSERFC + TSERFC flag clear + 10 + 1 + + + MODFC + Mode Fault flag clear + 9 + 1 + + + TIFREC + TI frame format error flag + clear + 8 + 1 + + + CRCEC + CRC Error flag clear + 7 + 1 + + + OVRC + Overrun flag clear + 6 + 1 + + + UDRC + Underrun flag clear + 5 + 1 + + + TXTFC + Transmission Transfer Filled flag + clear + 4 + 1 + + + EOTC + End Of Transfer flag clear + 3 + 1 + + + + + TXDR + TXDR + Transmit Data Register + 0x20 + 0x20 + write-only + 0x00000000 + + + TXDR + Transmit data register + 0 + 32 + + + + + RXDR + RXDR + Receive Data Register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDR + Receive data register + 0 + 32 + + + + + CRCPOLY + CRCPOLY + Polynomial Register + 0x40 + 0x20 + read-write + 0x00000107 + + + CRCPOLY + CRC polynomial register + 0 + 32 + + + + + TXCRC + TXCRC + Transmitter CRC Register + 0x44 + 0x20 + read-write + 0x00000000 + + + TXCRC + CRC register for + transmitter + 0 + 32 + + + + + RXCRC + RXCRC + Receiver CRC Register + 0x48 + 0x20 + read-write + 0x00000000 + + + RXCRC + CRC register for receiver + 0 + 32 + + + + + UDRDR + UDRDR + Underrun Data Register + 0x4C + 0x20 + read-write + 0x00000000 + + + UDRDR + Data at slave underrun + condition + 0 + 32 + + + + + CGFR + CGFR + configuration register + 0x50 + 0x20 + read-write + 0x00000000 + + + MCKOE + Master clock output enable + 25 + 1 + + + ODD + Odd factor for the + prescaler + 24 + 1 + + + I2SDIV + I2S linear prescaler + 16 + 8 + + + DATFMT + Data format + 14 + 1 + + + WSINV + Fixed channel length in + SLAVE + 13 + 1 + + + FIXCH + Word select inversion + 12 + 1 + + + CKPOL + Serial audio clock + polarity + 11 + 1 + + + CHLEN + Channel length (number of bits per audio + channel) + 10 + 1 + + + DATLEN + Data length to be + transferred + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + I2SCFG + I2S configuration mode + 1 + 3 + + + I2SMOD + I2S mode selection + 0 + 1 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40013400 + + SPI4 + SPI4 global interrupt + 84 + + + + SPI5 + 0x40015000 + + SPI5 + SPI5 global interrupt + 85 + + + + SPI6 + 0x58001400 + + SPI6 + SPI6 global interrupt + 86 + + + + LTDC + LCD-TFT Controller + LTDC + 0x50001000 + + 0x0 + 0x1000 + registers + + + LTDC + LCD-TFT global interrupt + 88 + + + LTDC_ER + LCD-TFT error interrupt + 89 + + + + SSCR + SSCR + Synchronization Size Configuration + Register + 0x8 + 0x20 + read-write + 0x00000000 + + + HSW + Horizontal Synchronization Width (in + units of pixel clock period) + 16 + 10 + + + VSH + Vertical Synchronization Height (in + units of horizontal scan line) + 0 + 11 + + + + + BPCR + BPCR + Back Porch Configuration + Register + 0xC + 0x20 + read-write + 0x00000000 + + + AHBP + Accumulated Horizontal back porch (in + units of pixel clock period) + 16 + 12 + + + AVBP + Accumulated Vertical back porch (in + units of horizontal scan line) + 0 + 11 + + + + + AWCR + AWCR + Active Width Configuration + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + AAV + AAV + 16 + 12 + + + AAH + Accumulated Active Height (in units of + horizontal scan line) + 0 + 11 + + + + + TWCR + TWCR + Total Width Configuration + Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTALW + Total Width (in units of pixel clock + period) + 16 + 12 + + + TOTALH + Total Height (in units of horizontal + scan line) + 0 + 11 + + + + + GCR + GCR + Global Control Register + 0x18 + 0x20 + 0x00002220 + + + HSPOL + Horizontal Synchronization + Polarity + 31 + 1 + read-write + + + VSPOL + Vertical Synchronization + Polarity + 30 + 1 + read-write + + + DEPOL + Data Enable Polarity + 29 + 1 + read-write + + + PCPOL + Pixel Clock Polarity + 28 + 1 + read-write + + + DEN + Dither Enable + 16 + 1 + read-write + + + DRW + Dither Red Width + 12 + 3 + read-only + + + DGW + Dither Green Width + 8 + 3 + read-only + + + DBW + Dither Blue Width + 4 + 3 + read-only + + + LTDCEN + LCD-TFT controller enable + bit + 0 + 1 + read-write + + + + + SRCR + SRCR + Shadow Reload Configuration + Register + 0x24 + 0x20 + read-write + 0x00000000 + + + VBR + Vertical Blanking Reload + 1 + 1 + + + IMR + Immediate Reload + 0 + 1 + + + + + BCCR + BCCR + Background Color Configuration + Register + 0x2C + 0x20 + read-write + 0x00000000 + + + BCBLUE + Background Color Blue + value + 0 + 8 + + + BCGREEN + Background Color Green + value + 8 + 8 + + + BCRED + Background Color Red value + 16 + 8 + + + + + IER + IER + Interrupt Enable Register + 0x34 + 0x20 + read-write + 0x00000000 + + + RRIE + Register Reload interrupt + enable + 3 + 1 + + + TERRIE + Transfer Error Interrupt + Enable + 2 + 1 + + + FUIE + FIFO Underrun Interrupt + Enable + 1 + 1 + + + LIE + Line Interrupt Enable + 0 + 1 + + + + + ISR + ISR + Interrupt Status Register + 0x38 + 0x20 + read-only + 0x00000000 + + + RRIF + Register Reload Interrupt + Flag + 3 + 1 + + + TERRIF + Transfer Error interrupt + flag + 2 + 1 + + + FUIF + FIFO Underrun Interrupt + flag + 1 + 1 + + + LIF + Line Interrupt flag + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x3C + 0x20 + write-only + 0x00000000 + + + CRRIF + Clears Register Reload Interrupt + Flag + 3 + 1 + + + CTERRIF + Clears the Transfer Error Interrupt + Flag + 2 + 1 + + + CFUIF + Clears the FIFO Underrun Interrupt + flag + 1 + 1 + + + CLIF + Clears the Line Interrupt + Flag + 0 + 1 + + + + + LIPCR + LIPCR + Line Interrupt Position Configuration + Register + 0x40 + 0x20 + read-write + 0x00000000 + + + LIPOS + Line Interrupt Position + 0 + 11 + + + + + CPSR + CPSR + Current Position Status + Register + 0x44 + 0x20 + read-only + 0x00000000 + + + CXPOS + Current X Position + 16 + 16 + + + CYPOS + Current Y Position + 0 + 16 + + + + + CDSR + CDSR + Current Display Status + Register + 0x48 + 0x20 + read-only + 0x0000000F + + + HSYNCS + Horizontal Synchronization display + Status + 3 + 1 + + + VSYNCS + Vertical Synchronization display + Status + 2 + 1 + + + HDES + Horizontal Data Enable display + Status + 1 + 1 + + + VDES + Vertical Data Enable display + Status + 0 + 1 + + + + + L1CR + L1CR + Layerx Control Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + + COLKEN + Color Keying Enable + 1 + 1 + + + LEN + Layer Enable + 0 + 1 + + + + + L1WHPCR + L1WHPCR + Layerx Window Horizontal Position + Configuration Register + 0x88 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop + Position + 16 + 12 + + + WHSTPOS + Window Horizontal Start + Position + 0 + 12 + + + + + L1WVPCR + L1WVPCR + Layerx Window Vertical Position + Configuration Register + 0x8C + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop + Position + 16 + 11 + + + WVSTPOS + Window Vertical Start + Position + 0 + 11 + + + + + L1CKCR + L1CKCR + Layerx Color Keying Configuration + Register + 0x90 + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + CKGREEN + Color Key Green value + 8 + 8 + + + CKBLUE + Color Key Blue value + 0 + 8 + + + + + L1PFCR + L1PFCR + Layerx Pixel Format Configuration + Register + 0x94 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + + + + L1CACR + L1CACR + Layerx Constant Alpha Configuration + Register + 0x98 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + + + L1DCCR + L1DCCR + Layerx Default Color Configuration + Register + 0x9C + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + DCRED + Default Color Red + 16 + 8 + + + DCGREEN + Default Color Green + 8 + 8 + + + DCBLUE + Default Color Blue + 0 + 8 + + + + + L1BFCR + L1BFCR + Layerx Blending Factors Configuration + Register + 0xA0 + 0x20 + read-write + 0x00000607 + + + BF1 + Blending Factor 1 + 8 + 3 + + + BF2 + Blending Factor 2 + 0 + 3 + + + + + L1CFBAR + L1CFBAR + Layerx Color Frame Buffer Address + Register + 0xAC + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start + Address + 0 + 32 + + + + + L1CFBLR + L1CFBLR + Layerx Color Frame Buffer Length + Register + 0xB0 + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in + bytes + 16 + 13 + + + CFBLL + Color Frame Buffer Line + Length + 0 + 13 + + + + + L1CFBLNR + L1CFBLNR + Layerx ColorFrame Buffer Line Number + Register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + + + L1CLUTWR + L1CLUTWR + Layerx CLUT Write Register + 0xC4 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + RED + Red value + 16 + 8 + + + GREEN + Green value + 8 + 8 + + + BLUE + Blue value + 0 + 8 + + + + + L2CR + L2CR + Layerx Control Register + 0x104 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + + COLKEN + Color Keying Enable + 1 + 1 + + + LEN + Layer Enable + 0 + 1 + + + + + L2WHPCR + L2WHPCR + Layerx Window Horizontal Position + Configuration Register + 0x108 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop + Position + 16 + 12 + + + WHSTPOS + Window Horizontal Start + Position + 0 + 12 + + + + + L2WVPCR + L2WVPCR + Layerx Window Vertical Position + Configuration Register + 0x10C + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop + Position + 16 + 11 + + + WVSTPOS + Window Vertical Start + Position + 0 + 11 + + + + + L2CKCR + L2CKCR + Layerx Color Keying Configuration + Register + 0x110 + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + CKGREEN + Color Key Green value + 8 + 8 + + + CKBLUE + Color Key Blue value + 0 + 8 + + + + + L2PFCR + L2PFCR + Layerx Pixel Format Configuration + Register + 0x114 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + + + + L2CACR + L2CACR + Layerx Constant Alpha Configuration + Register + 0x118 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + + + L2DCCR + L2DCCR + Layerx Default Color Configuration + Register + 0x11C + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + DCRED + Default Color Red + 16 + 8 + + + DCGREEN + Default Color Green + 8 + 8 + + + DCBLUE + Default Color Blue + 0 + 8 + + + + + L2BFCR + L2BFCR + Layerx Blending Factors Configuration + Register + 0x120 + 0x20 + read-write + 0x00000607 + + + BF1 + Blending Factor 1 + 8 + 3 + + + BF2 + Blending Factor 2 + 0 + 3 + + + + + L2CFBAR + L2CFBAR + Layerx Color Frame Buffer Address + Register + 0x12C + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start + Address + 0 + 32 + + + + + L2CFBLR + L2CFBLR + Layerx Color Frame Buffer Length + Register + 0x130 + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in + bytes + 16 + 13 + + + CFBLL + Color Frame Buffer Line + Length + 0 + 13 + + + + + L2CFBLNR + L2CFBLNR + Layerx ColorFrame Buffer Line Number + Register + 0x134 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + + + L2CLUTWR + L2CLUTWR + Layerx CLUT Write Register + 0x144 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + RED + Red value + 16 + 8 + + + GREEN + Green value + 8 + 8 + + + BLUE + Blue value + 0 + 8 + + + + + + + DSIHOST + DSIHOST + DSIHOST + 0x50000000 + + 0x0 + 0x800 + registers + + + + DSI_VR + DSI_VR + DSI Host version register + 0x0 + 0x20 + read-only + 0x3133302A + + + VERSION + VERSION + 0 + 32 + + + + + DSI_CR + DSI_CR + DSI Host control register + 0x4 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + + + DSI_CCR + DSI_CCR + DSI Host clock control register + 0x8 + 0x20 + read-write + 0x00000000 + + + TXECKDIV + TXECKDIV + 0 + 8 + + + TOCKDIV + TOCKDIV + 8 + 8 + + + + + DSI_LVCIDR + DSI_LVCIDR + DSI Host LTDC VCID register + 0xC + 0x20 + read-write + 0x00000000 + + + VCID + VCID + 0 + 2 + + + + + DSI_LCOLCR + DSI_LCOLCR + DSI Host LTDC color coding register + 0x10 + 0x20 + read-write + 0x00000000 + + + COLC + COLC + 0 + 4 + + + LPE + LPE + 8 + 1 + + + + + DSI_LPCR + DSI_LPCR + DSI Host LTDC polarity configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DEP + DEP + 0 + 1 + + + VSP + VSP + 1 + 1 + + + HSP + HSP + 2 + 1 + + + + + DSI_LPMCR + DSI_LPMCR + DSI Host low-power mode configuration register + 0x18 + 0x20 + read-write + 0x00000000 + + + VLPSIZE + VLPSIZE + 0 + 8 + + + LPSIZE + LPSIZE + 16 + 8 + + + + + DSI_PCR + DSI_PCR + DSI Host protocol configuration register + 0x2C + 0x20 + read-write + 0x00000000 + + + ETTXE + ETTXE + 0 + 1 + + + ETRXE + ETRXE + 1 + 1 + + + BTAE + BTAE + 2 + 1 + + + ECCRXE + ECCRXE + 3 + 1 + + + CRCRXE + CRCRXE + 4 + 1 + + + + + DSI_GVCIDR + DSI_GVCIDR + DSI Host generic VCID register + 0x30 + 0x20 + read-only + 0x00000000 + + + VCID + VCID + 0 + 2 + + + + + DSI_MCR + DSI_MCR + DSI Host mode configuration register + 0x34 + 0x20 + read-write + 0x00000001 + + + CMDM + CMDM + 0 + 1 + + + + + DSI_VMCR + DSI_VMCR + DSI Host video mode configuration register + 0x38 + 0x20 + read-write + 0x00000000 + + + VMT + VMT + 0 + 2 + + + LPVSAE + LPVSAE + 8 + 1 + + + LPVBPE + LPVBPE + 9 + 1 + + + LPVFPE + LPVFPE + 10 + 1 + + + LPVAE + LPVAE + 11 + 1 + + + LPHBPE + LPHBPE + 12 + 1 + + + LPHFPE + LPHFPE + 13 + 1 + + + FBTAAE + FBTAAE + 14 + 1 + + + LPCE + LPCE + 15 + 1 + + + PGE + PGE + 16 + 1 + + + PGM + PGM + 20 + 1 + + + PGO + PGO + 24 + 1 + + + + + DSI_VPCR + DSI_VPCR + DSI Host video packet configuration register + 0x3C + 0x20 + read-write + 0x00000000 + + + VPSIZE + VPSIZE + 0 + 14 + + + + + DSI_VCCR + DSI_VCCR + DSI Host video chunks configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + NUMC + NUMC + 0 + 13 + + + + + DSI_VNPCR + DSI_VNPCR + DSI Host video null packet configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + NPSIZE + NPSIZE + 0 + 13 + + + + + DSI_VHSACR + DSI_VHSACR + DSI Host video HSA configuration register + 0x48 + 0x20 + read-write + 0x00000000 + + + HSA + HSA + 0 + 12 + + + + + DSI_VHBPCR + DSI_VHBPCR + DSI Host video HBP configuration register + 0x4C + 0x20 + read-write + 0x00000000 + + + HBP + HBP + 0 + 12 + + + + + DSI_VLCR + DSI_VLCR + DSI Host video line configuration register + 0x50 + 0x20 + read-write + 0x00000000 + + + HLINE + HLINE + 0 + 15 + + + + + DSI_VVSACR + DSI_VVSACR + DSI Host video VSA configuration register + 0x54 + 0x20 + read-write + 0x00000000 + + + VSA + VSA + 0 + 10 + + + + + DSI_VVBPCR + DSI_VVBPCR + DSI Host video VBP configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + VBP + VBP + 0 + 10 + + + + + DSI_VVFPCR + DSI_VVFPCR + DSI Host video VFP configuration register + 0x5C + 0x20 + read-write + 0x00000000 + + + VFP + VFP + 0 + 10 + + + + + DSI_VVACR + DSI_VVACR + DSI Host video VA configuration register + 0x60 + 0x20 + read-write + 0x00000000 + + + VA + VA + 0 + 14 + + + + + DSI_LCCR + DSI_LCCR + DSI Host LTDC command configuration register + 0x64 + 0x20 + read-write + 0x00000000 + + + CMDSIZE + CMDSIZE + 0 + 16 + + + + + DSI_CMCR + DSI_CMCR + DSI Host command mode configuration register + 0x68 + 0x20 + read-write + 0x00000000 + + + TEARE + TEARE + 0 + 1 + + + ARE + ARE + 1 + 1 + + + GSW0TX + GSW0TX + 8 + 1 + + + GSW1TX + GSW1TX + 9 + 1 + + + GSW2TX + GSW2TX + 10 + 1 + + + GSR0TX + GSR0TX + 11 + 1 + + + GSR1TX + GSR1TX + 12 + 1 + + + GSR2TX + GSR2TX + 13 + 1 + + + GLWTX + GLWTX + 14 + 1 + + + DSW0TX + DSW0TX + 16 + 1 + + + DSW1TX + DSW1TX + 17 + 1 + + + DSR0TX + DSR0TX + 18 + 1 + + + DLWTX + DLWTX + 19 + 1 + + + MRDPS + MRDPS + 24 + 1 + + + + + DSI_GHCR + DSI_GHCR + DSI Host generic header configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + DT + 0 + 6 + + + VCID + VCID + 6 + 2 + + + WCLSB + WCLSB + 8 + 8 + + + WCMSB + WCMSB + 16 + 8 + + + + + DSI_GPDR + DSI_GPDR + DSI Host generic payload data register + 0x70 + 0x20 + read-write + 0x00000000 + + + DATA1 + DATA1 + 0 + 8 + + + DATA2 + DATA2 + 8 + 8 + + + DATA3 + DATA3 + 16 + 8 + + + DATA4 + DATA4 + 24 + 8 + + + + + DSI_GPSR + DSI_GPSR + DSI Host generic packet status register + 0x74 + 0x20 + read-only + 0x00000015 + + + CMDFE + CMDFE + 0 + 1 + + + CMDFF + CMDFF + 1 + 1 + + + PWRFE + PWRFE + 2 + 1 + + + PWRFF + PWRFF + 3 + 1 + + + PRDFE + PRDFE + 4 + 1 + + + PRDFF + PRDFF + 5 + 1 + + + RCB + RCB + 6 + 1 + + + + + DSI_TCCR0 + DSI_TCCR0 + DSI Host timeout counter configuration register 0 + 0x78 + 0x20 + read-write + 0x00000000 + + + LPRX_TOCNT + LPRX_TOCNT + 0 + 16 + + + HSTX_TOCNT + HSTX_TOCNT + 16 + 16 + + + + + DSI_TCCR1 + DSI_TCCR1 + DSI Host timeout counter configuration register 1 + 0x7C + 0x20 + read-write + 0x00000000 + + + HSRD_TOCNT + HSRD_TOCNT + 0 + 16 + + + + + DSI_TCCR2 + DSI_TCCR2 + DSI Host timeout counter configuration register 2 + 0x80 + 0x20 + read-write + 0x00000000 + + + LPRD_TOCNT + LPRD_TOCNT + 0 + 16 + + + + + DSI_TCCR3 + DSI_TCCR3 + DSI Host timeout counter configuration register 3 + 0x84 + 0x20 + read-write + 0x00000000 + + + HSWR_TOCNT + HSWR_TOCNT + 0 + 16 + + + PM + PM + 24 + 1 + + + + + DSI_TCCR4 + DSI_TCCR4 + DSI Host timeout counter configuration register 4 + 0x88 + 0x20 + read-write + 0x00000000 + + + LPWR_TOCNT + LPWR_TOCNT + 0 + 16 + + + + + DSI_TCCR5 + DSI_TCCR5 + DSI Host timeout counter configuration register 5 + 0x8C + 0x20 + read-write + 0x00000000 + + + BTA_TOCNT + BTA_TOCNT + 0 + 16 + + + + + DSI_CLCR + DSI_CLCR + DSI Host clock lane configuration register + 0x94 + 0x20 + read-write + 0x00000000 + + + DPCC + DPCC + 0 + 1 + + + ACR + ACR + 1 + 1 + + + + + DSI_CLTCR + DSI_CLTCR + DSI Host clock lane timer configuration register + 0x98 + 0x20 + read-write + 0x00000000 + + + LP2HS_TIME + LP2HS_TIME + 0 + 10 + + + HS2LP_TIME + HS2LP_TIME + 16 + 10 + + + + + DSI_DLTCR + DSI_DLTCR + DSI Host data lane timer configuration register + 0x9C + 0x20 + read-write + 0x00000000 + + + MRD_TIME + Maximum read time + 0 + 15 + + + LP2HS_TIME + LP2HS_TIME + 16 + 8 + + + HS2LP_TIME + HS2LP_TIME + 24 + 8 + + + + + DSI_PCTLR + DSI_PCTLR + DSI Host PHY control register + 0xA0 + 0x20 + read-write + 0x00000000 + + + DEN + DEN + 1 + 1 + + + CKE + CKE + 2 + 1 + + + + + DSI_PCONFR + DSI_PCONFR + DSI Host PHY configuration register + 0xA4 + 0x20 + read-write + 0x00000001 + + + NL + NL + 0 + 2 + + + SW_TIME + SW_TIME + 8 + 8 + + + + + DSI_PUCR + DSI_PUCR + DSI Host PHY ULPS control register + 0xA8 + 0x20 + read-write + 0x00000000 + + + URCL + URCL + 0 + 1 + + + UECL + UECL + 1 + 1 + + + URDL + URDL + 2 + 1 + + + UEDL + UEDL + 3 + 1 + + + + + DSI_PTTCR + DSI_PTTCR + DSI Host PHY TX triggers configuration register + 0xAC + 0x20 + read-write + 0x00000000 + + + TX_TRIG + TX_TRIG + 0 + 4 + + + + + DSI_PSR + DSI_PSR + DSI Host PHY status register + 0xB0 + 0x20 + read-only + 0x00001528 + + + PD + PD + 1 + 1 + + + PSSC + PSSC + 2 + 1 + + + UANC + UANC + 3 + 1 + + + PSS0 + PSS0 + 4 + 1 + + + UAN0 + UAN0 + 5 + 1 + + + RUE0 + RUE0 + 6 + 1 + + + PSS1 + PSS1 + 7 + 1 + + + UAN1 + UAN1 + 8 + 1 + + + + + DSI_ISR0 + DSI_ISR0 + DSI Host interrupt and status register 0 + 0xBC + 0x20 + read-only + 0x00000000 + + + AE0 + AE0 + 0 + 1 + + + AE1 + AE1 + 1 + 1 + + + AE2 + AE2 + 2 + 1 + + + AE3 + AE3 + 3 + 1 + + + AE4 + AE4 + 4 + 1 + + + AE5 + AE5 + 5 + 1 + + + AE6 + AE6 + 6 + 1 + + + AE7 + AE7 + 7 + 1 + + + AE8 + AE8 + 8 + 1 + + + AE9 + AE9 + 9 + 1 + + + AE10 + AE10 + 10 + 1 + + + AE11 + AE11 + 11 + 1 + + + AE12 + AE12 + 12 + 1 + + + AE13 + AE13 + 13 + 1 + + + AE14 + AE14 + 14 + 1 + + + AE15 + AE15 + 15 + 1 + + + PE0 + PE0 + 16 + 1 + + + PE1 + PE1 + 17 + 1 + + + PE2 + PE2 + 18 + 1 + + + PE3 + PE3 + 19 + 1 + + + PE4 + PE4 + 20 + 1 + + + + + DSI_ISR1 + DSI_ISR1 + DSI Host interrupt and status register 1 + 0xC0 + 0x20 + read-only + 0x00000000 + + + TOHSTX + TOHSTX + 0 + 1 + + + TOLPRX + TOLPRX + 1 + 1 + + + ECCSE + ECCSE + 2 + 1 + + + ECCME + ECCME + 3 + 1 + + + CRCE + CRCE + 4 + 1 + + + PSE + PSE + 5 + 1 + + + EOTPE + EOTPE + 6 + 1 + + + LPWRE + LPWRE + 7 + 1 + + + GCWRE + GCWRE + 8 + 1 + + + GPWRE + GPWRE + 9 + 1 + + + GPTXE + GPTXE + 10 + 1 + + + GPRDE + GPRDE + 11 + 1 + + + GPRXE + GPRXE + 12 + 1 + + + + + DSI_IER0 + DSI_IER0 + DSI Host interrupt enable register 0 + 0xC4 + 0x20 + read-write + 0x00000000 + + + AE0IE + AE0IE + 0 + 1 + + + AE1IE + AE1IE + 1 + 1 + + + AE2IE + AE2IE + 2 + 1 + + + AE3IE + AE3IE + 3 + 1 + + + AE4IE + AE4IE + 4 + 1 + + + AE5IE + AE5IE + 5 + 1 + + + AE6IE + AE6IE + 6 + 1 + + + AE7IE + AE7IE + 7 + 1 + + + AE8IE + AE8IE + 8 + 1 + + + AE9IE + AE9IE + 9 + 1 + + + AE10IE + AE10IE + 10 + 1 + + + AE11IE + AE11IE + 11 + 1 + + + AE12IE + AE12IE + 12 + 1 + + + AE13IE + AE13IE + 13 + 1 + + + AE14IE + AE14IE + 14 + 1 + + + AE15IE + AE15IE + 15 + 1 + + + PE0IE + PE0IE + 16 + 1 + + + PE1IE + PE1IE + 17 + 1 + + + PE2IE + PE2IE + 18 + 1 + + + PE3IE + PE3IE + 19 + 1 + + + PE4IE + PE4IE + 20 + 1 + + + + + DSI_IER1 + DSI_IER1 + DSI Host interrupt enable register 1 + 0xC8 + 0x20 + read-write + 0x00000000 + + + TOHSTXIE + TOHSTXIE + 0 + 1 + + + TOLPRXIE + TOLPRXIE + 1 + 1 + + + ECCSEIE + ECCSEIE + 2 + 1 + + + ECCMEIE + ECCMEIE + 3 + 1 + + + CRCEIE + CRCEIE + 4 + 1 + + + PSEIE + PSEIE + 5 + 1 + + + EOTPEIE + EOTPEIE + 6 + 1 + + + LPWREIE + LPWREIE + 7 + 1 + + + GCWREIE + GCWREIE + 8 + 1 + + + GPWREIE + GPWREIE + 9 + 1 + + + GPTXEIE + GPTXEIE + 10 + 1 + + + GPRDEIE + GPRDEIE + 11 + 1 + + + GPRXEIE + GPRXEIE + 12 + 1 + + + + + DSI_FIR0 + DSI_FIR0 + DSI Host force interrupt register 0 + 0xD8 + 0x20 + write-only + 0x00000000 + + + FAE0 + FAE0 + 0 + 1 + + + FAE1 + FAE1 + 1 + 1 + + + FAE2 + FAE2 + 2 + 1 + + + FAE3 + FAE3 + 3 + 1 + + + FAE4 + FAE4 + 4 + 1 + + + FAE5 + FAE5 + 5 + 1 + + + FAE6 + FAE6 + 6 + 1 + + + FAE7 + FAE7 + 7 + 1 + + + FAE8 + FAE8 + 8 + 1 + + + FAE9 + FAE9 + 9 + 1 + + + FAE10 + FAE10 + 10 + 1 + + + FAE11 + FAE11 + 11 + 1 + + + FAE12 + FAE12 + 12 + 1 + + + FAE13 + FAE13 + 13 + 1 + + + FAE14 + FAE14 + 14 + 1 + + + FAE15 + FAE15 + 15 + 1 + + + FPE0 + FPE0 + 16 + 1 + + + FPE1 + FPE1 + 17 + 1 + + + FPE2 + FPE2 + 18 + 1 + + + FPE3 + FPE3 + 19 + 1 + + + FPE4 + FPE4 + 20 + 1 + + + + + DSI_FIR1 + DSI_FIR1 + DSI Host force interrupt register 1 + 0xDC + 0x20 + write-only + 0x00000000 + + + FTOHSTX + FTOHSTX + 0 + 1 + + + FTOLPRX + FTOLPRX + 1 + 1 + + + FECCSE + FECCSE + 2 + 1 + + + FECCME + FECCME + 3 + 1 + + + FCRCE + FCRCE + 4 + 1 + + + FPSE + FPSE + 5 + 1 + + + FEOTPE + FEOTPE + 6 + 1 + + + FLPWRE + FLPWRE + 7 + 1 + + + FGCWRE + FGCWRE + 8 + 1 + + + FGPWRE + FGPWRE + 9 + 1 + + + FGPTXE + FGPTXE + 10 + 1 + + + FGPRDE + FGPRDE + 11 + 1 + + + FGPRXE + FGPRXE + 12 + 1 + + + + + DSI_VSCR + DSI_VSCR + DSI Host video shadow control register + 0x100 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + UR + UR + 8 + 1 + + + + + DSI_LCVCIDR + DSI_LCVCIDR + DSI Host LTDC current VCID register + 0x10C + 0x20 + read-write + 0x00000000 + + + VCID + VCID + 0 + 2 + + + + + DSI_LCCCR + DSI_LCCCR + DSI Host LTDC current color coding register + 0x110 + 0x20 + read-only + 0x00000000 + + + COLC + COLC + 0 + 4 + + + LPE + LPE + 8 + 1 + + + + + DSI_LPMCCR + DSI_LPMCCR + DSI Host low-power mode current configuration register + 0x118 + 0x20 + read-only + 0x00000000 + + + VLPSIZE + VLPSIZE + 0 + 8 + + + LPSIZE + LPSIZE + 16 + 8 + + + + + DSI_VMCCR + DSI_VMCCR + DSI Host video mode current configuration register + 0x138 + 0x20 + read-only + 0x00000000 + + + VMT + VMT + 0 + 2 + + + LPVSAE + LPVSAE + 2 + 1 + + + LPVBPE + LPVBPE + 3 + 1 + + + LPVFPE + LPVFPE + 4 + 1 + + + LPVAE + LPVAE + 5 + 1 + + + LPHBPE + LPHBPE + 6 + 1 + + + LPHFE + LPHFE + 7 + 1 + + + FBTAAE + FBTAAE + 8 + 1 + + + LPCE + LPCE + 9 + 1 + + + + + DSI_VPCCR + DSI_VPCCR + DSI Host video packet current configuration register + 0x13C + 0x20 + read-only + 0x00000000 + + + VPSIZE + VPSIZE + 0 + 14 + + + + + DSI_VCCCR + DSI_VCCCR + DSI Host video chunks current configuration register + 0x140 + 0x20 + read-only + 0x00000000 + + + NUMC + NUMC + 0 + 13 + + + + + DSI_VNPCCR + DSI_VNPCCR + DSI Host video null packet current configuration register + 0x144 + 0x20 + read-only + 0x00000000 + + + NPSIZE + NPSIZE + 0 + 13 + + + + + DSI_VHSACCR + DSI_VHSACCR + DSI Host video HSA current configuration register + 0x148 + 0x20 + read-only + 0x00000000 + + + HSA + HSA + 0 + 12 + + + + + DSI_VHBPCCR + DSI_VHBPCCR + DSI Host video HBP current configuration register + 0x14C + 0x20 + read-only + 0x00000000 + + + HBP + HBP + 0 + 12 + + + + + DSI_VLCCR + DSI_VLCCR + DSI Host video line current configuration register + 0x150 + 0x20 + read-only + 0x00000000 + + + HLINE + HLINE + 0 + 15 + + + + + DSI_VVSACCR + DSI_VVSACCR + DSI Host video VSA current configuration register + 0x154 + 0x20 + read-only + 0x00000000 + + + VSA + VSA + 0 + 10 + + + + + DSI_VVBPCCR + DSI_VVBPCCR + DSI Host video VBP current configuration register + 0x158 + 0x20 + read-only + 0x00000000 + + + VBP + VBP + 0 + 10 + + + + + DSI_VVFPCCR + DSI_VVFPCCR + DSI Host video VFP current configuration register + 0x15C + 0x20 + read-only + 0x00000000 + + + VFP + VFP + 0 + 10 + + + + + DSI_VVACCR + DSI_VVACCR + DSI Host video VA current configuration register + 0x160 + 0x20 + read-only + 0x00000000 + + + VA + VA + 0 + 14 + + + + + DSI_WCFGR + DSI_WCFGR + DSI wrapper configuration register + 0x400 + 0x20 + read-write + 0x00000000 + + + DSIM + DSIM + 0 + 1 + + + COLMUX + COLMUX + 1 + 3 + + + TESRC + TESRC + 4 + 1 + + + TEPOL + TEPOL + 5 + 1 + + + AR + AR + 6 + 1 + + + VSPOL + VSPOL + 7 + 1 + + + + + DSI_WCR + DSI_WCR + DSI wrapper control register + 0x404 + 0x20 + read-write + 0x00000000 + + + COLM + COLM + 0 + 1 + + + SHTDN + SHTDN + 1 + 1 + + + LTDCEN + LTDCEN + 2 + 1 + + + DSIEN + DSIEN + 3 + 1 + + + + + DSI_WIER + DSI_WIER + DSI wrapper interrupt enable register + 0x408 + 0x20 + read-write + 0x00000000 + + + TEIE + TEIE + 0 + 1 + + + ERIE + ERIE + 1 + 1 + + + PLLLIE + PLLLIE + 9 + 1 + + + PLLUIE + PLLUIE + 10 + 1 + + + RRIE + RRIE + 13 + 1 + + + + + DSI_WISR + DSI_WISR + DSI wrapper interrupt and status register + 0x40C + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + ERIF + ERIF + 1 + 1 + + + BUSY + BUSY + 2 + 1 + + + PLLLS + PLLLS + 8 + 1 + + + PLLLIF + PLLLIF + 9 + 1 + + + PLLUIF + PLLUIF + 10 + 1 + + + RRS + RRS + 12 + 1 + + + RRIF + RRIF + 13 + 1 + + + + + DSI_WIFCR + DSI_WIFCR + DSI wrapper interrupt flag clear register + 0x410 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CERIF + CERIF + 1 + 1 + + + CPLLLIF + CPLLLIF + 9 + 1 + + + CPLLUIF + CPLLUIF + 10 + 1 + + + CRRIF + CRRIF + 13 + 1 + + + + + DSI_WPCR0 + DSI_WPCR0 + DSI wrapper PHY configuration register 0 + 0x418 + 0x20 + read-write + 0x00000000 + + + UIX4 + UIX4 + 0 + 6 + + + SWCL + SWCL + 6 + 1 + + + SWDL0 + SWDL0 + 7 + 1 + + + SWDL1 + SWDL1 + 8 + 1 + + + HSICL + HSICL + 9 + 1 + + + HSIDL0 + HSIDL0 + 10 + 1 + + + HSIDL1 + HSIDL1 + 11 + 1 + + + FTXSMCL + FTXSMCL + 12 + 1 + + + FTXSMDL + FTXSMDL + 13 + 1 + + + CDOFFDL + CDOFFDL + 14 + 1 + + + TDDL + TDDL + 16 + 1 + + + PDEN + Pull-down enable + 18 + 1 + + + TCLKPREPEN + Custom time for tCLK-PREPARE enable + 19 + 1 + + + TCLKZEROEN + Custom time for tCLK-ZERO enable + 20 + 1 + + + THSPREPEN + Custom time for tHS-PREPARE enable + 21 + 1 + + + THSTRAILEN + Custom time for tHS-TRAIL enable + 22 + 1 + + + THSZEROEN + Custom time for tHS-ZERO enable + 23 + 1 + + + TLPXDEN + Custom time for tLPX for data lanes enable + 24 + 1 + + + THSEXITEN + Custom time for tHS-EXIT enable + 25 + 1 + + + TLPXCEN + Custom time for tLPX for clock lane enable + 26 + 1 + + + TCLKPOSTEN + Custom time for tCLK-POST enable + 27 + 1 + + + + + DSI_WPCR1 + DSI_WPCR1 + This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). + 0x41C + 0x20 + read-write + 0x00000000 + + + HSTXDCL + High-speed transmission delay on clock lane + 0 + 2 + + + HSTXDDL + High-speed transmission delay on data lanes + 2 + 2 + + + LPSRCCL + Low-power transmission slew-rate compensation on clock lane + 6 + 2 + + + LPSRCDL + Low-power transmission slew-rate compensation on data lanes + 8 + 2 + + + SDDC + SDD control + 12 + 1 + + + HSTXSRCCL + High-speed transmission slew-rate control on clock lane + 16 + 2 + + + HSTXSRCDL + High-speed transmission slew-rate control on data lanes + 18 + 2 + + + FLPRXLPM + Forces LP receiver in low-power mode + 22 + 1 + + + LPRXFT + Low-power RX low-pass filtering tuning + 25 + 2 + + + + + DSI_WPCR2 + DSI_WPCR2 + DSI wrapper PHY configuration register 2 + 0x420 + 0x20 + read-write + 0x00000000 + + + TCLKPREP + TCLKPREP + 0 + 8 + + + TCLKZERO + TCLKZERO + 8 + 8 + + + THSPREP + THSPREP + 16 + 8 + + + THSTRAIL + THSTRAIL + 24 + 8 + + + + + DSI_WPCR3 + DSI_WPCR3 + DSI wrapper PHY configuration register 3 + 0x424 + 0x20 + read-write + 0x00000000 + + + THSZERO + THSZERO + 0 + 8 + + + TLPXD + TLPXD + 8 + 8 + + + THSEXIT + THSEXIT + 16 + 8 + + + TLPXC + TLPXC + 24 + 8 + + + + + DSI_WPCR4 + DSI_WPCR4 + DSI wrapper PHY configuration register 4 + 0x428 + 0x20 + read-write + 0x00000000 + + + TCLKPOST + TCLKPOST + 0 + 8 + + + + + DSI_WRPCR + DSI_WRPCR + DSI wrapper regulator and PLL control register + 0x430 + 0x20 + read-write + 0x00000000 + + + PLLEN + PLLEN + 0 + 1 + + + NDIV + NDIV + 2 + 7 + + + IDF + IDF + 11 + 4 + + + ODF + ODF + 16 + 2 + + + REGEN + REGEN + 24 + 1 + + + + + + + SPDIFRX + Receiver Interface + SPDIFRX + 0x40004000 + + 0x0 + 0x400 + registers + + + SPDIF + SPDIFRX global interrupt + 97 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x00000000 + + + SPDIFRXEN + Peripheral Block Enable + 0 + 2 + + + RXDMAEN + Receiver DMA ENable for data + flow + 2 + 1 + + + RXSTEO + STerEO Mode + 3 + 1 + + + DRFMT + RX Data format + 4 + 2 + + + PMSK + Mask Parity error bit + 6 + 1 + + + VMSK + Mask of Validity bit + 7 + 1 + + + CUMSK + Mask of channel status and user + bits + 8 + 1 + + + PTMSK + Mask of Preamble Type bits + 9 + 1 + + + CBDMAEN + Control Buffer DMA ENable for control + flow + 10 + 1 + + + CHSEL + Channel Selection + 11 + 1 + + + NBTR + Maximum allowed re-tries during + synchronization phase + 12 + 2 + + + WFA + Wait For Activity + 14 + 1 + + + INSEL + input selection + 16 + 3 + + + CKSEN + Symbol Clock Enable + 20 + 1 + + + CKSBKPEN + Backup Symbol Clock Enable + 21 + 1 + + + + + IMR + IMR + Interrupt mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + RXNEIE + RXNE interrupt enable + 0 + 1 + + + CSRNEIE + Control Buffer Ready Interrupt + Enable + 1 + 1 + + + PERRIE + Parity error interrupt + enable + 2 + 1 + + + OVRIE + Overrun error Interrupt + Enable + 3 + 1 + + + SBLKIE + Synchronization Block Detected Interrupt + Enable + 4 + 1 + + + SYNCDIE + Synchronization Done + 5 + 1 + + + IFEIE + Serial Interface Error Interrupt + Enable + 6 + 1 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-only + 0x00000000 + + + RXNE + Read data register not + empty + 0 + 1 + + + CSRNE + Control Buffer register is not + empty + 1 + 1 + + + PERR + Parity error + 2 + 1 + + + OVR + Overrun error + 3 + 1 + + + SBD + Synchronization Block + Detected + 4 + 1 + + + SYNCD + Synchronization Done + 5 + 1 + + + FERR + Framing error + 6 + 1 + + + SERR + Synchronization error + 7 + 1 + + + TERR + Time-out error + 8 + 1 + + + WIDTH5 + Duration of 5 symbols counted with + SPDIF_CLK + 16 + 15 + + + + + IFCR + IFCR + Interrupt Flag Clear register + 0xC + 0x20 + write-only + 0x00000000 + + + PERRCF + Clears the Parity error + flag + 2 + 1 + + + OVRCF + Clears the Overrun error + flag + 3 + 1 + + + SBDCF + Clears the Synchronization Block + Detected flag + 4 + 1 + + + SYNCDCF + Clears the Synchronization Done + flag + 5 + 1 + + + + + DR_00 + DR_00 + Data input register + 0x10 + 0x20 + read-only + 0x00000000 + + + DR + Parity Error bit + 0 + 24 + + + PE + Parity Error bit + 24 + 1 + + + V + Validity bit + 25 + 1 + + + U + User bit + 26 + 1 + + + C + Channel Status bit + 27 + 1 + + + PT + Preamble Type + 28 + 2 + + + + + CSR + CSR + Channel Status register + 0x14 + 0x20 + read-only + 0x00000000 + + + USR + User data information + 0 + 16 + + + CS + Channel A status + information + 16 + 8 + + + SOB + Start Of Block + 24 + 1 + + + + + DIR + DIR + Debug Information register + 0x18 + 0x20 + read-only + 0x00000000 + + + THI + Threshold HIGH + 0 + 13 + + + TLO + Threshold LOW + 16 + 13 + + + + + VERR + VERR + SPDIFRX version register + 0x3F4 + 0x20 + read-only + 0x00000012 + + + MINREV + Minor revision + 0 + 4 + + + MAJREV + Major revision + 4 + 4 + + + + + IDR + IDR + SPDIFRX identification + register + 0x3F8 + 0x20 + read-only + 0x00130041 + + + ID + SPDIFRX identifier + 0 + 32 + + + + + SIDR + SIDR + SPDIFRX size identification + register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + Size identification + 0 + 32 + + + + + DR_01 + DR_01 + Data input register + DR_00 + 0x10 + 0x20 + read-only + 0x00000000 + + + PE + Parity Error bit + 0 + 1 + + + V + Validity bit + 1 + 1 + + + U + User bit + 2 + 1 + + + C + Channel Status bit + 3 + 1 + + + PT + Preamble Type + 4 + 2 + + + DR + Data value + 8 + 24 + + + + + DR_10 + DR_10 + Data input register + DR_00 + 0x10 + 0x20 + read-only + 0x00000000 + + + DRNL1 + Data value + 0 + 16 + + + DRNL2 + Data value + 16 + 16 + + + + + + + ADC3 + Analog to Digital Converter + ADC + 0x58026000 + + 0x0 + 0xD1 + registers + + + ADC3 + ADC3 global interrupt + 127 + + + + ISR + ISR + ADC interrupt and status + register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + ADC group injected contexts queue + overflow flag + 10 + 1 + + + AWD3 + ADC analog watchdog 3 flag + 9 + 1 + + + AWD2 + ADC analog watchdog 2 flag + 8 + 1 + + + AWD1 + ADC analog watchdog 1 flag + 7 + 1 + + + JEOS + ADC group injected end of sequence + conversions flag + 6 + 1 + + + JEOC + ADC group injected end of unitary + conversion flag + 5 + 1 + + + OVR + ADC group regular overrun + flag + 4 + 1 + + + EOS + ADC group regular end of sequence + conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary + conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling + flag + 1 + 1 + + + ADRDY + ADC ready flag + 0 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + ADC group injected contexts queue + overflow interrupt + 10 + 1 + + + AWD3IE + ADC analog watchdog 3 + interrupt + 9 + 1 + + + AWD2IE + ADC analog watchdog 2 + interrupt + 8 + 1 + + + AWD1IE + ADC analog watchdog 1 + interrupt + 7 + 1 + + + JEOSIE + ADC group injected end of sequence + conversions interrupt + 6 + 1 + + + JEOCIE + ADC group injected end of unitary + conversion interrupt + 5 + 1 + + + OVRIE + ADC group regular overrun + interrupt + 4 + 1 + + + EOSIE + ADC group regular end of sequence + conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary + conversion interrupt + 2 + 1 + + + EOSMPIE + ADC group regular end of sampling + interrupt + 1 + 1 + + + ADRDYIE + ADC ready interrupt + 0 + 1 + + + + + CR + CR + ADC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC calibration + 31 + 1 + + + ADCALDIF + ADC differential mode for + calibration + 30 + 1 + + + DEEPPWD + ADC deep power down enable + 29 + 1 + + + ADVREGEN + ADC voltage regulator + enable + 28 + 1 + + + LINCALRDYW6 + Linearity calibration ready Word + 6 + 27 + 1 + + + LINCALRDYW5 + Linearity calibration ready Word + 5 + 26 + 1 + + + LINCALRDYW4 + Linearity calibration ready Word + 4 + 25 + 1 + + + LINCALRDYW3 + Linearity calibration ready Word + 3 + 24 + 1 + + + LINCALRDYW2 + Linearity calibration ready Word + 2 + 23 + 1 + + + LINCALRDYW1 + Linearity calibration ready Word + 1 + 22 + 1 + + + ADCALLIN + Linearity calibration + 16 + 1 + + + BOOST + Boost mode control + 8 + 2 + + + JADSTP + ADC group injected conversion + stop + 5 + 1 + + + ADSTP + ADC group regular conversion + stop + 4 + 1 + + + JADSTART + ADC group injected conversion + start + 3 + 1 + + + ADSTART + ADC group regular conversion + start + 2 + 1 + + + ADDIS + ADC disable + 1 + 1 + + + ADEN + ADC enable + 0 + 1 + + + + + CFGR + CFGR + ADC configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + JQDIS + ADC group injected contexts queue + disable + 31 + 1 + + + AWDCH1CH + ADC analog watchdog 1 monitored channel + selection + 26 + 5 + + + JAUTO + ADC group injected automatic trigger + mode + 25 + 1 + + + JAWD1EN + ADC analog watchdog 1 enable on scope + ADC group injected + 24 + 1 + + + AWD1EN + ADC analog watchdog 1 enable on scope + ADC group regular + 23 + 1 + + + AWD1SGL + ADC analog watchdog 1 monitoring a + single channel or all channels + 22 + 1 + + + JQM + ADC group injected contexts queue + mode + 21 + 1 + + + JDISCEN + ADC group injected sequencer + discontinuous mode + 20 + 1 + + + DISCNUM + ADC group regular sequencer + discontinuous number of ranks + 17 + 3 + + + DISCEN + ADC group regular sequencer + discontinuous mode + 16 + 1 + + + AUTDLY + ADC low power auto wait + 14 + 1 + + + CONT + ADC group regular continuous conversion + mode + 13 + 1 + + + OVRMOD + ADC group regular overrun + configuration + 12 + 1 + + + EXTEN + ADC group regular external trigger + polarity + 10 + 2 + + + EXTSEL + ADC group regular external trigger + source + 5 + 5 + + + RES + ADC data resolution + 2 + 3 + + + DMNGT + ADC DMA transfer enable + 0 + 2 + + + + + CFGR2 + CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + ROVSE + ADC oversampler enable on scope ADC + group regular + 0 + 1 + + + JOVSE + ADC oversampler enable on scope ADC + group injected + 1 + 1 + + + OVSS + ADC oversampling shift + 5 + 4 + + + TROVS + ADC oversampling discontinuous mode + (triggered mode) for ADC group regular + 9 + 1 + + + ROVSM + Regular Oversampling mode + 10 + 1 + + + RSHIFT1 + Right-shift data after Offset 1 + correction + 11 + 1 + + + RSHIFT2 + Right-shift data after Offset 2 + correction + 12 + 1 + + + RSHIFT3 + Right-shift data after Offset 3 + correction + 13 + 1 + + + RSHIFT4 + Right-shift data after Offset 4 + correction + 14 + 1 + + + OSR + Oversampling ratio + 16 + 10 + + + LSHIFT + Left shift factor + 28 + 4 + + + + + SMPR1 + SMPR1 + ADC sampling time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + ADC channel 9 sampling time + selection + 27 + 3 + + + SMP8 + ADC channel 8 sampling time + selection + 24 + 3 + + + SMP7 + ADC channel 7 sampling time + selection + 21 + 3 + + + SMP6 + ADC channel 6 sampling time + selection + 18 + 3 + + + SMP5 + ADC channel 5 sampling time + selection + 15 + 3 + + + SMP4 + ADC channel 4 sampling time + selection + 12 + 3 + + + SMP3 + ADC channel 3 sampling time + selection + 9 + 3 + + + SMP2 + ADC channel 2 sampling time + selection + 6 + 3 + + + SMP1 + ADC channel 1 sampling time + selection + 3 + 3 + + + + + SMPR2 + SMPR2 + ADC sampling time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP19 + ADC channel 18 sampling time + selection + 27 + 3 + + + SMP18 + ADC channel 18 sampling time + selection + 24 + 3 + + + SMP17 + ADC channel 17 sampling time + selection + 21 + 3 + + + SMP16 + ADC channel 16 sampling time + selection + 18 + 3 + + + SMP15 + ADC channel 15 sampling time + selection + 15 + 3 + + + SMP14 + ADC channel 14 sampling time + selection + 12 + 3 + + + SMP13 + ADC channel 13 sampling time + selection + 9 + 3 + + + SMP12 + ADC channel 12 sampling time + selection + 6 + 3 + + + SMP11 + ADC channel 11 sampling time + selection + 3 + 3 + + + SMP10 + ADC channel 10 sampling time + selection + 0 + 3 + + + + + LTR1 + LTR1 + ADC analog watchdog 1 threshold + register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + LTR1 + ADC analog watchdog 1 threshold + low + 0 + 26 + + + + + LHTR1 + LHTR1 + ADC analog watchdog 2 threshold + register + 0x24 + 0x20 + read-write + 0x0FFF0000 + + + LHTR1 + ADC analog watchdog 2 threshold + low + 0 + 26 + + + + + SQR1 + SQR1 + ADC group regular sequencer ranks register + 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + ADC group regular sequencer rank + 4 + 24 + 5 + + + SQ3 + ADC group regular sequencer rank + 3 + 18 + 5 + + + SQ2 + ADC group regular sequencer rank + 2 + 12 + 5 + + + SQ1 + ADC group regular sequencer rank + 1 + 6 + 5 + + + L3 + L3 + 0 + 4 + + + + + SQR2 + SQR2 + ADC group regular sequencer ranks register + 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + ADC group regular sequencer rank + 9 + 24 + 5 + + + SQ8 + ADC group regular sequencer rank + 8 + 18 + 5 + + + SQ7 + ADC group regular sequencer rank + 7 + 12 + 5 + + + SQ6 + ADC group regular sequencer rank + 6 + 6 + 5 + + + SQ5 + ADC group regular sequencer rank + 5 + 0 + 5 + + + + + SQR3 + SQR3 + ADC group regular sequencer ranks register + 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + ADC group regular sequencer rank + 14 + 24 + 5 + + + SQ13 + ADC group regular sequencer rank + 13 + 18 + 5 + + + SQ12 + ADC group regular sequencer rank + 12 + 12 + 5 + + + SQ11 + ADC group regular sequencer rank + 11 + 6 + 5 + + + SQ10 + ADC group regular sequencer rank + 10 + 0 + 5 + + + + + SQR4 + SQR4 + ADC group regular sequencer ranks register + 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + ADC group regular sequencer rank + 16 + 6 + 5 + + + SQ15 + ADC group regular sequencer rank + 15 + 0 + 5 + + + + + DR + DR + ADC group regular conversion data + register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + ADC group regular conversion + data + 0 + 16 + + + + + JSQR + JSQR + ADC group injected sequencer + register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + ADC group injected sequencer rank + 4 + 27 + 5 + + + JSQ3 + ADC group injected sequencer rank + 3 + 21 + 5 + + + JSQ2 + ADC group injected sequencer rank + 2 + 15 + 5 + + + JSQ1 + ADC group injected sequencer rank + 1 + 9 + 5 + + + JEXTEN + ADC group injected external trigger + polarity + 7 + 2 + + + JEXTSEL + ADC group injected external trigger + source + 2 + 5 + + + JL + ADC group injected sequencer scan + length + 0 + 2 + + + + + OFR1 + OFR1 + ADC offset number 1 register + 0x60 + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + OFR2 + OFR2 + ADC offset number 2 register + 0x64 + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + OFR3 + OFR3 + ADC offset number 3 register + 0x68 + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + OFR4 + OFR4 + ADC offset number 4 register + 0x6C + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + JDR1 + JDR1 + ADC group injected sequencer rank 1 + register + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + ADC group injected sequencer rank 1 + conversion data + 0 + 32 + + + + + JDR2 + JDR2 + ADC group injected sequencer rank 2 + register + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + ADC group injected sequencer rank 2 + conversion data + 0 + 32 + + + + + JDR3 + JDR3 + ADC group injected sequencer rank 3 + register + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + ADC group injected sequencer rank 3 + conversion data + 0 + 32 + + + + + JDR4 + JDR4 + ADC group injected sequencer rank 4 + register + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + ADC group injected sequencer rank 4 + conversion data + 0 + 32 + + + + + AWD2CR + AWD2CR + ADC analog watchdog 2 configuration + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + ADC analog watchdog 2 monitored channel + selection + 0 + 20 + + + + + AWD3CR + AWD3CR + ADC analog watchdog 3 configuration + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + ADC analog watchdog 3 monitored channel + selection + 1 + 20 + + + + + DIFSEL + DIFSEL + ADC channel differential or single-ended + mode selection register + 0xC0 + 0x20 + read-write + 0x00000000 + + + DIFSEL + ADC channel differential or single-ended + mode for channel + 0 + 20 + + + + + CALFACT + CALFACT + ADC calibration factors + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + ADC calibration factor in differential + mode + 16 + 11 + + + CALFACT_S + ADC calibration factor in single-ended + mode + 0 + 11 + + + + + PCSEL + PCSEL + ADC pre channel selection + register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCSEL + Channel x (VINP[i]) pre + selection + 0 + 20 + + + + + LTR2 + LTR2 + ADC watchdog lower threshold register + 2 + 0xB0 + 0x20 + read-write + 0x00000000 + + + LTR2 + Analog watchdog 2 lower + threshold + 0 + 26 + + + + + HTR2 + HTR2 + ADC watchdog higher threshold register + 2 + 0xB4 + 0x20 + read-write + 0x00000000 + + + HTR2 + Analog watchdog 2 higher + threshold + 0 + 26 + + + + + LTR3 + LTR3 + ADC watchdog lower threshold register + 3 + 0xB8 + 0x20 + read-write + 0x00000000 + + + LTR3 + Analog watchdog 3 lower + threshold + 0 + 26 + + + + + HTR3 + HTR3 + ADC watchdog higher threshold register + 3 + 0xBC + 0x20 + read-write + 0x00000000 + + + HTR3 + Analog watchdog 3 higher + threshold + 0 + 26 + + + + + CALFACT2 + CALFACT2 + ADC Calibration Factor register + 2 + 0xC8 + 0x20 + read-write + 0x00000000 + + + LINCALFACT + Linearity Calibration + Factor + 0 + 30 + + + + + + + ADC1 + 0x40022000 + + + ADC2 + 0x40022100 + + + ADC3_Common + Analog-to-Digital Converter + ADC + 0x58026300 + + 0x0 + 0x100 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADRDY_MST + Master ADC ready + 0 + 1 + + + EOSMP_MST + End of Sampling phase flag of the master + ADC + 1 + 1 + + + EOC_MST + End of regular conversion of the master + ADC + 2 + 1 + + + EOS_MST + End of regular sequence flag of the + master ADC + 3 + 1 + + + OVR_MST + Overrun flag of the master + ADC + 4 + 1 + + + JEOC_MST + End of injected conversion flag of the + master ADC + 5 + 1 + + + JEOS_MST + End of injected sequence flag of the + master ADC + 6 + 1 + + + AWD1_MST + Analog watchdog 1 flag of the master + ADC + 7 + 1 + + + AWD2_MST + Analog watchdog 2 flag of the master + ADC + 8 + 1 + + + AWD3_MST + Analog watchdog 3 flag of the master + ADC + 9 + 1 + + + JQOVF_MST + Injected Context Queue Overflow flag of + the master ADC + 10 + 1 + + + ADRDY_SLV + Slave ADC ready + 16 + 1 + + + EOSMP_SLV + End of Sampling phase flag of the slave + ADC + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave + ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the + slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave + ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the + slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the + slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave + ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave + ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave + ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of + the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DUAL + Dual ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + DAMDF + Dual ADC Mode Data Format + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + PRESC + ADC prescaler + 18 + 4 + + + VREFEN + VREFINT enable + 22 + 1 + + + VSENSEEN + Temperature sensor enable + 23 + 1 + + + VBATEN + VBAT enable + 24 + 1 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave + ADC + 16 + 16 + + + RDATA_MST + Regular data of the master + ADC + 0 + 16 + + + + + CDR2 + CDR2 + ADC x common regular data register for + 32-bit dual mode + 0x10 + 0x20 + read-only + 0x00000000 + + + RDATA_ALT + Regular data of the master/slave + alternated ADCs + 0 + 32 + + + + + + + ADC12_Common + 0x40022300 + + ADC1_2 + ADC1 and ADC2 + 18 + + + + DMAMUX1 + DMAMUX + DMAMUX + 0x40020800 + + 0x0 + 0x400 + registers + + + DMAMUX1_OV + DMAMUX1 overrun interrupt + 102 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer + channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer + channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer + channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer + channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer + channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer + channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer + channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer + channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C8CR + C8CR + DMAMux - DMA request line multiplexer + channel x control register + 0x20 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C9CR + C9CR + DMAMux - DMA request line multiplexer + channel x control register + 0x24 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C10CR + C10CR + DMAMux - DMA request line multiplexer + channel x control register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C11CR + C11CR + DMAMux - DMA request line multiplexer + channel x control register + 0x2C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C12CR + C12CR + DMAMux - DMA request line multiplexer + channel x control register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C13CR + C13CR + DMAMux - DMA request line multiplexer + channel x control register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C14CR + C14CR + DMAMux - DMA request line multiplexer + channel x control register + 0x38 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C15CR + C15CR + DMAMux - DMA request line multiplexer + channel x control register + 0x3C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x + control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x + control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x + control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x + control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG4CR + RG4CR + DMAMux - DMA request generator channel x + control register + 0x110 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG5CR + RG5CR + DMAMux - DMA request generator channel x + control register + 0x114 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG6CR + RG6CR + DMAMux - DMA request generator channel x + control register + 0x118 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG7CR + RG7CR + DMAMux - DMA request generator channel x + control register + 0x11C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is + set when a trigger event occurs on DMA request + generator channel x, while the DMA request generator + counter value is lower than GNBREQ. The flag is + cleared by writing 1 to the corresponding COFx bit in + DMAMUX_RGCFR register. + 0 + 8 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag + register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon + setting, this bit clears the corresponding overrun + flag OFx in the DMAMUX_RGCSR register. + 0 + 8 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt + channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event + flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt + clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event + flag + 0 + 16 + + + + + + + CRC + Cryptographic processor + CRC + 0x58024C00 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 32 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + RESET + RESET bit + 0 + 1 + write-only + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + + + INIT + INIT + Initial CRC value + 0xC + 0x20 + read-write + 0x00000000 + + + CRC_INIT + Programmable initial CRC + value + 0 + 32 + + + + + POL + POL + CRC polynomial + 0x10 + 0x20 + read-write + 0x00000000 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + RCC + Reset and clock control + RCC + 0x58024400 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + clock control register + 0x0 + 0x20 + read-write + 0x00000083 + + + HSION + Internal high-speed clock + enable + 0 + 1 + + + HSIKERON + High Speed Internal clock enable in Stop + mode + 1 + 1 + + + HSIRDY + HSI clock ready flag + 2 + 1 + + + HSIDIV + HSI clock divider + 3 + 2 + + + HSIDIVF + HSI divider flag + 5 + 1 + + + CSION + CSI clock enable + 7 + 1 + + + CSIRDY + CSI clock ready flag + 8 + 1 + + + CSIKERON + CSI clock enable in Stop + mode + 9 + 1 + + + RC48ON + RC48 clock enable + 12 + 1 + + + RC48RDY + RC48 clock ready flag + 13 + 1 + + + D1CKRDY + D1 domain clocks ready + flag + 14 + 1 + + + D2CKRDY + D2 domain clocks ready + flag + 15 + 1 + + + HSEON + HSE clock enable + 16 + 1 + + + HSERDY + HSE clock ready flag + 17 + 1 + + + HSEBYP + HSE clock bypass + 18 + 1 + + + HSECSSON + HSE Clock Security System + enable + 19 + 1 + + + PLL1ON + PLL1 enable + 24 + 1 + + + PLL1RDY + PLL1 clock ready flag + 25 + 1 + + + PLL2ON + PLL2 enable + 26 + 1 + + + PLL2RDY + PLL2 clock ready flag + 27 + 1 + + + PLL3ON + PLL3 enable + 28 + 1 + + + PLL3RDY + PLL3 clock ready flag + 29 + 1 + + + + + ICSCR + ICSCR + RCC Internal Clock Source Calibration + Register + 0x4 + 0x20 + 0x40000000 + + + HSICAL + HSI clock calibration + 0 + 12 + read-only + + + HSITRIM + HSI clock trimming + 12 + 6 + read-write + + + CSICAL + CSI clock calibration + 18 + 8 + read-only + + + CSITRIM + CSI clock trimming + 26 + 5 + read-write + + + + + CRRCR + CRRCR + RCC Clock Recovery RC Register + 0x8 + 0x20 + read-only + 0x00000000 + + + RC48CAL + Internal RC 48 MHz clock + calibration + 0 + 10 + + + + + CFGR + CFGR + RCC Clock Configuration + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + SW + System clock switch + 0 + 3 + + + SWS + System clock switch status + 3 + 3 + + + STOPWUCK + System clock selection after a wake up + from system Stop + 6 + 1 + + + STOPKERWUCK + Kernel clock selection after a wake up + from system Stop + 7 + 1 + + + RTCPRE + HSE division factor for RTC + clock + 8 + 6 + + + HRTIMSEL + High Resolution Timer clock prescaler + selection + 14 + 1 + + + TIMPRE + Timers clocks prescaler + selection + 15 + 1 + + + MCO1PRE + MCO1 prescaler + 18 + 4 + + + MCO1SEL + Micro-controller clock output + 1 + 22 + 3 + + + MCO2PRE + MCO2 prescaler + 25 + 4 + + + MCO2SEL + Micro-controller clock output + 2 + 29 + 3 + + + + + D1CFGR + D1CFGR + RCC Domain 1 Clock Configuration + Register + 0x18 + 0x20 + read-write + 0x00000000 + + + HPRE + D1 domain AHB prescaler + 0 + 4 + + + D1PPRE + D1 domain APB3 prescaler + 4 + 3 + + + D1CPRE + D1 domain Core prescaler + 8 + 4 + + + + + D2CFGR + D2CFGR + RCC Domain 2 Clock Configuration + Register + 0x1C + 0x20 + read-write + 0x00000000 + + + D2PPRE1 + D2 domain APB1 prescaler + 4 + 3 + + + D2PPRE2 + D2 domain APB2 prescaler + 8 + 3 + + + + + D3CFGR + D3CFGR + RCC Domain 3 Clock Configuration + Register + 0x20 + 0x20 + read-write + 0x00000000 + + + D3PPRE + D3 domain APB4 prescaler + 4 + 3 + + + + + PLLCKSELR + PLLCKSELR + RCC PLLs Clock Source Selection + Register + 0x28 + 0x20 + read-write + 0x02020200 + + + PLLSRC + DIVMx and PLLs clock source + selection + 0 + 2 + + + DIVM1 + Prescaler for PLL1 + 4 + 6 + + + DIVM2 + Prescaler for PLL2 + 12 + 6 + + + DIVM3 + Prescaler for PLL3 + 20 + 6 + + + + + PLLCFGR + PLLCFGR + RCC PLLs Configuration + Register + 0x2C + 0x20 + read-write + 0x01FF0000 + + + PLL1FRACEN + PLL1 fractional latch + enable + 0 + 1 + + + PLL1VCOSEL + PLL1 VCO selection + 1 + 1 + + + PLL1RGE + PLL1 input frequency range + 2 + 2 + + + PLL2FRACEN + PLL2 fractional latch + enable + 4 + 1 + + + PLL2VCOSEL + PLL2 VCO selection + 5 + 1 + + + PLL2RGE + PLL2 input frequency range + 6 + 2 + + + PLL3FRACEN + PLL3 fractional latch + enable + 8 + 1 + + + PLL3VCOSEL + PLL3 VCO selection + 9 + 1 + + + PLL3RGE + PLL3 input frequency range + 10 + 2 + + + DIVP1EN + PLL1 DIVP divider output + enable + 16 + 1 + + + DIVQ1EN + PLL1 DIVQ divider output + enable + 17 + 1 + + + DIVR1EN + PLL1 DIVR divider output + enable + 18 + 1 + + + DIVP2EN + PLL2 DIVP divider output + enable + 19 + 1 + + + DIVQ2EN + PLL2 DIVQ divider output + enable + 20 + 1 + + + DIVR2EN + PLL2 DIVR divider output + enable + 21 + 1 + + + DIVP3EN + PLL3 DIVP divider output + enable + 22 + 1 + + + DIVQ3EN + PLL3 DIVQ divider output + enable + 23 + 1 + + + DIVR3EN + PLL3 DIVR divider output + enable + 24 + 1 + + + + + PLL1DIVR + PLL1DIVR + RCC PLL1 Dividers Configuration + Register + 0x30 + 0x20 + read-write + 0x01010280 + + + DIVN1 + Multiplication factor for PLL1 + VCO + 0 + 9 + + + DIVP1 + PLL1 DIVP division factor + 9 + 7 + + + DIVQ1 + PLL1 DIVQ division factor + 16 + 7 + + + DIVR1 + PLL1 DIVR division factor + 24 + 7 + + + + + PLL1FRACR + PLL1FRACR + RCC PLL1 Fractional Divider + Register + 0x34 + 0x20 + read-write + 0x00000000 + + + FRACN1 + Fractional part of the multiplication + factor for PLL1 VCO + 3 + 13 + + + + + PLL2DIVR + PLL2DIVR + RCC PLL2 Dividers Configuration + Register + 0x38 + 0x20 + read-write + 0x01010280 + + + DIVN1 + Multiplication factor for PLL1 + VCO + 0 + 9 + + + DIVP1 + PLL1 DIVP division factor + 9 + 7 + + + DIVQ1 + PLL1 DIVQ division factor + 16 + 7 + + + DIVR1 + PLL1 DIVR division factor + 24 + 7 + + + + + PLL2FRACR + PLL2FRACR + RCC PLL2 Fractional Divider + Register + 0x3C + 0x20 + read-write + 0x00000000 + + + FRACN2 + Fractional part of the multiplication + factor for PLL VCO + 3 + 13 + + + + + PLL3DIVR + PLL3DIVR + RCC PLL3 Dividers Configuration + Register + 0x40 + 0x20 + read-write + 0x01010280 + + + DIVN3 + Multiplication factor for PLL1 + VCO + 0 + 9 + + + DIVP3 + PLL DIVP division factor + 9 + 7 + + + DIVQ3 + PLL DIVQ division factor + 16 + 7 + + + DIVR3 + PLL DIVR division factor + 24 + 7 + + + + + PLL3FRACR + PLL3FRACR + RCC PLL3 Fractional Divider + Register + 0x44 + 0x20 + read-write + 0x00000000 + + + FRACN3 + Fractional part of the multiplication + factor for PLL3 VCO + 3 + 13 + + + + + D1CCIPR + D1CCIPR + RCC Domain 1 Kernel Clock Configuration + Register + 0x4C + 0x20 + read-write + 0x00000000 + + + FMCSRC + FMC kernel clock source + selection + 0 + 2 + + + QSPISRC + QUADSPI kernel clock source + selection + 4 + 2 + + + SDMMCSRC + SDMMC kernel clock source + selection + 16 + 1 + + + CKPERSRC + per_ck clock source + selection + 28 + 2 + + + + + D2CCIP1R + D2CCIP1R + RCC Domain 2 Kernel Clock Configuration + Register + 0x50 + 0x20 + read-write + 0x00000000 + + + SAI1SRC + SAI1 and DFSDM1 kernel Aclk clock source + selection + 0 + 3 + + + SAI23SRC + SAI2 and SAI3 kernel clock source + selection + 6 + 3 + + + SPI123SRC + SPI/I2S1,2 and 3 kernel clock source + selection + 12 + 3 + + + SPI45SRC + SPI4 and 5 kernel clock source + selection + 16 + 3 + + + SPDIFSRC + SPDIFRX kernel clock source + selection + 20 + 2 + + + DFSDM1SRC + DFSDM1 kernel Clk clock source + selection + 24 + 1 + + + FDCANSRC + FDCAN kernel clock source + selection + 28 + 2 + + + SWPSRC + SWPMI kernel clock source + selection + 31 + 1 + + + + + D2CCIP2R + D2CCIP2R + RCC Domain 2 Kernel Clock Configuration + Register + 0x54 + 0x20 + read-write + 0x00000000 + + + USART234578SRC + USART2/3, UART4,5, 7/8 (APB1) kernel + clock source selection + 0 + 3 + + + USART16SRC + USART1 and 6 kernel clock source + selection + 3 + 3 + + + RNGSRC + RNG kernel clock source + selection + 8 + 2 + + + I2C123SRC + I2C1,2,3 kernel clock source + selection + 12 + 2 + + + USBSRC + USBOTG 1 and 2 kernel clock source + selection + 20 + 2 + + + CECSRC + HDMI-CEC kernel clock source + selection + 22 + 2 + + + LPTIM1SRC + LPTIM1 kernel clock source + selection + 28 + 3 + + + + + D3CCIPR + D3CCIPR + RCC Domain 3 Kernel Clock Configuration + Register + 0x58 + 0x20 + read-write + 0x00000000 + + + LPUART1SRC + LPUART1 kernel clock source + selection + 0 + 3 + + + I2C4SRC + I2C4 kernel clock source + selection + 8 + 2 + + + LPTIM2SRC + LPTIM2 kernel clock source + selection + 10 + 3 + + + LPTIM345SRC + LPTIM3,4,5 kernel clock source + selection + 13 + 3 + + + ADCSRC + SAR ADC kernel clock source + selection + 16 + 2 + + + SAI4ASRC + Sub-Block A of SAI4 kernel clock source + selection + 21 + 3 + + + SAI4BSRC + Sub-Block B of SAI4 kernel clock source + selection + 24 + 3 + + + SPI6SRC + SPI6 kernel clock source + selection + 28 + 3 + + + + + CIER + CIER + RCC Clock Source Interrupt Enable + Register + 0x60 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI ready Interrupt Enable + 0 + 1 + + + LSERDYIE + LSE ready Interrupt Enable + 1 + 1 + + + HSIRDYIE + HSI ready Interrupt Enable + 2 + 1 + + + HSERDYIE + HSE ready Interrupt Enable + 3 + 1 + + + CSIRDYIE + CSI ready Interrupt Enable + 4 + 1 + + + RC48RDYIE + RC48 ready Interrupt + Enable + 5 + 1 + + + PLL1RDYIE + PLL1 ready Interrupt + Enable + 6 + 1 + + + PLL2RDYIE + PLL2 ready Interrupt + Enable + 7 + 1 + + + PLL3RDYIE + PLL3 ready Interrupt + Enable + 8 + 1 + + + LSECSSIE + LSE clock security system Interrupt + Enable + 9 + 1 + + + + + CIFR + CIFR + RCC Clock Source Interrupt Flag + Register + 0x64 + 0x20 + read-write + 0x00000000 + + + LSIRDYF + LSI ready Interrupt Flag + 0 + 1 + + + LSERDYF + LSE ready Interrupt Flag + 1 + 1 + + + HSIRDYF + HSI ready Interrupt Flag + 2 + 1 + + + HSERDYF + HSE ready Interrupt Flag + 3 + 1 + + + CSIRDY + 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Interrupt + Clear + 9 + 1 + + + HSECSSC + HSE clock security system Interrupt + Clear + 10 + 1 + + + + + BDCR + BDCR + RCC Backup Domain Control + Register + 0x70 + 0x20 + read-write + 0x00000000 + + + LSEON + LSE oscillator enabled + 0 + 1 + + + LSERDY + LSE oscillator ready + 1 + 1 + + + LSEBYP + LSE oscillator bypass + 2 + 1 + + + LSEDRV + LSE oscillator driving + capability + 3 + 2 + + + LSECSSON + LSE clock security system + enable + 5 + 1 + + + LSECSSD + LSE clock security system failure + detection + 6 + 1 + + + RTCSRC + RTC clock source selection + 8 + 2 + + + RTCEN + RTC clock enable + 15 + 1 + + + VSWRST + VSwitch domain software + reset + 16 + 1 + + + + + CSR + CSR + RCC Clock Control and Status + Register + 0x74 + 0x20 + read-write + 0x00000000 + + + LSION + LSI oscillator enable + 0 + 1 + + + LSIRDY + LSI oscillator ready + 1 + 1 + + + + + AHB3RSTR + AHB3RSTR + RCC AHB3 Reset Register + 0x7C + 0x20 + read-write + 0x00000000 + + + MDMARST + MDMA block reset + 0 + 1 + + + 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SDMMC2 Delay block + reset + 9 + 1 + + + + + AHB4RSTR + AHB4RSTR + RCC AHB4 Peripheral Reset + Register + 0x88 + 0x20 + read-write + 0x00000000 + + + GPIOARST + GPIO block reset + 0 + 1 + + + GPIOBRST + GPIO block reset + 1 + 1 + + + GPIOCRST + GPIO block reset + 2 + 1 + + + GPIODRST + GPIO block reset + 3 + 1 + + + GPIOERST + GPIO block reset + 4 + 1 + + + GPIOFRST + GPIO block reset + 5 + 1 + + + GPIOGRST + GPIO block reset + 6 + 1 + + + GPIOHRST + GPIO block reset + 7 + 1 + + + GPIOIRST + GPIO block reset + 8 + 1 + + + GPIOJRST + GPIO block reset + 9 + 1 + + + GPIOKRST + GPIO block reset + 10 + 1 + + + CRCRST + CRC block reset + 19 + 1 + + + BDMARST + BDMA block reset + 21 + 1 + + + ADC3RST + ADC3 block reset + 24 + 1 + + + HSEMRST + HSEM block reset + 25 + 1 + + + + + APB3RSTR + APB3RSTR + RCC APB3 Peripheral Reset + Register + 0x8C + 0x20 + read-write + 0x00000000 + + + LTDCRST + LTDC block reset + 3 + 1 + + + + + APB1LRSTR + APB1LRSTR + RCC APB1 Peripheral Reset + Register + 0x90 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM block reset + 0 + 1 + + + TIM3RST + TIM block reset + 1 + 1 + + + TIM4RST + TIM block reset + 2 + 1 + + + TIM5RST + TIM block reset + 3 + 1 + + + TIM6RST + TIM block reset + 4 + 1 + + + TIM7RST + TIM block reset + 5 + 1 + + + TIM12RST + TIM block reset + 6 + 1 + + + TIM13RST + TIM block reset + 7 + 1 + + + TIM14RST + TIM block reset + 8 + 1 + + + LPTIM1RST + TIM block reset + 9 + 1 + + + SPI2RST + SPI2 block reset + 14 + 1 + + + SPI3RST + SPI3 block reset + 15 + 1 + + + SPDIFRXRST + SPDIFRX block reset + 16 + 1 + + + USART2RST + USART2 block reset + 17 + 1 + + + USART3RST + USART3 block reset + 18 + 1 + + + UART4RST + UART4 block reset + 19 + 1 + + + UART5RST + UART5 block reset + 20 + 1 + + + I2C1RST + I2C1 block reset + 21 + 1 + + + I2C2RST + I2C2 block reset + 22 + 1 + + + I2C3RST + I2C3 block reset + 23 + 1 + + + HDMICECRST + HDMI-CEC block reset + 27 + 1 + + + DAC12RST + DAC1 and 2 Blocks Reset + 29 + 1 + + + USART7RST + USART7 block reset + 30 + 1 + + + USART8RST + USART8 block reset + 31 + 1 + + + + + APB1HRSTR + APB1HRSTR + RCC APB1 Peripheral Reset + Register + 0x94 + 0x20 + read-write + 0x00000000 + + + CRSRST + Clock Recovery System + reset + 1 + 1 + + + SWPRST + SWPMI block reset + 2 + 1 + + + OPAMPRST + OPAMP block reset + 4 + 1 + + + MDIOSRST + MDIOS block reset + 5 + 1 + + + FDCANRST + FDCAN block reset + 8 + 1 + + + + + APB2RSTR + APB2RSTR + RCC APB2 Peripheral Reset + Register + 0x98 + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1 block reset + 0 + 1 + + + TIM8RST + TIM8 block reset + 1 + 1 + + + USART1RST + USART1 block reset + 4 + 1 + + + USART6RST + USART6 block reset + 5 + 1 + + + SPI1RST + SPI1 block reset + 12 + 1 + + + SPI4RST + SPI4 block reset + 13 + 1 + + + TIM15RST + TIM15 block reset + 16 + 1 + + + TIM16RST + TIM16 block reset + 17 + 1 + + + TIM17RST + TIM17 block reset + 18 + 1 + + + SPI5RST + SPI5 block reset + 20 + 1 + + + SAI1RST + SAI1 block reset + 22 + 1 + + + SAI2RST + SAI2 block reset + 23 + 1 + + + SAI3RST + SAI3 block reset + 24 + 1 + + + DFSDM1RST + DFSDM1 block reset + 28 + 1 + + + HRTIMRST + HRTIM block reset + 29 + 1 + + + + + APB4RSTR + APB4RSTR + RCC APB4 Peripheral Reset + Register + 0x9C + 0x20 + read-write + 0x00000000 + + + SYSCFGRST + SYSCFG block reset + 1 + 1 + + + LPUART1RST + LPUART1 block reset + 3 + 1 + + + SPI6RST + SPI6 block reset + 5 + 1 + + + I2C4RST + I2C4 block reset + 7 + 1 + + + LPTIM2RST + LPTIM2 block reset + 9 + 1 + + + LPTIM3RST + LPTIM3 block reset + 10 + 1 + + + LPTIM4RST + LPTIM4 block reset + 11 + 1 + + + LPTIM5RST + LPTIM5 block reset + 12 + 1 + + + COMP12RST + COMP12 Blocks Reset + 14 + 1 + + + VREFRST + VREF block reset + 15 + 1 + + + SAI4RST + SAI4 block reset + 21 + 1 + + + + + GCR + GCR + RCC Global Control Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + WW1RSC + WWDG1 reset scope control + 0 + 1 + + + + + D3AMR + D3AMR + RCC D3 Autonomous mode + Register + 0xA8 + 0x20 + read-write + 0x00000000 + + + BDMAAMEN + BDMA and DMAMUX Autonomous mode + enable + 0 + 1 + + + LPUART1AMEN + LPUART1 Autonomous mode + enable + 3 + 1 + + + SPI6AMEN + SPI6 Autonomous mode + enable + 5 + 1 + + + I2C4AMEN + I2C4 Autonomous mode + enable + 7 + 1 + + + LPTIM2AMEN + LPTIM2 Autonomous mode + enable + 9 + 1 + + + LPTIM3AMEN + LPTIM3 Autonomous mode + enable + 10 + 1 + + + LPTIM4AMEN + LPTIM4 Autonomous mode + enable + 11 + 1 + + + LPTIM5AMEN + LPTIM5 Autonomous mode + enable + 12 + 1 + + + COMP12AMEN + COMP12 Autonomous mode + enable + 14 + 1 + + + VREFAMEN + VREF Autonomous mode + enable + 15 + 1 + + + RTCAMEN + RTC Autonomous mode enable + 16 + 1 + + + CRCAMEN + CRC Autonomous mode enable + 19 + 1 + + + SAI4AMEN + SAI4 Autonomous mode + enable + 21 + 1 + + + ADC3AMEN + ADC3 Autonomous mode + enable + 24 + 1 + + + BKPSRAMAMEN + Backup RAM Autonomous mode + enable + 28 + 1 + + + SRAM4AMEN + SRAM4 Autonomous mode + enable + 29 + 1 + + + + + RSR + RSR + RCC Reset Status Register + 0xD0 + 0x20 + read-write + 0x00000000 + + + RMVF + Remove reset flag + 16 + 1 + + + CPURSTF + CPU reset flag + 17 + 1 + + + D1RSTF + D1 domain power switch reset + flag + 19 + 1 + + + D2RSTF + D2 domain power switch reset + flag + 20 + 1 + + + BORRSTF + BOR reset flag + 21 + 1 + + + PINRSTF + Pin reset flag (NRST) + 22 + 1 + + + PORRSTF + POR/PDR reset flag + 23 + 1 + + + SFTRSTF + System reset from CPU reset + flag + 24 + 1 + + + IWDG1RSTF + Independent Watchdog reset + flag + 26 + 1 + + + WWDG1RSTF + Window Watchdog reset flag + 28 + 1 + + + LPWRRSTF + Reset due to illegal D1 DStandby or CPU + CStop flag + 30 + 1 + + + + + C1_RSR + C1_RSR + RCC Reset Status Register + 0x130 + 0x20 + read-write + 0x00000000 + + + RMVF + Remove reset flag + 16 + 1 + + + CPURSTF + CPU reset flag + 17 + 1 + + + D1RSTF + D1 domain power switch reset + flag + 19 + 1 + + + D2RSTF + D2 domain power switch reset + flag + 20 + 1 + + + BORRSTF + BOR reset flag + 21 + 1 + + + PINRSTF + Pin reset flag (NRST) + 22 + 1 + + + PORRSTF + POR/PDR reset flag + 23 + 1 + + + SFTRSTF + System reset from CPU reset + flag + 24 + 1 + + + IWDG1RSTF + Independent Watchdog reset + flag + 26 + 1 + + + WWDG1RSTF + Window Watchdog reset flag + 28 + 1 + + + LPWRRSTF + Reset due to illegal D1 DStandby or CPU + CStop flag + 30 + 1 + + + + + C1_AHB3ENR + C1_AHB3ENR + RCC AHB3 Clock Register + 0x134 + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMA Peripheral Clock + Enable + 0 + 1 + + + DMA2DEN + DMA2D Peripheral Clock + Enable + 4 + 1 + + + JPGDECEN + JPGDEC Peripheral Clock + Enable + 5 + 1 + + + FMCEN + FMC Peripheral Clocks + Enable + 12 + 1 + + + QSPIEN + QUADSPI and QUADSPI Delay Clock + Enable + 14 + 1 + + + SDMMC1EN + SDMMC1 and SDMMC1 Delay Clock + Enable + 16 + 1 + + + + + AHB3ENR + AHB3ENR + RCC AHB3 Clock Register + 0xD4 + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMA Peripheral Clock + Enable + 0 + 1 + + + DMA2DEN + DMA2D Peripheral Clock + Enable + 4 + 1 + + + JPGDECEN + JPGDEC Peripheral Clock + Enable + 5 + 1 + + + FMCEN + FMC Peripheral Clocks + Enable + 12 + 1 + + + QSPIEN + QUADSPI and QUADSPI Delay Clock + Enable + 14 + 1 + + + SDMMC1EN + SDMMC1 and SDMMC1 Delay Clock + Enable + 16 + 1 + + + + + AHB1ENR + AHB1ENR + RCC AHB1 Clock Register + 0xD8 + 0x20 + read-write + 0x00000000 + + + DMA1EN + DMA1 Clock Enable + 0 + 1 + + + DMA2EN + DMA2 Clock Enable + 1 + 1 + + + ADC12EN + ADC1/2 Peripheral Clocks + Enable + 5 + 1 + + + ETH1MACEN + Ethernet MAC bus interface Clock + Enable + 15 + 1 + + + ETH1TXEN + Ethernet Transmission Clock + Enable + 16 + 1 + + + ETH1RXEN + Ethernet Reception Clock + Enable + 17 + 1 + + + USB1OTGEN + USB1OTG Peripheral Clocks + Enable + 25 + 1 + + + USB1ULPIEN + USB_PHY1 Clocks Enable + 26 + 1 + + + USB2OTGEN + USB2OTG Peripheral Clocks + Enable + 27 + 1 + + + USB2ULPIEN + USB_PHY2 Clocks Enable + 28 + 1 + + + + + C1_AHB1ENR + C1_AHB1ENR + RCC AHB1 Clock Register + 0x138 + 0x20 + read-write + 0x00000000 + + + DMA1EN + DMA1 Clock Enable + 0 + 1 + + + DMA2EN + DMA2 Clock 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6 + 1 + + + GPIOHEN + 0GPIO peripheral clock + enable + 7 + 1 + + + GPIOIEN + 0GPIO peripheral clock + enable + 8 + 1 + + + GPIOJEN + 0GPIO peripheral clock + enable + 9 + 1 + + + GPIOKEN + 0GPIO peripheral clock + enable + 10 + 1 + + + CRCEN + CRC peripheral clock + enable + 19 + 1 + + + BDMAEN + BDMA and DMAMUX2 Clock + Enable + 21 + 1 + + + ADC3EN + ADC3 Peripheral Clocks + Enable + 24 + 1 + + + HSEMEN + HSEM peripheral clock + enable + 25 + 1 + + + BKPRAMEN + Backup RAM Clock Enable + 28 + 1 + + + + + C1_AHB4ENR + C1_AHB4ENR + RCC AHB4 Clock Register + 0x140 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + 0GPIO peripheral clock + enable + 0 + 1 + + + GPIOBEN + 0GPIO peripheral clock + enable + 1 + 1 + + + GPIOCEN + 0GPIO peripheral clock + enable + 2 + 1 + + + GPIODEN + 0GPIO peripheral clock + enable + 3 + 1 + + + GPIOEEN + 0GPIO peripheral clock + enable + 4 + 1 + + + GPIOFEN + 0GPIO peripheral clock + enable + 5 + 1 + + + GPIOGEN + 0GPIO peripheral clock + enable + 6 + 1 + + + GPIOHEN + 0GPIO peripheral clock + enable + 7 + 1 + + + GPIOIEN + 0GPIO peripheral clock + enable + 8 + 1 + + + GPIOJEN + 0GPIO peripheral clock + enable + 9 + 1 + + + GPIOKEN + 0GPIO peripheral clock + enable + 10 + 1 + + + CRCEN + CRC peripheral clock + enable + 19 + 1 + + + BDMAEN + BDMA and DMAMUX2 Clock + Enable + 21 + 1 + + + ADC3EN + ADC3 Peripheral Clocks + Enable + 24 + 1 + + + HSEMEN + HSEM peripheral clock + enable + 25 + 1 + + + BKPRAMEN + Backup RAM Clock Enable + 28 + 1 + + + + + C1_APB3ENR + C1_APB3ENR + RCC APB3 Clock Register + 0x144 + 0x20 + read-write + 0x00000000 + + + LTDCEN + LTDC peripheral clock + enable + 3 + 1 + + + WWDG1EN + WWDG1 Clock Enable + 6 + 1 + + + + + APB3ENR + APB3ENR + RCC APB3 Clock Register + 0xE4 + 0x20 + read-write + 0x00000000 + + + LTDCEN + LTDC peripheral clock + enable + 3 + 1 + + + WWDG1EN + WWDG1 Clock Enable + 6 + 1 + + + + + APB1LENR + APB1LENR + RCC APB1 Clock Register + 0xE8 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM peripheral clock + enable + 0 + 1 + + + TIM3EN + TIM peripheral clock + enable + 1 + 1 + + + TIM4EN + TIM peripheral clock + enable + 2 + 1 + + + TIM5EN + TIM peripheral clock + enable + 3 + 1 + + + TIM6EN + TIM peripheral clock + enable + 4 + 1 + + + TIM7EN + TIM peripheral clock + enable + 5 + 1 + + + TIM12EN + TIM peripheral clock + enable + 6 + 1 + + + TIM13EN + TIM peripheral clock + enable + 7 + 1 + + + TIM14EN + TIM peripheral clock + enable + 8 + 1 + + + LPTIM1EN + LPTIM1 Peripheral Clocks + Enable + 9 + 1 + + + SPI2EN + SPI2 Peripheral Clocks + Enable + 14 + 1 + + + SPI3EN + SPI3 Peripheral Clocks + Enable + 15 + 1 + + + SPDIFRXEN + SPDIFRX Peripheral Clocks + Enable + 16 + 1 + + + USART2EN + USART2 Peripheral Clocks + Enable + 17 + 1 + + + USART3EN + USART3 Peripheral Clocks + Enable + 18 + 1 + + + UART4EN + UART4 Peripheral Clocks + Enable + 19 + 1 + + + UART5EN + UART5 Peripheral Clocks + Enable + 20 + 1 + + + I2C1EN + I2C1 Peripheral Clocks + Enable + 21 + 1 + + + I2C2EN + I2C2 Peripheral Clocks + Enable + 22 + 1 + + + I2C3EN + I2C3 Peripheral Clocks + Enable + 23 + 1 + + + HDMICECEN + HDMI-CEC peripheral clock + enable + 27 + 1 + + + DAC12EN + DAC1&2 peripheral clock + enable + 29 + 1 + + + USART7EN + USART7 Peripheral Clocks + Enable + 30 + 1 + + + USART8EN + USART8 Peripheral Clocks + Enable + 31 + 1 + + + + + C1_APB1LENR + C1_APB1LENR + RCC APB1 Clock Register + 0x148 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM peripheral clock + enable + 0 + 1 + + + TIM3EN + TIM peripheral clock + enable + 1 + 1 + + + TIM4EN + TIM peripheral clock + enable + 2 + 1 + + + TIM5EN + TIM peripheral clock + enable + 3 + 1 + + + TIM6EN + TIM peripheral clock + enable + 4 + 1 + + + TIM7EN + TIM peripheral clock + enable + 5 + 1 + + + TIM12EN + TIM peripheral clock + enable + 6 + 1 + + + TIM13EN + TIM peripheral clock + enable + 7 + 1 + + + TIM14EN + TIM peripheral clock + enable + 8 + 1 + + + LPTIM1EN + LPTIM1 Peripheral Clocks + Enable + 9 + 1 + + + SPI2EN + SPI2 Peripheral Clocks + Enable + 14 + 1 + + + SPI3EN + SPI3 Peripheral Clocks + Enable + 15 + 1 + + + SPDIFRXEN + SPDIFRX Peripheral Clocks + Enable + 16 + 1 + + + USART2EN + USART2 Peripheral Clocks + Enable + 17 + 1 + + + USART3EN + USART3 Peripheral Clocks + Enable + 18 + 1 + + + UART4EN + UART4 Peripheral Clocks + Enable + 19 + 1 + + + UART5EN + UART5 Peripheral Clocks + Enable + 20 + 1 + + + I2C1EN + I2C1 Peripheral Clocks + Enable + 21 + 1 + + + I2C2EN + I2C2 Peripheral Clocks + Enable + 22 + 1 + + + I2C3EN + I2C3 Peripheral Clocks + Enable + 23 + 1 + + + HDMICECEN + HDMI-CEC peripheral clock + enable + 27 + 1 + + + DAC12EN + DAC1&2 peripheral clock + enable + 29 + 1 + + + USART7EN + USART7 Peripheral Clocks + Enable + 30 + 1 + + + USART8EN + USART8 Peripheral Clocks + Enable + 31 + 1 + + + + + APB1HENR + APB1HENR + RCC APB1 Clock Register + 0xEC + 0x20 + read-write + 0x00000000 + + + CRSEN + Clock Recovery System peripheral clock + enable + 1 + 1 + + + SWPEN + SWPMI Peripheral Clocks + Enable + 2 + 1 + + + OPAMPEN + OPAMP peripheral clock + enable + 4 + 1 + + + MDIOSEN + MDIOS peripheral clock + enable + 5 + 1 + + + FDCANEN + FDCAN Peripheral Clocks + Enable + 8 + 1 + + + + + C1_APB1HENR + C1_APB1HENR + RCC APB1 Clock Register + 0x14C + 0x20 + read-write + 0x00000000 + + + CRSEN + Clock Recovery System peripheral clock + enable + 1 + 1 + + + SWPEN + SWPMI Peripheral Clocks + Enable + 2 + 1 + + + OPAMPEN + OPAMP peripheral clock + enable + 4 + 1 + + + MDIOSEN + MDIOS peripheral clock + enable + 5 + 1 + + + FDCANEN + FDCAN Peripheral Clocks + Enable + 8 + 1 + + + + + C1_APB2ENR + C1_APB2ENR + RCC APB2 Clock Register + 0x150 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1 peripheral clock + enable + 0 + 1 + + + TIM8EN + TIM8 peripheral clock + enable + 1 + 1 + + + USART1EN + USART1 Peripheral Clocks + Enable + 4 + 1 + + + USART6EN + USART6 Peripheral Clocks + Enable + 5 + 1 + + + SPI1EN + SPI1 Peripheral Clocks + Enable + 12 + 1 + + + SPI4EN + SPI4 Peripheral Clocks + Enable + 13 + 1 + + + TIM16EN + TIM16 peripheral clock + enable + 17 + 1 + + + TIM15EN + TIM15 peripheral clock + enable + 16 + 1 + + + TIM17EN + TIM17 peripheral clock + enable + 18 + 1 + + + SPI5EN + SPI5 Peripheral Clocks + Enable + 20 + 1 + + + SAI1EN + SAI1 Peripheral Clocks + Enable + 22 + 1 + + + SAI2EN + SAI2 Peripheral Clocks + Enable + 23 + 1 + + + SAI3EN + SAI3 Peripheral Clocks + Enable + 24 + 1 + + + DFSDM1EN + DFSDM1 Peripheral Clocks + Enable + 28 + 1 + + + HRTIMEN + HRTIM peripheral clock + enable + 29 + 1 + + + + + APB2ENR + APB2ENR + RCC APB2 Clock Register + 0xF0 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1 peripheral clock + enable + 0 + 1 + + + TIM8EN + TIM8 peripheral clock + enable + 1 + 1 + + + USART1EN + USART1 Peripheral Clocks + Enable + 4 + 1 + + + USART6EN + USART6 Peripheral Clocks + Enable + 5 + 1 + + + SPI1EN + SPI1 Peripheral Clocks + Enable + 12 + 1 + + + SPI4EN + SPI4 Peripheral Clocks + Enable + 13 + 1 + + + TIM16EN + TIM16 peripheral clock + enable + 17 + 1 + + + TIM15EN + TIM15 peripheral clock + enable + 16 + 1 + + + TIM17EN + TIM17 peripheral clock + enable + 18 + 1 + + + SPI5EN + SPI5 Peripheral Clocks + Enable + 20 + 1 + + + SAI1EN + SAI1 Peripheral Clocks + Enable + 22 + 1 + + + SAI2EN + SAI2 Peripheral Clocks + Enable + 23 + 1 + + + SAI3EN + SAI3 Peripheral Clocks + Enable + 24 + 1 + + + DFSDM1EN + DFSDM1 Peripheral Clocks + Enable + 28 + 1 + + + HRTIMEN + HRTIM peripheral clock + enable + 29 + 1 + + + + + APB4ENR + APB4ENR + RCC APB4 Clock Register + 0xF4 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clock + enable + 1 + 1 + + + LPUART1EN + LPUART1 Peripheral Clocks + Enable + 3 + 1 + + + SPI6EN + SPI6 Peripheral Clocks + Enable + 5 + 1 + + + I2C4EN + I2C4 Peripheral Clocks + Enable + 7 + 1 + + + LPTIM2EN + LPTIM2 Peripheral Clocks + Enable + 9 + 1 + + + LPTIM3EN + LPTIM3 Peripheral Clocks + Enable + 10 + 1 + + + LPTIM4EN + LPTIM4 Peripheral Clocks + Enable + 11 + 1 + + + LPTIM5EN + LPTIM5 Peripheral Clocks + Enable + 12 + 1 + + + COMP12EN + COMP1/2 peripheral clock + enable + 14 + 1 + + + VREFEN + VREF peripheral clock + enable + 15 + 1 + + + RTCAPBEN + RTC APB Clock Enable + 16 + 1 + + + SAI4EN + SAI4 Peripheral Clocks + Enable + 21 + 1 + + + + + C1_APB4ENR + C1_APB4ENR + RCC APB4 Clock Register + 0x154 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clock + enable + 1 + 1 + + + LPUART1EN + LPUART1 Peripheral Clocks + Enable + 3 + 1 + + + SPI6EN + SPI6 Peripheral Clocks + Enable + 5 + 1 + + + I2C4EN + I2C4 Peripheral Clocks + Enable + 7 + 1 + + + LPTIM2EN + LPTIM2 Peripheral Clocks + Enable + 9 + 1 + + + LPTIM3EN + LPTIM3 Peripheral Clocks + Enable + 10 + 1 + + + LPTIM4EN + LPTIM4 Peripheral Clocks + Enable + 11 + 1 + + + LPTIM5EN + LPTIM5 Peripheral Clocks + Enable + 12 + 1 + + + COMP12EN + COMP1/2 peripheral clock + enable + 14 + 1 + + + VREFEN + VREF peripheral clock + enable + 15 + 1 + + + RTCAPBEN + RTC APB Clock Enable + 16 + 1 + + + SAI4EN + SAI4 Peripheral Clocks + Enable + 21 + 1 + + + + + C1_AHB3LPENR + C1_AHB3LPENR + RCC AHB3 Sleep Clock Register + 0x15C + 0x20 + read-write + 0x00000000 + + + MDMALPEN + MDMA Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2DLPEN + DMA2D Clock Enable During CSleep + Mode + 4 + 1 + + + JPGDECLPEN + JPGDEC Clock Enable During CSleep + Mode + 5 + 1 + + + FLITFLPEN + FLITF Clock Enable During CSleep + Mode + 8 + 1 + + + FMCLPEN + FMC Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + QSPILPEN + QUADSPI and QUADSPI Delay Clock Enable + During CSleep Mode + 14 + 1 + + + SDMMC1LPEN + SDMMC1 and SDMMC1 Delay Clock Enable + During CSleep Mode + 16 + 1 + + + D1DTCM1LPEN + D1DTCM1 Block Clock Enable During CSleep + mode + 28 + 1 + + + DTCM2LPEN + D1 DTCM2 Block Clock Enable During + CSleep mode + 29 + 1 + + + ITCMLPEN + D1ITCM Block Clock Enable During CSleep + mode + 30 + 1 + + + AXISRAMLPEN + AXISRAM Block Clock Enable During CSleep + mode + 31 + 1 + + + + + AHB3LPENR + AHB3LPENR + RCC AHB3 Sleep Clock Register + 0xFC + 0x20 + read-write + 0x00000000 + + + MDMALPEN + MDMA Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2DLPEN + DMA2D Clock Enable During CSleep + Mode + 4 + 1 + + + JPGDECLPEN + JPGDEC Clock Enable During CSleep + Mode + 5 + 1 + + + FLITFLPEN + FLITF Clock Enable During CSleep + Mode + 8 + 1 + + + FMCLPEN + FMC Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + QSPILPEN + QUADSPI and QUADSPI Delay Clock Enable + During CSleep Mode + 14 + 1 + + + SDMMC1LPEN + SDMMC1 and SDMMC1 Delay Clock Enable + During CSleep Mode + 16 + 1 + + + D1DTCM1LPEN + D1DTCM1 Block Clock Enable During CSleep + mode + 28 + 1 + + + DTCM2LPEN + D1 DTCM2 Block Clock Enable During + CSleep mode + 29 + 1 + + + ITCMLPEN + D1ITCM Block Clock Enable During CSleep + mode + 30 + 1 + + + AXISRAMLPEN + AXISRAM Block Clock Enable During CSleep + mode + 31 + 1 + + + + + AHB1LPENR + AHB1LPENR + RCC AHB1 Sleep Clock Register + 0x100 + 0x20 + read-write + 0x00000000 + + + DMA1LPEN + DMA1 Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2LPEN + DMA2 Clock Enable During CSleep + Mode + 1 + 1 + + + ADC12LPEN + ADC1/2 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + ETH1MACLPEN + Ethernet MAC bus interface Clock Enable + During CSleep Mode + 15 + 1 + + + ETH1TXLPEN + Ethernet Transmission Clock Enable + During CSleep Mode + 16 + 1 + + + ETH1RXLPEN + Ethernet Reception Clock Enable During + CSleep Mode + 17 + 1 + + + USB1OTGLPEN + USB1OTG peripheral clock enable during + CSleep mode + 25 + 1 + + + USB1ULPILPEN + USB_PHY1 clock enable during CSleep + mode + 26 + 1 + + + USB2OTGLPEN + USB2OTG peripheral clock enable during + CSleep mode + 27 + 1 + + + USB2ULPILPEN + USB_PHY2 clocks enable during CSleep + mode + 28 + 1 + + + + + C1_AHB1LPENR + C1_AHB1LPENR + RCC AHB1 Sleep Clock Register + 0x160 + 0x20 + read-write + 0x00000000 + + + DMA1LPEN + DMA1 Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2LPEN + DMA2 Clock Enable During CSleep + Mode + 1 + 1 + + + ADC12LPEN + ADC1/2 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + ETH1MACLPEN + Ethernet MAC bus interface Clock Enable + During CSleep Mode + 15 + 1 + + + ETH1TXLPEN + Ethernet Transmission Clock Enable + During CSleep Mode + 16 + 1 + + + ETH1RXLPEN + Ethernet Reception Clock Enable During + CSleep Mode + 17 + 1 + + + USB1OTGLPEN + USB1OTG peripheral clock enable during + CSleep mode + 25 + 1 + + + USB1ULPILPEN + USB_PHY1 clock enable during CSleep + mode + 26 + 1 + + + USB2OTGLPEN + USB2OTG peripheral clock enable during + CSleep mode + 27 + 1 + + + USB2ULPILPEN + USB_PHY2 clocks enable during CSleep + mode + 28 + 1 + + + + + C1_AHB2LPENR + C1_AHB2LPENR + RCC AHB2 Sleep Clock Register + 0x164 + 0x20 + read-write + 0x00000000 + + + CAMITFLPEN + CAMITF peripheral clock enable during + CSleep mode + 0 + 1 + + + CRYPTLPEN + CRYPT peripheral clock enable during + CSleep mode + 4 + 1 + + + HASHLPEN + HASH peripheral clock enable during + CSleep mode + 5 + 1 + + + SDMMC2LPEN + SDMMC2 and SDMMC2 Delay Clock Enable + During CSleep Mode + 9 + 1 + + + RNGLPEN + RNG peripheral clock enable during + CSleep mode + 6 + 1 + + + SRAM1LPEN + SRAM1 Clock Enable During CSleep + Mode + 29 + 1 + + + SRAM2LPEN + SRAM2 Clock Enable During CSleep + Mode + 30 + 1 + + + SRAM3LPEN + SRAM3 Clock Enable During CSleep + Mode + 31 + 1 + + + + + AHB2LPENR + AHB2LPENR + RCC AHB2 Sleep Clock Register + 0x104 + 0x20 + read-write + 0x00000000 + + + CAMITFLPEN + CAMITF peripheral clock enable during + CSleep mode + 0 + 1 + + + CRYPTLPEN + CRYPT peripheral clock enable during + CSleep mode + 4 + 1 + + + HASHLPEN + HASH peripheral clock enable during + CSleep mode + 5 + 1 + + + SDMMC2LPEN + SDMMC2 and SDMMC2 Delay Clock Enable + During CSleep Mode + 9 + 1 + + + RNGLPEN + RNG peripheral clock enable during + CSleep mode + 6 + 1 + + + SRAM1LPEN + SRAM1 Clock Enable During CSleep + Mode + 29 + 1 + + + SRAM2LPEN + SRAM2 Clock Enable During CSleep + Mode + 30 + 1 + + + SRAM3LPEN + SRAM3 Clock Enable During CSleep + Mode + 31 + 1 + + + + + AHB4LPENR + AHB4LPENR + RCC AHB4 Sleep Clock Register + 0x108 + 0x20 + read-write + 0x00000000 + + + GPIOALPEN + GPIO peripheral clock enable during + CSleep mode + 0 + 1 + + + GPIOBLPEN + GPIO peripheral clock enable during + CSleep mode + 1 + 1 + + + GPIOCLPEN + GPIO peripheral clock enable during + CSleep mode + 2 + 1 + + + GPIODLPEN + GPIO peripheral clock enable during + CSleep mode + 3 + 1 + + + GPIOELPEN + GPIO peripheral clock enable during + CSleep mode + 4 + 1 + + + GPIOFLPEN + GPIO peripheral clock enable during + CSleep mode + 5 + 1 + + + GPIOGLPEN + GPIO peripheral clock enable during + CSleep mode + 6 + 1 + + + GPIOHLPEN + GPIO peripheral clock enable during + CSleep mode + 7 + 1 + + + GPIOILPEN + GPIO peripheral clock enable during + CSleep mode + 8 + 1 + + + GPIOJLPEN + GPIO peripheral clock enable during + CSleep mode + 9 + 1 + + + GPIOKLPEN + GPIO peripheral clock enable during + CSleep mode + 10 + 1 + + + CRCLPEN + CRC peripheral clock enable during + CSleep mode + 19 + 1 + + + BDMALPEN + BDMA Clock Enable During CSleep + Mode + 21 + 1 + + + ADC3LPEN + ADC3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + BKPRAMLPEN + Backup RAM Clock Enable During CSleep + Mode + 28 + 1 + + + SRAM4LPEN + SRAM4 Clock Enable During CSleep + Mode + 29 + 1 + + + + + C1_AHB4LPENR + C1_AHB4LPENR + RCC AHB4 Sleep Clock Register + 0x168 + 0x20 + read-write + 0x00000000 + + + GPIOALPEN + GPIO peripheral clock enable during + CSleep mode + 0 + 1 + + + GPIOBLPEN + GPIO peripheral clock enable during + CSleep mode + 1 + 1 + + + GPIOCLPEN + GPIO peripheral clock enable during + CSleep mode + 2 + 1 + + + GPIODLPEN + GPIO peripheral clock enable during + CSleep mode + 3 + 1 + + + GPIOELPEN + GPIO peripheral clock enable during + CSleep mode + 4 + 1 + + + GPIOFLPEN + GPIO peripheral clock enable during + CSleep mode + 5 + 1 + + + GPIOGLPEN + GPIO peripheral clock enable during + CSleep mode + 6 + 1 + + + GPIOHLPEN + GPIO peripheral clock enable during + CSleep mode + 7 + 1 + + + GPIOILPEN + GPIO peripheral clock enable during + CSleep mode + 8 + 1 + + + GPIOJLPEN + GPIO peripheral clock enable during + CSleep mode + 9 + 1 + + + GPIOKLPEN + GPIO peripheral clock enable during + CSleep mode + 10 + 1 + + + CRCLPEN + CRC peripheral clock enable during + CSleep mode + 19 + 1 + + + BDMALPEN + BDMA Clock Enable During CSleep + Mode + 21 + 1 + + + ADC3LPEN + ADC3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + BKPRAMLPEN + Backup RAM Clock Enable During CSleep + Mode + 28 + 1 + + + SRAM4LPEN + SRAM4 Clock Enable During CSleep + Mode + 29 + 1 + + + + + C1_APB3LPENR + C1_APB3LPENR + RCC APB3 Sleep Clock Register + 0x16C + 0x20 + read-write + 0x00000000 + + + LTDCLPEN + LTDC peripheral clock enable during + CSleep mode + 3 + 1 + + + WWDG1LPEN + WWDG1 Clock Enable During CSleep + Mode + 6 + 1 + + + + + APB3LPENR + APB3LPENR + RCC APB3 Sleep Clock Register + 0x10C + 0x20 + read-write + 0x00000000 + + + LTDCLPEN + LTDC peripheral clock enable during + CSleep mode + 3 + 1 + + + WWDG1LPEN + WWDG1 Clock Enable During CSleep + Mode + 6 + 1 + + + + + APB1LLPENR + APB1LLPENR + RCC APB1 Low Sleep Clock + Register + 0x110 + 0x20 + read-write + 0x00000000 + + + TIM2LPEN + TIM2 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM3LPEN + TIM3 peripheral clock enable during + CSleep mode + 1 + 1 + + + TIM4LPEN + TIM4 peripheral clock enable during + CSleep mode + 2 + 1 + + + TIM5LPEN + TIM5 peripheral clock enable during + CSleep mode + 3 + 1 + + + TIM6LPEN + TIM6 peripheral clock enable during + CSleep mode + 4 + 1 + + + TIM7LPEN + TIM7 peripheral clock enable during + CSleep mode + 5 + 1 + + + TIM12LPEN + TIM12 peripheral clock enable during + CSleep mode + 6 + 1 + + + TIM13LPEN + TIM13 peripheral clock enable during + CSleep mode + 7 + 1 + + + TIM14LPEN + TIM14 peripheral clock enable during + CSleep mode + 8 + 1 + + + LPTIM1LPEN + LPTIM1 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + SPI2LPEN + SPI2 Peripheral Clocks Enable During + CSleep Mode + 14 + 1 + + + SPI3LPEN + SPI3 Peripheral Clocks Enable During + CSleep Mode + 15 + 1 + + + SPDIFRXLPEN + SPDIFRX Peripheral Clocks Enable During + CSleep Mode + 16 + 1 + + + USART2LPEN + USART2 Peripheral Clocks Enable During + CSleep Mode + 17 + 1 + + + USART3LPEN + USART3 Peripheral Clocks Enable During + CSleep Mode + 18 + 1 + + + UART4LPEN + UART4 Peripheral Clocks Enable During + CSleep Mode + 19 + 1 + + + UART5LPEN + UART5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + I2C1LPEN + I2C1 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + I2C2LPEN + I2C2 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + I2C3LPEN + I2C3 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + HDMICECLPEN + HDMI-CEC Peripheral Clocks Enable During + CSleep Mode + 27 + 1 + + + DAC12LPEN + DAC1/2 peripheral clock enable during + CSleep mode + 29 + 1 + + + USART7LPEN + USART7 Peripheral Clocks Enable During + CSleep Mode + 30 + 1 + + + USART8LPEN + USART8 Peripheral Clocks Enable During + CSleep Mode + 31 + 1 + + + + + C1_APB1LLPENR + C1_APB1LLPENR + RCC APB1 Low Sleep Clock + Register + 0x170 + 0x20 + read-write + 0x00000000 + + + TIM2LPEN + TIM2 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM3LPEN + TIM3 peripheral clock enable during + CSleep mode + 1 + 1 + + + TIM4LPEN + TIM4 peripheral clock enable during + CSleep mode + 2 + 1 + + + TIM5LPEN + TIM5 peripheral clock enable during + CSleep mode + 3 + 1 + + + TIM6LPEN + TIM6 peripheral clock enable during + CSleep mode + 4 + 1 + + + TIM7LPEN + TIM7 peripheral clock enable during + CSleep mode + 5 + 1 + + + TIM12LPEN + TIM12 peripheral clock enable during + CSleep mode + 6 + 1 + + + TIM13LPEN + TIM13 peripheral clock enable during + CSleep mode + 7 + 1 + + + TIM14LPEN + TIM14 peripheral clock enable during + CSleep mode + 8 + 1 + + + LPTIM1LPEN + LPTIM1 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + SPI2LPEN + SPI2 Peripheral Clocks Enable During + CSleep Mode + 14 + 1 + + + SPI3LPEN + SPI3 Peripheral Clocks Enable During + CSleep Mode + 15 + 1 + + + SPDIFRXLPEN + SPDIFRX Peripheral Clocks Enable During + CSleep Mode + 16 + 1 + + + USART2LPEN + USART2 Peripheral Clocks Enable During + CSleep Mode + 17 + 1 + + + USART3LPEN + USART3 Peripheral Clocks Enable During + CSleep Mode + 18 + 1 + + + UART4LPEN + UART4 Peripheral Clocks Enable During + CSleep Mode + 19 + 1 + + + UART5LPEN + UART5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + I2C1LPEN + I2C1 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + I2C2LPEN + I2C2 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + I2C3LPEN + I2C3 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + HDMICECLPEN + HDMI-CEC Peripheral Clocks Enable During + CSleep Mode + 27 + 1 + + + DAC12LPEN + DAC1/2 peripheral clock enable during + CSleep mode + 29 + 1 + + + USART7LPEN + USART7 Peripheral Clocks Enable During + CSleep Mode + 30 + 1 + + + USART8LPEN + USART8 Peripheral Clocks Enable During + CSleep Mode + 31 + 1 + + + + + C1_APB1HLPENR + C1_APB1HLPENR + RCC APB1 High Sleep Clock + Register + 0x174 + 0x20 + read-write + 0x00000000 + + + CRSLPEN + Clock Recovery System peripheral clock + enable during CSleep mode + 1 + 1 + + + SWPLPEN + SWPMI Peripheral Clocks Enable During + CSleep Mode + 2 + 1 + + + OPAMPLPEN + OPAMP peripheral clock enable during + CSleep mode + 4 + 1 + + + MDIOSLPEN + MDIOS peripheral clock enable during + CSleep mode + 5 + 1 + + + FDCANLPEN + FDCAN Peripheral Clocks Enable During + CSleep Mode + 8 + 1 + + + + + APB1HLPENR + APB1HLPENR + RCC APB1 High Sleep Clock + Register + 0x114 + 0x20 + read-write + 0x00000000 + + + CRSLPEN + Clock Recovery System peripheral clock + enable during CSleep mode + 1 + 1 + + + SWPLPEN + SWPMI Peripheral Clocks Enable During + CSleep Mode + 2 + 1 + + + OPAMPLPEN + OPAMP peripheral clock enable during + CSleep mode + 4 + 1 + + + MDIOSLPEN + MDIOS peripheral clock enable during + CSleep mode + 5 + 1 + + + FDCANLPEN + FDCAN Peripheral Clocks Enable During + CSleep Mode + 8 + 1 + + + + + APB2LPENR + APB2LPENR + RCC APB2 Sleep Clock Register + 0x118 + 0x20 + read-write + 0x00000000 + + + TIM1LPEN + TIM1 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM8LPEN + TIM8 peripheral clock enable during + CSleep mode + 1 + 1 + + + USART1LPEN + USART1 Peripheral Clocks Enable During + CSleep Mode + 4 + 1 + + + USART6LPEN + USART6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + SPI1LPEN + SPI1 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + SPI4LPEN + SPI4 Peripheral Clocks Enable During + CSleep Mode + 13 + 1 + + + TIM15LPEN + TIM15 peripheral clock enable during + CSleep mode + 16 + 1 + + + TIM16LPEN + TIM16 peripheral clock enable during + CSleep mode + 17 + 1 + + + TIM17LPEN + TIM17 peripheral clock enable during + CSleep mode + 18 + 1 + + + SPI5LPEN + SPI5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + SAI1LPEN + SAI1 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + SAI2LPEN + SAI2 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + SAI3LPEN + SAI3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + DFSDM1LPEN + DFSDM1 Peripheral Clocks Enable During + CSleep Mode + 28 + 1 + + + HRTIMLPEN + HRTIM peripheral clock enable during + CSleep mode + 29 + 1 + + + + + C1_APB2LPENR + C1_APB2LPENR + RCC APB2 Sleep Clock Register + 0x178 + 0x20 + read-write + 0x00000000 + + + TIM1LPEN + TIM1 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM8LPEN + TIM8 peripheral clock enable during + CSleep mode + 1 + 1 + + + USART1LPEN + USART1 Peripheral Clocks Enable During + CSleep Mode + 4 + 1 + + + USART6LPEN + USART6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + SPI1LPEN + SPI1 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + SPI4LPEN + SPI4 Peripheral Clocks Enable During + CSleep Mode + 13 + 1 + + + TIM15LPEN + TIM15 peripheral clock enable during + CSleep mode + 16 + 1 + + + TIM16LPEN + TIM16 peripheral clock enable during + CSleep mode + 17 + 1 + + + TIM17LPEN + TIM17 peripheral clock enable during + CSleep mode + 18 + 1 + + + SPI5LPEN + SPI5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + SAI1LPEN + SAI1 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + SAI2LPEN + SAI2 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + SAI3LPEN + SAI3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + DFSDM1LPEN + DFSDM1 Peripheral Clocks Enable During + CSleep Mode + 28 + 1 + + + HRTIMLPEN + HRTIM peripheral clock enable during + CSleep mode + 29 + 1 + + + + + C1_APB4LPENR + C1_APB4LPENR + RCC APB4 Sleep Clock Register + 0x17C + 0x20 + read-write + 0x00000000 + + + SYSCFGLPEN + SYSCFG peripheral clock enable during + CSleep mode + 1 + 1 + + + LPUART1LPEN + LPUART1 Peripheral Clocks Enable During + CSleep Mode + 3 + 1 + + + SPI6LPEN + SPI6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + I2C4LPEN + I2C4 Peripheral Clocks Enable During + CSleep Mode + 7 + 1 + + + LPTIM2LPEN + LPTIM2 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + LPTIM3LPEN + LPTIM3 Peripheral Clocks Enable During + CSleep Mode + 10 + 1 + + + LPTIM4LPEN + LPTIM4 Peripheral Clocks Enable During + CSleep Mode + 11 + 1 + + + LPTIM5LPEN + LPTIM5 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + COMP12LPEN + COMP1/2 peripheral clock enable during + CSleep mode + 14 + 1 + + + VREFLPEN + VREF peripheral clock enable during + CSleep mode + 15 + 1 + + + RTCAPBLPEN + RTC APB Clock Enable During CSleep + Mode + 16 + 1 + + + SAI4LPEN + SAI4 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + + + APB4LPENR + APB4LPENR + RCC APB4 Sleep Clock Register + 0x11C + 0x20 + read-write + 0x00000000 + + + SYSCFGLPEN + SYSCFG peripheral clock enable during + CSleep mode + 1 + 1 + + + LPUART1LPEN + LPUART1 Peripheral Clocks Enable During + CSleep Mode + 3 + 1 + + + SPI6LPEN + SPI6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + I2C4LPEN + I2C4 Peripheral Clocks Enable During + CSleep Mode + 7 + 1 + + + LPTIM2LPEN + LPTIM2 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + LPTIM3LPEN + LPTIM3 Peripheral Clocks Enable During + CSleep Mode + 10 + 1 + + + LPTIM4LPEN + LPTIM4 Peripheral Clocks Enable During + CSleep Mode + 11 + 1 + + + LPTIM5LPEN + LPTIM5 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + COMP12LPEN + COMP1/2 peripheral clock enable during + CSleep mode + 14 + 1 + + + VREFLPEN + VREF peripheral clock enable during + CSleep mode + 15 + 1 + + + RTCAPBLPEN + RTC APB Clock Enable During CSleep + Mode + 16 + 1 + + + SAI4LPEN + SAI4 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + + + + + LPTIM1 + Low power timer + LPTIM + 0x40002400 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIM1 global interrupt + 93 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + LPTIM Enable + 0 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + COUNTRST + Counter reset + 3 + 1 + + + RSTARE + Reset after read enable + 4 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + CFGR2 + CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + LPTIM Input 1 selection + 0 + 2 + + + IN2SEL + LPTIM Input 2 selection + 4 + 2 + + + + + + + LPTIM2 + 0x58002400 + + LPTIM2 + LPTIM2 timer interrupt + 138 + + + + LPTIM3 + Low power timer + LPTIM + 0x58002800 + + 0x0 + 0x400 + registers + + + LPTIM3 + LPTIM2 timer interrupt + 139 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + LPTIM Enable + 0 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + COUNTRST + Counter reset + 3 + 1 + + + RSTARE + Reset after read enable + 4 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + CFGR2 + CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + LPTIM Input 1 selection + 0 + 2 + + + + + + + LPTIM4 + 0x58002C00 + + LPTIM4 + LPTIM2 timer interrupt + 140 + + + + LPTIM5 + 0x58003000 + + LPTIM5 + LPTIM2 timer interrupt + 141 + + + + LPUART1 + LPUART1 + LPUART + 0x58000C00 + + 0x0 + 0x400 + registers + + + LPUART + LPUART global interrupt + 142 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFIFO Full interrupt + enable + 31 + 1 + + + TXFEIE + TXFIFO empty interrupt + enable + 30 + 1 + + + FIFOEN + FIFO mode enable + 29 + 1 + + + M1 + Word length + 28 + 1 + + + DEAT + Driver Enable assertion + time + 21 + 5 + + + DEDT + Driver Enable deassertion + time + 16 + 5 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD + Address of the USART node + 24 + 8 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + DATAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFIFO threshold + configuration + 29 + 3 + + + RXFTIE + RXFIFO threshold interrupt + enable + 28 + 1 + + + RXFTCFG + Receive FIFO threshold + configuration + 25 + 3 + + + TXFTIE + TXFIFO threshold interrupt + enable + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR + 0 + 20 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFIFO threshold flag + 27 + 1 + + + RXFT + RXFIFO threshold flag + 26 + 1 + + + RXFF + RXFIFO Full + 24 + 1 + + + TXFE + TXFIFO Empty + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NE + NE + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + Prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + Clock prescaler + 0 + 4 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x58000400 + + 0x0 + 0x400 + registers + + + + PMCR + PMCR + peripheral mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + I2C1FMP + I2C1 Fm+ + 0 + 1 + + + I2C2FMP + I2C2 Fm+ + 1 + 1 + + + I2C3FMP + I2C3 Fm+ + 2 + 1 + + + I2C4FMP + I2C4 Fm+ + 3 + 1 + + + PB6FMP + PB(6) Fm+ + 4 + 1 + + + PB7FMP + PB(7) Fast Mode Plus + 5 + 1 + + + PB8FMP + PB(8) Fast Mode Plus + 6 + 1 + + + PB9FMP + PB(9) Fm+ + 7 + 1 + + + BOOSTE + Booster Enable + 8 + 1 + + + EPIS + Ethernet PHY Interface + Selection + 21 + 3 + + + PA0SO + PA0 Switch Open + 24 + 1 + + + PA1SO + PA1 Switch Open + 25 + 1 + + + PC2SO + PC2 Switch Open + 26 + 1 + + + PC3SO + PC3 Switch Open + 27 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to + 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to + 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to + 15) + 0 + 4 + + + + + CCCSR + CCCSR + compensation cell control/status + register + 0x20 + 0x20 + read-write + 0x00000000 + + + EN + enable + 0 + 1 + + + CS + Code selection + 1 + 1 + + + READY + Compensation cell ready + flag + 8 + 1 + + + HSLV + High-speed at low-voltage + 16 + 1 + + + + + CCVR + CCVR + SYSCFG compensation cell value + register + 0x24 + 0x20 + read-only + 0x00000000 + + + NCV + NMOS compensation value + 0 + 4 + + + PCV + PMOS compensation value + 4 + 4 + + + + + CCCR + CCCR + SYSCFG compensation cell code + register + 0x28 + 0x20 + read-write + 0x00000000 + + + NCC + NMOS compensation code + 0 + 4 + + + PCC + PMOS compensation code + 4 + 4 + + + + + PKGR + PKGR + SYSCFG package register + 0x124 + 0x20 + read-only + 0x00000000 + + + PKG + Package + 0 + 4 + + + + + UR0 + UR0 + SYSCFG user register 0 + 0x300 + 0x20 + read-only + 0x00000000 + + + BKS + Bank Swap + 0 + 1 + + + RDP + Readout protection + 16 + 8 + + + + + UR2 + UR2 + SYSCFG user register 2 + 0x308 + 0x20 + read-write + 0x00000000 + + + BORH + BOR_LVL Brownout Reset Threshold + Level + 0 + 2 + + + BOOT_ADD0 + Boot Address 0 + 16 + 16 + + + + + UR3 + UR3 + SYSCFG user register 3 + 0x30C + 0x20 + read-write + 0x00000000 + + + BOOT_ADD1 + Boot Address 1 + 16 + 16 + + + + + UR4 + UR4 + SYSCFG user register 4 + 0x310 + 0x20 + read-only + 0x00000000 + + + MEPAD_1 + Mass Erase Protected Area Disabled for + bank 1 + 16 + 1 + + + + + UR5 + UR5 + SYSCFG user register 5 + 0x314 + 0x20 + read-only + 0x00000000 + + + MESAD_1 + Mass erase secured area disabled for + bank 1 + 0 + 1 + + + WRPN_1 + Write protection for flash bank + 1 + 16 + 8 + + + + + UR6 + UR6 + SYSCFG user register 6 + 0x318 + 0x20 + read-only + 0x00000000 + + + PA_BEG_1 + Protected area start address for bank + 1 + 0 + 12 + + + PA_END_1 + Protected area end address for bank + 1 + 16 + 12 + + + + + UR7 + UR7 + SYSCFG user register 7 + 0x31C + 0x20 + read-only + 0x00000000 + + + SA_BEG_1 + Secured area start address for bank + 1 + 0 + 12 + + + SA_END_1 + Secured area end address for bank + 1 + 16 + 12 + + + + + UR8 + UR8 + SYSCFG user register 8 + 0x320 + 0x20 + read-only + 0x00000000 + + + MEPAD_2 + Mass erase protected area disabled for + bank 2 + 0 + 1 + + + MESAD_2 + Mass erase secured area disabled for + bank 2 + 16 + 1 + + + + + UR9 + UR9 + SYSCFG user register 9 + 0x324 + 0x20 + read-only + 0x00000000 + + + WRPN_2 + Write protection for flash bank + 2 + 0 + 8 + + + PA_BEG_2 + Protected area start address for bank + 2 + 16 + 12 + + + + + UR10 + UR10 + SYSCFG user register 10 + 0x328 + 0x20 + read-only + 0x00000000 + + + PA_END_2 + Protected area end address for bank + 2 + 0 + 12 + + + SA_BEG_2 + Secured area start address for bank + 2 + 16 + 12 + + + + + UR11 + UR11 + SYSCFG user register 11 + 0x32C + 0x20 + read-only + 0x00000000 + + + SA_END_2 + Secured area end address for bank + 2 + 0 + 12 + + + IWDG1M + Independent Watchdog 1 + mode + 16 + 1 + + + + + UR12 + UR12 + SYSCFG user register 12 + 0x330 + 0x20 + read-only + 0x00000000 + + + SECURE + Secure mode + 16 + 1 + + + + + UR13 + UR13 + SYSCFG user register 13 + 0x334 + 0x20 + read-only + 0x00000000 + + + SDRS + Secured DTCM RAM Size + 0 + 2 + + + D1SBRST + D1 Standby reset + 16 + 1 + + + + + UR14 + UR14 + SYSCFG user register 14 + 0x338 + 0x20 + read-write + 0x00000000 + + + D1STPRST + D1 Stop Reset + 0 + 1 + + + + + UR15 + UR15 + SYSCFG user register 15 + 0x33C + 0x20 + read-only + 0x00000000 + + + FZIWDGSTB + Freeze independent watchdog in Standby + mode + 16 + 1 + + + + + UR16 + UR16 + SYSCFG user register 16 + 0x340 + 0x20 + read-only + 0x00000000 + + + FZIWDGSTP + Freeze independent watchdog in Stop + mode + 0 + 1 + + + PKP + Private key programmed + 16 + 1 + + + + + UR17 + UR17 + SYSCFG user register 17 + 0x344 + 0x20 + read-only + 0x00000000 + + + IO_HSLV + I/O high speed / low + voltage + 0 + 1 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x58000000 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD through EXTI line + 1 + + + EXTI0 + EXTI Line 0 interrupt + 6 + + + EXTI1 + EXTI Line 1 interrupt + 7 + + + EXTI2 + EXTI Line 2 interrupt + 8 + + + EXTI3 + EXTI Line 3interrupt + 9 + + + EXTI4 + EXTI Line 4interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + cm7_sev_it + Arm® + Cortex®-M7 Send + 64 + + + WKUP + WKUP1 to WKUP6 pins + 149 + + + HOLD_CORE + CPU2 hold + 148 + + + + RTSR1 + RTSR1 + EXTI rising trigger selection + register + 0x0 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + TR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + TR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + TR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + TR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + TR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + TR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + TR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + TR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + TR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + TR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + TR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + TR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + TR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + TR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + TR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + TR16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + TR17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + TR18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + TR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + TR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + TR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + + + FTSR1 + FTSR1 + EXTI falling trigger selection + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + TR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + TR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + TR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + TR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + TR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + TR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + TR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + TR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + TR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + TR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + TR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + TR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + TR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + TR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + TR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + TR16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + TR17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + TR18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + TR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + TR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + TR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + + + SWIER1 + SWIER1 + EXTI software interrupt event + register + 0x8 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + SWIER1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + SWIER2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + SWIER3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + SWIER4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + SWIER5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + SWIER6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + SWIER7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + SWIER8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + SWIER9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + SWIER10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + SWIER11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + SWIER12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + SWIER13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + SWIER14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + SWIER15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + SWIER16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + SWIER17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + SWIER18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + SWIER19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + SWIER20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + SWIER21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + + + D3PMR1 + D3PMR1 + EXTI D3 pending mask register + 0xC + 0x20 + read-write + 0x00000000 + + + MR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + MR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + MR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + MR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + MR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + MR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + MR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + MR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + MR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + MR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + MR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + MR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + MR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + MR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + MR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + MR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + MR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + MR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + MR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + MR25 + Rising trigger event configuration bit + of Configurable Event input + 25 + 1 + + + + + D3PCR1L + D3PCR1L + EXTI D3 pending clear selection register + low + 0x10 + 0x20 + read-write + 0x00000000 + + + PCS0 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 0 + 2 + + + PCS1 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 2 + 2 + + + PCS2 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 4 + 2 + + + PCS3 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 6 + 2 + + + PCS4 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 8 + 2 + + + PCS5 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 10 + 2 + + + PCS6 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 12 + 2 + + + PCS7 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 14 + 2 + + + PCS8 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 16 + 2 + + + PCS9 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 18 + 2 + + + PCS10 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 20 + 2 + + + PCS11 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 22 + 2 + + + PCS12 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 24 + 2 + + + PCS13 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 26 + 2 + + + PCS14 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 28 + 2 + + + PCS15 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 30 + 2 + + + + + D3PCR1H + D3PCR1H + EXTI D3 pending clear selection register + high + 0x14 + 0x20 + read-write + 0x00000000 + + + PCS19 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 6 + 2 + + + PCS20 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 8 + 2 + + + PCS21 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 10 + 2 + + + PCS25 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 18 + 2 + + + + + RTSR2 + RTSR2 + EXTI rising trigger selection + register + 0x20 + 0x20 + read-write + 0x00000000 + + + TR49 + Rising trigger event configuration bit + of Configurable Event input x+32 + 17 + 1 + + + TR51 + Rising trigger event configuration bit + of Configurable Event input x+32 + 19 + 1 + + + + + FTSR2 + FTSR2 + EXTI falling trigger selection + register + 0x24 + 0x20 + read-write + 0x00000000 + + + TR49 + Falling trigger event configuration bit + of Configurable Event input x+32 + 17 + 1 + + + TR51 + Falling trigger event configuration bit + of Configurable Event input x+32 + 19 + 1 + + + + + SWIER2 + SWIER2 + EXTI software interrupt event + register + 0x28 + 0x20 + read-write + 0x00000000 + + + SWIER49 + Software interrupt on line + x+32 + 17 + 1 + + + SWIER51 + Software interrupt on line + x+32 + 19 + 1 + + + + + D3PMR2 + D3PMR2 + EXTI D3 pending mask register + 0x2C + 0x20 + read-write + 0x00000000 + + + MR34 + D3 Pending Mask on Event input + x+32 + 2 + 1 + + + MR35 + D3 Pending Mask on Event input + x+32 + 3 + 1 + + + MR41 + D3 Pending Mask on Event input + x+32 + 9 + 1 + + + MR48 + D3 Pending Mask on Event input + x+32 + 16 + 1 + + + MR49 + D3 Pending Mask on Event input + x+32 + 17 + 1 + + + MR50 + D3 Pending Mask on Event input + x+32 + 18 + 1 + + + MR51 + D3 Pending Mask on Event input + x+32 + 19 + 1 + + + MR52 + D3 Pending Mask on Event input + x+32 + 20 + 1 + + + MR53 + D3 Pending Mask on Event input + x+32 + 21 + 1 + + + + + D3PCR2L + D3PCR2L + EXTI D3 pending clear selection register + low + 0x30 + 0x20 + read-write + 0x00000000 + + + PCS35 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+64)/2) + 6 + 2 + + + PCS34 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+64)/2) + 4 + 2 + + + PCS41 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+64)/2) + 18 + 2 + + + + + D3PCR2H + D3PCR2H + EXTI D3 pending clear selection register + high + 0x34 + 0x20 + read-write + 0x00000000 + + + PCS48 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 0 + 2 + + + PCS49 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 2 + 2 + + + PCS50 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 4 + 2 + + + PCS51 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 6 + 2 + + + PCS52 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 8 + 2 + + + PCS53 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 10 + 2 + + + + + RTSR3 + RTSR3 + EXTI rising trigger selection + register + 0x40 + 0x20 + read-write + 0x00000000 + + + TR82 + Rising trigger event configuration bit + of Configurable Event input x+64 + 18 + 1 + + + TR84 + Rising trigger event configuration bit + of Configurable Event input x+64 + 20 + 1 + + + TR85 + Rising trigger event configuration bit + of Configurable Event input x+64 + 21 + 1 + + + TR86 + Rising trigger event configuration bit + of Configurable Event input x+64 + 22 + 1 + + + + + FTSR3 + FTSR3 + EXTI falling trigger selection + register + 0x44 + 0x20 + read-write + 0x00000000 + + + TR82 + Falling trigger event configuration bit + of Configurable Event input x+64 + 18 + 1 + + + TR84 + Falling trigger event configuration bit + of Configurable Event input x+64 + 20 + 1 + + + TR85 + Falling trigger event configuration bit + of Configurable Event input x+64 + 21 + 1 + + + TR86 + Falling trigger event configuration bit + of Configurable Event input x+64 + 22 + 1 + + + + + SWIER3 + SWIER3 + EXTI software interrupt event + register + 0x48 + 0x20 + read-write + 0x00000000 + + + SWIER82 + Software interrupt on line + x+64 + 18 + 1 + + + SWIER84 + Software interrupt on line + x+64 + 20 + 1 + + + SWIER85 + Software interrupt on line + x+64 + 21 + 1 + + + SWIER86 + Software interrupt on line + x+64 + 22 + 1 + + + + + D3PMR3 + D3PMR3 + EXTI D3 pending mask register + 0x4C + 0x20 + read-write + 0x00000000 + + + MR88 + D3 Pending Mask on Event input + x+64 + 24 + 1 + + + + + D3PCR3H + D3PCR3H + EXTI D3 pending clear selection register + high + 0x54 + 0x20 + read-write + 0x00000000 + + + PCS88 + D3 Pending request clear input signal + selection on Event input x= truncate + N+160/2 + 18 + 2 + + + + + CPUIMR1 + CPUIMR1 + EXTI interrupt mask register + 0x80 + 0x20 + read-write + 0xFFC00000 + + + MR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + MR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + MR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + MR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + MR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + MR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + MR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + MR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + MR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + MR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + MR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + MR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + MR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + MR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + MR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + MR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + MR16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + MR17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + MR18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + MR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + MR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + MR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + MR22 + Rising trigger event configuration bit + of Configurable Event input + 22 + 1 + + + MR23 + Rising trigger event configuration bit + of Configurable Event input + 23 + 1 + + + MR24 + Rising trigger event configuration bit + of Configurable Event input + 24 + 1 + + + MR25 + Rising trigger event configuration bit + of Configurable Event input + 25 + 1 + + + MR26 + Rising trigger event configuration bit + of Configurable Event input + 26 + 1 + + + MR27 + Rising trigger event configuration bit + of Configurable Event input + 27 + 1 + + + MR28 + Rising trigger event configuration bit + of Configurable Event input + 28 + 1 + + + MR29 + Rising trigger event configuration bit + of Configurable Event input + 29 + 1 + + + MR30 + Rising trigger event configuration bit + of Configurable Event input + 30 + 1 + + + MR31 + Rising trigger event configuration bit + of Configurable Event input + 31 + 1 + + + + + CPUEMR1 + CPUEMR1 + EXTI event mask register + 0x84 + 0x20 + read-write + 0x00000000 + + + MR0 + CPU Event mask on Event input + x + 0 + 1 + + + MR1 + CPU Event mask on Event input + x + 1 + 1 + + + MR2 + CPU Event mask on Event input + x + 2 + 1 + + + MR3 + CPU Event mask on Event input + x + 3 + 1 + + + MR4 + CPU Event mask on Event input + x + 4 + 1 + + + MR5 + CPU Event mask on Event input + x + 5 + 1 + + + MR6 + CPU Event mask on Event input + x + 6 + 1 + + + MR7 + CPU Event mask on Event input + x + 7 + 1 + + + MR8 + CPU Event mask on Event input + x + 8 + 1 + + + MR9 + CPU Event mask on Event input + x + 9 + 1 + + + MR10 + CPU Event mask on Event input + x + 10 + 1 + + + MR11 + CPU Event mask on Event input + x + 11 + 1 + + + MR12 + CPU Event mask on Event input + x + 12 + 1 + + + MR13 + CPU Event mask on Event input + x + 13 + 1 + + + MR14 + CPU Event mask on Event input + x + 14 + 1 + + + MR15 + CPU Event mask on Event input + x + 15 + 1 + + + MR16 + CPU Event mask on Event input + x + 16 + 1 + + + MR17 + CPU Event mask on Event input + x + 17 + 1 + + + MR18 + CPU Event mask on Event input + x + 18 + 1 + + + MR19 + CPU Event mask on Event input + x + 19 + 1 + + + MR20 + CPU Event mask on Event input + x + 20 + 1 + + + MR21 + CPU Event mask on Event input + x + 21 + 1 + + + MR22 + CPU Event mask on Event input + x + 22 + 1 + + + MR23 + CPU Event mask on Event input + x + 23 + 1 + + + MR24 + CPU Event mask on Event input + x + 24 + 1 + + + MR25 + CPU Event mask on Event input + x + 25 + 1 + + + MR26 + CPU Event mask on Event input + x + 26 + 1 + + + MR27 + CPU Event mask on Event input + x + 27 + 1 + + + MR28 + CPU Event mask on Event input + x + 28 + 1 + + + MR29 + CPU Event mask on Event input + x + 29 + 1 + + + MR30 + CPU Event mask on Event input + x + 30 + 1 + + + MR31 + CPU Event mask on Event input + x + 31 + 1 + + + + + CPUPR1 + CPUPR1 + EXTI pending register + 0x88 + 0x20 + read-write + 0x00000000 + + + PR0 + CPU Event mask on Event input + x + 0 + 1 + + + PR1 + CPU Event mask on Event input + x + 1 + 1 + + + PR2 + CPU Event mask on Event input + x + 2 + 1 + + + PR3 + CPU Event mask on Event input + x + 3 + 1 + + + PR4 + CPU Event mask on Event input + x + 4 + 1 + + + PR5 + CPU Event mask on Event input + x + 5 + 1 + + + PR6 + CPU Event mask on Event input + x + 6 + 1 + + + PR7 + CPU Event mask on Event input + x + 7 + 1 + + + PR8 + CPU Event mask on Event input + x + 8 + 1 + + + PR9 + CPU Event mask on Event input + x + 9 + 1 + + + PR10 + CPU Event mask on Event input + x + 10 + 1 + + + PR11 + CPU Event mask on Event input + x + 11 + 1 + + + PR12 + CPU Event mask on Event input + x + 12 + 1 + + + PR13 + CPU Event mask on Event input + x + 13 + 1 + + + PR14 + CPU Event mask on Event input + x + 14 + 1 + + + PR15 + CPU Event mask on Event input + x + 15 + 1 + + + PR16 + CPU Event mask on Event input + x + 16 + 1 + + + PR17 + CPU Event mask on Event input + x + 17 + 1 + + + PR18 + CPU Event mask on Event input + x + 18 + 1 + + + PR19 + CPU Event mask on Event input + x + 19 + 1 + + + PR20 + CPU Event mask on Event input + x + 20 + 1 + + + PR21 + CPU Event mask on Event input + x + 21 + 1 + + + + + CPUIMR2 + CPUIMR2 + EXTI interrupt mask register + 0x90 + 0x20 + read-write + 0x00000000 + + + MR0 + CPU Interrupt Mask on Direct Event input + x+32 + 0 + 1 + + + MR1 + CPU Interrupt Mask on Direct Event input + x+32 + 1 + 1 + + + MR2 + CPU Interrupt Mask on Direct Event input + x+32 + 2 + 1 + + + MR3 + CPU Interrupt Mask on Direct Event input + x+32 + 3 + 1 + + + MR4 + CPU Interrupt Mask on Direct Event input + x+32 + 4 + 1 + + + MR5 + CPU Interrupt Mask on Direct Event input + x+32 + 5 + 1 + + + MR6 + CPU Interrupt Mask on Direct Event input + x+32 + 6 + 1 + + + MR7 + CPU Interrupt Mask on Direct Event input + x+32 + 7 + 1 + + + MR8 + CPU Interrupt Mask on Direct Event input + x+32 + 8 + 1 + + + MR9 + CPU Interrupt Mask on Direct Event input + x+32 + 9 + 1 + + + MR10 + CPU Interrupt Mask on Direct Event input + x+32 + 10 + 1 + + + MR11 + CPU Interrupt Mask on Direct Event input + x+32 + 11 + 1 + + + MR12 + CPU Interrupt Mask on Direct Event input + x+32 + 12 + 1 + + + MR14 + CPU Interrupt Mask on Direct Event input + x+32 + 14 + 1 + + + MR15 + CPU Interrupt Mask on Direct Event input + x+32 + 15 + 1 + + + MR16 + CPU Interrupt Mask on Direct Event input + x+32 + 16 + 1 + + + MR17 + CPU Interrupt Mask on Direct Event input + x+32 + 17 + 1 + + + MR18 + CPU Interrupt Mask on Direct Event input + x+32 + 18 + 1 + + + MR19 + CPU Interrupt Mask on Direct Event input + x+32 + 19 + 1 + + + MR20 + CPU Interrupt Mask on Direct Event input + x+32 + 20 + 1 + + + MR21 + CPU Interrupt Mask on Direct Event input + x+32 + 21 + 1 + + + MR22 + CPU Interrupt Mask on Direct Event input + x+32 + 22 + 1 + + + MR23 + CPU Interrupt Mask on Direct Event input + x+32 + 23 + 1 + + + MR24 + CPU Interrupt Mask on Direct Event input + x+32 + 24 + 1 + + + MR25 + CPU Interrupt Mask on Direct Event input + x+32 + 25 + 1 + + + MR26 + CPU Interrupt Mask on Direct Event input + x+32 + 26 + 1 + + + MR27 + CPU Interrupt Mask on Direct Event input + x+32 + 27 + 1 + + + MR28 + CPU Interrupt Mask on Direct Event input + x+32 + 28 + 1 + + + MR29 + CPU Interrupt Mask on Direct Event input + x+32 + 29 + 1 + + + MR30 + CPU Interrupt Mask on Direct Event input + x+32 + 30 + 1 + + + MR31 + CPU Interrupt Mask on Direct Event input + x+32 + 31 + 1 + + + + + CPUEMR2 + CPUEMR2 + EXTI event mask register + 0x94 + 0x20 + read-write + 0x00000000 + + + MR32 + CPU Interrupt Mask on Direct Event input + x+32 + 0 + 1 + + + MR33 + CPU Interrupt Mask on Direct Event input + x+32 + 1 + 1 + + + MR34 + CPU Interrupt Mask on Direct Event input + x+32 + 2 + 1 + + + MR35 + CPU Interrupt Mask on Direct Event input + x+32 + 3 + 1 + + + MR36 + CPU Interrupt Mask on Direct Event input + x+32 + 4 + 1 + + + MR37 + CPU Interrupt Mask on Direct Event input + x+32 + 5 + 1 + + + MR38 + CPU Interrupt Mask on Direct Event input + x+32 + 6 + 1 + + + MR39 + CPU Interrupt Mask on Direct Event input + x+32 + 7 + 1 + + + MR40 + CPU Interrupt Mask on Direct Event input + x+32 + 8 + 1 + + + MR41 + CPU Interrupt Mask on Direct Event input + x+32 + 9 + 1 + + + MR42 + CPU Interrupt Mask on Direct Event input + x+32 + 10 + 1 + + + MR43 + CPU Interrupt Mask on Direct Event input + x+32 + 11 + 1 + + + MR44 + CPU Interrupt Mask on Direct Event input + x+32 + 12 + 1 + + + MR46 + CPU Interrupt Mask on Direct Event input + x+32 + 14 + 1 + + + MR47 + CPU Interrupt Mask on Direct Event input + x+32 + 15 + 1 + + + MR48 + CPU Interrupt Mask on Direct Event input + x+32 + 16 + 1 + + + MR49 + CPU Interrupt Mask on Direct Event input + x+32 + 17 + 1 + + + MR50 + CPU Interrupt Mask on Direct Event input + x+32 + 18 + 1 + + + MR51 + CPU Interrupt Mask on Direct Event input + x+32 + 19 + 1 + + + MR52 + CPU Interrupt Mask on Direct Event input + x+32 + 20 + 1 + + + MR53 + CPU Interrupt Mask on Direct Event input + x+32 + 21 + 1 + + + MR54 + CPU Interrupt Mask on Direct Event input + x+32 + 22 + 1 + + + MR55 + CPU Interrupt Mask on Direct Event input + x+32 + 23 + 1 + + + MR56 + CPU Interrupt Mask on Direct Event input + x+32 + 24 + 1 + + + MR57 + CPU Interrupt Mask on Direct Event input + x+32 + 25 + 1 + + + MR58 + CPU Interrupt Mask on Direct Event input + x+32 + 26 + 1 + + + MR59 + CPU Interrupt Mask on Direct Event input + x+32 + 27 + 1 + + + MR60 + CPU Interrupt Mask on Direct Event input + x+32 + 28 + 1 + + + MR61 + CPU Interrupt Mask on Direct Event input + x+32 + 29 + 1 + + + MR62 + CPU Interrupt Mask on Direct Event input + x+32 + 30 + 1 + + + MR63 + CPU Interrupt Mask on Direct Event input + x+32 + 31 + 1 + + + + + CPUPR2 + CPUPR2 + EXTI pending register + 0x98 + 0x20 + read-only + 0x00000000 + + + PR49 + Configurable event inputs x+32 Pending + bit + 17 + 1 + + + PR51 + Configurable event inputs x+32 Pending + bit + 19 + 1 + + + + + CPUIMR3 + CPUIMR3 + EXTI interrupt mask register + 0xA0 + 0x20 + read-only + 0x00000000 + + + MR64 + CPU Interrupt Mask on Direct Event input + x+64 + 0 + 1 + + + MR65 + CPU Interrupt Mask on Direct Event input + x+64 + 1 + 1 + + + MR66 + CPU Interrupt Mask on Direct Event input + x+64 + 2 + 1 + + + MR67 + CPU Interrupt Mask on Direct Event input + x+64 + 3 + 1 + + + MR68 + CPU Interrupt Mask on Direct Event input + x+64 + 4 + 1 + + + MR69 + CPU Interrupt Mask on Direct Event input + x+64 + 5 + 1 + + + MR70 + CPU Interrupt Mask on Direct Event input + x+64 + 6 + 1 + + + MR71 + CPU Interrupt Mask on Direct Event input + x+64 + 7 + 1 + + + MR72 + CPU Interrupt Mask on Direct Event input + x+64 + 8 + 1 + + + MR73 + CPU Interrupt Mask on Direct Event input + x+64 + 9 + 1 + + + MR74 + CPU Interrupt Mask on Direct Event input + x+64 + 10 + 1 + + + MR75 + CPU Interrupt Mask on Direct Event input + x+64 + 11 + 1 + + + MR76 + CPU Interrupt Mask on Direct Event input + x+64 + 12 + 1 + + + MR77 + CPU Interrupt Mask on Direct Event input + x+64 + 13 + 1 + + + MR78 + CPU Interrupt Mask on Direct Event input + x+64 + 14 + 1 + + + MR79 + CPU Interrupt Mask on Direct Event input + x+64 + 15 + 1 + + + MR80 + CPU Interrupt Mask on Direct Event input + x+64 + 16 + 1 + + + MR82 + CPU Interrupt Mask on Direct Event input + x+64 + 18 + 1 + + + MR84 + CPU Interrupt Mask on Direct Event input + x+64 + 20 + 1 + + + MR85 + CPU Interrupt Mask on Direct Event input + x+64 + 21 + 1 + + + MR86 + CPU Interrupt Mask on Direct Event input + x+64 + 22 + 1 + + + MR87 + CPU Interrupt Mask on Direct Event input + x+64 + 23 + 1 + + + MR88 + CPU Interrupt Mask on Direct Event input + x+64 + 24 + 1 + + + + + CPUEMR3 + CPUEMR3 + EXTI event mask register + 0xA4 + 0x20 + read-only + 0x00000000 + + + MR64 + CPU Event mask on Event input + x+64 + 0 + 1 + + + MR65 + CPU Event mask on Event input + x+64 + 1 + 1 + + + MR66 + CPU Event mask on Event input + x+64 + 2 + 1 + + + MR67 + CPU Event mask on Event input + x+64 + 3 + 1 + + + MR68 + CPU Event mask on Event input + x+64 + 4 + 1 + + + MR69 + CPU Event mask on Event input + x+64 + 5 + 1 + + + MR70 + CPU Event mask on Event input + x+64 + 6 + 1 + + + MR71 + CPU Event mask on Event input + x+64 + 7 + 1 + + + MR72 + CPU Event mask on Event input + x+64 + 8 + 1 + + + MR73 + CPU Event mask on Event input + x+64 + 9 + 1 + + + MR74 + CPU Event mask on Event input + x+64 + 10 + 1 + + + MR75 + CPU Event mask on Event input + x+64 + 11 + 1 + + + MR76 + CPU Event mask on Event input + x+64 + 12 + 1 + + + MR77 + CPU Event mask on Event input + x+64 + 13 + 1 + + + MR78 + CPU Event mask on Event input + x+64 + 14 + 1 + + + MR79 + CPU Event mask on Event input + x+64 + 15 + 1 + + + MR80 + CPU Event mask on Event input + x+64 + 16 + 1 + + + MR82 + CPU Event mask on Event input + x+64 + 18 + 1 + + + MR84 + CPU Event mask on Event input + x+64 + 20 + 1 + + + MR85 + CPU Event mask on Event input + x+64 + 21 + 1 + + + MR86 + CPU Event mask on Event input + x+64 + 22 + 1 + + + MR87 + CPU Event mask on Event input + x+64 + 23 + 1 + + + MR88 + CPU Event mask on Event input + x+64 + 24 + 1 + + + + + CPUPR3 + CPUPR3 + EXTI pending register + 0xA8 + 0x20 + read-only + 0x00000000 + + + PR82 + Configurable event inputs x+64 Pending + bit + 18 + 1 + + + PR84 + Configurable event inputs x+64 Pending + bit + 20 + 1 + + + PR85 + Configurable event inputs x+64 Pending + bit + 21 + 1 + + + PR86 + Configurable event inputs x+64 Pending + bit + 22 + 1 + + + + + + + DELAY_Block_SDMMC1 + DELAY_Block_SDMMC1 + DLYB + 0x52008000 + + 0x0 + 0x100 + registers + + + + CR + CR + DLYB control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DEN + Delay block enable bit + 0 + 1 + + + SEN + Sampler length enable bit + 1 + 1 + + + + + CFGR + CFGR + DLYB configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + SEL + Select the phase for the Output + clock + 0 + 4 + + + UNIT + Delay Defines the delay of a Unit delay + cell + 8 + 7 + + + LNG + Delay line length value + 16 + 12 + + + LNGF + Length valid flag + 31 + 1 + + + + + + + DELAY_Block_QUADSPI + 0x52006000 + + + DELAY_Block_SDMMC2 + 0x48022800 + + + Flash + Flash + Flash + 0x52002000 + + 0x0 + 0x1000 + registers + + + FLASH + Flash memory + 4 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Read latency + 0 + 3 + + + WRHIGHFREQ + Flash signal delay + 4 + 2 + + + + + ACR_ + ACR_ + Access control register + 0x100 + 0x20 + read-write + 0x00000000 + + + LATENCY + Read latency + 0 + 3 + + + WRHIGHFREQ + Flash signal delay + 4 + 2 + + + + + KEYR1 + KEYR1 + FLASH key register for bank 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + KEYR1 + Bank 1 access configuration unlock + key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + FLASH option key register + 0x8 + 0x20 + read-write + 0x00000000 + + + OPTKEYR + Unlock key option bytes + 0 + 32 + + + + + OPTKEYR_ + OPTKEYR_ + FLASH option key register + 0x108 + 0x20 + read-write + 0x00000000 + + + OPTKEYR + Unlock key option bytes + 0 + 32 + + + + + CR1 + CR1 + FLASH control register for bank + 1 + 0xC + 0x20 + read-write + 0x00000000 + + + LOCK1 + Bank 1 configuration lock + bit + 0 + 1 + + + PG1 + Bank 1 program enable bit + 1 + 1 + + + SER1 + Bank 1 sector erase + request + 2 + 1 + + + BER1 + Bank 1 erase request + 3 + 1 + + + PSIZE1 + Bank 1 program size + 4 + 2 + + + FW1 + Bank 1 write forcing control + bit + 6 + 1 + + + START1 + Bank 1 bank or sector erase start + control bit + 7 + 1 + + + SNB1 + Bank 1 sector erase selection + number + 8 + 3 + + + CRC_EN + Bank 1 CRC control bit + 15 + 1 + + + EOPIE1 + Bank 1 end-of-program interrupt control + bit + 16 + 1 + + + WRPERRIE1 + Bank 1 write protection error interrupt + enable bit + 17 + 1 + + + PGSERRIE1 + Bank 1 programming sequence error + interrupt enable bit + 18 + 1 + + + STRBERRIE1 + Bank 1 strobe error interrupt enable + bit + 19 + 1 + + + INCERRIE1 + Bank 1 inconsistency error interrupt + enable bit + 21 + 1 + + + OPERRIE1 + Bank 1 write/erase error interrupt + enable bit + 22 + 1 + + + RDPERRIE1 + Bank 1 read protection error interrupt + enable bit + 23 + 1 + + + RDSERRIE1 + Bank 1 secure error interrupt enable + bit + 24 + 1 + + + SNECCERRIE1 + Bank 1 ECC single correction error + interrupt enable bit + 25 + 1 + + + DBECCERRIE1 + Bank 1 ECC double detection error + interrupt enable bit + 26 + 1 + + + CRCENDIE1 + Bank 1 end of CRC calculation interrupt + enable bit + 27 + 1 + + + + + SR1 + SR1 + FLASH status register for bank + 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + BSY1 + Bank 1 ongoing program + flag + 0 + 1 + + + WBNE1 + Bank 1 write buffer not empty + flag + 1 + 1 + + + QW1 + Bank 1 wait queue flag + 2 + 1 + + + CRC_BUSY1 + Bank 1 CRC busy flag + 3 + 1 + + + EOP1 + Bank 1 end-of-program flag + 16 + 1 + + + WRPERR1 + Bank 1 write protection error + flag + 17 + 1 + + + PGSERR1 + Bank 1 programming sequence error + flag + 18 + 1 + + + STRBERR1 + Bank 1 strobe error flag + 19 + 1 + + + INCERR1 + Bank 1 inconsistency error + flag + 21 + 1 + + + OPERR1 + Bank 1 write/erase error + flag + 22 + 1 + + + RDPERR1 + Bank 1 read protection error + flag + 23 + 1 + + + RDSERR1 + Bank 1 secure error flag + 24 + 1 + + + SNECCERR11 + Bank 1 single correction error + flag + 25 + 1 + + + DBECCERR1 + Bank 1 ECC double detection error + flag + 26 + 1 + + + CRCEND1 + Bank 1 CRC-complete flag + 27 + 1 + + + + + CCR1 + CCR1 + FLASH clear control register for bank + 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + CLR_EOP1 + Bank 1 EOP1 flag clear bit + 16 + 1 + + + CLR_WRPERR1 + Bank 1 WRPERR1 flag clear + bit + 17 + 1 + + + CLR_PGSERR1 + Bank 1 PGSERR1 flag clear + bi + 18 + 1 + + + CLR_STRBERR1 + Bank 1 STRBERR1 flag clear + bit + 19 + 1 + + + CLR_INCERR1 + Bank 1 INCERR1 flag clear + bit + 21 + 1 + + + CLR_OPERR1 + Bank 1 OPERR1 flag clear + bit + 22 + 1 + + + CLR_RDPERR1 + Bank 1 RDPERR1 flag clear + bit + 23 + 1 + + + CLR_RDSERR1 + Bank 1 RDSERR1 flag clear + bit + 24 + 1 + + + CLR_SNECCERR1 + Bank 1 SNECCERR1 flag clear + bit + 25 + 1 + + + CLR_DBECCERR1 + Bank 1 DBECCERR1 flag clear + bit + 26 + 1 + + + CLR_CRCEND1 + Bank 1 CRCEND1 flag clear + bit + 27 + 1 + + + + + OPTCR + OPTCR + FLASH option control register + 0x18 + 0x20 + read-write + 0x00000000 + + + OPTLOCK + FLASH_OPTCR lock option configuration + bit + 0 + 1 + + + OPTSTART + Option byte start change option + configuration bit + 1 + 1 + + + MER + Flash mass erase enable + bit + 4 + 1 + + + OPTCHANGEERRIE + Option byte change error interrupt + enable bit + 30 + 1 + + + SWAP_BANK + Bank swapping configuration + bit + 31 + 1 + + + + + OPTCR_ + OPTCR_ + FLASH option control register + 0x118 + 0x20 + read-write + 0x00000000 + + + OPTLOCK + FLASH_OPTCR lock option configuration + bit + 0 + 1 + + + OPTSTART + Option byte start change option + configuration bit + 1 + 1 + + + MER + Flash mass erase enable + bit + 4 + 1 + + + OPTCHANGEERRIE + Option byte change error interrupt + enable bit + 30 + 1 + + + SWAP_BANK + Bank swapping configuration + bit + 31 + 1 + + + + + OPTSR_CUR_ + OPTSR_CUR_ + FLASH option status register + 0x11C + 0x20 + read-write + 0x00000000 + + + OPT_BUSY + Option byte change ongoing + flag + 0 + 1 + + + BOR_LEV + Brownout level option status + bit + 2 + 2 + + + IWDG1_HW + IWDG1 control option status + bit + 4 + 1 + + + nRST_STOP_D1 + D1 DStop entry reset option status + bit + 6 + 1 + + + nRST_STBY_D1 + D1 DStandby entry reset option status + bit + 7 + 1 + + + RDP + Readout protection level option status + byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option status + bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option status + bit + 18 + 1 + + + ST_RAM_SIZE + DTCM RAM size option + status + 19 + 2 + + + SECURITY + Security enable option status + bit + 21 + 1 + + + RSS1 + User option bit 1 + 26 + 1 + + + PERSO_OK + Device personalization status + bit + 28 + 1 + + + IO_HSLV + I/O high-speed at low-voltage status bit + (PRODUCT_BELOW_25V) + 29 + 1 + + + OPTCHANGEERR + Option byte change error + flag + 30 + 1 + + + SWAP_BANK_OPT + Bank swapping option status + bit + 31 + 1 + + + + + OPTSR_CUR + OPTSR_CUR + FLASH option status register + 0x1C + 0x20 + read-write + 0x00000000 + + + OPT_BUSY + Option byte change ongoing + flag + 0 + 1 + + + BOR_LEV + Brownout level option status + bit + 2 + 2 + + + IWDG1_HW + IWDG1 control option status + bit + 4 + 1 + + + nRST_STOP_D1 + D1 DStop entry reset option status + bit + 6 + 1 + + + nRST_STBY_D1 + D1 DStandby entry reset option status + bit + 7 + 1 + + + RDP + Readout protection level option status + byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option status + bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option status + bit + 18 + 1 + + + ST_RAM_SIZE + DTCM RAM size option + status + 19 + 2 + + + SECURITY + Security enable option status + bit + 21 + 1 + + + RSS1 + User option bit 1 + 26 + 1 + + + PERSO_OK + Device personalization status + bit + 28 + 1 + + + IO_HSLV + I/O high-speed at low-voltage status bit + (PRODUCT_BELOW_25V) + 29 + 1 + + + OPTCHANGEERR + Option byte change error + flag + 30 + 1 + + + SWAP_BANK_OPT + Bank swapping option status + bit + 31 + 1 + + + + + OPTSR_PRG + OPTSR_PRG + FLASH option status register + 0x20 + 0x20 + read-write + 0x00000000 + + + BOR_LEV + BOR reset level option configuration + bits + 2 + 2 + + + IWDG1_HW + IWDG1 option configuration + bit + 4 + 1 + + + nRST_STOP_D1 + Option byte erase after D1 DStop option + configuration bit + 6 + 1 + + + nRST_STBY_D1 + Option byte erase after D1 DStandby + option configuration bit + 7 + 1 + + + RDP + Readout protection level option + configuration byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option + configuration bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option + configuration bit + 18 + 1 + + + ST_RAM_SIZE + DTCM size select option configuration + bits + 19 + 2 + + + SECURITY + Security option configuration + bit + 21 + 1 + + + RSS1 + User option configuration bit + 1 + 26 + 1 + + + RSS2 + User option configuration bit + 2 + 27 + 1 + + + IO_HSLV + I/O high-speed at low-voltage + (PRODUCT_BELOW_25V) + 29 + 1 + + + SWAP_BANK_OPT + Bank swapping option configuration + bit + 31 + 1 + + + + + OPTSR_PRG_ + OPTSR_PRG_ + FLASH option status register + 0x120 + 0x20 + read-write + 0x00000000 + + + BOR_LEV + BOR reset level option configuration + bits + 2 + 2 + + + IWDG1_HW + IWDG1 option configuration + bit + 4 + 1 + + + nRST_STOP_D1 + Option byte erase after D1 DStop option + configuration bit + 6 + 1 + + + nRST_STBY_D1 + Option byte erase after D1 DStandby + option configuration bit + 7 + 1 + + + RDP + Readout protection level option + configuration byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option + configuration bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option + configuration bit + 18 + 1 + + + ST_RAM_SIZE + DTCM size select option configuration + bits + 19 + 2 + + + SECURITY + Security option configuration + bit + 21 + 1 + + + RSS1 + User option configuration bit + 1 + 26 + 1 + + + RSS2 + User option configuration bit + 2 + 27 + 1 + + + IO_HSLV + I/O high-speed at low-voltage + (PRODUCT_BELOW_25V) + 29 + 1 + + + SWAP_BANK_OPT + Bank swapping option configuration + bit + 31 + 1 + + + + + OPTCCR_ + OPTCCR_ + FLASH option clear control + register + 0x124 + 0x20 + write-only + 0x00000000 + + + CLR_OPTCHANGEERR + OPTCHANGEERR reset bit + 30 + 1 + + + + + OPTCCR + OPTCCR + FLASH option clear control + register + 0x24 + 0x20 + write-only + 0x00000000 + + + CLR_OPTCHANGEERR + OPTCHANGEERR reset bit + 30 + 1 + + + + + PRAR_CUR1 + PRAR_CUR1 + FLASH protection address for bank + 1 + 0x28 + 0x20 + read-only + 0x00000000 + + + PROT_AREA_START1 + Bank 1 lowest PCROP protected + address + 0 + 12 + + + PROT_AREA_END1 + Bank 1 highest PCROP protected + address + 16 + 12 + + + DMEP1 + Bank 1 PCROP protected erase enable + option status bit + 31 + 1 + + + + + PRAR_PRG1 + PRAR_PRG1 + FLASH protection address for bank + 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + PROT_AREA_START1 + Bank 1 lowest PCROP protected address + configuration + 0 + 12 + + + PROT_AREA_END1 + Bank 1 highest PCROP protected address + configuration + 16 + 12 + + + DMEP1 + Bank 1 PCROP protected erase enable + option configuration bit + 31 + 1 + + + + + SCAR_CUR1 + SCAR_CUR1 + FLASH secure address for bank + 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START1 + Bank 1 lowest secure protected + address + 0 + 12 + + + SEC_AREA_END1 + Bank 1 highest secure protected + address + 16 + 12 + + + DMES1 + Bank 1 secure protected erase enable + option status bit + 31 + 1 + + + + + SCAR_PRG1 + SCAR_PRG1 + FLASH secure address for bank + 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START1 + Bank 1 lowest secure protected address + configuration + 0 + 12 + + + SEC_AREA_END1 + Bank 1 highest secure protected address + configuration + 16 + 12 + + + DMES1 + Bank 1 secure protected erase enable + option configuration bit + 31 + 1 + + + + + WPSN_CUR1R + WPSN_CUR1R + FLASH write sector protection for bank + 1 + 0x38 + 0x20 + read-only + 0x00000000 + + + WRPSn1 + Bank 1 sector write protection option + status byte + 0 + 8 + + + + + WPSN_PRG1R + WPSN_PRG1R + FLASH write sector protection for bank + 1 + 0x3C + 0x20 + read-write + 0x00000000 + + + WRPSn1 + Bank 1 sector write protection + configuration byte + 0 + 8 + + + + + BOOT_CURR + BOOT_CURR + FLASH register with boot + address + 0x40 + 0x20 + read-only + 0x00000000 + + + BOOT_ADD0 + Boot address 0 + 0 + 16 + + + BOOT_ADD1 + Boot address 1 + 16 + 16 + + + + + BOOT_PRGR + BOOT_PRGR + FLASH register with boot + address + 0x44 + 0x20 + read-only + 0x00000000 + + + BOOT_ADD0 + Boot address 0 + 0 + 16 + + + BOOT_ADD1 + Boot address 1 + 16 + 16 + + + + + CRCCR1 + CRCCR1 + FLASH CRC control register for bank + 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + CRC_SECT + Bank 1 CRC sector number + 0 + 3 + + + ALL_BANK + Bank 1 CRC select bit + 7 + 1 + + + CRC_BY_SECT + Bank 1 CRC sector mode select + bit + 8 + 1 + + + ADD_SECT + Bank 1 CRC sector select + bit + 9 + 1 + + + CLEAN_SECT + Bank 1 CRC sector list clear + bit + 10 + 1 + + + START_CRC + Bank 1 CRC start bit + 16 + 1 + + + CLEAN_CRC + Bank 1 CRC clear bit + 17 + 1 + + + CRC_BURST + Bank 1 CRC burst size + 20 + 2 + + + + + CRCSADD1R + CRCSADD1R + FLASH CRC start address register for bank + 1 + 0x54 + 0x20 + read-write + 0x00000000 + + + CRC_START_ADDR + CRC start address on bank + 1 + 0 + 32 + + + + + CRCEADD1R + CRCEADD1R + FLASH CRC end address register for bank + 1 + 0x58 + 0x20 + read-write + 0x00000000 + + + CRC_END_ADDR + CRC end address on bank 1 + 0 + 32 + + + + + CRCDATAR + CRCDATAR + FLASH CRC data register + 0x5C + 0x20 + read-write + 0x00000000 + + + CRC_DATA + CRC result + 0 + 32 + + + + + ECC_FA1R + ECC_FA1R + FLASH ECC fail address for bank + 1 + 0x60 + 0x20 + read-only + 0x00000000 + + + FAIL_ECC_ADDR1 + Bank 1 ECC error address + 0 + 15 + + + + + KEYR2 + KEYR2 + FLASH key register for bank 2 + 0x104 + 0x20 + read-only + 0x00000000 + + + KEYR2 + Bank 2 access configuration unlock + key + 0 + 32 + + + + + CR2 + CR2 + FLASH control register for bank + 2 + 0x10C + 0x20 + read-write + 0x00000000 + + + LOCK2 + Bank 2 configuration lock + bit + 0 + 1 + + + PG2 + Bank 2 program enable bit + 1 + 1 + + + SER2 + Bank 2 sector erase + request + 2 + 1 + + + BER2 + Bank 2 erase request + 3 + 1 + + + PSIZE2 + Bank 2 program size + 4 + 2 + + + FW2 + Bank 2 write forcing control + bit + 6 + 1 + + + START2 + Bank 2 bank or sector erase start + control bit + 7 + 1 + + + SNB2 + Bank 2 sector erase selection + number + 8 + 3 + + + CRC_EN + Bank 2 CRC control bit + 15 + 1 + + + EOPIE2 + Bank 2 end-of-program interrupt control + bit + 16 + 1 + + + WRPERRIE2 + Bank 2 write protection error interrupt + enable bit + 17 + 1 + + + PGSERRIE2 + Bank 2 programming sequence error + interrupt enable bit + 18 + 1 + + + STRBERRIE2 + Bank 2 strobe error interrupt enable + bit + 19 + 1 + + + INCERRIE2 + Bank 2 inconsistency error interrupt + enable bit + 21 + 1 + + + OPERRIE2 + Bank 2 write/erase error interrupt + enable bit + 22 + 1 + + + RDPERRIE2 + Bank 2 read protection error interrupt + enable bit + 23 + 1 + + + RDSERRIE2 + Bank 2 secure error interrupt enable + bit + 24 + 1 + + + SNECCERRIE2 + Bank 2 ECC single correction error + interrupt enable bit + 25 + 1 + + + DBECCERRIE2 + Bank 2 ECC double detection error + interrupt enable bit + 26 + 1 + + + CRCENDIE2 + Bank 2 end of CRC calculation interrupt + enable bit + 27 + 1 + + + + + SR2 + SR2 + FLASH status register for bank + 2 + 0x110 + 0x20 + read-write + 0x00000000 + + + BSY2 + Bank 2 ongoing program + flag + 0 + 1 + + + WBNE2 + Bank 2 write buffer not empty + flag + 1 + 1 + + + QW2 + Bank 2 wait queue flag + 2 + 1 + + + CRC_BUSY2 + Bank 2 CRC busy flag + 3 + 1 + + + EOP2 + Bank 2 end-of-program flag + 16 + 1 + + + WRPERR2 + Bank 2 write protection error + flag + 17 + 1 + + + PGSERR2 + Bank 2 programming sequence error + flag + 18 + 1 + + + STRBERR2 + Bank 2 strobe error flag + 19 + 1 + + + INCERR2 + Bank 2 inconsistency error + flag + 21 + 1 + + + OPERR2 + Bank 2 write/erase error + flag + 22 + 1 + + + RDPERR2 + Bank 2 read protection error + flag + 23 + 1 + + + RDSERR2 + Bank 2 secure error flag + 24 + 1 + + + SNECCERR2 + Bank 2 single correction error + flag + 25 + 1 + + + DBECCERR2 + Bank 2 ECC double detection error + flag + 26 + 1 + + + CRCEND2 + Bank 2 CRC-complete flag + 27 + 1 + + + + + CCR2 + CCR2 + FLASH clear control register for bank + 2 + 0x114 + 0x20 + read-write + 0x00000000 + + + CLR_EOP2 + Bank 1 EOP1 flag clear bit + 16 + 1 + + + CLR_WRPERR2 + Bank 2 WRPERR1 flag clear + bit + 17 + 1 + + + CLR_PGSERR2 + Bank 2 PGSERR1 flag clear + bi + 18 + 1 + + + CLR_STRBERR2 + Bank 2 STRBERR1 flag clear + bit + 19 + 1 + + + CLR_INCERR2 + Bank 2 INCERR1 flag clear + bit + 21 + 1 + + + CLR_OPERR2 + Bank 2 OPERR1 flag clear + bit + 22 + 1 + + + CLR_RDPERR2 + Bank 2 RDPERR1 flag clear + bit + 23 + 1 + + + CLR_RDSERR1 + Bank 1 RDSERR1 flag clear + bit + 24 + 1 + + + CLR_SNECCERR2 + Bank 2 SNECCERR1 flag clear + bit + 25 + 1 + + + CLR_DBECCERR1 + Bank 1 DBECCERR1 flag clear + bit + 26 + 1 + + + CLR_CRCEND2 + Bank 2 CRCEND1 flag clear + bit + 27 + 1 + + + + + PRAR_CUR2 + PRAR_CUR2 + FLASH protection address for bank + 1 + 0x128 + 0x20 + read-only + 0x00000000 + + + PROT_AREA_START2 + Bank 2 lowest PCROP protected + address + 0 + 12 + + + PROT_AREA_END2 + Bank 2 highest PCROP protected + address + 16 + 12 + + + DMEP2 + Bank 2 PCROP protected erase enable + option status bit + 31 + 1 + + + + + PRAR_PRG2 + PRAR_PRG2 + FLASH protection address for bank + 2 + PRAR_PRG1 + 0x2C + 0x20 + read-write + 0x00000000 + + + PROT_AREA_START2 + Bank 2 lowest PCROP protected address + configuration + 0 + 12 + + + PROT_AREA_END2 + Bank 2 highest PCROP protected address + configuration + 16 + 12 + + + DMEP2 + Bank 2 PCROP protected erase enable + option configuration bit + 31 + 1 + + + + + SCAR_CUR2 + SCAR_CUR2 + FLASH secure address for bank + 2 + 0x130 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START2 + Bank 2 lowest secure protected + address + 0 + 12 + + + SEC_AREA_END2 + Bank 2 highest secure protected + address + 16 + 12 + + + DMES2 + Bank 2 secure protected erase enable + option status bit + 31 + 1 + + + + + SCAR_PRG2 + SCAR_PRG2 + FLASH secure address for bank + 2 + 0x134 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START2 + Bank 2 lowest secure protected address + configuration + 0 + 12 + + + SEC_AREA_END2 + Bank 2 highest secure protected address + configuration + 16 + 12 + + + DMES2 + Bank 2 secure protected erase enable + option configuration bit + 31 + 1 + + + + + WPSN_CUR2R + WPSN_CUR2R + FLASH write sector protection for bank + 2 + 0x138 + 0x20 + read-only + 0x00000000 + + + WRPSn2 + Bank 2 sector write protection option + status byte + 0 + 8 + + + + + WPSN_PRG2R + WPSN_PRG2R + FLASH write sector protection for bank + 2 + 0x13C + 0x20 + read-write + 0x00000000 + + + WRPSn2 + Bank 2 sector write protection + configuration byte + 0 + 8 + + + + + CRCCR2 + CRCCR2 + FLASH CRC control register for bank + 1 + 0x150 + 0x20 + read-write + 0x00000000 + + + CRC_SECT + Bank 2 CRC sector number + 0 + 3 + + + ALL_BANK + Bank 2 CRC select bit + 7 + 1 + + + CRC_BY_SECT + Bank 2 CRC sector mode select + bit + 8 + 1 + + + ADD_SECT + Bank 2 CRC sector select + bit + 9 + 1 + + + CLEAN_SECT + Bank 2 CRC sector list clear + bit + 10 + 1 + + + START_CRC + Bank 2 CRC start bit + 16 + 1 + + + CLEAN_CRC + Bank 2 CRC clear bit + 17 + 1 + + + CRC_BURST + Bank 2 CRC burst size + 20 + 2 + + + + + CRCSADD2R + CRCSADD2R + FLASH CRC start address register for bank + 2 + 0x154 + 0x20 + read-write + 0x00000000 + + + CRC_START_ADDR + CRC start address on bank + 2 + 0 + 32 + + + + + CRCEADD2R + CRCEADD2R + FLASH CRC end address register for bank + 2 + 0x158 + 0x20 + read-write + 0x00000000 + + + CRC_END_ADDR + CRC end address on bank 2 + 0 + 32 + + + + + ECC_FA2R + ECC_FA2R + FLASH ECC fail address for bank + 2 + 0x160 + 0x20 + read-only + 0x00000000 + + + FAIL_ECC_ADDR2 + Bank 2 ECC error address + 0 + 15 + + + + + + + AXI + AXI interconnect registers + AXI + 0x51000000 + + 0x0 + 0x100000 + registers + + + + AXI_PERIPH_ID_4 + AXI_PERIPH_ID_4 + AXI interconnect - peripheral ID4 + register + 0x1FD0 + 0x20 + read-only + 0x00000004 + + + JEP106CON + JEP106 continuation code + 0 + 4 + + + KCOUNT4 + Register file size + 4 + 4 + + + + + AXI_PERIPH_ID_0 + AXI_PERIPH_ID_0 + AXI interconnect - peripheral ID0 + register + 0x1FE0 + 0x20 + read-only + 0x00000004 + + + PARTNUM + Peripheral part number bits 0 to + 7 + 0 + 8 + + + + + AXI_PERIPH_ID_1 + AXI_PERIPH_ID_1 + AXI interconnect - peripheral ID1 + register + 0x1FE4 + 0x20 + read-only + 0x00000004 + + + PARTNUM + Peripheral part number bits 8 to + 11 + 0 + 4 + + + JEP106I + JEP106 identity bits 0 to + 3 + 4 + 4 + + + + + AXI_PERIPH_ID_2 + AXI_PERIPH_ID_2 + AXI interconnect - peripheral ID2 + register + 0x1FE8 + 0x20 + read-only + 0x00000004 + + + JEP106ID + JEP106 Identity bits 4 to + 6 + 0 + 3 + + + JEDEC + JEP106 code flag + 3 + 1 + + + REVISION + Peripheral revision number + 4 + 4 + + + + + AXI_PERIPH_ID_3 + AXI_PERIPH_ID_3 + AXI interconnect - peripheral ID3 + register + 0x1FEC + 0x20 + read-only + 0x00000004 + + + CUST_MOD_NUM + Customer modification + 0 + 4 + + + REV_AND + Customer version + 4 + 4 + + + + + AXI_COMP_ID_0 + AXI_COMP_ID_0 + AXI interconnect - component ID0 + register + 0x1FF0 + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 0 to 7 + 0 + 8 + + + + + AXI_COMP_ID_1 + AXI_COMP_ID_1 + AXI interconnect - component ID1 + register + 0x1FF4 + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 8 to 11 + 0 + 4 + + + CLASS + Component class + 4 + 4 + + + + + AXI_COMP_ID_2 + AXI_COMP_ID_2 + AXI interconnect - component ID2 + register + 0x1FF8 + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 12 to 19 + 0 + 8 + + + + + AXI_COMP_ID_3 + AXI_COMP_ID_3 + AXI interconnect - component ID3 + register + 0x1FFC + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 20 to 27 + 0 + 8 + + + + + AXI_TARG1_FN_MOD_ISS_BM + AXI_TARG1_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x2008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG2_FN_MOD_ISS_BM + AXI_TARG2_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x3008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG3_FN_MOD_ISS_BM + AXI_TARG3_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x4008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG4_FN_MOD_ISS_BM + AXI_TARG4_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x5008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG5_FN_MOD_ISS_BM + AXI_TARG5_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x6008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG6_FN_MOD_ISS_BM + AXI_TARG6_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x7008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG7_FN_MOD_ISS_BM + AXI_TARG7_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x800C + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG1_FN_MOD2 + AXI_TARG1_FN_MOD2 + AXI interconnect - TARG x bus matrix + functionality 2 register + 0x2024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disable packing of beats to match the + output data width + 0 + 1 + + + + + AXI_TARG2_FN_MOD2 + AXI_TARG2_FN_MOD2 + AXI interconnect - TARG x bus matrix + functionality 2 register + 0x3024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disable packing of beats to match the + output data width + 0 + 1 + + + + + AXI_TARG7_FN_MOD2 + AXI_TARG7_FN_MOD2 + AXI interconnect - TARG x bus matrix + functionality 2 register + 0x8024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disable packing of beats to match the + output data width + 0 + 1 + + + + + AXI_TARG1_FN_MOD_LB + AXI_TARG1_FN_MOD_LB + AXI interconnect - TARG x long burst + functionality modification + 0x202C + 0x20 + read-write + 0x00000004 + + + FN_MOD_LB + Controls burst breaking of long + bursts + 0 + 1 + + + + + AXI_TARG2_FN_MOD_LB + AXI_TARG2_FN_MOD_LB + AXI interconnect - TARG x long burst + functionality modification + 0x302C + 0x20 + read-write + 0x00000004 + + + FN_MOD_LB + Controls burst breaking of long + bursts + 0 + 1 + + + + + AXI_TARG1_FN_MOD + AXI_TARG1_FN_MOD + AXI interconnect - TARG x long burst + functionality modification + 0x2108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override AMIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override AMIB write issuing + capability + 1 + 1 + + + + + AXI_TARG2_FN_MOD + AXI_TARG2_FN_MOD + AXI interconnect - TARG x long burst + functionality modification + 0x3108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override AMIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override AMIB write issuing + capability + 1 + 1 + + + + + AXI_TARG7_FN_MOD + AXI_TARG7_FN_MOD + AXI interconnect - TARG x long burst + functionality modification + 0x8108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override AMIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override AMIB write issuing + capability + 1 + 1 + + + + + AXI_INI1_FN_MOD2 + AXI_INI1_FN_MOD2 + AXI interconnect - INI x functionality + modification 2 register + 0x42024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disables alteration of transactions by + the up-sizer unless required by the + protocol + 0 + 1 + + + + + AXI_INI3_FN_MOD2 + AXI_INI3_FN_MOD2 + AXI interconnect - INI x functionality + modification 2 register + 0x44024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disables alteration of transactions by + the up-sizer unless required by the + protocol + 0 + 1 + + + + + AXI_INI1_FN_MOD_AHB + AXI_INI1_FN_MOD_AHB + AXI interconnect - INI x AHB functionality + modification register + 0x42028 + 0x20 + read-write + 0x00000004 + + + RD_INC_OVERRIDE + Converts all AHB-Lite write transactions + to a series of single beat AXI + 0 + 1 + + + WR_INC_OVERRIDE + Converts all AHB-Lite read transactions + to a series of single beat AXI + 1 + 1 + + + + + AXI_INI3_FN_MOD_AHB + AXI_INI3_FN_MOD_AHB + AXI interconnect - INI x AHB functionality + modification register + 0x44028 + 0x20 + read-write + 0x00000004 + + + RD_INC_OVERRIDE + Converts all AHB-Lite write transactions + to a series of single beat AXI + 0 + 1 + + + WR_INC_OVERRIDE + Converts all AHB-Lite read transactions + to a series of single beat AXI + 1 + 1 + + + + + AXI_INI1_READ_QOS + AXI_INI1_READ_QOS + AXI interconnect - INI x read QoS + register + 0x42100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI2_READ_QOS + AXI_INI2_READ_QOS + AXI interconnect - INI x read QoS + register + 0x43100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI3_READ_QOS + AXI_INI3_READ_QOS + AXI interconnect - INI x read QoS + register + 0x44100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI4_READ_QOS + AXI_INI4_READ_QOS + AXI interconnect - INI x read QoS + register + 0x45100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI5_READ_QOS + AXI_INI5_READ_QOS + AXI interconnect - INI x read QoS + register + 0x46100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI6_READ_QOS + AXI_INI6_READ_QOS + AXI interconnect - INI x read QoS + register + 0x47100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI1_WRITE_QOS + AXI_INI1_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x42104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI2_WRITE_QOS + AXI_INI2_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x43104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI3_WRITE_QOS + AXI_INI3_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x44104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI4_WRITE_QOS + AXI_INI4_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x45104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI5_WRITE_QOS + AXI_INI5_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x46104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI6_WRITE_QOS + AXI_INI6_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x47104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI1_FN_MOD + AXI_INI1_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x42108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI2_FN_MOD + AXI_INI2_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x43108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI3_FN_MOD + AXI_INI3_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x44108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI4_FN_MOD + AXI_INI4_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x45108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI5_FN_MOD + AXI_INI5_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x46108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI6_FN_MOD + AXI_INI6_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x47108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + + + DCMI + Digital camera interface + DCMI + 0x48020000 + + 0x0 + 0x400 + registers + + + DCMI + DCMI global interrupt + 78 + + + + CR + CR + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + OELS + Odd/Even Line Select (Line Select + Start) + 20 + 1 + + + LSM + Line Select mode + 19 + 1 + + + OEBS + Odd/Even Byte Select (Byte Select + Start) + 18 + 1 + + + BSM + Byte Select mode + 16 + 2 + + + ENABLE + DCMI enable + 14 + 1 + + + EDM + Extended data mode + 10 + 2 + + + FCRC + Frame capture rate control + 8 + 2 + + + VSPOL + Vertical synchronization + polarity + 7 + 1 + + + HSPOL + Horizontal synchronization + polarity + 6 + 1 + + + PCKPOL + Pixel clock polarity + 5 + 1 + + + ESS + Embedded synchronization + select + 4 + 1 + + + JPEG + JPEG format + 3 + 1 + + + CROP + Crop feature + 2 + 1 + + + CM + Capture mode + 1 + 1 + + + CAPTURE + Capture enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x0000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + HSYNC + HSYNC + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x0000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt + status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt + status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt + status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt + enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt + enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status + register + 0x10 + 0x20 + read-only + 0x0000 + + + LINE_MIS + Line masked interrupt + status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt + status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt + status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt + status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt + status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + LINE_ISC + line interrupt status + clear + 4 + 1 + + + VSYNC_ISC + Vertical synch interrupt status + clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status + clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status + clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status + clear + 0 + 1 + + + + + ESCR + ESCR + embedded synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter + unmask + 8 + 8 + + + FSU + Frame start delimiter + unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x0000 + + + Byte3 + Data byte 3 + 24 + 8 + + + Byte2 + Data byte 2 + 16 + 8 + + + Byte1 + Data byte 1 + 8 + 8 + + + Byte0 + Data byte 0 + 0 + 8 + + + + + + + OTG1_HS_GLOBAL + USB 1 on the go high speed + USB_OTG_HS + 0x40040000 + + 0x0 + 0x400 + registers + + + OTG_FS_EP1_OUT + OTG_FS out global interrupt + 98 + + + OTG_FS_EP1_IN + OTG_FS in global interrupt + 99 + + + OTG_FS_WKUP + OTG_FS wakeup + 100 + + + OTG_FS + OTG_FS global interrupt + 101 + + + + OTG_HS_GOTGCTL + OTG_HS_GOTGCTL + OTG_HS control and status + register + 0x0 + 32 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + EHEN + Embedded host enable + 12 + 1 + read-write + + + + + OTG_HS_GOTGINT + OTG_HS_GOTGINT + OTG_HS interrupt register + 0x4 + 32 + read-write + 0x0 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + IDCHNG + ID input pin changed + 20 + 1 + + + + + OTG_HS_GAHBCFG + OTG_HS_GAHBCFG + OTG_HS AHB configuration + register + 0x8 + 32 + read-write + 0x0 + + + GINT + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst length/type + 1 + 4 + + + DMAEN + DMA enable + 5 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + OTG_HS_GUSBCFG + OTG_HS_GUSBCFG + OTG_HS USB configuration + register + 0xC + 32 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + USB 2.0 high-speed ULPI PHY or USB 1.1 + full-speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + PHYLPCS + PHY Low-power clock select + 15 + 1 + read-write + + + ULPIFSLS + ULPI FS/LS select + 17 + 1 + read-write + + + ULPIAR + ULPI Auto-resume + 18 + 1 + read-write + + + ULPICSM + ULPI Clock SuspendM + 19 + 1 + read-write + + + ULPIEVBUSD + ULPI External VBUS Drive + 20 + 1 + read-write + + + ULPIEVBUSI + ULPI external VBUS + indicator + 21 + 1 + read-write + + + TSDPS + TermSel DLine pulsing + selection + 22 + 1 + read-write + + + PCCI + Indicator complement + 23 + 1 + read-write + + + PTCI + Indicator pass through + 24 + 1 + read-write + + + ULPIIPD + ULPI interface protect + disable + 25 + 1 + read-write + + + FHMOD + Forced host mode + 29 + 1 + read-write + + + FDMOD + Forced peripheral mode + 30 + 1 + read-write + + + + + OTG_HS_GRSTCTL + OTG_HS_GRSTCTL + OTG_HS reset register + 0x10 + 32 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + DMAREQ + DMA request signal enabled for USB OTG + HS + 30 + 1 + read-only + + + + + OTG_HS_GINTSTS + OTG_HS_GINTSTS + OTG_HS core interrupt register + 0x14 + 32 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO nonempty + 4 + 1 + read-only + + + NPTXFE + Nonperiodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN nonperiodic NAK + effective + 6 + 1 + read-only + + + BOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + PXFR_INCOMPISOOUT + Incomplete periodic + transfer + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended + 22 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + OTG_HS_GINTMSK + OTG_HS_GINTMSK + OTG_HS interrupt mask register + 0x18 + 32 + 0x0 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO nonempty mask + 4 + 1 + read-write + + + NPTXFEM + Nonperiodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global nonperiodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + PXFRM_IISOOXFRM + Incomplete periodic transfer + mask + 21 + 1 + read-write + + + FSUSPM + Data fetch suspended mask + 22 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + RSTDE + Reset detected interrupt + mask + 23 + 1 + read-write + + + LPMINTM + LPM interrupt mask + 27 + 1 + read-write + + + + + OTG_HS_GRXSTSR_Host + OTG_HS_GRXSTSR_Host + OTG_HS Receive status debug read register + (host mode) + 0x1C + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXSTSP_Host + OTG_HS_GRXSTSP_Host + OTG_HS status read and pop register (host + mode) + 0x20 + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXFSIZ + OTG_HS_GRXFSIZ + OTG_HS Receive FIFO size + register + 0x24 + 32 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + OTG_HS_HNPTXFSIZ_Host + OTG_HS_HNPTXFSIZ_Host + OTG_HS nonperiodic transmit FIFO size + register (host mode) + 0x28 + 32 + read-write + 0x00000200 + + + NPTXFSA + Nonperiodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Nonperiodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF0_Device + OTG_HS_DIEPTXF0_Device + Endpoint 0 transmit FIFO size (peripheral + mode) + OTG_HS_HNPTXFSIZ_Host + 0x28 + 32 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + OTG_HS_GNPTXSTS + OTG_HS_GNPTXSTS + OTG_HS nonperiodic transmit FIFO/queue + status register + 0x2C + 32 + read-only + 0x00080200 + + + NPTXFSAV + Nonperiodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Nonperiodic transmit request queue space + available + 16 + 8 + + + NPTXQTOP + Top of the nonperiodic transmit request + queue + 24 + 7 + + + + + OTG_HS_GCCFG + OTG_HS_GCCFG + OTG_HS general core configuration + register + 0x38 + 32 + read-write + 0x0 + + + PWRDWN + Power down + 16 + 1 + + + BCDEN + Battery charging detector (BCD) + enable + 17 + 1 + + + DCDEN + Data contact detection (DCD) mode + enable + 18 + 1 + + + PDEN + Primary detection (PD) mode + enable + 19 + 1 + + + SDEN + Secondary detection (SD) mode + enable + 20 + 1 + + + VBDEN + USB VBUS detection enable + 21 + 1 + + + DCDET + Data contact detection (DCD) + status + 0 + 1 + + + PDET + Primary detection (PD) + status + 1 + 1 + + + SDET + Secondary detection (SD) + status + 2 + 1 + + + PS2DET + DM pull-up detection + status + 3 + 1 + + + + + OTG_HS_CID + OTG_HS_CID + OTG_HS core ID register + 0x3C + 32 + read-write + 0x00001200 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + OTG_HS_HPTXFSIZ + OTG_HS_HPTXFSIZ + OTG_HS Host periodic transmit FIFO size + register + 0x100 + 32 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF1 + OTG_HS_DIEPTXF1 + OTG_HS device IN endpoint transmit FIFO size + register + 0x104 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF2 + OTG_HS_DIEPTXF2 + OTG_HS device IN endpoint transmit FIFO size + register + 0x108 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF3 + OTG_HS_DIEPTXF3 + OTG_HS device IN endpoint transmit FIFO size + register + 0x11C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF4 + OTG_HS_DIEPTXF4 + OTG_HS device IN endpoint transmit FIFO size + register + 0x120 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF5 + OTG_HS_DIEPTXF5 + OTG_HS device IN endpoint transmit FIFO size + register + 0x124 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF6 + OTG_HS_DIEPTXF6 + OTG_HS device IN endpoint transmit FIFO size + register + 0x128 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF7 + OTG_HS_DIEPTXF7 + OTG_HS device IN endpoint transmit FIFO size + register + 0x12C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_GRXSTSR_Device + OTG_HS_GRXSTSR_Device + OTG_HS Receive status debug read register + (peripheral mode mode) + OTG_HS_GRXSTSR_Host + 0x1C + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GRXSTSP_Device + OTG_HS_GRXSTSP_Device + OTG_HS status read and pop register + (peripheral mode) + OTG_HS_GRXSTSP_Host + 0x20 + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GLPMCFG + OTG_HS_GLPMCFG + OTG core LPM configuration + register + 0x54 + 32 + 0x0 + + + LPMEN + LPM support enable + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge + enable + 1 + 1 + read-write + + + BESL + Best effort service + latency + 2 + 4 + read-only + + + REMWAKE + bRemoteWake value + 6 + 1 + read-only + + + L1SSEN + L1 Shallow Sleep enable + 7 + 1 + read-write + + + BESLTHRS + BESL threshold + 8 + 4 + read-write + + + L1DSEN + L1 deep sleep enable + 12 + 1 + read-write + + + LPMRST + LPM response + 13 + 2 + read-only + + + SLPSTS + Port sleep status + 15 + 1 + read-only + + + L1RSMOK + Sleep State Resume OK + 16 + 1 + read-only + + + LPMCHIDX + LPM Channel Index + 17 + 4 + read-write + + + LPMRCNT + LPM retry count + 21 + 3 + read-write + + + SNDLPM + Send LPM transaction + 24 + 1 + read-write + + + LPMRCNTSTS + LPM retry count status + 25 + 3 + read-only + + + ENBESL + Enable best effort service + latency + 28 + 1 + read-write + + + + + + + OTG2_HS_GLOBAL + 0x40080000 + + OTG_HS_EP1_OUT + OTG_HS out global interrupt + 74 + + + OTG_HS_EP1_IN + OTG_HS in global interrupt + 75 + + + OTG_HS_WKUP + OTG_HS wakeup interrupt + 76 + + + OTG_HS + OTG_HS global interrupt + 77 + + + + OTG1_HS_HOST + USB 1 on the go high speed + USB_OTG_HS + 0x40040400 + + 0x0 + 0x400 + registers + + + + OTG_HS_HCFG + OTG_HS_HCFG + OTG_HS host configuration + register + 0x0 + 32 + 0x0 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + OTG_HS_HFIR + OTG_HS_HFIR + OTG_HS Host frame interval + register + 0x4 + 32 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + OTG_HS_HFNUM + OTG_HS_HFNUM + OTG_HS host frame number/frame time + remaining register + 0x8 + 32 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + OTG_HS_HPTXSTS + OTG_HS_HPTXSTS + OTG_HS_Host periodic transmit FIFO/queue + status register + 0x10 + 32 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + OTG_HS_HAINT + OTG_HS_HAINT + OTG_HS Host all channels interrupt + register + 0x14 + 32 + read-only + 0x0 + + + HAINT + Channel interrupts + 0 + 16 + + + + + OTG_HS_HAINTMSK + OTG_HS_HAINTMSK + OTG_HS host all channels interrupt mask + register + 0x18 + 32 + read-write + 0x0 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + OTG_HS_HPRT + OTG_HS_HPRT + OTG_HS host port control and status + register + 0x40 + 32 + 0x0 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + OTG_HS_HCCHAR0 + OTG_HS_HCCHAR0 + OTG_HS host channel-0 characteristics + register + 0x100 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR1 + OTG_HS_HCCHAR1 + OTG_HS host channel-1 characteristics + register + 0x120 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR2 + OTG_HS_HCCHAR2 + OTG_HS host channel-2 characteristics + register + 0x140 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR3 + OTG_HS_HCCHAR3 + OTG_HS host channel-3 characteristics + register + 0x160 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR4 + OTG_HS_HCCHAR4 + OTG_HS host channel-4 characteristics + register + 0x180 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR5 + OTG_HS_HCCHAR5 + OTG_HS host channel-5 characteristics + register + 0x1A0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR6 + OTG_HS_HCCHAR6 + OTG_HS host channel-6 characteristics + register + 0x1C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR7 + OTG_HS_HCCHAR7 + OTG_HS host channel-7 characteristics + register + 0x1E0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR8 + OTG_HS_HCCHAR8 + OTG_HS host channel-8 characteristics + register + 0x200 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR9 + OTG_HS_HCCHAR9 + OTG_HS host channel-9 characteristics + register + 0x220 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR10 + OTG_HS_HCCHAR10 + OTG_HS host channel-10 characteristics + register + 0x240 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR11 + OTG_HS_HCCHAR11 + OTG_HS host channel-11 characteristics + register + 0x260 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT0 + OTG_HS_HCSPLT0 + OTG_HS host channel-0 split control + register + 0x104 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT1 + OTG_HS_HCSPLT1 + OTG_HS host channel-1 split control + register + 0x124 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT2 + OTG_HS_HCSPLT2 + OTG_HS host channel-2 split control + register + 0x144 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT3 + OTG_HS_HCSPLT3 + OTG_HS host channel-3 split control + register + 0x164 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT4 + OTG_HS_HCSPLT4 + OTG_HS host channel-4 split control + register + 0x184 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT5 + OTG_HS_HCSPLT5 + OTG_HS host channel-5 split control + register + 0x1A4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT6 + OTG_HS_HCSPLT6 + OTG_HS host channel-6 split control + register + 0x1C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT7 + OTG_HS_HCSPLT7 + OTG_HS host channel-7 split control + register + 0x1E4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT8 + OTG_HS_HCSPLT8 + OTG_HS host channel-8 split control + register + 0x204 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT9 + OTG_HS_HCSPLT9 + OTG_HS host channel-9 split control + register + 0x224 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT10 + OTG_HS_HCSPLT10 + OTG_HS host channel-10 split control + register + 0x244 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT11 + OTG_HS_HCSPLT11 + OTG_HS host channel-11 split control + register + 0x264 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT0 + OTG_HS_HCINT0 + OTG_HS host channel-11 interrupt + register + 0x108 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT1 + OTG_HS_HCINT1 + OTG_HS host channel-1 interrupt + register + 0x128 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT2 + OTG_HS_HCINT2 + OTG_HS host channel-2 interrupt + register + 0x148 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT3 + OTG_HS_HCINT3 + OTG_HS host channel-3 interrupt + register + 0x168 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT4 + OTG_HS_HCINT4 + OTG_HS host channel-4 interrupt + register + 0x188 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT5 + OTG_HS_HCINT5 + OTG_HS host channel-5 interrupt + register + 0x1A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT6 + OTG_HS_HCINT6 + OTG_HS host channel-6 interrupt + register + 0x1C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT7 + OTG_HS_HCINT7 + OTG_HS host channel-7 interrupt + register + 0x1E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT8 + OTG_HS_HCINT8 + OTG_HS host channel-8 interrupt + register + 0x208 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT9 + OTG_HS_HCINT9 + OTG_HS host channel-9 interrupt + register + 0x228 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT10 + OTG_HS_HCINT10 + OTG_HS host channel-10 interrupt + register + 0x248 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT11 + OTG_HS_HCINT11 + OTG_HS host channel-11 interrupt + register + 0x268 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK0 + OTG_HS_HCINTMSK0 + OTG_HS host channel-11 interrupt mask + register + 0x10C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK1 + OTG_HS_HCINTMSK1 + OTG_HS host channel-1 interrupt mask + register + 0x12C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK2 + OTG_HS_HCINTMSK2 + OTG_HS host channel-2 interrupt mask + register + 0x14C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK3 + OTG_HS_HCINTMSK3 + OTG_HS host channel-3 interrupt mask + register + 0x16C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK4 + OTG_HS_HCINTMSK4 + OTG_HS host channel-4 interrupt mask + register + 0x18C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK5 + OTG_HS_HCINTMSK5 + OTG_HS host channel-5 interrupt mask + register + 0x1AC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK6 + OTG_HS_HCINTMSK6 + OTG_HS host channel-6 interrupt mask + register + 0x1CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK7 + OTG_HS_HCINTMSK7 + OTG_HS host channel-7 interrupt mask + register + 0x1EC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK8 + OTG_HS_HCINTMSK8 + OTG_HS host channel-8 interrupt mask + register + 0x20C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK9 + OTG_HS_HCINTMSK9 + OTG_HS host channel-9 interrupt mask + register + 0x22C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK10 + OTG_HS_HCINTMSK10 + OTG_HS host channel-10 interrupt mask + register + 0x24C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK11 + OTG_HS_HCINTMSK11 + OTG_HS host channel-11 interrupt mask + register + 0x26C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ0 + OTG_HS_HCTSIZ0 + OTG_HS host channel-11 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ1 + OTG_HS_HCTSIZ1 + OTG_HS host channel-1 transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ2 + OTG_HS_HCTSIZ2 + OTG_HS host channel-2 transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ3 + OTG_HS_HCTSIZ3 + OTG_HS host channel-3 transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ4 + OTG_HS_HCTSIZ4 + OTG_HS host channel-4 transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ5 + OTG_HS_HCTSIZ5 + OTG_HS host channel-5 transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ6 + OTG_HS_HCTSIZ6 + OTG_HS host channel-6 transfer size + register + 0x1D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ7 + OTG_HS_HCTSIZ7 + OTG_HS host channel-7 transfer size + register + 0x1F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ8 + OTG_HS_HCTSIZ8 + OTG_HS host channel-8 transfer size + register + 0x210 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ9 + OTG_HS_HCTSIZ9 + OTG_HS host channel-9 transfer size + register + 0x230 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ10 + OTG_HS_HCTSIZ10 + OTG_HS host channel-10 transfer size + register + 0x250 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ11 + OTG_HS_HCTSIZ11 + OTG_HS host channel-11 transfer size + register + 0x270 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA0 + OTG_HS_HCDMA0 + OTG_HS host channel-0 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA1 + OTG_HS_HCDMA1 + OTG_HS host channel-1 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA2 + OTG_HS_HCDMA2 + OTG_HS host channel-2 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA3 + OTG_HS_HCDMA3 + OTG_HS host channel-3 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA4 + OTG_HS_HCDMA4 + OTG_HS host channel-4 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA5 + OTG_HS_HCDMA5 + OTG_HS host channel-5 DMA address + register + 0x1B4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA6 + OTG_HS_HCDMA6 + OTG_HS host channel-6 DMA address + register + 0x1D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA7 + OTG_HS_HCDMA7 + OTG_HS host channel-7 DMA address + register + 0x1F4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA8 + OTG_HS_HCDMA8 + OTG_HS host channel-8 DMA address + register + 0x214 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA9 + OTG_HS_HCDMA9 + OTG_HS host channel-9 DMA address + register + 0x234 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA10 + OTG_HS_HCDMA10 + OTG_HS host channel-10 DMA address + register + 0x254 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA11 + OTG_HS_HCDMA11 + OTG_HS host channel-11 DMA address + register + 0x274 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR12 + OTG_HS_HCCHAR12 + OTG_HS host channel-12 characteristics + register + 0x278 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT12 + OTG_HS_HCSPLT12 + OTG_HS host channel-12 split control + register + 0x27C + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT12 + OTG_HS_HCINT12 + OTG_HS host channel-12 interrupt + register + 0x280 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK12 + OTG_HS_HCINTMSK12 + OTG_HS host channel-12 interrupt mask + register + 0x284 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ12 + OTG_HS_HCTSIZ12 + OTG_HS host channel-12 transfer size + register + 0x288 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA12 + OTG_HS_HCDMA12 + OTG_HS host channel-12 DMA address + register + 0x28C + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR13 + OTG_HS_HCCHAR13 + OTG_HS host channel-13 characteristics + register + 0x290 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT13 + OTG_HS_HCSPLT13 + OTG_HS host channel-13 split control + register + 0x294 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT13 + OTG_HS_HCINT13 + OTG_HS host channel-13 interrupt + register + 0x298 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK13 + OTG_HS_HCINTMSK13 + OTG_HS host channel-13 interrupt mask + register + 0x29C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALLM response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ13 + OTG_HS_HCTSIZ13 + OTG_HS host channel-13 transfer size + register + 0x2A0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA13 + OTG_HS_HCDMA13 + OTG_HS host channel-13 DMA address + register + 0x2A4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR14 + OTG_HS_HCCHAR14 + OTG_HS host channel-14 characteristics + register + 0x2A8 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT14 + OTG_HS_HCSPLT14 + OTG_HS host channel-14 split control + register + 0x2AC + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT14 + OTG_HS_HCINT14 + OTG_HS host channel-14 interrupt + register + 0x2B0 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK14 + OTG_HS_HCINTMSK14 + OTG_HS host channel-14 interrupt mask + register + 0x2B4 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAKM response received interrupt + mask + 4 + 1 + + + ACKM + ACKM response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ14 + OTG_HS_HCTSIZ14 + OTG_HS host channel-14 transfer size + register + 0x2B8 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA14 + OTG_HS_HCDMA14 + OTG_HS host channel-14 DMA address + register + 0x2BC + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR15 + OTG_HS_HCCHAR15 + OTG_HS host channel-15 characteristics + register + 0x2C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT15 + OTG_HS_HCSPLT15 + OTG_HS host channel-15 split control + register + 0x2C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT15 + OTG_HS_HCINT15 + OTG_HS host channel-15 interrupt + register + 0x2C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK15 + OTG_HS_HCINTMSK15 + OTG_HS host channel-15 interrupt mask + register + 0x2CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ15 + OTG_HS_HCTSIZ15 + OTG_HS host channel-15 transfer size + register + 0x2D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA15 + OTG_HS_HCDMA15 + OTG_HS host channel-15 DMA address + register + 0x2D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + + + OTG2_HS_HOST + 0x40080400 + + + OTG1_HS_DEVICE + USB 1 on the go high speed + USB_OTG_HS + 0x40040800 + + 0x0 + 0x400 + registers + + + + OTG_HS_DCFG + OTG_HS_DCFG + OTG_HS device configuration + register + 0x0 + 32 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Nonzero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic (micro)frame + interval + 11 + 2 + + + PERSCHIVL + Periodic scheduling + interval + 24 + 2 + + + + + OTG_HS_DCTL + OTG_HS_DCTL + OTG_HS device control register + 0x4 + 32 + 0x0 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + OTG_HS_DSTS + OTG_HS_DSTS + OTG_HS device status register + 0x8 + 32 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + OTG_HS_DIEPMSK + OTG_HS_DIEPMSK + OTG_HS device IN endpoint common interrupt + mask register + 0x10 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DOEPMSK + OTG_HS_DOEPMSK + OTG_HS device OUT endpoint common interrupt + mask register + 0x14 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + mask + 6 + 1 + + + OPEM + OUT packet error mask + 8 + 1 + + + BOIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DAINT + OTG_HS_DAINT + OTG_HS device all endpoints interrupt + register + 0x18 + 32 + read-only + 0x0 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + OTG_HS_DAINTMSK + OTG_HS_DAINTMSK + OTG_HS all endpoints interrupt mask + register + 0x1C + 32 + read-write + 0x0 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + OTG_HS_DVBUSDIS + OTG_HS_DVBUSDIS + OTG_HS device VBUS discharge time + register + 0x28 + 32 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + OTG_HS_DVBUSPULSE + OTG_HS_DVBUSPULSE + OTG_HS device VBUS pulsing time + register + 0x2C + 32 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + OTG_HS_DTHRCTL + OTG_HS_DTHRCTL + OTG_HS Device threshold control + register + 0x30 + 32 + read-write + 0x0 + + + NONISOTHREN + Nonisochronous IN endpoints threshold + enable + 0 + 1 + + + ISOTHREN + ISO IN endpoint threshold + enable + 1 + 1 + + + TXTHRLEN + Transmit threshold length + 2 + 9 + + + RXTHREN + Receive threshold enable + 16 + 1 + + + RXTHRLEN + Receive threshold length + 17 + 9 + + + ARPEN + Arbiter parking enable + 27 + 1 + + + + + OTG_HS_DIEPEMPMSK + OTG_HS_DIEPEMPMSK + OTG_HS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 32 + read-write + 0x0 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + OTG_HS_DEACHINT + OTG_HS_DEACHINT + OTG_HS device each endpoint interrupt + register + 0x38 + 32 + read-write + 0x0 + + + IEP1INT + IN endpoint 1interrupt bit + 1 + 1 + + + OEP1INT + OUT endpoint 1 interrupt + bit + 17 + 1 + + + + + OTG_HS_DEACHINTMSK + OTG_HS_DEACHINTMSK + OTG_HS device each endpoint interrupt + register mask + 0x3C + 32 + read-write + 0x0 + + + IEP1INTM + IN Endpoint 1 interrupt mask + bit + 1 + 1 + + + OEP1INTM + OUT Endpoint 1 interrupt mask + bit + 17 + 1 + + + + + OTG_HS_DIEPCTL0 + OTG_HS_DIEPCTL0 + OTG device endpoint-0 control + register + 0x100 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL1 + OTG_HS_DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL2 + OTG_HS_DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL3 + OTG_HS_DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL4 + OTG_HS_DIEPCTL4 + OTG device endpoint-4 control + register + 0x180 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL5 + OTG_HS_DIEPCTL5 + OTG device endpoint-5 control + register + 0x1A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL6 + OTG_HS_DIEPCTL6 + OTG device endpoint-6 control + register + 0x1C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL7 + OTG_HS_DIEPCTL7 + OTG device endpoint-7 control + register + 0x1E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPINT0 + OTG_HS_DIEPINT0 + OTG device endpoint-0 interrupt + register + 0x108 + 32 + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT1 + OTG_HS_DIEPINT1 + OTG device endpoint-1 interrupt + register + 0x128 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT2 + OTG_HS_DIEPINT2 + OTG device endpoint-2 interrupt + register + 0x148 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT3 + OTG_HS_DIEPINT3 + OTG device endpoint-3 interrupt + register + 0x168 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT4 + OTG_HS_DIEPINT4 + OTG device endpoint-4 interrupt + register + 0x188 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT5 + OTG_HS_DIEPINT5 + OTG device endpoint-5 interrupt + register + 0x1A8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT6 + OTG_HS_DIEPINT6 + OTG device endpoint-6 interrupt + register + 0x1C8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT7 + OTG_HS_DIEPINT7 + OTG device endpoint-7 interrupt + register + 0x1E8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPTSIZ0 + OTG_HS_DIEPTSIZ0 + OTG_HS device IN endpoint 0 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + OTG_HS_DIEPDMA1 + OTG_HS_DIEPDMA1 + OTG_HS device endpoint-1 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA2 + OTG_HS_DIEPDMA2 + OTG_HS device endpoint-2 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA3 + OTG_HS_DIEPDMA3 + OTG_HS device endpoint-3 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA4 + OTG_HS_DIEPDMA4 + OTG_HS device endpoint-4 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA5 + OTG_HS_DIEPDMA5 + OTG_HS device endpoint-5 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DTXFSTS0 + OTG_HS_DTXFSTS0 + OTG_HS device IN endpoint transmit FIFO + status register + 0x118 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS1 + OTG_HS_DTXFSTS1 + OTG_HS device IN endpoint transmit FIFO + status register + 0x138 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS2 + OTG_HS_DTXFSTS2 + OTG_HS device IN endpoint transmit FIFO + status register + 0x158 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS3 + OTG_HS_DTXFSTS3 + OTG_HS device IN endpoint transmit FIFO + status register + 0x178 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS4 + OTG_HS_DTXFSTS4 + OTG_HS device IN endpoint transmit FIFO + status register + 0x198 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS5 + OTG_HS_DTXFSTS5 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1B8 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ1 + OTG_HS_DIEPTSIZ1 + OTG_HS device endpoint transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ2 + OTG_HS_DIEPTSIZ2 + OTG_HS device endpoint transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ3 + OTG_HS_DIEPTSIZ3 + OTG_HS device endpoint transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ4 + OTG_HS_DIEPTSIZ4 + OTG_HS device endpoint transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ5 + OTG_HS_DIEPTSIZ5 + OTG_HS device endpoint transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DOEPCTL0 + OTG_HS_DOEPCTL0 + OTG_HS device control OUT endpoint 0 control + register + 0x300 + 32 + 0x00008000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-only + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + write-only + + + + + OTG_HS_DOEPCTL1 + OTG_HS_DOEPCTL1 + OTG device endpoint-1 control + register + 0x320 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL2 + OTG_HS_DOEPCTL2 + OTG device endpoint-2 control + register + 0x340 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL3 + OTG_HS_DOEPCTL3 + OTG device endpoint-3 control + register + 0x360 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPINT0 + OTG_HS_DOEPINT0 + OTG_HS device endpoint-0 interrupt + register + 0x308 + 32 + read-write + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT1 + OTG_HS_DOEPINT1 + OTG_HS device endpoint-1 interrupt + register + 0x328 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT2 + OTG_HS_DOEPINT2 + OTG_HS device endpoint-2 interrupt + register + 0x348 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT3 + OTG_HS_DOEPINT3 + OTG_HS device endpoint-3 interrupt + register + 0x368 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT4 + OTG_HS_DOEPINT4 + OTG_HS device endpoint-4 interrupt + register + 0x388 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT5 + OTG_HS_DOEPINT5 + OTG_HS device endpoint-5 interrupt + register + 0x3A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT6 + OTG_HS_DOEPINT6 + OTG_HS device endpoint-6 interrupt + register + 0x3C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT7 + OTG_HS_DOEPINT7 + OTG_HS device endpoint-7 interrupt + register + 0x3E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPTSIZ0 + OTG_HS_DOEPTSIZ0 + OTG_HS device endpoint-0 transfer size + register + 0x310 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + STUPCNT + SETUP packet count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ1 + OTG_HS_DOEPTSIZ1 + OTG_HS device endpoint-1 transfer size + register + 0x330 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ2 + OTG_HS_DOEPTSIZ2 + OTG_HS device endpoint-2 transfer size + register + 0x350 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ3 + OTG_HS_DOEPTSIZ3 + OTG_HS device endpoint-3 transfer size + register + 0x370 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ4 + OTG_HS_DOEPTSIZ4 + OTG_HS device endpoint-4 transfer size + register + 0x390 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ6 + OTG_HS_DIEPTSIZ6 + OTG_HS device endpoint transfer size + register + OTG_HS_DIEPCTL5 + 0x1A0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DTXFSTS6 + OTG_HS_DTXFSTS6 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1A4 + 32 + read-write + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ7 + OTG_HS_DIEPTSIZ7 + OTG_HS device endpoint transfer size + register + OTG_HS_DIEPINT5 + 0x1A8 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DTXFSTS7 + OTG_HS_DTXFSTS7 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1AC + 32 + read-write + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DOEPCTL4 + OTG_HS_DOEPCTL4 + OTG device endpoint-4 control + register + 0x380 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL5 + OTG_HS_DOEPCTL5 + OTG device endpoint-5 control + register + 0x3A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL6 + OTG_HS_DOEPCTL6 + OTG device endpoint-6 control + register + 0x3C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL7 + OTG_HS_DOEPCTL7 + OTG device endpoint-7 control + register + 0x3E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPTSIZ5 + OTG_HS_DOEPTSIZ5 + OTG_HS device endpoint-5 transfer size + register + 0x3B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ6 + OTG_HS_DOEPTSIZ6 + OTG_HS device endpoint-6 transfer size + register + 0x3D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ7 + OTG_HS_DOEPTSIZ7 + OTG_HS device endpoint-7 transfer size + register + 0x3F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + + + OTG2_HS_DEVICE + 0x40080800 + + + OTG1_HS_PWRCLK + USB 1 on the go high speed + USB_OTG_HS + 0x40040E00 + + 0x0 + 0x3F200 + registers + + + + OTG_HS_PCGCR + OTG_HS_PCGCR + Power and clock gating control + register + 0x0 + 32 + read-write + 0x0 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY suspended + 4 + 1 + + + + + + + OTG2_HS_PWRCLK + 0x40080E00 + + + Ethernet_MAC + Ethernet: media access control + (MAC) + Ethernet + 0x40028000 + + 0x0 + 0x1400 + registers + + + ETH + Ethernet global interrupt + 61 + + + ETH_WKUP + Ethernet wakeup through EXTI + 62 + + + + DMAMR + DMAMR + DMA mode register + 0x1000 + 0x20 + 0x00000000 + + + SWR + Software Reset + 0 + 1 + read-write + + + DA + DMA Tx or Rx Arbitration + Scheme + 1 + 1 + read-only + + + TXPR + Transmit priority + 11 + 1 + read-only + + + PR + Priority ratio + 12 + 3 + read-only + + + INTM + Interrupt Mode + 16 + 1 + read-write + + + + + DMASBMR + DMASBMR + System bus mode register + 0x1004 + 0x20 + 0x01010000 + + + FB + Fixed Burst Length + 0 + 1 + read-write + + + AAL + Address-Aligned Beats + 12 + 1 + read-write + + + MB + Mixed Burst + 14 + 1 + read-only + + + RB + Rebuild INCRx Burst + 15 + 1 + read-only + + + + + DMAISR + DMAISR + Interrupt status register + 0x1008 + 0x20 + read-only + 0x00000000 + + + DC0IS + DMA Channel Interrupt + Status + 0 + 1 + + + MTLIS + MTL Interrupt Status + 16 + 1 + + + MACIS + MAC Interrupt Status + 17 + 1 + + + + + DMADSR + DMADSR + Debug status register + 0x100C + 0x20 + read-only + 0x00000000 + + + AXWHSTS + AHB Master Write Channel + 0 + 1 + + + RPS0 + DMA Channel Receive Process + State + 8 + 4 + + + TPS0 + DMA Channel Transmit Process + State + 12 + 4 + + + + + DMACCR + DMACCR + Channel control register + 0x1100 + 0x20 + read-write + 0x00000000 + + + MSS + Maximum Segment Size + 0 + 14 + + + PBLX8 + 8xPBL mode + 16 + 1 + + + DSL + Descriptor Skip Length + 18 + 3 + + + + + DMACTxCR + DMACTxCR + Channel transmit control + register + 0x1104 + 0x20 + read-write + 0x00000000 + + + ST + Start or Stop Transmission + Command + 0 + 1 + + + OSF + Operate on Second Packet + 4 + 1 + + + TSE + TCP Segmentation Enabled + 12 + 1 + + + TXPBL + Transmit Programmable Burst + Length + 16 + 6 + + + + + DMACRxCR + DMACRxCR + Channel receive control + register + 0x1108 + 0x20 + read-write + 0x00000000 + + + SR + Start or Stop Receive + Command + 0 + 1 + + + RBSZ + Receive Buffer size + 1 + 14 + + + RXPBL + RXPBL + 16 + 6 + + + RPF + DMA Rx Channel Packet + Flush + 31 + 1 + + + + + DMACTxDLAR + DMACTxDLAR + Channel Tx descriptor list address + register + 0x1114 + 0x20 + read-write + 0x00000000 + + + TDESLA + Start of Transmit List + 2 + 30 + + + + + DMACRxDLAR + DMACRxDLAR + Channel Rx descriptor list address + register + 0x111C + 0x20 + read-write + 0x00000000 + + + RDESLA + Start of Receive List + 2 + 30 + + + + + DMACTxDTPR + DMACTxDTPR + Channel Tx descriptor tail pointer + register + 0x1120 + 0x20 + read-write + 0x00000000 + + + TDT + Transmit Descriptor Tail + Pointer + 2 + 30 + + + + + DMACRxDTPR + DMACRxDTPR + Channel Rx descriptor tail pointer + register + 0x1128 + 0x20 + read-write + 0x00000000 + + + RDT + Receive Descriptor Tail + Pointer + 2 + 30 + + + + + DMACTxRLR + DMACTxRLR + Channel Tx descriptor ring length + register + 0x112C + 0x20 + read-write + 0x00000000 + + + TDRL + Transmit Descriptor Ring + Length + 0 + 10 + + + + + DMACRxRLR + DMACRxRLR + Channel Rx descriptor ring length + register + 0x1130 + 0x20 + read-write + 0x00000000 + + + RDRL + Receive Descriptor Ring + Length + 0 + 10 + + + + + DMACIER + DMACIER + Channel interrupt enable + register + 0x1134 + 0x20 + read-write + 0x00000000 + + + TIE + Transmit Interrupt Enable + 0 + 1 + + + TXSE + Transmit Stopped Enable + 1 + 1 + + + TBUE + Transmit Buffer Unavailable + Enable + 2 + 1 + + + RIE + Receive Interrupt Enable + 6 + 1 + + + RBUE + Receive Buffer Unavailable + Enable + 7 + 1 + + + RSE + Receive Stopped Enable + 8 + 1 + + + RWTE + Receive Watchdog Timeout + Enable + 9 + 1 + + + ETIE + Early Transmit Interrupt + Enable + 10 + 1 + + + ERIE + Early Receive Interrupt + Enable + 11 + 1 + + + FBEE + Fatal Bus Error Enable + 12 + 1 + + + CDEE + Context Descriptor Error + Enable + 13 + 1 + + + AIE + Abnormal Interrupt Summary + Enable + 14 + 1 + + + NIE + Normal Interrupt Summary + Enable + 15 + 1 + + + + + DMACRxIWTR + DMACRxIWTR + Channel Rx interrupt watchdog timer + register + 0x1138 + 0x20 + read-write + 0x00000000 + + + RWT + Receive Interrupt Watchdog Timer + Count + 0 + 8 + + + + + DMACCATxDR + DMACCATxDR + Channel current application transmit + descriptor register + 0x1144 + 0x20 + read-only + 0x00000000 + + + CURTDESAPTR + Application Transmit Descriptor Address + Pointer + 0 + 32 + + + + + DMACCARxDR + DMACCARxDR + Channel current application receive + descriptor register + 0x114C + 0x20 + read-only + 0x00000000 + + + CURRDESAPTR + Application Receive Descriptor Address + Pointer + 0 + 32 + + + + + DMACCATxBR + DMACCATxBR + Channel current application transmit buffer + register + 0x1154 + 0x20 + read-only + 0x00000000 + + + CURTBUFAPTR + Application Transmit Buffer Address + Pointer + 0 + 32 + + + + + DMACCARxBR + DMACCARxBR + Channel current application receive buffer + register + 0x115C + 0x20 + read-only + 0x00000000 + + + CURRBUFAPTR + Application Receive Buffer Address + Pointer + 0 + 32 + + + + + DMACSR + DMACSR + Channel status register + 0x1160 + 0x20 + 0x00000000 + + + TI + Transmit Interrupt + 0 + 1 + read-write + + + TPS + Transmit Process Stopped + 1 + 1 + read-write + + + TBU + Transmit Buffer + Unavailable + 2 + 1 + read-write + + + RI + Receive Interrupt + 6 + 1 + read-write + + + RBU + Receive Buffer Unavailable + 7 + 1 + read-write + + + RPS + Receive Process Stopped + 8 + 1 + read-write + + + RWT + Receive Watchdog Timeout + 9 + 1 + read-write + + + ET + Early Transmit Interrupt + 10 + 1 + read-write + + + ER + Early Receive Interrupt + 11 + 1 + read-write + + + FBE + Fatal Bus Error + 12 + 1 + read-write + + + CDE + Context Descriptor Error + 13 + 1 + read-write + + + AIS + Abnormal Interrupt Summary + 14 + 1 + read-write + + + NIS + Normal Interrupt Summary + 15 + 1 + read-write + + + TEB + Tx DMA Error Bits + 16 + 3 + read-only + + + REB + Rx DMA Error Bits + 19 + 3 + read-only + + + + + DMACMFCR + DMACMFCR + Channel missed frame count + register + 0x116C + 0x20 + read-only + 0x00000000 + + + MFC + Dropped Packet Counters + 0 + 11 + + + MFCO + Overflow status of the MFC + Counter + 15 + 1 + + + + + MTLOMR + MTLOMR + Operating mode Register + 0xC00 + 0x20 + read-write + 0x00000000 + + + DTXSTS + DTXSTS + 1 + 1 + + + CNTPRST + CNTPRST + 8 + 1 + + + CNTCLR + CNTCLR + 9 + 1 + + + + + MTLISR + MTLISR + Interrupt status Register + 0xC20 + 0x20 + read-only + 0x00000000 + + + Q0IS + Queue interrupt status + 0 + 1 + + + + + MTLTxQOMR + MTLTxQOMR + Tx queue operating mode + Register + 0xD00 + 0x20 + 0x00070008 + + + FTQ + Flush Transmit Queue + 0 + 1 + read-write + + + TSF + Transmit Store and Forward + 1 + 1 + read-write + + + TXQEN + Transmit Queue Enable + 2 + 2 + read-only + + + TTC + Transmit Threshold Control + 4 + 3 + read-write + + + TQS + Transmit Queue Size + 16 + 9 + read-write + + + + + MTLTxQUR + MTLTxQUR + Tx queue underflow register + 0xD04 + 0x20 + read-only + 0x00000000 + + + UFFRMCNT + Underflow Packet Counter + 0 + 11 + + + UFCNTOVF + UFCNTOVF + 11 + 1 + + + + + MTLTxQDR + MTLTxQDR + Tx queue debug Register + 0xD08 + 0x20 + read-only + 0x00000000 + + + TXQPAUSED + TXQPAUSED + 0 + 1 + + + TRCSTS + TRCSTS + 1 + 2 + + + TWCSTS + TWCSTS + 3 + 1 + + + TXQSTS + TXQSTS + 4 + 1 + + + TXSTSFSTS + TXSTSFSTS + 5 + 1 + + + PTXQ + PTXQ + 16 + 3 + + + STXSTSF + STXSTSF + 20 + 3 + + + + + MTLQICSR + MTLQICSR + Queue interrupt control status + Register + 0xD2C + 0x20 + read-write + 0x00000000 + + + TXUNFIS + TXUNFIS + 0 + 1 + + + TXUIE + TXUIE + 8 + 1 + + + RXOVFIS + RXOVFIS + 16 + 1 + + + RXOIE + RXOIE + 24 + 1 + + + + + MTLRxQOMR + MTLRxQOMR + Rx queue operating mode + register + 0xD30 + 0x20 + 0x00700000 + + + RTC + RTC + 0 + 2 + read-write + + + FUP + FUP + 3 + 1 + read-write + + + FEP + FEP + 4 + 1 + read-write + + + RSF + RSF + 5 + 1 + read-write + + + DIS_TCP_EF + DIS_TCP_EF + 6 + 1 + read-write + + + EHFC + EHFC + 7 + 1 + read-write + + + RFA + RFA + 8 + 3 + read-write + + + RFD + RFD + 14 + 3 + read-write + + + RQS + RQS + 20 + 3 + read-only + + + + + MTLRxQMPOCR + MTLRxQMPOCR + Rx queue missed packet and overflow counter + register + 0xD34 + 0x20 + read-only + 0x00000000 + + + OVFPKTCNT + OVFPKTCNT + 0 + 11 + + + OVFCNTOVF + OVFCNTOVF + 11 + 1 + + + MISPKTCNT + MISPKTCNT + 16 + 11 + + + MISCNTOVF + MISCNTOVF + 27 + 1 + + + + + MTLRxQDR + MTLRxQDR + Rx queue debug register + 0xD38 + 0x20 + read-only + 0x00000000 + + + RWCSTS + RWCSTS + 0 + 1 + + + RRCSTS + RRCSTS + 1 + 2 + + + RXQSTS + RXQSTS + 4 + 2 + + + PRXQ + PRXQ + 16 + 14 + + + + + MACCR + MACCR + Operating mode configuration + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RE + Receiver Enable + 0 + 1 + + + TE + TE + 1 + 1 + + + PRELEN + PRELEN + 2 + 2 + + + DC + DC + 4 + 1 + + + BL + BL + 5 + 2 + + + DR + DR + 8 + 1 + + + DCRS + DCRS + 9 + 1 + + + DO + DO + 10 + 1 + + + ECRSFD + ECRSFD + 11 + 1 + + + LM + LM + 12 + 1 + + + DM + DM + 13 + 1 + + + FES + FES + 14 + 1 + + + JE + JE + 16 + 1 + + + JD + JD + 17 + 1 + + + WD + WD + 19 + 1 + + + ACS + ACS + 20 + 1 + + + CST + CST + 21 + 1 + + + S2KP + S2KP + 22 + 1 + + + GPSLCE + GPSLCE + 23 + 1 + + + IPG + IPG + 24 + 3 + + + IPC + IPC + 27 + 1 + + + SARC + SARC + 28 + 3 + + + ARPEN + ARPEN + 31 + 1 + + + + + MACECR + MACECR + Extended operating mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + GPSL + GPSL + 0 + 14 + + + DCRCC + DCRCC + 16 + 1 + + + SPEN + SPEN + 17 + 1 + + + USP + USP + 18 + 1 + + + EIPGEN + EIPGEN + 24 + 1 + + + EIPG + EIPG + 25 + 5 + + + + + MACPFR + MACPFR + Packet filtering control + register + 0x8 + 0x20 + read-write + 0x00000000 + + + PR + PR + 0 + 1 + + + HUC + HUC + 1 + 1 + + + HMC + HMC + 2 + 1 + + + DAIF + DAIF + 3 + 1 + + + PM + PM + 4 + 1 + + + DBF + DBF + 5 + 1 + + + PCF + PCF + 6 + 2 + + + SAIF + SAIF + 8 + 1 + + + SAF + SAF + 9 + 1 + + + HPF + HPF + 10 + 1 + + + VTFE + VTFE + 16 + 1 + + + IPFE + IPFE + 20 + 1 + + + DNTU + DNTU + 21 + 1 + + + RA + RA + 31 + 1 + + + + + MACWTR + MACWTR + Watchdog timeout register + 0xC + 0x20 + read-write + 0x00000000 + + + WTO + WTO + 0 + 4 + + + PWE + PWE + 8 + 1 + + + + + MACHT0R + MACHT0R + Hash Table 0 register + 0x10 + 0x20 + read-write + 0x00000000 + + + HT31T0 + HT31T0 + 0 + 32 + + + + + MACHT1R + MACHT1R + Hash Table 1 register + 0x14 + 0x20 + read-write + 0x00000000 + + + HT63T32 + HT63T32 + 0 + 32 + + + + + MACVTR + MACVTR + VLAN tag register + 0x50 + 0x20 + read-write + 0x00000000 + + + VL + VL + 0 + 16 + + + ETV + ETV + 16 + 1 + + + VTIM + VTIM + 17 + 1 + + + ESVL + ESVL + 18 + 1 + + + ERSVLM + ERSVLM + 19 + 1 + + + DOVLTC + DOVLTC + 20 + 1 + + + EVLS + EVLS + 21 + 2 + + + EVLRXS + EVLRXS + 24 + 1 + + + VTHM + VTHM + 25 + 1 + + + EDVLP + EDVLP + 26 + 1 + + + ERIVLT + ERIVLT + 27 + 1 + + + EIVLS + EIVLS + 28 + 2 + + + EIVLRXS + EIVLRXS + 31 + 1 + + + + + MACVHTR + MACVHTR + VLAN Hash table register + 0x58 + 0x20 + read-write + 0x00000000 + + + VLHT + VLHT + 0 + 16 + + + + + MACVIR + MACVIR + VLAN inclusion register + 0x60 + 0x20 + read-write + 0x00000000 + + + VLT + VLT + 0 + 16 + + + VLC + VLC + 16 + 2 + + + VLP + VLP + 18 + 1 + + + CSVL + CSVL + 19 + 1 + + + VLTI + VLTI + 20 + 1 + + + + + MACIVIR + MACIVIR + Inner VLAN inclusion register + 0x64 + 0x20 + read-write + 0x00000000 + + + VLT + VLT + 0 + 16 + + + VLC + VLC + 16 + 2 + + + VLP + VLP + 18 + 1 + + + CSVL + CSVL + 19 + 1 + + + VLTI + VLTI + 20 + 1 + + + + + MACQTxFCR + MACQTxFCR + Tx Queue flow control register + 0x70 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + FCB_BPA + 0 + 1 + + + TFE + TFE + 1 + 1 + + + PLT + PLT + 4 + 3 + + + DZPQ + DZPQ + 7 + 1 + + + PT + PT + 16 + 16 + + + + + MACRxFCR + MACRxFCR + Rx flow control register + 0x90 + 0x20 + read-write + 0x00000000 + + + RFE + RFE + 0 + 1 + + + UP + UP + 1 + 1 + + + + + MACISR + MACISR + Interrupt status register + 0xB0 + 0x20 + read-only + 0x00000000 + + + PHYIS + PHYIS + 3 + 1 + + + PMTIS + PMTIS + 4 + 1 + + + LPIIS + LPIIS + 5 + 1 + + + MMCIS + MMCIS + 8 + 1 + + + MMCRXIS + MMCRXIS + 9 + 1 + + + MMCTXIS + MMCTXIS + 10 + 1 + + + TSIS + TSIS + 12 + 1 + + + TXSTSIS + TXSTSIS + 13 + 1 + + + RXSTSIS + RXSTSIS + 14 + 1 + + + + + MACIER + MACIER + Interrupt enable register + 0xB4 + 0x20 + read-write + 0x00000000 + + + PHYIE + PHYIE + 3 + 1 + + + PMTIE + PMTIE + 4 + 1 + + + LPIIE + LPIIE + 5 + 1 + + + TSIE + TSIE + 12 + 1 + + + TXSTSIE + TXSTSIE + 13 + 1 + + + RXSTSIE + RXSTSIE + 14 + 1 + + + + + MACRxTxSR + MACRxTxSR + Rx Tx status register + 0xB8 + 0x20 + read-only + 0x00000000 + + + TJT + TJT + 0 + 1 + + + NCARR + NCARR + 1 + 1 + + + LCARR + LCARR + 2 + 1 + + + EXDEF + EXDEF + 3 + 1 + + + LCOL + LCOL + 4 + 1 + + + EXCOL + LCOL + 5 + 1 + + + RWT + RWT + 8 + 1 + + + + + MACPCSR + MACPCSR + PMT control status register + 0xC0 + 0x20 + 0x00000000 + + + PWRDWN + PWRDWN + 0 + 1 + read-write + + + MGKPKTEN + MGKPKTEN + 1 + 1 + read-write + + + RWKPKTEN + RWKPKTEN + 2 + 1 + read-write + + + MGKPRCVD + MGKPRCVD + 5 + 1 + read-only + + + RWKPRCVD + RWKPRCVD + 6 + 1 + read-only + + + GLBLUCAST + GLBLUCAST + 9 + 1 + read-write + + + RWKPFE + RWKPFE + 10 + 1 + read-write + + + RWKPTR + RWKPTR + 24 + 5 + read-write + + + RWKFILTRST + RWKFILTRST + 31 + 1 + read-write + + + + + MACRWKPFR + MACRWKPFR + Remove wakeup packet filter + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + WKUPFRMFTR + WKUPFRMFTR + 0 + 32 + + + + + MACLCSR + MACLCSR + LPI control status register + 0xD0 + 0x20 + 0x00000000 + + + TLPIEN + TLPIEN + 0 + 1 + read-only + + + TLPIEX + TLPIEX + 1 + 1 + read-only + + + RLPIEN + RLPIEN + 2 + 1 + read-only + + + RLPIEX + RLPIEX + 3 + 1 + read-only + + + TLPIST + TLPIST + 8 + 1 + read-only + + + RLPIST + RLPIST + 9 + 1 + read-only + + + LPIEN + LPIEN + 16 + 1 + read-write + + + PLS + PLS + 17 + 1 + read-write + + + PLSEN + PLSEN + 18 + 1 + read-write + + + LPITXA + LPITXA + 19 + 1 + read-write + + + LPITE + LPITE + 20 + 1 + read-write + + + LPITCSE + LPITCSE + 21 + 1 + read-write + + + + + MACLTCR + MACLTCR + LPI timers control register + 0xD4 + 0x20 + read-write + 0x03E80000 + + + TWT + TWT + 0 + 16 + + + LST + LST + 16 + 10 + + + + + MACLETR + MACLETR + LPI entry timer register + 0xD8 + 0x20 + read-write + 0x00000000 + + + LPIET + LPIET + 0 + 17 + + + + + MAC1USTCR + MAC1USTCR + 1-microsecond-tick counter + register + 0xDC + 0x20 + read-write + 0x00000000 + + + TIC_1US_CNTR + TIC_1US_CNTR + 0 + 12 + + + + + MACVR + MACVR + Version register + 0x110 + 0x20 + read-only + 0x00003041 + + + SNPSVER + SNPSVER + 0 + 8 + + + USERVER + USERVER + 8 + 8 + + + + + MACHWF1R + MACHWF1R + HW feature 1 register + 0x120 + 0x20 + read-only + 0x11841904 + + + RXFIFOSIZE + RXFIFOSIZE + 0 + 5 + + + TXFIFOSIZE + TXFIFOSIZE + 6 + 5 + + + OSTEN + OSTEN + 11 + 1 + + + PTOEN + PTOEN + 12 + 1 + + + ADVTHWORD + ADVTHWORD + 13 + 1 + + + DCBEN + DCBEN + 16 + 1 + + + SPHEN + SPHEN + 17 + 1 + + + TSOEN + TSOEN + 18 + 1 + + + DBGMEMA + DBGMEMA + 19 + 1 + + + AVSEL + AVSEL + 20 + 1 + + + HASHTBLSZ + HASHTBLSZ + 24 + 2 + + + L3L4FNUM + L3L4FNUM + 27 + 4 + + + + + MACHWF2R + MACHWF2R + HW feature 2 register + 0x124 + 0x20 + read-only + 0x41000000 + + + RXQCNT + RXQCNT + 0 + 4 + + + TXQCNT + TXQCNT + 6 + 4 + + + RXCHCNT + RXCHCNT + 12 + 4 + + + TXCHCNT + TXCHCNT + 18 + 4 + + + PPSOUTNUM + PPSOUTNUM + 24 + 3 + + + AUXSNAPNUM + AUXSNAPNUM + 28 + 3 + + + + + MACMDIOAR + MACMDIOAR + MDIO address register + 0x200 + 0x20 + read-write + 0x00000000 + + + MB + MB + 0 + 1 + + + C45E + C45E + 1 + 1 + + + GOC + GOC + 2 + 2 + + + SKAP + SKAP + 4 + 1 + + + CR + CR + 8 + 4 + + + NTC + NTC + 12 + 3 + + + RDA + RDA + 16 + 5 + + + PA + PA + 21 + 5 + + + BTB + BTB + 26 + 1 + + + PSE + PSE + 27 + 1 + + + + + MACMDIODR + MACMDIODR + MDIO data register + 0x204 + 0x20 + read-write + 0x00000000 + + + MD + MD + 0 + 16 + + + RA + RA + 16 + 16 + + + + + MACARPAR + MACARPAR + ARP address register + 0xAE0 + 0x20 + read-write + 0x00000000 + + + ARPPA + ARPPA + 0 + 32 + + + + + MACA0HR + MACA0HR + Address 0 high register + 0x300 + 0x20 + 0x8000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + read-write + + + AE + AE + 31 + 1 + read-only + + + + + MACA0LR + MACA0LR + Address 0 low register + 0x304 + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA1LR + MACA1LR + Address 1 low register + 0x30C + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA2LR + MACA2LR + Address 2 low register + 0x314 + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA3LR + MACA3LR + Address 3 low register + 0x31C + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA1HR + MACA1HR + Address 1 high register + 0x308 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA2HR + MACA2HR + Address 2 high register + 0x310 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA3HR + MACA3HR + Address 3 high register + 0x318 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MMC_CONTROL + MMC_CONTROL + MMC control register + 0x700 + 0x20 + read-write + 0x00000000 + + + CNTRST + CNTRST + 0 + 1 + + + CNTSTOPRO + CNTSTOPRO + 1 + 1 + + + RSTONRD + RSTONRD + 2 + 1 + + + CNTFREEZ + CNTFREEZ + 3 + 1 + + + CNTPRST + CNTPRST + 4 + 1 + + + CNTPRSTLVL + CNTPRSTLVL + 5 + 1 + + + UCDBC + UCDBC + 8 + 1 + + + + + MMC_RX_INTERRUPT + MMC_RX_INTERRUPT + MMC Rx interrupt register + 0x704 + 0x20 + read-only + 0x00000000 + + + RXCRCERPIS + RXCRCERPIS + 5 + 1 + + + RXALGNERPIS + RXALGNERPIS + 6 + 1 + + + RXUCGPIS + RXUCGPIS + 17 + 1 + + + RXLPIUSCIS + RXLPIUSCIS + 26 + 1 + + + RXLPITRCIS + RXLPITRCIS + 27 + 1 + + + + + MMC_TX_INTERRUPT + MMC_TX_INTERRUPT + MMC Tx interrupt register + 0x708 + 0x20 + read-only + 0x00000000 + + + TXSCOLGPIS + TXSCOLGPIS + 14 + 1 + + + TXMCOLGPIS + TXMCOLGPIS + 15 + 1 + + + TXGPKTIS + TXGPKTIS + 21 + 1 + + + TXLPIUSCIS + TXLPIUSCIS + 26 + 1 + + + TXLPITRCIS + TXLPITRCIS + 27 + 1 + + + + + MMC_RX_INTERRUPT_MASK + MMC_RX_INTERRUPT_MASK + MMC Rx interrupt mask register + 0x70C + 0x20 + 0x00000000 + + + RXCRCERPIM + RXCRCERPIM + 5 + 1 + read-write + + + RXALGNERPIM + RXALGNERPIM + 6 + 1 + read-write + + + RXUCGPIM + RXUCGPIM + 17 + 1 + read-write + + + RXLPIUSCIM + RXLPIUSCIM + 26 + 1 + read-write + + + RXLPITRCIM + RXLPITRCIM + 27 + 1 + read-only + + + + + MMC_TX_INTERRUPT_MASK + MMC_TX_INTERRUPT_MASK + MMC Tx interrupt mask register + 0x710 + 0x20 + 0x00000000 + + + TXSCOLGPIM + TXSCOLGPIM + 14 + 1 + read-write + + + TXMCOLGPIM + TXMCOLGPIM + 15 + 1 + read-write + + + TXGPKTIM + TXGPKTIM + 21 + 1 + read-write + + + TXLPIUSCIM + TXLPIUSCIM + 26 + 1 + read-write + + + TXLPITRCIM + TXLPITRCIM + 27 + 1 + read-only + + + + + TX_SINGLE_COLLISION_GOOD_PACKETS + + TX_SINGLE_COLLISION_GOOD_PACKETS + Tx single collision good packets + register + 0x74C + 0x20 + read-only + 0x00000000 + + + TXSNGLCOLG + TXSNGLCOLG + 0 + 32 + + + + + TX_MULTIPLE_COLLISION_GOOD_PACKETS + + TX_MULTIPLE_COLLISION_GOOD_PACKETS + Tx multiple collision good packets + register + 0x750 + 0x20 + read-only + 0x00000000 + + + TXMULTCOLG + TXMULTCOLG + 0 + 32 + + + + + TX_PACKET_COUNT_GOOD + TX_PACKET_COUNT_GOOD + Tx packet count good register + 0x768 + 0x20 + read-only + 0x00000000 + + + TXPKTG + TXPKTG + 0 + 32 + + + + + RX_CRC_ERROR_PACKETS + RX_CRC_ERROR_PACKETS + Rx CRC error packets register + 0x794 + 0x20 + read-only + 0x00000000 + + + RXCRCERR + RXCRCERR + 0 + 32 + + + + + RX_ALIGNMENT_ERROR_PACKETS + RX_ALIGNMENT_ERROR_PACKETS + Rx alignment error packets + register + 0x798 + 0x20 + read-only + 0x00000000 + + + RXALGNERR + RXALGNERR + 0 + 32 + + + + + RX_UNICAST_PACKETS_GOOD + RX_UNICAST_PACKETS_GOOD + Rx unicast packets good + register + 0x7C4 + 0x20 + read-only + 0x00000000 + + + RXUCASTG + RXUCASTG + 0 + 32 + + + + + TX_LPI_USEC_CNTR + TX_LPI_USEC_CNTR + Tx LPI microsecond timer + register + 0x7EC + 0x20 + read-only + 0x00000000 + + + TXLPIUSC + TXLPIUSC + 0 + 32 + + + + + TX_LPI_TRAN_CNTR + TX_LPI_TRAN_CNTR + Tx LPI transition counter + register + 0x7F0 + 0x20 + read-only + 0x00000000 + + + TXLPITRC + TXLPITRC + 0 + 32 + + + + + RX_LPI_USEC_CNTR + RX_LPI_USEC_CNTR + Rx LPI microsecond counter + register + 0x7F4 + 0x20 + read-only + 0x00000000 + + + RXLPIUSC + RXLPIUSC + 0 + 32 + + + + + RX_LPI_TRAN_CNTR + RX_LPI_TRAN_CNTR + Rx LPI transition counter + register + 0x7F8 + 0x20 + read-only + 0x00000000 + + + RXLPITRC + RXLPITRC + 0 + 32 + + + + + MACL3L4C0R + MACL3L4C0R + L3 and L4 control 0 register + 0x900 + 0x20 + read-write + 0x00000000 + + + L3PEN0 + L3PEN0 + 0 + 1 + + + L3SAM0 + L3SAM0 + 2 + 1 + + + L3SAIM0 + L3SAIM0 + 3 + 1 + + + L3DAM0 + L3DAM0 + 4 + 1 + + + L3DAIM0 + L3DAIM0 + 5 + 1 + + + L3HSBM0 + L3HSBM0 + 6 + 5 + + + L3HDBM0 + L3HDBM0 + 11 + 5 + + + L4PEN0 + L4PEN0 + 16 + 1 + + + L4SPM0 + L4SPM0 + 18 + 1 + + + L4SPIM0 + L4SPIM0 + 19 + 1 + + + L4DPM0 + L4DPM0 + 20 + 1 + + + L4DPIM0 + L4DPIM0 + 21 + 1 + + + + + MACL4A0R + MACL4A0R + Layer4 address filter 0 + register + 0x904 + 0x20 + read-write + 0x00000000 + + + L4SP0 + L4SP0 + 0 + 16 + + + L4DP0 + L4DP0 + 16 + 16 + + + + + MACDR + MACDR + Debug register + 0x114 + 0x20 + read-only + 0x00000000 + + + RPESTS + RPESTS + 0 + 1 + + + RFCFCSTS + RFCFCSTS + 1 + 2 + + + TPESTS + TPESTS + 16 + 1 + + + TFCSTS + TFCSTS + 17 + 2 + + + + + MACL3A00R + MACL3A00R + MACL3A00R + 0x910 + 0x20 + read-write + 0x00000000 + + + L3A00 + L3A00 + 0 + 32 + + + + + MACL3A10R + MACL3A10R + Layer3 address 1 filter 0 + register + 0x914 + 0x20 + read-write + 0x00000000 + + + L3A10 + L3A10 + 0 + 32 + + + + + MACL3A20 + MACL3A20 + Layer3 Address 2 filter 0 + register + 0x918 + 0x20 + read-write + 0x00000000 + + + L3A20 + L3A20 + 0 + 32 + + + + + MACL3A30 + MACL3A30 + Layer3 Address 3 filter 0 + register + 0x91C + 0x20 + read-write + 0x00000000 + + + L3A30 + L3A30 + 0 + 32 + + + + + MACL3L4C1R + MACL3L4C1R + L3 and L4 control 1 register + 0x930 + 0x20 + read-write + 0x00000000 + + + L3PEN1 + L3PEN1 + 0 + 1 + + + L3SAM1 + L3SAM1 + 2 + 1 + + + L3SAIM1 + L3SAIM1 + 3 + 1 + + + L3DAM1 + L3DAM1 + 4 + 1 + + + L3DAIM1 + L3DAIM1 + 5 + 1 + + + L3HSBM1 + L3HSBM1 + 6 + 5 + + + L3HDBM1 + L3HDBM1 + 11 + 5 + + + L4PEN1 + L4PEN1 + 16 + 1 + + + L4SPM1 + L4SPM1 + 18 + 1 + + + L4SPIM1 + L4SPIM1 + 19 + 1 + + + L4DPM1 + L4DPM1 + 20 + 1 + + + L4DPIM1 + L4DPIM1 + 21 + 1 + + + + + MACL4A1R + MACL4A1R + Layer 4 address filter 1 + register + 0x934 + 0x20 + read-write + 0x00000000 + + + L4SP1 + L4SP1 + 0 + 16 + + + L4DP1 + L4DP1 + 16 + 16 + + + + + MACL3A01R + MACL3A01R + Layer3 address 0 filter 1 + Register + 0x940 + 0x20 + read-write + 0x00000000 + + + L3A01 + L3A01 + 0 + 32 + + + + + MACL3A11R + MACL3A11R + Layer3 address 1 filter 1 + register + 0x944 + 0x20 + read-write + 0x00000000 + + + L3A11 + L3A11 + 0 + 32 + + + + + MACL3A21R + MACL3A21R + Layer3 address 2 filter 1 + Register + 0x948 + 0x20 + read-write + 0x00000000 + + + L3A21 + L3A21 + 0 + 32 + + + + + MACL3A31R + MACL3A31R + Layer3 address 3 filter 1 + register + 0x94C + 0x20 + read-write + 0x00000000 + + + L3A31 + L3A31 + 0 + 32 + + + + + MACTSCR + MACTSCR + Timestamp control Register + 0xB00 + 0x20 + 0x00000200 + + + TSENA + TSENA + 0 + 1 + read-write + + + TSCFUPDT + TSCFUPDT + 1 + 1 + read-write + + + TSINIT + TSINIT + 2 + 1 + read-write + + + TSUPDT + TSUPDT + 3 + 1 + read-write + + + TSADDREG + TSADDREG + 5 + 1 + read-write + + + TSENALL + TSENALL + 8 + 1 + read-write + + + TSCTRLSSR + TSCTRLSSR + 9 + 1 + read-write + + + TSVER2ENA + TSVER2ENA + 10 + 1 + read-write + + + TSIPENA + TSIPENA + 11 + 1 + read-write + + + TSIPV6ENA + TSIPV6ENA + 12 + 1 + read-write + + + TSIPV4ENA + TSIPV4ENA + 13 + 1 + read-write + + + TSEVNTENA + TSEVNTENA + 14 + 1 + read-write + + + TSMSTRENA + TSMSTRENA + 15 + 1 + read-write + + + SNAPTYPSEL + SNAPTYPSEL + 16 + 2 + read-write + + + TSENMACADDR + TSENMACADDR + 18 + 1 + read-write + + + CSC + CSC + 19 + 1 + read-only + + + TXTSSTSM + TXTSSTSM + 24 + 1 + read-write + + + + + MACSSIR + MACSSIR + Sub-second increment register + 0xB04 + 0x20 + read-write + 0x00000000 + + + SNSINC + SNSINC + 8 + 8 + + + SSINC + SSINC + 16 + 8 + + + + + MACSTSR + MACSTSR + System time seconds register + 0xB08 + 0x20 + read-only + 0x00000000 + + + TSS + TSS + 0 + 32 + + + + + MACSTNR + MACSTNR + System time nanoseconds + register + 0xB0C + 0x20 + read-only + 0x00000000 + + + TSSS + TSSS + 0 + 31 + + + + + MACSTSUR + MACSTSUR + System time seconds update + register + 0xB10 + 0x20 + read-write + 0x00000000 + + + TSS + TSS + 0 + 32 + + + + + MACSTNUR + MACSTNUR + System time nanoseconds update + register + 0xB14 + 0x20 + read-write + 0x00000000 + + + TSSS + TSSS + 0 + 31 + + + ADDSUB + ADDSUB + 31 + 1 + + + + + MACTSAR + MACTSAR + Timestamp addend register + 0xB18 + 0x20 + read-write + 0x00000000 + + + TSAR + TSAR + 0 + 32 + + + + + MACTSSR + MACTSSR + Timestamp status register + 0xB20 + 0x20 + read-only + 0x00000000 + + + TSSOVF + TSSOVF + 0 + 1 + + + TSTARGT0 + TSTARGT0 + 1 + 1 + + + AUXTSTRIG + AUXTSTRIG + 2 + 1 + + + TSTRGTERR0 + TSTRGTERR0 + 3 + 1 + + + TXTSSIS + TXTSSIS + 15 + 1 + + + ATSSTN + ATSSTN + 16 + 4 + + + ATSSTM + ATSSTM + 24 + 1 + + + ATSNS + ATSNS + 25 + 5 + + + + + MACTxTSSNR + MACTxTSSNR + Tx timestamp status nanoseconds + register + 0xB30 + 0x20 + read-only + 0x00000000 + + + TXTSSLO + TXTSSLO + 0 + 31 + + + TXTSSMIS + TXTSSMIS + 31 + 1 + + + + + MACTxTSSSR + MACTxTSSSR + Tx timestamp status seconds + register + 0xB34 + 0x20 + read-only + 0x00000000 + + + TXTSSHI + TXTSSHI + 0 + 32 + + + + + MACACR + MACACR + Auxiliary control register + 0xB40 + 0x20 + read-write + 0x00000000 + + + ATSFC + ATSFC + 0 + 1 + + + ATSEN0 + ATSEN0 + 4 + 1 + + + ATSEN1 + ATSEN1 + 5 + 1 + + + ATSEN2 + ATSEN2 + 6 + 1 + + + ATSEN3 + ATSEN3 + 7 + 1 + + + + + MACATSNR + MACATSNR + Auxiliary timestamp nanoseconds + register + 0xB48 + 0x20 + read-only + 0x00000000 + + + AUXTSLO + AUXTSLO + 0 + 31 + + + + + MACATSSR + MACATSSR + Auxiliary timestamp seconds + register + 0xB4C + 0x20 + read-only + 0x00000000 + + + AUXTSHI + AUXTSHI + 0 + 32 + + + + + MACTSIACR + MACTSIACR + Timestamp Ingress asymmetric correction + register + 0xB50 + 0x20 + read-write + 0x00000000 + + + OSTIAC + OSTIAC + 0 + 32 + + + + + MACTSEACR + MACTSEACR + Timestamp Egress asymmetric correction + register + 0xB54 + 0x20 + read-write + 0x00000000 + + + OSTEAC + OSTEAC + 0 + 32 + + + + + MACTSICNR + MACTSICNR + Timestamp Ingress correction nanosecond + register + 0xB58 + 0x20 + read-write + 0x00000000 + + + TSIC + TSIC + 0 + 32 + + + + + MACTSECNR + MACTSECNR + Timestamp Egress correction nanosecond + register + 0xB5C + 0x20 + read-write + 0x00000000 + + + TSEC + TSEC + 0 + 32 + + + + + MACPPSCR + MACPPSCR + PPS control register + 0xB70 + 0x20 + read-write + 0x00000000 + + + PPSCTRL + PPSCTRL + 0 + 4 + + + PPSEN0 + PPSEN0 + 4 + 1 + + + TRGTMODSEL0 + TRGTMODSEL0 + 5 + 2 + + + + + MACPPSTTSR + MACPPSTTSR + PPS target time seconds + register + 0xB80 + 0x20 + read-write + 0x00000000 + + + TSTRH0 + TSTRH0 + 0 + 31 + + + + + MACPPSTTNR + MACPPSTTNR + PPS target time nanoseconds + register + 0xB84 + 0x20 + read-write + 0x00000000 + + + TTSL0 + TTSL0 + 0 + 31 + + + TRGTBUSY0 + TRGTBUSY0 + 31 + 1 + + + + + MACPPSIR + MACPPSIR + PPS interval register + 0xB88 + 0x20 + read-write + 0x00000000 + + + PPSINT0 + PPSINT0 + 0 + 32 + + + + + MACPPSWR + MACPPSWR + PPS width register + 0xB8C + 0x20 + read-write + 0x00000000 + + + PPSWIDTH0 + PPSWIDTH0 + 0 + 32 + + + + + MACPOCR + MACPOCR + PTP Offload control register + 0xBC0 + 0x20 + read-write + 0x00000000 + + + PTOEN + PTOEN + 0 + 1 + + + ASYNCEN + ASYNCEN + 1 + 1 + + + APDREQEN + APDREQEN + 2 + 1 + + + ASYNCTRIG + ASYNCTRIG + 4 + 1 + + + APDREQTRIG + APDREQTRIG + 5 + 1 + + + DRRDIS + DRRDIS + 6 + 1 + + + DN + DN + 8 + 8 + + + + + MACSPI0R + MACSPI0R + PTP Source Port Identity 0 + Register + 0xBC4 + 0x20 + read-write + 0x00000000 + + + SPI0 + SPI0 + 0 + 32 + + + + + MACSPI1R + MACSPI1R + PTP Source port identity 1 + register + 0xBC8 + 0x20 + read-write + 0x00000000 + + + SPI1 + SPI1 + 0 + 32 + + + + + MACSPI2R + MACSPI2R + PTP Source port identity 2 + register + 0xBCC + 0x20 + read-write + 0x00000000 + + + SPI2 + SPI2 + 0 + 16 + + + + + MACLMIR + MACLMIR + Log message interval register + 0xBD0 + 0x20 + read-write + 0x00000000 + + + LSI + LSI + 0 + 8 + + + DRSYNCR + DRSYNCR + 8 + 3 + + + LMPDRI + LMPDRI + 24 + 8 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA_STR0 + DMA1 Stream0 + 11 + + + DMA_STR1 + DMA1 Stream1 + 12 + + + DMA_STR2 + DMA1 Stream2 + 13 + + + DMA_STR3 + DMA1 Stream3 + 14 + + + DMA_STR4 + DMA1 Stream4 + 15 + + + DMA_STR5 + DMA1 Stream5 + 16 + + + DMA_STR6 + DMA1 Stream6 + 17 + + + DMA1_STR7 + DMA1 Stream7 + 47 + + + + LISR + LISR + low interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TCIF3 + Stream x transfer complete interrupt + flag (x = 3..0) + 27 + 1 + + + HTIF3 + Stream x half transfer interrupt flag + (x=3..0) + 26 + 1 + + + TEIF3 + Stream x transfer error interrupt flag + (x=3..0) + 25 + 1 + + + DMEIF3 + Stream x direct mode error interrupt + flag (x=3..0) + 24 + 1 + + + FEIF3 + Stream x FIFO error interrupt flag + (x=3..0) + 22 + 1 + + + TCIF2 + Stream x transfer complete interrupt + flag (x = 3..0) + 21 + 1 + + + HTIF2 + Stream x half transfer interrupt flag + (x=3..0) + 20 + 1 + + + TEIF2 + Stream x transfer error interrupt flag + (x=3..0) + 19 + 1 + + + DMEIF2 + Stream x direct mode error interrupt + flag (x=3..0) + 18 + 1 + + + FEIF2 + Stream x FIFO error interrupt flag + (x=3..0) + 16 + 1 + + + TCIF1 + Stream x transfer complete interrupt + flag (x = 3..0) + 11 + 1 + + + HTIF1 + Stream x half transfer interrupt flag + (x=3..0) + 10 + 1 + + + TEIF1 + Stream x transfer error interrupt flag + (x=3..0) + 9 + 1 + + + DMEIF1 + Stream x direct mode error interrupt + flag (x=3..0) + 8 + 1 + + + FEIF1 + Stream x FIFO error interrupt flag + (x=3..0) + 6 + 1 + + + TCIF0 + Stream x transfer complete interrupt + flag (x = 3..0) + 5 + 1 + + + HTIF0 + Stream x half transfer interrupt flag + (x=3..0) + 4 + 1 + + + TEIF0 + Stream x transfer error interrupt flag + (x=3..0) + 3 + 1 + + + DMEIF0 + Stream x direct mode error interrupt + flag (x=3..0) + 2 + 1 + + + FEIF0 + Stream x FIFO error interrupt flag + (x=3..0) + 0 + 1 + + + + + HISR + HISR + high interrupt status register + 0x4 + 0x20 + read-only + 0x00000000 + + + TCIF7 + Stream x transfer complete interrupt + flag (x=7..4) + 27 + 1 + + + HTIF7 + Stream x half transfer interrupt flag + (x=7..4) + 26 + 1 + + + TEIF7 + Stream x transfer error interrupt flag + (x=7..4) + 25 + 1 + + + DMEIF7 + Stream x direct mode error interrupt + flag (x=7..4) + 24 + 1 + + + FEIF7 + Stream x FIFO error interrupt flag + (x=7..4) + 22 + 1 + + + TCIF6 + Stream x transfer complete interrupt + flag (x=7..4) + 21 + 1 + + + HTIF6 + Stream x half transfer interrupt flag + (x=7..4) + 20 + 1 + + + TEIF6 + Stream x transfer error interrupt flag + (x=7..4) + 19 + 1 + + + DMEIF6 + Stream x direct mode error interrupt + flag (x=7..4) + 18 + 1 + + + FEIF6 + Stream x FIFO error interrupt flag + (x=7..4) + 16 + 1 + + + TCIF5 + Stream x transfer complete interrupt + flag (x=7..4) + 11 + 1 + + + HTIF5 + Stream x half transfer interrupt flag + (x=7..4) + 10 + 1 + + + TEIF5 + Stream x transfer error interrupt flag + (x=7..4) + 9 + 1 + + + DMEIF5 + Stream x direct mode error interrupt + flag (x=7..4) + 8 + 1 + + + FEIF5 + Stream x FIFO error interrupt flag + (x=7..4) + 6 + 1 + + + TCIF4 + Stream x transfer complete interrupt + flag (x=7..4) + 5 + 1 + + + HTIF4 + Stream x half transfer interrupt flag + (x=7..4) + 4 + 1 + + + TEIF4 + Stream x transfer error interrupt flag + (x=7..4) + 3 + 1 + + + DMEIF4 + Stream x direct mode error interrupt + flag (x=7..4) + 2 + 1 + + + FEIF4 + Stream x FIFO error interrupt flag + (x=7..4) + 0 + 1 + + + + + LIFCR + LIFCR + low interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTCIF3 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 27 + 1 + + + CHTIF3 + Stream x clear half transfer interrupt + flag (x = 3..0) + 26 + 1 + + + CTEIF3 + Stream x clear transfer error interrupt + flag (x = 3..0) + 25 + 1 + + + CDMEIF3 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 24 + 1 + + + CFEIF3 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 22 + 1 + + + CTCIF2 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 21 + 1 + + + CHTIF2 + Stream x clear half transfer interrupt + flag (x = 3..0) + 20 + 1 + + + CTEIF2 + Stream x clear transfer error interrupt + flag (x = 3..0) + 19 + 1 + + + CDMEIF2 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 18 + 1 + + + CFEIF2 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 16 + 1 + + + CTCIF1 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 11 + 1 + + + CHTIF1 + Stream x clear half transfer interrupt + flag (x = 3..0) + 10 + 1 + + + CTEIF1 + Stream x clear transfer error interrupt + flag (x = 3..0) + 9 + 1 + + + CDMEIF1 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 8 + 1 + + + CFEIF1 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 6 + 1 + + + CTCIF0 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 5 + 1 + + + CHTIF0 + Stream x clear half transfer interrupt + flag (x = 3..0) + 4 + 1 + + + CTEIF0 + Stream x clear transfer error interrupt + flag (x = 3..0) + 3 + 1 + + + CDMEIF0 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 2 + 1 + + + CFEIF0 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 0 + 1 + + + + + HIFCR + HIFCR + high interrupt flag clear + register + 0xC + 0x20 + read-write + 0x00000000 + + + CTCIF7 + Stream x clear transfer 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16 + + + + + CH3DATINR + CH3DATINR + CH3DATINR + 0x70 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH3DLYR + CH3DLYR + channel y delay register + 0x74 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + CH4CFGR1 + CH4CFGR1 + CH4CFGR1 + 0x80 + 0x20 + read-write + 0x0 + + + DATPACK + DATPACK + 14 + 2 + + + DATMPX + DATMPX + 12 + 2 + + + CHINSEL + CHINSEL + 8 + 1 + + + CHEN + CHEN + 7 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + SCDEN + SCDEN + 5 + 1 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SITP + SITP + 0 + 2 + + + + + CH4CFGR2 + CH4CFGR2 + CH4CFGR2 + 0x84 + 0x20 + read-write + 0x0 + + + OFFSET + OFFSET + 8 + 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + CH4AWSCDR + CH4AWSCDR + CH4AWSCDR + 0x88 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CH4WDATR + CH4WDATR + CH4WDATR + 0x8C + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CH4DATINR + CH4DATINR + CH4DATINR + 0x90 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH4DLYR + CH4DLYR + channel y delay register + 0x94 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + CH5CFGR1 + CH5CFGR1 + CH5CFGR1 + 0xA0 + 0x20 + read-write + 0x0 + + + DATPACK + DATPACK + 14 + 2 + + + DATMPX + DATMPX + 12 + 2 + + + CHINSEL + CHINSEL + 8 + 1 + + + CHEN + CHEN + 7 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + SCDEN + SCDEN + 5 + 1 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SITP + SITP + 0 + 2 + + + + + CH5CFGR2 + CH5CFGR2 + CH5CFGR2 + 0xA4 + 0x20 + read-write + 0x0 + + + OFFSET + OFFSET + 8 + 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + CH5AWSCDR + CH5AWSCDR + CH5AWSCDR + 0xA8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CH5WDATR + CH5WDATR + CH5WDATR + 0xAC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CH5DATINR + CH5DATINR + CH5DATINR + 0xB0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH5DLYR + CH5DLYR + channel y delay register + 0xB4 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + CH6CFGR1 + CH6CFGR1 + CH6CFGR1 + 0xC0 + 0x20 + read-write + 0x0 + + + DATPACK + DATPACK + 14 + 2 + + + DATMPX + DATMPX + 12 + 2 + + + CHINSEL + CHINSEL + 8 + 1 + + + CHEN + CHEN + 7 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + SCDEN + SCDEN + 5 + 1 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SITP + SITP + 0 + 2 + + + + + CH6CFGR2 + CH6CFGR2 + CH6CFGR2 + 0xC4 + 0x20 + read-write + 0x0 + + + OFFSET + OFFSET + 8 + 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + CH6AWSCDR + CH6AWSCDR + CH6AWSCDR + 0xC8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CH6WDATR + CH6WDATR + CH6WDATR + 0xCC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CH6DATINR + CH6DATINR + CH6DATINR + 0xD0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH6DLYR + CH6DLYR + channel y delay register + 0xD4 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + CH7CFGR1 + CH7CFGR1 + CH7CFGR1 + 0xE0 + 0x20 + read-write + 0x0 + + + DATPACK + DATPACK + 14 + 2 + + + DATMPX + DATMPX + 12 + 2 + + + CHINSEL + CHINSEL + 8 + 1 + + + CHEN + CHEN + 7 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + SCDEN + SCDEN + 5 + 1 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SITP + SITP + 0 + 2 + + + + + CH7CFGR2 + CH7CFGR2 + CH7CFGR2 + 0xE4 + 0x20 + read-write + 0x0 + + + OFFSET + OFFSET + 8 + 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + CH7AWSCDR + CH7AWSCDR + CH7AWSCDR + 0xE8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CH7WDATR + CH7WDATR + CH7WDATR + 0xEC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CH7DATINR + CH7DATINR + CH7DATINR + 0xF0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH7DLYR + CH7DLYR + channel y delay register + 0xF4 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_FLT0CR1 + DFSDM_FLT0CR1 + control register 1 + 0x100 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT0CR2 + DFSDM_FLT0CR2 + control register 2 + 0x104 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT0ISR + DFSDM_FLT0ISR + interrupt and status register + 0x108 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT0ICR + DFSDM_FLT0ICR + interrupt flag clear register + 0x10C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT0JCHGR + DFSDM_FLT0JCHGR + injected channel group selection + register + 0x110 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT0FCR + DFSDM_FLT0FCR + filter control register + 0x114 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT0JDATAR + DFSDM_FLT0JDATAR + data register for injected + group + 0x118 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT0RDATAR + DFSDM_FLT0RDATAR + data register for the regular + channel + 0x11C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT0AWHTR + DFSDM_FLT0AWHTR + analog watchdog high threshold + register + 0x120 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT0AWLTR + DFSDM_FLT0AWLTR + analog watchdog low threshold + register + 0x124 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT0AWSR + DFSDM_FLT0AWSR + analog watchdog status + register + 0x128 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT0AWCFR + DFSDM_FLT0AWCFR + analog watchdog clear flag + register + 0x12C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT0EXMAX + DFSDM_FLT0EXMAX + Extremes detector maximum + register + 0x130 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT0EXMIN + DFSDM_FLT0EXMIN + Extremes detector minimum + register + 0x134 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT0CNVTIMR + DFSDM_FLT0CNVTIMR + conversion timer register + 0x138 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT1CR1 + DFSDM_FLT1CR1 + control register 1 + 0x180 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT1CR2 + DFSDM_FLT1CR2 + control register 2 + 0x184 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT1ISR + DFSDM_FLT1ISR + interrupt and status register + 0x188 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT1ICR + DFSDM1_ICR + interrupt flag clear register + 0x18C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT1CHGR + DFSDM_FLT1JCHGR + injected channel group selection + register + 0x190 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT1FCR + DFSDM1_FCR + filter control register + 0x194 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT1JDATAR + DFSDM_FLT1JDATAR + data register for injected + group + 0x198 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT1RDATAR + DFSDM_FLT1RDATAR + data register for the regular + channel + 0x19C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT1AWHTR + DFSDM_FLT1AWHTR + analog watchdog high threshold + register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT1AWLTR + DFSDM_FLT1AWLTR + analog watchdog low threshold + register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT1AWSR + DFSDM_FLT1AWSR + analog watchdog status + register + 0x1A8 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT1AWCFR + DFSDM_FLT1AWCFR + analog watchdog clear flag + register + 0x1AC + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT1EXMAX + DFSDM_FLT1EXMAX + Extremes detector maximum + register + 0x1B0 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT1EXMIN + DFSDM_FLT1EXMIN + Extremes detector minimum + register + 0x1B4 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT1CNVTIMR + DFSDM_FLT1CNVTIMR + conversion timer register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT2CR1 + DFSDM_FLT2CR1 + control register 1 + 0x200 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT2CR2 + DFSDM_FLT2CR2 + control register 2 + 0x204 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT2ISR + DFSDM_FLT2ISR + interrupt and status register + 0x208 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT2ICR + DFSDM_FLT2ICR + interrupt flag clear register + 0x20C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT2JCHGR + DFSDM_FLT2JCHGR + injected channel group selection + register + 0x210 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT2FCR + DFSDM_FLT2FCR + filter control register + 0x214 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT2JDATAR + DFSDM_FLT2JDATAR + data register for injected + group + 0x218 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT2RDATAR + DFSDM_FLT2RDATAR + data register for the regular + channel + 0x21C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT2AWHTR + DFSDM_FLT2AWHTR + analog watchdog high threshold + register + 0x220 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT2AWLTR + DFSDM_FLT2AWLTR + analog watchdog low threshold + register + 0x224 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT2AWSR + DFSDM_FLT2AWSR + analog watchdog status + register + 0x228 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT2AWCFR + DFSDM_FLT2AWCFR + analog watchdog clear flag + register + 0x22C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT2EXMAX + DFSDM_FLT2EXMAX + Extremes detector maximum + register + 0x230 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT2EXMIN + DFSDM_FLT2EXMIN + Extremes detector minimum + register + 0x234 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT2CNVTIMR + DFSDM_FLT2CNVTIMR + conversion timer register + 0x238 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT3CR1 + DFSDM_FLT3CR1 + control register 1 + 0x280 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT3CR2 + DFSDM_FLT3CR2 + control register 2 + 0x284 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT3ISR + DFSDM_FLT3ISR + interrupt and status register + 0x288 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT3ICR + DFSDM_FLT3ICR + interrupt flag clear register + 0x28C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT3JCHGR + DFSDM_FLT3JCHGR + injected channel group selection + register + 0x290 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT3FCR + DFSDM_FLT3FCR + filter control register + 0x294 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT3JDATAR + DFSDM_FLT3JDATAR + data register for injected + group + 0x298 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT3RDATAR + DFSDM_FLT3RDATAR + data register for the regular + channel + 0x29C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT3AWHTR + DFSDM_FLT3AWHTR + analog watchdog high threshold + register + 0x2A0 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT3AWLTR + DFSDM_FLT3AWLTR + analog watchdog low threshold + register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT3AWSR + DFSDM_FLT3AWSR + analog watchdog status + register + 0x2A8 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT3AWCFR + DFSDM_FLT3AWCFR + analog watchdog clear flag + register + 0x2AC + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT3EXMAX + DFSDM_FLT3EXMAX + Extremes detector maximum + register + 0x2B0 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT3EXMIN + DFSDM_FLT3EXMIN + Extremes detector minimum + register + 0x2B4 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT3CNVTIMR + DFSDM_FLT3CNVTIMR + conversion timer register + 0x2B8 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + + + TIM16 + General-purpose-timers + TIMs + 0x40014400 + + 0x0 + 0x400 + registers + + + TIM16 + TIM16 global interrupt + 117 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + TIM16_AF1 + TIM16_AF1 + TIM16 alternate function register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK1E + BRK dfsdm1_break[1] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + + + TIM16_TISEL + TIM16_TISEL + TIM16 input selection register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + selects TI1[0] to TI1[15] + input + 0 + 4 + + + + + + + TIM17 + General-purpose-timers + TIMs + 0x40014800 + + 0x0 + 0x400 + registers + + + TIM17 + TIM17 global interrupt + 118 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + TIM17_AF1 + TIM17_AF1 + TIM17 alternate function register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK1E + BRK dfsdm1_break[1] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + + + TIM17_TISEL + TIM17_TISEL + TIM17 input selection register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + selects TI1[0] to TI1[15] + input + 0 + 4 + + + + + + + TIM15 + General purpose timers + TIMs + 0x40014000 + + 0x0 + 0x400 + registers + + + TIM15 + TIM15 global interrupt + 116 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + MMS + Master mode selection + 4 + 3 + + + TI1S + TI1 selection + 7 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + TS_2_0 + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + SMS_3 + Slave mode selection bit 3 + 16 + 1 + + + TS_4_3 + Trigger selection - bit + 4:3 + 20 + 2 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC1M_3 + Output Compare 1 mode bit + 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode bit + 3 + 24 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C 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value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFIFO threshold flag + 27 + 1 + + + RXFT + RXFIFO threshold flag + 26 + 1 + + + TCBGT + Transmission complete before guard time + flag + 25 + 1 + + + RXFF + RXFIFO Full + 24 + 1 + + + TXFE + TXFIFO Empty + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + SPI slave underrun error + flag + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + SPI slave underrun clear + flag + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear + flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear + flag + 8 + 1 + + + TCBGTC + Transmission complete before Guard time + clear flag + 7 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + TXFECF + TXFIFO empty clear flag + 5 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + Clock prescaler + 0 + 4 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + UART4 + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + UART7 + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + TIM1 + Advanced-timers + TIM + 0x40010000 + + 0x0 + 0x400 + registers + + + TIM1_BRK + TIM1 break interrupt + 24 + + + TIM1_UP + TIM1 update interrupt + 25 + + + TIM1_TRG_COM + TIM1 trigger and commutation + 26 + + + TIM_CC + TIM1 capture / compare + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 + 18 + 1 + + + OIS5 + Output Idle state 5 + 16 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + TS + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + ETF + External trigger filter + 8 + 4 + + + ETPS + External trigger prescaler + 12 + 2 + + + ECE + External clock enable + 14 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + SMS_3 + Slave mode selection - bit + 3 + 16 + 1 + + + TS_4_3 + Trigger selection - bit + 4:3 + 20 + 2 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + SBIF + System Break interrupt + flag + 13 + 1 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + TG + Trigger generation + 6 + 1 + + + BG + Break generation + 7 + 1 + + + B2G + Break 2 generation + 8 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC1M_3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC3M_3 + Output Compare 3 mode - bit + 3 + 16 + 1 + + + OC4M_4 + Output Compare 4 mode - bit + 3 + 24 + 1 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4NP + Capture/Compare 4 complementary output + polarity + 15 + 1 + + + CC5E + Capture/Compare 5 output + enable + 16 + 1 + + + CC5P + Capture/Compare 5 output + polarity + 17 + 1 + + + CC6E + Capture/Compare 6 output + enable + 20 + 1 + + + CC6P + Capture/Compare 6 output + polarity + 21 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BK2F + Break 2 filter + 20 + 4 + + + BK2E + Break 2 enable + 24 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 3 (output 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Tx Event FIFO Element + Lost. + 25 + 1 + + + + + FDCAN_TXEFA + FDCAN_TXEFA + FDCAN Tx Event FIFO Acknowledge + Register + 0xF8 + 0x20 + read-write + 0x00000000 + + + EFAI + Event FIFO Acknowledge + Index + 0 + 5 + + + + + FDCAN_TTTMC + FDCAN_TTTMC + FDCAN TT Trigger Memory Configuration + Register + 0x100 + 0x20 + read-write + 0x00000000 + + + TMSA + Trigger Memory Start + Address + 2 + 14 + + + TME + Trigger Memory Elements + 16 + 7 + + + + + FDCAN_TTRMC + FDCAN_TTRMC + FDCAN TT Reference Message Configuration + Register + 0x104 + 0x20 + read-write + 0x00000000 + + + RID + Reference Identifier. + 0 + 29 + + + XTD + Extended Identifier + 30 + 1 + + + RMPS + Reference Message Payload + Select + 31 + 1 + + + + + FDCAN_TTOCF + FDCAN_TTOCF + FDCAN TT Operation Configuration + Register + 0x108 + 0x20 + read-write + 0x00000000 + + + OM + Operation Mode + 0 + 2 + + + GEN + Gap Enable + 3 + 1 + + + TM + Time Master + 4 + 1 + + + LDSDL + LD of Synchronization Deviation + Limit + 5 + 3 + + + IRTO + Initial Reference Trigger + Offset + 8 + 7 + + + EECS + Enable External Clock + Synchronization + 15 + 1 + + + AWL + Application Watchdog Limit + 16 + 8 + + + EGTF + Enable Global Time + Filtering + 24 + 1 + + + ECC + Enable Clock Calibration + 25 + 1 + + + EVTP + Event Trigger Polarity + 26 + 1 + + + + + FDCAN_TTMLM + FDCAN_TTMLM + FDCAN TT Matrix Limits + Register + 0x10C + 0x20 + read-write + 0x00000000 + + + CCM + Cycle Count Max + 0 + 6 + + + CSS + Cycle Start + Synchronization + 6 + 2 + + + TXEW + Tx Enable Window + 8 + 4 + + + ENTT + Expected Number of Tx + Triggers + 16 + 12 + + + + + FDCAN_TURCF + FDCAN_TURCF + FDCAN TUR Configuration + Register + 0x110 + 0x20 + read-write + 0x00000000 + + + NCL + Numerator Configuration + Low. + 0 + 16 + + + DC + Denominator Configuration. + 16 + 14 + + + ELT + Enable Local Time + 31 + 1 + + + + + FDCAN_TTOCN + FDCAN_TTOCN + FDCAN TT Operation Control + Register + 0x114 + 0x20 + read-write + 0x00000000 + + + SGT + Set Global time + 0 + 1 + + + ECS + External Clock + Synchronization + 1 + 1 + + + SWP + Stop Watch Polarity + 2 + 1 + + + SWS + Stop Watch Source. + 3 + 2 + + + RTIE + Register Time Mark Interrupt Pulse + Enable + 5 + 1 + + + TMC + Register Time Mark Compare + 6 + 2 + + + TTIE + Trigger Time Mark Interrupt Pulse + Enable + 8 + 1 + + + GCS + Gap Control Select + 9 + 1 + + + FGP + Finish Gap. + 10 + 1 + + + TMG + Time Mark Gap + 11 + 1 + + + NIG + Next is Gap + 12 + 1 + + + ESCN + External Synchronization + Control + 13 + 1 + + + LCKC + TT Operation Control Register + Locked + 15 + 1 + + + + + CAN_TTGTP + CAN_TTGTP + FDCAN TT Global Time Preset + Register + 0x118 + 0x20 + read-write + 0x00000000 + + + NCL + Time Preset + 0 + 16 + + + CTP + Cycle Time Target Phase + 16 + 16 + + + + + FDCAN_TTTMK + FDCAN_TTTMK + FDCAN TT Time Mark Register + 0x11C + 0x20 + read-write + 0x00000000 + + + TM + Time Mark + 0 + 16 + + + TICC + Time Mark Cycle Code + 16 + 7 + + + LCKM + TT Time Mark Register + Locked + 31 + 1 + + + + + FDCAN_TTIR + FDCAN_TTIR + FDCAN TT Interrupt Register + 0x120 + 0x20 + read-write + 0x00000000 + + + SBC + Start of Basic Cycle + 0 + 1 + + + SMC + Start of Matrix Cycle + 1 + 1 + + + CSM + Change of Synchronization + Mode + 2 + 1 + + + SOG + Start of Gap + 3 + 1 + + + RTMI + Register Time Mark + Interrupt. + 4 + 1 + + + TTMI + Trigger Time Mark Event + Internal + 5 + 1 + + + SWE + Stop Watch Event + 6 + 1 + + + GTW + Global Time Wrap + 7 + 1 + + + GTD + Global Time Discontinuity + 8 + 1 + + + GTE + Global Time Error + 9 + 1 + + + TXU + Tx Count Underflow + 10 + 1 + + + TXO + Tx Count Overflow + 11 + 1 + + + SE1 + Scheduling Error 1 + 12 + 1 + + + SE2 + Scheduling Error 2 + 13 + 1 + + + ELC + Error Level Changed. + 14 + 1 + + + IWTG + Initialization Watch + Trigger + 15 + 1 + + + WT + Watch Trigger + 16 + 1 + + + AW + Application Watchdog + 17 + 1 + + + CER + Configuration Error + 18 + 1 + + + + + FDCAN_TTIE + FDCAN_TTIE + FDCAN TT Interrupt Enable + Register + 0x124 + 0x20 + read-write + 0x00000000 + + + SBCE + Start of Basic Cycle Interrupt + Enable + 0 + 1 + + + SMCE + Start of Matrix Cycle Interrupt + Enable + 1 + 1 + + + CSME + Change of Synchronization Mode Interrupt + Enable + 2 + 1 + + + SOGE + Start of Gap Interrupt + Enable + 3 + 1 + + + RTMIE + Register Time Mark Interrupt + Enable + 4 + 1 + + + TTMIE + Trigger Time Mark Event Internal + Interrupt Enable + 5 + 1 + + + SWEE + Stop Watch Event Interrupt + Enable + 6 + 1 + + + GTWE + Global Time Wrap Interrupt + Enable + 7 + 1 + + + GTDE + Global Time Discontinuity Interrupt + Enable + 8 + 1 + + + GTEE + Global Time Error Interrupt + Enable + 9 + 1 + + + TXUE + Tx Count Underflow Interrupt + Enable + 10 + 1 + + + TXOE + Tx Count Overflow Interrupt + Enable + 11 + 1 + + + SE1E + Scheduling Error 1 Interrupt + Enable + 12 + 1 + + + SE2E + Scheduling Error 2 Interrupt + Enable + 13 + 1 + + + ELCE + Change Error Level Interrupt + Enable + 14 + 1 + + + IWTGE + Initialization Watch Trigger Interrupt + Enable + 15 + 1 + + + WTE + Watch Trigger Interrupt + Enable + 16 + 1 + + + AWE + Application Watchdog Interrupt + Enable + 17 + 1 + + + CERE + Configuration Error Interrupt + Enable + 18 + 1 + + + + + FDCAN_TTILS + FDCAN_TTILS + FDCAN TT Interrupt Line Select + Register + 0x128 + 0x20 + read-write + 0x00000000 + + + SBCL + Start of Basic Cycle Interrupt + Line + 0 + 1 + + + SMCL + Start of Matrix Cycle Interrupt + Line + 1 + 1 + + + CSML + Change of Synchronization Mode Interrupt + Line + 2 + 1 + + + SOGL + Start of Gap Interrupt + Line + 3 + 1 + + + RTMIL + Register Time Mark Interrupt + Line + 4 + 1 + + + TTMIL + Trigger Time Mark Event Internal + Interrupt Line + 5 + 1 + + + SWEL + Stop Watch Event Interrupt + Line + 6 + 1 + + + GTWL + Global Time Wrap Interrupt + Line + 7 + 1 + + + GTDL + Global Time Discontinuity Interrupt + Line + 8 + 1 + + + GTEL + Global Time Error Interrupt + Line + 9 + 1 + + + TXUL + Tx Count Underflow Interrupt + Line + 10 + 1 + + + TXOL + Tx Count Overflow Interrupt + Line + 11 + 1 + + + SE1L + Scheduling Error 1 Interrupt + Line + 12 + 1 + + + SE2L + Scheduling Error 2 Interrupt + Line + 13 + 1 + + + ELCL + Change Error Level Interrupt + Line + 14 + 1 + + + IWTGL + Initialization Watch Trigger Interrupt + Line + 15 + 1 + + + WTL + Watch Trigger Interrupt + Line + 16 + 1 + + + AWL + Application Watchdog Interrupt + Line + 17 + 1 + + + CERL + Configuration Error Interrupt + Line + 18 + 1 + + + + + FDCAN_TTOST + FDCAN_TTOST + FDCAN TT Operation Status + Register + 0x12C + 0x20 + read-write + 0x00000000 + + + EL + Error Level + 0 + 2 + + + MS + Master State. + 2 + 2 + + + SYS + Synchronization State + 4 + 2 + + + GTP + Quality of Global Time + Phase + 6 + 1 + + + QCS + Quality of Clock Speed + 7 + 1 + + + RTO + Reference Trigger Offset + 8 + 8 + + + WGTD + Wait for Global Time + Discontinuity + 22 + 1 + + + GFI + Gap Finished Indicator. + 23 + 1 + + + TMP + Time Master Priority + 24 + 3 + + + GSI + Gap Started Indicator. + 27 + 1 + + + WFE + Wait for Event + 28 + 1 + + + AWE + Application Watchdog Event + 29 + 1 + + + WECS + Wait for External Clock + Synchronization + 30 + 1 + + + SPL + Schedule Phase Lock + 31 + 1 + + + + + FDCAN_TURNA + FDCAN_TURNA + FDCAN TUR Numerator Actual + Register + 0x130 + 0x20 + read-only + 0x00000000 + + + NAV + Numerator Actual Value + 0 + 18 + + + + + FDCAN_TTLGT + FDCAN_TTLGT + FDCAN TT Local and Global Time + Register + 0x134 + 0x20 + read-only + 0x00000000 + + + LT + Local Time + 0 + 16 + + + GT + Global Time + 16 + 16 + + + + + FDCAN_TTCTC + FDCAN_TTCTC + FDCAN TT Cycle Time and Count + Register + 0x138 + 0x20 + read-only + 0x00000000 + + + CT + Cycle Time + 0 + 16 + + + CC + Cycle Count + 16 + 6 + + + + + FDCAN_TTCPT + FDCAN_TTCPT + FDCAN TT Capture Time Register + 0x13C + 0x20 + read-only + 0x00000000 + + + CT + Cycle Count Value + 0 + 6 + + + SWV + Stop Watch Value + 16 + 16 + + + + + FDCAN_TTCSM + FDCAN_TTCSM + FDCAN TT Cycle Sync Mark + Register + 0x140 + 0x20 + read-only + 0x00000000 + + + CSM + Cycle Sync Mark + 0 + 16 + + + + + FDCAN_TTTS + FDCAN_TTTS + FDCAN TT Trigger Select + Register + 0x300 + 0x20 + read-write + 0x00000000 + + + SWTDEL + Stop watch trigger input + selection + 0 + 2 + + + EVTSEL + Event trigger input + selection + 4 + 2 + + + + + + + FDCAN2 + 0x4000A400 + + FDCAN2_IT0 + FDCAN2 Interrupt 0 + 20 + + + FDCAN2_IT1 + FDCAN2 Interrupt 1 + 22 + + + + CAN_CCU + CCU registers + FDCAN + 0x4000A800 + + 0x0 + 0x400 + registers + + + + CREL + CREL + Clock Calibration Unit Core Release + Register + 0x0 + 0x20 + read-write + 0x00000000 + + + DAY + Time Stamp Day + 0 + 8 + + + MON + Time Stamp Month + 8 + 8 + + + YEAR + Time Stamp Year + 16 + 4 + + + SUBSTEP + Sub-step of Core Release + 20 + 4 + + + STEP + Step of Core Release + 24 + 4 + + + REL + Core Release + 28 + 4 + + + + + CCFG + CCFG + Calibration Configuration + Register + 0x4 + 0x20 + read-write + 0x00000000 + + + TQBT + Time Quanta per Bit Time + 0 + 5 + + + BCC + Bypass Clock Calibration + 6 + 1 + + + CFL + Calibration Field Length + 7 + 1 + + + OCPM + Oscillator Clock Periods + Minimum + 8 + 8 + + + CDIV + Clock Divider + 16 + 4 + + + SWR + Software Reset + 31 + 1 + + + + + CSTAT + CSTAT + Calibration Status Register + 0x8 + 0x20 + read-write + 0x00000000 + + + OCPC + Oscillator Clock Period + Counter + 0 + 18 + + + TQC + Time Quanta Counter + 18 + 11 + + + CALS + Calibration State + 30 + 2 + + + + + CWD + CWD + Calibration Watchdog Register + 0xC + 0x20 + read-write + 0x00000000 + + + WDC + WDC + 0 + 16 + + + WDV + WDV + 16 + 16 + + + + + IR + IR + Clock Calibration Unit Interrupt + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CWE + Calibration Watchdog Event + 0 + 1 + + + CSC + Calibration State Changed + 1 + 1 + + + + + IE + IE + Clock Calibration Unit Interrupt Enable + Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CWEE + Calibration Watchdog Event + Enable + 0 + 1 + + + CSCE + Calibration State Changed + Enable + 1 + 1 + + + + + + + MDIOS + Management data input/output slave + MDIOS + 0x40009400 + + 0x0 + 0x400 + registers + + + MDIOS_WKUP + MDIOS wakeup + 119 + + + MDIOS + MDIOS global interrupt + 120 + + + + MDIOS_CR + MDIOS_CR + MDIOS configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + Peripheral enable + 0 + 1 + + + WRIE + Register write interrupt + enable + 1 + 1 + + + RDIE + Register Read Interrupt + Enable + 2 + 1 + + + EIE + Error interrupt enable + 3 + 1 + + + DPC + Disable Preamble Check + 7 + 1 + + + PORT_ADDRESS + Slaves's address + 8 + 5 + + + + + MDIOS_WRFR + MDIOS_WRFR + MDIOS write flag register + 0x4 + 0x20 + read-only + 0x00000000 + + + WRF + Write flags for MDIO registers 0 to + 31 + 0 + 32 + + + + + MDIOS_CWRFR + MDIOS_CWRFR + MDIOS clear write flag + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CWRF + Clear the write flag + 0 + 32 + + + + + MDIOS_RDFR + MDIOS_RDFR + MDIOS read flag register + 0xC + 0x20 + read-only + 0x00000000 + + + RDF + Read flags for MDIO registers 0 to + 31 + 0 + 32 + + + + + MDIOS_CRDFR + MDIOS_CRDFR + MDIOS clear read flag register + 0x10 + 0x20 + read-write + 0x00000000 + + + CRDF + Clear the read flag + 0 + 32 + + + + + MDIOS_SR + MDIOS_SR + MDIOS status register + 0x14 + 0x20 + read-only + 0x00000000 + + + PERF + Preamble error flag + 0 + 1 + + + SERF + Start error flag + 1 + 1 + + + TERF + Turnaround error flag + 2 + 1 + + + + + MDIOS_CLRFR + MDIOS_CLRFR + MDIOS clear flag register + 0x18 + 0x20 + read-write + 0x00000000 + + + CPERF + Clear the preamble error + flag + 0 + 1 + + + CSERF + Clear the start error flag + 1 + 1 + + + CTERF + Clear the turnaround error + flag + 2 + 1 + + + + + MDIOS_DINR0 + MDIOS_DINR0 + MDIOS input data register 0 + 0x1C + 0x20 + read-only + 0x00000000 + + + DIN0 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR1 + MDIOS_DINR1 + MDIOS input data register 1 + 0x20 + 0x20 + read-only + 0x00000000 + + + DIN1 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR2 + MDIOS_DINR2 + MDIOS input data register 2 + 0x24 + 0x20 + read-only + 0x00000000 + + + DIN2 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR3 + MDIOS_DINR3 + MDIOS input data register 3 + 0x28 + 0x20 + read-only + 0x00000000 + + + DIN3 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR4 + MDIOS_DINR4 + MDIOS input data register 4 + 0x2C + 0x20 + read-only + 0x00000000 + + + DIN4 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR5 + MDIOS_DINR5 + MDIOS input data register 5 + 0x30 + 0x20 + read-only + 0x00000000 + + + DIN5 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR6 + MDIOS_DINR6 + MDIOS input data register 6 + 0x34 + 0x20 + read-only + 0x00000000 + + + DIN6 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR7 + MDIOS_DINR7 + MDIOS input data register 7 + 0x38 + 0x20 + read-only + 0x00000000 + + + DIN7 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR8 + MDIOS_DINR8 + MDIOS input data register 8 + 0x3C + 0x20 + read-only + 0x00000000 + + + DIN8 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR9 + MDIOS_DINR9 + MDIOS input data register 9 + 0x40 + 0x20 + read-only + 0x00000000 + + + DIN9 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR10 + MDIOS_DINR10 + MDIOS input data register 10 + 0x44 + 0x20 + read-only + 0x00000000 + + + DIN10 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR11 + MDIOS_DINR11 + MDIOS input data register 11 + 0x48 + 0x20 + read-only + 0x00000000 + + + DIN11 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR12 + MDIOS_DINR12 + MDIOS input data register 12 + 0x4C + 0x20 + read-only + 0x00000000 + + + DIN12 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR13 + MDIOS_DINR13 + MDIOS input data register 13 + 0x50 + 0x20 + read-only + 0x00000000 + + + DIN13 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR14 + MDIOS_DINR14 + MDIOS input data register 14 + 0x54 + 0x20 + read-only + 0x00000000 + + + DIN14 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR15 + MDIOS_DINR15 + MDIOS input data register 15 + 0x58 + 0x20 + read-only + 0x00000000 + + + DIN15 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR16 + MDIOS_DINR16 + MDIOS input data register 16 + 0x5C + 0x20 + read-only + 0x00000000 + + + DIN16 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR17 + MDIOS_DINR17 + MDIOS input data register 17 + 0x60 + 0x20 + read-only + 0x00000000 + + + DIN17 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR18 + MDIOS_DINR18 + MDIOS input data register 18 + 0x64 + 0x20 + read-only + 0x00000000 + + + DIN18 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR19 + MDIOS_DINR19 + MDIOS input data register 19 + 0x68 + 0x20 + read-only + 0x00000000 + + + DIN19 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR20 + MDIOS_DINR20 + MDIOS input data register 20 + 0x6C + 0x20 + read-only + 0x00000000 + + + DIN20 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR21 + MDIOS_DINR21 + MDIOS input data register 21 + 0x70 + 0x20 + read-only + 0x00000000 + + + DIN21 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR22 + MDIOS_DINR22 + MDIOS input data register 22 + 0x74 + 0x20 + read-only + 0x00000000 + + + DIN22 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR23 + MDIOS_DINR23 + MDIOS input data register 23 + 0x78 + 0x20 + read-only + 0x00000000 + + + DIN23 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR24 + MDIOS_DINR24 + MDIOS input data register 24 + 0x7C + 0x20 + read-only + 0x00000000 + + + DIN24 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR25 + MDIOS_DINR25 + MDIOS input data register 25 + 0x80 + 0x20 + read-only + 0x00000000 + + + DIN25 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR26 + MDIOS_DINR26 + MDIOS input data register 26 + 0x84 + 0x20 + read-only + 0x00000000 + + + DIN26 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR27 + MDIOS_DINR27 + MDIOS input data register 27 + 0x88 + 0x20 + read-only + 0x00000000 + + + DIN27 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR28 + MDIOS_DINR28 + MDIOS input data register 28 + 0x8C + 0x20 + read-only + 0x00000000 + + + DIN28 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR29 + MDIOS_DINR29 + MDIOS input data register 29 + 0x90 + 0x20 + read-only + 0x00000000 + + + DIN29 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR30 + MDIOS_DINR30 + MDIOS input data register 30 + 0x94 + 0x20 + read-only + 0x00000000 + + + DIN30 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR31 + MDIOS_DINR31 + MDIOS input data register 31 + 0x98 + 0x20 + read-only + 0x00000000 + + + DIN31 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DOUTR0 + MDIOS_DOUTR0 + MDIOS output data register 0 + 0x9C + 0x20 + read-write + 0x00000000 + + + DOUT0 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR1 + MDIOS_DOUTR1 + MDIOS output data register 1 + 0xA0 + 0x20 + read-write + 0x00000000 + + + DOUT1 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR2 + MDIOS_DOUTR2 + MDIOS output data register 2 + 0xA4 + 0x20 + read-write + 0x00000000 + + + DOUT2 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR3 + MDIOS_DOUTR3 + MDIOS output data register 3 + 0xA8 + 0x20 + read-write + 0x00000000 + + + DOUT3 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR4 + MDIOS_DOUTR4 + MDIOS output data register 4 + 0xAC + 0x20 + read-write + 0x00000000 + + + DOUT4 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR5 + MDIOS_DOUTR5 + MDIOS output data register 5 + 0xB0 + 0x20 + read-write + 0x00000000 + + + DOUT5 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR6 + MDIOS_DOUTR6 + MDIOS output data register 6 + 0xB4 + 0x20 + read-write + 0x00000000 + + + DOUT6 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR7 + MDIOS_DOUTR7 + MDIOS output data register 7 + 0xB8 + 0x20 + read-write + 0x00000000 + + + DOUT7 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR8 + MDIOS_DOUTR8 + MDIOS output data register 8 + 0xBC + 0x20 + read-write + 0x00000000 + + + DOUT8 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR9 + MDIOS_DOUTR9 + MDIOS output data register 9 + 0xC0 + 0x20 + read-write + 0x00000000 + + + DOUT9 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR10 + MDIOS_DOUTR10 + MDIOS output data register 10 + 0xC4 + 0x20 + read-write + 0x00000000 + + + DOUT10 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR11 + MDIOS_DOUTR11 + MDIOS output data register 11 + 0xC8 + 0x20 + read-write + 0x00000000 + + + DOUT11 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR12 + MDIOS_DOUTR12 + MDIOS output data register 12 + 0xCC + 0x20 + read-write + 0x00000000 + + + DOUT12 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR13 + MDIOS_DOUTR13 + MDIOS output data register 13 + 0xD0 + 0x20 + read-write + 0x00000000 + + + DOUT13 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR14 + MDIOS_DOUTR14 + MDIOS output data register 14 + 0xD4 + 0x20 + read-write + 0x00000000 + + + DOUT14 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR15 + MDIOS_DOUTR15 + MDIOS output data register 15 + 0xD8 + 0x20 + read-write + 0x00000000 + + + DOUT15 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR16 + MDIOS_DOUTR16 + MDIOS output data register 16 + 0xDC + 0x20 + read-write + 0x00000000 + + + DOUT16 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR17 + MDIOS_DOUTR17 + MDIOS output data register 17 + 0xE0 + 0x20 + read-write + 0x00000000 + + + DOUT17 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR18 + MDIOS_DOUTR18 + MDIOS output data register 18 + 0xE4 + 0x20 + read-write + 0x00000000 + + + DOUT18 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR19 + MDIOS_DOUTR19 + MDIOS output data register 19 + 0xE8 + 0x20 + read-write + 0x00000000 + + + DOUT19 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR20 + MDIOS_DOUTR20 + MDIOS output data register 20 + 0xEC + 0x20 + read-write + 0x00000000 + + + DOUT20 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR21 + MDIOS_DOUTR21 + MDIOS output data register 21 + 0xF0 + 0x20 + read-write + 0x00000000 + + + DOUT21 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR22 + MDIOS_DOUTR22 + MDIOS output data register 22 + 0xF4 + 0x20 + read-write + 0x00000000 + + + DOUT22 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR23 + MDIOS_DOUTR23 + MDIOS output data register 23 + 0xF8 + 0x20 + read-write + 0x00000000 + + + DOUT23 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR24 + MDIOS_DOUTR24 + MDIOS output data register 24 + 0xFC + 0x20 + read-write + 0x00000000 + + + DOUT24 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR25 + MDIOS_DOUTR25 + MDIOS output data register 25 + 0x100 + 0x20 + read-write + 0x00000000 + + + DOUT25 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR26 + MDIOS_DOUTR26 + MDIOS output data register 26 + 0x104 + 0x20 + read-write + 0x00000000 + + + DOUT26 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR27 + MDIOS_DOUTR27 + MDIOS output data register 27 + 0x108 + 0x20 + read-write + 0x00000000 + + + DOUT27 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR28 + MDIOS_DOUTR28 + MDIOS output data register 28 + 0x10C + 0x20 + read-write + 0x00000000 + + + DOUT28 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR29 + MDIOS_DOUTR29 + MDIOS output data register 29 + 0x110 + 0x20 + read-write + 0x00000000 + + + DOUT29 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR30 + MDIOS_DOUTR30 + MDIOS output data register 30 + 0x114 + 0x20 + read-write + 0x00000000 + + + DOUT30 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR31 + MDIOS_DOUTR31 + MDIOS output data register 31 + 0x118 + 0x20 + read-write + 0x00000000 + + + DOUT31 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + + + OPAMP + Operational amplifiers + OPAMP + 0x40009000 + + 0x0 + 0x400 + registers + + + + OPAMP1_CSR + OPAMP1_CSR + OPAMP1 control/status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier + Enable + 0 + 1 + + + FORCE_VP + Force internal reference on VP (reserved + for test + 1 + 1 + + + VP_SEL + Operational amplifier PGA + mode + 2 + 2 + + + VM_SEL + Inverting input selection + 5 + 2 + + + OPAHSM + Operational amplifier high-speed + mode + 8 + 1 + + + CALON + Calibration mode enabled + 11 + 1 + + + CALSEL + Calibration selection + 12 + 2 + + + PGA_GAIN + allows to switch from AOP offset trimmed + values to AOP offset + 14 + 4 + + + USERTRIM + User trimming enable + 18 + 1 + + + TSTREF + OPAMP calibration reference voltage + output control (reserved for test) + 29 + 1 + + + CALOUT + Operational amplifier calibration + output + 30 + 1 + + + + + OPAMP1_OTR + OPAMP1_OTR + OPAMP1 offset trimming register in normal + mode + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIMOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP1_HSOTR + OPAMP1_HSOTR + OPAMP1 offset trimming register in low-power + mode + 0x8 + 0x20 + read-write + 0x00000000 + + + TRIMLPOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMLPOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP2_CSR + OPAMP2_CSR + OPAMP2 control/status register + 0x10 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier + Enable + 0 + 1 + + + FORCE_VP + Force internal reference on VP (reserved + for test) + 1 + 1 + + + VM_SEL + Inverting input selection + 5 + 2 + + + OPAHSM + Operational amplifier high-speed + mode + 8 + 1 + + + CALON + Calibration mode enabled + 11 + 1 + + + CALSEL + Calibration selection + 12 + 2 + + + PGA_GAIN + Operational amplifier Programmable + amplifier gain value + 14 + 4 + + + USERTRIM + User trimming enable + 18 + 1 + + + TSTREF + OPAMP calibration reference voltage + output control (reserved for test) + 29 + 1 + + + CALOUT + Operational amplifier calibration + output + 30 + 1 + + + + + OPAMP2_OTR + OPAMP2_OTR + OPAMP2 offset trimming register in normal + mode + 0x14 + 0x20 + read-write + 0x00000000 + + + TRIMOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP2_HSOTR + OPAMP2_HSOTR + OPAMP2 offset trimming register in low-power + mode + 0x18 + 0x20 + read-write + 0x00000000 + + + TRIMLPOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMLPOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + + + SWPMI + Single Wire Protocol Master + Interface + SWPMI + 0x40008800 + + 0x0 + 0x400 + registers + + + SWPMI1 + SWPMI global interrupt + 115 + + + + CR + CR + SWPMI Configuration/Control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RXDMA + Reception DMA enable + 0 + 1 + + + TXDMA + Transmission DMA enable + 1 + 1 + + + RXMODE + Reception buffering mode + 2 + 1 + + + TXMODE + Transmission buffering + mode + 3 + 1 + + + LPBK + Loopback mode enable + 4 + 1 + + + SWPACT + Single wire protocol master interface + activate + 5 + 1 + + + DEACT + Single wire protocol master interface + deactivate + 10 + 1 + + + SWPTEN + Single wire protocol master transceiver + enable + 11 + 1 + + + + + BRR + BRR + SWPMI Bitrate register + 0x4 + 0x20 + read-write + 0x00000001 + + + BR + Bitrate prescaler + 0 + 8 + + + + + ISR + ISR + SWPMI Interrupt and Status + register + 0xC + 0x20 + read-only + 0x000002C2 + + + RXBFF + Receive buffer full flag + 0 + 1 + + + TXBEF + Transmit buffer empty flag + 1 + 1 + + + RXBERF + Receive CRC error flag + 2 + 1 + + + RXOVRF + Receive overrun error flag + 3 + 1 + + + TXUNRF + Transmit underrun error + flag + 4 + 1 + + + RXNE + Receive data register not + empty + 5 + 1 + + + TXE + Transmit data register + empty + 6 + 1 + + + TCF + Transfer complete flag + 7 + 1 + + + SRF + Slave resume flag + 8 + 1 + + + SUSP + SUSPEND flag + 9 + 1 + + + DEACTF + DEACTIVATED flag + 10 + 1 + + + RDYF + transceiver ready flag + 11 + 1 + + + + + ICR + ICR + SWPMI Interrupt Flag Clear + register + 0x10 + 0x20 + write-only + 0x00000000 + + + CRXBFF + Clear receive buffer full + flag + 0 + 1 + + + CTXBEF + Clear transmit buffer empty + flag + 1 + 1 + + + CRXBERF + Clear receive CRC error + flag + 2 + 1 + + + CRXOVRF + Clear receive overrun error + flag + 3 + 1 + + + CTXUNRF + Clear transmit underrun error + flag + 4 + 1 + + + CTCF + Clear transfer complete + flag + 7 + 1 + + + CSRF + Clear slave resume flag + 8 + 1 + + + CRDYF + Clear transceiver ready + flag + 11 + 1 + + + + + IER + IER + SWPMI Interrupt Enable + register + 0x14 + 0x20 + read-write + 0x00000000 + + + RXBFIE + Receive buffer full interrupt + enable + 0 + 1 + + + TXBEIE + Transmit buffer empty interrupt + enable + 1 + 1 + + + RXBERIE + Receive CRC error interrupt + enable + 2 + 1 + + + RXOVRIE + Receive overrun error interrupt + enable + 3 + 1 + + + TXUNRIE + Transmit underrun error interrupt + enable + 4 + 1 + + + RIE + Receive interrupt enable + 5 + 1 + + + TIE + Transmit interrupt enable + 6 + 1 + + + TCIE + Transmit complete interrupt + enable + 7 + 1 + + + SRIE + Slave resume interrupt + enable + 8 + 1 + + + RDYIE + Transceiver ready interrupt + enable + 11 + 1 + + + + + RFL + RFL + SWPMI Receive Frame Length + register + 0x18 + 0x20 + read-only + 0x00000000 + + + RFL + Receive frame length + 0 + 5 + + + + + TDR + TDR + SWPMI Transmit data register + 0x1C + 0x20 + write-only + 0x00000000 + + + TD + Transmit data + 0 + 32 + + + + + RDR + RDR + SWPMI Receive data register + 0x20 + 0x20 + read-only + 0x00000000 + + + RD + received data + 0 + 32 + + + + + OR + OR + SWPMI Option register + 0x24 + 0x20 + read-write + 0x00000000 + + + SWP_TBYP + SWP transceiver bypass + 0 + 1 + + + SWP_CLASS + SWP class selection + 1 + 1 + + + + + + + TIM2 + General purpose timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + TS_4_3 + Trigger selection + 20 + 2 + + + SMS_3 + Slave mode selection - bit + 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + OC1FE + OC1FE + 2 + 1 + + + OC1PE + OC1PE + 3 + 1 + + + OC1M + OC1M + 4 + 3 + + + OC1CE + OC1CE + 7 + 1 + + + CC2S + CC2S + 8 + 2 + + + OC2FE + OC2FE + 10 + 1 + + + OC2PE + OC2PE + 11 + 1 + + + OC2M + OC2M + 12 + 3 + + + OC2CE + OC2CE + 15 + 1 + + + OC1M_3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + OC3M_3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC4CE + OC4CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + OC4PE + OC4PE + 11 + 1 + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + + OC3PE + OC3PE + 3 + 1 + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT_L + low counter value + 0 + 16 + + + CNT_H + High counter value + 16 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR_H + High Auto-reload value + 16 + 16 + + + ARR_L + Low Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1_H + High Capture/Compare 1 + value + 16 + 16 + + + CCR1_L + Low Capture/Compare 1 + value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2_H + High Capture/Compare 2 + value + 16 + 16 + + + CCR2_L + Low Capture/Compare 2 + value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3_H + High Capture/Compare value + 16 + 16 + + + CCR3_L + Low Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4_H + High Capture/Compare value + 16 + 16 + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + AF1 + AF1 + TIM alternate function option register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + ETRSEL + ETR source selection + 14 + 4 + + + + + TISEL + TISEL + TIM timer input selection + register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + TI1[0] to TI1[15] input + selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input + selection + 8 + 4 + + + TI3SEL + TI3[0] to TI3[15] input + selection + 16 + 4 + + + TI4SEL + TI4[0] to TI4[15] input + selection + 24 + 4 + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 global interrupt + 29 + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 global interrupt + 30 + + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 global interrupt + 50 + + + + TIM12 + 0x40001800 + + + TIM13 + 0x40001C00 + + + TIM14 + 0x40002000 + + + TIM6 + Basic timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + UIFCPY + UIF Copy + 31 + 1 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 55 + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x401 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable + Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending + Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x208 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register + 0x350 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR21 + IPR21 + Interrupt Priority Register + 0x354 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR22 + IPR22 + Interrupt Priority Register + 0x358 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR23 + IPR23 + Interrupt Priority Register + 0x35C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR24 + IPR24 + Interrupt Priority Register + 0x360 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR25 + IPR25 + Interrupt Priority Register + 0x364 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR26 + IPR26 + Interrupt Priority Register + 0x368 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR27 + IPR27 + Interrupt Priority Register + 0x36C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR28 + IPR28 + Interrupt Priority Register + 0x370 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR29 + IPR29 + Interrupt Priority Register + 0x374 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR30 + IPR30 + Interrupt Priority Register + 0x378 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR31 + IPR31 + Interrupt Priority Register + 0x37C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR32 + IPR32 + Interrupt Priority Register + 0x380 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR33 + IPR33 + Interrupt Priority Register + 0x384 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR34 + IPR34 + Interrupt Priority Register + 0x388 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR35 + IPR35 + Interrupt Priority Register + 0x38C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR36 + IPR36 + Interrupt Priority Register + 0x390 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR37 + IPR37 + Interrupt Priority Register + 0x394 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR38 + IPR38 + Interrupt Priority Register + 0x398 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + ISER3 + ISER3 + Interrupt Set-Enable Register + 0xC + 0x20 + read-write + 0x00000000 + + + ICER3 + ICER3 + Interrupt Clear-Enable + Register + 0x8C + 0x20 + read-write + 0x00000000 + + + ISPR3 + ISPR3 + Interrupt Set-Pending Register + 0x10C + 0x20 + read-write + 0x00000000 + + + ICPR3 + ICPR3 + Interrupt Clear-Pending + Register + 0x1C0 + 0x20 + read-write + 0x00000000 + + + IABR3 + IABR3 + Interrupt Active Bit Register + 0x20C + 0x20 + read-write + 0x00000000 + + + + + DBGMCU + Microcontroller Debug Unit + DBGMCU + 0x5C001000 + + 0x0 + 0x400 + registers + + + + IDC + IDC + DBGMCU Identity Code Register + 0x0 + 0x20 + read-only + 0x10006450 + + + DEV_ID + Device ID + 0 + 12 + + + REV_ID + Revision + 16 + 16 + + + + + CR + CR + DBGMCU Configuration Register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBGSLPD1 + Allow D1 domain debug in Sleep mode + 0 + 1 + + + DBGSTPD1 + Allow D1 domain debug in Stop mode + 1 + 1 + + + DBGSTBD1 + Allow D1 domain debug in Standby mode + 2 + 1 + + + DBGSLPD2 + Allow D2 domain debug in Sleep mode + 3 + 1 + + + DBGSTPD2 + Allow D2 domain debug in Stop mode + 4 + 1 + + + DBGSTBD2 + Allow D2 domain debug in Standby mode + 5 + 1 + + + DBGSTPD3 + Allow debug in D3 Stop mode + 7 + 1 + + + DBGSTBD3 + Allow debug in D3 Standby mode + 8 + 1 + + + TRACECLKEN + Trace port clock enable + 20 + 1 + + + D1DBGCKEN + D1 debug clock enable + 21 + 1 + + + D3DBGCKEN + D3 debug clock enable + 22 + 1 + + + TRGOEN + External trigger output enable + 28 + 1 + + + + + APB3FZ1 + APB3FZ1 + DBGMCU APB3 peripheral freeze register CPU1 + 0x34 + 0x20 + read-write + 0x00000000 + + + WWDG1 + WWDG1 stop in debug + 6 + 1 + + + + + APB3FZ2 + APB3FZ2 + DBGMCU APB3 peripheral freeze register CPU2 + 0x38 + 0x20 + read-write + 0x00000000 + + + WWDG1 + WWDG1 stop in debug + 6 + 1 + + + + + APB1LFZ1 + APB1LFZ1 + DBGMCU APB1L peripheral freeze register + 0x3C + 0x20 + read-write + 0x00000000 + + + DBG_TIM2 + TIM2 stop in debug + 0 + 1 + + + DBG_TIM3 + TIM3 stop in debug + 1 + 1 + + + DBG_TIM4 + TIM4 stop in debug + 2 + 1 + + + DBG_TIM5 + TIM5 stop in debug + 3 + 1 + + + DBG_TIM6 + TIM6 stop in debug + 4 + 1 + + + DBG_TIM7 + TIM7 stop in debug + 5 + 1 + + + DBG_TIM12 + TIM12 stop in debug + 6 + 1 + + + DBG_TIM13 + TIM13 stop in debug + 7 + 1 + + + DBG_TIM14 + TIM14 stop in debug + 8 + 1 + + + DBG_LPTIM1 + LPTIM1 stop in debug + 9 + 1 + + + DBG_WWDG2 + WWDG2 stop in debug + 11 + 1 + + + DBG_I2C1 + I2C1 SMBUS timeout stop in debug + 21 + 1 + + + DBG_I2C2 + I2C2 SMBUS timeout stop in debug + 22 + 1 + + + DBG_I2C3 + I2C3 SMBUS timeout stop in debug + 23 + 1 + + + + + APB1LFZ2 + APB1LFZ2 + DBGMCU APB1L peripheral freeze register CPU2 + 0x40 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2 + TIM2 stop in debug + 0 + 1 + + + DBG_TIM3 + TIM3 stop in debug + 1 + 1 + + + DBG_TIM4 + TIM4 stop in debug + 2 + 1 + + + DBG_TIM5 + TIM5 stop in debug + 3 + 1 + + + DBG_TIM6 + TIM6 stop in debug + 4 + 1 + + + DBG_TIM7 + TIM4 stop in debug + 5 + 1 + + + DBG_TIM12 + TIM12 stop in debug + 6 + 1 + + + DBG_TIM13 + TIM13 stop in debug + 7 + 1 + + + DBG_TIM14 + TIM14 stop in debug + 8 + 1 + + + DBG_LPTIM1 + LPTIM1 stop in debug + 9 + 1 + + + DBG_WWDG2 + WWDG2 stop in debug + 11 + 1 + + + DBG_I2C1 + I2C1 SMBUS timeout stop in debug + 21 + 1 + + + DBG_I2C2 + I2C2 SMBUS timeout stop in debug + 22 + 1 + + + DBG_I2C3 + I2C3 SMBUS timeout stop in debug + 23 + 1 + + + + + APB2FZ1 + APB2FZ1 + DBGMCU APB2 peripheral freeze register + 0x4C + 0x20 + read-write + 0x00000000 + + + DBG_TIM1 + TIM1 stop in debug + 0 + 1 + + + DBG_TIM8 + TIM8 stop in debug + 1 + 1 + + + DBG_TIM15 + TIM15 stop in debug + 16 + 1 + + + DBG_TIM16 + TIM16 stop in debug + 17 + 1 + + + DBG_TIM17 + TIM17 stop in debug + 18 + 1 + + + DBG_HRTIM + HRTIM stop in debug + 29 + 1 + + + + + APB2FZ2 + APB2FZ2 + DBGMCU APB2 peripheral freeze register CPU2 + 0x50 + 0x20 + read-write + 0x00000000 + + + DBG_TIM1 + TIM1 stop in debug + 0 + 1 + + + DBG_TIM8 + TIM8 stop in debug + 1 + 1 + + + DBG_TIM15 + TIM15 stop in debug + 16 + 1 + + + DBG_TIM16 + TIM16 stop in debug + 17 + 1 + + + DBG_TIM17 + TIM17 stop in debug + 18 + 1 + + + DBG_HRTIM + HRTIM stop in debug + 29 + 1 + + + + + APB4FZ1 + APB4FZ1 + DBGMCU APB4 peripheral freeze register + 0x54 + 0x20 + read-write + 0x00000000 + + + DBG_I2C4 + I2C4 SMBUS timeout stop in debug + 7 + 1 + + + DBG_LPTIM2 + LPTIM2 stop in debug + 9 + 1 + + + DBG_LPTIM3 + LPTIM2 stop in debug + 10 + 1 + + + DBG_LPTIM4 + LPTIM4 stop in debug + 11 + 1 + + + DBG_LPTIM5 + LPTIM5 stop in debug + 12 + 1 + + + DBG_RTC + RTC stop in debug + 16 + 1 + + + DBG_WDGLSD1 + Independent watchdog for D1 stop in debug + 18 + 1 + + + DBG_WDGLSD2 + Independent watchdog for D2 stop in debug + 19 + 1 + + + + + APB4FZ2 + APB4FZ2 + DBGMCU APB4 peripheral freeze register CPU2 + 0x58 + 0x20 + read-write + 0x00000000 + + + DBG_I2C4 + I2C4 SMBUS timeout stop in debug + 7 + 1 + + + DBG_LPTIM2 + LPTIM2 stop in debug + 9 + 1 + + + DBG_LPTIM3 + LPTIM2 stop in debug + 10 + 1 + + + DBG_LPTIM4 + LPTIM4 stop in debug + 11 + 1 + + + DBG_LPTIM5 + LPTIM5 stop in debug + 12 + 1 + + + DBG_RTC + RTC stop in debug + 16 + 1 + + + DBG_WDGLSD1 + LS watchdog for D1 stop in debug + 18 + 1 + + + DBG_WDGLSD2 + LS watchdog for D2 stop in debug + 19 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-write + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CSR + CSR + SysTick control and status + register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + RVR + RVR + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + CVR + CVR + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control + register + 0x0 + 0x20 + read-write + 0x0000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISFOLD + DISFOLD + 2 + 1 + + + FPEXCODIS + FPEXCODIS + 10 + 1 + + + DISRAMODE + DISRAMODE + 11 + 1 + + + DISITMATBFLUSH + DISITMATBFLUSH + 12 + 1 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point unit interrupt + 81 + + + + FPCCR + FPCCR + Floating-point context control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address + register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated + floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control + register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception + bit + 0 + 1 + + + DZC + Division by zero cumulative exception + bit. + 1 + 1 + + + OFC + Overflow cumulative exception + bit + 2 + 1 + + + UFC + Underflow cumulative exception + bit + 3 + 1 + + + IXC + Inexact cumulative exception + bit + 4 + 1 + + + IDC + Input denormal cumulative exception + bit. + 7 + 1 + + + RMode + Rounding Mode control + field + 22 + 2 + + + FZ + Flush-to-zero mode control + bit: + 24 + 1 + + + DN + Default NaN mode control + bit + 25 + 1 + + + AHP + Alternative half-precision control + bit + 26 + 1 + + + V + Overflow condition code + flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code + flag + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + DC + DC + 16 + 1 + + + IC + IC + 17 + 1 + + + BP + BP + 18 + 1 + + + + + SHPR1 + SHPR1 + System handler priority + registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler + 4 + 0 + 8 + + + PRI_5 + Priority of system handler + 5 + 8 + 8 + + + PRI_6 + Priority of system handler + 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + SHCSR + SHCSR + System handler control and state + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active + bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active + bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active + bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active + bit + 10 + 1 + + + SYSTICKACT + SysTick exception active + bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending + bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception + pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending + bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable + bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status + register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + IACCVIOL + 0 + 1 + + + DACCVIOL + DACCVIOL + 1 + 1 + + + MUNSTKERR + MUNSTKERR + 3 + 1 + + + MSTKERR + MSTKERR + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + MMARVALID + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return + from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception + entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state + preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid + flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage + fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage + fault + 18 + 1 + + + NOCP + No coprocessor usage + fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage + fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Memory management fault + address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Bus fault address + 0 + 32 + + + + + + + PF + Processor features + PF + 0xE000ED78 + + 0x0 + 0xD + registers + + + + CLIDR + CLIDR + Cache Level ID register + 0x0 + 0x20 + read-only + 0x09000003 + + + CL1 + CL1 + 0 + 3 + + + CL2 + CL2 + 3 + 3 + + + CL3 + CL3 + 6 + 3 + + + CL4 + CL4 + 9 + 3 + + + CL5 + CL5 + 12 + 3 + + + CL6 + CL6 + 15 + 3 + + + CL7 + CL7 + 18 + 3 + + + LoUIS + LoUIS + 21 + 3 + + + LoC + LoC + 24 + 3 + + + LoU + LoU + 27 + 3 + + + + + CTR + CTR + Cache Type register + 0x4 + 0x20 + read-only + 0X8303C003 + + + _IminLine + IminLine + 0 + 4 + + + DMinLine + DMinLine + 16 + 4 + + + ERG + ERG + 20 + 4 + + + CWG + CWG + 24 + 4 + + + Format + Format + 29 + 3 + + + + + CCSIDR + CCSIDR + Cache Size ID register + 0x8 + 0x20 + read-only + 0X00000000 + + + LineSize + LineSize + 0 + 3 + + + Associativity + Associativity + 3 + 10 + + + NumSets + NumSets + 13 + 15 + + + WA + WA + 28 + 1 + + + RA + RA + 29 + 1 + + + WB + WB + 30 + 1 + + + WT + WT + 31 + 1 + + + + + + + AC + Access control + AC + 0xE000EF90 + + 0x0 + 0x1D + registers + + + + ITCMCR + ITCMCR + Instruction and Data Tightly-Coupled Memory + Control Registers + 0x0 + 0x20 + read-write + 0X00000000 + + + EN + EN + 0 + 1 + + + RMW + RMW + 1 + 1 + + + RETEN + RETEN + 2 + 1 + + + SZ + SZ + 3 + 4 + + + + + DTCMCR + DTCMCR + Instruction and Data Tightly-Coupled Memory + Control Registers + 0x4 + 0x20 + read-write + 0X00000000 + + + EN + EN + 0 + 1 + + + RMW + RMW + 1 + 1 + + + RETEN + RETEN + 2 + 1 + + + SZ + SZ + 3 + 4 + + + + + AHBPCR + AHBPCR + AHBP Control register + 0x8 + 0x20 + read-write + 0X00000000 + + + EN + EN + 0 + 1 + + + SZ + SZ + 1 + 3 + + + + + CACR + CACR + Auxiliary Cache Control + register + 0xC + 0x20 + read-write + 0X00000000 + + + SIWT + SIWT + 0 + 1 + + + ECCEN + ECCEN + 1 + 1 + + + FORCEWT + FORCEWT + 2 + 1 + + + + + AHBSCR + AHBSCR + AHB Slave Control register + 0x10 + 0x20 + read-write + 0X00000000 + + + CTL + CTL + 0 + 2 + + + TPRI + TPRI + 2 + 9 + + + INITCOUNT + INITCOUNT + 11 + 5 + + + + + ABFSR + ABFSR + Auxiliary Bus Fault Status + register + 0x18 + 0x20 + read-write + 0X00000000 + + + ITCM + ITCM + 0 + 1 + + + DTCM + DTCM + 1 + 1 + + + AHBP + AHBP + 2 + 1 + + + AXIM + AXIM + 3 + 1 + + + EPPB + EPPB + 4 + 1 + + + AXIMTYPE + AXIMTYPE + 8 + 2 + + + + + + + RAMECC1 + ECC controller is associated to each RAM + area + RAMECC + 0x52009000 + + 0x0 + 0x400 + registers + + + + IER + IER + RAMECC interrupt enable + register + 0x0 + 0x20 + read-write + 0x00000000 + + + GIE + Global interrupt enable + 0 + 1 + + + GECCSEIE_ + Global ECC single error interrupt + enable + 1 + 1 + + + GECCDEIE + Global ECC double error interrupt + enable + 2 + 1 + + + GECCDEBWIE + Global ECC double error on byte write + (BW) interrupt enable + 3 + 1 + + + + + M1CR + M1CR + RAMECC monitor x configuration + register + 0x20 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1SR + M1SR + RAMECC monitor x status + register + 0x24 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1FAR + M1FAR + RAMECC monitor x failing address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1FDRL + M1FDRL + RAMECC monitor x failing data low + register + 0x2C + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1FDRH + M1FDRH + RAMECC monitor x failing data high + register + 0x30 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1FECR + M1FECR + RAMECC monitor x failing ECC error code + register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2CR + M2CR + RAMECC monitor x configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2SR + M2SR + RAMECC monitor x status + register + 0x44 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2FAR + M2FAR + RAMECC monitor x failing address + register + 0x48 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2FDRL + M2FDRL + RAMECC monitor x failing data low + register + 0x4C + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2FDRH + M2FDRH + RAMECC monitor x failing data high + register + 0x50 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M2FECR + M2FECR + RAMECC monitor x failing ECC error code + register + 0x58 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3CR + M3CR + RAMECC monitor x configuration + register + 0x60 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3SR + M3SR + RAMECC monitor x status + register + 0x64 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3FAR + M3FAR + RAMECC monitor x failing address + register + 0x68 + 0x20 + read-write + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3FDRL + M3FDRL + RAMECC monitor x failing data low + register + 0x6C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M3FDRH + M3FDRH + RAMECC monitor x failing data high + register + 0x70 + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M3FECR + M3FECR + RAMECC monitor x failing ECC error code + register + 0x7C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M4CR + M4CR + RAMECC monitor x configuration + register + 0x80 + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M4SR + M4SR + RAMECC monitor x status + register + 0x84 + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M4FAR + M4FAR + RAMECC monitor x failing address + register + 0x88 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M4FDRL + M4FDRL + RAMECC monitor x failing data low + register + 0x8C + 0x20 + read-write + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M4FDRH + M4FDRH + RAMECC monitor x failing data high + register + 0x90 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M4FECR + M4FECR + RAMECC monitor x failing ECC error code + register + M4FDRH + 0x90 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M5CR + M5CR + RAMECC monitor x configuration + register + 0xA0 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5SR + M5SR + RAMECC monitor x status + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FAR + M5FAR + RAMECC monitor x failing address + register + 0xA8 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FDRL + M5FDRL + RAMECC monitor x failing data low + register + 0xAC + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FDRH + M5FDRH + RAMECC monitor x failing data high + register + 0xB0 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FECR + M5FECR + RAMECC monitor x failing ECC error code + register + 0xB4 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + + + RAMECC2 + ECC controller is associated to each RAM + area + RAMECC + 0x48023000 + + 0x0 + 0x400 + registers + + + + IER + IER + RAMECC interrupt enable + register + 0x0 + 0x20 + read-write + 0x00000000 + + + GIE + Global interrupt enable + 0 + 1 + + + GECCSEIE_ + Global ECC single error interrupt + enable + 1 + 1 + + + GECCDEIE + Global ECC double error interrupt + enable + 2 + 1 + + + GECCDEBWIE + Global ECC double error on byte write + (BW) interrupt enable + 3 + 1 + + + + + M1CR + M1CR + RAMECC monitor x configuration + register + 0x20 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M2CR + M2CR + RAMECC monitor x configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M3CR + M3CR + RAMECC monitor x configuration + register + 0x60 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M4CR + M4CR + RAMECC monitor x configuration + register + 0x80 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M5CR + M5CR + RAMECC monitor x configuration + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1SR + M1SR + RAMECC monitor x status + register + 0x24 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2SR + M2SR + RAMECC monitor x status + register + 0x44 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M3SR + M3SR + RAMECC monitor x status + register + 0x64 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M4SR + M4SR + RAMECC monitor x status + register + 0x84 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M5SR + M5SR + RAMECC monitor x status + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M1FAR + M1FAR + RAMECC monitor x failing address + register + 0x28 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M2FAR + M2FAR + RAMECC monitor x failing address + register + 0x48 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3FAR + M3FAR + RAMECC monitor x failing address + register + 0x68 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M4FAR + M4FAR + RAMECC monitor x failing address + register + 0x88 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M5FAR + M5FAR + RAMECC monitor x failing address + register + 0xA8 + 0x20 + read-write + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M1FDRL + M1FDRL + RAMECC monitor x failing data low + register + 0x2C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M2FDRL + M2FDRL + RAMECC monitor x failing data low + register + 0x4C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M3FDRL + M3FDRL + RAMECC monitor x failing data low + register + 0x6C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M4FDRL + M4FDRL + RAMECC monitor x failing data low + register + 0x8C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M5FDRL + M5FDRL + RAMECC monitor x failing data low + register + 0xAC + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M1FDRH + M1FDRH + RAMECC monitor x failing data high + register + 0x30 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M2FDRH + M2FDRH + RAMECC monitor x failing data high + register + 0x50 + 0x20 + read-write + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M3FDRH + M3FDRH + RAMECC monitor x failing data high + register + 0x70 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M4FDRH + M4FDRH + RAMECC monitor x failing data high + register + 0x90 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M5FDRH + M5FDRH + RAMECC monitor x failing data high + register + 0xB0 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M1FECR + M1FECR + RAMECC monitor x failing ECC error code + register + 0x34 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M2FECR + M2FECR + RAMECC monitor x failing ECC error code + register + 0x58 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M3FECR + M3FECR + RAMECC monitor x failing ECC error code + register + 0x7C + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M4FECR + M4FECR + RAMECC monitor x failing ECC error code + register + M4FDRH + 0x90 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FECR + M5FECR + RAMECC monitor x failing ECC error code + register + 0xB4 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + + + RAMECC3 + ECC controller is associated to each RAM + area + RAMECC + 0x58027000 + + 0x0 + 0x400 + registers + + + + IER + IER + RAMECC interrupt enable + register + 0x0 + 0x20 + read-write + 0x00000000 + + + GIE + Global interrupt enable + 0 + 1 + + + GECCSEIE_ + Global ECC single error interrupt + enable + 1 + 1 + + + GECCDEIE + Global ECC double error interrupt + enable + 2 + 1 + + + GECCDEBWIE + Global ECC double error on byte write + (BW) interrupt enable + 3 + 1 + + + + + M1CR + M1CR + RAMECC monitor x configuration + register + 0x20 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M2CR + M2CR + RAMECC monitor x configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1SR + M1SR + RAMECC monitor x status + register + 0x24 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2SR + M2SR + RAMECC monitor x status + register + 0x44 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M1FAR + M1FAR + RAMECC monitor x failing address + register + 0x28 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M2FAR + M2FAR + RAMECC monitor x failing address + register + 0x48 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M1FDRL + M1FDRL + RAMECC monitor x failing data low + register + 0x2C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M2FDRL + M2FDRL + RAMECC monitor x failing data low + register + 0x4C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M1FDRH + M1FDRH + RAMECC monitor x failing data high + register + 0x30 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M2FDRH + M2FDRH + RAMECC monitor x failing data high + register + 0x50 + 0x20 + read-write + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M1FECR + M1FECR + RAMECC monitor x failing ECC error code + register + 0x34 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M2FECR + M2FECR + RAMECC monitor x failing ECC error code + register + 0x58 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + + + ART + accelerator - control register + (ART_CTR) + ART + 0x40024400 + + 0x0 + 0x400 + registers + + + + CTR + CTR + control register + 0x0 + 0x20 + read-write + 0x00000004 + + + EN + Cache enable + 0 + 1 + + + PCACHEADDR + Cacheable page index + 8 + 12 + + + + + + + diff --git a/svd/STM32H747_CM7.svd b/svd/STM32H747_CM7.svd new file mode 100644 index 000000000..ea03cfcc4 --- /dev/null +++ b/svd/STM32H747_CM7.svd @@ -0,0 +1,109474 @@ + + + STM32H747_CM7 + 1.2 + STM32H747_CM7 + + CM7 + r0p1 + little + true + true + 4 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + COMP1 + COMP1 + COMP1 + 0x58003800 + + 0x0 + 0x400 + registers + + + COMP + COMP1 and COMP2 + 137 + + + + SR + SR + Comparator status register + 0x0 + 0x20 + read-only + 0x00000000 + + + C1VAL + COMP channel 1 output status + bit + 0 + 1 + + + C2VAL + COMP channel 2 output status + bit + 1 + 1 + + + C1IF + COMP channel 1 Interrupt + Flag + 16 + 1 + + + C2IF + COMP channel 2 Interrupt + Flag + 17 + 1 + + + + + ICFR + ICFR + Comparator interrupt clear flag + register + 0x4 + 0x20 + write-only + 0x00000000 + + + CC1IF + Clear COMP channel 1 Interrupt + Flag + 16 + 1 + + + CC2IF + Clear COMP channel 2 Interrupt + Flag + 17 + 1 + + + + + OR + OR + Comparator option register + 0x8 + 0x20 + read-write + 0x00000000 + + + AFOP + Selection of source for alternate + function of output ports + 0 + 11 + + + OR + Option Register + 11 + 21 + + + + + CFGR1 + CFGR1 + Comparator configuration register + 1 + 0xC + 0x20 + read-write + 0x00000000 + + + EN + COMP channel 1 enable bit + 0 + 1 + + + BRGEN + Scaler bridge enable + 1 + 1 + + + SCALEN + Voltage scaler enable bit + 2 + 1 + + + POLARITY + COMP channel 1 polarity selection + bit + 3 + 1 + + + ITEN + COMP channel 1 interrupt + enable + 6 + 1 + + + HYST + COMP channel 1 hysteresis selection + bits + 8 + 2 + + + PWRMODE + Power Mode of the COMP channel + 1 + 12 + 2 + + + INMSEL + COMP channel 1 inverting input selection + field + 16 + 3 + + + INPSEL + COMP channel 1 non-inverting input + selection bit + 20 + 1 + + + BLANKING + COMP channel 1 blanking source selection + bits + 24 + 4 + + + LOCK + Lock bit + 31 + 1 + + + + + CFGR2 + CFGR2 + Comparator configuration register + 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + EN + COMP channel 1 enable bit + 0 + 1 + + + BRGEN + Scaler bridge enable + 1 + 1 + + + SCALEN + Voltage scaler enable bit + 2 + 1 + + + POLARITY + COMP channel 1 polarity selection + bit + 3 + 1 + + + WINMODE + Window comparator mode selection + bit + 4 + 1 + + + ITEN + COMP channel 1 interrupt + enable + 6 + 1 + + + HYST + COMP channel 1 hysteresis selection + bits + 8 + 2 + + + PWRMODE + Power Mode of the COMP channel + 1 + 12 + 2 + + + INMSEL + COMP channel 1 inverting input selection + field + 16 + 3 + + + INPSEL + COMP channel 1 non-inverting input + selection bit + 20 + 1 + + + BLANKING + COMP channel 1 blanking source selection + bits + 24 + 4 + + + LOCK + Lock bit + 31 + 1 + + + + + + + CRS + CRS + CRS + 0x40008400 + + 0x0 + 0x400 + registers + + + CRS + Clock Recovery System globa + 144 + + + + CR + CR + CRS control register + 0x0 + 0x20 + 0x00002000 + + + SYNCOKIE + SYNC event OK interrupt + enable + 0 + 1 + read-write + + + SYNCWARNIE + SYNC warning interrupt + enable + 1 + 1 + read-write + + + ERRIE + Synchronization or trimming error + interrupt enable + 2 + 1 + read-write + + + ESYNCIE + Expected SYNC interrupt + enable + 3 + 1 + read-write + + + CEN + Frequency error counter enable This bit + enables the oscillator clock for the frequency error + counter. When this bit is set, the CRS_CFGR register + is write-protected and cannot be + modified. + 5 + 1 + read-write + + + AUTOTRIMEN + Automatic trimming enable This bit + enables the automatic hardware adjustment of TRIM + bits according to the measured frequency error + between two SYNC events. If this bit is set, the TRIM + bits are read-only. The TRIM value can be adjusted by + hardware by one or two steps at a time, depending on + the measured frequency error value. Refer to + Section7.3.4: Frequency error evaluation and + automatic trimming for more details. + 6 + 1 + read-write + + + SWSYNC + Generate software SYNC event This bit is + set by software in order to generate a software SYNC + event. It is automatically cleared by + hardware. + 7 + 1 + read-only + + + TRIM + HSI48 oscillator smooth trimming These + bits provide a user-programmable trimming value to + the HSI48 oscillator. They can be programmed to + adjust to variations in voltage and temperature that + influence the frequency of the HSI48. The default + value is 32, which corresponds to the middle of the + trimming interval. The trimming step is around 67 kHz + between two consecutive TRIM steps. A higher TRIM + value corresponds to a higher output frequency. When + the AUTOTRIMEN bit is set, this field is controlled + by hardware and is read-only. + 8 + 6 + read-write + + + + + CFGR + CFGR + This register can be written only when the + frequency error counter is disabled (CEN bit is cleared + in CRS_CR). When the counter is enabled, this register is + write-protected. + 0x4 + 0x20 + read-write + 0x2022BB7F + + + RELOAD + Counter reload value RELOAD is the value + to be loaded in the frequency error counter with each + SYNC event. Refer to Section7.3.3: Frequency error + measurement for more details about counter + behavior. + 0 + 16 + + + FELIM + Frequency error limit FELIM contains the + value to be used to evaluate the captured frequency + error value latched in the FECAP[15:0] bits of the + CRS_ISR register. Refer to Section7.3.4: Frequency + error evaluation and automatic trimming for more + details about FECAP evaluation. + 16 + 8 + + + SYNCDIV + SYNC divider These bits are set and + cleared by software to control the division factor of + the SYNC signal. + 24 + 3 + + + SYNCSRC + SYNC signal source selection These bits + are set and cleared by software to select the SYNC + signal source. Note: When using USB LPM (Link Power + Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. + No SYNC signal will therefore be provided to the CRS + to calibrate the HSI48 on the run. To guarantee the + required clock precision after waking up from Sleep + mode, the LSE or reference clock on the GPIOs should + be used as SYNC signal. + 28 + 2 + + + SYNCPOL + SYNC polarity selection This bit is set + and cleared by software to select the input polarity + for the SYNC signal source. + 31 + 1 + + + + + ISR + ISR + CRS interrupt and status + register + 0x8 + 0x20 + read-only + 0x00000000 + + + SYNCOKF + SYNC event OK flag This flag is set by + hardware when the measured frequency error is smaller + than FELIM * 3. This means that either no adjustment + of the TRIM value is needed or that an adjustment by + one trimming step is enough to compensate the + frequency error. An interrupt is generated if the + SYNCOKIE bit is set in the CRS_CR register. It is + cleared by software by setting the SYNCOKC bit in the + CRS_ICR register. + 0 + 1 + + + SYNCWARNF + SYNC warning flag This flag is set by + hardware when the measured frequency error is greater + than or equal to FELIM * 3, but smaller than FELIM * + 128. This means that to compensate the frequency + error, the TRIM value must be adjusted by two steps + or more. An interrupt is generated if the SYNCWARNIE + bit is set in the CRS_CR register. It is cleared by + software by setting the SYNCWARNC bit in the CRS_ICR + register. + 1 + 1 + + + ERRF + Error flag This flag is set by hardware + in case of any synchronization or trimming error. It + is the logical OR of the TRIMOVF, SYNCMISS and + SYNCERR bits. An interrupt is generated if the ERRIE + bit is set in the CRS_CR register. It is cleared by + software in reaction to setting the ERRC bit in the + CRS_ICR register, which clears the TRIMOVF, SYNCMISS + and SYNCERR bits. + 2 + 1 + + + ESYNCF + Expected SYNC flag This flag is set by + hardware when the frequency error counter reached a + zero value. An interrupt is generated if the ESYNCIE + bit is set in the CRS_CR register. It is cleared by + software by setting the ESYNCC bit in the CRS_ICR + register. + 3 + 1 + + + SYNCERR + SYNC error This flag is set by hardware + when the SYNC pulse arrives before the ESYNC event + and the measured frequency error is greater than or + equal to FELIM * 128. This means that the frequency + error is too big (internal frequency too low) to be + compensated by adjusting the TRIM value, and that + some other action should be taken. An interrupt is + generated if the ERRIE bit is set in the CRS_CR + register. It is cleared by software by setting the + ERRC bit in the CRS_ICR register. + 8 + 1 + + + SYNCMISS + SYNC missed This flag is set by hardware + when the frequency error counter reached value FELIM + * 128 and no SYNC was detected, meaning either that a + SYNC pulse was missed or that the frequency error is + too big (internal frequency too high) to be + compensated by adjusting the TRIM value, and that + some other action should be taken. At this point, the + frequency error counter is stopped (waiting for a + next SYNC) and an interrupt is generated if the ERRIE + bit is set in the CRS_CR register. It is cleared by + software by setting the ERRC bit in the CRS_ICR + register. + 9 + 1 + + + TRIMOVF + Trimming overflow or underflow This flag + is set by hardware when the automatic trimming tries + to over- or under-flow the TRIM value. An interrupt + is generated if the ERRIE bit is set in the CRS_CR + register. It is cleared by software by setting the + ERRC bit in the CRS_ICR register. + 10 + 1 + + + FEDIR + Frequency error direction FEDIR is the + counting direction of the frequency error counter + latched in the time of the last SYNC event. It shows + whether the actual frequency is below or above the + target. + 15 + 1 + + + FECAP + Frequency error capture FECAP is the + frequency error counter value latched in the time of + the last SYNC event. Refer to Section7.3.4: Frequency + error evaluation and automatic trimming for more + details about FECAP usage. + 16 + 16 + + + + + ICR + ICR + CRS interrupt flag clear + register + 0xC + 0x20 + read-write + 0x00000000 + + + SYNCOKC + SYNC event OK clear flag Writing 1 to + this bit clears the SYNCOKF flag in the CRS_ISR + register. + 0 + 1 + + + SYNCWARNC + SYNC warning clear flag Writing 1 to + this bit clears the SYNCWARNF flag in the CRS_ISR + register. + 1 + 1 + + + ERRC + Error clear flag Writing 1 to this bit + clears TRIMOVF, SYNCMISS and SYNCERR bits and + consequently also the ERRF flag in the CRS_ISR + register. + 2 + 1 + + + ESYNCC + Expected SYNC clear flag Writing 1 to + this bit clears the ESYNCF flag in the CRS_ISR + register. + 3 + 1 + + + + + + + DAC + DAC + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CR + CR + DAC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable This bit is set and + cleared by software to enable/disable DAC + channel1. + 0 + 1 + + + TEN1 + DAC channel1 trigger + enable + 1 + 1 + + + TSEL1 + DAC channel1 trigger selection These + bits select the external event used to trigger DAC + channel1. Note: Only used if bit TEN1 = 1 (DAC + channel1 trigger enabled). + 2 + 3 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable These bits are set and cleared by + software. Note: Only used if bit TEN1 = 1 (DAC + channel1 trigger enabled). + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude selector + These bits are written by software to select mask in + wave generation mode or amplitude in triangle + generation mode. = 1011: Unmask bits[11:0] of LFSR/ + triangle amplitude equal to 4095 + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable This bit is set + and cleared by software. + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable This bit is set and cleared by + software. + 13 + 1 + + + CEN1 + DAC Channel 1 calibration enable This + bit is set and cleared by software to enable/disable + DAC channel 1 calibration, it can be written only if + bit EN1=0 into DAC_CR (the calibration mode can be + entered/exit only when the DAC channel is disabled) + Otherwise, the write operation is + ignored. + 14 + 1 + + + EN2 + DAC channel2 enable This bit is set and + cleared by software to enable/disable DAC + channel2. + 16 + 1 + + + TEN2 + DAC channel2 trigger + enable + 17 + 1 + + + TSEL2 + DAC channel2 trigger selection These + bits select the external event used to trigger DAC + channel2 Note: Only used if bit TEN2 = 1 (DAC + channel2 trigger enabled). + 18 + 3 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable These bits are set/reset by + software. 1x: Triangle wave generation enabled Note: + Only used if bit TEN2 = 1 (DAC channel2 trigger + enabled) + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude selector + These bits are written by software to select mask in + wave generation mode or amplitude in triangle + generation mode. = 1011: Unmask bits[11:0] of LFSR/ + triangle amplitude equal to 4095 + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable This bit is set + and cleared by software. + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable This bit is set and cleared by + software. + 29 + 1 + + + CEN2 + DAC Channel 2 calibration enable This + bit is set and cleared by software to enable/disable + DAC channel 2 calibration, it can be written only if + bit EN2=0 into DAC_CR (the calibration mode can be + entered/exit only when the DAC channel is disabled) + Otherwise, the write operation is + ignored. + 30 + 1 + + + + + SWTRGR + SWTRGR + DAC software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software trigger This bit + is set by software to trigger the DAC in software + trigger mode. Note: This bit is cleared by hardware + (one APB1 clock cycle later) once the DAC_DHR1 + register value has been loaded into the DAC_DOR1 + register. + 0 + 1 + + + SWTRIG2 + DAC channel2 software trigger This bit + is set by software to trigger the DAC in software + trigger mode. Note: This bit is cleared by hardware + (one APB1 clock cycle later) once the DAC_DHR2 + register value has been loaded into the DAC_DOR2 + register. + 1 + 1 + + + + + DHR12R1 + DHR12R1 + DAC channel1 12-bit right-aligned data + holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 0 + 12 + + + + + DHR12L1 + DHR12L1 + DAC channel1 12-bit left aligned data + holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 4 + 12 + + + + + DHR8R1 + DHR8R1 + DAC channel1 8-bit right aligned data + holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel1. + 0 + 8 + + + + + DHR12R2 + DHR12R2 + DAC channel2 12-bit right aligned data + holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel2. + 0 + 12 + + + + + DHR12L2 + DHR12L2 + DAC channel2 12-bit left aligned data + holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + These bits are written by software which specify + 12-bit data for DAC channel2. + 4 + 12 + + + + + DHR8R2 + DHR8R2 + DAC channel2 8-bit right-aligned data + holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel2. + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel2. + 16 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel1. + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + These bits are written by software which specifies + 12-bit data for DAC channel2. + 20 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel1. + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + These bits are written by software which specifies + 8-bit data for DAC channel2. + 8 + 8 + + + + + DOR1 + DOR1 + DAC channel1 data output + register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output These bits are + read-only, they contain data output for DAC + channel1. + 0 + 12 + + + + + DOR2 + DOR2 + DAC channel2 data output + register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output These bits are + read-only, they contain data output for DAC + channel2. + 0 + 12 + + + + + SR + SR + DAC status register + 0x34 + 0x20 + 0x00000000 + + + DMAUDR1 + DAC channel1 DMA underrun flag This bit + is set by hardware and cleared by software (by + writing it to 1). + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset status + This bit is set and cleared by hardware + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time + flag This bit is systematically set just after Sample + & Hold mode enable and is set each time the + software writes the register DAC_SHSR1, It is cleared + by hardware when the write operation of DAC_SHSR1 is + complete. (It takes about 3LSI periods of + synchronization). + 15 + 1 + read-only + + + DMAUDR2 + DAC channel2 DMA underrun flag This bit + is set by hardware and cleared by software (by + writing it to 1). + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset status + This bit is set and cleared by hardware + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time + flag This bit is systematically set just after Sample + & Hold mode enable and is set each time the + software writes the register DAC_SHSR2, It is cleared + by hardware when the write operation of DAC_SHSR2 is + complete. (It takes about 3 LSI periods of + synchronization). + 31 + 1 + read-only + + + + + CCR + CCR + DAC calibration control + register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming + value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming + value + 16 + 5 + + + + + MCR + MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode These bits can be + written only when the DAC is disabled and not in the + calibration mode (when bit EN1=0 and bit CEN1 =0 in + the DAC_CR register). If EN1=1 or CEN1 =1 the write + operation is ignored. They can be set and cleared by + software to select the DAC Channel 1 mode: DAC + Channel 1 in normal Mode DAC Channel 1 in sample + &amp; hold mode + 0 + 3 + + + MODE2 + DAC Channel 2 mode These bits can be + written only when the DAC is disabled and not in the + calibration mode (when bit EN2=0 and bit CEN2 =0 in + the DAC_CR register). If EN2=1 or CEN2 =1 the write + operation is ignored. They can be set and cleared by + software to select the DAC Channel 2 mode: DAC + Channel 2 in normal Mode DAC Channel 2 in sample + &amp; hold mode + 16 + 3 + + + + + SHSR1 + SHSR1 + DAC Sample and Hold sample time register + 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time (only valid in + sample &amp; hold mode) These bits can be written + when the DAC channel1 is disabled or also during + normal operation. in the latter case, the write can + be done only when BWSTx of DAC_SR register is low, If + BWSTx=1, the write operation is + ignored. + 0 + 10 + + + + + SHSR2 + SHSR2 + DAC Sample and Hold sample time register + 2 + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time (only valid in + sample &amp; hold mode) These bits can be written + when the DAC channel2 is disabled or also during + normal operation. in the latter case, the write can + be done only when BWSTx of DAC_SR register is low, if + BWSTx=1, the write operation is + ignored. + 0 + 10 + + + + + SHHR + SHHR + DAC Sample and Hold hold time + register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time (only valid in + sample &amp; hold mode) Hold time= (THOLD[9:0]) x + T LSI + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time (only valid in + sample &amp; hold mode). Hold time= (THOLD[9:0]) + x T LSI + 16 + 10 + + + + + SHRR + SHRR + DAC Sample and Hold refresh time + register + 0x4C + 0x20 + read-write + 0x00010001 + + + TREFRESH1 + DAC Channel 1 refresh Time (only valid + in sample &amp; hold mode) Refresh time= + (TREFRESH[7:0]) x T LSI + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time (only valid + in sample &amp; hold mode) Refresh time= + (TREFRESH[7:0]) x T LSI + 16 + 8 + + + + + + + BDMA + BDMA + BDMA + 0x58025400 + + 0x0 + 0x400 + registers + + + BDMA_CH1 + BDMA channel 1 interrupt + 129 + + + BDMA_CH2 + BDMA channel 2 interrupt + 130 + + + BDMA_CH3 + BDMA channel 3 interrupt + 131 + + + BDMA_CH4 + BDMA channel 4 interrupt + 132 + + + BDMA_CH5 + BDMA channel 5 interrupt + 133 + + + BDMA_CH6 + BDMA channel 6 interrupt + 134 + + + BDMA_CH7 + BDMA channel 7 interrupt + 135 + + + BDMA_CH8 + BDMA channel 8 interrupt + 136 + + + + ISR + ISR + DMA interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 0 + 1 + + + TCIF1 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 1 + 1 + + + HTIF1 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 2 + 1 + + + TEIF1 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 3 + 1 + + + GIF2 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 4 + 1 + + + TCIF2 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 5 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 6 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 7 + 1 + + + GIF3 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 8 + 1 + + + TCIF3 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 9 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 10 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 11 + 1 + + + GIF4 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 12 + 1 + + + TCIF4 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 13 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 14 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 15 + 1 + + + GIF5 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 16 + 1 + + + TCIF5 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 17 + 1 + + + HTIF5 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 18 + 1 + + + TEIF5 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 19 + 1 + + + GIF6 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 20 + 1 + + + TCIF6 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 21 + 1 + + + HTIF6 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 22 + 1 + + + TEIF6 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 23 + 1 + + + GIF7 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 24 + 1 + + + TCIF7 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 25 + 1 + + + HTIF7 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 26 + 1 + + + TEIF7 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 27 + 1 + + + GIF8 + Channel x global interrupt flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 28 + 1 + + + TCIF8 + Channel x transfer complete flag (x = + 1..8) This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 29 + 1 + + + HTIF8 + Channel x half transfer flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 30 + 1 + + + TEIF8 + Channel x transfer error flag (x = 1..8) + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCR register. + 31 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear + register + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel x global interrupt clear This + bit is set and cleared by software. + 0 + 1 + + + CTCIF1 + Channel x transfer complete clear This + bit is set and cleared by software. + 1 + 1 + + + CHTIF1 + Channel x half transfer clear This bit + is set and cleared by software. + 2 + 1 + + + CTEIF1 + Channel x transfer error clear This bit + is set and cleared by software. + 3 + 1 + + + CGIF2 + Channel x global interrupt clear This + bit is set and cleared by software. + 4 + 1 + + + CTCIF2 + Channel x transfer complete clear This + bit is set and cleared by software. + 5 + 1 + + + CHTIF2 + Channel x half transfer clear This bit + is set and cleared by software. + 6 + 1 + + + CTEIF2 + Channel x transfer error clear This bit + is set and cleared by software. + 7 + 1 + + + CGIF3 + Channel x global interrupt clear This + bit is set and cleared by software. + 8 + 1 + + + CTCIF3 + Channel x transfer complete clear This + bit is set and cleared by software. + 9 + 1 + + + CHTIF3 + Channel x half transfer clear This bit + is set and cleared by software. + 10 + 1 + + + CTEIF3 + Channel x transfer error clear This bit + is set and cleared by software. + 11 + 1 + + + CGIF4 + Channel x global interrupt clear This + bit is set and cleared by software. + 12 + 1 + + + CTCIF4 + Channel x transfer complete clear This + bit is set and cleared by software. + 13 + 1 + + + CHTIF4 + Channel x half transfer clear This bit + is set and cleared by software. + 14 + 1 + + + CTEIF4 + Channel x transfer error clear This bit + is set and cleared by software. + 15 + 1 + + + CGIF5 + Channel x global interrupt clear This + bit is set and cleared by software. + 16 + 1 + + + CTCIF5 + Channel x transfer complete clear This + bit is set and cleared by software. + 17 + 1 + + + CHTIF5 + Channel x half transfer clear This bit + is set and cleared by software. + 18 + 1 + + + CTEIF5 + Channel x transfer error clear This bit + is set and cleared by software. + 19 + 1 + + + CGIF6 + Channel x global interrupt clear This + bit is set and cleared by software. + 20 + 1 + + + CTCIF6 + Channel x transfer complete clear This + bit is set and cleared by software. + 21 + 1 + + + CHTIF6 + Channel x half transfer clear This bit + is set and cleared by software. + 22 + 1 + + + CTEIF6 + Channel x transfer error clear This bit + is set and cleared by software. + 23 + 1 + + + CGIF7 + Channel x global interrupt clear This + bit is set and cleared by software. + 24 + 1 + + + CTCIF7 + Channel x transfer complete clear This + bit is set and cleared by software. + 25 + 1 + + + CHTIF7 + Channel x half transfer clear This bit + is set and cleared by software. + 26 + 1 + + + CTEIF7 + Channel x transfer error clear This bit + is set and cleared by software. + 27 + 1 + + + CGIF8 + Channel x global interrupt clear This + bit is set and cleared by software. + 28 + 1 + + + CTCIF8 + Channel x transfer complete clear This + bit is set and cleared by software. + 29 + 1 + + + CHTIF8 + Channel x half transfer clear This bit + is set and cleared by software. + 30 + 1 + + + CTEIF8 + Channel x transfer error clear This bit + is set and cleared by software. + 31 + 1 + + + + + CCR1 + CCR1 + DMA channel x configuration + register + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel x number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR1 + CPAR1 + This register must not be written when the + channel is enabled. + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR1 + CMAR1 + This register must not be written when the + channel is enabled. + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel x configuration + register + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel x number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR2 + CPAR2 + This register must not be written when the + channel is enabled. + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR2 + CMAR2 + This register must not be written when the + channel is enabled. + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel x configuration + register + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel x number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR3 + CPAR3 + This register must not be written when the + channel is enabled. + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR3 + CMAR3 + This register must not be written when the + channel is enabled. + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR4 + CCR4 + DMA channel x configuration + register + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR4 + CNDTR4 + DMA channel x number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR4 + CPAR4 + This register must not be written when the + channel is enabled. + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR4 + CMAR4 + This register must not be written when the + channel is enabled. + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR5 + CCR5 + DMA channel x configuration + register + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR5 + CNDTR5 + DMA channel x number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR5 + CPAR5 + This register must not be written when the + channel is enabled. + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR5 + CMAR5 + This register must not be written when the + channel is enabled. + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR6 + CCR6 + DMA channel x configuration + register + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR6 + CNDTR6 + DMA channel x number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR6 + CPAR6 + This register must not be written when the + channel is enabled. + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR6 + CMAR6 + This register must not be written when the + channel is enabled. + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR7 + CCR7 + DMA channel x configuration + register + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR7 + CNDTR7 + DMA channel x number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR7 + CPAR7 + This register must not be written when the + channel is enabled. + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR7 + CMAR7 + This register must not be written when the + channel is enabled. + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CCR8 + CCR8 + DMA channel x configuration + register + 0x94 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable This bit is set and + cleared by software. + 0 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 1 + 1 + + + HTIE + Half transfer interrupt enable This bit + is set and cleared by software. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 3 + 1 + + + DIR + Data transfer direction This bit is set + and cleared by software. + 4 + 1 + + + CIRC + Circular mode This bit is set and + cleared by software. + 5 + 1 + + + PINC + Peripheral increment mode This bit is + set and cleared by software. + 6 + 1 + + + MINC + Memory increment mode This bit is set + and cleared by software. + 7 + 1 + + + PSIZE + Peripheral size These bits are set and + cleared by software. + 8 + 2 + + + MSIZE + Memory size These bits are set and + cleared by software. + 10 + 2 + + + PL + Channel priority level These bits are + set and cleared by software. + 12 + 2 + + + MEM2MEM + Memory to memory mode This bit is set + and cleared by software. + 14 + 1 + + + + + CNDTR8 + CNDTR8 + DMA channel x number of data + register + 0x98 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer Number of + data to be transferred (0 up to 65535). This register + can only be written when the channel is disabled. + Once the channel is enabled, this register is + read-only, indicating the remaining bytes to be + transmitted. This register decrements after each DMA + transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded + automatically by the value previously programmed if + the channel is configured in auto-reload mode. If + this register is zero, no transaction can be served + whether the channel is enabled or not. + 0 + 16 + + + + + CPAR8 + CPAR8 + This register must not be written when the + channel is enabled. + 0x9C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address Base address of the + peripheral data register from/to which the data will + be read/written. When PSIZE is 01 (16-bit), the PA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When PSIZE is 10 (32-bit), PA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + CMAR8 + CMAR8 + This register must not be written when the + channel is enabled. + 0xA0 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Base address of the + memory area from/to which the data will be + read/written. When MSIZE is 01 (16-bit), the MA[0] + bit is ignored. Access is automatically aligned to a + half-word address. When MSIZE is 10 (32-bit), MA[1:0] + are ignored. Access is automatically aligned to a + word address. + 0 + 32 + + + + + + + DMA2D + DMA2D + DMA2D + 0x52001000 + + 0x0 + 0x400 + registers + + + DMA2D + DMA2D global interrupt + 90 + + + + CR + CR + DMA2D control register + 0x0 + 0x20 + read-write + 0x00000000 + + + START + Start This bit can be used to launch the + DMA2D according to the parameters loaded in the + various configuration registers + 0 + 1 + + + SUSP + Suspend This bit can be used to suspend + the current transfer. This bit is set and reset by + software. It is automatically reset by hardware when + the START bit is reset. + 1 + 1 + + + ABORT + Abort This bit can be used to abort the + current transfer. This bit is set by software and is + automatically reset by hardware when the START bit is + reset. + 2 + 1 + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 8 + 1 + + + TCIE + Transfer complete interrupt enable This + bit is set and cleared by software. + 9 + 1 + + + TWIE + Transfer watermark interrupt enable This + bit is set and cleared by software. + 10 + 1 + + + CAEIE + CLUT access error interrupt enable This + bit is set and cleared by software. + 11 + 1 + + + CTCIE + CLUT transfer complete interrupt enable + This bit is set and cleared by + software. + 12 + 1 + + + CEIE + Configuration Error Interrupt Enable + This bit is set and cleared by + software. + 13 + 1 + + + MODE + DMA2D mode This bit is set and cleared + by software. It cannot be modified while a transfer + is ongoing. + 16 + 2 + + + + + ISR + ISR + DMA2D Interrupt Status + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + TEIF + Transfer error interrupt flag This bit + is set when an error occurs during a DMA transfer + (data transfer or automatic CLUT + loading). + 0 + 1 + + + TCIF + Transfer complete interrupt flag This + bit is set when a DMA2D transfer operation is + complete (data transfer only). + 1 + 1 + + + TWIF + Transfer watermark interrupt flag This + bit is set when the last pixel of the watermarked + line has been transferred. + 2 + 1 + + + CAEIF + CLUT access error interrupt flag This + bit is set when the CPU accesses the CLUT while the + CLUT is being automatically copied from a system + memory to the internal DMA2D. + 3 + 1 + + + CTCIF + CLUT transfer complete interrupt flag + This bit is set when the CLUT copy from a system + memory area to the internal DMA2D memory is + complete. + 4 + 1 + + + CEIF + Configuration error interrupt flag This + bit is set when the START bit of DMA2D_CR, + DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong + configuration has been programmed. + 5 + 1 + + + + + IFCR + IFCR + DMA2D interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTEIF + Clear Transfer error interrupt flag + Programming this bit to 1 clears the TEIF flag in the + DMA2D_ISR register + 0 + 1 + + + CTCIF + Clear transfer complete interrupt flag + Programming this bit to 1 clears the TCIF flag in the + DMA2D_ISR register + 1 + 1 + + + CTWIF + Clear transfer watermark interrupt flag + Programming this bit to 1 clears the TWIF flag in the + DMA2D_ISR register + 2 + 1 + + + CAECIF + Clear CLUT access error interrupt flag + Programming this bit to 1 clears the CAEIF flag in + the DMA2D_ISR register + 3 + 1 + + + CCTCIF + Clear CLUT transfer complete interrupt + flag Programming this bit to 1 clears the CTCIF flag + in the DMA2D_ISR register + 4 + 1 + + + CCEIF + Clear configuration error interrupt flag + Programming this bit to 1 clears the CEIF flag in the + DMA2D_ISR register + 5 + 1 + + + + + FGMAR + FGMAR + DMA2D foreground memory address + register + 0xC + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the foreground image. This register can only be + written when data transfers are disabled. Once the + data transfer has started, this register is + read-only. The address alignment must match the image + format selected e.g. a 32-bit per pixel format must + be 32-bit aligned, a 16-bit per pixel format must be + 16-bit aligned and a 4-bit per pixel format must be + 8-bit aligned. + 0 + 32 + + + + + FGOR + FGOR + DMA2D foreground offset + register + 0x10 + 0x20 + read-write + 0x00000000 + + + LO + Line offset Line offset used for the + foreground expressed in pixel. This value is used to + generate the address. It is added at the end of each + line to determine the starting address of the next + line. These bits can only be written when data + transfers are disabled. Once a data transfer has + started, they become read-only. If the image format + is 4-bit per pixel, the line offset must be + even. + 0 + 14 + + + + + BGMAR + BGMAR + DMA2D background memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the background image. This register can only be + written when data transfers are disabled. Once a data + transfer has started, this register is read-only. The + address alignment must match the image format + selected e.g. a 32-bit per pixel format must be + 32-bit aligned, a 16-bit per pixel format must be + 16-bit aligned and a 4-bit per pixel format must be + 8-bit aligned. + 0 + 32 + + + + + BGOR + BGOR + DMA2D background offset + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LO + Line offset Line offset used for the + background image (expressed in pixel). This value is + used for the address generation. It is added at the + end of each line to determine the starting address of + the next line. These bits can only be written when + data transfers are disabled. Once data transfer has + started, they become read-only. If the image format + is 4-bit per pixel, the line offset must be + even. + 0 + 14 + + + + + FGPFCCR + FGPFCCR + DMA2D foreground PFC control + register + 0x1C + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits defines the color + format of the foreground image. They can only be + written when data transfers are disabled. Once the + transfer has started, they are read-only. others: + meaningless + 0 + 4 + + + CCM + CLUT color mode This bit defines the + color format of the CLUT. It can only be written when + the transfer is disabled. Once the CLUT transfer has + started, this bit is read-only. + 4 + 1 + + + START + Start This bit can be set to start the + automatic loading of the CLUT. It is automatically + reset: ** at the end of the transfer ** when the + transfer is aborted by the user application by + setting the ABORT bit in DMA2D_CR ** when a transfer + error occurs ** when the transfer has not started due + to a configuration error or another transfer + operation already ongoing (data transfer or automatic + background CLUT transfer). + 5 + 1 + + + CS + CLUT size These bits define the size of + the CLUT used for the foreground image. Once the CLUT + transfer has started, this field is read-only. The + number of CLUT entries is equal to CS[7:0] + + 1. + 8 + 8 + + + AM + Alpha mode These bits select the alpha + channel value to be used for the foreground image. + They can only be written data the transfer are + disabled. Once the transfer has started, they become + read-only. other configurations are + meaningless + 16 + 2 + + + CSS + Chroma Sub-Sampling These bits define + the chroma sub-sampling mode for YCbCr color mode. + Once the transfer has started, these bits are + read-only. others: meaningless + 18 + 2 + + + AI + Alpha Inverted This bit inverts the + alpha value. Once the transfer has started, this bit + is read-only. + 20 + 1 + + + RBS + Red Blue Swap This bit allows to swap + the R &amp; B to support BGR or ABGR color + formats. Once the transfer has started, this bit is + read-only. + 21 + 1 + + + ALPHA + Alpha value These bits define a fixed + alpha channel value which can replace the original + alpha value or be multiplied by the original alpha + value according to the alpha mode selected through + the AM[1:0] bits. These bits can only be written when + data transfers are disabled. Once a transfer has + started, they become read-only. + 24 + 8 + + + + + FGCOLR + FGCOLR + DMA2D foreground color + register + 0x20 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits defines the blue + value for the A4 or A8 mode of the foreground image. + They can only be written when data transfers are + disabled. Once the transfer has started, They are + read-only. + 0 + 8 + + + GREEN + Green Value These bits defines the green + value for the A4 or A8 mode of the foreground image. + They can only be written when data transfers are + disabled. Once the transfer has started, They are + read-only. + 8 + 8 + + + RED + Red Value These bits defines the red + value for the A4 or A8 mode of the foreground image. + They can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 16 + 8 + + + + + BGPFCCR + BGPFCCR + DMA2D background PFC control + register + 0x24 + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits define the color + format of the foreground image. These bits can only + be written when data transfers are disabled. Once the + transfer has started, they are read-only. others: + meaningless + 0 + 4 + + + CCM + CLUT Color mode These bits define the + color format of the CLUT. This register can only be + written when the transfer is disabled. Once the CLUT + transfer has started, this bit is + read-only. + 4 + 1 + + + START + Start This bit is set to start the + automatic loading of the CLUT. This bit is + automatically reset: ** at the end of the transfer ** + when the transfer is aborted by the user application + by setting the ABORT bit in the DMA2D_CR ** when a + transfer error occurs ** when the transfer has not + started due to a configuration error or another + transfer operation already on going (data transfer or + automatic BackGround CLUT transfer). + 5 + 1 + + + CS + CLUT size These bits define the size of + the CLUT used for the BG. Once the CLUT transfer has + started, this field is read-only. The number of CLUT + entries is equal to CS[7:0] + 1. + 8 + 8 + + + AM + Alpha mode These bits define which alpha + channel value to be used for the background image. + These bits can only be written when data transfers + are disabled. Once the transfer has started, they are + read-only. others: meaningless + 16 + 2 + + + AI + Alpha Inverted This bit inverts the + alpha value. Once the transfer has started, this bit + is read-only. + 20 + 1 + + + RBS + Red Blue Swap This bit allows to swap + the R &amp; B to support BGR or ABGR color + formats. Once the transfer has started, this bit is + read-only. + 21 + 1 + + + ALPHA + Alpha value These bits define a fixed + alpha channel value which can replace the original + alpha value or be multiplied with the original alpha + value according to the alpha mode selected with bits + AM[1: 0]. These bits can only be written when data + transfers are disabled. Once the transfer has + started, they are read-only. + 24 + 8 + + + + + BGCOLR + BGCOLR + DMA2D background color + register + 0x28 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits define the blue + value for the A4 or A8 mode of the background. These + bits can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 0 + 8 + + + GREEN + Green Value These bits define the green + value for the A4 or A8 mode of the background. These + bits can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 8 + 8 + + + RED + Red Value These bits define the red + value for the A4 or A8 mode of the background. These + bits can only be written when data transfers are + disabled. Once the transfer has started, they are + read-only. + 16 + 8 + + + + + FGCMAR + FGCMAR + DMA2D foreground CLUT memory address + register + 0x2C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address Address of the data used + for the CLUT address dedicated to the foreground + image. This register can only be written when no + transfer is ongoing. Once the CLUT transfer has + started, this register is read-only. If the + foreground CLUT format is 32-bit, the address must be + 32-bit aligned. + 0 + 32 + + + + + BGCMAR + BGCMAR + DMA2D background CLUT memory address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the CLUT address dedicated to the background + image. This register can only be written when no + transfer is on going. Once the CLUT transfer has + started, this register is read-only. If the + background CLUT format is 32-bit, the address must be + 32-bit aligned. + 0 + 32 + + + + + OPFCCR + OPFCCR + DMA2D output PFC control + register + 0x34 + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits define the color + format of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are read-only. others: + meaningless + 0 + 3 + + + AI + Alpha Inverted This bit inverts the + alpha value. Once the transfer has started, this bit + is read-only. + 20 + 1 + + + RBS + Red Blue Swap This bit allows to swap + the R &amp; B to support BGR or ABGR color + formats. Once the transfer has started, this bit is + read-only. + 21 + 1 + + + + + OCOLR + OCOLR + DMA2D output color register + 0x38 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits define the blue + value of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 0 + 8 + + + GREEN + Green Value These bits define the green + value of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 8 + 8 + + + RED + Red Value These bits define the red + value of the output image. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 16 + 8 + + + ALPHA + Alpha Channel Value These bits define + the alpha channel of the output color. These bits can + only be written when data transfers are disabled. + Once the transfer has started, they are + read-only. + 24 + 8 + + + + + OMAR + OMAR + DMA2D output memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address Address of the data used + for the output FIFO. These bits can only be written + when data transfers are disabled. Once the transfer + has started, they are read-only. The address + alignment must match the image format selected e.g. a + 32-bit per pixel format must be 32-bit aligned and a + 16-bit per pixel format must be 16-bit + aligned. + 0 + 32 + + + + + OOR + OOR + DMA2D output offset register + 0x40 + 0x20 + read-write + 0x00000000 + + + LO + Line Offset Line offset used for the + output (expressed in pixels). This value is used for + the address generation. It is added at the end of + each line to determine the starting address of the + next line. These bits can only be written when data + transfers are disabled. Once the transfer has + started, they are read-only. + 0 + 14 + + + + + NLR + NLR + DMA2D number of line register + 0x44 + 0x20 + read-write + 0x00000000 + + + NL + Number of lines Number of lines of the + area to be transferred. These bits can only be + written when data transfers are disabled. Once the + transfer has started, they are + read-only. + 0 + 16 + + + PL + Pixel per lines Number of pixels per + lines of the area to be transferred. These bits can + only be written when data transfers are disabled. + Once the transfer has started, they are read-only. If + any of the input image format is 4-bit per pixel, + pixel per lines must be even. + 16 + 14 + + + + + LWR + LWR + DMA2D line watermark register + 0x48 + 0x20 + read-write + 0x00000000 + + + LW + Line watermark These bits allow to + configure the line watermark for interrupt + generation. An interrupt is raised when the last + pixel of the watermarked line has been transferred. + These bits can only be written when data transfers + are disabled. Once the transfer has started, they are + read-only. + 0 + 16 + + + + + AMTCR + AMTCR + DMA2D AXI master timer configuration + register + 0x4C + 0x20 + read-write + 0x00000000 + + + EN + Enable Enables the dead time + functionality. + 0 + 1 + + + DT + Dead Time Dead time value in the AXI + clock cycle inserted between two consecutive accesses + on the AXI master port. These bits represent the + minimum guaranteed number of cycles between two + consecutive AXI accesses. + 8 + 8 + + + + + + + DMAMUX2 + DMAMUX + DMAMUX + 0x58025800 + + 0x0 + 0x400 + registers + + + DMAMUX2_OVR + DMAMUX2 overrun interrupt + 128 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer + channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer + channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer + channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer + channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer + channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer + channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer + channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer + channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x + control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x + control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x + control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x + control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG4CR + RG4CR + DMAMux - DMA request generator channel x + control register + 0x110 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG5CR + RG5CR + DMAMux - DMA request generator channel x + control register + 0x114 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG6CR + RG6CR + DMAMux - DMA request generator channel x + control register + 0x118 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG7CR + RG7CR + DMAMux - DMA request generator channel x + control register + 0x11C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is + set when a trigger event occurs on DMA request + generator channel x, while the DMA request generator + counter value is lower than GNBREQ. The flag is + cleared by writing 1 to the corresponding COFx bit in + DMAMUX_RGCFR register. + 0 + 8 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag + register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon + setting, this bit clears the corresponding overrun + flag OFx in the DMAMUX_RGCSR register. + 0 + 8 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt + channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event + flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt + clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event + flag + 0 + 16 + + + + + + + FMC + FMC + FMC + 0x52004000 + + 0x0 + 0x400 + registers + + + FMC + FMC global interrupt + 48 + + + + BCR1 + BCR1 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x0 + 0x20 + read-write + 0x000030DB + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR1 + BTR1 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BCR2 + BCR2 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x8 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR2 + BTR2 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 1. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BCR3 + BCR3 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x10 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR3 + BTR3 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + &#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BCR4 + BCR4 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x18 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit This bit enables + the memory bank. After reset Bank1 is enabled, all + others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + When this bit is set, the address and data values are + multiplexed on the data bus, valid only with NOR and + PSRAM memories: + 1 + 1 + + + MTYP + Memory type These bits define the type + of external memory attached to the corresponding + memory bank: + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable This bit enables NOR + Flash memory access operations. + 6 + 1 + + + BURSTEN + Burst enable bit This bit + enables/disables synchronous accesses during read + operations. It is valid only for synchronous memories + operating in Burst mode: + 8 + 1 + + + WAITPOL + Wait signal polarity bit This bit + defines the polarity of the wait signal from memory + used for either in synchronous or asynchronous + mode: + 9 + 1 + + + WAITCFG + Wait timing configuration The NWAIT + signal indicates whether the data from the memory are + valid or if a wait state must be inserted when + accessing the memory in synchronous mode. This + configuration bit determines if NWAIT is asserted by + the memory one clock cycle before the wait state or + during the wait state: + 11 + 1 + + + WREN + Write enable bit This bit indicates + whether write operations are enabled/disabled in the + bank by the FMC: + 12 + 1 + + + WAITEN + Wait enable bit This bit + enables/disables wait-state insertion via the NWAIT + signal when accessing the memory in synchronous + mode. + 13 + 1 + + + EXTMOD + Extended mode enable. This bit enables + the FMC to program the write timings for asynchronous + accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. + Note: When the extended mode is disabled, the FMC can + operate in Mode1 or Mode2 as follows: ** Mode 1 is + the default mode when the SRAM/PSRAM memory type is + selected (MTYP =0x0 or 0x01) ** Mode 2 is the default + mode when the NOR memory type is selected (MTYP = + 0x10). + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers This bit enables/disables the FMC to use + the wait signal even during an asynchronous + protocol. + 15 + 1 + + + CPSIZE + CRAM Page Size These are used for + Cellular RAM 1.5 which does not allow burst access to + cross the address boundaries between pages. When + these bits are configured, the FMC controller splits + automatically the burst access when the memory page + size is reached (refer to memory datasheet for page + size). Other configuration: reserved. + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode, the bit enables synchronous + accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the + FMC_BCRx register. + 19 + 1 + + + CCLKEN + Continuous Clock Enable This bit enables + the FMC_CLK clock output to external memory devices. + Note: The CCLKEN bit of the FMC_BCR2..4 registers is + dont care. It is only enabled through the FMC_BCR1 + register. Bank 1 must be configured in synchronous + mode to generate the FMC_CLK continuous clock. If + CCLKEN bit is set, the FMC_CLK clock ratio is + specified by CLKDIV value in the FMC_BTR1 register. + CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous + memories connected to other banks than Bank 1 are + clocked by the same clock (the CLKDIV value in the + FMC_BTR2..4 and FMC_BWTR2..4 registers for other + banks has no effect.) + 20 + 1 + + + WFDIS + Write FIFO Disable This bit disables the + Write FIFO used by the FMC controller. Note: The + WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 + register. + 21 + 1 + + + BMAP + FMC bank mapping These bits allows + different to remap SDRAM bank2 or swap the FMC + NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: + The BMAP bits of the FMC_BCR2..4 registers are dont + care. It is only enabled through the FMC_BCR1 + register. + 24 + 2 + + + FMCEN + FMC controller Enable This bit + enables/disables the FMC controller. Note: The FMCEN + bit of the FMC_BCR2..4 registers is dont care. It is + only enabled through the FMC_BCR1 + register. + 31 + 1 + + + + + BTR4 + BTR4 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for + write and read access, that is, 2 registers are + available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx + registers). + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration These bits + are written by software to define the duration of the + address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For + each access mode address setup phase duration, please + refer to the respective figure (refer to Figure81 to + Figure93). Note: In synchronous accesses, this value + is dont care. In Muxed mode or Mode D, the minimum + value for ADDSET is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each + access mode address-hold phase duration, please refer + to the respective figure (Figure81 to Figure93). + Note: In synchronous accesses, this value is not + used, the address hold phase is always 1 memory clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous accesses: For each memory type and + access mode data-phase duration, please refer to the + respective figure (Figure81 to Figure93). Example: + Mode1, write access, DATAST=1: Data-phase duration= + DATAST+1 = 2 KCK_FMC clock cycles. Note: In + synchronous accesses, this value is dont + care. + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between + an asynchronous read (in muxed or mode D) or write + transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation + is performed, the bank can be the same or a different + one, whereas it must be different in case of write + operation to the bank, except in muxed mode or mode + D. In some cases, whatever the programmed BUSTRUN + values, the bus turnaround delay is fixed as follows: + The bus turnaround delay is not inserted between two + consecutive asynchronous write transfers to the same + static memory bank except in muxed mode and mode D. + There is a bus turnaround delay of 1 FMC clock cycle + between: Two consecutive asynchronous read transfers + to the same static memory bank except for modes muxed + and D. An asynchronous read to an asynchronous or + synchronous write to any static bank or dynamic bank + except in modes muxed and D mode. There is a bus + turnaround delay of 2 FMC clock cycle between: Two + consecutive synchronous write operations (in Burst or + Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or + read transfer to or from static memory bank (the bank + can be the same or a different one in case of a read + operation. Two consecutive synchronous read + operations (in Burst or Single mode) followed by any + synchronous/asynchronous read or write from/to + another static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive + synchronous write operations (in Burst or Single + mode) to different static banks. A synchronous write + access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus + turnaround delay allows to match the minimum time + between consecutive transactions (tEHEL from NEx high + to NEx low) and the maximum time required by the + memory to free the data bus after a read access + (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; + tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + &#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1. + ... + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + These bits define the period of FMC_CLK clock output + signal, expressed in number of KCK_FMC cycles: In + asynchronous NOR Flash, SRAM or PSRAM accesses, this + value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio + formula) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + these bits define the number of memory clock + cycles + 24 + 4 + + + ACCMOD + Access mode These bits specify the + asynchronous access modes as shown in the timing + diagrams. They are taken into account only when the + EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + PCR + PCR + NAND Flash control registers + 0x80 + 0x20 + read-write + 0x00000018 + + + PWAITEN + Wait feature enable bit. This bit + enables the Wait feature for the NAND Flash memory + bank: + 1 + 1 + + + PBKEN + NAND Flash memory bank enable bit. This + bit enables the memory bank. Accessing a disabled + memory bank causes an ERROR on AXI bus + 2 + 1 + + + PWID + Data bus width. These bits define the + external memory device width. + 4 + 2 + + + ECCEN + ECC computation logic enable + bit + 6 + 1 + + + TCLR + CLE to RE delay. These bits set time + from CLE low to RE low in number of KCK_FMC clock + cycles. The time is give by the following formula: + t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is + the KCK_FMC clock period Note: Set is MEMSET or + ATTSET according to the addressed + space. + 9 + 4 + + + TAR + ALE to RE delay. These bits set time + from ALE low to RE low in number of KCK_FMC clock + cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC + where TKCK_FMC is the FMC clock period Note: Set is + MEMSET or ATTSET according to the addressed + space. + 13 + 4 + + + ECCPS + ECC page size. These bits define the + page size for the extended ECC: + 17 + 3 + + + + + SR + SR + This register contains information about the + FIFO status and interrupt. The FMC features a FIFO that + is used when writing to memories to transfer up to 16 + words of data.This is used to quickly write to the FIFO + and free the AXI bus for transactions to peripherals + other than the FMC, while the FMC is draining its FIFO + into the memory. One of these register bits indicates the + status of the FIFO, for ECC purposes.The ECC is + calculated while the data are written to the memory. To + read the correct ECC, the software must consequently wait + until the FIFO is empty. + 0x84 + 0x20 + 0x00000040 + + + IRS + Interrupt rising edge status The flag is + set by hardware and reset by software. Note: If this + bit is written by software to 1 it will be + set. + 0 + 1 + read-write + + + ILS + Interrupt high-level status The flag is + set by hardware and reset by software. + 1 + 1 + read-write + + + IFS + Interrupt falling edge status The flag + is set by hardware and reset by software. Note: If + this bit is written by software to 1 it will be + set. + 2 + 1 + read-write + + + IREN + Interrupt rising edge detection enable + bit + 3 + 1 + read-write + + + ILEN + Interrupt high-level detection enable + bit + 4 + 1 + read-write + + + IFEN + Interrupt falling edge detection enable + bit + 5 + 1 + read-write + + + FEMPT + FIFO empty. Read-only bit that provides + the status of the FIFO + 6 + 1 + read-only + + + + + PMEM + PMEM + The FMC_PMEM read/write register contains + the timing information for NAND Flash memory bank. This + information is used to access either the common memory + space of the NAND Flash for command, address write access + and data read/write access. + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMSET + Common memory x setup time These bits + define the number of KCK_FMC (+1) clock cycles to set + up the address before the command assertion (NWE, + NOE), for NAND Flash read or write access to common + memory space: + 0 + 8 + + + MEMWAIT + Common memory wait time These bits + define the minimum number of KCK_FMC (+1) clock + cycles to assert the command (NWE, NOE), for NAND + Flash read or write access to common memory space. + The duration of command assertion is extended if the + wait signal (NWAIT) is active (low) at the end of the + programmed value of KCK_FMC: + 8 + 8 + + + MEMHOLD + Common memory hold time These bits + define the number of KCK_FMC clock cycles for write + accesses and KCK_FMC+1 clock cycles for read accesses + during which the address is held (and data for write + accesses) after the command is de-asserted (NWE, + NOE), for NAND Flash read or write access to common + memory space: + 16 + 8 + + + MEMHIZ + Common memory x data bus Hi-Z time These + bits define the number of KCK_FMC clock cycles during + which the data bus is kept Hi-Z after the start of a + NAND Flash write access to common memory space. This + is only valid for write transactions: + 24 + 8 + + + + + PATT + PATT + The FMC_PATT read/write register contains + the timing information for NAND Flash memory bank. It is + used for 8-bit accesses to the attribute memory space of + the NAND Flash for the last address write access if the + timing must differ from that of previous accesses (for + Ready/Busy management, refer to Section20.8.5: NAND Flash + prewait feature). + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTSET + Attribute memory setup time These bits + define the number of KCK_FMC (+1) clock cycles to set + up address before the command assertion (NWE, NOE), + for NAND Flash read or write access to attribute + memory space: + 0 + 8 + + + ATTWAIT + Attribute memory wait time These bits + define the minimum number of x KCK_FMC (+1) clock + cycles to assert the command (NWE, NOE), for NAND + Flash read or write access to attribute memory space. + The duration for command assertion is extended if the + wait signal (NWAIT) is active (low) at the end of the + programmed value of KCK_FMC: + 8 + 8 + + + ATTHOLD + Attribute memory hold time These bits + define the number of KCK_FMC clock cycles during + which the address is held (and data for write access) + after the command de-assertion (NWE, NOE), for NAND + Flash read or write access to attribute memory + space: + 16 + 8 + + + ATTHIZ + Attribute memory data bus Hi-Z time + These bits define the number of KCK_FMC clock cycles + during which the data bus is kept in Hi-Z after the + start of a NAND Flash write access to attribute + memory space on socket. Only valid for writ + transaction: + 24 + 8 + + + + + ECCR + ECCR + This register contain the current error + correction code value computed by the ECC computation + modules of the FMC NAND controller. When the CPU + reads/writes the data from a NAND Flash memory page at + the correct address (refer to Section20.8.6: Computation + of the error correction code (ECC) in NAND Flash memory), + the data read/written from/to the NAND Flash memory are + processed automatically by the ECC computation module. + When X bytes have been read (according to the ECCPS field + in the FMC_PCR registers), the CPU must read the computed + ECC value from the FMC_ECC registers. It then verifies if + these computed parity data are the same as the parity + value recorded in the spare area, to determine whether a + page is valid, and, to correct it otherwise. The FMC_ECCR + register should be cleared after being read by setting + the ECCEN bit to 0. To compute a new data block, the + ECCEN bit must be set to 1. + 0x94 + 0x20 + read-only + 0x00000000 + + + ECC + ECC result This field contains the value + computed by the ECC computation logic. Table167 + describes the contents of these bit + fields. + 0 + 32 + + + + + BWTR1 + BWTR1 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BWTR2 + BWTR2 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BWTR3 + BWTR3 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + BWTR4 + BWTR4 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active + for write access. + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration. These bits + are written by software to define the duration of the + address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: + ... Note: In synchronous accesses, this value is not + used, the address setup phase is always 1 Flash clock + period duration. In muxed mode, the minimum ADDSET + value is 1. + 0 + 4 + + + ADDHLD + Address-hold phase duration. These bits + are written by software to define the duration of the + address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: + In synchronous NOR Flash accesses, this value is not + used, the address hold phase is always 1 Flash clock + period duration. + 4 + 4 + + + DATAST + Data-phase duration. These bits are + written by software to define the duration of the + data phase (refer to Figure81 to Figure93), used in + asynchronous SRAM, PSRAM and NOR Flash memory + accesses: + 8 + 8 + + + BUSTURN + Bus turnaround phase duration These bits + are written by software to add a delay at the end of + a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx + low): (BUSTRUN + 1) KCK_FMC period &#8805; + tEHELmin. The programmed bus turnaround delay is + inserted between a an asynchronous write transfer and + any other asynchronous /synchronous read or write + transfer to or from a static bank. If a read + operation is performed, the bank can be the same or a + different one, whereas it must be different in case + of write operation to the bank, except in muxed mode + or mode D. In some cases, whatever the programmed + BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted + between two consecutive asynchronous write transfers + to the same static memory bank except for muxed mode + and mode D. There is a bus turnaround delay of 2 FMC + clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or + Single mode) and an asynchronous write or read + transfer to or from static memory bank. There is a + bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in + Burst or Single mode) to different static banks. A + synchronous write transfer (in Burst or Single mode) + and a synchronous read from the same or a different + bank. ... + 16 + 4 + + + ACCMOD + Access mode. These bits specify the + asynchronous access modes as shown in the next timing + diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is + 1. + 28 + 2 + + + + + SDCR1 + SDCR1 + This register contains the control + parameters for each SDRAM memory bank + 0x140 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address bits These bits + define the number of bits of a column + address. + 0 + 2 + + + NR + Number of row address bits These bits + define the number of bits of a row + address. + 2 + 2 + + + MWID + Memory data bus width. These bits define + the memory device width. + 4 + 2 + + + NB + Number of internal banks This bit sets + the number of internal banks. + 6 + 1 + + + CAS + CAS Latency This bits sets the SDRAM CAS + latency in number of memory clock + cycles + 7 + 2 + + + WP + Write protection This bit enables write + mode access to the SDRAM bank. + 9 + 1 + + + SDCLK + SDRAM clock configuration These bits + define the SDRAM clock period for both SDRAM banks + and allow disabling the clock before changing the + frequency. In this case the SDRAM must be + re-initialized. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 10 + 2 + + + RBURST + Burst read This bit enables burst read + mode. The SDRAM controller anticipates the next read + commands during the CAS latency and stores data in + the Read FIFO. Note: The corresponding bit in the + FMC_SDCR2 register is read only. + 12 + 1 + + + RPIPE + Read pipe These bits define the delay, + in KCK_FMC clock cycles, for reading data after CAS + latency. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 13 + 2 + + + + + SDCR2 + SDCR2 + This register contains the control + parameters for each SDRAM memory bank + 0x144 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address bits These bits + define the number of bits of a column + address. + 0 + 2 + + + NR + Number of row address bits These bits + define the number of bits of a row + address. + 2 + 2 + + + MWID + Memory data bus width. These bits define + the memory device width. + 4 + 2 + + + NB + Number of internal banks This bit sets + the number of internal banks. + 6 + 1 + + + CAS + CAS Latency This bits sets the SDRAM CAS + latency in number of memory clock + cycles + 7 + 2 + + + WP + Write protection This bit enables write + mode access to the SDRAM bank. + 9 + 1 + + + SDCLK + SDRAM clock configuration These bits + define the SDRAM clock period for both SDRAM banks + and allow disabling the clock before changing the + frequency. In this case the SDRAM must be + re-initialized. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 10 + 2 + + + RBURST + Burst read This bit enables burst read + mode. The SDRAM controller anticipates the next read + commands during the CAS latency and stores data in + the Read FIFO. Note: The corresponding bit in the + FMC_SDCR2 register is read only. + 12 + 1 + + + RPIPE + Read pipe These bits define the delay, + in KCK_FMC clock cycles, for reading data after CAS + latency. Note: The corresponding bits in the + FMC_SDCR2 register is read only. + 13 + 2 + + + + + SDTR1 + SDTR1 + This register contains the timing parameters + of each SDRAM bank + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to Active These bits + define the delay between a Load Mode Register command + and an Active or Refresh command in number of memory + clock cycles. .... + 0 + 4 + + + TXSR + Exit Self-refresh delay These bits + define the delay from releasing the Self-refresh + command to issuing the Activate command in number of + memory clock cycles. .... Note: If two SDRAM devices + are used, the FMC_SDTR1 and FMC_SDTR2 must be + programmed with the same TXSR timing corresponding to + the slowest SDRAM device. + 4 + 4 + + + TRAS + Self refresh time These bits define the + minimum Self-refresh period in number of memory clock + cycles. .... + 8 + 4 + + + TRC + Row cycle delay These bits define the + delay between the Refresh command and the Activate + command, as well as the delay between two consecutive + Refresh commands. It is expressed in number of memory + clock cycles. The TRC timing is only configured in + the FMC_SDTR1 register. If two SDRAM devices are + used, the TRC must be programmed with the timings of + the slowest device. .... Note: TRC must match the TRC + and TRFC (Auto Refresh period) timings defined in the + SDRAM device datasheet. Note: The corresponding bits + in the FMC_SDTR2 register are dont + care. + 12 + 4 + + + TWR + Recovery delay These bits define the + delay between a Write and a Precharge command in + number of memory clock cycles. .... Note: TWR must be + programmed to match the write recovery time (tWR) + defined in the SDRAM datasheet, and to guarantee + that: TWR &#8805; TRAS - TRCD and TWR + &#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles, + TRCD= 2 cycles. So, TWR &gt;= 2 cycles. TWR must + be programmed to 0x1. If two SDRAM devices are used, + the FMC_SDTR1 and FMC_SDTR2 must be programmed with + the same TWR timing corresponding to the slowest + SDRAM device. + 16 + 4 + + + TRP + Row precharge delay These bits define + the delay between a Precharge command and another + command in number of memory clock cycles. The TRP + timing is only configured in the FMC_SDTR1 register. + If two SDRAM devices are used, the TRP must be + programmed with the timing of the slowest device. + .... Note: The corresponding bits in the FMC_SDTR2 + register are dont care. + 20 + 4 + + + TRCD + Row to column delay These bits define + the delay between the Activate command and a + Read/Write command in number of memory clock cycles. + .... + 24 + 4 + + + + + SDTR2 + SDTR2 + This register contains the timing parameters + of each SDRAM bank + 0x14C + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to Active These bits + define the delay between a Load Mode Register command + and an Active or Refresh command in number of memory + clock cycles. .... + 0 + 4 + + + TXSR + Exit Self-refresh delay These bits + define the delay from releasing the Self-refresh + command to issuing the Activate command in number of + memory clock cycles. .... Note: If two SDRAM devices + are used, the FMC_SDTR1 and FMC_SDTR2 must be + programmed with the same TXSR timing corresponding to + the slowest SDRAM device. + 4 + 4 + + + TRAS + Self refresh time These bits define the + minimum Self-refresh period in number of memory clock + cycles. .... + 8 + 4 + + + TRC + Row cycle delay These bits define the + delay between the Refresh command and the Activate + command, as well as the delay between two consecutive + Refresh commands. It is expressed in number of memory + clock cycles. The TRC timing is only configured in + the FMC_SDTR1 register. If two SDRAM devices are + used, the TRC must be programmed with the timings of + the slowest device. .... Note: TRC must match the TRC + and TRFC (Auto Refresh period) timings defined in the + SDRAM device datasheet. Note: The corresponding bits + in the FMC_SDTR2 register are dont + care. + 12 + 4 + + + TWR + Recovery delay These bits define the + delay between a Write and a Precharge command in + number of memory clock cycles. .... Note: TWR must be + programmed to match the write recovery time (tWR) + defined in the SDRAM datasheet, and to guarantee + that: TWR &#8805; TRAS - TRCD and TWR + &#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles, + TRCD= 2 cycles. So, TWR &gt;= 2 cycles. TWR must + be programmed to 0x1. If two SDRAM devices are used, + the FMC_SDTR1 and FMC_SDTR2 must be programmed with + the same TWR timing corresponding to the slowest + SDRAM device. + 16 + 4 + + + TRP + Row precharge delay These bits define + the delay between a Precharge command and another + command in number of memory clock cycles. The TRP + timing is only configured in the FMC_SDTR1 register. + If two SDRAM devices are used, the TRP must be + programmed with the timing of the slowest device. + .... Note: The corresponding bits in the FMC_SDTR2 + register are dont care. + 20 + 4 + + + TRCD + Row to column delay These bits define + the delay between the Activate command and a + Read/Write command in number of memory clock cycles. + .... + 24 + 4 + + + + + SDCMR + SDCMR + This register contains the command issued + when the SDRAM device is accessed. This register is used + to initialize the SDRAM device, and to activate the + Self-refresh and the Power-down modes. As soon as the + MODE field is written, the command will be issued only to + one or to both SDRAM banks according to CTB1 and CTB2 + command bits. This register is the same for both SDRAM + banks. + 0x150 + 0x20 + read-write + 0x00000000 + + + MODE + Command mode These bits define the + command issued to the SDRAM device. Note: When a + command is issued, at least one Command Target Bank + bit ( CTB1 or CTB2) must be set otherwise the command + will be ignored. Note: If two SDRAM banks are used, + the Auto-refresh and PALL command must be issued + simultaneously to the two devices with CTB1 and CTB2 + bits set otherwise the command will be ignored. Note: + If only one SDRAM bank is used and a command is + issued with its associated CTB bit set, the other CTB + bit of the unused bank must be kept to + 0. + 0 + 3 + + + CTB2 + Command Target Bank 2 This bit indicates + whether the command will be issued to SDRAM Bank 2 or + not. + 3 + 1 + + + CTB1 + Command Target Bank 1 This bit indicates + whether the command will be issued to SDRAM Bank 1 or + not. + 4 + 1 + + + NRFS + Number of Auto-refresh These bits define + the number of consecutive Auto-refresh commands + issued when MODE = 011. .... + 5 + 4 + + + MRD + Mode Register definition This 14-bit + field defines the SDRAM Mode Register content. The + Mode Register is programmed using the Load Mode + Register command. The MRD[13:0] bits are also used to + program the extended mode register for mobile + SDRAM. + 9 + 14 + + + + + SDRTR + SDRTR + This register sets the refresh rate in + number of SDCLK clock cycles between the refresh cycles + by configuring the Refresh Timer Count value.Examplewhere + 64 ms is the SDRAM refresh period.The refresh rate must + be increased by 20 SDRAM clock cycles (as in the above + example) to obtain a safe margin if an internal refresh + request occurs when a read request has been accepted. It + corresponds to a COUNT value of 0000111000000 (448). This + 13-bit field is loaded into a timer which is decremented + using the SDRAM clock. This timer generates a refresh + pulse when zero is reached. The COUNT value must be set + at least to 41 SDRAM clock cycles.As soon as the + FMC_SDRTR register is programmed, the timer starts + counting. If the value programmed in the register is 0, + no refresh is carried out. This register must not be + reprogrammed after the initialization procedure to avoid + modifying the refresh rate.Each time a refresh pulse is + generated, this 13-bit COUNT field is reloaded into the + counter.If a memory access is in progress, the + Auto-refresh request is delayed. However, if the memory + access and Auto-refresh requests are generated + simultaneously, the Auto-refresh takes precedence. If the + memory access occurs during a refresh operation, the + request is buffered to be processed when the refresh is + complete.This register is common to SDRAM bank 1 and bank + 2. + 0x154 + 0x20 + 0x00000000 + + + CRE + Clear Refresh error flag This bit is + used to clear the Refresh Error Flag (RE) in the + Status Register. + 0 + 1 + write-only + + + COUNT + Refresh Timer Count This 13-bit field + defines the refresh rate of the SDRAM device. It is + expressed in number of memory clock cycles. It must + be set at least to 41 SDRAM clock cycles (0x29). + Refresh rate = (COUNT + 1) x SDRAM frequency clock + COUNT = (SDRAM refresh period / Number of rows) - + 20 + 1 + 13 + read-write + + + REIE + RES Interrupt Enable + 14 + 1 + read-write + + + + + SDSR + SDSR + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + RE + Refresh error flag An interrupt is + generated if REIE = 1 and RE = 1 + 0 + 1 + + + MODES1 + Status Mode for Bank 1 These bits define + the Status Mode of SDRAM Bank 1. + 1 + 2 + + + MODES2 + Status Mode for Bank 2 These bits define + the Status Mode of SDRAM Bank 2. + 3 + 2 + + + + + + + CEC + CEC + CEC + 0x40006C00 + + 0x0 + 0x400 + registers + + + CEC + HDMI-CEC global interrupt + 94 + + + + CR + CR + CEC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CECEN + CEC Enable The CECEN bit is set and + cleared by software. CECEN=1 starts message reception + and enables the TXSOM control. CECEN=0 disables the + CEC peripheral, clears all bits of CEC_CR register + and aborts any on-going reception or + transmission. + 0 + 1 + + + TXSOM + Tx Start Of Message TXSOM is set by + software to command transmission of the first byte of + a CEC message. If the CEC message consists of only + one byte, TXEOM must be set before of TXSOM. + Start-Bit is effectively started on the CEC line + after SFT is counted. If TXSOM is set while a message + reception is ongoing, transmission will start after + the end of reception. TXSOM is cleared by hardware + after the last byte of the message is sent with a + positive acknowledge (TXEND=1), in case of + transmission underrun (TXUDR=1), negative acknowledge + (TXACKE=1), and transmission error (TXERR=1). It is + also cleared by CECEN=0. It is not cleared and + transmission is automatically retried in case of + arbitration lost (ARBLST=1). TXSOM can be also used + as a status bit informing application whether any + transmission request is pending or under execution. + The application can abort a transmission request at + any time by clearing the CECEN bit. Note: TXSOM must + be set when CECEN=1 TXSOM must be set when + transmission data is available into TXDR HEADERs + first four bits containing own peripheral address are + taken from TXDR[7:4], not from CEC_CFGR.OAR which is + used only for reception + 1 + 1 + + + TXEOM + Tx End Of Message The TXEOM bit is set + by software to command transmission of the last byte + of a CEC message. TXEOM is cleared by hardware at the + same time and under the same conditions as for TXSOM. + Note: TXEOM must be set when CECEN=1 TXEOM must be + set before writing transmission data to TXDR If TXEOM + is set when TXSOM=0, transmitted message will consist + of 1 byte (HEADER) only (PING message) + 2 + 1 + + + + + CFGR + CFGR + This register is used to configure the + HDMI-CEC controller. It is mandatory to write CEC_CFGR + only when CECEN=0. + 0x4 + 0x20 + read-write + 0x00000000 + + + SFT + Signal Free Time SFT bits are set by + software. In the SFT=0x0 configuration the number of + nominal data bit periods waited before transmission + is ruled by hardware according to the transmission + history. In all the other configurations the SFT + number is determined by software. * 0x0 ** 2.5 + Data-Bit periods if CEC is the last bus initiator + with unsuccessful transmission (ARBLST=1, TXERR=1, + TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is + the new bus initiator ** 6 Data-Bit periods if CEC is + the last bus initiator with successful transmission + (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: + 1.5 nominal data bit periods * 0x3: 2.5 nominal data + bit periods * 0x4: 3.5 nominal data bit periods * + 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal + data bit periods * 0x7: 6.5 nominal data bit + periods + 0 + 3 + + + RXTOL + Rx-Tolerance The RXTOL bit is set and + cleared by software. ** Start-Bit, +/- 200 s rise, + +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 + s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall + ** Data-Bit: +/-300 s rise, +/- 500 s + fall + 3 + 1 + + + BRESTP + Rx-Stop on Bit Rising Error The BRESTP + bit is set and cleared by software. + 4 + 1 + + + BREGEN + Generate Error-Bit on Bit Rising Error + The BREGEN bit is set and cleared by software. Note: + If BRDNOGEN=0, an Error-bit is generated upon BRE + detection with BRESTP=1 in broadcast even if + BREGEN=0 + 5 + 1 + + + LBPEGEN + Generate Error-Bit on Long Bit Period + Error The LBPEGEN bit is set and cleared by software. + Note: If BRDNOGEN=0, an Error-bit is generated upon + LBPE detection in broadcast even if + LBPEGEN=0 + 6 + 1 + + + BRDNOGEN + Avoid Error-Bit Generation in Broadcast + The BRDNOGEN bit is set and cleared by + software. + 7 + 1 + + + SFTOPT + SFT Option Bit The SFTOPT bit is set and + cleared by software. + 8 + 1 + + + OAR + Own addresses configuration The OAR bits + are set by software to select which destination + logical addresses has to be considered in receive + mode. Each bit, when set, enables the CEC logical + address identified by the given bit position. At the + end of HEADER reception, the received destination + address is compared with the enabled addresses. In + case of matching address, the incoming message is + acknowledged and received. In case of non-matching + address, the incoming message is received only in + listen mode (LSTN=1), but without acknowledge sent. + Broadcast messages are always received. Example: OAR + = 0b000 0000 0010 0001 means that CEC acknowledges + addresses 0x0 and 0x5. Consequently, each message + directed to one of these addresses is + received. + 16 + 15 + + + LSTN + Listen mode LSTN bit is set and cleared + by software. + 31 + 1 + + + + + TXDR + TXDR + CEC Tx data register + 0x8 + 0x20 + write-only + 0x00000000 + + + TXD + Tx Data register. TXD is a write-only + register containing the data byte to be transmitted. + Note: TXD must be written when + TXSTART=1 + 0 + 8 + + + + + RXDR + RXDR + CEC Rx Data Register + 0xC + 0x20 + read-only + 0x00000000 + + + RXD + Rx Data register. RXD is read-only and + contains the last data byte which has been received + from the CEC line. + 0 + 8 + + + + + ISR + ISR + CEC Interrupt and Status + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RXBR + Rx-Byte Received The RXBR bit is set by + hardware to inform application that a new byte has + been received from the CEC line and stored into the + RXD buffer. RXBR is cleared by software write at + 1. + 0 + 1 + + + RXEND + End Of Reception RXEND is set by + hardware to inform application that the last byte of + a CEC message is received from the CEC line and + stored into the RXD buffer. RXEND is set at the same + time of RXBR. RXEND is cleared by software write at + 1. + 1 + 1 + + + RXOVR + Rx-Overrun RXOVR is set by hardware if + RXBR is not yet cleared at the time a new byte is + received on the CEC line and stored into RXD. RXOVR + assertion stops message reception so that no + acknowledge is sent. In case of broadcast, a negative + acknowledge is sent. RXOVR is cleared by software + write at 1. + 2 + 1 + + + BRE + Rx-Bit Rising Error BRE is set by + hardware in case a Data-Bit waveform is detected with + Bit Rising Error. BRE is set either at the time the + misplaced rising edge occurs, or at the end of the + maximum BRE tolerance allowed by RXTOL, in case + rising edge is still longing. BRE stops message + reception if BRESTP=1. BRE generates an Error-Bit on + the CEC line if BREGEN=1. BRE is cleared by software + write at 1. + 3 + 1 + + + SBPE + Rx-Short Bit Period Error SBPE is set by + hardware in case a Data-Bit waveform is detected with + Short Bit Period Error. SBPE is set at the time the + anticipated falling edge occurs. SBPE generates an + Error-Bit on the CEC line. SBPE is cleared by + software write at 1. + 4 + 1 + + + LBPE + Rx-Long Bit Period Error LBPE is set by + hardware in case a Data-Bit waveform is detected with + Long Bit Period Error. LBPE is set at the end of the + maximum bit-extension tolerance allowed by RXTOL, in + case falling edge is still longing. LBPE always stops + reception of the CEC message. LBPE generates an + Error-Bit on the CEC line if LBPEGEN=1. In case of + broadcast, Error-Bit is generated even in case of + LBPEGEN=0. LBPE is cleared by software write at + 1. + 5 + 1 + + + RXACKE + Rx-Missing Acknowledge In receive mode, + RXACKE is set by hardware to inform application that + no acknowledge was seen on the CEC line. RXACKE + applies only for broadcast messages and in listen + mode also for not directly addressed messages + (destination address not enabled in OAR). RXACKE + aborts message reception. RXACKE is cleared by + software write at 1. + 6 + 1 + + + ARBLST + Arbitration Lost ARBLST is set by + hardware to inform application that CEC device is + switching to reception due to arbitration lost event + following the TXSOM command. ARBLST can be due either + to a contending CEC device starting earlier or + starting at the same time but with higher HEADER + priority. After ARBLST assertion TXSOM bit keeps + pending for next transmission attempt. ARBLST is + cleared by software write at 1. + 7 + 1 + + + TXBR + Tx-Byte Request TXBR is set by hardware + to inform application that the next transmission data + has to be written to TXDR. TXBR is set when the 4th + bit of currently transmitted byte is sent. + Application must write the next byte to TXDR within 6 + nominal data-bit periods before transmission underrun + error occurs (TXUDR). TXBR is cleared by software + write at 1. + 8 + 1 + + + TXEND + End of Transmission TXEND is set by + hardware to inform application that the last byte of + the CEC message has been successfully transmitted. + TXEND clears the TXSOM and TXEOM control bits. TXEND + is cleared by software write at 1. + 9 + 1 + + + TXUDR + Tx-Buffer Underrun In transmission mode, + TXUDR is set by hardware if application was not in + time to load TXDR before of next byte transmission. + TXUDR aborts message transmission and clears TXSOM + and TXEOM control bits. TXUDR is cleared by software + write at 1 + 10 + 1 + + + TXERR + Tx-Error In transmission mode, TXERR is + set by hardware if the CEC initiator detects low + impedance on the CEC line while it is released. TXERR + aborts message transmission and clears TXSOM and + TXEOM controls. TXERR is cleared by software write at + 1. + 11 + 1 + + + TXACKE + Tx-Missing Acknowledge Error In + transmission mode, TXACKE is set by hardware to + inform application that no acknowledge was received. + In case of broadcast transmission, TXACKE informs + application that a negative acknowledge was received. + TXACKE aborts message transmission and clears TXSOM + and TXEOM controls. TXACKE is cleared by software + write at 1. + 12 + 1 + + + + + IER + IER + CEC interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + RXBRIE + Rx-Byte Received Interrupt Enable The + RXBRIE bit is set and cleared by + software. + 0 + 1 + + + RXENDIE + End Of Reception Interrupt Enable The + RXENDIE bit is set and cleared by + software. + 1 + 1 + + + RXOVRIE + Rx-Buffer Overrun Interrupt Enable The + RXOVRIE bit is set and cleared by + software. + 2 + 1 + + + BREIE + Bit Rising Error Interrupt Enable The + BREIE bit is set and cleared by + software. + 3 + 1 + + + SBPEIE + Short Bit Period Error Interrupt Enable + The SBPEIE bit is set and cleared by + software. + 4 + 1 + + + LBPEIE + Long Bit Period Error Interrupt Enable + The LBPEIE bit is set and cleared by + software. + 5 + 1 + + + RXACKIE + Rx-Missing Acknowledge Error Interrupt + Enable The RXACKIE bit is set and cleared by + software. + 6 + 1 + + + ARBLSTIE + Arbitration Lost Interrupt Enable The + ARBLSTIE bit is set and cleared by + software. + 7 + 1 + + + TXBRIE + Tx-Byte Request Interrupt Enable The + TXBRIE bit is set and cleared by + software. + 8 + 1 + + + TXENDIE + Tx-End Of Message Interrupt Enable The + TXENDIE bit is set and cleared by + software. + 9 + 1 + + + TXUDRIE + Tx-Underrun Interrupt Enable The TXUDRIE + bit is set and cleared by software. + 10 + 1 + + + TXERRIE + Tx-Error Interrupt Enable The TXERRIE + bit is set and cleared by software. + 11 + 1 + + + TXACKIE + Tx-Missing Acknowledge Error Interrupt + Enable The TXACKEIE bit is set and cleared by + software. + 12 + 1 + + + + + + + HSEM + HSEM + HSEM + 0x58026400 + + 0x0 + 0x400 + registers + + + HSEM0 + HSEM global interrupt 1 + 125 + + + + HSEM_R0 + HSEM_R0 + HSEM register HSEM_R0 HSEM_R31 + 0x0 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R1 + HSEM_R1 + HSEM register HSEM_R0 HSEM_R31 + 0x4 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R2 + HSEM_R2 + HSEM register HSEM_R0 HSEM_R31 + 0x8 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R3 + HSEM_R3 + HSEM register HSEM_R0 HSEM_R31 + 0xC + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R4 + HSEM_R4 + HSEM register HSEM_R0 HSEM_R31 + 0x10 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R5 + HSEM_R5 + HSEM register HSEM_R0 HSEM_R31 + 0x14 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R6 + HSEM_R6 + HSEM register HSEM_R0 HSEM_R31 + 0x18 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R7 + HSEM_R7 + HSEM register HSEM_R0 HSEM_R31 + 0x1C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R8 + HSEM_R8 + HSEM register HSEM_R0 HSEM_R31 + 0x20 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R9 + HSEM_R9 + HSEM register HSEM_R0 HSEM_R31 + 0x24 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R10 + HSEM_R10 + HSEM register HSEM_R0 HSEM_R31 + 0x28 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R11 + HSEM_R11 + HSEM register HSEM_R0 HSEM_R31 + 0x2C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R12 + HSEM_R12 + HSEM register HSEM_R0 HSEM_R31 + 0x30 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R13 + HSEM_R13 + HSEM register HSEM_R0 HSEM_R31 + 0x34 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R14 + HSEM_R14 + HSEM register HSEM_R0 HSEM_R31 + 0x38 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R15 + HSEM_R15 + HSEM register HSEM_R0 HSEM_R31 + 0x3C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R16 + HSEM_R16 + HSEM register HSEM_R0 HSEM_R31 + 0x40 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R17 + HSEM_R17 + HSEM register HSEM_R0 HSEM_R31 + 0x44 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R18 + HSEM_R18 + HSEM register HSEM_R0 HSEM_R31 + 0x48 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R19 + HSEM_R19 + HSEM register HSEM_R0 HSEM_R31 + 0x4C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R20 + HSEM_R20 + HSEM register HSEM_R0 HSEM_R31 + 0x50 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R21 + HSEM_R21 + HSEM register HSEM_R0 HSEM_R31 + 0x54 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R22 + HSEM_R22 + HSEM register HSEM_R0 HSEM_R31 + 0x58 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R23 + HSEM_R23 + HSEM register HSEM_R0 HSEM_R31 + 0x5C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R24 + HSEM_R24 + HSEM register HSEM_R0 HSEM_R31 + 0x60 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R25 + HSEM_R25 + HSEM register HSEM_R0 HSEM_R31 + 0x64 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R26 + HSEM_R26 + HSEM register HSEM_R0 HSEM_R31 + 0x68 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R27 + HSEM_R27 + HSEM register HSEM_R0 HSEM_R31 + 0x6C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R28 + HSEM_R28 + HSEM register HSEM_R0 HSEM_R31 + 0x70 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R29 + HSEM_R29 + HSEM register HSEM_R0 HSEM_R31 + 0x74 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R30 + HSEM_R30 + HSEM register HSEM_R0 HSEM_R31 + 0x78 + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_R31 + HSEM_R31 + HSEM register HSEM_R0 HSEM_R31 + 0x7C + 0x20 + read-write + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR0 + HSEM_RLR0 + HSEM Read lock register + 0x80 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR1 + HSEM_RLR1 + HSEM Read lock register + 0x84 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR2 + HSEM_RLR2 + HSEM Read lock register + 0x88 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR3 + HSEM_RLR3 + HSEM Read lock register + 0x8C + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR4 + HSEM_RLR4 + HSEM Read lock register + 0x90 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR5 + HSEM_RLR5 + HSEM Read lock register + 0x94 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR6 + HSEM_RLR6 + HSEM Read lock register + 0x98 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR7 + HSEM_RLR7 + HSEM Read lock register + 0x9C + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR8 + HSEM_RLR8 + HSEM Read lock register + 0xA0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR9 + HSEM_RLR9 + HSEM Read lock register + 0xA4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR10 + HSEM_RLR10 + HSEM Read lock register + 0xA8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR11 + HSEM_RLR11 + HSEM Read lock register + 0xAC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR12 + HSEM_RLR12 + HSEM Read lock register + 0xB0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR13 + HSEM_RLR13 + HSEM Read lock register + 0xB4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR14 + HSEM_RLR14 + HSEM Read lock register + 0xB8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR15 + HSEM_RLR15 + HSEM Read lock register + 0xBC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR16 + HSEM_RLR16 + HSEM Read lock register + 0xC0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR17 + HSEM_RLR17 + HSEM Read lock register + 0xC4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR18 + HSEM_RLR18 + HSEM Read lock register + 0xC8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR19 + HSEM_RLR19 + HSEM Read lock register + 0xCC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR20 + HSEM_RLR20 + HSEM Read lock register + 0xD0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR21 + HSEM_RLR21 + HSEM Read lock register + 0xD4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR22 + HSEM_RLR22 + HSEM Read lock register + 0xD8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR23 + HSEM_RLR23 + HSEM Read lock register + 0xDC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR24 + HSEM_RLR24 + HSEM Read lock register + 0xE0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR25 + HSEM_RLR25 + HSEM Read lock register + 0xE4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR26 + HSEM_RLR26 + HSEM Read lock register + 0xE8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR27 + HSEM_RLR27 + HSEM Read lock register + 0xEC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR28 + HSEM_RLR28 + HSEM Read lock register + 0xF0 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR29 + HSEM_RLR29 + HSEM Read lock register + 0xF4 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR30 + HSEM_RLR30 + HSEM Read lock register + 0xF8 + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLR31 + HSEM_RLR31 + HSEM Read lock register + 0xFC + 0x20 + read-only + 0x00000000 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + MASTERID + Semaphore MasterID + 8 + 8 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_IER + HSEM_IER + HSEM Interrupt enable register + 0x100 + 0x20 + read-write + 0x00000000 + + + ISEM0 + Interrupt semaphore n enable + bit + 0 + 1 + + + ISEM1 + Interrupt semaphore n enable + bit + 1 + 1 + + + ISEM2 + Interrupt semaphore n enable + bit + 2 + 1 + + + ISEM3 + Interrupt semaphore n enable + bit + 3 + 1 + + + ISEM4 + Interrupt semaphore n enable + bit + 4 + 1 + + + ISEM5 + Interrupt semaphore n enable + bit + 5 + 1 + + + ISEM6 + Interrupt semaphore n enable + bit + 6 + 1 + + + ISEM7 + Interrupt semaphore n enable + bit + 7 + 1 + + + ISEM8 + Interrupt semaphore n enable + bit + 8 + 1 + + + ISEM9 + Interrupt semaphore n enable + bit + 9 + 1 + + + ISEM10 + Interrupt semaphore n enable + bit + 10 + 1 + + + ISEM11 + Interrupt semaphore n enable + bit + 11 + 1 + + + ISEM12 + Interrupt semaphore n enable + bit + 12 + 1 + + + ISEM13 + Interrupt semaphore n enable + bit + 13 + 1 + + + ISEM14 + Interrupt semaphore n enable + bit + 14 + 1 + + + ISEM15 + Interrupt semaphore n enable + bit + 15 + 1 + + + ISEM16 + Interrupt semaphore n enable + bit + 16 + 1 + + + ISEM17 + Interrupt semaphore n enable + bit + 17 + 1 + + + ISEM18 + Interrupt semaphore n enable + bit + 18 + 1 + + + ISEM19 + Interrupt semaphore n enable + bit + 19 + 1 + + + ISEM20 + Interrupt semaphore n enable + bit + 20 + 1 + + + ISEM21 + Interrupt semaphore n enable + bit + 21 + 1 + + + ISEM22 + Interrupt semaphore n enable + bit + 22 + 1 + + + ISEM23 + Interrupt semaphore n enable + bit + 23 + 1 + + + ISEM24 + Interrupt semaphore n enable + bit + 24 + 1 + + + ISEM25 + Interrupt semaphore n enable + bit + 25 + 1 + + + ISEM26 + Interrupt semaphore n enable + bit + 26 + 1 + + + ISEM27 + Interrupt semaphore n enable + bit + 27 + 1 + + + ISEM28 + Interrupt semaphore n enable + bit + 28 + 1 + + + ISEM29 + Interrupt semaphore n enable + bit + 29 + 1 + + + ISEM30 + Interrupt semaphore n enable + bit + 30 + 1 + + + ISEM31 + Interrupt(N) semaphore n enable + bit. + 31 + 1 + + + + + HSEM_ICR + HSEM_ICR + HSEM Interrupt clear register + 0x104 + 0x20 + read-only + 0x00000000 + + + ISEM0 + Interrupt(N) semaphore n clear + bit + 0 + 1 + + + ISEM1 + Interrupt(N) semaphore n clear + bit + 1 + 1 + + + ISEM2 + Interrupt(N) semaphore n clear + bit + 2 + 1 + + + ISEM3 + Interrupt(N) semaphore n clear + bit + 3 + 1 + + + ISEM4 + Interrupt(N) semaphore n clear + bit + 4 + 1 + + + ISEM5 + Interrupt(N) semaphore n clear + bit + 5 + 1 + + + ISEM6 + Interrupt(N) semaphore n clear + bit + 6 + 1 + + + ISEM7 + Interrupt(N) semaphore n clear + bit + 7 + 1 + + + ISEM8 + Interrupt(N) semaphore n clear + bit + 8 + 1 + + + ISEM9 + Interrupt(N) semaphore n clear + bit + 9 + 1 + + + ISEM10 + Interrupt(N) semaphore n clear + bit + 10 + 1 + + + ISEM11 + Interrupt(N) semaphore n clear + bit + 11 + 1 + + + ISEM12 + Interrupt(N) semaphore n clear + bit + 12 + 1 + + + ISEM13 + Interrupt(N) semaphore n clear + bit + 13 + 1 + + + ISEM14 + Interrupt(N) semaphore n clear + bit + 14 + 1 + + + ISEM15 + Interrupt(N) semaphore n clear + bit + 15 + 1 + + + ISEM16 + Interrupt(N) semaphore n clear + bit + 16 + 1 + + + ISEM17 + Interrupt(N) semaphore n clear + bit + 17 + 1 + + + ISEM18 + Interrupt(N) semaphore n clear + bit + 18 + 1 + + + ISEM19 + Interrupt(N) semaphore n clear + bit + 19 + 1 + + + ISEM20 + Interrupt(N) semaphore n clear + bit + 20 + 1 + + + ISEM21 + Interrupt(N) semaphore n clear + bit + 21 + 1 + + + ISEM22 + Interrupt(N) semaphore n clear + bit + 22 + 1 + + + ISEM23 + Interrupt(N) semaphore n clear + bit + 23 + 1 + + + ISEM24 + Interrupt(N) semaphore n clear + bit + 24 + 1 + + + ISEM25 + Interrupt(N) semaphore n clear + bit + 25 + 1 + + + ISEM26 + Interrupt(N) semaphore n clear + bit + 26 + 1 + + + ISEM27 + Interrupt(N) semaphore n clear + bit + 27 + 1 + + + ISEM28 + Interrupt(N) semaphore n clear + bit + 28 + 1 + + + ISEM29 + Interrupt(N) semaphore n clear + bit + 29 + 1 + + + ISEM30 + Interrupt(N) semaphore n clear + bit + 30 + 1 + + + ISEM31 + Interrupt(N) semaphore n clear + bit + 31 + 1 + + + + + HSEM_ISR + HSEM_ISR + HSEM Interrupt status register + 0x108 + 0x20 + read-only + 0x00000000 + + + ISEM0 + Interrupt(N) semaphore n status bit + before enable (mask) + 0 + 1 + + + ISEM1 + Interrupt(N) semaphore n status bit + before enable (mask) + 1 + 1 + + + ISEM2 + Interrupt(N) semaphore n status bit + before enable (mask) + 2 + 1 + + + ISEM3 + Interrupt(N) semaphore n status bit + before enable (mask) + 3 + 1 + + + ISEM4 + Interrupt(N) semaphore n status bit + before enable (mask) + 4 + 1 + + + ISEM5 + Interrupt(N) semaphore n status bit + before enable (mask) + 5 + 1 + + + ISEM6 + Interrupt(N) semaphore n status bit + before enable (mask) + 6 + 1 + + + ISEM7 + Interrupt(N) semaphore n status bit + before enable (mask) + 7 + 1 + + + ISEM8 + Interrupt(N) semaphore n status bit + before enable (mask) + 8 + 1 + + + ISEM9 + Interrupt(N) semaphore n status bit + before enable (mask) + 9 + 1 + + + ISEM10 + Interrupt(N) semaphore n status bit + before enable (mask) + 10 + 1 + + + ISEM11 + Interrupt(N) semaphore n status bit + before enable (mask) + 11 + 1 + + + ISEM12 + Interrupt(N) semaphore n status bit + before enable (mask) + 12 + 1 + + + ISEM13 + Interrupt(N) semaphore n status bit + before enable (mask) + 13 + 1 + + + ISEM14 + Interrupt(N) semaphore n status bit + before enable (mask) + 14 + 1 + + + ISEM15 + Interrupt(N) semaphore n status bit + before enable (mask) + 15 + 1 + + + ISEM16 + Interrupt(N) semaphore n status bit + before enable (mask) + 16 + 1 + + + ISEM17 + Interrupt(N) semaphore n status bit + before enable (mask) + 17 + 1 + + + ISEM18 + Interrupt(N) semaphore n status bit + before enable (mask) + 18 + 1 + + + ISEM19 + Interrupt(N) semaphore n status bit + before enable (mask) + 19 + 1 + + + ISEM20 + Interrupt(N) semaphore n status bit + before enable (mask) + 20 + 1 + + + ISEM21 + Interrupt(N) semaphore n status bit + before enable (mask) + 21 + 1 + + + ISEM22 + Interrupt(N) semaphore n status bit + before enable (mask) + 22 + 1 + + + ISEM23 + Interrupt(N) semaphore n status bit + before enable (mask) + 23 + 1 + + + ISEM24 + Interrupt(N) semaphore n status bit + before enable (mask) + 24 + 1 + + + ISEM25 + Interrupt(N) semaphore n status bit + before enable (mask) + 25 + 1 + + + ISEM26 + Interrupt(N) semaphore n status bit + before enable (mask) + 26 + 1 + + + ISEM27 + Interrupt(N) semaphore n status bit + before enable (mask) + 27 + 1 + + + ISEM28 + Interrupt(N) semaphore n status bit + before enable (mask) + 28 + 1 + + + ISEM29 + Interrupt(N) semaphore n status bit + before enable (mask) + 29 + 1 + + + ISEM30 + Interrupt(N) semaphore n status bit + before enable (mask) + 30 + 1 + + + ISEM31 + Interrupt(N) semaphore n status bit + before enable (mask) + 31 + 1 + + + + + HSEM_MISR + HSEM_MISR + HSEM Masked interrupt status + register + 0x10C + 0x20 + read-only + 0x00000000 + + + ISEM0 + masked interrupt(N) semaphore n status + bit after enable (mask) + 0 + 1 + + + ISEM1 + masked interrupt(N) semaphore n status + bit after enable (mask) + 1 + 1 + + + ISEM2 + masked interrupt(N) semaphore n status + bit after enable (mask) + 2 + 1 + + + ISEM3 + masked interrupt(N) semaphore n status + bit after enable (mask) + 3 + 1 + + + ISEM4 + masked interrupt(N) semaphore n status + bit after enable (mask) + 4 + 1 + + + ISEM5 + masked interrupt(N) semaphore n status + bit after enable (mask) + 5 + 1 + + + ISEM6 + masked interrupt(N) semaphore n status + bit after enable (mask) + 6 + 1 + + + ISEM7 + masked interrupt(N) semaphore n status + bit after enable (mask) + 7 + 1 + + + ISEM8 + masked interrupt(N) semaphore n status + bit after enable (mask) + 8 + 1 + + + ISEM9 + masked interrupt(N) semaphore n status + bit after enable (mask) + 9 + 1 + + + ISEM10 + masked interrupt(N) semaphore n status + bit after enable (mask) + 10 + 1 + + + ISEM11 + masked interrupt(N) semaphore n status + bit after enable (mask) + 11 + 1 + + + ISEM12 + masked interrupt(N) semaphore n status + bit after enable (mask) + 12 + 1 + + + ISEM13 + masked interrupt(N) semaphore n status + bit after enable (mask) + 13 + 1 + + + ISEM14 + masked interrupt(N) semaphore n status + bit after enable (mask) + 14 + 1 + + + ISEM15 + masked interrupt(N) semaphore n status + bit after enable (mask) + 15 + 1 + + + ISEM16 + masked interrupt(N) semaphore n status + bit after enable (mask) + 16 + 1 + + + ISEM17 + masked interrupt(N) semaphore n status + bit after enable (mask) + 17 + 1 + + + ISEM18 + masked interrupt(N) semaphore n status + bit after enable (mask) + 18 + 1 + + + ISEM19 + masked interrupt(N) semaphore n status + bit after enable (mask) + 19 + 1 + + + ISEM20 + masked interrupt(N) semaphore n status + bit after enable (mask) + 20 + 1 + + + ISEM21 + masked interrupt(N) semaphore n status + bit after enable (mask) + 21 + 1 + + + ISEM22 + masked interrupt(N) semaphore n status + bit after enable (mask) + 22 + 1 + + + ISEM23 + masked interrupt(N) semaphore n status + bit after enable (mask) + 23 + 1 + + + ISEM24 + masked interrupt(N) semaphore n status + bit after enable (mask) + 24 + 1 + + + ISEM25 + masked interrupt(N) semaphore n status + bit after enable (mask) + 25 + 1 + + + ISEM26 + masked interrupt(N) semaphore n status + bit after enable (mask) + 26 + 1 + + + ISEM27 + masked interrupt(N) semaphore n status + bit after enable (mask) + 27 + 1 + + + ISEM28 + masked interrupt(N) semaphore n status + bit after enable (mask) + 28 + 1 + + + ISEM29 + masked interrupt(N) semaphore n status + bit after enable (mask) + 29 + 1 + + + ISEM30 + masked interrupt(N) semaphore n status + bit after enable (mask) + 30 + 1 + + + ISEM31 + masked interrupt(N) semaphore n status + bit after enable (mask) + 31 + 1 + + + + + HSEM_CR + HSEM_CR + HSEM Clear register + 0x140 + 0x20 + read-write + 0x00000000 + + + MASTERID + MasterID of semaphores to be + cleared + 8 + 8 + + + KEY + Semaphore clear Key + 16 + 16 + + + + + HSEM_KEYR + HSEM_KEYR + HSEM Interrupt clear register + 0x144 + 0x20 + read-write + 0x00000000 + + + KEY + Semaphore Clear Key + 16 + 16 + + + + + + + I2C1 + I2C + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + + CR1 + CR1 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable Note: When PE=0, the + I2C SCL and SDA lines are released. Internal state + machines and status bits are put back to their reset + value. When cleared, PE must be kept low for at least + 3 APB clock cycles. + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match Interrupt enable (slave + only) + 3 + 1 + + + NACKIE + Not acknowledge received Interrupt + enable + 4 + 1 + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + + + TCIE + Transfer Complete interrupt enable Note: + Any of these events will generate an interrupt: + Transfer Complete (TC) Transfer Complete Reload + (TCR) + 6 + 1 + + + ERRIE + Error interrupts enable Note: Any of + these errors generate an interrupt: Arbitration Loss + (ARLO) Bus Error detection (BERR) Overrun/Underrun + (OVR) Timeout detection (TIMEOUT) PEC error detection + (PECERR) Alert pin event detection + (ALERT) + 7 + 1 + + + DNF + Digital noise filter These bits are used + to configure the digital noise filter on SDA and SCL + input. The digital filter will filter spikes with a + length of up to DNF[3:0] * tI2CCLK ... Note: If the + analog filter is also enabled, the digital filter is + added to the analog filter. This filter can only be + programmed when the I2C is disabled (PE = + 0). + 8 + 4 + + + ANFOFF + Analog noise filter OFF Note: This bit + can only be programmed when the I2C is disabled (PE = + 0). + 12 + 1 + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + + + SBC + Slave byte control This bit is used to + enable hardware byte control in slave + mode. + 16 + 1 + + + NOSTRETCH + Clock stretching disable This bit is + used to disable clock stretching in slave mode. It + must be kept cleared in master mode. Note: This bit + can only be programmed when the I2C is disabled (PE = + 0). + 17 + 1 + + + WUPEN + Wakeup from Stop mode enable Note: If + the Wakeup from Stop mode feature is not supported, + this bit is reserved and forced by hardware to 0. + Please refer to Section25.3: I2C implementation. + Note: WUPEN can be set only when DNF = + 0000 + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable Note: If the + SMBus feature is not supported, this bit is reserved + and forced by hardware to 0. Please refer to + Section25.3: I2C implementation. + 20 + 1 + + + SMBDEN + SMBus Device Default address enable + Note: If the SMBus feature is not supported, this bit + is reserved and forced by hardware to 0. Please refer + to Section25.3: I2C implementation. + 21 + 1 + + + ALERTEN + SMBus alert enable Device mode + (SMBHEN=0): Host mode (SMBHEN=1): Note: When + ALERTEN=0, the SMBA pin can be used as a standard + GPIO. If the SMBus feature is not supported, this bit + is reserved and forced by hardware to 0. Please refer + to Section25.3: I2C implementation. + 22 + 1 + + + PECEN + PEC enable Note: If the SMBus feature is + not supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 23 + 1 + + + + + CR2 + CR2 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x4 + 0x20 + read-write + 0x00000000 + + + SADD0 + Slave address bit 0 (master mode) In + 7-bit addressing mode (ADD10 = 0): This bit is dont + care In 10-bit addressing mode (ADD10 = 1): This bit + should be written with bit 0 of the slave address to + be sent Note: Changing these bits when the START bit + is set is not allowed. + 0 + 1 + + + SADD1 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 1 + 1 + + + SADD2 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 2 + 1 + + + SADD3 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 3 + 1 + + + SADD4 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 4 + 1 + + + SADD5 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 5 + 1 + + + SADD6 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 6 + 1 + + + SADD7 + Slave address bit 7:1 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits should + be written with the 7-bit slave address to be sent In + 10-bit addressing mode (ADD10 = 1): These bits should + be written with bits 7:1 of the slave address to be + sent. Note: Changing these bits when the START bit is + set is not allowed. + 7 + 1 + + + SADD8 + Slave address bit 9:8 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits are + dont care In 10-bit addressing mode (ADD10 = 1): + These bits should be written with bits 9:8 of the + slave address to be sent Note: Changing these bits + when the START bit is set is not + allowed. + 8 + 1 + + + SADD9 + Slave address bit 9:8 (master mode) In + 7-bit addressing mode (ADD10 = 0): These bits are + dont care In 10-bit addressing mode (ADD10 = 1): + These bits should be written with bits 9:8 of the + slave address to be sent Note: Changing these bits + when the START bit is set is not + allowed. + 9 + 1 + + + RD_WRN + Transfer direction (master mode) Note: + Changing this bit when the START bit is set is not + allowed. + 10 + 1 + + + ADD10 + 10-bit addressing mode (master mode) + Note: Changing this bit when the START bit is set is + not allowed. + 11 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) Note: Changing this + bit when the START bit is set is not + allowed. + 12 + 1 + + + START + Start generation This bit is set by + software, and cleared by hardware after the Start + followed by the address sequence is sent, by an + arbitration loss, by a timeout error detection, or + when PE = 0. It can also be cleared by software by + writing 1 to the ADDRCF bit in the I2C_ICR register. + If the I2C is already in master mode with AUTOEND = + 0, setting this bit generates a Repeated Start + condition when RELOAD=0, after the end of the NBYTES + transfer. Otherwise setting this bit will generate a + START condition once the bus is free. Note: Writing 0 + to this bit has no effect. The START bit can be set + even if the bus is BUSY or I2C is in slave mode. This + bit has no effect when RELOAD is set. + 13 + 1 + + + STOP + Stop generation (master mode) The bit is + set by software, cleared by hardware when a Stop + condition is detected, or when PE = 0. In Master + Mode: Note: Writing 0 to this bit has no + effect. + 14 + 1 + + + NACK + NACK generation (slave mode) The bit is + set by software, cleared by hardware when the NACK is + sent, or when a STOP condition or an Address matched + is received, or when PE=0. Note: Writing 0 to this + bit has no effect. This bit is used in slave mode + only: in master receiver mode, NACK is automatically + generated after last byte preceding STOP or RESTART + condition, whatever the NACK bit value. When an + overrun occurs in slave receiver NOSTRETCH mode, a + NACK is automatically generated whatever the NACK bit + value. When hardware PEC checking is enabled + (PECBYTE=1), the PEC acknowledge value does not + depend on the NACK value. + 15 + 1 + + + NBYTES + Number of bytes The number of bytes to + be transmitted/received is programmed there. This + field is dont care in slave mode with SBC=0. Note: + Changing these bits when the START bit is set is not + allowed. + 16 + 8 + + + RELOAD + NBYTES reload mode This bit is set and + cleared by software. + 24 + 1 + + + AUTOEND + Automatic end mode (master mode) This + bit is set and cleared by software. Note: This bit + has no effect in slave mode or when the RELOAD bit is + set. + 25 + 1 + + + PECBYTE + Packet error checking byte This bit is + set by software, and cleared by hardware when the PEC + is transferred, or when a STOP condition or an + Address matched is received, also when PE=0. Note: + Writing 0 to this bit has no effect. This bit has no + effect when RELOAD is set. This bit has no effect is + slave mode when SBC=0. If the SMBus feature is not + supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 26 + 1 + + + + + OAR1 + OAR1 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address 7-bit addressing mode: + dont care 10-bit addressing mode: bits 9:8 of address + Note: These bits can be written only when OA1EN=0. + OA1[7:1]: Interface address Bits 7:1 of address Note: + These bits can be written only when OA1EN=0. OA1[0]: + Interface address 7-bit addressing mode: dont care + 10-bit addressing mode: bit 0 of address Note: This + bit can be written only when OA1EN=0. + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode Note: This bit + can be written only when OA1EN=0. + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address bits 7:1 of address + Note: These bits can be written only when + OA2EN=0. + 1 + 7 + + + OA2MSK + Own Address 2 masks Note: These bits can + be written only when OA2EN=0. As soon as OA2MSK is + not equal to 0, the reserved I2C addresses (0b0000xxx + and 0b1111xxx) are not acknowledged even if the + comparison matches. + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Access: No wait states + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) This field + is used to generate the SCL low period in master + mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also + used to generate tBUF and tSU:STA + timings. + 0 + 8 + + + SCLH + SCL high period (master mode) This field + is used to generate the SCL high period in master + mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also + used to generate tSU:STO and tHD:STA + timing. + 8 + 8 + + + SDADEL + Data hold time This field is used to + generate the delay tSDADEL between SCL falling edge + and SDA edge. In master mode and in slave mode with + NOSTRETCH = 0, the SCL line is stretched low during + tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is + used to generate tHD:DAT timing. + 16 + 4 + + + SCLDEL + Data setup time This field is used to + generate a delay tSCLDEL between SDA edge and SCL + rising edge. In master mode and in slave mode with + NOSTRETCH = 0, the SCL line is stretched low during + tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL + is used to generate tSU:DAT timing. + 20 + 4 + + + PRESC + Timing prescaler This field is used to + prescale I2CCLK in order to generate the clock period + tPRESC used for data setup and hold counters (refer + to I2C timings on page9) and for SCL high and low + level counters (refer to I2C master initialization on + page24). tPRESC = (PRESC+1) x tI2CCLK + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Access: No wait states, except if a write + access occurs while a write access to this register is + ongoing. In this case, wait states are inserted in the + second write access until the previous one is completed. + The latency of the second write access can be up to 2 x + PCLK1 + 6 x I2CCLK. + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus Timeout A This field is used to + configure: The SCL low timeout condition tTIMEOUT + when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK + The bus idle condition (both SCL and SDA high) when + TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These + bits can be written only when + TIMOUTEN=0. + 0 + 12 + + + TIDLE + Idle clock timeout detection Note: This + bit can be written only when + TIMOUTEN=0. + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B This field is used to + configure the cumulative clock extension timeout: In + master mode, the master cumulative clock low extend + time (tLOW:MEXT) is detected In slave mode, the slave + cumulative clock low extend time (tLOW:SEXT) is + detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK + Note: These bits can be written only when + TEXTEN=0. + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Access: No wait states + 0x18 + 0x20 + 0x00000001 + + + TXE + Transmit data register empty + (transmitters) This bit is set by hardware when the + I2C_TXDR register is empty. It is cleared when the + next data to be sent is written in the I2C_TXDR + register. This bit can be written to 1 by software in + order to flush the transmit data register I2C_TXDR. + Note: This bit is set by hardware when + PE=0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) + This bit is set by hardware when the I2C_TXDR + register is empty and the data to be transmitted must + be written in the I2C_TXDR register. It is cleared + when the next data to be sent is written in the + I2C_TXDR register. This bit can be written to 1 by + software when NOSTRETCH=1 only, in order to generate + a TXIS event (interrupt if TXIE=1 or DMA request if + TXDMAEN=1). Note: This bit is cleared by hardware + when PE=0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty + (receivers) This bit is set by hardware when the + received data is copied into the I2C_RXDR register, + and is ready to be read. It is cleared when I2C_RXDR + is read. Note: This bit is cleared by hardware when + PE=0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) This bit is + set by hardware as soon as the received slave address + matched with one of the enabled slave addresses. It + is cleared by software by setting ADDRCF bit. Note: + This bit is cleared by hardware when + PE=0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag This flag + is set by hardware when a NACK is received after a + byte transmission. It is cleared by software by + setting the NACKCF bit. Note: This bit is cleared by + hardware when PE=0. + 4 + 1 + read-only + + + STOPF + Stop detection flag This flag is set by + hardware when a Stop condition is detected on the bus + and the peripheral is involved in this transfer: + either as a master, provided that the STOP condition + is generated by the peripheral. or as a slave, + provided that the peripheral has been addressed + previously during this transfer. It is cleared by + software by setting the STOPCF bit. Note: This bit is + cleared by hardware when PE=0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) This + flag is set by hardware when RELOAD=0, AUTOEND=0 and + NBYTES data have been transferred. It is cleared by + software when START bit or STOP bit is set. Note: + This bit is cleared by hardware when + PE=0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload This flag is + set by hardware when RELOAD=1 and NBYTES data have + been transferred. It is cleared by software when + NBYTES is written to a non-zero value. Note: This bit + is cleared by hardware when PE=0. This flag is only + for master mode, or for slave mode when the SBC bit + is set. + 7 + 1 + read-only + + + BERR + Bus error This flag is set by hardware + when a misplaced Start or Stop condition is detected + whereas the peripheral is involved in the transfer. + The flag is not set during the address phase in slave + mode. It is cleared by software by setting BERRCF + bit. Note: This bit is cleared by hardware when + PE=0. + 8 + 1 + read-only + + + ARLO + Arbitration lost This flag is set by + hardware in case of arbitration loss. It is cleared + by software by setting the ARLOCF bit. Note: This bit + is cleared by hardware when PE=0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) This flag + is set by hardware in slave mode with NOSTRETCH=1, + when an overrun/underrun error occurs. It is cleared + by software by setting the OVRCF bit. Note: This bit + is cleared by hardware when PE=0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception This flag is set + by hardware when the received PEC does not match with + the PEC register content. A NACK is automatically + sent after the wrong PEC reception. It is cleared by + software by setting the PECCF bit. Note: This bit is + cleared by hardware when PE=0. If the SMBus feature + is not supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or tLOW detection flag This flag + is set by hardware when a timeout or extended clock + timeout occurred. It is cleared by software by + setting the TIMEOUTCF bit. Note: This bit is cleared + by hardware when PE=0. If the SMBus feature is not + supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert This flag is set by hardware + when SMBHEN=1 (SMBus host configuration), ALERTEN=1 + and a SMBALERT event (falling edge) is detected on + SMBA pin. It is cleared by software by setting the + ALERTCF bit. Note: This bit is cleared by hardware + when PE=0. If the SMBus feature is not supported, + this bit is reserved and forced by hardware to 0. + Please refer to Section25.3: I2C + implementation. + 13 + 1 + read-only + + + BUSY + Bus busy This flag indicates that a + communication is in progress on the bus. It is set by + hardware when a START condition is detected. It is + cleared by hardware when a Stop condition is + detected, or when PE=0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) This + flag is updated when an address match event occurs + (ADDR=1). + 16 + 1 + read-only + + + ADDCODE + Address match code (Slave mode) These + bits are updated with the received address when an + address match event occurs (ADDR = 1). In the case of + a 10-bit address, ADDCODE provides the 10-bit header + followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + ICR + ICR + Access: No wait states + 0x1C + 0x20 + write-only + 0x00000000 + + + ADDRCF + Address matched flag clear Writing 1 to + this bit clears the ADDR flag in the I2C_ISR + register. Writing 1 to this bit also clears the START + bit in the I2C_CR2 register. + 3 + 1 + + + NACKCF + Not Acknowledge flag clear Writing 1 to + this bit clears the ACKF flag in I2C_ISR + register. + 4 + 1 + + + STOPCF + Stop detection flag clear Writing 1 to + this bit clears the STOPF flag in the I2C_ISR + register. + 5 + 1 + + + BERRCF + Bus error flag clear Writing 1 to this + bit clears the BERRF flag in the I2C_ISR + register. + 8 + 1 + + + ARLOCF + Arbitration Lost flag clear Writing 1 to + this bit clears the ARLO flag in the I2C_ISR + register. + 9 + 1 + + + OVRCF + Overrun/Underrun flag clear Writing 1 to + this bit clears the OVR flag in the I2C_ISR + register. + 10 + 1 + + + PECCF + PEC Error flag clear Writing 1 to this + bit clears the PECERR flag in the I2C_ISR register. + Note: If the SMBus feature is not supported, this bit + is reserved and forced by hardware to 0. Please refer + to Section25.3: I2C implementation. + 11 + 1 + + + TIMOUTCF + Timeout detection flag clear Writing 1 + to this bit clears the TIMEOUT flag in the I2C_ISR + register. Note: If the SMBus feature is not + supported, this bit is reserved and forced by + hardware to 0. Please refer to Section25.3: I2C + implementation. + 12 + 1 + + + ALERTCF + Alert flag clear Writing 1 to this bit + clears the ALERT flag in the I2C_ISR register. Note: + If the SMBus feature is not supported, this bit is + reserved and forced by hardware to 0. Please refer to + Section25.3: I2C implementation. + 13 + 1 + + + + + PECR + PECR + Access: No wait states + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register This + field contains the internal PEC when PECEN=1. The PEC + is cleared by hardware when PE=0. + 0 + 8 + + + + + RXDR + RXDR + Access: No wait states + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data Data byte received + from the I2C bus. + 0 + 8 + + + + + TXDR + TXDR + Access: No wait states + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data Data byte to be + transmitted to the I2C bus. Note: These bits can be + written only when TXE=1. + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + + I2C4 + 0x58001C00 + + I2C4_EV + I2C4 event interrupt + 95 + + + I2C4_ER + I2C4 error interrupt + 96 + + + + GPIOA + GPIO + GPIO + 0x58020000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xABFFFFFF + + + MODE0 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 0 + 2 + + + MODE1 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 2 + 2 + + + MODE2 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 4 + 2 + + + MODE3 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 6 + 2 + + + MODE4 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 8 + 2 + + + MODE5 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 10 + 2 + + + MODE6 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 12 + 2 + + + MODE7 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 14 + 2 + + + MODE8 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 16 + 2 + + + MODE9 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 18 + 2 + + + MODE10 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 20 + 2 + + + MODE11 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 22 + 2 + + + MODE12 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 24 + 2 + + + MODE13 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 26 + 2 + + + MODE14 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 28 + 2 + + + MODE15 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O mode. + 30 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 0 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 1 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 2 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 3 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 4 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 5 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 6 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 7 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 8 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 9 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 10 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 11 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 12 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 13 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 14 + 1 + + + OT15 + Port x configuration bits (y = 0..15) + These bits are written by software to configure the + I/O output type. + 15 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEED0 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 0 + 2 + + + OSPEED1 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 2 + 2 + + + OSPEED2 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 4 + 2 + + + OSPEED3 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 6 + 2 + + + OSPEED4 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 8 + 2 + + + OSPEED5 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 10 + 2 + + + OSPEED6 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 12 + 2 + + + OSPEED7 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 14 + 2 + + + OSPEED8 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 16 + 2 + + + OSPEED9 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 18 + 2 + + + OSPEED10 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 20 + 2 + + + OSPEED11 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 22 + 2 + + + OSPEED12 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 24 + 2 + + + OSPEED13 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 26 + 2 + + + OSPEED14 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 28 + 2 + + + OSPEED15 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O output speed. Note: Refer to the + device datasheet for the frequency specifications and + the power supply and load conditions for each + speed. + 30 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x12100000 + + + PUPD0 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 0 + 2 + + + PUPD1 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 2 + 2 + + + PUPD2 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 4 + 2 + + + PUPD3 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 6 + 2 + + + PUPD4 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 8 + 2 + + + PUPD5 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 10 + 2 + + + PUPD6 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 12 + 2 + + + PUPD7 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 14 + 2 + + + PUPD8 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 16 + 2 + + + PUPD9 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 18 + 2 + + + PUPD10 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 20 + 2 + + + PUPD11 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 22 + 2 + + + PUPD12 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 24 + 2 + + + PUPD13 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 26 + 2 + + + PUPD14 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 28 + 2 + + + PUPD15 + [1:0]: Port x configuration bits (y = + 0..15) These bits are written by software to + configure the I/O pull-up or pull-down + 30 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 0 + 1 + + + ID1 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 1 + 1 + + + ID2 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 2 + 1 + + + ID3 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 3 + 1 + + + ID4 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 4 + 1 + + + ID5 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 5 + 1 + + + ID6 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 6 + 1 + + + ID7 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 7 + 1 + + + ID8 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 8 + 1 + + + ID9 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 9 + 1 + + + ID10 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 10 + 1 + + + ID11 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 11 + 1 + + + ID12 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 12 + 1 + + + ID13 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 13 + 1 + + + ID14 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 14 + 1 + + + ID15 + Port input data bit (y = 0..15) These + bits are read-only. They contain the input value of + the corresponding I/O port. + 15 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 0 + 1 + + + OD1 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 1 + 1 + + + OD2 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 2 + 1 + + + OD3 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 3 + 1 + + + OD4 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 4 + 1 + + + OD5 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 5 + 1 + + + OD6 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 6 + 1 + + + OD7 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 7 + 1 + + + OD8 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 8 + 1 + + + OD9 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 9 + 1 + + + OD10 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 10 + 1 + + + OD11 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 11 + 1 + + + OD12 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 12 + 1 + + + OD13 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 13 + 1 + + + OD14 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 14 + 1 + + + OD15 + Port output data bit These bits can be + read and written by software. Note: For atomic bit + set/reset, the OD bits can be individually set and/or + reset by writing to the GPIOx_BSRR or GPIOx_BRR + registers (x = A..F). + 15 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 0 + 1 + + + BS1 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 1 + 1 + + + BS2 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 2 + 1 + + + BS3 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 3 + 1 + + + BS4 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 4 + 1 + + + BS5 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 5 + 1 + + + BS6 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 6 + 1 + + + BS7 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 7 + 1 + + + BS8 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 8 + 1 + + + BS9 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 9 + 1 + + + BS10 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 10 + 1 + + + BS11 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 11 + 1 + + + BS12 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 12 + 1 + + + BS13 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 13 + 1 + + + BS14 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 14 + 1 + + + BS15 + Port x set bit y (y= 0..15) These bits + are write-only. A read to these bits returns the + value 0x0000. + 15 + 1 + + + BR0 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 16 + 1 + + + BR1 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 17 + 1 + + + BR2 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 18 + 1 + + + BR3 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 19 + 1 + + + BR4 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 20 + 1 + + + BR5 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 21 + 1 + + + BR6 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 22 + 1 + + + BR7 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 23 + 1 + + + BR8 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 24 + 1 + + + BR9 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 25 + 1 + + + BR10 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 26 + 1 + + + BR11 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 27 + 1 + + + BR12 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 28 + 1 + + + BR13 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 29 + 1 + + + BR14 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 30 + 1 + + + BR15 + Port x reset bit y (y = 0..15) These + bits are write-only. A read to these bits returns the + value 0x0000. Note: If both BSx and BRx are set, BSx + has priority. + 31 + 1 + + + + + LCKR + LCKR + This register is used to lock the + configuration of the port bits when a correct write + sequence is applied to bit 16 (LCKK). The value of bits + [15:0] is used to lock the configuration of the GPIO. + During the write sequence, the value of LCKR[15:0] must + not change. When the LOCK sequence has been applied on a + port bit, the value of this port bit can no longer be + modified until the next MCU reset or peripheral reset.A + specific write sequence is used to write to the + GPIOx_LCKR register. Only word access (32-bit long) is + allowed during this locking sequence.Each lock bit + freezes a specific configuration register (control and + alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 0 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 1 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 2 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 3 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 4 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 5 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 6 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 7 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 8 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 9 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 10 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 11 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 12 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 13 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 14 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) These bits + are read/write but can only be written when the LCKK + bit is 0. + 15 + 1 + + + LCKK + Lock key This bit can be read any time. + It can only be modified using the lock key write + sequence. LOCK key write sequence: WR LCKR[16] = 1 + + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = + 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read + operation is optional but it confirms that the lock + is active) Note: During the LOCK key write sequence, + the value of LCK[15:0] must not change. Any error in + the lock sequence aborts the lock. After the first + lock sequence on any bit of the port, any read access + on the LCKK bit will return 1 until the next MCU + reset or peripheral reset. + 16 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 0 + 4 + + + AFSEL1 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 4 + 4 + + + AFSEL2 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 8 + 4 + + + AFSEL3 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 12 + 4 + + + AFSEL4 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 16 + 4 + + + AFSEL5 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 20 + 4 + + + AFSEL6 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 24 + 4 + + + AFSEL7 + [3:0]: Alternate function selection for + port x pin y (y = 0..7) These bits are written by + software to configure alternate function I/Os AFSELy + selection: + 28 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 0 + 4 + + + AFSEL9 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 4 + 4 + + + AFSEL10 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 8 + 4 + + + AFSEL11 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 12 + 4 + + + AFSEL12 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 16 + 4 + + + AFSEL13 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 20 + 4 + + + AFSEL14 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 24 + 4 + + + AFSEL15 + [3:0]: Alternate function selection for + port x pin y (y = 8..15) These bits are written by + software to configure alternate function + I/Os + 28 + 4 + + + + + + + GPIOB + 0x58020400 + + + GPIOC + 0x58020800 + + + GPIOD + 0x58020C00 + + + GPIOE + 0x58021000 + + + GPIOF + 0x58021400 + + + GPIOG + 0x58021800 + + + GPIOH + 0x58021C00 + + + GPIOI + 0x58022000 + + + GPIOJ + 0x58022400 + + + GPIOK + 0x58022800 + + + JPEG + JPEG + JPEG + 0x52003000 + + 0x0 + 0x400 + registers + + + JPEG + JPEG global interrupt + 121 + + + + CONFR0 + CONFR0 + JPEG codec control register + 0x0 + 0x20 + write-only + 0x00000000 + + + START + Start This bit start or stop the + encoding or decoding process. Read this register + always return 0. + 0 + 1 + + + + + CONFR1 + CONFR1 + JPEG codec configuration register + 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + NF + Number of color components This field + defines the number of color components minus + 1. + 0 + 2 + + + DE + Decoding Enable This bit selects the + coding or decoding process + 3 + 1 + + + COLORSPACE + Color Space This filed defines the + number of quantization tables minus 1 to insert in + the output stream. + 4 + 2 + + + NS + Number of components for Scan This field + defines the number of components minus 1 for scan + header marker segment. + 6 + 2 + + + HDR + Header Processing This bit enable the + header processing (generation/parsing). + 8 + 1 + + + YSIZE + Y Size This field defines the number of + lines in source image. + 16 + 16 + + + + + CONFR2 + CONFR2 + JPEG codec configuration register + 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + NMCU + Number of MCU For encoding: this field + defines the number of MCU units minus 1 to encode. + For decoding: this field indicates the number of + complete MCU units minus 1 to be decoded (this field + is updated after the JPEG header parsing). If the + decoded image size has not a X or Y size multiple of + 8 or 16 (depending on the sub-sampling process), the + resulting incomplete or empty MCU must be added to + this value to get the total number of MCU + generated. + 0 + 26 + + + + + CONFR3 + CONFR3 + JPEG codec configuration register + 3 + 0xC + 0x20 + read-write + 0x00000000 + + + XSIZE + X size This field defines the number of + pixels per line. + 16 + 16 + + + + + CONFRN1 + CONFRN1 + JPEG codec configuration register + 4-7 + 0x10 + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CONFRN2 + CONFRN2 + JPEG codec configuration register + 4-7 + 0x14 + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CONFRN3 + CONFRN3 + JPEG codec configuration register + 4-7 + 0x18 + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CONFRN4 + CONFRN4 + JPEG codec configuration register + 4-7 + 0x1C + 0x20 + read-write + 0x00000000 + + + HD + Huffman DC Selects the Huffman table for + encoding the DC coefficients. + 0 + 1 + + + HA + Huffman AC Selects the Huffman table for + encoding the AC coefficients. + 1 + 1 + + + QT + Quantization Table Selects quantization + table associated with a color + component. + 2 + 2 + + + NB + Number of Block Number of data units + minus 1 that belong to a particular color in the + MCU. + 4 + 4 + + + VSF + Vertical Sampling Factor Vertical + sampling factor for component i. + 8 + 4 + + + HSF + Horizontal Sampling Factor Horizontal + sampling factor for component i. + 12 + 4 + + + + + CR + CR + JPEG control register + 0x30 + 0x20 + read-write + 0x00000000 + + + JCEN + JPEG Core Enable Enable the JPEG codec + Core. + 0 + 1 + + + IFTIE + Input FIFO Threshold Interrupt Enable + This bit enables the interrupt generation when input + FIFO reach the threshold. + 1 + 1 + + + IFNFIE + Input FIFO Not Full Interrupt Enable + This bit enables the interrupt generation when input + FIFO is not empty. + 2 + 1 + + + OFTIE + Output FIFO Threshold Interrupt Enable + This bit enables the interrupt generation when output + FIFO reach the threshold. + 3 + 1 + + + OFNEIE + Output FIFO Not Empty Interrupt Enable + This bit enables the interrupt generation when output + FIFO is not empty. + 4 + 1 + + + EOCIE + End of Conversion Interrupt Enable This + bit enables the interrupt generation on the end of + conversion. + 5 + 1 + + + HPDIE + Header Parsing Done Interrupt Enable + This bit enables the interrupt generation on the + Header Parsing Operation. + 6 + 1 + + + IDMAEN + Input DMA Enable Enable the DMA request + generation for the input FIFO. + 11 + 1 + + + ODMAEN + Output DMA Enable Enable the DMA request + generation for the output FIFO. + 12 + 1 + + + IFF + Input FIFO Flush This bit flush the + input FIFO. This bit is always read as + 0. + 13 + 1 + + + OFF + Output FIFO Flush This bit flush the + output FIFO. This bit is always read as + 0. + 14 + 1 + + + + + SR + SR + JPEG status register + 0x34 + 0x20 + read-only + 0x00000006 + + + IFTF + Input FIFO Threshold Flag This bit is + set when the input FIFO is not full and is bellow its + threshold. + 1 + 1 + + + IFNFF + Input FIFO Not Full Flag This bit is set + when the input FIFO is not full (a data can be + written). + 2 + 1 + + + OFTF + Output FIFO Threshold Flag This bit is + set when the output FIFO is not empty and has reach + its threshold. + 3 + 1 + + + OFNEF + Output FIFO Not Empty Flag This bit is + set when the output FIFO is not empty (a data is + available). + 4 + 1 + + + EOCF + End of Conversion Flag This bit is set + when the JPEG codec core has finished the encoding or + the decoding process and than last data has been sent + to the output FIFO. + 5 + 1 + + + HPDF + Header Parsing Done Flag This bit is set + in decode mode when the JPEG codec has finished the + parsing of the headers and the internal registers + have been updated. + 6 + 1 + + + COF + Codec Operation Flag This bit is set + when when a JPEG codec operation is on going + (encoding or decoding). + 7 + 1 + + + + + CFR + CFR + JPEG clear flag register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEOCF + Clear End of Conversion Flag Writing 1 + clears the End of Conversion Flag of the JPEG Status + Register. + 5 + 1 + + + CHPDF + Clear Header Parsing Done Flag Writing 1 + clears the Header Parsing Done Flag of the JPEG + Status Register. + 6 + 1 + + + + + DIR + DIR + JPEG data input register + 0x40 + 0x20 + write-only + 0x00000000 + + + DATAIN + Data Input FIFO Input FIFO data + register. + 0 + 32 + + + + + DOR + DOR + JPEG data output register + 0x44 + 0x20 + read-only + 0x00000000 + + + DATAOUT + Data Output FIFO Output FIFO data + register. + 0 + 32 + + + + + + + MDMA + MDMA + MDMA + 0x52000000 + + 0x0 + 0x1000 + registers + + + MDMA + MDMA + 122 + + + + MDMA_GISR0 + MDMA_GISR0 + MDMA Global Interrupt/Status + Register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 0 + 1 + + + GIF1 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 1 + 1 + + + GIF2 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 2 + 1 + + + GIF3 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 3 + 1 + + + GIF4 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 4 + 1 + + + GIF5 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 5 + 1 + + + GIF6 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 6 + 1 + + + GIF7 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 7 + 1 + + + GIF8 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 8 + 1 + + + GIF9 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 9 + 1 + + + GIF10 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 10 + 1 + + + GIF11 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 11 + 1 + + + GIF12 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 12 + 1 + + + GIF13 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 13 + 1 + + + GIF14 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 14 + 1 + + + GIF15 + Channel x global interrupt flag (x=...) + This bit is set and reset by hardware. It is a + logical OR of all the Channel x interrupt flags + (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in + the interrupt mask register (CTCIEx, BTIEx, BRTIEx, + TEIEx) + 15 + 1 + + + + + MDMA_C0ISR + MDMA_C0ISR + MDMA channel x interrupt/status + register + 0x40 + 0x20 + read-only + 0x00000000 + + + TEIF0 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF0 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF0 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF0 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF0 + channel x buffer transfer + complete + 4 + 1 + + + CRQA0 + channel x request active + flag + 16 + 1 + + + + + MDMA_C0IFCR + MDMA_C0IFCR + MDMA channel x interrupt flag clear + register + 0x44 + 0x20 + write-only + 0x00000000 + + + CTEIF0 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF0 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF0 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF0 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF0 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C0ESR + MDMA_C0ESR + MDMA Channel x error status + register + 0x48 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C0CR + MDMA_C0CR + This register is used to control the + concerned channel. + 0x4C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C0TCR + MDMA_C0TCR + This register is used to configure the + concerned channel. + 0x50 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C0BNDTR + MDMA_C0BNDTR + MDMA Channel x block number of data + register + 0x54 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C0SAR + MDMA_C0SAR + MDMA channel x source address + register + 0x58 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C0DAR + MDMA_C0DAR + MDMA channel x destination address + register + 0x5C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C0BRUR + MDMA_C0BRUR + MDMA channel x Block Repeat address Update + register + 0x60 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C0LAR + MDMA_C0LAR + MDMA channel x Link Address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C0TBR + MDMA_C0TBR + MDMA channel x Trigger and Bus selection + Register + 0x68 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C0MAR + MDMA_C0MAR + MDMA channel x Mask address + register + 0x70 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C0MDR + MDMA_C0MDR + MDMA channel x Mask Data + register + 0x74 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C1ISR + MDMA_C1ISR + MDMA channel x interrupt/status + register + 0x80 + 0x20 + read-only + 0x00000000 + + + TEIF1 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF1 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF1 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF1 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF1 + channel x buffer transfer + complete + 4 + 1 + + + CRQA1 + channel x request active + flag + 16 + 1 + + + + + MDMA_C1IFCR + MDMA_C1IFCR + MDMA channel x interrupt flag clear + register + 0x84 + 0x20 + write-only + 0x00000000 + + + CTEIF1 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF1 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF1 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF1 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF1 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C1ESR + MDMA_C1ESR + MDMA Channel x error status + register + 0x88 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C1CR + MDMA_C1CR + This register is used to control the + concerned channel. + 0x8C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C1TCR + MDMA_C1TCR + This register is used to configure the + concerned channel. + 0x90 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C1BNDTR + MDMA_C1BNDTR + MDMA Channel x block number of data + register + 0x94 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C1SAR + MDMA_C1SAR + MDMA channel x source address + register + 0x98 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C1DAR + MDMA_C1DAR + MDMA channel x destination address + register + 0x9C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C1BRUR + MDMA_C1BRUR + MDMA channel x Block Repeat address Update + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C1LAR + MDMA_C1LAR + MDMA channel x Link Address + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C1TBR + MDMA_C1TBR + MDMA channel x Trigger and Bus selection + Register + 0xA8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C1MAR + MDMA_C1MAR + MDMA channel x Mask address + register + 0xB0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C1MDR + MDMA_C1MDR + MDMA channel x Mask Data + register + 0xB4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C2ISR + MDMA_C2ISR + MDMA channel x interrupt/status + register + 0xC0 + 0x20 + read-only + 0x00000000 + + + TEIF2 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF2 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF2 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF2 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF2 + channel x buffer transfer + complete + 4 + 1 + + + CRQA2 + channel x request active + flag + 16 + 1 + + + + + MDMA_C2IFCR + MDMA_C2IFCR + MDMA channel x interrupt flag clear + register + 0xC4 + 0x20 + write-only + 0x00000000 + + + CTEIF2 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF2 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF2 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF2 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF2 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C2ESR + MDMA_C2ESR + MDMA Channel x error status + register + 0xC8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C2CR + MDMA_C2CR + This register is used to control the + concerned channel. + 0xCC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C2TCR + MDMA_C2TCR + This register is used to configure the + concerned channel. + 0xD0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C2BNDTR + MDMA_C2BNDTR + MDMA Channel x block number of data + register + 0xD4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C2SAR + MDMA_C2SAR + MDMA channel x source address + register + 0xD8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C2DAR + MDMA_C2DAR + MDMA channel x destination address + register + 0xDC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C2BRUR + MDMA_C2BRUR + MDMA channel x Block Repeat address Update + register + 0xE0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C2LAR + MDMA_C2LAR + MDMA channel x Link Address + register + 0xE4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C2TBR + MDMA_C2TBR + MDMA channel x Trigger and Bus selection + Register + 0xE8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C2MAR + MDMA_C2MAR + MDMA channel x Mask address + register + 0xF0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C2MDR + MDMA_C2MDR + MDMA channel x Mask Data + register + 0xF4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C3ISR + MDMA_C3ISR + MDMA channel x interrupt/status + register + 0x100 + 0x20 + read-only + 0x00000000 + + + TEIF3 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF3 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF3 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF3 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF3 + channel x buffer transfer + complete + 4 + 1 + + + CRQA3 + channel x request active + flag + 16 + 1 + + + + + MDMA_C3IFCR + MDMA_C3IFCR + MDMA channel x interrupt flag clear + register + 0x104 + 0x20 + write-only + 0x00000000 + + + CTEIF3 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF3 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF3 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF3 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF3 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C3ESR + MDMA_C3ESR + MDMA Channel x error status + register + 0x108 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C3CR + MDMA_C3CR + This register is used to control the + concerned channel. + 0x10C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C3TCR + MDMA_C3TCR + This register is used to configure the + concerned channel. + 0x110 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C3BNDTR + MDMA_C3BNDTR + MDMA Channel x block number of data + register + 0x114 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C3SAR + MDMA_C3SAR + MDMA channel x source address + register + 0x118 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C3DAR + MDMA_C3DAR + MDMA channel x destination address + register + 0x11C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C3BRUR + MDMA_C3BRUR + MDMA channel x Block Repeat address Update + register + 0x120 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C3LAR + MDMA_C3LAR + MDMA channel x Link Address + register + 0x124 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C3TBR + MDMA_C3TBR + MDMA channel x Trigger and Bus selection + Register + 0x128 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C3MAR + MDMA_C3MAR + MDMA channel x Mask address + register + 0x130 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C3MDR + MDMA_C3MDR + MDMA channel x Mask Data + register + 0x134 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C4ISR + MDMA_C4ISR + MDMA channel x interrupt/status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + TEIF4 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF4 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF4 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF4 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF4 + channel x buffer transfer + complete + 4 + 1 + + + CRQA4 + channel x request active + flag + 16 + 1 + + + + + MDMA_C4IFCR + MDMA_C4IFCR + MDMA channel x interrupt flag clear + register + 0x144 + 0x20 + write-only + 0x00000000 + + + CTEIF4 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF4 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF4 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF4 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF4 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C4ESR + MDMA_C4ESR + MDMA Channel x error status + register + 0x148 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C4CR + MDMA_C4CR + This register is used to control the + concerned channel. + 0x14C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C4TCR + MDMA_C4TCR + This register is used to configure the + concerned channel. + 0x150 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C4BNDTR + MDMA_C4BNDTR + MDMA Channel x block number of data + register + 0x154 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C4SAR + MDMA_C4SAR + MDMA channel x source address + register + 0x158 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C4DAR + MDMA_C4DAR + MDMA channel x destination address + register + 0x15C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C4BRUR + MDMA_C4BRUR + MDMA channel x Block Repeat address Update + register + 0x160 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C4LAR + MDMA_C4LAR + MDMA channel x Link Address + register + 0x164 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C4TBR + MDMA_C4TBR + MDMA channel x Trigger and Bus selection + Register + 0x168 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C4MAR + MDMA_C4MAR + MDMA channel x Mask address + register + 0x170 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C4MDR + MDMA_C4MDR + MDMA channel x Mask Data + register + 0x174 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C5ISR + MDMA_C5ISR + MDMA channel x interrupt/status + register + 0x180 + 0x20 + read-only + 0x00000000 + + + TEIF5 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF5 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF5 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF5 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF5 + channel x buffer transfer + complete + 4 + 1 + + + CRQA5 + channel x request active + flag + 16 + 1 + + + + + MDMA_C5IFCR + MDMA_C5IFCR + MDMA channel x interrupt flag clear + register + 0x184 + 0x20 + write-only + 0x00000000 + + + CTEIF5 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF5 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF5 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF5 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF5 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C5ESR + MDMA_C5ESR + MDMA Channel x error status + register + 0x188 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C5CR + MDMA_C5CR + This register is used to control the + concerned channel. + 0x18C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C5TCR + MDMA_C5TCR + This register is used to configure the + concerned channel. + 0x190 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C5BNDTR + MDMA_C5BNDTR + MDMA Channel x block number of data + register + 0x194 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C5SAR + MDMA_C5SAR + MDMA channel x source address + register + 0x198 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C5DAR + MDMA_C5DAR + MDMA channel x destination address + register + 0x19C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C5BRUR + MDMA_C5BRUR + MDMA channel x Block Repeat address Update + register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C5LAR + MDMA_C5LAR + MDMA channel x Link Address + register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C5TBR + MDMA_C5TBR + MDMA channel x Trigger and Bus selection + Register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C5MAR + MDMA_C5MAR + MDMA channel x Mask address + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C5MDR + MDMA_C5MDR + MDMA channel x Mask Data + register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C6ISR + MDMA_C6ISR + MDMA channel x interrupt/status + register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + TEIF6 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF6 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF6 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF6 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF6 + channel x buffer transfer + complete + 4 + 1 + + + CRQA6 + channel x request active + flag + 16 + 1 + + + + + MDMA_C6IFCR + MDMA_C6IFCR + MDMA channel x interrupt flag clear + register + 0x1C4 + 0x20 + write-only + 0x00000000 + + + CTEIF6 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF6 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF6 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF6 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF6 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C6ESR + MDMA_C6ESR + MDMA Channel x error status + register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C6CR + MDMA_C6CR + This register is used to control the + concerned channel. + 0x1CC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C6TCR + MDMA_C6TCR + This register is used to configure the + concerned channel. + 0x1D0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C6BNDTR + MDMA_C6BNDTR + MDMA Channel x block number of data + register + 0x1D4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0 + 20 + 12 + + + + + MDMA_C6SAR + MDMA_C6SAR + MDMA channel x source address + register + 0x1D8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C6DAR + MDMA_C6DAR + MDMA channel x destination address + register + 0x1DC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C6BRUR + MDMA_C6BRUR + MDMA channel x Block Repeat address Update + register + 0x1E0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C6LAR + MDMA_C6LAR + MDMA channel x Link Address + register + 0x1E4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C6TBR + MDMA_C6TBR + MDMA channel x Trigger and Bus selection + Register + 0x1E8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C6MAR + MDMA_C6MAR + MDMA channel x Mask address + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C6MDR + MDMA_C6MDR + MDMA channel x Mask Data + register + 0x1F4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C7ISR + MDMA_C7ISR + MDMA channel x interrupt/status + register + 0x200 + 0x20 + read-only + 0x00000000 + + + TEIF7 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF7 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF7 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF7 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF7 + channel x buffer transfer + complete + 4 + 1 + + + CRQA7 + channel x request active + flag + 16 + 1 + + + + + MDMA_C7IFCR + MDMA_C7IFCR + MDMA channel x interrupt flag clear + register + 0x204 + 0x20 + write-only + 0x00000000 + + + CTEIF7 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF7 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF7 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF7 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF7 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C7ESR + MDMA_C7ESR + MDMA Channel x error status + register + 0x208 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C7CR + MDMA_C7CR + This register is used to control the + concerned channel. + 0x20C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C7TCR + MDMA_C7TCR + This register is used to configure the + concerned channel. + 0x210 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C7BNDTR + MDMA_C7BNDTR + MDMA Channel x block number of data + register + 0x214 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C7SAR + MDMA_C7SAR + MDMA channel x source address + register + 0x218 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C7DAR + MDMA_C7DAR + MDMA channel x destination address + register + 0x21C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C7BRUR + MDMA_C7BRUR + MDMA channel x Block Repeat address Update + register + 0x220 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C7LAR + MDMA_C7LAR + MDMA channel x Link Address + register + 0x224 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C7TBR + MDMA_C7TBR + MDMA channel x Trigger and Bus selection + Register + 0x228 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C7MAR + MDMA_C7MAR + MDMA channel x Mask address + register + 0x230 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C7MDR + MDMA_C7MDR + MDMA channel x Mask Data + register + 0x234 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C8ISR + MDMA_C8ISR + MDMA channel x interrupt/status + register + 0x240 + 0x20 + read-only + 0x00000000 + + + TEIF8 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF8 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF8 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF8 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF8 + channel x buffer transfer + complete + 4 + 1 + + + CRQA8 + channel x request active + flag + 16 + 1 + + + + + MDMA_C8IFCR + MDMA_C8IFCR + MDMA channel x interrupt flag clear + register + 0x244 + 0x20 + write-only + 0x00000000 + + + CTEIF8 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF8 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF8 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF8 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF8 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C8ESR + MDMA_C8ESR + MDMA Channel x error status + register + 0x248 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C8CR + MDMA_C8CR + This register is used to control the + concerned channel. + 0x24C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C8TCR + MDMA_C8TCR + This register is used to configure the + concerned channel. + 0x250 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C8BNDTR + MDMA_C8BNDTR + MDMA Channel x block number of data + register + 0x254 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C8SAR + MDMA_C8SAR + MDMA channel x source address + register + 0x258 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C8DAR + MDMA_C8DAR + MDMA channel x destination address + register + 0x25C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C8BRUR + MDMA_C8BRUR + MDMA channel x Block Repeat address Update + register + 0x260 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C8LAR + MDMA_C8LAR + MDMA channel x Link Address + register + 0x264 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C8TBR + MDMA_C8TBR + MDMA channel x Trigger and Bus selection + Register + 0x268 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C8MAR + MDMA_C8MAR + MDMA channel x Mask address + register + 0x270 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C8MDR + MDMA_C8MDR + MDMA channel x Mask Data + register + 0x274 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C9ISR + MDMA_C9ISR + MDMA channel x interrupt/status + register + 0x280 + 0x20 + read-only + 0x00000000 + + + TEIF9 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF9 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF9 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF9 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF9 + channel x buffer transfer + complete + 4 + 1 + + + CRQA9 + channel x request active + flag + 16 + 1 + + + + + MDMA_C9IFCR + MDMA_C9IFCR + MDMA channel x interrupt flag clear + register + 0x284 + 0x20 + write-only + 0x00000000 + + + CTEIF9 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF9 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF9 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF9 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF9 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C9ESR + MDMA_C9ESR + MDMA Channel x error status + register + 0x288 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C9CR + MDMA_C9CR + This register is used to control the + concerned channel. + 0x28C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C9TCR + MDMA_C9TCR + This register is used to configure the + concerned channel. + 0x290 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C9BNDTR + MDMA_C9BNDTR + MDMA Channel x block number of data + register + 0x294 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C9SAR + MDMA_C9SAR + MDMA channel x source address + register + 0x298 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C9DAR + MDMA_C9DAR + MDMA channel x destination address + register + 0x29C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C9BRUR + MDMA_C9BRUR + MDMA channel x Block Repeat address Update + register + 0x2A0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C9LAR + MDMA_C9LAR + MDMA channel x Link Address + register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C9TBR + MDMA_C9TBR + MDMA channel x Trigger and Bus selection + Register + 0x2A8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C9MAR + MDMA_C9MAR + MDMA channel x Mask address + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C9MDR + MDMA_C9MDR + MDMA channel x Mask Data + register + 0x2B4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C10ISR + MDMA_C10ISR + MDMA channel x interrupt/status + register + 0x2C0 + 0x20 + read-only + 0x00000000 + + + TEIF10 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF10 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF10 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF10 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF10 + channel x buffer transfer + complete + 4 + 1 + + + CRQA10 + channel x request active + flag + 16 + 1 + + + + + MDMA_C10IFCR + MDMA_C10IFCR + MDMA channel x interrupt flag clear + register + 0x2C4 + 0x20 + write-only + 0x00000000 + + + CTEIF10 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF10 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF10 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF10 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF10 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C10ESR + MDMA_C10ESR + MDMA Channel x error status + register + 0x2C8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C10CR + MDMA_C10CR + This register is used to control the + concerned channel. + 0x2CC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C10TCR + MDMA_C10TCR + This register is used to configure the + concerned channel. + 0x2D0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C10BNDTR + MDMA_C10BNDTR + MDMA Channel x block number of data + register + 0x2D4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C10SAR + MDMA_C10SAR + MDMA channel x source address + register + 0x2D8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C10DAR + MDMA_C10DAR + MDMA channel x destination address + register + 0x2DC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C10BRUR + MDMA_C10BRUR + MDMA channel x Block Repeat address Update + register + 0x2E0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C10LAR + MDMA_C10LAR + MDMA channel x Link Address + register + 0x2E4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C10TBR + MDMA_C10TBR + MDMA channel x Trigger and Bus selection + Register + 0x2E8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C10MAR + MDMA_C10MAR + MDMA channel x Mask address + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C10MDR + MDMA_C10MDR + MDMA channel x Mask Data + register + 0x2F4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C11ISR + MDMA_C11ISR + MDMA channel x interrupt/status + register + 0x300 + 0x20 + read-only + 0x00000000 + + + TEIF11 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF11 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF11 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF11 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF11 + channel x buffer transfer + complete + 4 + 1 + + + CRQA11 + channel x request active + flag + 16 + 1 + + + + + MDMA_C11IFCR + MDMA_C11IFCR + MDMA channel x interrupt flag clear + register + 0x304 + 0x20 + write-only + 0x00000000 + + + CTEIF11 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF11 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF11 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF11 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF11 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C11ESR + MDMA_C11ESR + MDMA Channel x error status + register + 0x308 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C11CR + MDMA_C11CR + This register is used to control the + concerned channel. + 0x30C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C11TCR + MDMA_C11TCR + This register is used to configure the + concerned channel. + 0x310 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C11BNDTR + MDMA_C11BNDTR + MDMA Channel x block number of data + register + 0x314 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C11SAR + MDMA_C11SAR + MDMA channel x source address + register + 0x318 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C11DAR + MDMA_C11DAR + MDMA channel x destination address + register + 0x31C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C11BRUR + MDMA_C11BRUR + MDMA channel x Block Repeat address Update + register + 0x320 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C11LAR + MDMA_C11LAR + MDMA channel x Link Address + register + 0x324 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C11TBR + MDMA_C11TBR + MDMA channel x Trigger and Bus selection + Register + 0x328 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C11MAR + MDMA_C11MAR + MDMA channel x Mask address + register + 0x330 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C11MDR + MDMA_C11MDR + MDMA channel x Mask Data + register + 0x334 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C12ISR + MDMA_C12ISR + MDMA channel x interrupt/status + register + 0x340 + 0x20 + read-only + 0x00000000 + + + TEIF12 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF12 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF12 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF12 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF12 + channel x buffer transfer + complete + 4 + 1 + + + CRQA12 + channel x request active + flag + 16 + 1 + + + + + MDMA_C12IFCR + MDMA_C12IFCR + MDMA channel x interrupt flag clear + register + 0x344 + 0x20 + write-only + 0x00000000 + + + CTEIF12 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF12 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF12 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF12 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF12 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C12ESR + MDMA_C12ESR + MDMA Channel x error status + register + 0x348 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C12CR + MDMA_C12CR + This register is used to control the + concerned channel. + 0x34C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C12TCR + MDMA_C12TCR + This register is used to configure the + concerned channel. + 0x350 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C12BNDTR + MDMA_C12BNDTR + MDMA Channel x block number of data + register + 0x354 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C12SAR + MDMA_C12SAR + MDMA channel x source address + register + 0x358 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C12DAR + MDMA_C12DAR + MDMA channel x destination address + register + 0x35C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C12BRUR + MDMA_C12BRUR + MDMA channel x Block Repeat address Update + register + 0x360 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C12LAR + MDMA_C12LAR + MDMA channel x Link Address + register + 0x364 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C12TBR + MDMA_C12TBR + MDMA channel x Trigger and Bus selection + Register + 0x368 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C12MAR + MDMA_C12MAR + MDMA channel x Mask address + register + 0x370 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C12MDR + MDMA_C12MDR + MDMA channel x Mask Data + register + 0x374 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C13ISR + MDMA_C13ISR + MDMA channel x interrupt/status + register + 0x380 + 0x20 + read-only + 0x00000000 + + + TEIF13 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF13 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF13 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF13 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF13 + channel x buffer transfer + complete + 4 + 1 + + + CRQA13 + channel x request active + flag + 16 + 1 + + + + + MDMA_C13IFCR + MDMA_C13IFCR + MDMA channel x interrupt flag clear + register + 0x384 + 0x20 + write-only + 0x00000000 + + + CTEIF13 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF13 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF13 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF13 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF13 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C13ESR + MDMA_C13ESR + MDMA Channel x error status + register + 0x388 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C13CR + MDMA_C13CR + This register is used to control the + concerned channel. + 0x38C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C13TCR + MDMA_C13TCR + This register is used to configure the + concerned channel. + 0x390 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C13BNDTR + MDMA_C13BNDTR + MDMA Channel x block number of data + register + 0x394 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C13SAR + MDMA_C13SAR + MDMA channel x source address + register + 0x398 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C13DAR + MDMA_C13DAR + MDMA channel x destination address + register + 0x39C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C13BRUR + MDMA_C13BRUR + MDMA channel x Block Repeat address Update + register + 0x3A0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C13LAR + MDMA_C13LAR + MDMA channel x Link Address + register + 0x3A4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C13TBR + MDMA_C13TBR + MDMA channel x Trigger and Bus selection + Register + 0x3A8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C13MAR + MDMA_C13MAR + MDMA channel x Mask address + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C13MDR + MDMA_C13MDR + MDMA channel x Mask Data + register + 0x3B4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C14ISR + MDMA_C14ISR + MDMA channel x interrupt/status + register + 0x3C0 + 0x20 + read-only + 0x00000000 + + + TEIF14 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF14 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF14 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF14 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF14 + channel x buffer transfer + complete + 4 + 1 + + + CRQA14 + channel x request active + flag + 16 + 1 + + + + + MDMA_C14IFCR + MDMA_C14IFCR + MDMA channel x interrupt flag clear + register + 0x3C4 + 0x20 + write-only + 0x00000000 + + + CTEIF14 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF14 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF14 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF14 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF14 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C14ESR + MDMA_C14ESR + MDMA Channel x error status + register + 0x3C8 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C14CR + MDMA_C14CR + This register is used to control the + concerned channel. + 0x3CC + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C14TCR + MDMA_C14TCR + This register is used to configure the + concerned channel. + 0x3D0 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C14BNDTR + MDMA_C14BNDTR + MDMA Channel x block number of data + register + 0x3D4 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C14SAR + MDMA_C14SAR + MDMA channel x source address + register + 0x3D8 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C14DAR + MDMA_C14DAR + MDMA channel x destination address + register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C14BRUR + MDMA_C14BRUR + MDMA channel x Block Repeat address Update + register + 0x3E0 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C14LAR + MDMA_C14LAR + MDMA channel x Link Address + register + 0x3E4 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C14TBR + MDMA_C14TBR + MDMA channel x Trigger and Bus selection + Register + 0x3E8 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C14MAR + MDMA_C14MAR + MDMA channel x Mask address + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C14MDR + MDMA_C14MDR + MDMA channel x Mask Data + register + 0x3F4 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + MDMA_C15ISR + MDMA_C15ISR + MDMA channel x interrupt/status + register + 0x400 + 0x20 + read-only + 0x00000000 + + + TEIF15 + Channel x transfer error interrupt flag + This bit is set by hardware. It is cleared by + software writing 1 to the corresponding bit in the + DMA_IFCRy register. + 0 + 1 + + + CTCIF15 + Channel x Channel Transfer Complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. CTC is set when the + last block was transferred and the channel has been + automatically disabled. CTC is also set when the + channel is suspended, as a result of writing EN bit + to 0. + 1 + 1 + + + BRTIF15 + Channel x block repeat transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 2 + 1 + + + BTIF15 + Channel x block transfer complete + interrupt flag This bit is set by hardware. It is + cleared by software writing 1 to the corresponding + bit in the DMA_IFCRy register. + 3 + 1 + + + TCIF15 + channel x buffer transfer + complete + 4 + 1 + + + CRQA15 + channel x request active + flag + 16 + 1 + + + + + MDMA_C15IFCR + MDMA_C15IFCR + MDMA channel x interrupt flag clear + register + 0x404 + 0x20 + write-only + 0x00000000 + + + CTEIF15 + Channel x clear transfer error interrupt + flag Writing a 1 into this bit clears TEIFx in the + MDMA_ISRy register + 0 + 1 + + + CCTCIF15 + Clear Channel transfer complete + interrupt flag for channel x Writing a 1 into this + bit clears CTCIFx in the MDMA_ISRy + register + 1 + 1 + + + CBRTIF15 + Channel x clear block repeat transfer + complete interrupt flag Writing a 1 into this bit + clears BRTIFx in the MDMA_ISRy register + 2 + 1 + + + CBTIF15 + Channel x Clear block transfer complete + interrupt flag Writing a 1 into this bit clears BTIFx + in the MDMA_ISRy register + 3 + 1 + + + CLTCIF15 + CLear buffer Transfer Complete Interrupt + Flag for channel x Writing a 1 into this bit clears + TCIFx in the MDMA_ISRy register + 4 + 1 + + + + + MDMA_C15ESR + MDMA_C15ESR + MDMA Channel x error status + register + 0x408 + 0x20 + read-only + 0x00000000 + + + TEA + Transfer Error Address These bits are + set and cleared by HW, in case of an MDMA data + transfer error. It is used in conjunction with TED. + This field indicates the 7 LSBits of the address + which generated a transfer/access error. It may be + used by SW to retrieve the failing address, by adding + this value (truncated to the buffer transfer length + size) to the current SAR/DAR value. Note: The SAR/DAR + current value doesnt reflect this last address due to + the FIFO management system. The SAR/DAR are only + updated at the end of a (buffer) transfer (of TLEN+1 + bytes). Note: It is not set in case of a link data + error. + 0 + 7 + + + TED + Transfer Error Direction These bit is + set and cleared by HW, in case of an MDMA data + transfer error. + 7 + 1 + + + TELD + Transfer Error Link Data These bit is + set by HW, in case of a transfer error while reading + the block link data structure. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 8 + 1 + + + TEMD + Transfer Error Mask Data These bit is + set by HW, in case of a transfer error while writing + the Mask Data. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 9 + 1 + + + ASE + Address/Size Error These bit is set by + HW, when the programmed address is not aligned with + the data size. TED will indicate whether the problem + is on the source or destination. It is cleared by + software writing 1 to the CTEIFx bit in the DMA_IFCRy + register. + 10 + 1 + + + BSE + Block Size Error These bit is set by HW, + when the block size is not an integer multiple of the + data size either for source or destination. TED will + indicate whether the problem is on the source or + destination. It is cleared by software writing 1 to + the CTEIFx bit in the DMA_IFCRy + register. + 11 + 1 + + + + + MDMA_C15CR + MDMA_C15CR + This register is used to control the + concerned channel. + 0x40C + 0x20 + 0x00000000 + + + EN + channel enable + 0 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + is set and cleared by software. + 1 + 1 + read-write + + + CTCIE + Channel Transfer Complete interrupt + enable This bit is set and cleared by + software. + 2 + 1 + read-write + + + BRTIE + Block Repeat transfer interrupt enable + This bit is set and cleared by + software. + 3 + 1 + read-write + + + BTIE + Block Transfer interrupt enable This bit + is set and cleared by software. + 4 + 1 + read-write + + + TCIE + buffer Transfer Complete interrupt + enable This bit is set and cleared by + software. + 5 + 1 + read-write + + + PL + Priority level These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0. + 6 + 2 + read-write + + + BEX + byte Endianness exchange + 12 + 1 + read-write + + + HEX + Half word Endianes + exchange + 13 + 1 + read-write + + + WEX + Word Endianness exchange + 14 + 1 + read-write + + + SWRQ + SW ReQuest Writing a 1 into this bit + sets the CRQAx in MDMA_ISRy register, activating the + request on Channel x Note: Either the whole CxCR + register or the 8-bit/16-bit register @ Address + offset: 0x4E + 0x40 chn may be used for SWRQ + activation. In case of a SW request, acknowledge is + not generated (neither HW signal, nor CxMAR write + access). + 16 + 1 + write-only + + + + + MDMA_C15TCR + MDMA_C15TCR + This register is used to configure the + concerned channel. + 0x410 + 0x20 + read-write + 0x00000000 + + + SINC + Source increment mode These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0 Note: When source is + AHB (SBUS=1), SINC = 00 is forbidden. In Linked List + Mode, at the end of a block (single or last block in + repeated block transfer mode), this register will be + loaded from memory (from address given by current + LAR[31:0] + 0x00). + 0 + 2 + + + DINC + Destination increment mode These bits + are set and cleared by software. These bits are + protected and can be written only if EN is 0 Note: + When destination is AHB (DBUS=1), DINC = 00 is + forbidden. + 2 + 2 + + + SSIZE + Source data size These bits are set and + cleared by software. These bits are protected and can + be written only if EN is 0 Note: If a value of 11 is + programmed for the TCM access/AHB port, a transfer + error will occur (TEIF bit set) If SINCOS &lt; + SSIZE and SINC &#8800; 00, the result will be + unpredictable. Note: SSIZE = 11 (double-word) is + forbidden when source is TCM/AHB bus + (SBUS=1). + 4 + 2 + + + DSIZE + Destination data size These bits are set + and cleared by software. These bits are protected and + can be written only if EN is 0. Note: If a value of + 11 is programmed for the TCM access/AHB port, a + transfer error will occur (TEIF bit set) If DINCOS + &lt; DSIZE and DINC &#8800; 00, the result + will be unpredictable. Note: DSIZE = 11 (double-word) + is forbidden when destination is TCM/AHB bus + (DBUS=1). + 6 + 2 + + + SINCOS + source increment offset + size + 8 + 2 + + + DINCOS + Destination increment + offset + 10 + 2 + + + SBURST + source burst transfer + configuration + 12 + 3 + + + DBURST + Destination burst transfer + configuration + 15 + 3 + + + TLEN + buffer transfer lengh + 18 + 7 + + + PKE + PacK Enable These bit is set and cleared + by software. If the Source Size is smaller than the + destination, it will be padded according to the PAM + value. If the Source data size is larger than the + destination one, it will be truncated. The alignment + will be done according to the PAM[0] value. This bit + is protected and can be written only if EN is + 0 + 25 + 1 + + + PAM + Padding/Alignement Mode These bits are + set and cleared by software. Case 1: Source data size + smaller than destination data size - 3 options are + valid. Case 2: Source data size larger than + destination data size. The remainder part is + discarded. When PKE = 1 or DSIZE=SSIZE, these bits + are ignored. These bits are protected and can be + written only if EN is 0 + 26 + 2 + + + TRGM + Trigger Mode These bits are set and + cleared by software. Note: If TRGM is 11 for the + current block, all the values loaded at the end of + the current block through the linked list mechanism + must keep the same value (TRGM=11) and the same SWRM + value, otherwise the result is undefined. These bits + are protected and can be written only if EN is + 0. + 28 + 2 + + + SWRM + SW Request Mode This bit is set and + cleared by software. If a HW or SW request is + currently active, the bit change will be delayed + until the current transfer is completed. If the CxMAR + contains a valid address, the CxMDR value will also + be written @ CxMAR address. This bit is protected and + can be written only if EN is 0. + 30 + 1 + + + BWM + Bufferable Write Mode This bit is set + and cleared by software. This bit is protected and + can be written only if EN is 0. Note: All MDMA + destination accesses are non-cacheable. + 31 + 1 + + + + + MDMA_C15BNDTR + MDMA_C15BNDTR + MDMA Channel x block number of data + register + 0x414 + 0x20 + read-write + 0x00000000 + + + BNDT + block number of data to + transfer + 0 + 17 + + + BRSUM + Block Repeat Source address Update Mode + These bits are protected and can be written only if + EN is 0. + 18 + 1 + + + BRDUM + Block Repeat Destination address Update + Mode These bits are protected and can be written only + if EN is 0. + 19 + 1 + + + BRC + Block Repeat Count This field contains + the number of repetitions of the current block (0 to + 4095). When the channel is enabled, this register is + read-only, indicating the remaining number of blocks, + excluding the current one. This register decrements + after each complete block transfer. Once the last + block transfer has completed, this register can + either stay at zero or be reloaded automatically from + memory (in Linked List mode - i.e. Link Address + valid). These bits are protected and can be written + only if EN is 0. + 20 + 12 + + + + + MDMA_C15SAR + MDMA_C15SAR + MDMA channel x source address + register + 0x418 + 0x20 + read-write + 0x00000000 + + + SAR + source adr base + 0 + 32 + + + + + MDMA_C15DAR + MDMA_C15DAR + MDMA channel x destination address + register + 0x41C + 0x20 + read-write + 0x00000000 + + + DAR + Destination adr base + 0 + 32 + + + + + MDMA_C15BRUR + MDMA_C15BRUR + MDMA channel x Block Repeat address Update + register + 0x420 + 0x20 + read-write + 0x00000000 + + + SUV + source adresse update + value + 0 + 16 + + + DUV + destination address update + 16 + 16 + + + + + MDMA_C15LAR + MDMA_C15LAR + MDMA channel x Link Address + register + 0x424 + 0x20 + read-write + 0x00000000 + + + LAR + Link address register + 0 + 32 + + + + + MDMA_C15TBR + MDMA_C15TBR + MDMA channel x Trigger and Bus selection + Register + 0x428 + 0x20 + read-write + 0x00000000 + + + TSEL + Trigger selection + 0 + 6 + + + SBUS + Source BUS select This bit is protected + and can be written only if EN is 0. + 16 + 1 + + + DBUS + Destination BUS slect This bit is + protected and can be written only if EN is + 0. + 17 + 1 + + + + + MDMA_C15MAR + MDMA_C15MAR + MDMA channel x Mask address + register + 0x430 + 0x20 + read-write + 0x00000000 + + + MAR + Mask address + 0 + 32 + + + + + MDMA_C15MDR + MDMA_C15MDR + MDMA channel x Mask Data + register + 0x434 + 0x20 + read-write + 0x00000000 + + + MDR + Mask data + 0 + 32 + + + + + + + QUADSPI + QUADSPI + QUADSPI + 0x52005000 + + 0x0 + 0x400 + registers + + + QUADSPI + QuadSPI global interrupt + 92 + + + + CR + CR + QUADSPI control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + Enable Enable the QUADSPI. + 0 + 1 + + + ABORT + Abort request This bit aborts the + on-going command sequence. It is automatically reset + once the abort is complete. This bit stops the + current transfer. In polling mode or memory-mapped + mode, this bit also reset the APM bit or the DM + bit. + 1 + 1 + + + DMAEN + DMA enable In indirect mode, DMA can be + used to input or output data via the QUADSPI_DR + register. DMA transfers are initiated when the FIFO + threshold flag, FTF, is set. + 2 + 1 + + + TCEN + Timeout counter enable This bit is valid + only when memory-mapped mode (FMODE = 11) is + selected. Activating this bit causes the chip select + (nCS) to be released (and thus reduces consumption) + if there has not been an access after a certain + amount of time, where this time is defined by + TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout + counter. By default, the QUADSPI never stops its + prefetch operation, keeping the previous read + operation active with nCS maintained low, even if no + access to the Flash memory occurs for a long time. + Since Flash memories tend to consume more when nCS is + held low, the application might want to activate the + timeout counter (TCEN = 1, QUADSPI_CR[3]) so that nCS + is released after a period of TIMEOUT[15:0] + (QUADSPI_LPTR) cycles have elapsed without an access + since when the FIFO becomes full with prefetch data. + This bit can be modified only when BUSY = + 0. + 3 + 1 + + + SSHIFT + Sample shift By default, the QUADSPI + samples data 1/2 of a CLK cycle after the data is + driven by the Flash memory. This bit allows the data + is to be sampled later in order to account for + external signal delays. Firmware must assure that + SSHIFT = 0 when in DDR mode (when DDRM = 1). This + field can be modified only when BUSY = + 0. + 4 + 1 + + + DFM + Dual-flash mode This bit activates + dual-flash mode, where two external Flash memories + are used simultaneously to double throughput and + capacity. This bit can be modified only when BUSY = + 0. + 6 + 1 + + + FSEL + Flash memory selection This bit selects + the Flash memory to be addressed in single flash mode + (when DFM = 0). This bit can be modified only when + BUSY = 0. This bit is ignored when DFM = + 1. + 7 + 1 + + + FTHRES + FIFO threshold level Defines, in + indirect mode, the threshold number of bytes in the + FIFO that will cause the FIFO threshold flag (FTF, + QUADSPI_SR[2]) to be set. In indirect write mode + (FMODE = 00): ... In indirect read mode (FMODE = 01): + ... If DMAEN = 1, then the DMA controller for the + corresponding channel must be disabled before + changing the FTHRES value. + 8 + 5 + + + TEIE + Transfer error interrupt enable This bit + enables the transfer error interrupt. + 16 + 1 + + + TCIE + Transfer complete interrupt enable This + bit enables the transfer complete + interrupt. + 17 + 1 + + + FTIE + FIFO threshold interrupt enable This bit + enables the FIFO threshold interrupt. + 18 + 1 + + + SMIE + Status match interrupt enable This bit + enables the status match interrupt. + 19 + 1 + + + TOIE + TimeOut interrupt enable This bit + enables the TimeOut interrupt. + 20 + 1 + + + APMS + Automatic poll mode stop This bit + determines if automatic polling is stopped after a + match. This bit can be modified only when BUSY = + 0. + 22 + 1 + + + PMM + Polling match mode This bit indicates + which method should be used for determining a match + during automatic polling mode. This bit can be + modified only when BUSY = 0. + 23 + 1 + + + PRESCALER + clock prescaler + 24 + 8 + + + + + DCR + DCR + QUADSPI device configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + CKMODE + indicates the level that clk takes + between command + 0 + 1 + + + CSHT + Chip select high time CSHT+1 defines the + minimum number of CLK cycles which the chip select + (nCS) must remain high between commands issued to the + Flash memory. ... This field can be modified only + when BUSY = 0. + 8 + 3 + + + FSIZE + Flash memory size This field defines the + size of external memory using the following formula: + Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 + is effectively the number of address bits required to + address the Flash memory. The Flash memory capacity + can be up to 4GB (addressed using 32 bits) in + indirect mode, but the addressable space in + memory-mapped mode is limited to 256MB. If DFM = 1, + FSIZE indicates the total capacity of the two Flash + memories together. This field can be modified only + when BUSY = 0. + 16 + 5 + + + + + SR + SR + QUADSPI status register + 0x8 + 0x20 + read-only + 0x00000000 + + + TEF + Transfer error flag This bit is set in + indirect mode when an invalid address is being + accessed in indirect mode. It is cleared by writing 1 + to CTEF. + 0 + 1 + + + TCF + Transfer complete flag This bit is set + in indirect mode when the programmed number of data + has been transferred or in any mode when the transfer + has been aborted.It is cleared by writing 1 to + CTCF. + 1 + 1 + + + FTF + FIFO threshold flag In indirect mode, + this bit is set when the FIFO threshold has been + reached, or if there is any data left in the FIFO + after reads from the Flash memory are complete. It is + cleared automatically as soon as threshold condition + is no longer true. In automatic polling mode this bit + is set every time the status register is read, and + the bit is cleared when the data register is + read. + 2 + 1 + + + SMF + Status match flag This bit is set in + automatic polling mode when the unmasked received + data matches the corresponding bits in the match + register (QUADSPI_PSMAR). It is cleared by writing 1 + to CSMF. + 3 + 1 + + + TOF + Timeout flag This bit is set when + timeout occurs. It is cleared by writing 1 to + CTOF. + 4 + 1 + + + BUSY + Busy This bit is set when an operation + is on going. This bit clears automatically when the + operation with the Flash memory is finished and the + FIFO is empty. + 5 + 1 + + + FLEVEL + FIFO level This field gives the number + of valid bytes which are being held in the FIFO. + FLEVEL = 0 when the FIFO is empty, and 16 when it is + full. In memory-mapped mode and in automatic status + polling mode, FLEVEL is zero. + 8 + 6 + + + + + FCR + FCR + QUADSPI flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTEF + Clear transfer error flag Writing 1 + clears the TEF flag in the QUADSPI_SR + register + 0 + 1 + + + CTCF + Clear transfer complete flag Writing 1 + clears the TCF flag in the QUADSPI_SR + register + 1 + 1 + + + CSMF + Clear status match flag Writing 1 clears + the SMF flag in the QUADSPI_SR register + 3 + 1 + + + CTOF + Clear timeout flag Writing 1 clears the + TOF flag in the QUADSPI_SR register + 4 + 1 + + + + + DLR + DLR + QUADSPI data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length Number of data to be + retrieved (value+1) in indirect and status-polling + modes. A value no greater than 3 (indicating 4 bytes) + should be used for status-polling mode. All 1s in + indirect mode means undefined length, where QUADSPI + will continue until the end of memory, as defined by + FSIZE. 0x0000_0000: 1 byte is to be transferred + 0x0000_0001: 2 bytes are to be transferred + 0x0000_0002: 3 bytes are to be transferred + 0x0000_0003: 4 bytes are to be transferred ... + 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be + transferred 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes + are to be transferred 0xFFFF_FFFF: undefined length + -- all bytes until the end of Flash memory (as + defined by FSIZE) are to be transferred. Continue + reading indefinitely if FSIZE = 0x1F. DL[0] is stuck + at 1 in dual-flash mode (DFM = 1) even when 0 is + written to this bit, thus assuring that each access + transfers an even number of bytes. This field has no + effect when in memory-mapped mode (FMODE = 10). This + field can be written only when BUSY = + 0. + 0 + 32 + + + + + CCR + CCR + QUADSPI communication configuration + register + 0x14 + 0x20 + read-write + 0x00000000 + + + INSTRUCTION + Instruction Instruction to be send to + the external SPI device. This field can be written + only when BUSY = 0. + 0 + 8 + + + IMODE + Instruction mode This field defines the + instruction phase mode of operation: This field can + be written only when BUSY = 0. + 8 + 2 + + + ADMODE + Address mode This field defines the + address phase mode of operation: This field can be + written only when BUSY = 0. + 10 + 2 + + + ADSIZE + Address size This bit defines address + size: This field can be written only when BUSY = + 0. + 12 + 2 + + + ABMODE + Alternate bytes mode This field defines + the alternate-bytes phase mode of operation: This + field can be written only when BUSY = + 0. + 14 + 2 + + + ABSIZE + Alternate bytes size This bit defines + alternate bytes size: This field can be written only + when BUSY = 0. + 16 + 2 + + + DCYC + Number of dummy cycles This field + defines the duration of the dummy phase. In both SDR + and DDR modes, it specifies a number of CLK cycles + (0-31). This field can be written only when BUSY = + 0. + 18 + 5 + + + DMODE + Data mode This field defines the data + phases mode of operation: This field also determines + the dummy phase mode of operation. This field can be + written only when BUSY = 0. + 24 + 2 + + + FMODE + Functional mode This field defines the + QUADSPI functional mode of operation. If DMAEN = 1 + already, then the DMA controller for the + corresponding channel must be disabled before + changing the FMODE value. This field can be written + only when BUSY = 0. + 26 + 2 + + + SIOO + Send instruction only once mode See + Section15.3.11: Sending the instruction only once on + page13. This bit has no effect when IMODE = 00. This + field can be written only when BUSY = + 0. + 28 + 1 + + + DHHC + DDR hold Delay the data output by 1/4 of + the QUADSPI output clock cycle in DDR mode: This + feature is only active in DDR mode. This field can be + written only when BUSY = 0. + 30 + 1 + + + DDRM + Double data rate mode This bit sets the + DDR mode for the address, alternate byte and data + phase: This field can be written only when BUSY = + 0. + 31 + 1 + + + + + AR + AR + QUADSPI address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + [31 0]: Address Address to be send to + the external Flash memory Writes to this field are + ignored when BUSY = 0 or when FMODE = 11 + (memory-mapped mode). In dual flash mode, ADDRESS[0] + is automatically stuck to 0 as the address should + always be even + 0 + 32 + + + + + ABR + ABR + QUADSPI alternate bytes + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + Alternate Bytes Optional data to be send + to the external SPI device right after the address. + This field can be written only when BUSY = + 0. + 0 + 32 + + + + + DR + DR + QUADSPI data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data Data to be sent/received to/from + the external SPI device. In indirect write mode, data + written to this register is stored on the FIFO before + it is sent to the Flash memory during the data phase. + If the FIFO is too full, a write operation is stalled + until the FIFO has enough space to accept the amount + of data being written. In indirect read mode, reading + this register gives (via the FIFO) the data which was + received from the Flash memory. If the FIFO does not + have as many bytes as requested by the read operation + and if BUSY=1, the read operation is stalled until + enough data is present or until the transfer is + complete, whichever happens first. In automatic + polling mode, this register contains the last data + read from the Flash memory (without masking). Word, + halfword, and byte accesses to this register are + supported. In indirect write mode, a byte write adds + 1 byte to the FIFO, a halfword write 2, and a word + write 4. Similarly, in indirect read mode, a byte + read removes 1 byte from the FIFO, a halfword read 2, + and a word read 4. Accesses in indirect mode must be + aligned to the bottom of this register: a byte read + must read DATA[7:0] and a halfword read must read + DATA[15:0]. + 0 + 32 + + + + + PSMKR + PSMKR + QUADSPI polling status mask + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask Mask to be applied to the + status bytes received in polling mode. For bit n: + This field can be written only when BUSY = + 0. + 0 + 32 + + + + + PSMAR + PSMAR + QUADSPI polling status match + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match Value to be compared with + the masked status register to get a match. This field + can be written only when BUSY = 0. + 0 + 32 + + + + + PIR + PIR + QUADSPI polling interval + register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval Number of CLK cycles + between to read during automatic polling phases. This + field can be written only when BUSY = + 0. + 0 + 16 + + + + + LPTR + LPTR + QUADSPI low-power timeout + register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period After each access in + memory-mapped mode, the QUADSPI prefetches the + subsequent bytes and holds these bytes in the FIFO. + This field indicates how many CLK cycles the QUADSPI + waits after the FIFO becomes full until it raises + nCS, putting the Flash memory in a lower-consumption + state. This field can be written only when BUSY = + 0. + 0 + 16 + + + + + + + RNG + RNG + RNG + 0x48021800 + + 0x0 + 0x400 + registers + + + + CR + CR + RNG control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RNGEN + Random number generator + enable + 2 + 1 + + + IE + Interrupt enable + 3 + 1 + + + CED + Clock error detection Note: The clock + error detection can be used only when ck_rc48 or + ck_pll1_q (ck_pll1_q = 48MHz) source is selected + otherwise, CED bit must be equal to 1. The clock + error detection cannot be enabled nor disabled on the + fly when RNG peripheral is enabled, to enable or + disable CED the RNG must be disabled. + 5 + 1 + + + + + SR + SR + RNG status register + 0x4 + 0x20 + 0x00000000 + + + DRDY + Data ready Note: If IE=1 in RNG_CR, an + interrupt is generated when DRDY=1. It can rise when + the peripheral is disabled. When the output buffer + becomes empty (after reading RNG_DR), this bit + returns to 0 until a new random value is + generated. + 0 + 1 + read-only + + + CECS + Clock error current status Note: This + bit is meaningless if CED (Clock error detection) bit + in RNG_CR is equal to 1. + 1 + 1 + read-only + + + SECS + Seed error current status ** More than + 64 consecutive bits at the same value (0 or 1) ** + More than 32 consecutive alternances of 0 and 1 + (0101010101...01) + 2 + 1 + read-only + + + CEIS + Clock error interrupt status This bit is + set at the same time as CECS. It is cleared by + writing it to 0. An interrupt is pending if IE = 1 in + the RNG_CR register. Note: This bit is meaningless if + CED (Clock error detection) bit in RNG_CR is equal to + 1. + 5 + 1 + read-write + + + SEIS + Seed error interrupt status This bit is + set at the same time as SECS. It is cleared by + writing it to 0. ** More than 64 consecutive bits at + the same value (0 or 1) ** More than 32 consecutive + alternances of 0 and 1 (0101010101...01) An interrupt + is pending if IE = 1 in the RNG_CR + register. + 6 + 1 + read-write + + + + + DR + DR + The RNG_DR register is a read-only register + that delivers a 32-bit random value when read. The + content of this register is valid when DRDY= 1, even if + RNGEN=0. + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data 32-bit random data which are + valid when DRDY=1. + 0 + 32 + + + + + + + RTC + RTC + RTC + 0x58004000 + + 0x0 + 0x400 + registers + + + RTC_TAMP_STAMP_CSS_LSE + RTC tamper, timestamp + 2 + + + RTC_WKUP + RTC Wakeup interrupt + 3 + + + RTC_ALARM + RTC alarms (A and B) + 41 + + + + RTC_TR + RTC_TR + The RTC_TR is the calendar time shadow + register. This register must be written in initialization + mode only. Refer to Calendar initialization and + configuration on page9 and Reading the calendar on + page10.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x0 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + RTC_DR + RTC_DR + The RTC_DR is the calendar date shadow + register. This register must be written in initialization + mode only. Refer to Calendar initialization and + configuration on page9 and Reading the calendar on + page10.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x4 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format + 0 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + MU + Month units in BCD format + 8 + 4 + + + MT + Month tens in BCD format + 12 + 1 + + + WDU + Week day units + 13 + 3 + + + YU + Year units in BCD format + 16 + 4 + + + YT + Year tens in BCD format + 20 + 4 + + + + + RTC_CR + RTC_CR + RTC control register + 0x8 + 0x20 + 0x00000000 + + + WUCKSEL + Wakeup clock selection + 0 + 3 + read-write + + + TSEDGE + Time-stamp event active edge TSE must be + reset when TSEDGE is changed to avoid unwanted TSF + setting. + 3 + 1 + read-write + + + REFCKON + RTC_REFIN reference clock detection + enable (50 or 60Hz) Note: PREDIV_S must be + 0x00FF. + 4 + 1 + read-write + + + BYPSHAD + Bypass the shadow registers Note: If the + frequency of the APB clock is less than seven times + the frequency of RTCCLK, BYPSHAD must be set to + 1. + 5 + 1 + read-write + + + FMT + Hour format + 6 + 1 + read-write + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + WUTE + Wakeup timer enable + 10 + 1 + read-write + + + TSE + timestamp enable + 11 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + read-write + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + read-write + + + ADD1H + Add 1 hour (summer time change) When + this bit is set outside initialization mode, 1 hour + is added to the calendar time. This bit is always + read as 0. + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) + When this bit is set outside initialization mode, 1 + hour is subtracted to the calendar time if the + current hour is not 0. This bit is always read as 0. + Setting this bit has no effect when current hour is + 0. + 17 + 1 + write-only + + + BKP + Backup This bit can be written by the + user to memorize whether the daylight saving time + change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection When COE=1, + this bit selects which signal is output on RTC_CALIB. + These frequencies are valid for RTCCLK at 32.768 kHz + and prescalers at their default values (PREDIV_A=127 + and PREDIV_S=255). Refer to Section24.3.15: + Calibration clock output + 19 + 1 + read-write + + + POL + Output polarity This bit is used to + configure the polarity of RTC_ALARM + output + 20 + 1 + read-write + + + OSEL + Output selection These bits are used to + select the flag to be routed to RTC_ALARM + output + 21 + 2 + read-write + + + COE + Calibration output enable This bit + enables the RTC_CALIB output + 23 + 1 + read-write + + + ITSE + timestamp on internal event + enable + 24 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + This register is write protected (except for + RTC_ISR[13:8] bits). The write access procedure is + described in RTC register write protection on + page9. + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag This bit is set by + hardware when Alarm A values can be changed, after + the ALRAE bit has been set to 0 in RTC_CR. It is + cleared by hardware in initialization + mode. + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag This bit is set by + hardware when Alarm B values can be changed, after + the ALRBE bit has been set to 0 in RTC_CR. It is + cleared by hardware in initialization + mode. + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag This bit is set + by hardware up to 2 RTCCLK cycles after the WUTE bit + has been set to 0 in RTC_CR, and is cleared up to 2 + RTCCLK cycles after the WUTE bit has been set to 1. + The wakeup timer values can be changed when WUTE bit + is cleared and WUTWF is set. + 2 + 1 + read-only + + + SHPF + Shift operation pending This flag is set + by hardware as soon as a shift operation is initiated + by a write to the RTC_SHIFTR register. It is cleared + by hardware when the corresponding shift operation + has been executed. Writing to the SHPF bit has no + effect. + 3 + 1 + read-only + + + INITS + Initialization status flag This bit is + set by hardware when the calendar year field is + different from 0 (Backup domain reset + state). + 4 + 1 + read-only + + + RSF + Registers synchronization flag This bit + is set by hardware each time the calendar registers + are copied into the shadow registers (RTC_SSRx, + RTC_TRx and RTC_DRx). This bit is cleared by hardware + in initialization mode, while a shift operation is + pending (SHPF=1), or when in bypass shadow register + mode (BYPSHAD=1). This bit can also be cleared by + software. It is cleared either by software or by + hardware in initialization mode. + 5 + 1 + read-write + + + INITF + Initialization flag When this bit is set + to 1, the RTC is in initialization state, and the + time, date and prescaler registers can be + updated. + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag This flag is set by + hardware when the time/date registers (RTC_TR and + RTC_DR) match the Alarm A register (RTC_ALRMAR). This + flag is cleared by software by writing + 0. + 8 + 1 + read-write + + + ALRBF + Alarm B flag This flag is set by + hardware when the time/date registers (RTC_TR and + RTC_DR) match the Alarm B register (RTC_ALRMBR). This + flag is cleared by software by writing + 0. + 9 + 1 + read-write + + + WUTF + Wakeup timer flag This flag is set by + hardware when the wakeup auto-reload counter reaches + 0. This flag is cleared by software by writing 0. + This flag must be cleared by software at least 1.5 + RTCCLK periods before WUTF is set to 1 + again. + 10 + 1 + read-write + + + TSF + Time-stamp flag This flag is set by + hardware when a time-stamp event occurs. This flag is + cleared by software by writing 0. + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag This flag is + set by hardware when a time-stamp event occurs while + TSF is already set. This flag is cleared by software + by writing 0. It is recommended to check and then + clear TSOVF only after clearing the TSF bit. + Otherwise, an overflow might not be noticed if a + time-stamp event occurs immediately before the TSF + bit is cleared. + 12 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag This flag is + set by hardware when a tamper detection event is + detected on the RTC_TAMP1 input. It is cleared by + software writing 0 + 13 + 1 + read-write + + + TAMP2F + RTC_TAMP2 detection flag This flag is + set by hardware when a tamper detection event is + detected on the RTC_TAMP2 input. It is cleared by + software writing 0 + 14 + 1 + read-write + + + TAMP3F + RTC_TAMP3 detection flag This flag is + set by hardware when a tamper detection event is + detected on the RTC_TAMP3 input. It is cleared by + software writing 0 + 15 + 1 + read-write + + + RECALPF + Recalibration pending Flag The RECALPF + status flag is automatically set to 1 when software + writes to the RTC_CALR register, indicating that the + RTC_CALR register is blocked. When the new + calibration settings are taken into account, this bit + returns to 0. Refer to Re-calibration + on-the-fly. + 16 + 1 + read-only + + + ITSF + Internal tTime-stamp flag + 17 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + This register must be written in + initialization mode only. The initialization must be + performed in two separate write accesses. Refer to + Calendar initialization and configuration on page9.This + register is write protected. The write access procedure + is described in RTC register write protection on + page9. + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor This is the + synchronous division factor: ck_spre frequency = + ck_apre frequency/(PREDIV_S+1) + 0 + 15 + + + PREDIV_A + Asynchronous prescaler factor This is + the asynchronous division factor: ck_apre frequency = + RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + + + + + RTC_WUTR + RTC_WUTR + This register can be written only when WUTWF + is set to 1 in RTC_ISR.This register is write protected. + The write access procedure is described in RTC register + write protection on page9. + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits When the + wakeup timer is enabled (WUTE set to 1), the WUTF + flag is set every (WUT[15:0] + 1) ck_wut cycles. The + ck_wut period is selected through WUCKSEL[2:0] bits + of the RTC_CR register When WUCKSEL[2] = 1, the + wakeup timer becomes 17-bits and WUCKSEL[1] + effectively becomes WUT[16] the most-significant bit + to be reloaded into the timer. The first assertion of + WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. + Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 + (RTCCLK/2) is forbidden. + 0 + 16 + + + + + RTC_ALRMAR + RTC_ALRMAR + This register can be written only when + ALRAWF is set to 1 in RTC_ISR, or in initialization + mode.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD + format. + 0 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + HU + Hour units in BCD format. + 16 + 4 + + + HT + Hour tens in BCD format. + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + DU + Date units or day in BCD + format. + 24 + 4 + + + DT + Date tens in BCD format. + 28 + 2 + + + WDSEL + Week day selection + 30 + 1 + + + MSK4 + Alarm A date mask + 31 + 1 + + + + + RTC_ALRMBR + RTC_ALRMBR + This register can be written only when + ALRBWF is set to 1 in RTC_ISR, or in initialization + mode.This register is write protected. The write access + procedure is described in RTC register write protection + on page9. + 0x20 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + DU + Date units or day in BCD + format + 24 + 4 + + + DT + Date tens in BCD format + 28 + 2 + + + WDSEL + Week day selection + 30 + 1 + + + MSK4 + Alarm B date mask + 31 + 1 + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key This byte is + written by software. Reading this byte always returns + 0x00. Refer to RTC register write protection for a + description of how to unlock RTC register write + protection. + 0 + 8 + + + + + RTC_SSR + RTC_SSR + RTC sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value SS[15:0] is the value + in the synchronous prescaler counter. The fraction of + a second is given by the formula below: Second + fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS + can be larger than PREDIV_S only after a shift + operation. In that case, the correct time/date is one + second less than as indicated by + RTC_TR/RTC_DR. + 0 + 16 + + + + + RTC_SHIFTR + RTC_SHIFTR + This register is write protected. The write + access procedure is described in RTC register write + protection on page9. + 0x2C + 0x20 + write-only + 0x00000000 + + + SUBFS + Subtract a fraction of a second These + bits are write only and is always read as zero. + Writing to this bit has no effect when a shift + operation is pending (when SHPF=1, in RTC_ISR). The + value which is written to SUBFS is added to the + synchronous prescaler counter. Since this counter + counts down, this operation effectively subtracts + from (delays) the clock by: Delay (seconds) = SUBFS / + (PREDIV_S + 1) A fraction of a second can effectively + be added to the clock (advancing the clock) when the + ADD1S function is used in conjunction with SUBFS, + effectively advancing the clock by: Advance (seconds) + = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to + SUBFS causes RSF to be cleared. Software can then + wait until RSF=1 to be sure that the shadow registers + have been updated with the shifted + time. + 0 + 15 + + + ADD1S + Add one second This bit is write only + and is always read as zero. Writing to this bit has + no effect when a shift operation is pending (when + SHPF=1, in RTC_ISR). This function is intended to be + used with SUBFS (see description below) in order to + effectively add a fraction of a second to the clock + in an atomic operation. + 31 + 1 + + + + + RTC_TSTR + RTC_TSTR + The content of this register is valid only + when TSF is set to 1 in RTC_ISR. It is cleared when TSF + bit is reset. + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD + format. + 0 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + HU + Hour units in BCD format. + 16 + 4 + + + HT + Hour tens in BCD format. + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + RTC_TSDR + RTC_TSDR + The content of this register is valid only + when TSF is set to 1 in RTC_ISR. It is cleared when TSF + bit is reset. + 0x34 + 0x20 + read-only + 0x00000000 + + + DU + Date units in BCD format + 0 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + MU + Month units in BCD format + 8 + 4 + + + MT + Month tens in BCD format + 12 + 1 + + + WDU + Week day units + 13 + 3 + + + + + RTC_TSSSR + RTC_TSSSR + The content of this register is valid only + when RTC_ISR/TSF is set. It is cleared when the + RTC_ISR/TSF bit is reset. + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value SS[15:0] is the value + of the synchronous prescaler counter when the + timestamp event occurred. + 0 + 16 + + + + + RTC_CALR + RTC_CALR + This register is write protected. The write + access procedure is described in RTC register write + protection on page9. + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus The frequency of the + calendar is reduced by masking CALM out of 220 RTCCLK + pulses (32 seconds if the input frequency is 32768 + Hz). This decreases the frequency of the calendar + with a resolution of 0.9537 ppm. To increase the + frequency of the calendar, this feature should be + used in conjunction with CALP. See Section24.3.12: + RTC smooth digital calibration on + page13. + 0 + 9 + + + CALW16 + Use a 16-second calibration cycle period + When CALW16 is set to 1, the 16-second calibration + cycle period is selected.This bit must not be set to + 1 if CALW8=1. Note: CALM[0] is stuck at 0 when + CALW16= 1. Refer to Section24.3.12: RTC smooth + digital calibration. + 13 + 1 + + + CALW8 + Use an 8-second calibration cycle period + When CALW8 is set to 1, the 8-second calibration + cycle period is selected. Note: CALM[1:0] are stuck + at 00; when CALW8= 1. Refer to Section24.3.12: RTC + smooth digital calibration. + 14 + 1 + + + CALP + Increase frequency of RTC by 488.5 ppm + This feature is intended to be used in conjunction + with CALM, which lowers the frequency of the calendar + with a fine resolution. if the input frequency is + 32768 Hz, the number of RTCCLK pulses added during a + 32-second window is calculated as follows: (512 * + CALP) - CALM. Refer to Section24.3.12: RTC smooth + digital calibration. + 15 + 1 + + + + + RTC_TAMPCR + RTC_TAMPCR + RTC tamper and alternate function + configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + RTC_TAMP1 input detection + enable + 0 + 1 + + + TAMP1TRG + Active level for RTC_TAMP1 input If + TAMPFLT != 00 if TAMPFLT = 00: + 1 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP2E + RTC_TAMP2 input detection + enable + 3 + 1 + + + TAMP2TRG + Active level for RTC_TAMP2 input if + TAMPFLT != 00: if TAMPFLT = 00: + 4 + 1 + + + TAMP3E + RTC_TAMP3 detection enable + 5 + 1 + + + TAMP3TRG + Active level for RTC_TAMP3 input if + TAMPFLT != 00: if TAMPFLT = 00: + 6 + 1 + + + TAMPTS + Activate timestamp on tamper detection + event TAMPTS is valid even if TSE=0 in the RTC_CR + register. + 7 + 1 + + + TAMPFREQ + Tamper sampling frequency Determines the + frequency at which each of the RTC_TAMPx inputs are + sampled. + 8 + 3 + + + TAMPFLT + RTC_TAMPx filter count These bits + determines the number of consecutive samples at the + specified level (TAMP*TRG) needed to activate a + Tamper event. TAMPFLT is valid for each of the + RTC_TAMPx inputs. + 11 + 2 + + + TAMPPRCH + RTC_TAMPx precharge duration These bit + determines the duration of time during which the + pull-up/is activated before each sample. TAMPPRCH is + valid for each of the RTC_TAMPx inputs. + 13 + 2 + + + TAMPPUDIS + RTC_TAMPx pull-up disable This bit + determines if each of the RTC_TAMPx pins are + pre-charged before each sample. + 15 + 1 + + + TAMP1IE + Tamper 1 interrupt enable + 16 + 1 + + + TAMP1NOERASE + Tamper 1 no erase + 17 + 1 + + + TAMP1MF + Tamper 1 mask flag + 18 + 1 + + + TAMP2IE + Tamper 2 interrupt enable + 19 + 1 + + + TAMP2NOERASE + Tamper 2 no erase + 20 + 1 + + + TAMP2MF + Tamper 2 mask flag + 21 + 1 + + + TAMP3IE + Tamper 3 interrupt enable + 22 + 1 + + + TAMP3NOERASE + Tamper 3 no erase + 23 + 1 + + + TAMP3MF + Tamper 3 mask flag + 24 + 1 + + + + + RTC_ALRMASSR + RTC_ALRMASSR + This register can be written only when ALRAE + is reset in RTC_CR register, or in initialization + mode.This register is write protected. The write access + procedure is described in RTC register write protection + on page9 + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value This value is compared + with the contents of the synchronous prescaler + counter to determine if Alarm A is to be activated. + Only bits 0 up MASKSS-1 are compared. + 0 + 15 + + + MASKSS + Mask the most-significant bits starting + at this bit ... The overflow bits of the synchronous + counter (bits 15) is never compared. This bit can be + different from 0 only after a shift + operation. + 24 + 4 + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + This register can be written only when ALRBE + is reset in RTC_CR register, or in initialization + mode.This register is write protected.The write access + procedure is described in Section: RTC register write + protection. + 0x48 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value This value is compared + with the contents of the synchronous prescaler + counter to determine if Alarm B is to be activated. + Only bits 0 up to MASKSS-1 are + compared. + 0 + 15 + + + MASKSS + Mask the most-significant bits starting + at this bit ... The overflow bits of the synchronous + counter (bits 15) is never compared. This bit can be + different from 0 only after a shift + operation. + 24 + 4 + + + + + RTC_BKP0R + RTC_BKP0R + RTC backup registers + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP1R + RTC_BKP1R + RTC backup registers + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP2R + RTC_BKP2R + RTC backup registers + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP3R + RTC_BKP3R + RTC backup registers + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP4R + RTC_BKP4R + RTC backup registers + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP5R + RTC_BKP5R + RTC backup registers + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP6R + RTC_BKP6R + RTC backup registers + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP7R + RTC_BKP7R + RTC backup registers + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP8R + RTC_BKP8R + RTC backup registers + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP9R + RTC_BKP9R + RTC backup registers + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP10R + RTC_BKP10R + RTC backup registers + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP11R + RTC_BKP11R + RTC backup registers + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP12R + RTC_BKP12R + RTC backup registers + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP13R + RTC_BKP13R + RTC backup registers + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP14R + RTC_BKP14R + RTC backup registers + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP15R + RTC_BKP15R + RTC backup registers + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_OR + RTC_OR + RTC option register + 0x4C + 0x20 + read-write + 0x00000000 + + + RTC_ALARM_TYPE + RTC_ALARM output type on + PC13 + 0 + 1 + + + RTC_OUT_RMP + RTC_OUT remap + 1 + 1 + + + + + RTC_BKP16R + RTC_BKP16R + RTC backup registers + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP17R + RTC_BKP17R + RTC backup registers + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP18R + RTC_BKP18R + RTC backup registers + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP19R + RTC_BKP19R + RTC backup registers + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP20R + RTC_BKP20R + RTC backup registers + 0xA0 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP21R + RTC_BKP21R + RTC backup registers + 0xA4 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP22R + RTC_BKP22R + RTC backup registers + 0xA8 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP23R + RTC_BKP23R + RTC backup registers + 0xAC + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP24R + RTC_BKP24R + RTC backup registers + 0xB0 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP25R + RTC_BKP25R + RTC backup registers + 0xB4 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP26R + RTC_BKP26R + RTC backup registers + 0xB8 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP27R + RTC_BKP27R + RTC backup registers + 0xBC + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP28R + RTC_BKP28R + RTC backup registers + 0xC0 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP29R + RTC_BKP29R + RTC backup registers + 0xC4 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP30R + RTC_BKP30R + RTC backup registers + 0xC8 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + RTC_BKP31R + RTC_BKP31R + RTC backup registers + 0xCC + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data + to and from these registers. They are powered-on by + VBAT when VDD is switched off, so that they are not + reset by System reset, and their contents remain + valid when the device operates in low-power mode. + This register is reset on a tamper detection event, + as long as TAMPxF=1. or when the Flash readout + protection is disabled. + 0 + 32 + + + + + + + SAI4 + SAI + SAI + 0x58005400 + + 0x0 + 0x400 + registers + + + SAI4 + SAI4 global interrupt + 146 + + + + SAI_GCR + SAI_GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCOUT + Synchronization outputs These bits are + set and cleared by software. + 4 + 2 + + + SYNCIN + Synchronization inputs + 0 + 2 + + + + + SAI_ACR1 + SAI_ACR1 + Configuration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MODE + SAIx audio block mode + immediately + 0 + 2 + + + PRTCFG + Protocol configuration. These bits are + set and cleared by software. These bits have to be + configured when the audio block is + disabled. + 2 + 2 + + + DS + Data size. These bits are set and + cleared by software. These bits are ignored when the + SPDIF protocols are selected (bit PRTCFG[1:0]), + because the frame and the data size are fixed in such + case. When the companding mode is selected through + COMP[1:0] bits, DS[1:0] are ignored since the data + size is fixed to 8 bits by the algorithm. These bits + must be configured when the audio block is + disabled. + 5 + 3 + + + LSBFIRST + Least significant bit first. This bit is + set and cleared by software. It must be configured + when the audio block is disabled. This bit has no + meaning in AC97 audio protocol since AC97 data are + always transferred with the MSB first. This bit has + no meaning in SPDIF audio protocol since in SPDIF + data are always transferred with LSB + first. + 8 + 1 + + + CKSTR + Clock strobing edge. This bit is set and + cleared by software. It must be configured when the + audio block is disabled. This bit has no meaning in + SPDIF audio protocol. + 9 + 1 + + + SYNCEN + Synchronization enable. These bits are + set and cleared by software. They must be configured + when the audio sub-block is disabled. Note: The audio + sub-block should be configured as asynchronous when + SPDIF mode is enabled. + 10 + 2 + + + MONO + Mono mode. This bit is set and cleared + by software. It is meaningful only when the number of + slots is equal to 2. When the mono mode is selected, + slot 0 data are duplicated on slot 1 when the audio + block operates as a transmitter. In reception mode, + the slot1 is discarded and only the data received + from slot 0 are stored. Refer to Section: Mono/stereo + mode for more details. + 12 + 1 + + + OUTDRIV + Output drive. This bit is set and + cleared by software. Note: This bit has to be set + before enabling the audio block and after the audio + block configuration. + 13 + 1 + + + SAIXEN + Audio block enable where x is A or B. + This bit is set by software. To switch off the audio + block, the application software must program this bit + to 0 and poll the bit till it reads back 0, meaning + that the block is completely disabled. Before setting + this bit to 1, check that it is set to 0, otherwise + the enable command will not be taken into account. + This bit allows to control the state of SAIx audio + block. If it is disabled when an audio frame transfer + is ongoing, the ongoing transfer completes and the + cell is fully disabled at the end of this audio frame + transfer. Note: When SAIx block is configured in + master mode, the clock must be present on the input + of SAIx before setting SAIXEN bit. + 16 + 1 + + + DMAEN + DMA enable. This bit is set and cleared + by software. Note: Since the audio block defaults to + operate as a transmitter after reset, the MODE[1:0] + bits must be configured before setting DMAEN to avoid + a DMA request in receiver mode. + 17 + 1 + + + NOMCK + No divider + 19 + 1 + + + MCKDIV + Master clock divider. These bits are set + and cleared by software. These bits are meaningless + when the audio block operates in slave mode. They + have to be configured when the audio block is + disabled. Others: the master clock frequency is + calculated accordingly to the following + formula: + 20 + 4 + + + OSR + Oversampling ratio for master + clock + 26 + 1 + + + + + SAI_ACR2 + SAI_ACR2 + Configuration register 2 + 0x8 + 0x20 + 0x00000000 + + + FTH + FIFO threshold. This bit is set and + cleared by software. + 0 + 3 + read-write + + + FFLUSH + FIFO flush. This bit is set by software. + It is always read as 0. This bit should be configured + when the SAI is disabled. + 3 + 1 + write-only + + + TRIS + Tristate management on data line. This + bit is set and cleared by software. It is meaningful + only if the audio block is configured as a + transmitter. This bit is not used when the audio + block is configured in SPDIF mode. It should be + configured when SAI is disabled. Refer to Section: + Output data line management on an inactive slot for + more details. + 4 + 1 + read-write + + + MUTE + Mute. This bit is set and cleared by + software. It is meaningful only when the audio block + operates as a transmitter. The MUTE value is linked + to value of MUTEVAL if the number of slots is lower + or equal to 2, or equal to 0 if it is greater than 2. + Refer to Section: Mute mode for more details. Note: + This bit is meaningless and should not be used for + SPDIF audio blocks. + 5 + 1 + read-write + + + MUTEVAL + Mute value. This bit is set and cleared + by software.It must be written before enabling the + audio block: SAIXEN. This bit is meaningful only when + the audio block operates as a transmitter, the number + of slots is lower or equal to 2 and the MUTE bit is + set. If more slots are declared, the bit value sent + during the transmission in mute mode is equal to 0, + whatever the value of MUTEVAL. if the number of slot + is lower or equal to 2 and MUTEVAL = 1, the MUTE + value transmitted for each slot is the one sent + during the previous frame. Refer to Section: Mute + mode for more details. Note: This bit is meaningless + and should not be used for SPDIF audio + blocks. + 6 + 1 + read-write + + + MUTECNT + Mute counter. These bits are set and + cleared by software. They are used only in reception + mode. The value set in these bits is compared to the + number of consecutive mute frames detected in + reception. When the number of mute frames is equal to + this value, the flag MUTEDET will be set and an + interrupt will be generated if bit MUTEDETIE is set. + Refer to Section: Mute mode for more + details. + 7 + 6 + read-write + + + CPL + Complement bit. This bit is set and + cleared by software. It defines the type of + complement to be used for companding mode Note: This + bit has effect only when the companding mode is -Law + algorithm or A-Law algorithm. + 13 + 1 + read-write + + + COMP + Companding mode. These bits are set and + cleared by software. The -Law and the A-Law log are a + part of the CCITT G.711 recommendation, the type of + complement that will be used depends on CPL bit. The + data expansion or data compression are determined by + the state of bit MODE[0]. The data compression is + applied if the audio block is configured as a + transmitter. The data expansion is automatically + applied when the audio block is configured as a + receiver. Refer to Section: Companding mode for more + details. Note: Companding mode is applicable only + when TDM is selected. + 14 + 2 + read-write + + + + + SAI_AFRCR + SAI_AFRCR + This register has no meaning in AC97 and + SPDIF audio protocol + 0xC + 0x20 + 0x00000007 + + + FRL + Frame length. These bits are set and + cleared by software. They define the audio frame + length expressed in number of SCK clock cycles: the + number of bits in the frame is equal to FRL[7:0] + 1. + The minimum number of bits to transfer in an audio + frame must be equal to 8, otherwise the audio block + will behaves in an unexpected way. This is the case + when the data size is 8 bits and only one slot 0 is + defined in NBSLOT[4:0] of SAI_xSLOTR register + (NBSLOT[3:0] = 0000). In master mode, if the master + clock (available on MCLK_x pin) is used, the frame + length should be aligned with a number equal to a + power of 2, ranging from 8 to 256. When the master + clock is not used (NODIV = 1), it is recommended to + program the frame length to an value ranging from 8 + to 256. These bits are meaningless and are not used + in AC97 or SPDIF audio block + configuration. + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length. These bits are set and cleared by software. + They specify the length in number of bit clock (SCK) + + 1 (FSALL[6:0] + 1) of the active level of the FS + signal in the audio frame These bits are meaningless + and are not used in AC97 or SPDIF audio block + configuration. They must be configured when the audio + block is disabled. + 8 + 7 + read-write + + + FSDEF + Frame synchronization definition. This + bit is set and cleared by software. When the bit is + set, the number of slots defined in the SAI_xSLOTR + register has to be even. It means that half of this + number of slots will be dedicated to the left channel + and the other slots for the right channel (e.g: this + bit has to be set for I2S or MSB/LSB-justified + protocols...). This bit is meaningless and is not + used in AC97 or SPDIF audio block configuration. It + must be configured when the audio block is + disabled. + 16 + 1 + read-only + + + FSPOL + Frame synchronization polarity. This bit + is set and cleared by software. It is used to + configure the level of the start of frame on the FS + signal. It is meaningless and is not used in AC97 or + SPDIF audio block configuration. This bit must be + configured when the audio block is + disabled. + 17 + 1 + read-write + + + FSOFF + Frame synchronization offset. This bit + is set and cleared by software. It is meaningless and + is not used in AC97 or SPDIF audio block + configuration. This bit must be configured when the + audio block is disabled. + 18 + 1 + read-write + + + + + SAI_ASLOTR + SAI_ASLOTR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x10 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset These bits are set and + cleared by software. The value set in this bitfield + defines the position of the first data transfer bit + in the slot. It represents an offset value. In + transmission mode, the bits outside the data field + are forced to 0. In reception mode, the extra + received bits are discarded. These bits must be set + when the audio block is disabled. They are ignored in + AC97 or SPDIF mode. + 0 + 5 + + + SLOTSZ + Slot size This bits is set and cleared + by software. The slot size must be higher or equal to + the data size. If this condition is not respected, + the behavior of the SAI will be undetermined. Refer + to Section: Output data line management on an + inactive slot for information on how to drive SD + line. These bits must be set when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 6 + 2 + + + NBSLOT + Number of slots in an audio frame. These + bits are set and cleared by software. The value set + in this bitfield represents the number of slots + 1 + in the audio frame (including the number of inactive + slots). The maximum number of slots is 16. The number + of slots should be even if FSDEF bit in the SAI_xFRCR + register is set. The number of slots must be + configured when the audio block is disabled. They are + ignored in AC97 or SPDIF mode. + 8 + 4 + + + SLOTEN + Slot enable. These bits are set and + cleared by software. Each SLOTEN bit corresponds to a + slot position from 0 to 15 (maximum 16 slots). The + slot must be enabled when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 16 + 16 + + + + + SAI_AIM + SAI_AIM + Interrupt mask register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the OVRUDR bit in + the SAI_xSR register is set. + 0 + 1 + + + MUTEDETIE + Mute detection interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the MUTEDET bit in + the SAI_xSR register is set. This bit has a meaning + only if the audio block is configured in receiver + mode. + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable. This bit is set and cleared by software. This + bit is taken into account only if the audio block is + configured as a master (MODE[1] = 0) and NODIV = 0. + It generates an interrupt if the WCKCFG flag in the + SAI_xSR register is set. Note: This bit is used only + in TDM mode and is meaningless in other + modes. + 2 + 1 + + + FREQIE + FIFO request interrupt enable. This bit + is set and cleared by software. When this bit is set, + an interrupt is generated if the FREQ bit in the + SAI_xSR register is set. Since the audio block + defaults to operate as a transmitter after reset, the + MODE bit must be configured before setting FREQIE to + avoid a parasitic interruption in receiver + mode, + 3 + 1 + + + CNRDYIE + Codec not ready interrupt enable (AC97). + This bit is set and cleared by software. When the + interrupt is enabled, the audio block detects in the + slot 0 (tag0) of the AC97 frame if the Codec + connected to this line is ready or not. If it is not + ready, the CNRDY flag in the SAI_xSR register is set + and an interruption i generated. This bit has a + meaning only if the AC97 mode is selected through + PRTCFG[1:0] bits and the audio block is operates as a + receiver. + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable. This bit is set and + cleared by software. When this bit is set, an + interrupt will be generated if the AFSDET bit in the + SAI_xSR register is set. This bit is meaningless in + AC97, SPDIF mode or when the audio block operates as + a master. + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable. This bit is set and cleared by + software. When this bit is set, an interrupt will be + generated if the LFSDET bit is set in the SAI_xSR + register. This bit is meaningless in AC97, SPDIF mode + or when the audio block operates as a + master. + 6 + 1 + + + + + SAI_ASR + SAI_ASR + Status register + 0x18 + 0x20 + read-only + 0x00000008 + + + OVRUDR + Overrun / underrun. This bit is read + only. The overrun and underrun conditions can occur + only when the audio block is configured as a receiver + and a transmitter, respectively. It can generate an + interrupt if OVRUDRIE bit is set in SAI_xIM register. + This flag is cleared when the software sets COVRUDR + bit in SAI_xCLRFR register. + 0 + 1 + + + MUTEDET + Mute detection. This bit is read only. + This flag is set if consecutive 0 values are received + in each slot of a given audio frame and for a + consecutive number of audio frames (set in the + MUTECNT bit in the SAI_xCR2 register). It can + generate an interrupt if MUTEDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets bit CMUTEDET in the SAI_xCLRFR + register. + 1 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit + is read only. This bit is used only when the audio + block operates in master mode (MODE[1] = 0) and NODIV + = 0. It can generate an interrupt if WCKCFGIE bit is + set in SAI_xIM register. This flag is cleared when + the software sets CWCKCFG bit in SAI_xCLRFR + register. + 2 + 1 + + + FREQ + FIFO request. This bit is read only. The + request depends on the audio block configuration: If + the block is configured in transmission mode, the + FIFO request is related to a write request operation + in the SAI_xDR. If the block configured in reception, + the FIFO request related to a read request operation + from the SAI_xDR. This flag can generate an interrupt + if FREQIE bit is set in SAI_xIM + register. + 3 + 1 + + + CNRDY + Codec not ready. This bit is read only. + This bit is used only when the AC97 audio protocol is + selected in the SAI_xCR1 register and configured in + receiver mode. It can generate an interrupt if + CNRDYIE bit is set in SAI_xIM register. This flag is + cleared when the software sets CCNRDY bit in + SAI_xCLRFR register. + 4 + 1 + + + AFSDET + Anticipated frame synchronization + detection. This bit is read only. This flag can be + set only if the audio block is configured in slave + mode. It is not used in AC97or SPDIF mode. It can + generate an interrupt if AFSDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets CAFSDET bit in SAI_xCLRFR + register. + 5 + 1 + + + LFSDET + Late frame synchronization detection. + This bit is read only. This flag can be set only if + the audio block is configured in slave mode. It is + not used in AC97 or SPDIF mode. It can generate an + interrupt if LFSDETIE bit is set in the SAI_xIM + register. This flag is cleared when the software sets + bit CLFSDET in SAI_xCLRFR register + 6 + 1 + + + FLVL + FIFO level threshold. This bit is read + only. The FIFO level threshold flag is managed only + by hardware and its setting depends on SAI block + configuration (transmitter or receiver mode). If the + SAI block is configured as transmitter: If SAI block + is configured as receiver: + 16 + 3 + + + + + SAI_ACLRFR + SAI_ACLRFR + Clear flag register + 0x1C + 0x20 + write-only + 0x00000000 + + + COVRUDR + Clear overrun / underrun. This bit is + write only. Programming this bit to 1 clears the + OVRUDR flag in the SAI_xSR register. Reading this bit + always returns the value 0. + 0 + 1 + + + CMUTEDET + Mute detection flag. This bit is write + only. Programming this bit to 1 clears the MUTEDET + flag in the SAI_xSR register. Reading this bit always + returns the value 0. + 1 + 1 + + + CWCKCFG + Clear wrong clock configuration flag. + This bit is write only. Programming this bit to 1 + clears the WCKCFG flag in the SAI_xSR register. This + bit is used only when the audio block is set as + master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 + register. Reading this bit always returns the value + 0. + 2 + 1 + + + CCNRDY + Clear Codec not ready flag. This bit is + write only. Programming this bit to 1 clears the + CNRDY flag in the SAI_xSR register. This bit is used + only when the AC97 audio protocol is selected in the + SAI_xCR1 register. Reading this bit always returns + the value 0. + 4 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the AFSDET flag in the SAI_xSR + register. It is not used in AC97or SPDIF mode. + Reading this bit always returns the value + 0. + 5 + 1 + + + CLFSDET + Clear late frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the LFSDET flag in the SAI_xSR + register. This bit is not used in AC97or SPDIF mode + Reading this bit always returns the value + 0. + 6 + 1 + + + + + SAI_ADR + SAI_ADR + Data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data A write to this register loads the + FIFO provided the FIFO is not full. A read from this + register empties the FIFO if the FIFO is not + empty. + 0 + 32 + + + + + SAI_BCR1 + SAI_BCR1 + Configuration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MODE + SAIx audio block mode + immediately + 0 + 2 + + + PRTCFG + Protocol configuration. These bits are + set and cleared by software. These bits have to be + configured when the audio block is + disabled. + 2 + 2 + + + DS + Data size. These bits are set and + cleared by software. These bits are ignored when the + SPDIF protocols are selected (bit PRTCFG[1:0]), + because the frame and the data size are fixed in such + case. When the companding mode is selected through + COMP[1:0] bits, DS[1:0] are ignored since the data + size is fixed to 8 bits by the algorithm. These bits + must be configured when the audio block is + disabled. + 5 + 3 + + + LSBFIRST + Least significant bit first. This bit is + set and cleared by software. It must be configured + when the audio block is disabled. This bit has no + meaning in AC97 audio protocol since AC97 data are + always transferred with the MSB first. This bit has + no meaning in SPDIF audio protocol since in SPDIF + data are always transferred with LSB + first. + 8 + 1 + + + CKSTR + Clock strobing edge. This bit is set and + cleared by software. It must be configured when the + audio block is disabled. This bit has no meaning in + SPDIF audio protocol. + 9 + 1 + + + SYNCEN + Synchronization enable. These bits are + set and cleared by software. They must be configured + when the audio sub-block is disabled. Note: The audio + sub-block should be configured as asynchronous when + SPDIF mode is enabled. + 10 + 2 + + + MONO + Mono mode. This bit is set and cleared + by software. It is meaningful only when the number of + slots is equal to 2. When the mono mode is selected, + slot 0 data are duplicated on slot 1 when the audio + block operates as a transmitter. In reception mode, + the slot1 is discarded and only the data received + from slot 0 are stored. Refer to Section: Mono/stereo + mode for more details. + 12 + 1 + + + OUTDRIV + Output drive. This bit is set and + cleared by software. Note: This bit has to be set + before enabling the audio block and after the audio + block configuration. + 13 + 1 + + + SAIXEN + Audio block enable where x is A or B. + This bit is set by software. To switch off the audio + block, the application software must program this bit + to 0 and poll the bit till it reads back 0, meaning + that the block is completely disabled. Before setting + this bit to 1, check that it is set to 0, otherwise + the enable command will not be taken into account. + This bit allows to control the state of SAIx audio + block. If it is disabled when an audio frame transfer + is ongoing, the ongoing transfer completes and the + cell is fully disabled at the end of this audio frame + transfer. Note: When SAIx block is configured in + master mode, the clock must be present on the input + of SAIx before setting SAIXEN bit. + 16 + 1 + + + DMAEN + DMA enable. This bit is set and cleared + by software. Note: Since the audio block defaults to + operate as a transmitter after reset, the MODE[1:0] + bits must be configured before setting DMAEN to avoid + a DMA request in receiver mode. + 17 + 1 + + + NOMCK + No divider + 19 + 1 + + + MCKDIV + Master clock divider. These bits are set + and cleared by software. These bits are meaningless + when the audio block operates in slave mode. They + have to be configured when the audio block is + disabled. Others: the master clock frequency is + calculated accordingly to the following + formula: + 20 + 4 + + + OSR + Oversampling ratio for master + clock + 26 + 1 + + + + + SAI_BCR2 + SAI_BCR2 + Configuration register 2 + 0x28 + 0x20 + 0x00000000 + + + FTH + FIFO threshold. This bit is set and + cleared by software. + 0 + 3 + read-write + + + FFLUSH + FIFO flush. This bit is set by software. + It is always read as 0. This bit should be configured + when the SAI is disabled. + 3 + 1 + write-only + + + TRIS + Tristate management on data line. This + bit is set and cleared by software. It is meaningful + only if the audio block is configured as a + transmitter. This bit is not used when the audio + block is configured in SPDIF mode. It should be + configured when SAI is disabled. Refer to Section: + Output data line management on an inactive slot for + more details. + 4 + 1 + read-write + + + MUTE + Mute. This bit is set and cleared by + software. It is meaningful only when the audio block + operates as a transmitter. The MUTE value is linked + to value of MUTEVAL if the number of slots is lower + or equal to 2, or equal to 0 if it is greater than 2. + Refer to Section: Mute mode for more details. Note: + This bit is meaningless and should not be used for + SPDIF audio blocks. + 5 + 1 + read-write + + + MUTEVAL + Mute value. This bit is set and cleared + by software.It must be written before enabling the + audio block: SAIXEN. This bit is meaningful only when + the audio block operates as a transmitter, the number + of slots is lower or equal to 2 and the MUTE bit is + set. If more slots are declared, the bit value sent + during the transmission in mute mode is equal to 0, + whatever the value of MUTEVAL. if the number of slot + is lower or equal to 2 and MUTEVAL = 1, the MUTE + value transmitted for each slot is the one sent + during the previous frame. Refer to Section: Mute + mode for more details. Note: This bit is meaningless + and should not be used for SPDIF audio + blocks. + 6 + 1 + read-write + + + MUTECNT + Mute counter. These bits are set and + cleared by software. They are used only in reception + mode. The value set in these bits is compared to the + number of consecutive mute frames detected in + reception. When the number of mute frames is equal to + this value, the flag MUTEDET will be set and an + interrupt will be generated if bit MUTEDETIE is set. + Refer to Section: Mute mode for more + details. + 7 + 6 + read-write + + + CPL + Complement bit. This bit is set and + cleared by software. It defines the type of + complement to be used for companding mode Note: This + bit has effect only when the companding mode is -Law + algorithm or A-Law algorithm. + 13 + 1 + read-write + + + COMP + Companding mode. These bits are set and + cleared by software. The -Law and the A-Law log are a + part of the CCITT G.711 recommendation, the type of + complement that will be used depends on CPL bit. The + data expansion or data compression are determined by + the state of bit MODE[0]. The data compression is + applied if the audio block is configured as a + transmitter. The data expansion is automatically + applied when the audio block is configured as a + receiver. Refer to Section: Companding mode for more + details. Note: Companding mode is applicable only + when TDM is selected. + 14 + 2 + read-write + + + + + SAI_BFRCR + SAI_BFRCR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x2C + 0x20 + 0x00000007 + + + FRL + Frame length. These bits are set and + cleared by software. They define the audio frame + length expressed in number of SCK clock cycles: the + number of bits in the frame is equal to FRL[7:0] + 1. + The minimum number of bits to transfer in an audio + frame must be equal to 8, otherwise the audio block + will behaves in an unexpected way. This is the case + when the data size is 8 bits and only one slot 0 is + defined in NBSLOT[4:0] of SAI_xSLOTR register + (NBSLOT[3:0] = 0000). In master mode, if the master + clock (available on MCLK_x pin) is used, the frame + length should be aligned with a number equal to a + power of 2, ranging from 8 to 256. When the master + clock is not used (NODIV = 1), it is recommended to + program the frame length to an value ranging from 8 + to 256. These bits are meaningless and are not used + in AC97 or SPDIF audio block + configuration. + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length. These bits are set and cleared by software. + They specify the length in number of bit clock (SCK) + + 1 (FSALL[6:0] + 1) of the active level of the FS + signal in the audio frame These bits are meaningless + and are not used in AC97 or SPDIF audio block + configuration. They must be configured when the audio + block is disabled. + 8 + 7 + read-write + + + FSDEF + Frame synchronization definition. This + bit is set and cleared by software. When the bit is + set, the number of slots defined in the SAI_xSLOTR + register has to be even. It means that half of this + number of slots will be dedicated to the left channel + and the other slots for the right channel (e.g: this + bit has to be set for I2S or MSB/LSB-justified + protocols...). This bit is meaningless and is not + used in AC97 or SPDIF audio block configuration. It + must be configured when the audio block is + disabled. + 16 + 1 + read-only + + + FSPOL + Frame synchronization polarity. This bit + is set and cleared by software. It is used to + configure the level of the start of frame on the FS + signal. It is meaningless and is not used in AC97 or + SPDIF audio block configuration. This bit must be + configured when the audio block is + disabled. + 17 + 1 + read-write + + + FSOFF + Frame synchronization offset. This bit + is set and cleared by software. It is meaningless and + is not used in AC97 or SPDIF audio block + configuration. This bit must be configured when the + audio block is disabled. + 18 + 1 + read-write + + + + + SAI_BSLOTR + SAI_BSLOTR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x30 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset These bits are set and + cleared by software. The value set in this bitfield + defines the position of the first data transfer bit + in the slot. It represents an offset value. In + transmission mode, the bits outside the data field + are forced to 0. In reception mode, the extra + received bits are discarded. These bits must be set + when the audio block is disabled. They are ignored in + AC97 or SPDIF mode. + 0 + 5 + + + SLOTSZ + Slot size This bits is set and cleared + by software. The slot size must be higher or equal to + the data size. If this condition is not respected, + the behavior of the SAI will be undetermined. Refer + to Section: Output data line management on an + inactive slot for information on how to drive SD + line. These bits must be set when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 6 + 2 + + + NBSLOT + Number of slots in an audio frame. These + bits are set and cleared by software. The value set + in this bitfield represents the number of slots + 1 + in the audio frame (including the number of inactive + slots). The maximum number of slots is 16. The number + of slots should be even if FSDEF bit in the SAI_xFRCR + register is set. The number of slots must be + configured when the audio block is disabled. They are + ignored in AC97 or SPDIF mode. + 8 + 4 + + + SLOTEN + Slot enable. These bits are set and + cleared by software. Each SLOTEN bit corresponds to a + slot position from 0 to 15 (maximum 16 slots). The + slot must be enabled when the audio block is + disabled. They are ignored in AC97 or SPDIF + mode. + 16 + 16 + + + + + SAI_BIM + SAI_BIM + Interrupt mask register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the OVRUDR bit in + the SAI_xSR register is set. + 0 + 1 + + + MUTEDETIE + Mute detection interrupt enable. This + bit is set and cleared by software. When this bit is + set, an interrupt is generated if the MUTEDET bit in + the SAI_xSR register is set. This bit has a meaning + only if the audio block is configured in receiver + mode. + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable. This bit is set and cleared by software. This + bit is taken into account only if the audio block is + configured as a master (MODE[1] = 0) and NODIV = 0. + It generates an interrupt if the WCKCFG flag in the + SAI_xSR register is set. Note: This bit is used only + in TDM mode and is meaningless in other + modes. + 2 + 1 + + + FREQIE + FIFO request interrupt enable. This bit + is set and cleared by software. When this bit is set, + an interrupt is generated if the FREQ bit in the + SAI_xSR register is set. Since the audio block + defaults to operate as a transmitter after reset, the + MODE bit must be configured before setting FREQIE to + avoid a parasitic interruption in receiver + mode, + 3 + 1 + + + CNRDYIE + Codec not ready interrupt enable (AC97). + This bit is set and cleared by software. When the + interrupt is enabled, the audio block detects in the + slot 0 (tag0) of the AC97 frame if the Codec + connected to this line is ready or not. If it is not + ready, the CNRDY flag in the SAI_xSR register is set + and an interruption i generated. This bit has a + meaning only if the AC97 mode is selected through + PRTCFG[1:0] bits and the audio block is operates as a + receiver. + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable. This bit is set and + cleared by software. When this bit is set, an + interrupt will be generated if the AFSDET bit in the + SAI_xSR register is set. This bit is meaningless in + AC97, SPDIF mode or when the audio block operates as + a master. + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable. This bit is set and cleared by + software. When this bit is set, an interrupt will be + generated if the LFSDET bit is set in the SAI_xSR + register. This bit is meaningless in AC97, SPDIF mode + or when the audio block operates as a + master. + 6 + 1 + + + + + SAI_BSR + SAI_BSR + Status register + 0x38 + 0x20 + read-only + 0x00000008 + + + OVRUDR + Overrun / underrun. This bit is read + only. The overrun and underrun conditions can occur + only when the audio block is configured as a receiver + and a transmitter, respectively. It can generate an + interrupt if OVRUDRIE bit is set in SAI_xIM register. + This flag is cleared when the software sets COVRUDR + bit in SAI_xCLRFR register. + 0 + 1 + + + MUTEDET + Mute detection. This bit is read only. + This flag is set if consecutive 0 values are received + in each slot of a given audio frame and for a + consecutive number of audio frames (set in the + MUTECNT bit in the SAI_xCR2 register). It can + generate an interrupt if MUTEDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets bit CMUTEDET in the SAI_xCLRFR + register. + 1 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit + is read only. This bit is used only when the audio + block operates in master mode (MODE[1] = 0) and NODIV + = 0. It can generate an interrupt if WCKCFGIE bit is + set in SAI_xIM register. This flag is cleared when + the software sets CWCKCFG bit in SAI_xCLRFR + register. + 2 + 1 + + + FREQ + FIFO request. This bit is read only. The + request depends on the audio block configuration: If + the block is configured in transmission mode, the + FIFO request is related to a write request operation + in the SAI_xDR. If the block configured in reception, + the FIFO request related to a read request operation + from the SAI_xDR. This flag can generate an interrupt + if FREQIE bit is set in SAI_xIM + register. + 3 + 1 + + + CNRDY + Codec not ready. This bit is read only. + This bit is used only when the AC97 audio protocol is + selected in the SAI_xCR1 register and configured in + receiver mode. It can generate an interrupt if + CNRDYIE bit is set in SAI_xIM register. This flag is + cleared when the software sets CCNRDY bit in + SAI_xCLRFR register. + 4 + 1 + + + AFSDET + Anticipated frame synchronization + detection. This bit is read only. This flag can be + set only if the audio block is configured in slave + mode. It is not used in AC97or SPDIF mode. It can + generate an interrupt if AFSDETIE bit is set in + SAI_xIM register. This flag is cleared when the + software sets CAFSDET bit in SAI_xCLRFR + register. + 5 + 1 + + + LFSDET + Late frame synchronization detection. + This bit is read only. This flag can be set only if + the audio block is configured in slave mode. It is + not used in AC97 or SPDIF mode. It can generate an + interrupt if LFSDETIE bit is set in the SAI_xIM + register. This flag is cleared when the software sets + bit CLFSDET in SAI_xCLRFR register + 6 + 1 + + + FLVL + FIFO level threshold. This bit is read + only. The FIFO level threshold flag is managed only + by hardware and its setting depends on SAI block + configuration (transmitter or receiver mode). If the + SAI block is configured as transmitter: If SAI block + is configured as receiver: + 16 + 3 + + + + + SAI_BCLRFR + SAI_BCLRFR + Clear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + COVRUDR + Clear overrun / underrun. This bit is + write only. Programming this bit to 1 clears the + OVRUDR flag in the SAI_xSR register. Reading this bit + always returns the value 0. + 0 + 1 + + + CMUTEDET + Mute detection flag. This bit is write + only. Programming this bit to 1 clears the MUTEDET + flag in the SAI_xSR register. Reading this bit always + returns the value 0. + 1 + 1 + + + CWCKCFG + Clear wrong clock configuration flag. + This bit is write only. Programming this bit to 1 + clears the WCKCFG flag in the SAI_xSR register. This + bit is used only when the audio block is set as + master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 + register. Reading this bit always returns the value + 0. + 2 + 1 + + + CCNRDY + Clear Codec not ready flag. This bit is + write only. Programming this bit to 1 clears the + CNRDY flag in the SAI_xSR register. This bit is used + only when the AC97 audio protocol is selected in the + SAI_xCR1 register. Reading this bit always returns + the value 0. + 4 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the AFSDET flag in the SAI_xSR + register. It is not used in AC97or SPDIF mode. + Reading this bit always returns the value + 0. + 5 + 1 + + + CLFSDET + Clear late frame synchronization + detection flag. This bit is write only. Programming + this bit to 1 clears the LFSDET flag in the SAI_xSR + register. This bit is not used in AC97or SPDIF mode + Reading this bit always returns the value + 0. + 6 + 1 + + + + + SAI_BDR + SAI_BDR + Data register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data A write to this register loads the + FIFO provided the FIFO is not full. A read from this + register empties the FIFO if the FIFO is not + empty. + 0 + 32 + + + + + SAI_PDMCR + SAI_PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDM enable + 0 + 1 + + + MICNBR + Number of microphones + 4 + 2 + + + CKEN1 + Clock enable of bitstream clock number + 1 + 8 + 1 + + + CKEN2 + Clock enable of bitstream clock number + 2 + 9 + 1 + + + CKEN3 + Clock enable of bitstream clock number + 3 + 10 + 1 + + + CKEN4 + Clock enable of bitstream clock number + 4 + 11 + 1 + + + + + SAI_PDMDLY + SAI_PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + Delay line adjust for first microphone + of pair 1 + 0 + 3 + + + DLYM1R + Delay line adjust for second microphone + of pair 1 + 4 + 3 + + + DLYM2L + Delay line for first microphone of pair + 2 + 8 + 3 + + + DLYM2R + Delay line for second microphone of pair + 2 + 12 + 3 + + + DLYM3L + Delay line for first microphone of pair + 3 + 16 + 3 + + + DLYM3R + Delay line for second microphone of pair + 3 + 20 + 3 + + + DLYM4L + Delay line for first microphone of pair + 4 + 24 + 3 + + + DLYM4R + Delay line for second microphone of pair + 4 + 28 + 3 + + + + + + + SAI1 + 0x40015800 + + SAI1 + SAI1 global interrupt + 87 + + + + SAI2 + 0x40015C00 + + SAI2 + SAI2 global interrupt + 91 + + + + SAI3 + 0x40016000 + + SAI3 + SAI3 global interrupt + 114 + + + + SDMMC1 + SDMMC1 + SDMMC + 0x52007000 + + 0x0 + 0x100 + registers + + + SDMMC1 + SDMMC global interrupt + 49 + + + SDMMC + SDMMC global interrupt + 124 + + + + POWER + POWER + SDMMC power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + SDMMC state control bits. These bits can + only be written when the SDMMC is not in the power-on + state (PWRCTRL?11). These bits are used to define the + functional state of the SDMMC signals: Any further + write will be ignored, PWRCTRL value will keep + 11. + 0 + 2 + + + VSWITCH + Voltage switch sequence start. This bit + is used to start the timing critical section of the + voltage switch sequence: + 2 + 1 + + + VSWITCHEN + Voltage switch procedure enable. This + bit can only be written by firmware when CPSM is + disabled (CPSMEN = 0). This bit is used to stop the + SDMMC_CK after the voltage switch command + response: + 3 + 1 + + + DIRPOL + Data and command direction signals + polarity selection. This bit can only be written when + the SDMMC is in the power-off state (PWRCTRL = + 00). + 4 + 1 + + + + + CLKCR + CLKCR + The SDMMC_CLKCR register controls the + SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, + and the bus width. + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock divide factor This bit can only be + written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0). This field defines the + divide factor between the input clock (SDMMCCLK) and + the output clock (SDMMC_CK): SDMMC_CK frequency = + SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: + etc.. + 0 + 10 + + + PWRSAV + Power saving configuration bit This bit + can only be written when the CPSM and DPSM are not + active (CPSMACT = 0 and DPSMACT = 0) For power + saving, the SDMMC_CK clock output can be disabled + when the bus is idle by setting PWRSAV: + 12 + 1 + + + WIDBUS + Wide bus mode enable bit This bit can + only be written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0) + 14 + 2 + + + NEGEDGE + SDMMC_CK dephasing selection bit for + data and Command. This bit can only be written when + the CPSM and DPSM are not active (CPSMACT = 0 and + DPSMACT = 0). When clock division = 1 (CLKDIV = 0), + this bit has no effect. Data and Command change on + SDMMC_CK falling edge. When clock division &gt;1 + (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK + edge occurs on SDMMCCLK rising edge. When clock + division >1 (CLKDIV > 0) & DDR = 1: - Data + changed on the SDMMCCLK falling edge succeeding a + SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK + rising edge. - Data changed on the SDMMC_CK falling + edge succeeding a SDMMC_CK edge. - SDMMC_CK edge + occurs on SDMMCCLK rising edge. + 16 + 1 + + + HWFC_EN + Hardware flow control enable This bit + can only be written when the CPSM and DPSM are not + active (CPSMACT = 0 and DPSMACT = 0) When Hardware + flow control is enabled, the meaning of the TXFIFOE + and RXFIFOF flags change, please see SDMMC status + register definition in Section56.8.11. + 17 + 1 + + + DDR + Data rate signaling selection This bit + can only be written when the CPSM and DPSM are not + active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall + only be selected with 4-bit or 8-bit wide bus mode. + (WIDBUS &gt; 00). DDR = 1 has no effect when + WIDBUS = 00 (1-bit wide bus). DDR rate shall only be + selected with clock division &gt;1. (CLKDIV + &gt; 0) + 18 + 1 + + + BUSSPEED + Bus speed mode selection between DS, HS, + SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can + only be written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0) + 19 + 1 + + + SELCLKRX + Receive clock selection. These bits can + only be written when the CPSM and DPSM are not active + (CPSMACT = 0 and DPSMACT = 0) + 20 + 2 + + + + + ARGR + ARGR + The SDMMC_ARGR register contains a 32-bit + command argument, which is sent to a card as part of a + command message. + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument. These bits can only be + written by firmware when CPSM is disabled (CPSMEN = + 0). Command argument sent to a card as part of a + command message. If a command contains an argument, + it must be loaded into this register before writing a + command to the command register. + 0 + 32 + + + + + CMDR + CMDR + The SDMMC_CMDR register contains the command + index and command type bits. The command index is sent to + a card as part of a command message. The command type + bits control the command path state machine + (CPSM). + 0xC + 0x20 + read-write + 0x00000000 + + + CMDINDEX + Command index. This bit can only be + written by firmware when CPSM is disabled (CPSMEN = + 0). The command index is sent to the card as part of + a command message. + 0 + 6 + + + CMDTRANS + The CPSM treats the command as a data + transfer command, stops the interrupt period, and + signals DataEnable to the DPSM This bit can only be + written by firmware when CPSM is disabled (CPSMEN = + 0). If this bit is set, the CPSM issues an end of + interrupt period and issues DataEnable signal to the + DPSM when the command is sent. + 6 + 1 + + + CMDSTOP + The CPSM treats the command as a Stop + Transmission command and signals Abort to the DPSM. + This bit can only be written by firmware when CPSM is + disabled (CPSMEN = 0). If this bit is set, the CPSM + issues the Abort signal to the DPSM when the command + is sent. + 7 + 1 + + + WAITRESP + Wait for response bits. This bit can + only be written by firmware when CPSM is disabled + (CPSMEN = 0). They are used to configure whether the + CPSM is to wait for a response, and if yes, which + kind of response. + 8 + 2 + + + WAITINT + CPSM waits for interrupt request. If + this bit is set, the CPSM disables command timeout + and waits for an card interrupt request (Response). + If this bit is cleared in the CPSM Wait state, will + cause the abort of the interrupt mode. + 10 + 1 + + + WAITPEND + CPSM Waits for end of data transfer + (CmdPend internal signal) from DPSM. This bit when + set, the CPSM waits for the end of data transfer + trigger before it starts sending a command. WAITPEND + is only taken into account when DTMODE = MMC stream + data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT + = 1 and DTDIR = from host to card. + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable + bit This bit is written 1 by firmware, and cleared by + hardware when the CPSM enters the Idle state. If this + bit is set, the CPSM is enabled. When DTEN = 1, no + command will be transfered nor boot procedure will be + started. CPSMEN is cleared to 0. + 12 + 1 + + + DTHOLD + Hold new data block transmission and + reception in the DPSM. If this bit is set, the DPSM + will not move from the Wait_S state to the Send state + or from the Wait_R state to the Receive + state. + 13 + 1 + + + BOOTMODE + Select the boot mode procedure to be + used. This bit can only be written by firmware when + CPSM is disabled (CPSMEN = 0) + 14 + 1 + + + BOOTEN + Enable boot mode + procedure. + 15 + 1 + + + CMDSUSPEND + The CPSM treats the command as a Suspend + or Resume command and signals interrupt period + start/end. This bit can only be written by firmware + when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 + and CMDTRANS = 0 Suspend command, start interrupt + period when response bit BS=0. CMDSUSPEND = 1 and + CMDTRANS = 1 Resume command with data, end interrupt + period when response bit DF=1. + 16 + 1 + + + + + RESP1R + RESP1R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + see Table 432 + 0 + 32 + + + + + RESP2R + RESP2R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + see Table404. + 0 + 32 + + + + + RESP3R + RESP3R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + see Table404. + 0 + 32 + + + + + RESP4R + RESP4R + The SDMMC_RESP1/2/3/4R registers contain the + status of a card, which is part of the received + response. + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + see Table404. + 0 + 32 + + + + + DTIMER + DTIMER + The SDMMC_DTIMER register contains the data + timeout period, in card bus clock periods. A counter + loads the value from the SDMMC_DTIMER register, and + starts decrementing when the data path state machine + (DPSM) enters the Wait_R or Busy state. If the timer + reaches 0 while the DPSM is in either of these states, + the timeout status flag is set. + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data and R1b busy timeout period This + bit can only be written when the CPSM and DPSM are + not active (CPSMACT = 0 and DPSMACT = 0). Data and + R1b busy timeout period expressed in card bus clock + periods. + 0 + 32 + + + + + DLENR + DLENR + The SDMMC_DLENR register contains the number + of data bytes to be transferred. The value is loaded into + the data counter when data transfer starts. + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value This register can only + be written by firmware when DPSM is inactive (DPSMACT + = 0). Number of data bytes to be transferred. When + DDR = 1 DATALENGTH is truncated to a multiple of 2. + (The last odd byte is not transfered) When DATALENGTH + = 0 no data will be transfered, when requested by a + CPSMEN and CMDTRANS = 1 also no command will be + transfered. DTEN and CPSMEN are cleared to + 0. + 0 + 25 + + + + + DCTRL + DCTRL + The SDMMC_DCTRL register control the data + path state machine (DPSM). + 0x2C + 0x20 + read-write + 0x00000000 + + + DTEN + Data transfer enable bit This bit can + only be written by firmware when DPSM is inactive + (DPSMACT = 0). This bit is cleared by Hardware when + data transfer completes. This bit shall only be used + to transfer data when no associated data transfer + command is used, i.e. shall not be used with SD or + eMMC cards. + 0 + 1 + + + DTDIR + Data transfer direction selection This + bit can only be written by firmware when DPSM is + inactive (DPSMACT = 0). + 1 + 1 + + + DTMODE + Data transfer mode selection. This bit + can only be written by firmware when DPSM is inactive + (DPSMACT = 0). + 2 + 2 + + + DBLOCKSIZE + Data block size This bit can only be + written by firmware when DPSM is inactive (DPSMACT = + 0). Define the data block length when the block data + transfer mode is selected: When DATALENGTH is not a + multiple of DBLOCKSIZE, the transfered data is + truncated at a multiple of DBLOCKSIZE. (Any remain + data will not be transfered.) When DDR = 1, + DBLOCKSIZE = 0000 shall not be used. (No data will be + transfered) + 4 + 4 + + + RWSTART + Read wait start. If this bit is set, + read wait operation starts. + 8 + 1 + + + RWSTOP + Read wait stop This bit is written by + firmware and auto cleared by hardware when the DPSM + moves from the READ_WAIT state to the WAIT_R or IDLE + state. + 9 + 1 + + + RWMOD + Read wait mode. This bit can only be + written by firmware when DPSM is inactive (DPSMACT = + 0). + 10 + 1 + + + SDIOEN + SD I/O interrupt enable functions This + bit can only be written by firmware when DPSM is + inactive (DPSMACT = 0). If this bit is set, the DPSM + enables the SD I/O card specific interrupt + operation. + 11 + 1 + + + BOOTACKEN + Enable the reception of the boot + acknowledgment. This bit can only be written by + firmware when DPSM is inactive (DPSMACT = + 0). + 12 + 1 + + + FIFORST + FIFO reset, will flush any remaining + data. This bit can only be written by firmware when + IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit + will only take effect when a transfer error or + transfer hold occurs. + 13 + 1 + + + + + DCNTR + DCNTR + The SDMMC_DCNTR register loads the value + from the data length register (see SDMMC_DLENR) when the + DPSM moves from the Idle state to the Wait_R or Wait_S + state. As data is transferred, the counter decrements the + value until it reaches 0. The DPSM then moves to the Idle + state and when there has been no error, the data status + end flag (DATAEND) is set. + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value When read, the number + of remaining data bytes to be transferred is + returned. Write has no effect. + 0 + 25 + + + + + STAR + STAR + The SDMMC_STAR register is a read-only + register. It contains two types of flag:Static flags + (bits [29,21,11:0]): these bits remain asserted until + they are cleared by writing to the SDMMC interrupt Clear + register (see SDMMC_ICR)Dynamic flags (bits [20:12]): + these bits change state depending on the state of the + underlying logic (for example, FIFO full and empty flags + are asserted and de-asserted as data while written to the + FIFO) + 0x34 + 0x20 + read-only + 0x00000000 + + + CCRCFAIL + Command response received (CRC check + failed). Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 0 + 1 + + + DCRCFAIL + Data block sent/received (CRC check + failed). Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 1 + 1 + + + CTIMEOUT + Command response timeout. Interrupt flag + is cleared by writing corresponding interrupt clear + bit in SDMMC_ICR. The Command Timeout period has a + fixed value of 64 SDMMC_CK clock + periods. + 2 + 1 + + + DTIMEOUT + Data timeout. Interrupt flag is cleared + by writing corresponding interrupt clear bit in + SDMMC_ICR. + 3 + 1 + + + TXUNDERR + Transmit FIFO underrun error or IDMA + read transfer error. Interrupt flag is cleared by + writing corresponding interrupt clear bit in + SDMMC_ICR. + 4 + 1 + + + RXOVERR + Received FIFO overrun error or IDMA + write transfer error. Interrupt flag is cleared by + writing corresponding interrupt clear bit in + SDMMC_ICR. + 5 + 1 + + + CMDREND + Command response received (CRC check + passed, or no CRC). Interrupt flag is cleared by + writing corresponding interrupt clear bit in + SDMMC_ICR. + 6 + 1 + + + CMDSENT + Command sent (no response required). + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 7 + 1 + + + DATAEND + Data transfer ended correctly. (data + counter, DATACOUNT is zero and no errors occur). + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 8 + 1 + + + DHOLD + Data transfer Hold. Interrupt flag is + cleared by writing corresponding interrupt clear bit + in SDMMC_ICR. + 9 + 1 + + + DBCKEND + Data block sent/received. (CRC check + passed) and DPSM moves to the READWAIT state. + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 10 + 1 + + + DABORT + Data transfer aborted by CMD12. + Interrupt flag is cleared by writing corresponding + interrupt clear bit in SDMMC_ICR. + 11 + 1 + + + DPSMACT + Data path state machine active, i.e. not + in Idle state. This is a hardware status flag only, + does not generate an interrupt. + 12 + 1 + + + CPSMACT + Command path state machine active, i.e. + not in Idle state. This is a hardware status flag + only, does not generate an interrupt. + 13 + 1 + + + TXFIFOHE + Transmit FIFO half empty At least half + the number of words can be written into the FIFO. + This bit is cleared when the FIFO becomes half+1 + full. + 14 + 1 + + + RXFIFOHF + Receive FIFO half full There are at + least half the number of words in the FIFO. This bit + is cleared when the FIFO becomes half+1 + empty. + 15 + 1 + + + TXFIFOF + Transmit FIFO full This is a hardware + status flag only, does not generate an interrupt. + This bit is cleared when one FIFO location becomes + empty. + 16 + 1 + + + RXFIFOF + Receive FIFO full This bit is cleared + when one FIFO location becomes empty. + 17 + 1 + + + TXFIFOE + Transmit FIFO empty This bit is cleared + when one FIFO location becomes full. + 18 + 1 + + + RXFIFOE + Receive FIFO empty This is a hardware + status flag only, does not generate an interrupt. + This bit is cleared when one FIFO location becomes + full. + 19 + 1 + + + BUSYD0 + Inverted value of SDMMC_D0 line (Busy), + sampled at the end of a CMD response and a second + time 2 SDMMC_CK cycles after the CMD response. This + bit is reset to not busy when the SDMMCD0 line + changes from busy to not busy. This bit does not + signal busy due to data transfer. This is a hardware + status flag only, it does not generate an + interrupt. + 20 + 1 + + + BUSYD0END + end of SDMMC_D0 Busy following a CMD + response detected. This indicates only end of busy + following a CMD response. This bit does not signal + busy due to data transfer. Interrupt flag is cleared + by writing corresponding interrupt clear bit in + SDMMC_ICR. + 21 + 1 + + + SDIOIT + SDIO interrupt received. Interrupt flag + is cleared by writing corresponding interrupt clear + bit in SDMMC_ICR. + 22 + 1 + + + ACKFAIL + Boot acknowledgment received (boot + acknowledgment check fail). Interrupt flag is cleared + by writing corresponding interrupt clear bit in + SDMMC_ICR. + 23 + 1 + + + ACKTIMEOUT + Boot acknowledgment timeout. Interrupt + flag is cleared by writing corresponding interrupt + clear bit in SDMMC_ICR. + 24 + 1 + + + VSWEND + Voltage switch critical timing section + completion. Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 25 + 1 + + + CKSTOP + SDMMC_CK stopped in Voltage switch + procedure. Interrupt flag is cleared by writing + corresponding interrupt clear bit in + SDMMC_ICR. + 26 + 1 + + + IDMATE + IDMA transfer error. Interrupt flag is + cleared by writing corresponding interrupt clear bit + in SDMMC_ICR. + 27 + 1 + + + IDMABTC + IDMA buffer transfer complete. interrupt + flag is cleared by writing corresponding interrupt + clear bit in SDMMC_ICR. + 28 + 1 + + + + + ICR + ICR + The SDMMC_ICR register is a write-only + register. Writing a bit with 1 clears the corresponding + bit in the SDMMC_STAR status register. + 0x38 + 0x20 + read-write + 0x00000000 + + + CCRCFAILC + CCRCFAIL flag clear bit Set by software + to clear the CCRCFAIL flag. + 0 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit Set by software + to clear the DCRCFAIL flag. + 1 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit Set by software + to clear the CTIMEOUT flag. + 2 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit Set by software + to clear the DTIMEOUT flag. + 3 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit Set by software + to clear TXUNDERR flag. + 4 + 1 + + + RXOVERRC + RXOVERR flag clear bit Set by software + to clear the RXOVERR flag. + 5 + 1 + + + CMDRENDC + CMDREND flag clear bit Set by software + to clear the CMDREND flag. + 6 + 1 + + + CMDSENTC + CMDSENT flag clear bit Set by software + to clear the CMDSENT flag. + 7 + 1 + + + DATAENDC + DATAEND flag clear bit Set by software + to clear the DATAEND flag. + 8 + 1 + + + DHOLDC + DHOLD flag clear bit Set by software to + clear the DHOLD flag. + 9 + 1 + + + DBCKENDC + DBCKEND flag clear bit Set by software + to clear the DBCKEND flag. + 10 + 1 + + + DABORTC + DABORT flag clear bit Set by software to + clear the DABORT flag. + 11 + 1 + + + BUSYD0ENDC + BUSYD0END flag clear bit Set by software + to clear the BUSYD0END flag. + 21 + 1 + + + SDIOITC + SDIOIT flag clear bit Set by software to + clear the SDIOIT flag. + 22 + 1 + + + ACKFAILC + ACKFAIL flag clear bit Set by software + to clear the ACKFAIL flag. + 23 + 1 + + + ACKTIMEOUTC + ACKTIMEOUT flag clear bit Set by + software to clear the ACKTIMEOUT flag. + 24 + 1 + + + VSWENDC + VSWEND flag clear bit Set by software to + clear the VSWEND flag. + 25 + 1 + + + CKSTOPC + CKSTOP flag clear bit Set by software to + clear the CKSTOP flag. + 26 + 1 + + + IDMATEC + IDMA transfer error clear bit Set by + software to clear the IDMATE flag. + 27 + 1 + + + IDMABTCC + IDMA buffer transfer complete clear bit + Set by software to clear the IDMABTC + flag. + 28 + 1 + + + + + MASKR + MASKR + The interrupt mask register determines which + status flags generate an interrupt request by setting the + corresponding bit to 1. + 0x3C + 0x20 + read-write + 0x00000000 + + + CCRCFAILIE + Command CRC fail interrupt enable Set + and cleared by software to enable/disable interrupt + caused by command CRC failure. + 0 + 1 + + + DCRCFAILIE + Data CRC fail interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data CRC failure. + 1 + 1 + + + CTIMEOUTIE + Command timeout interrupt enable Set and + cleared by software to enable/disable interrupt + caused by command timeout. + 2 + 1 + + + DTIMEOUTIE + Data timeout interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data timeout. + 3 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt enable + Set and cleared by software to enable/disable + interrupt caused by Tx FIFO underrun + error. + 4 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt enable + Set and cleared by software to enable/disable + interrupt caused by Rx FIFO overrun + error. + 5 + 1 + + + CMDRENDIE + Command response received interrupt + enable Set and cleared by software to enable/disable + interrupt caused by receiving command + response. + 6 + 1 + + + CMDSENTIE + Command sent interrupt enable Set and + cleared by software to enable/disable interrupt + caused by sending command. + 7 + 1 + + + DATAENDIE + Data end interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data end. + 8 + 1 + + + DHOLDIE + Data hold interrupt enable Set and + cleared by software to enable/disable the interrupt + generated when sending new data is hold in the DPSM + Wait_S state. + 9 + 1 + + + DBCKENDIE + Data block end interrupt enable Set and + cleared by software to enable/disable interrupt + caused by data block end. + 10 + 1 + + + DABORTIE + Data transfer aborted interrupt enable + Set and cleared by software to enable/disable + interrupt caused by a data transfer being + aborted. + 11 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt enable Set + and cleared by software to enable/disable interrupt + caused by Tx FIFO half empty. + 14 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt enable Set + and cleared by software to enable/disable interrupt + caused by Rx FIFO half full. + 15 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt enable Set and + cleared by software to enable/disable interrupt + caused by Rx FIFO full. + 17 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt enable Set and + cleared by software to enable/disable interrupt + caused by Tx FIFO empty. + 18 + 1 + + + BUSYD0ENDIE + BUSYD0END interrupt enable Set and + cleared by software to enable/disable the interrupt + generated when SDMMC_D0 signal changes from busy to + NOT busy following a CMD response. + 21 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable Set and cleared by software to enable/disable + the interrupt generated when receiving the SDIO mode + interrupt. + 22 + 1 + + + ACKFAILIE + Acknowledgment Fail interrupt enable Set + and cleared by software to enable/disable interrupt + caused by acknowledgment Fail. + 23 + 1 + + + ACKTIMEOUTIE + Acknowledgment timeout interrupt enable + Set and cleared by software to enable/disable + interrupt caused by acknowledgment + timeout. + 24 + 1 + + + VSWENDIE + Voltage switch critical timing section + completion interrupt enable Set and cleared by + software to enable/disable the interrupt generated + when voltage switch critical timing section + completion. + 25 + 1 + + + CKSTOPIE + Voltage Switch clock stopped interrupt + enable Set and cleared by software to enable/disable + interrupt caused by Voltage Switch clock + stopped. + 26 + 1 + + + IDMABTCIE + IDMA buffer transfer complete interrupt + enable Set and cleared by software to enable/disable + the interrupt generated when the IDMA has transferred + all data belonging to a memory buffer. + 28 + 1 + + + + + ACKTIMER + ACKTIMER + The SDMMC_ACKTIMER register contains the + acknowledgment timeout period, in SDMMC_CK bus clock + periods. A counter loads the value from the + SDMMC_ACKTIMER register, and starts decrementing when the + data path state machine (DPSM) enters the Wait_Ack state. + If the timer reaches 0 while the DPSM is in this states, + the acknowledgment timeout status flag is + set. + 0x40 + 0x20 + read-write + 0x00000000 + + + ACKTIME + Boot acknowledgment timeout period This + bit can only be written by firmware when CPSM is + disabled (CPSMEN = 0). Boot acknowledgment timeout + period expressed in card bus clock + periods. + 0 + 25 + + + + + IDMACTRLR + IDMACTRLR + The receive and transmit FIFOs can be read + or written as 32-bit wide registers. The FIFOs contain 32 + entries on 32 sequential addresses. This allows the CPU + to use its load and store multiple operands to read + from/write to the FIFO. + 0x50 + 0x20 + read-write + 0x00000000 + + + IDMAEN + IDMA enable This bit can only be written + by firmware when DPSM is inactive (DPSMACT = + 0). + 0 + 1 + + + IDMABMODE + Buffer mode selection. This bit can only + be written by firmware when DPSM is inactive (DPSMACT + = 0). + 1 + 1 + + + IDMABACT + Double buffer mode active buffer + indication This bit can only be written by firmware + when DPSM is inactive (DPSMACT = 0). When IDMA is + enabled this bit is toggled by + hardware. + 2 + 1 + + + + + IDMABSIZER + IDMABSIZER + The SDMMC_IDMABSIZER register contains the + buffers size when in double buffer + configuration. + 0x54 + 0x20 + read-write + 0x00000000 + + + IDMABNDT + Number of transfers per buffer. This + 8-bit value shall be multiplied by 8 to get the size + of the buffer in 32-bit words and by 32 to get the + size of the buffer in bytes. Example: IDMABNDT = + 0x01: buffer size = 8 words = 32 bytes. These bits + can only be written by firmware when DPSM is inactive + (DPSMACT = 0). + 5 + 8 + + + + + IDMABASE0R + IDMABASE0R + The SDMMC_IDMABASE0R register contains the + memory buffer base address in single buffer configuration + and the buffer 0 base address in double buffer + configuration. + 0x58 + 0x20 + read-write + 0x00000000 + + + IDMABASE0 + Buffer 0 memory base address bits + [31:2], shall be word aligned (bit [1:0] are always 0 + and read only). This register can be written by + firmware when DPSM is inactive (DPSMACT = 0), and can + dynamically be written by firmware when DPSM active + (DPSMACT = 1) and memory buffer 0 is inactive + (IDMABACT = 1). + 0 + 32 + + + + + IDMABASE1R + IDMABASE1R + The SDMMC_IDMABASE1R register contains the + double buffer configuration second buffer memory base + address. + 0x5C + 0x20 + read-write + 0x00000000 + + + IDMABASE1 + Buffer 1 memory base address, shall be + word aligned (bit [1:0] are always 0 and read only). + This register can be written by firmware when DPSM is + inactive (DPSMACT = 0), and can dynamically be + written by firmware when DPSM active (DPSMACT = 1) + and memory buffer 1 is inactive (IDMABACT = + 0). + 0 + 32 + + + + + FIFOR + FIFOR + The receive and transmit FIFOs can be only + read or written as word (32-bit) wide registers. The + FIFOs contain 16 entries on sequential addresses. This + allows the CPU to use its load and store multiple + operands to read from/write to the FIFO.When accessing + SDMMC_FIFOR with half word or byte access an AHB bus + fault is generated. + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data This + register can only be read or written by firmware when + the DPSM is active (DPSMACT=1). The FIFO data + occupies 16 entries of 32-bit words. + 0 + 32 + + + + + RESPCMDR + RESPCMDR + SDMMC command response + register + 0x10 + 0x20 + read-only + 0xA3C5DD01 + + + RESPCMD + Response command index + 0 + 6 + + + + + + + SDMMC2 + 0x48022400 + + + VREFBUF + VREFBUF + VREFBUF + 0x58003C00 + + 0x0 + 0x400 + registers + + + + CSR + CSR + VREFBUF control and status + register + 0x0 + 0x20 + 0x00000002 + + + ENVR + Voltage reference buffer mode enable + This bit is used to enable the voltage reference + buffer mode. + 0 + 1 + read-write + + + HIZ + High impedance mode This bit controls + the analog switch to connect or not the VREF+ pin. + Refer to Table196: VREF buffer modes for the mode + descriptions depending on ENVR bit + configuration. + 1 + 1 + read-write + + + VRR + Voltage reference buffer + ready + 3 + 1 + read-only + + + VRS + Voltage reference scale These bits + select the value generated by the voltage reference + buffer. Other: Reserved + 4 + 3 + read-write + + + + + CCR + CCR + VREFBUF calibration control + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIM + Trimming code These bits are + automatically initialized after reset with the + trimming value stored in the Flash memory during the + production test. Writing into these bits allows to + tune the internal reference buffer + voltage. + 0 + 6 + + + + + + + IWDG1 + IWDG + IWDG + 0x58004800 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0x0000) + These bits must be written by software at regular + intervals with the key value 0xAAAA, otherwise the + watchdog generates a reset when the counter reaches + 0. Writing the key value 0x5555 to enable access to + the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see + Section23.3.6: Register access protection) Writing + the key value CCCCh starts the watchdog (except if + the hardware watchdog option is + selected) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider These bits are write + access protected see Section23.3.6: Register access + protection. They are written by software to select + the prescaler divider feeding the counter clock. PVU + bit of IWDG_SR must be reset in order to be able to + change the prescaler divider. Note: Reading this + register returns the prescaler value from the VDD + voltage domain. This value may not be up to + date/valid if a write operation to this register is + ongoing. For this reason the value read from this + register is valid only when the PVU bit in the + IWDG_SR register is reset. + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value These bits + are write access protected see Section23.3.6. They + are written by software to define the value to be + loaded in the watchdog counter each time the value + 0xAAAA is written in the IWDG_KR register. The + watchdog counter counts down from this value. The + timeout period is a function of this value and the + clock prescaler. Refer to the datasheet for the + timeout information. The RVU bit in the IWDG_SR + register must be reset in order to be able to change + the reload value. Note: Reading this register returns + the reload value from the VDD voltage domain. This + value may not be up to date/valid if a write + operation to this register is ongoing on this + register. For this reason the value read from this + register is valid only when the RVU bit in the + IWDG_SR register is reset. + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update This bit + is set by hardware to indicate that an update of the + prescaler value is ongoing. It is reset by hardware + when the prescaler update operation is completed in + the VDD voltage domain (takes up to 5 RC 40 kHz + cycles). Prescaler value can be updated only when PVU + bit is reset. + 0 + 1 + + + RVU + Watchdog counter reload value update + This bit is set by hardware to indicate that an + update of the reload value is ongoing. It is reset by + hardware when the reload value update operation is + completed in the VDD voltage domain (takes up to 5 RC + 40 kHz cycles). Reload value can be updated only when + RVU bit is reset. + 1 + 1 + + + WVU + Watchdog counter window value update + This bit is set by hardware to indicate that an + update of the window value is ongoing. It is reset by + hardware when the reload value update operation is + completed in the VDD voltage domain (takes up to 5 RC + 40 kHz cycles). Window value can be updated only when + WVU bit is reset. This bit is generated only if + generic window = 1 + 2 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value These bits + are write access protected see Section23.3.6. These + bits contain the high limit of the window value to be + compared to the downcounter. To prevent a reset, the + downcounter must be reloaded when its value is lower + than the window register value and greater than 0x0 + The WVU bit in the IWDG_SR register must be reset in + order to be able to change the reload value. Note: + Reading this register returns the reload value from + the VDD voltage domain. This value may not be valid + if a write operation to this register is ongoing. For + this reason the value read from this register is + valid only when the WVU bit in the IWDG_SR register + is reset. + 0 + 12 + + + + + + + IWDG2 + 0x58004C00 + + + WWDG1 + WWDG + WWDG + 0x50003000 + + 0x0 + 0x400 + registers + + + WWDG1 + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + T + 7-bit counter (MSB to LSB) These bits + contain the value of the watchdog counter. It is + decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A + reset is produced when it is decremented from 0x40 to + 0x3F (T6 becomes cleared). + 0 + 7 + + + WDGA + Activation bit This bit is set by + software and only cleared by hardware after a reset. + When WDGA=1, the watchdog can generate a + reset. + 7 + 1 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + W + 7-bit window value These bits contain + the window value to be compared to the + downcounter. + 0 + 7 + + + WDGTB + Timer base The time base of the + prescaler can be modified as follows: + 11 + 2 + + + EWI + Early wakeup interrupt When set, an + interrupt occurs whenever the counter reaches the + value 0x40. This interrupt is only cleared by + hardware after a reset. + 9 + 1 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag This bit is + set by hardware when the counter has reached the + value 0x40. It must be cleared by software by writing + 0. A write of 1 has no effect. This bit is also set + if the interrupt is not enabled. + 0 + 1 + + + + + + + WWDG2 + 0x40002C00 + + WWDG2_RST + Window Watchdog interrupt + 143 + + + + PWR + PWR + PWR + 0x58024800 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + PWR control register 1 + 0x0 + 0x20 + read-write + 0xF000C000 + + + LPDS + Low-power Deepsleep with SVOS3 (SVOS4 + and SVOS5 always use low-power, regardless of the + setting of this bit) + 0 + 1 + + + PVDE + Programmable voltage detector + enable + 4 + 1 + + + PLS + Programmable voltage detector level + selection These bits select the voltage threshold + detected by the PVD. Note: Refer to Section + Electrical characteristics of the product datasheet + for more details. + 5 + 3 + + + DBP + Disable backup domain write protection + In reset state, the RCC_BDCR register, the RTC + registers (including the backup registers), BREN and + MOEN bits in PWR_CR2 register, are protected against + parasitic write access. This bit must be set to + enable write access to these registers. + 8 + 1 + + + FLPS + Flash low-power mode in DStop mode This + bit allows to obtain the best trade-off between + low-power consumption and restart time when exiting + from DStop mode. When it is set, the Flash memory + enters low-power mode when D1 domain is in DStop + mode. + 9 + 1 + + + SVOS + System Stop mode voltage scaling + selection These bits control the VCORE voltage level + in system Stop mode, to obtain the best trade-off + between power consumption and + performance. + 14 + 2 + + + AVDEN + Peripheral voltage monitor on VDDA + enable + 16 + 1 + + + ALS + Analog voltage detector level selection + These bits select the voltage threshold detected by + the AVD. + 17 + 2 + + + + + CSR1 + CSR1 + PWR control status register 1 + 0x4 + 0x20 + read-only + 0x00004000 + + + PVDO + Programmable voltage detect output This + bit is set and cleared by hardware. It is valid only + if the PVD has been enabled by the PVDE bit. Note: + since the PVD is disabled in Standby mode, this bit + is equal to 0 after Standby or reset until the PVDE + bit is set. + 4 + 1 + + + ACTVOSRDY + Voltage levels ready bit for currently + used VOS and SDLEVEL This bit is set to 1 by hardware + when the voltage regulator and the SD converter are + both disabled and Bypass mode is selected in PWR + control register 3 (PWR_CR3). + 13 + 1 + + + ACTVOS + VOS currently applied for VCORE voltage + scaling selection. These bits reflect the last VOS + value applied to the PMU. + 14 + 2 + + + AVDO + Analog voltage detector output on VDDA + This bit is set and cleared by hardware. It is valid + only if AVD on VDDA is enabled by the AVDEN bit. + Note: Since the AVD is disabled in Standby mode, this + bit is equal to 0 after Standby or reset until the + AVDEN bit is set. + 16 + 1 + + + + + CR2 + CR2 + This register is not reset by wakeup from + Standby mode, RESET signal and VDD POR. It is only reset + by VSW POR and VSWRST reset. This register shall not be + accessed when VSWRST bit in RCC_BDCR register resets the + VSW domain.After reset, PWR_CR2 register is + write-protected. Prior to modifying its content, the DBP + bit in PWR_CR1 register must be set to disable the write + protection. + 0x8 + 0x20 + 0x00000000 + + + BREN + Backup regulator enable When set, the + Backup regulator (used to maintain the backup RAM + content in Standby and VBAT modes) is enabled. If + BREN is reset, the backup regulator is switched off. + The backup RAM can still be used in Run and Stop + modes. However, its content will be lost in Standby + and VBAT modes. If BREN is set, the application must + wait till the Backup Regulator Ready flag (BRRDY) is + set to indicate that the data written into the SRAM + will be maintained in Standby and VBAT + modes. + 0 + 1 + read-write + + + MONEN + VBAT and temperature monitoring enable + When set, the VBAT supply and temperature monitoring + is enabled. + 4 + 1 + read-write + + + BRRDY + Backup regulator ready This bit is set + by hardware to indicate that the Backup regulator is + ready. + 16 + 1 + read-only + + + VBATL + VBAT level monitoring versus low + threshold + 20 + 1 + read-only + + + VBATH + VBAT level monitoring versus high + threshold + 21 + 1 + read-only + + + TEMPL + Temperature level monitoring versus low + threshold + 22 + 1 + read-only + + + TEMPH + Temperature level monitoring versus high + threshold + 23 + 1 + read-only + + + + + CR3 + CR3 + Reset only by POR only, not reset by wakeup + from Standby mode and RESET pad. The lower byte of this + register is written once after POR and shall be written + before changing VOS level or ck_sys clock frequency. No + limitation applies to the upper bytes.Programming data + corresponding to an invalid combination of SDLEVEL, + SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be + ignored: data will not be written, the written-once + mechanism will lock the register and any further write + access will be ignored. The default supply configuration + will be kept and the ACTVOSRDY bit in PWR control status + register 1 (PWR_CSR1) will go on indicating invalid + voltage levels. The system shall be power cycled before + writing a new value. + 0xC + 0x20 + 0x00000006 + + + BYPASS + Power management unit + bypass + 0 + 1 + read-write + + + LDOEN + Low drop-out regulator + enable + 1 + 1 + read-write + + + SDEN + SD converter Enable + 2 + 1 + read-write + + + VBE + VBAT charging enable + 8 + 1 + read-write + + + VBRS + VBAT charging resistor + selection + 9 + 1 + read-write + + + USB33DEN + VDD33USB voltage level detector + enable. + 24 + 1 + write-only + + + USBREGEN + USB regulator enable. + 25 + 1 + read-write + + + USB33RDY + USB supply ready. + 26 + 1 + read-only + + + + + CPUCR + CPUCR + This register allows controlling CPU1 + power. + 0x10 + 0x20 + 0x00000000 + + + PDDS_D1 + D1 domain Power Down Deepsleep + selection. This bit allows CPU1 to define the + Deepsleep mode for D1 domain. + 0 + 1 + read-write + + + PDDS_D2 + D2 domain Power Down Deepsleep. This bit + allows CPU1 to define the Deepsleep mode for D2 + domain. + 1 + 1 + read-write + + + PDDS_D3 + System D3 domain Power Down Deepsleep. + This bit allows CPU1 to define the Deepsleep mode for + System D3 domain. + 2 + 1 + read-write + + + STOPF + STOP flag This bit is set by hardware + and cleared only by any reset or by setting the CPU1 + CSSF bit. + 5 + 1 + read-only + + + SBF + System Standby flag This bit is set by + hardware and cleared only by a POR (Power-on Reset) + or by setting the CPU1 CSSF bit + 6 + 1 + read-only + + + SBF_D1 + D1 domain DStandby flag This bit is set + by hardware and cleared by any system reset or by + setting the CPU1 CSSF bit. Once set, this bit can be + cleared only when the D1 domain is no longer in + DStandby mode. + 7 + 1 + read-only + + + SBF_D2 + D2 domain DStandby flag This bit is set + by hardware and cleared by any system reset or by + setting the CPU1 CSSF bit. Once set, this bit can be + cleared only when the D2 domain is no longer in + DStandby mode. + 8 + 1 + read-only + + + CSSF + Clear D1 domain CPU1 Standby, Stop and + HOLD flags (always read as 0) This bit is cleared to + 0 by hardware. + 9 + 1 + read-write + + + RUN_D3 + Keep system D3 domain in Run mode + regardless of the CPU sub-systems modes + 11 + 1 + read-write + + + + + D3CR + D3CR + This register allows controlling D3 domain + power.Following reset VOSRDY will be read 1 by + software + 0x18 + 0x20 + 0x00004000 + + + VOSRDY + VOS Ready bit for VCORE voltage scaling + output selection. This bit is set to 1 by hardware + when Bypass mode is selected in PWR control register + 3 (PWR_CR3). + 13 + 1 + read-only + + + VOS + Voltage scaling selection according to + performance These bits control the VCORE voltage + level and allow to obtains the best trade-off between + power consumption and performance: When increasing + the performance, the voltage scaling shall be changed + before increasing the system frequency. When + decreasing performance, the system frequency shall + first be decreased before changing the voltage + scaling. + 14 + 2 + read-write + + + + + WKUPCR + WKUPCR + reset only by system reset, not reset by + wakeup from Standby mode5 wait states are required when + writing this register (when clearing a WKUPF bit in + PWR_WKUPFR, the AHB write access will complete after the + WKUPF has been cleared). + 0x20 + 0x20 + read-write + 0x00000000 + + + WKUPC + Clear Wakeup pin flag for WKUP. These + bits are always read as 0. + 0 + 6 + + + + + WKUPFR + WKUPFR + reset only by system reset, not reset by + wakeup from Standby mode + 0x24 + 0x20 + read-write + 0x00000000 + + + WKUPF1 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 0 + 1 + + + WKUPF2 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 1 + 1 + + + WKUPF3 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 2 + 1 + + + WKUPF4 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 3 + 1 + + + WKUPF5 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 4 + 1 + + + WKUPF6 + Wakeup pin WKUPF flag. This bit is set + by hardware and cleared only by a Reset pin or by + setting the WKUPCn+1 bit in the PWR wakeup clear + register (PWR_WKUPCR). + 5 + 1 + + + + + WKUPEPR + WKUPEPR + Reset only by system reset, not reset by + wakeup from Standby mode + 0x28 + 0x20 + read-write + 0x00000000 + + + WKUPEN1 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 0 + 1 + + + WKUPEN2 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 1 + 1 + + + WKUPEN3 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 2 + 1 + + + WKUPEN4 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 3 + 1 + + + WKUPEN5 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 4 + 1 + + + WKUPEN6 + Enable Wakeup Pin WKUPn+1 Each bit is + set and cleared by software. Note: An additional + wakeup event is detected if WKUPn+1 pin is enabled + (by setting the WKUPENn+1 bit) when WKUPn+1 pin level + is already high when WKUPPn+1 selects rising edge, or + low when WKUPPn+1 selects falling edge. + 5 + 1 + + + WKUPP1 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 8 + 1 + + + WKUPP2 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 9 + 1 + + + WKUPP3 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 10 + 1 + + + WKUPP4 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 11 + 1 + + + WKUPP5 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 12 + 1 + + + WKUPP6 + Wakeup pin polarity bit for WKUPn-7 + These bits define the polarity used for event + detection on WKUPn-7 external wakeup + pin. + 13 + 1 + + + WKUPPUPD1 + Wakeup pin pull + configuration + 16 + 2 + + + WKUPPUPD2 + Wakeup pin pull + configuration + 18 + 2 + + + WKUPPUPD3 + Wakeup pin pull + configuration + 20 + 2 + + + WKUPPUPD4 + Wakeup pin pull + configuration + 22 + 2 + + + WKUPPUPD5 + Wakeup pin pull + configuration + 24 + 2 + + + WKUPPUPD6 + Wakeup pin pull configuration for + WKUP(truncate(n/2)-7) These bits define the I/O pad + pull configuration used when WKUPEN(truncate(n/2)-7) + = 1. The associated GPIO port pull configuration + shall be set to the same value or to 00. The Wakeup + pin pull configuration is kept in Standby + mode. + 26 + 2 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + 0x00000000 + + + IOLOCK + Locking the AF configuration of + associated IOs + 16 + 1 + read-only + + + TCRCI + CRC calculation initialization pattern + control for transmitter + 15 + 1 + read-write + + + RCRCI + CRC calculation initialization pattern + control for receiver + 14 + 1 + read-write + + + CRC33_17 + 32-bit CRC polynomial + configuration + 13 + 1 + read-write + + + SSI + Internal SS signal input + level + 12 + 1 + read-write + + + HDDIR + Rx/Tx direction at Half-duplex + mode + 11 + 1 + read-write + + + CSUSP + Master SUSPend request + 10 + 1 + write-only + + + CSTART + Master transfer start + 9 + 1 + read-only + + + MASRX + Master automatic SUSP in Receive + mode + 8 + 1 + read-write + + + SPE + Serial Peripheral Enable + 0 + 1 + read-write + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + 0x00000000 + + + TSER + Number of data transfer extension to be + reload into TSIZE just when a previous + 16 + 16 + read-only + + + TSIZE + Number of data at current + transfer + 0 + 16 + read-write + + + + + CFG1 + CFG1 + configuration register 1 + 0x8 + 0x20 + read-write + 0x00070007 + + + MBR + Master baud rate + 28 + 3 + + + CRCEN + Hardware CRC computation + enable + 22 + 1 + + + CRCSIZE + Length of CRC frame to be transacted and + compared + 16 + 5 + + + TXDMAEN + Tx DMA stream enable + 15 + 1 + + + RXDMAEN + Rx DMA stream enable + 14 + 1 + + + UDRDET + Detection of underrun condition at slave + transmitter + 11 + 2 + + + UDRCFG + Behavior of slave transmitter at + underrun condition + 9 + 2 + + + FTHVL + threshold level + 5 + 4 + + + DSIZE + Number of bits in at single SPI data + frame + 0 + 5 + + + + + CFG2 + CFG2 + configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + AFCNTR + Alternate function GPIOs + control + 31 + 1 + + + SSOM + SS output management in master + mode + 30 + 1 + + + SSOE + SS output enable + 29 + 1 + + + SSIOP + SS input/output polarity + 28 + 1 + + + SSM + Software management of SS signal + input + 26 + 1 + + + CPOL + Clock polarity + 25 + 1 + + + CPHA + Clock phase + 24 + 1 + + + LSBFRST + Data frame format + 23 + 1 + + + MASTER + SPI Master + 22 + 1 + + + SP + Serial Protocol + 19 + 3 + + + COMM + SPI Communication Mode + 17 + 2 + + + IOSWP + Swap functionality of MISO and MOSI + pins + 15 + 1 + + + MIDI + Master Inter-Data Idleness + 4 + 4 + + + MSSI + Master SS Idleness + 0 + 4 + + + + + IER + IER + Interrupt Enable Register + 0x10 + 0x20 + 0x00000000 + + + TSERFIE + Additional number of transactions reload + interrupt enable + 10 + 1 + read-write + + + MODFIE + Mode Fault interrupt + enable + 9 + 1 + read-write + + + TIFREIE + TIFRE interrupt enable + 8 + 1 + read-write + + + CRCEIE + CRC Interrupt enable + 7 + 1 + read-write + + + OVRIE + OVR interrupt enable + 6 + 1 + read-write + + + UDRIE + UDR interrupt enable + 5 + 1 + read-write + + + TXTFIE + TXTFIE interrupt enable + 4 + 1 + read-write + + + EOTIE + EOT, SUSP and TXC interrupt + enable + 3 + 1 + read-write + + + DPXPIE + DXP interrupt enabled + 2 + 1 + read-only + + + TXPIE + TXP interrupt enable + 1 + 1 + read-only + + + RXPIE + RXP Interrupt Enable + 0 + 1 + read-write + + + + + SR + SR + Status Register + 0x14 + 0x20 + read-only + 0x00001002 + + + CTSIZE + Number of data frames remaining in + current TSIZE session + 16 + 16 + + + RXWNE + RxFIFO Word Not Empty + 15 + 1 + + + RXPLVL + RxFIFO Packing LeVeL + 13 + 2 + + + TXC + TxFIFO transmission + complete + 12 + 1 + + + SUSP + SUSPend + 11 + 1 + + + TSERF + Additional number of SPI data to be + transacted was reload + 10 + 1 + + + MODF + Mode Fault + 9 + 1 + + + TIFRE + TI frame format error + 8 + 1 + + + CRCE + CRC Error + 7 + 1 + + + OVR + Overrun + 6 + 1 + + + UDR + Underrun at slave transmission + mode + 5 + 1 + + + TXTF + Transmission Transfer + Filled + 4 + 1 + + + EOT + End Of Transfer + 3 + 1 + + + DXP + Duplex Packet + 2 + 1 + + + TXP + Tx-Packet space available + 1 + 1 + + + RXP + Rx-Packet available + 0 + 1 + + + + + IFCR + IFCR + Interrupt/Status Flags Clear + Register + 0x18 + 0x20 + write-only + 0x00000000 + + + SUSPC + SUSPend flag clear + 11 + 1 + + + TSERFC + TSERFC flag clear + 10 + 1 + + + MODFC + Mode Fault flag clear + 9 + 1 + + + TIFREC + TI frame format error flag + clear + 8 + 1 + + + CRCEC + CRC Error flag clear + 7 + 1 + + + OVRC + Overrun flag clear + 6 + 1 + + + UDRC + Underrun flag clear + 5 + 1 + + + TXTFC + Transmission Transfer Filled flag + clear + 4 + 1 + + + EOTC + End Of Transfer flag clear + 3 + 1 + + + + + TXDR + TXDR + Transmit Data Register + 0x20 + 0x20 + write-only + 0x00000000 + + + TXDR + Transmit data register + 0 + 32 + + + + + RXDR + RXDR + Receive Data Register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDR + Receive data register + 0 + 32 + + + + + CRCPOLY + CRCPOLY + Polynomial Register + 0x40 + 0x20 + read-write + 0x00000107 + + + CRCPOLY + CRC polynomial register + 0 + 32 + + + + + TXCRC + TXCRC + Transmitter CRC Register + 0x44 + 0x20 + read-write + 0x00000000 + + + TXCRC + CRC register for + transmitter + 0 + 32 + + + + + RXCRC + RXCRC + Receiver CRC Register + 0x48 + 0x20 + read-write + 0x00000000 + + + RXCRC + CRC register for receiver + 0 + 32 + + + + + UDRDR + UDRDR + Underrun Data Register + 0x4C + 0x20 + read-write + 0x00000000 + + + UDRDR + Data at slave underrun + condition + 0 + 32 + + + + + CGFR + CGFR + configuration register + 0x50 + 0x20 + read-write + 0x00000000 + + + MCKOE + Master clock output enable + 25 + 1 + + + ODD + Odd factor for the + prescaler + 24 + 1 + + + I2SDIV + I2S linear prescaler + 16 + 8 + + + DATFMT + Data format + 14 + 1 + + + WSINV + Fixed channel length in + SLAVE + 13 + 1 + + + FIXCH + Word select inversion + 12 + 1 + + + CKPOL + Serial audio clock + polarity + 11 + 1 + + + CHLEN + Channel length (number of bits per audio + channel) + 10 + 1 + + + DATLEN + Data length to be + transferred + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + I2SCFG + I2S configuration mode + 1 + 3 + + + I2SMOD + I2S mode selection + 0 + 1 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40013400 + + SPI4 + SPI4 global interrupt + 84 + + + + SPI5 + 0x40015000 + + SPI5 + SPI5 global interrupt + 85 + + + + SPI6 + 0x58001400 + + SPI6 + SPI6 global interrupt + 86 + + + + LTDC + LCD-TFT Controller + LTDC + 0x50001000 + + 0x0 + 0x1000 + registers + + + LTDC + LCD-TFT global interrupt + 88 + + + LTDC_ER + LCD-TFT error interrupt + 89 + + + + SSCR + SSCR + Synchronization Size Configuration + Register + 0x8 + 0x20 + read-write + 0x00000000 + + + HSW + Horizontal Synchronization Width (in + units of pixel clock period) + 16 + 10 + + + VSH + Vertical Synchronization Height (in + units of horizontal scan line) + 0 + 11 + + + + + BPCR + BPCR + Back Porch Configuration + Register + 0xC + 0x20 + read-write + 0x00000000 + + + AHBP + Accumulated Horizontal back porch (in + units of pixel clock period) + 16 + 12 + + + AVBP + Accumulated Vertical back porch (in + units of horizontal scan line) + 0 + 11 + + + + + AWCR + AWCR + Active Width Configuration + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + AAV + AAV + 16 + 12 + + + AAH + Accumulated Active Height (in units of + horizontal scan line) + 0 + 11 + + + + + TWCR + TWCR + Total Width Configuration + Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTALW + Total Width (in units of pixel clock + period) + 16 + 12 + + + TOTALH + Total Height (in units of horizontal + scan line) + 0 + 11 + + + + + GCR + GCR + Global Control Register + 0x18 + 0x20 + 0x00002220 + + + HSPOL + Horizontal Synchronization + Polarity + 31 + 1 + read-write + + + VSPOL + Vertical Synchronization + Polarity + 30 + 1 + read-write + + + DEPOL + Data Enable Polarity + 29 + 1 + read-write + + + PCPOL + Pixel Clock Polarity + 28 + 1 + read-write + + + DEN + Dither Enable + 16 + 1 + read-write + + + DRW + Dither Red Width + 12 + 3 + read-only + + + DGW + Dither Green Width + 8 + 3 + read-only + + + DBW + Dither Blue Width + 4 + 3 + read-only + + + LTDCEN + LCD-TFT controller enable + bit + 0 + 1 + read-write + + + + + SRCR + SRCR + Shadow Reload Configuration + Register + 0x24 + 0x20 + read-write + 0x00000000 + + + VBR + Vertical Blanking Reload + 1 + 1 + + + IMR + Immediate Reload + 0 + 1 + + + + + BCCR + BCCR + Background Color Configuration + Register + 0x2C + 0x20 + read-write + 0x00000000 + + + BCBLUE + Background Color Blue + value + 0 + 8 + + + BCGREEN + Background Color Green + value + 8 + 8 + + + BCRED + Background Color Red value + 16 + 8 + + + + + IER + IER + Interrupt Enable Register + 0x34 + 0x20 + read-write + 0x00000000 + + + RRIE + Register Reload interrupt + enable + 3 + 1 + + + TERRIE + Transfer Error Interrupt + Enable + 2 + 1 + + + FUIE + FIFO Underrun Interrupt + Enable + 1 + 1 + + + LIE + Line Interrupt Enable + 0 + 1 + + + + + ISR + ISR + Interrupt Status Register + 0x38 + 0x20 + read-only + 0x00000000 + + + RRIF + Register Reload Interrupt + Flag + 3 + 1 + + + TERRIF + Transfer Error interrupt + flag + 2 + 1 + + + FUIF + FIFO Underrun Interrupt + flag + 1 + 1 + + + LIF + Line Interrupt flag + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x3C + 0x20 + write-only + 0x00000000 + + + CRRIF + Clears Register Reload Interrupt + Flag + 3 + 1 + + + CTERRIF + Clears the Transfer Error Interrupt + Flag + 2 + 1 + + + CFUIF + Clears the FIFO Underrun Interrupt + flag + 1 + 1 + + + CLIF + Clears the Line Interrupt + Flag + 0 + 1 + + + + + LIPCR + LIPCR + Line Interrupt Position Configuration + Register + 0x40 + 0x20 + read-write + 0x00000000 + + + LIPOS + Line Interrupt Position + 0 + 11 + + + + + CPSR + CPSR + Current Position Status + Register + 0x44 + 0x20 + read-only + 0x00000000 + + + CXPOS + Current X Position + 16 + 16 + + + CYPOS + Current Y Position + 0 + 16 + + + + + CDSR + CDSR + Current Display Status + Register + 0x48 + 0x20 + read-only + 0x0000000F + + + HSYNCS + Horizontal Synchronization display + Status + 3 + 1 + + + VSYNCS + Vertical Synchronization display + Status + 2 + 1 + + + HDES + Horizontal Data Enable display + Status + 1 + 1 + + + VDES + Vertical Data Enable display + Status + 0 + 1 + + + + + L1CR + L1CR + Layerx Control Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + + COLKEN + Color Keying Enable + 1 + 1 + + + LEN + Layer Enable + 0 + 1 + + + + + L1WHPCR + L1WHPCR + Layerx Window Horizontal Position + Configuration Register + 0x88 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop + Position + 16 + 12 + + + WHSTPOS + Window Horizontal Start + Position + 0 + 12 + + + + + L1WVPCR + L1WVPCR + Layerx Window Vertical Position + Configuration Register + 0x8C + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop + Position + 16 + 11 + + + WVSTPOS + Window Vertical Start + Position + 0 + 11 + + + + + L1CKCR + L1CKCR + Layerx Color Keying Configuration + Register + 0x90 + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + CKGREEN + Color Key Green value + 8 + 8 + + + CKBLUE + Color Key Blue value + 0 + 8 + + + + + L1PFCR + L1PFCR + Layerx Pixel Format Configuration + Register + 0x94 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + + + + L1CACR + L1CACR + Layerx Constant Alpha Configuration + Register + 0x98 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + + + L1DCCR + L1DCCR + Layerx Default Color Configuration + Register + 0x9C + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + DCRED + Default Color Red + 16 + 8 + + + DCGREEN + Default Color Green + 8 + 8 + + + DCBLUE + Default Color Blue + 0 + 8 + + + + + L1BFCR + L1BFCR + Layerx Blending Factors Configuration + Register + 0xA0 + 0x20 + read-write + 0x00000607 + + + BF1 + Blending Factor 1 + 8 + 3 + + + BF2 + Blending Factor 2 + 0 + 3 + + + + + L1CFBAR + L1CFBAR + Layerx Color Frame Buffer Address + Register + 0xAC + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start + Address + 0 + 32 + + + + + L1CFBLR + L1CFBLR + Layerx Color Frame Buffer Length + Register + 0xB0 + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in + bytes + 16 + 13 + + + CFBLL + Color Frame Buffer Line + Length + 0 + 13 + + + + + L1CFBLNR + L1CFBLNR + Layerx ColorFrame Buffer Line Number + Register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + + + L1CLUTWR + L1CLUTWR + Layerx CLUT Write Register + 0xC4 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + RED + Red value + 16 + 8 + + + GREEN + Green value + 8 + 8 + + + BLUE + Blue value + 0 + 8 + + + + + L2CR + L2CR + Layerx Control Register + 0x104 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + + COLKEN + Color Keying Enable + 1 + 1 + + + LEN + Layer Enable + 0 + 1 + + + + + L2WHPCR + L2WHPCR + Layerx Window Horizontal Position + Configuration Register + 0x108 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop + Position + 16 + 12 + + + WHSTPOS + Window Horizontal Start + Position + 0 + 12 + + + + + L2WVPCR + L2WVPCR + Layerx Window Vertical Position + Configuration Register + 0x10C + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop + Position + 16 + 11 + + + WVSTPOS + Window Vertical Start + Position + 0 + 11 + + + + + L2CKCR + L2CKCR + Layerx Color Keying Configuration + Register + 0x110 + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + CKGREEN + Color Key Green value + 8 + 8 + + + CKBLUE + Color Key Blue value + 0 + 8 + + + + + L2PFCR + L2PFCR + Layerx Pixel Format Configuration + Register + 0x114 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + + + + L2CACR + L2CACR + Layerx Constant Alpha Configuration + Register + 0x118 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + + + L2DCCR + L2DCCR + Layerx Default Color Configuration + Register + 0x11C + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + DCRED + Default Color Red + 16 + 8 + + + DCGREEN + Default Color Green + 8 + 8 + + + DCBLUE + Default Color Blue + 0 + 8 + + + + + L2BFCR + L2BFCR + Layerx Blending Factors Configuration + Register + 0x120 + 0x20 + read-write + 0x00000607 + + + BF1 + Blending Factor 1 + 8 + 3 + + + BF2 + Blending Factor 2 + 0 + 3 + + + + + L2CFBAR + L2CFBAR + Layerx Color Frame Buffer Address + Register + 0x12C + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start + Address + 0 + 32 + + + + + L2CFBLR + L2CFBLR + Layerx Color Frame Buffer Length + Register + 0x130 + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in + bytes + 16 + 13 + + + CFBLL + Color Frame Buffer Line + Length + 0 + 13 + + + + + L2CFBLNR + L2CFBLNR + Layerx ColorFrame Buffer Line Number + Register + 0x134 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + + + L2CLUTWR + L2CLUTWR + Layerx CLUT Write Register + 0x144 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + RED + Red value + 16 + 8 + + + GREEN + Green value + 8 + 8 + + + BLUE + Blue value + 0 + 8 + + + + + + + DSIHOST + DSIHOST + DSIHOST + 0x50000000 + + 0x0 + 0x800 + registers + + + + DSI_VR + DSI_VR + DSI Host version register + 0x0 + 0x20 + read-only + 0x3133302A + + + VERSION + VERSION + 0 + 32 + + + + + DSI_CR + DSI_CR + DSI Host control register + 0x4 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + + + DSI_CCR + DSI_CCR + DSI Host clock control register + 0x8 + 0x20 + read-write + 0x00000000 + + + TXECKDIV + TXECKDIV + 0 + 8 + + + TOCKDIV + TOCKDIV + 8 + 8 + + + + + DSI_LVCIDR + DSI_LVCIDR + DSI Host LTDC VCID register + 0xC + 0x20 + read-write + 0x00000000 + + + VCID + VCID + 0 + 2 + + + + + DSI_LCOLCR + DSI_LCOLCR + DSI Host LTDC color coding register + 0x10 + 0x20 + read-write + 0x00000000 + + + COLC + COLC + 0 + 4 + + + LPE + LPE + 8 + 1 + + + + + DSI_LPCR + DSI_LPCR + DSI Host LTDC polarity configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DEP + DEP + 0 + 1 + + + VSP + VSP + 1 + 1 + + + HSP + HSP + 2 + 1 + + + + + DSI_LPMCR + DSI_LPMCR + DSI Host low-power mode configuration register + 0x18 + 0x20 + read-write + 0x00000000 + + + VLPSIZE + VLPSIZE + 0 + 8 + + + LPSIZE + LPSIZE + 16 + 8 + + + + + DSI_PCR + DSI_PCR + DSI Host protocol configuration register + 0x2C + 0x20 + read-write + 0x00000000 + + + ETTXE + ETTXE + 0 + 1 + + + ETRXE + ETRXE + 1 + 1 + + + BTAE + BTAE + 2 + 1 + + + ECCRXE + ECCRXE + 3 + 1 + + + CRCRXE + CRCRXE + 4 + 1 + + + + + DSI_GVCIDR + DSI_GVCIDR + DSI Host generic VCID register + 0x30 + 0x20 + read-only + 0x00000000 + + + VCID + VCID + 0 + 2 + + + + + DSI_MCR + DSI_MCR + DSI Host mode configuration register + 0x34 + 0x20 + read-write + 0x00000001 + + + CMDM + CMDM + 0 + 1 + + + + + DSI_VMCR + DSI_VMCR + DSI Host video mode configuration register + 0x38 + 0x20 + read-write + 0x00000000 + + + VMT + VMT + 0 + 2 + + + LPVSAE + LPVSAE + 8 + 1 + + + LPVBPE + LPVBPE + 9 + 1 + + + LPVFPE + LPVFPE + 10 + 1 + + + LPVAE + LPVAE + 11 + 1 + + + LPHBPE + LPHBPE + 12 + 1 + + + LPHFPE + LPHFPE + 13 + 1 + + + FBTAAE + FBTAAE + 14 + 1 + + + LPCE + LPCE + 15 + 1 + + + PGE + PGE + 16 + 1 + + + PGM + PGM + 20 + 1 + + + PGO + PGO + 24 + 1 + + + + + DSI_VPCR + DSI_VPCR + DSI Host video packet configuration register + 0x3C + 0x20 + read-write + 0x00000000 + + + VPSIZE + VPSIZE + 0 + 14 + + + + + DSI_VCCR + DSI_VCCR + DSI Host video chunks configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + NUMC + NUMC + 0 + 13 + + + + + DSI_VNPCR + DSI_VNPCR + DSI Host video null packet configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + NPSIZE + NPSIZE + 0 + 13 + + + + + DSI_VHSACR + DSI_VHSACR + DSI Host video HSA configuration register + 0x48 + 0x20 + read-write + 0x00000000 + + + HSA + HSA + 0 + 12 + + + + + DSI_VHBPCR + DSI_VHBPCR + DSI Host video HBP configuration register + 0x4C + 0x20 + read-write + 0x00000000 + + + HBP + HBP + 0 + 12 + + + + + DSI_VLCR + DSI_VLCR + DSI Host video line configuration register + 0x50 + 0x20 + read-write + 0x00000000 + + + HLINE + HLINE + 0 + 15 + + + + + DSI_VVSACR + DSI_VVSACR + DSI Host video VSA configuration register + 0x54 + 0x20 + read-write + 0x00000000 + + + VSA + VSA + 0 + 10 + + + + + DSI_VVBPCR + DSI_VVBPCR + DSI Host video VBP configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + VBP + VBP + 0 + 10 + + + + + DSI_VVFPCR + DSI_VVFPCR + DSI Host video VFP configuration register + 0x5C + 0x20 + read-write + 0x00000000 + + + VFP + VFP + 0 + 10 + + + + + DSI_VVACR + DSI_VVACR + DSI Host video VA configuration register + 0x60 + 0x20 + read-write + 0x00000000 + + + VA + VA + 0 + 14 + + + + + DSI_LCCR + DSI_LCCR + DSI Host LTDC command configuration register + 0x64 + 0x20 + read-write + 0x00000000 + + + CMDSIZE + CMDSIZE + 0 + 16 + + + + + DSI_CMCR + DSI_CMCR + DSI Host command mode configuration register + 0x68 + 0x20 + read-write + 0x00000000 + + + TEARE + TEARE + 0 + 1 + + + ARE + ARE + 1 + 1 + + + GSW0TX + GSW0TX + 8 + 1 + + + GSW1TX + GSW1TX + 9 + 1 + + + GSW2TX + GSW2TX + 10 + 1 + + + GSR0TX + GSR0TX + 11 + 1 + + + GSR1TX + GSR1TX + 12 + 1 + + + GSR2TX + GSR2TX + 13 + 1 + + + GLWTX + GLWTX + 14 + 1 + + + DSW0TX + DSW0TX + 16 + 1 + + + DSW1TX + DSW1TX + 17 + 1 + + + DSR0TX + DSR0TX + 18 + 1 + + + DLWTX + DLWTX + 19 + 1 + + + MRDPS + MRDPS + 24 + 1 + + + + + DSI_GHCR + DSI_GHCR + DSI Host generic header configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + DT + 0 + 6 + + + VCID + VCID + 6 + 2 + + + WCLSB + WCLSB + 8 + 8 + + + WCMSB + WCMSB + 16 + 8 + + + + + DSI_GPDR + DSI_GPDR + DSI Host generic payload data register + 0x70 + 0x20 + read-write + 0x00000000 + + + DATA1 + DATA1 + 0 + 8 + + + DATA2 + DATA2 + 8 + 8 + + + DATA3 + DATA3 + 16 + 8 + + + DATA4 + DATA4 + 24 + 8 + + + + + DSI_GPSR + DSI_GPSR + DSI Host generic packet status register + 0x74 + 0x20 + read-only + 0x00000015 + + + CMDFE + CMDFE + 0 + 1 + + + CMDFF + CMDFF + 1 + 1 + + + PWRFE + PWRFE + 2 + 1 + + + PWRFF + PWRFF + 3 + 1 + + + PRDFE + PRDFE + 4 + 1 + + + PRDFF + PRDFF + 5 + 1 + + + RCB + RCB + 6 + 1 + + + + + DSI_TCCR0 + DSI_TCCR0 + DSI Host timeout counter configuration register 0 + 0x78 + 0x20 + read-write + 0x00000000 + + + LPRX_TOCNT + LPRX_TOCNT + 0 + 16 + + + HSTX_TOCNT + HSTX_TOCNT + 16 + 16 + + + + + DSI_TCCR1 + DSI_TCCR1 + DSI Host timeout counter configuration register 1 + 0x7C + 0x20 + read-write + 0x00000000 + + + HSRD_TOCNT + HSRD_TOCNT + 0 + 16 + + + + + DSI_TCCR2 + DSI_TCCR2 + DSI Host timeout counter configuration register 2 + 0x80 + 0x20 + read-write + 0x00000000 + + + LPRD_TOCNT + LPRD_TOCNT + 0 + 16 + + + + + DSI_TCCR3 + DSI_TCCR3 + DSI Host timeout counter configuration register 3 + 0x84 + 0x20 + read-write + 0x00000000 + + + HSWR_TOCNT + HSWR_TOCNT + 0 + 16 + + + PM + PM + 24 + 1 + + + + + DSI_TCCR4 + DSI_TCCR4 + DSI Host timeout counter configuration register 4 + 0x88 + 0x20 + read-write + 0x00000000 + + + LPWR_TOCNT + LPWR_TOCNT + 0 + 16 + + + + + DSI_TCCR5 + DSI_TCCR5 + DSI Host timeout counter configuration register 5 + 0x8C + 0x20 + read-write + 0x00000000 + + + BTA_TOCNT + BTA_TOCNT + 0 + 16 + + + + + DSI_CLCR + DSI_CLCR + DSI Host clock lane configuration register + 0x94 + 0x20 + read-write + 0x00000000 + + + DPCC + DPCC + 0 + 1 + + + ACR + ACR + 1 + 1 + + + + + DSI_CLTCR + DSI_CLTCR + DSI Host clock lane timer configuration register + 0x98 + 0x20 + read-write + 0x00000000 + + + LP2HS_TIME + LP2HS_TIME + 0 + 10 + + + HS2LP_TIME + HS2LP_TIME + 16 + 10 + + + + + DSI_DLTCR + DSI_DLTCR + DSI Host data lane timer configuration register + 0x9C + 0x20 + read-write + 0x00000000 + + + MRD_TIME + Maximum read time + 0 + 15 + + + LP2HS_TIME + LP2HS_TIME + 16 + 8 + + + HS2LP_TIME + HS2LP_TIME + 24 + 8 + + + + + DSI_PCTLR + DSI_PCTLR + DSI Host PHY control register + 0xA0 + 0x20 + read-write + 0x00000000 + + + DEN + DEN + 1 + 1 + + + CKE + CKE + 2 + 1 + + + + + DSI_PCONFR + DSI_PCONFR + DSI Host PHY configuration register + 0xA4 + 0x20 + read-write + 0x00000001 + + + NL + NL + 0 + 2 + + + SW_TIME + SW_TIME + 8 + 8 + + + + + DSI_PUCR + DSI_PUCR + DSI Host PHY ULPS control register + 0xA8 + 0x20 + read-write + 0x00000000 + + + URCL + URCL + 0 + 1 + + + UECL + UECL + 1 + 1 + + + URDL + URDL + 2 + 1 + + + UEDL + UEDL + 3 + 1 + + + + + DSI_PTTCR + DSI_PTTCR + DSI Host PHY TX triggers configuration register + 0xAC + 0x20 + read-write + 0x00000000 + + + TX_TRIG + TX_TRIG + 0 + 4 + + + + + DSI_PSR + DSI_PSR + DSI Host PHY status register + 0xB0 + 0x20 + read-only + 0x00001528 + + + PD + PD + 1 + 1 + + + PSSC + PSSC + 2 + 1 + + + UANC + UANC + 3 + 1 + + + PSS0 + PSS0 + 4 + 1 + + + UAN0 + UAN0 + 5 + 1 + + + RUE0 + RUE0 + 6 + 1 + + + PSS1 + PSS1 + 7 + 1 + + + UAN1 + UAN1 + 8 + 1 + + + + + DSI_ISR0 + DSI_ISR0 + DSI Host interrupt and status register 0 + 0xBC + 0x20 + read-only + 0x00000000 + + + AE0 + AE0 + 0 + 1 + + + AE1 + AE1 + 1 + 1 + + + AE2 + AE2 + 2 + 1 + + + AE3 + AE3 + 3 + 1 + + + AE4 + AE4 + 4 + 1 + + + AE5 + AE5 + 5 + 1 + + + AE6 + AE6 + 6 + 1 + + + AE7 + AE7 + 7 + 1 + + + AE8 + AE8 + 8 + 1 + + + AE9 + AE9 + 9 + 1 + + + AE10 + AE10 + 10 + 1 + + + AE11 + AE11 + 11 + 1 + + + AE12 + AE12 + 12 + 1 + + + AE13 + AE13 + 13 + 1 + + + AE14 + AE14 + 14 + 1 + + + AE15 + AE15 + 15 + 1 + + + PE0 + PE0 + 16 + 1 + + + PE1 + PE1 + 17 + 1 + + + PE2 + PE2 + 18 + 1 + + + PE3 + PE3 + 19 + 1 + + + PE4 + PE4 + 20 + 1 + + + + + DSI_ISR1 + DSI_ISR1 + DSI Host interrupt and status register 1 + 0xC0 + 0x20 + read-only + 0x00000000 + + + TOHSTX + TOHSTX + 0 + 1 + + + TOLPRX + TOLPRX + 1 + 1 + + + ECCSE + ECCSE + 2 + 1 + + + ECCME + ECCME + 3 + 1 + + + CRCE + CRCE + 4 + 1 + + + PSE + PSE + 5 + 1 + + + EOTPE + EOTPE + 6 + 1 + + + LPWRE + LPWRE + 7 + 1 + + + GCWRE + GCWRE + 8 + 1 + + + GPWRE + GPWRE + 9 + 1 + + + GPTXE + GPTXE + 10 + 1 + + + GPRDE + GPRDE + 11 + 1 + + + GPRXE + GPRXE + 12 + 1 + + + + + DSI_IER0 + DSI_IER0 + DSI Host interrupt enable register 0 + 0xC4 + 0x20 + read-write + 0x00000000 + + + AE0IE + AE0IE + 0 + 1 + + + AE1IE + AE1IE + 1 + 1 + + + AE2IE + AE2IE + 2 + 1 + + + AE3IE + AE3IE + 3 + 1 + + + AE4IE + AE4IE + 4 + 1 + + + AE5IE + AE5IE + 5 + 1 + + + AE6IE + AE6IE + 6 + 1 + + + AE7IE + AE7IE + 7 + 1 + + + AE8IE + AE8IE + 8 + 1 + + + AE9IE + AE9IE + 9 + 1 + + + AE10IE + AE10IE + 10 + 1 + + + AE11IE + AE11IE + 11 + 1 + + + AE12IE + AE12IE + 12 + 1 + + + AE13IE + AE13IE + 13 + 1 + + + AE14IE + AE14IE + 14 + 1 + + + AE15IE + AE15IE + 15 + 1 + + + PE0IE + PE0IE + 16 + 1 + + + PE1IE + PE1IE + 17 + 1 + + + PE2IE + PE2IE + 18 + 1 + + + PE3IE + PE3IE + 19 + 1 + + + PE4IE + PE4IE + 20 + 1 + + + + + DSI_IER1 + DSI_IER1 + DSI Host interrupt enable register 1 + 0xC8 + 0x20 + read-write + 0x00000000 + + + TOHSTXIE + TOHSTXIE + 0 + 1 + + + TOLPRXIE + TOLPRXIE + 1 + 1 + + + ECCSEIE + ECCSEIE + 2 + 1 + + + ECCMEIE + ECCMEIE + 3 + 1 + + + CRCEIE + CRCEIE + 4 + 1 + + + PSEIE + PSEIE + 5 + 1 + + + EOTPEIE + EOTPEIE + 6 + 1 + + + LPWREIE + LPWREIE + 7 + 1 + + + GCWREIE + GCWREIE + 8 + 1 + + + GPWREIE + GPWREIE + 9 + 1 + + + GPTXEIE + GPTXEIE + 10 + 1 + + + GPRDEIE + GPRDEIE + 11 + 1 + + + GPRXEIE + GPRXEIE + 12 + 1 + + + + + DSI_FIR0 + DSI_FIR0 + DSI Host force interrupt register 0 + 0xD8 + 0x20 + write-only + 0x00000000 + + + FAE0 + FAE0 + 0 + 1 + + + FAE1 + FAE1 + 1 + 1 + + + FAE2 + FAE2 + 2 + 1 + + + FAE3 + FAE3 + 3 + 1 + + + FAE4 + FAE4 + 4 + 1 + + + FAE5 + FAE5 + 5 + 1 + + + FAE6 + FAE6 + 6 + 1 + + + FAE7 + FAE7 + 7 + 1 + + + FAE8 + FAE8 + 8 + 1 + + + FAE9 + FAE9 + 9 + 1 + + + FAE10 + FAE10 + 10 + 1 + + + FAE11 + FAE11 + 11 + 1 + + + FAE12 + FAE12 + 12 + 1 + + + FAE13 + FAE13 + 13 + 1 + + + FAE14 + FAE14 + 14 + 1 + + + FAE15 + FAE15 + 15 + 1 + + + FPE0 + FPE0 + 16 + 1 + + + FPE1 + FPE1 + 17 + 1 + + + FPE2 + FPE2 + 18 + 1 + + + FPE3 + FPE3 + 19 + 1 + + + FPE4 + FPE4 + 20 + 1 + + + + + DSI_FIR1 + DSI_FIR1 + DSI Host force interrupt register 1 + 0xDC + 0x20 + write-only + 0x00000000 + + + FTOHSTX + FTOHSTX + 0 + 1 + + + FTOLPRX + FTOLPRX + 1 + 1 + + + FECCSE + FECCSE + 2 + 1 + + + FECCME + FECCME + 3 + 1 + + + FCRCE + FCRCE + 4 + 1 + + + FPSE + FPSE + 5 + 1 + + + FEOTPE + FEOTPE + 6 + 1 + + + FLPWRE + FLPWRE + 7 + 1 + + + FGCWRE + FGCWRE + 8 + 1 + + + FGPWRE + FGPWRE + 9 + 1 + + + FGPTXE + FGPTXE + 10 + 1 + + + FGPRDE + FGPRDE + 11 + 1 + + + FGPRXE + FGPRXE + 12 + 1 + + + + + DSI_VSCR + DSI_VSCR + DSI Host video shadow control register + 0x100 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + UR + UR + 8 + 1 + + + + + DSI_LCVCIDR + DSI_LCVCIDR + DSI Host LTDC current VCID register + 0x10C + 0x20 + read-write + 0x00000000 + + + VCID + VCID + 0 + 2 + + + + + DSI_LCCCR + DSI_LCCCR + DSI Host LTDC current color coding register + 0x110 + 0x20 + read-only + 0x00000000 + + + COLC + COLC + 0 + 4 + + + LPE + LPE + 8 + 1 + + + + + DSI_LPMCCR + DSI_LPMCCR + DSI Host low-power mode current configuration register + 0x118 + 0x20 + read-only + 0x00000000 + + + VLPSIZE + VLPSIZE + 0 + 8 + + + LPSIZE + LPSIZE + 16 + 8 + + + + + DSI_VMCCR + DSI_VMCCR + DSI Host video mode current configuration register + 0x138 + 0x20 + read-only + 0x00000000 + + + VMT + VMT + 0 + 2 + + + LPVSAE + LPVSAE + 2 + 1 + + + LPVBPE + LPVBPE + 3 + 1 + + + LPVFPE + LPVFPE + 4 + 1 + + + LPVAE + LPVAE + 5 + 1 + + + LPHBPE + LPHBPE + 6 + 1 + + + LPHFE + LPHFE + 7 + 1 + + + FBTAAE + FBTAAE + 8 + 1 + + + LPCE + LPCE + 9 + 1 + + + + + DSI_VPCCR + DSI_VPCCR + DSI Host video packet current configuration register + 0x13C + 0x20 + read-only + 0x00000000 + + + VPSIZE + VPSIZE + 0 + 14 + + + + + DSI_VCCCR + DSI_VCCCR + DSI Host video chunks current configuration register + 0x140 + 0x20 + read-only + 0x00000000 + + + NUMC + NUMC + 0 + 13 + + + + + DSI_VNPCCR + DSI_VNPCCR + DSI Host video null packet current configuration register + 0x144 + 0x20 + read-only + 0x00000000 + + + NPSIZE + NPSIZE + 0 + 13 + + + + + DSI_VHSACCR + DSI_VHSACCR + DSI Host video HSA current configuration register + 0x148 + 0x20 + read-only + 0x00000000 + + + HSA + HSA + 0 + 12 + + + + + DSI_VHBPCCR + DSI_VHBPCCR + DSI Host video HBP current configuration register + 0x14C + 0x20 + read-only + 0x00000000 + + + HBP + HBP + 0 + 12 + + + + + DSI_VLCCR + DSI_VLCCR + DSI Host video line current configuration register + 0x150 + 0x20 + read-only + 0x00000000 + + + HLINE + HLINE + 0 + 15 + + + + + DSI_VVSACCR + DSI_VVSACCR + DSI Host video VSA current configuration register + 0x154 + 0x20 + read-only + 0x00000000 + + + VSA + VSA + 0 + 10 + + + + + DSI_VVBPCCR + DSI_VVBPCCR + DSI Host video VBP current configuration register + 0x158 + 0x20 + read-only + 0x00000000 + + + VBP + VBP + 0 + 10 + + + + + DSI_VVFPCCR + DSI_VVFPCCR + DSI Host video VFP current configuration register + 0x15C + 0x20 + read-only + 0x00000000 + + + VFP + VFP + 0 + 10 + + + + + DSI_VVACCR + DSI_VVACCR + DSI Host video VA current configuration register + 0x160 + 0x20 + read-only + 0x00000000 + + + VA + VA + 0 + 14 + + + + + DSI_WCFGR + DSI_WCFGR + DSI wrapper configuration register + 0x400 + 0x20 + read-write + 0x00000000 + + + DSIM + DSIM + 0 + 1 + + + COLMUX + COLMUX + 1 + 3 + + + TESRC + TESRC + 4 + 1 + + + TEPOL + TEPOL + 5 + 1 + + + AR + AR + 6 + 1 + + + VSPOL + VSPOL + 7 + 1 + + + + + DSI_WCR + DSI_WCR + DSI wrapper control register + 0x404 + 0x20 + read-write + 0x00000000 + + + COLM + COLM + 0 + 1 + + + SHTDN + SHTDN + 1 + 1 + + + LTDCEN + LTDCEN + 2 + 1 + + + DSIEN + DSIEN + 3 + 1 + + + + + DSI_WIER + DSI_WIER + DSI wrapper interrupt enable register + 0x408 + 0x20 + read-write + 0x00000000 + + + TEIE + TEIE + 0 + 1 + + + ERIE + ERIE + 1 + 1 + + + PLLLIE + PLLLIE + 9 + 1 + + + PLLUIE + PLLUIE + 10 + 1 + + + RRIE + RRIE + 13 + 1 + + + + + DSI_WISR + DSI_WISR + DSI wrapper interrupt and status register + 0x40C + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + ERIF + ERIF + 1 + 1 + + + BUSY + BUSY + 2 + 1 + + + PLLLS + PLLLS + 8 + 1 + + + PLLLIF + PLLLIF + 9 + 1 + + + PLLUIF + PLLUIF + 10 + 1 + + + RRS + RRS + 12 + 1 + + + RRIF + RRIF + 13 + 1 + + + + + DSI_WIFCR + DSI_WIFCR + DSI wrapper interrupt flag clear register + 0x410 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CERIF + CERIF + 1 + 1 + + + CPLLLIF + CPLLLIF + 9 + 1 + + + CPLLUIF + CPLLUIF + 10 + 1 + + + CRRIF + CRRIF + 13 + 1 + + + + + DSI_WPCR0 + DSI_WPCR0 + DSI wrapper PHY configuration register 0 + 0x418 + 0x20 + read-write + 0x00000000 + + + UIX4 + UIX4 + 0 + 6 + + + SWCL + SWCL + 6 + 1 + + + SWDL0 + SWDL0 + 7 + 1 + + + SWDL1 + SWDL1 + 8 + 1 + + + HSICL + HSICL + 9 + 1 + + + HSIDL0 + HSIDL0 + 10 + 1 + + + HSIDL1 + HSIDL1 + 11 + 1 + + + FTXSMCL + FTXSMCL + 12 + 1 + + + FTXSMDL + FTXSMDL + 13 + 1 + + + CDOFFDL + CDOFFDL + 14 + 1 + + + TDDL + TDDL + 16 + 1 + + + PDEN + Pull-down enable + 18 + 1 + + + TCLKPREPEN + Custom time for tCLK-PREPARE enable + 19 + 1 + + + TCLKZEROEN + Custom time for tCLK-ZERO enable + 20 + 1 + + + THSPREPEN + Custom time for tHS-PREPARE enable + 21 + 1 + + + THSTRAILEN + Custom time for tHS-TRAIL enable + 22 + 1 + + + THSZEROEN + Custom time for tHS-ZERO enable + 23 + 1 + + + TLPXDEN + Custom time for tLPX for data lanes enable + 24 + 1 + + + THSEXITEN + Custom time for tHS-EXIT enable + 25 + 1 + + + TLPXCEN + Custom time for tLPX for clock lane enable + 26 + 1 + + + TCLKPOSTEN + Custom time for tCLK-POST enable + 27 + 1 + + + + + DSI_WPCR1 + DSI_WPCR1 + This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). + 0x41C + 0x20 + read-write + 0x00000000 + + + HSTXDCL + High-speed transmission delay on clock lane + 0 + 2 + + + HSTXDDL + High-speed transmission delay on data lanes + 2 + 2 + + + LPSRCCL + Low-power transmission slew-rate compensation on clock lane + 6 + 2 + + + LPSRCDL + Low-power transmission slew-rate compensation on data lanes + 8 + 2 + + + SDDC + SDD control + 12 + 1 + + + HSTXSRCCL + High-speed transmission slew-rate control on clock lane + 16 + 2 + + + HSTXSRCDL + High-speed transmission slew-rate control on data lanes + 18 + 2 + + + FLPRXLPM + Forces LP receiver in low-power mode + 22 + 1 + + + LPRXFT + Low-power RX low-pass filtering tuning + 25 + 2 + + + + + DSI_WPCR2 + DSI_WPCR2 + DSI wrapper PHY configuration register 2 + 0x420 + 0x20 + read-write + 0x00000000 + + + TCLKPREP + TCLKPREP + 0 + 8 + + + TCLKZERO + TCLKZERO + 8 + 8 + + + THSPREP + THSPREP + 16 + 8 + + + THSTRAIL + THSTRAIL + 24 + 8 + + + + + DSI_WPCR3 + DSI_WPCR3 + DSI wrapper PHY configuration register 3 + 0x424 + 0x20 + read-write + 0x00000000 + + + THSZERO + THSZERO + 0 + 8 + + + TLPXD + TLPXD + 8 + 8 + + + THSEXIT + THSEXIT + 16 + 8 + + + TLPXC + TLPXC + 24 + 8 + + + + + DSI_WPCR4 + DSI_WPCR4 + DSI wrapper PHY configuration register 4 + 0x428 + 0x20 + read-write + 0x00000000 + + + TCLKPOST + TCLKPOST + 0 + 8 + + + + + DSI_WRPCR + DSI_WRPCR + DSI wrapper regulator and PLL control register + 0x430 + 0x20 + read-write + 0x00000000 + + + PLLEN + PLLEN + 0 + 1 + + + NDIV + NDIV + 2 + 7 + + + IDF + IDF + 11 + 4 + + + ODF + ODF + 16 + 2 + + + REGEN + REGEN + 24 + 1 + + + + + + + SPDIFRX + Receiver Interface + SPDIFRX + 0x40004000 + + 0x0 + 0x400 + registers + + + SPDIF + SPDIFRX global interrupt + 97 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x00000000 + + + SPDIFRXEN + Peripheral Block Enable + 0 + 2 + + + RXDMAEN + Receiver DMA ENable for data + flow + 2 + 1 + + + RXSTEO + STerEO Mode + 3 + 1 + + + DRFMT + RX Data format + 4 + 2 + + + PMSK + Mask Parity error bit + 6 + 1 + + + VMSK + Mask of Validity bit + 7 + 1 + + + CUMSK + Mask of channel status and user + bits + 8 + 1 + + + PTMSK + Mask of Preamble Type bits + 9 + 1 + + + CBDMAEN + Control Buffer DMA ENable for control + flow + 10 + 1 + + + CHSEL + Channel Selection + 11 + 1 + + + NBTR + Maximum allowed re-tries during + synchronization phase + 12 + 2 + + + WFA + Wait For Activity + 14 + 1 + + + INSEL + input selection + 16 + 3 + + + CKSEN + Symbol Clock Enable + 20 + 1 + + + CKSBKPEN + Backup Symbol Clock Enable + 21 + 1 + + + + + IMR + IMR + Interrupt mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + RXNEIE + RXNE interrupt enable + 0 + 1 + + + CSRNEIE + Control Buffer Ready Interrupt + Enable + 1 + 1 + + + PERRIE + Parity error interrupt + enable + 2 + 1 + + + OVRIE + Overrun error Interrupt + Enable + 3 + 1 + + + SBLKIE + Synchronization Block Detected Interrupt + Enable + 4 + 1 + + + SYNCDIE + Synchronization Done + 5 + 1 + + + IFEIE + Serial Interface Error Interrupt + Enable + 6 + 1 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-only + 0x00000000 + + + RXNE + Read data register not + empty + 0 + 1 + + + CSRNE + Control Buffer register is not + empty + 1 + 1 + + + PERR + Parity error + 2 + 1 + + + OVR + Overrun error + 3 + 1 + + + SBD + Synchronization Block + Detected + 4 + 1 + + + SYNCD + Synchronization Done + 5 + 1 + + + FERR + Framing error + 6 + 1 + + + SERR + Synchronization error + 7 + 1 + + + TERR + Time-out error + 8 + 1 + + + WIDTH5 + Duration of 5 symbols counted with + SPDIF_CLK + 16 + 15 + + + + + IFCR + IFCR + Interrupt Flag Clear register + 0xC + 0x20 + write-only + 0x00000000 + + + PERRCF + Clears the Parity error + flag + 2 + 1 + + + OVRCF + Clears the Overrun error + flag + 3 + 1 + + + SBDCF + Clears the Synchronization Block + Detected flag + 4 + 1 + + + SYNCDCF + Clears the Synchronization Done + flag + 5 + 1 + + + + + DR_00 + DR_00 + Data input register + 0x10 + 0x20 + read-only + 0x00000000 + + + DR + Parity Error bit + 0 + 24 + + + PE + Parity Error bit + 24 + 1 + + + V + Validity bit + 25 + 1 + + + U + User bit + 26 + 1 + + + C + Channel Status bit + 27 + 1 + + + PT + Preamble Type + 28 + 2 + + + + + CSR + CSR + Channel Status register + 0x14 + 0x20 + read-only + 0x00000000 + + + USR + User data information + 0 + 16 + + + CS + Channel A status + information + 16 + 8 + + + SOB + Start Of Block + 24 + 1 + + + + + DIR + DIR + Debug Information register + 0x18 + 0x20 + read-only + 0x00000000 + + + THI + Threshold HIGH + 0 + 13 + + + TLO + Threshold LOW + 16 + 13 + + + + + VERR + VERR + SPDIFRX version register + 0x3F4 + 0x20 + read-only + 0x00000012 + + + MINREV + Minor revision + 0 + 4 + + + MAJREV + Major revision + 4 + 4 + + + + + IDR + IDR + SPDIFRX identification + register + 0x3F8 + 0x20 + read-only + 0x00130041 + + + ID + SPDIFRX identifier + 0 + 32 + + + + + SIDR + SIDR + SPDIFRX size identification + register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + Size identification + 0 + 32 + + + + + DR_01 + DR_01 + Data input register + DR_00 + 0x10 + 0x20 + read-only + 0x00000000 + + + PE + Parity Error bit + 0 + 1 + + + V + Validity bit + 1 + 1 + + + U + User bit + 2 + 1 + + + C + Channel Status bit + 3 + 1 + + + PT + Preamble Type + 4 + 2 + + + DR + Data value + 8 + 24 + + + + + DR_10 + DR_10 + Data input register + DR_00 + 0x10 + 0x20 + read-only + 0x00000000 + + + DRNL1 + Data value + 0 + 16 + + + DRNL2 + Data value + 16 + 16 + + + + + + + ADC3 + Analog to Digital Converter + ADC + 0x58026000 + + 0x0 + 0xD1 + registers + + + ADC3 + ADC3 global interrupt + 127 + + + + ISR + ISR + ADC interrupt and status + register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + ADC group injected contexts queue + overflow flag + 10 + 1 + + + AWD3 + ADC analog watchdog 3 flag + 9 + 1 + + + AWD2 + ADC analog watchdog 2 flag + 8 + 1 + + + AWD1 + ADC analog watchdog 1 flag + 7 + 1 + + + JEOS + ADC group injected end of sequence + conversions flag + 6 + 1 + + + JEOC + ADC group injected end of unitary + conversion flag + 5 + 1 + + + OVR + ADC group regular overrun + flag + 4 + 1 + + + EOS + ADC group regular end of sequence + conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary + conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling + flag + 1 + 1 + + + ADRDY + ADC ready flag + 0 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + ADC group injected contexts queue + overflow interrupt + 10 + 1 + + + AWD3IE + ADC analog watchdog 3 + interrupt + 9 + 1 + + + AWD2IE + ADC analog watchdog 2 + interrupt + 8 + 1 + + + AWD1IE + ADC analog watchdog 1 + interrupt + 7 + 1 + + + JEOSIE + ADC group injected end of sequence + conversions interrupt + 6 + 1 + + + JEOCIE + ADC group injected end of unitary + conversion interrupt + 5 + 1 + + + OVRIE + ADC group regular overrun + interrupt + 4 + 1 + + + EOSIE + ADC group regular end of sequence + conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary + conversion interrupt + 2 + 1 + + + EOSMPIE + ADC group regular end of sampling + interrupt + 1 + 1 + + + ADRDYIE + ADC ready interrupt + 0 + 1 + + + + + CR + CR + ADC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC calibration + 31 + 1 + + + ADCALDIF + ADC differential mode for + calibration + 30 + 1 + + + DEEPPWD + ADC deep power down enable + 29 + 1 + + + ADVREGEN + ADC voltage regulator + enable + 28 + 1 + + + LINCALRDYW6 + Linearity calibration ready Word + 6 + 27 + 1 + + + LINCALRDYW5 + Linearity calibration ready Word + 5 + 26 + 1 + + + LINCALRDYW4 + Linearity calibration ready Word + 4 + 25 + 1 + + + LINCALRDYW3 + Linearity calibration ready Word + 3 + 24 + 1 + + + LINCALRDYW2 + Linearity calibration ready Word + 2 + 23 + 1 + + + LINCALRDYW1 + Linearity calibration ready Word + 1 + 22 + 1 + + + ADCALLIN + Linearity calibration + 16 + 1 + + + BOOST + Boost mode control + 8 + 2 + + + JADSTP + ADC group injected conversion + stop + 5 + 1 + + + ADSTP + ADC group regular conversion + stop + 4 + 1 + + + JADSTART + ADC group injected conversion + start + 3 + 1 + + + ADSTART + ADC group regular conversion + start + 2 + 1 + + + ADDIS + ADC disable + 1 + 1 + + + ADEN + ADC enable + 0 + 1 + + + + + CFGR + CFGR + ADC configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + JQDIS + ADC group injected contexts queue + disable + 31 + 1 + + + AWDCH1CH + ADC analog watchdog 1 monitored channel + selection + 26 + 5 + + + JAUTO + ADC group injected automatic trigger + mode + 25 + 1 + + + JAWD1EN + ADC analog watchdog 1 enable on scope + ADC group injected + 24 + 1 + + + AWD1EN + ADC analog watchdog 1 enable on scope + ADC group regular + 23 + 1 + + + AWD1SGL + ADC analog watchdog 1 monitoring a + single channel or all channels + 22 + 1 + + + JQM + ADC group injected contexts queue + mode + 21 + 1 + + + JDISCEN + ADC group injected sequencer + discontinuous mode + 20 + 1 + + + DISCNUM + ADC group regular sequencer + discontinuous number of ranks + 17 + 3 + + + DISCEN + ADC group regular sequencer + discontinuous mode + 16 + 1 + + + AUTDLY + ADC low power auto wait + 14 + 1 + + + CONT + ADC group regular continuous conversion + mode + 13 + 1 + + + OVRMOD + ADC group regular overrun + configuration + 12 + 1 + + + EXTEN + ADC group regular external trigger + polarity + 10 + 2 + + + EXTSEL + ADC group regular external trigger + source + 5 + 5 + + + RES + ADC data resolution + 2 + 3 + + + DMNGT + ADC DMA transfer enable + 0 + 2 + + + + + CFGR2 + CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + ROVSE + ADC oversampler enable on scope ADC + group regular + 0 + 1 + + + JOVSE + ADC oversampler enable on scope ADC + group injected + 1 + 1 + + + OVSS + ADC oversampling shift + 5 + 4 + + + TROVS + ADC oversampling discontinuous mode + (triggered mode) for ADC group regular + 9 + 1 + + + ROVSM + Regular Oversampling mode + 10 + 1 + + + RSHIFT1 + Right-shift data after Offset 1 + correction + 11 + 1 + + + RSHIFT2 + Right-shift data after Offset 2 + correction + 12 + 1 + + + RSHIFT3 + Right-shift data after Offset 3 + correction + 13 + 1 + + + RSHIFT4 + Right-shift data after Offset 4 + correction + 14 + 1 + + + OSR + Oversampling ratio + 16 + 10 + + + LSHIFT + Left shift factor + 28 + 4 + + + + + SMPR1 + SMPR1 + ADC sampling time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + ADC channel 9 sampling time + selection + 27 + 3 + + + SMP8 + ADC channel 8 sampling time + selection + 24 + 3 + + + SMP7 + ADC channel 7 sampling time + selection + 21 + 3 + + + SMP6 + ADC channel 6 sampling time + selection + 18 + 3 + + + SMP5 + ADC channel 5 sampling time + selection + 15 + 3 + + + SMP4 + ADC channel 4 sampling time + selection + 12 + 3 + + + SMP3 + ADC channel 3 sampling time + selection + 9 + 3 + + + SMP2 + ADC channel 2 sampling time + selection + 6 + 3 + + + SMP1 + ADC channel 1 sampling time + selection + 3 + 3 + + + + + SMPR2 + SMPR2 + ADC sampling time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP19 + ADC channel 18 sampling time + selection + 27 + 3 + + + SMP18 + ADC channel 18 sampling time + selection + 24 + 3 + + + SMP17 + ADC channel 17 sampling time + selection + 21 + 3 + + + SMP16 + ADC channel 16 sampling time + selection + 18 + 3 + + + SMP15 + ADC channel 15 sampling time + selection + 15 + 3 + + + SMP14 + ADC channel 14 sampling time + selection + 12 + 3 + + + SMP13 + ADC channel 13 sampling time + selection + 9 + 3 + + + SMP12 + ADC channel 12 sampling time + selection + 6 + 3 + + + SMP11 + ADC channel 11 sampling time + selection + 3 + 3 + + + SMP10 + ADC channel 10 sampling time + selection + 0 + 3 + + + + + LTR1 + LTR1 + ADC analog watchdog 1 threshold + register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + LTR1 + ADC analog watchdog 1 threshold + low + 0 + 26 + + + + + LHTR1 + LHTR1 + ADC analog watchdog 2 threshold + register + 0x24 + 0x20 + read-write + 0x0FFF0000 + + + LHTR1 + ADC analog watchdog 2 threshold + low + 0 + 26 + + + + + SQR1 + SQR1 + ADC group regular sequencer ranks register + 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + ADC group regular sequencer rank + 4 + 24 + 5 + + + SQ3 + ADC group regular sequencer rank + 3 + 18 + 5 + + + SQ2 + ADC group regular sequencer rank + 2 + 12 + 5 + + + SQ1 + ADC group regular sequencer rank + 1 + 6 + 5 + + + L3 + L3 + 0 + 4 + + + + + SQR2 + SQR2 + ADC group regular sequencer ranks register + 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + ADC group regular sequencer rank + 9 + 24 + 5 + + + SQ8 + ADC group regular sequencer rank + 8 + 18 + 5 + + + SQ7 + ADC group regular sequencer rank + 7 + 12 + 5 + + + SQ6 + ADC group regular sequencer rank + 6 + 6 + 5 + + + SQ5 + ADC group regular sequencer rank + 5 + 0 + 5 + + + + + SQR3 + SQR3 + ADC group regular sequencer ranks register + 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + ADC group regular sequencer rank + 14 + 24 + 5 + + + SQ13 + ADC group regular sequencer rank + 13 + 18 + 5 + + + SQ12 + ADC group regular sequencer rank + 12 + 12 + 5 + + + SQ11 + ADC group regular sequencer rank + 11 + 6 + 5 + + + SQ10 + ADC group regular sequencer rank + 10 + 0 + 5 + + + + + SQR4 + SQR4 + ADC group regular sequencer ranks register + 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + ADC group regular sequencer rank + 16 + 6 + 5 + + + SQ15 + ADC group regular sequencer rank + 15 + 0 + 5 + + + + + DR + DR + ADC group regular conversion data + register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + ADC group regular conversion + data + 0 + 16 + + + + + JSQR + JSQR + ADC group injected sequencer + register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + ADC group injected sequencer rank + 4 + 27 + 5 + + + JSQ3 + ADC group injected sequencer rank + 3 + 21 + 5 + + + JSQ2 + ADC group injected sequencer rank + 2 + 15 + 5 + + + JSQ1 + ADC group injected sequencer rank + 1 + 9 + 5 + + + JEXTEN + ADC group injected external trigger + polarity + 7 + 2 + + + JEXTSEL + ADC group injected external trigger + source + 2 + 5 + + + JL + ADC group injected sequencer scan + length + 0 + 2 + + + + + OFR1 + OFR1 + ADC offset number 1 register + 0x60 + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + OFR2 + OFR2 + ADC offset number 2 register + 0x64 + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + OFR3 + OFR3 + ADC offset number 3 register + 0x68 + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + OFR4 + OFR4 + ADC offset number 4 register + 0x6C + 0x20 + read-write + 0x00000000 + + + SSATE + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel + selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset + level + 0 + 26 + + + + + JDR1 + JDR1 + ADC group injected sequencer rank 1 + register + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + ADC group injected sequencer rank 1 + conversion data + 0 + 32 + + + + + JDR2 + JDR2 + ADC group injected sequencer rank 2 + register + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + ADC group injected sequencer rank 2 + conversion data + 0 + 32 + + + + + JDR3 + JDR3 + ADC group injected sequencer rank 3 + register + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + ADC group injected sequencer rank 3 + conversion data + 0 + 32 + + + + + JDR4 + JDR4 + ADC group injected sequencer rank 4 + register + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + ADC group injected sequencer rank 4 + conversion data + 0 + 32 + + + + + AWD2CR + AWD2CR + ADC analog watchdog 2 configuration + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + ADC analog watchdog 2 monitored channel + selection + 0 + 20 + + + + + AWD3CR + AWD3CR + ADC analog watchdog 3 configuration + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + ADC analog watchdog 3 monitored channel + selection + 1 + 20 + + + + + DIFSEL + DIFSEL + ADC channel differential or single-ended + mode selection register + 0xC0 + 0x20 + read-write + 0x00000000 + + + DIFSEL + ADC channel differential or single-ended + mode for channel + 0 + 20 + + + + + CALFACT + CALFACT + ADC calibration factors + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + ADC calibration factor in differential + mode + 16 + 11 + + + CALFACT_S + ADC calibration factor in single-ended + mode + 0 + 11 + + + + + PCSEL + PCSEL + ADC pre channel selection + register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCSEL + Channel x (VINP[i]) pre + selection + 0 + 20 + + + + + LTR2 + LTR2 + ADC watchdog lower threshold register + 2 + 0xB0 + 0x20 + read-write + 0x00000000 + + + LTR2 + Analog watchdog 2 lower + threshold + 0 + 26 + + + + + HTR2 + HTR2 + ADC watchdog higher threshold register + 2 + 0xB4 + 0x20 + read-write + 0x00000000 + + + HTR2 + Analog watchdog 2 higher + threshold + 0 + 26 + + + + + LTR3 + LTR3 + ADC watchdog lower threshold register + 3 + 0xB8 + 0x20 + read-write + 0x00000000 + + + LTR3 + Analog watchdog 3 lower + threshold + 0 + 26 + + + + + HTR3 + HTR3 + ADC watchdog higher threshold register + 3 + 0xBC + 0x20 + read-write + 0x00000000 + + + HTR3 + Analog watchdog 3 higher + threshold + 0 + 26 + + + + + CALFACT2 + CALFACT2 + ADC Calibration Factor register + 2 + 0xC8 + 0x20 + read-write + 0x00000000 + + + LINCALFACT + Linearity Calibration + Factor + 0 + 30 + + + + + + + ADC1 + 0x40022000 + + + ADC2 + 0x40022100 + + + ADC3_Common + Analog-to-Digital Converter + ADC + 0x58026300 + + 0x0 + 0x100 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADRDY_MST + Master ADC ready + 0 + 1 + + + EOSMP_MST + End of Sampling phase flag of the master + ADC + 1 + 1 + + + EOC_MST + End of regular conversion of the master + ADC + 2 + 1 + + + EOS_MST + End of regular sequence flag of the + master ADC + 3 + 1 + + + OVR_MST + Overrun flag of the master + ADC + 4 + 1 + + + JEOC_MST + End of injected conversion flag of the + master ADC + 5 + 1 + + + JEOS_MST + End of injected sequence flag of the + master ADC + 6 + 1 + + + AWD1_MST + Analog watchdog 1 flag of the master + ADC + 7 + 1 + + + AWD2_MST + Analog watchdog 2 flag of the master + ADC + 8 + 1 + + + AWD3_MST + Analog watchdog 3 flag of the master + ADC + 9 + 1 + + + JQOVF_MST + Injected Context Queue Overflow flag of + the master ADC + 10 + 1 + + + ADRDY_SLV + Slave ADC ready + 16 + 1 + + + EOSMP_SLV + End of Sampling phase flag of the slave + ADC + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave + ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the + slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave + ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the + slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the + slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave + ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave + ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave + ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of + the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DUAL + Dual ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + DAMDF + Dual ADC Mode Data Format + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + PRESC + ADC prescaler + 18 + 4 + + + VREFEN + VREFINT enable + 22 + 1 + + + VSENSEEN + Temperature sensor enable + 23 + 1 + + + VBATEN + VBAT enable + 24 + 1 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave + ADC + 16 + 16 + + + RDATA_MST + Regular data of the master + ADC + 0 + 16 + + + + + CDR2 + CDR2 + ADC x common regular data register for + 32-bit dual mode + 0x10 + 0x20 + read-only + 0x00000000 + + + RDATA_ALT + Regular data of the master/slave + alternated ADCs + 0 + 32 + + + + + + + ADC12_Common + 0x40022300 + + ADC1_2 + ADC1 and ADC2 + 18 + + + + DMAMUX1 + DMAMUX + DMAMUX + 0x40020800 + + 0x0 + 0x400 + registers + + + DMAMUX1_OV + DMAMUX1 overrun interrupt + 102 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer + channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer + channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer + channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer + channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer + channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer + channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer + channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer + channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C8CR + C8CR + DMAMux - DMA request line multiplexer + channel x control register + 0x20 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C9CR + C9CR + DMAMux - DMA request line multiplexer + channel x control register + 0x24 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C10CR + C10CR + DMAMux - DMA request line multiplexer + channel x control register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C11CR + C11CR + DMAMux - DMA request line multiplexer + channel x control register + 0x2C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C12CR + C12CR + DMAMux - DMA request line multiplexer + channel x control register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C13CR + C13CR + DMAMux - DMA request line multiplexer + channel x control register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C14CR + C14CR + DMAMux - DMA request line multiplexer + channel x control register + 0x38 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + C15CR + C15CR + DMAMux - DMA request line multiplexer + channel x control register + 0x3C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line + selected + 0 + 8 + + + SOIE + Interrupt enable at synchronization + event overrun + 8 + 1 + + + EGE + Event generation + enable/disable + 9 + 1 + + + SE + Synchronous operating mode + enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector + Defines the synchronization event on the selected + synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward + Defines the number of DMA requests forwarded before + output event is generated. In synchronous mode, it + also defines the number of DMA requests to forward + after a synchronization event, then stop forwarding. + The actual number of DMA requests forwarded is + NBREQ+1. Note: This field can only be written when + both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input + selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x + control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x + control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x + control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x + control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG4CR + RG4CR + DMAMux - DMA request generator channel x + control register + 0x110 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG5CR + RG5CR + DMAMux - DMA request generator channel x + control register + 0x114 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG6CR + RG6CR + DMAMux - DMA request generator channel x + control register + 0x118 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RG7CR + RG7CR + DMAMux - DMA request generator channel x + control register + 0x11C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input + selected + 0 + 5 + + + OIE + Interrupt enable at trigger event + overrun + 8 + 1 + + + GE + DMA request generator channel + enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type + selection Defines the trigger event on the selected + DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate + Defines the number of DMA requests generated after a + trigger event, then stop generating. The actual + number of generated DMA requests is GNBREQ+1. Note: + This field can only be written when GE bit is + reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status + register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is + set when a trigger event occurs on DMA request + generator channel x, while the DMA request generator + counter value is lower than GNBREQ. The flag is + cleared by writing 1 to the corresponding COFx bit in + DMAMUX_RGCFR register. + 0 + 8 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag + register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon + setting, this bit clears the corresponding overrun + flag OFx in the DMAMUX_RGCSR register. + 0 + 8 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt + channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event + flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt + clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event + flag + 0 + 16 + + + + + + + CRC + Cryptographic processor + CRC + 0x58024C00 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 32 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + RESET + RESET bit + 0 + 1 + write-only + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + + + INIT + INIT + Initial CRC value + 0xC + 0x20 + read-write + 0x00000000 + + + CRC_INIT + Programmable initial CRC + value + 0 + 32 + + + + + POL + POL + CRC polynomial + 0x10 + 0x20 + read-write + 0x00000000 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + RCC + Reset and clock control + RCC + 0x58024400 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + clock control register + 0x0 + 0x20 + read-write + 0x00000083 + + + HSION + Internal high-speed clock + enable + 0 + 1 + + + HSIKERON + High Speed Internal clock enable in Stop + mode + 1 + 1 + + + HSIRDY + HSI clock ready flag + 2 + 1 + + + HSIDIV + HSI clock divider + 3 + 2 + + + HSIDIVF + HSI divider flag + 5 + 1 + + + CSION + CSI clock enable + 7 + 1 + + + CSIRDY + CSI clock ready flag + 8 + 1 + + + CSIKERON + CSI clock enable in Stop + mode + 9 + 1 + + + RC48ON + RC48 clock enable + 12 + 1 + + + RC48RDY + RC48 clock ready flag + 13 + 1 + + + D1CKRDY + D1 domain clocks ready + flag + 14 + 1 + + + D2CKRDY + D2 domain clocks ready + flag + 15 + 1 + + + HSEON + HSE clock enable + 16 + 1 + + + HSERDY + HSE clock ready flag + 17 + 1 + + + HSEBYP + HSE clock bypass + 18 + 1 + + + HSECSSON + HSE Clock Security System + enable + 19 + 1 + + + PLL1ON + PLL1 enable + 24 + 1 + + + PLL1RDY + PLL1 clock ready flag + 25 + 1 + + + PLL2ON + PLL2 enable + 26 + 1 + + + PLL2RDY + PLL2 clock ready flag + 27 + 1 + + + PLL3ON + PLL3 enable + 28 + 1 + + + PLL3RDY + PLL3 clock ready flag + 29 + 1 + + + + + ICSCR + ICSCR + RCC Internal Clock Source Calibration + Register + 0x4 + 0x20 + 0x40000000 + + + HSICAL + HSI clock calibration + 0 + 12 + read-only + + + HSITRIM + HSI clock trimming + 12 + 6 + read-write + + + CSICAL + CSI clock calibration + 18 + 8 + read-only + + + CSITRIM + CSI clock trimming + 26 + 5 + read-write + + + + + CRRCR + CRRCR + RCC Clock Recovery RC Register + 0x8 + 0x20 + read-only + 0x00000000 + + + RC48CAL + Internal RC 48 MHz clock + calibration + 0 + 10 + + + + + CFGR + CFGR + RCC Clock Configuration + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + SW + System clock switch + 0 + 3 + + + SWS + System clock switch status + 3 + 3 + + + STOPWUCK + System clock selection after a wake up + from system Stop + 6 + 1 + + + STOPKERWUCK + Kernel clock selection after a wake up + from system Stop + 7 + 1 + + + RTCPRE + HSE division factor for RTC + clock + 8 + 6 + + + HRTIMSEL + High Resolution Timer clock prescaler + selection + 14 + 1 + + + TIMPRE + Timers clocks prescaler + selection + 15 + 1 + + + MCO1PRE + MCO1 prescaler + 18 + 4 + + + MCO1SEL + Micro-controller clock output + 1 + 22 + 3 + + + MCO2PRE + MCO2 prescaler + 25 + 4 + + + MCO2SEL + Micro-controller clock output + 2 + 29 + 3 + + + + + D1CFGR + D1CFGR + RCC Domain 1 Clock Configuration + Register + 0x18 + 0x20 + read-write + 0x00000000 + + + HPRE + D1 domain AHB prescaler + 0 + 4 + + + D1PPRE + D1 domain APB3 prescaler + 4 + 3 + + + D1CPRE + D1 domain Core prescaler + 8 + 4 + + + + + D2CFGR + D2CFGR + RCC Domain 2 Clock Configuration + Register + 0x1C + 0x20 + read-write + 0x00000000 + + + D2PPRE1 + D2 domain APB1 prescaler + 4 + 3 + + + D2PPRE2 + D2 domain APB2 prescaler + 8 + 3 + + + + + D3CFGR + D3CFGR + RCC Domain 3 Clock Configuration + Register + 0x20 + 0x20 + read-write + 0x00000000 + + + D3PPRE + D3 domain APB4 prescaler + 4 + 3 + + + + + PLLCKSELR + PLLCKSELR + RCC PLLs Clock Source Selection + Register + 0x28 + 0x20 + read-write + 0x02020200 + + + PLLSRC + DIVMx and PLLs clock source + selection + 0 + 2 + + + DIVM1 + Prescaler for PLL1 + 4 + 6 + + + DIVM2 + Prescaler for PLL2 + 12 + 6 + + + DIVM3 + Prescaler for PLL3 + 20 + 6 + + + + + PLLCFGR + PLLCFGR + RCC PLLs Configuration + Register + 0x2C + 0x20 + read-write + 0x01FF0000 + + + PLL1FRACEN + PLL1 fractional latch + enable + 0 + 1 + + + PLL1VCOSEL + PLL1 VCO selection + 1 + 1 + + + PLL1RGE + PLL1 input frequency range + 2 + 2 + + + PLL2FRACEN + PLL2 fractional latch + enable + 4 + 1 + + + PLL2VCOSEL + PLL2 VCO selection + 5 + 1 + + + PLL2RGE + PLL2 input frequency range + 6 + 2 + + + PLL3FRACEN + PLL3 fractional latch + enable + 8 + 1 + + + PLL3VCOSEL + PLL3 VCO selection + 9 + 1 + + + PLL3RGE + PLL3 input frequency range + 10 + 2 + + + DIVP1EN + PLL1 DIVP divider output + enable + 16 + 1 + + + DIVQ1EN + PLL1 DIVQ divider output + enable + 17 + 1 + + + DIVR1EN + PLL1 DIVR divider output + enable + 18 + 1 + + + DIVP2EN + PLL2 DIVP divider output + enable + 19 + 1 + + + DIVQ2EN + PLL2 DIVQ divider output + enable + 20 + 1 + + + DIVR2EN + PLL2 DIVR divider output + enable + 21 + 1 + + + DIVP3EN + PLL3 DIVP divider output + enable + 22 + 1 + + + DIVQ3EN + PLL3 DIVQ divider output + enable + 23 + 1 + + + DIVR3EN + PLL3 DIVR divider output + enable + 24 + 1 + + + + + PLL1DIVR + PLL1DIVR + RCC PLL1 Dividers Configuration + Register + 0x30 + 0x20 + read-write + 0x01010280 + + + DIVN1 + Multiplication factor for PLL1 + VCO + 0 + 9 + + + DIVP1 + PLL1 DIVP division factor + 9 + 7 + + + DIVQ1 + PLL1 DIVQ division factor + 16 + 7 + + + DIVR1 + PLL1 DIVR division factor + 24 + 7 + + + + + PLL1FRACR + PLL1FRACR + RCC PLL1 Fractional Divider + Register + 0x34 + 0x20 + read-write + 0x00000000 + + + FRACN1 + Fractional part of the multiplication + factor for PLL1 VCO + 3 + 13 + + + + + PLL2DIVR + PLL2DIVR + RCC PLL2 Dividers Configuration + Register + 0x38 + 0x20 + read-write + 0x01010280 + + + DIVN1 + Multiplication factor for PLL1 + VCO + 0 + 9 + + + DIVP1 + PLL1 DIVP division factor + 9 + 7 + + + DIVQ1 + PLL1 DIVQ division factor + 16 + 7 + + + DIVR1 + PLL1 DIVR division factor + 24 + 7 + + + + + PLL2FRACR + PLL2FRACR + RCC PLL2 Fractional Divider + Register + 0x3C + 0x20 + read-write + 0x00000000 + + + FRACN2 + Fractional part of the multiplication + factor for PLL VCO + 3 + 13 + + + + + PLL3DIVR + PLL3DIVR + RCC PLL3 Dividers Configuration + Register + 0x40 + 0x20 + read-write + 0x01010280 + + + DIVN3 + Multiplication factor for PLL1 + VCO + 0 + 9 + + + DIVP3 + PLL DIVP division factor + 9 + 7 + + + DIVQ3 + PLL DIVQ division factor + 16 + 7 + + + DIVR3 + PLL DIVR division factor + 24 + 7 + + + + + PLL3FRACR + PLL3FRACR + RCC PLL3 Fractional Divider + Register + 0x44 + 0x20 + read-write + 0x00000000 + + + FRACN3 + Fractional part of the multiplication + factor for PLL3 VCO + 3 + 13 + + + + + D1CCIPR + D1CCIPR + RCC Domain 1 Kernel Clock Configuration + Register + 0x4C + 0x20 + read-write + 0x00000000 + + + FMCSRC + FMC kernel clock source + selection + 0 + 2 + + + QSPISRC + QUADSPI kernel clock source + selection + 4 + 2 + + + SDMMCSRC + SDMMC kernel clock source + selection + 16 + 1 + + + CKPERSRC + per_ck clock source + selection + 28 + 2 + + + + + D2CCIP1R + D2CCIP1R + RCC Domain 2 Kernel Clock Configuration + Register + 0x50 + 0x20 + read-write + 0x00000000 + + + SAI1SRC + SAI1 and DFSDM1 kernel Aclk clock source + selection + 0 + 3 + + + SAI23SRC + SAI2 and SAI3 kernel clock source + selection + 6 + 3 + + + SPI123SRC + SPI/I2S1,2 and 3 kernel clock source + selection + 12 + 3 + + + SPI45SRC + SPI4 and 5 kernel clock source + selection + 16 + 3 + + + SPDIFSRC + SPDIFRX kernel clock source + selection + 20 + 2 + + + DFSDM1SRC + DFSDM1 kernel Clk clock source + selection + 24 + 1 + + + FDCANSRC + FDCAN kernel clock source + selection + 28 + 2 + + + SWPSRC + SWPMI kernel clock source + selection + 31 + 1 + + + + + D2CCIP2R + D2CCIP2R + RCC Domain 2 Kernel Clock Configuration + Register + 0x54 + 0x20 + read-write + 0x00000000 + + + USART234578SRC + USART2/3, UART4,5, 7/8 (APB1) kernel + clock source selection + 0 + 3 + + + USART16SRC + USART1 and 6 kernel clock source + selection + 3 + 3 + + + RNGSRC + RNG kernel clock source + selection + 8 + 2 + + + I2C123SRC + I2C1,2,3 kernel clock source + selection + 12 + 2 + + + USBSRC + USBOTG 1 and 2 kernel clock source + selection + 20 + 2 + + + CECSRC + HDMI-CEC kernel clock source + selection + 22 + 2 + + + LPTIM1SRC + LPTIM1 kernel clock source + selection + 28 + 3 + + + + + D3CCIPR + D3CCIPR + RCC Domain 3 Kernel Clock Configuration + Register + 0x58 + 0x20 + read-write + 0x00000000 + + + LPUART1SRC + LPUART1 kernel clock source + selection + 0 + 3 + + + I2C4SRC + I2C4 kernel clock source + selection + 8 + 2 + + + LPTIM2SRC + LPTIM2 kernel clock source + selection + 10 + 3 + + + LPTIM345SRC + LPTIM3,4,5 kernel clock source + selection + 13 + 3 + + + ADCSRC + SAR ADC kernel clock source + selection + 16 + 2 + + + SAI4ASRC + Sub-Block A of SAI4 kernel clock source + selection + 21 + 3 + + + SAI4BSRC + Sub-Block B of SAI4 kernel clock source + selection + 24 + 3 + + + SPI6SRC + SPI6 kernel clock source + selection + 28 + 3 + + + + + CIER + CIER + RCC Clock Source Interrupt Enable + Register + 0x60 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI ready Interrupt Enable + 0 + 1 + + + LSERDYIE + LSE ready Interrupt Enable + 1 + 1 + + + HSIRDYIE + HSI ready Interrupt Enable + 2 + 1 + + + HSERDYIE + HSE ready Interrupt Enable + 3 + 1 + + + CSIRDYIE + CSI ready Interrupt Enable + 4 + 1 + + + RC48RDYIE + RC48 ready Interrupt + Enable + 5 + 1 + + + PLL1RDYIE + PLL1 ready Interrupt + Enable + 6 + 1 + + + PLL2RDYIE + PLL2 ready Interrupt + Enable + 7 + 1 + + + PLL3RDYIE + PLL3 ready Interrupt + Enable + 8 + 1 + + + LSECSSIE + LSE clock security system Interrupt + Enable + 9 + 1 + + + + + CIFR + CIFR + RCC Clock Source Interrupt Flag + Register + 0x64 + 0x20 + read-write + 0x00000000 + + + LSIRDYF + LSI ready Interrupt Flag + 0 + 1 + + + LSERDYF + LSE ready Interrupt Flag + 1 + 1 + + + HSIRDYF + HSI ready Interrupt Flag + 2 + 1 + + + HSERDYF + HSE ready Interrupt Flag + 3 + 1 + + + CSIRDY + CSI ready Interrupt Flag + 4 + 1 + + + RC48RDYF + RC48 ready Interrupt Flag + 5 + 1 + + + PLL1RDYF + PLL1 ready Interrupt Flag + 6 + 1 + + + PLL2RDYF + PLL2 ready Interrupt Flag + 7 + 1 + + + PLL3RDYF + PLL3 ready Interrupt Flag + 8 + 1 + + + LSECSSF + LSE clock security system Interrupt + Flag + 9 + 1 + + + HSECSSF + HSE clock security system Interrupt + Flag + 10 + 1 + + + + + CICR + CICR + RCC Clock Source Interrupt Clear + Register + 0x68 + 0x20 + read-write + 0x00000000 + + + LSIRDYC + LSI ready Interrupt Clear + 0 + 1 + + + LSERDYC + LSE ready Interrupt Clear + 1 + 1 + + + HSIRDYC + HSI ready Interrupt Clear + 2 + 1 + + + HSERDYC + HSE ready Interrupt Clear + 3 + 1 + + + HSE_ready_Interrupt_Clear + CSI ready Interrupt Clear + 4 + 1 + + + RC48RDYC + RC48 ready Interrupt Clear + 5 + 1 + + + PLL1RDYC + PLL1 ready Interrupt Clear + 6 + 1 + + + PLL2RDYC + PLL2 ready Interrupt Clear + 7 + 1 + + + PLL3RDYC + PLL3 ready Interrupt Clear + 8 + 1 + + + LSECSSC + LSE clock security system Interrupt + Clear + 9 + 1 + + + HSECSSC + HSE clock security system Interrupt + Clear + 10 + 1 + + + + + BDCR + BDCR + RCC Backup Domain Control + Register + 0x70 + 0x20 + read-write + 0x00000000 + + + LSEON + LSE oscillator enabled + 0 + 1 + + + LSERDY + LSE oscillator ready + 1 + 1 + + + LSEBYP + LSE oscillator bypass + 2 + 1 + + + LSEDRV + LSE oscillator driving + capability + 3 + 2 + + + LSECSSON + LSE clock security system + enable + 5 + 1 + + + LSECSSD + LSE clock security system failure + detection + 6 + 1 + + + RTCSRC + RTC clock source selection + 8 + 2 + + + RTCEN + RTC clock enable + 15 + 1 + + + VSWRST + VSwitch domain software + reset + 16 + 1 + + + + + CSR + CSR + RCC Clock Control and Status + Register + 0x74 + 0x20 + read-write + 0x00000000 + + + LSION + LSI oscillator enable + 0 + 1 + + + LSIRDY + LSI oscillator ready + 1 + 1 + + + + + AHB3RSTR + AHB3RSTR + RCC AHB3 Reset Register + 0x7C + 0x20 + read-write + 0x00000000 + + + MDMARST + MDMA block reset + 0 + 1 + + + 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TIM16 peripheral clock + enable + 17 + 1 + + + TIM15EN + TIM15 peripheral clock + enable + 16 + 1 + + + TIM17EN + TIM17 peripheral clock + enable + 18 + 1 + + + SPI5EN + SPI5 Peripheral Clocks + Enable + 20 + 1 + + + SAI1EN + SAI1 Peripheral Clocks + Enable + 22 + 1 + + + SAI2EN + SAI2 Peripheral Clocks + Enable + 23 + 1 + + + SAI3EN + SAI3 Peripheral Clocks + Enable + 24 + 1 + + + DFSDM1EN + DFSDM1 Peripheral Clocks + Enable + 28 + 1 + + + HRTIMEN + HRTIM peripheral clock + enable + 29 + 1 + + + + + APB4ENR + APB4ENR + RCC APB4 Clock Register + 0xF4 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clock + enable + 1 + 1 + + + LPUART1EN + LPUART1 Peripheral Clocks + Enable + 3 + 1 + + + SPI6EN + SPI6 Peripheral Clocks + Enable + 5 + 1 + + + I2C4EN + I2C4 Peripheral Clocks + Enable + 7 + 1 + + + LPTIM2EN + LPTIM2 Peripheral Clocks + Enable + 9 + 1 + + + LPTIM3EN + LPTIM3 Peripheral Clocks + Enable + 10 + 1 + + + LPTIM4EN + LPTIM4 Peripheral Clocks + Enable + 11 + 1 + + + LPTIM5EN + LPTIM5 Peripheral Clocks + Enable + 12 + 1 + + + COMP12EN + COMP1/2 peripheral clock + enable + 14 + 1 + + + VREFEN + VREF peripheral clock + enable + 15 + 1 + + + RTCAPBEN + RTC APB Clock Enable + 16 + 1 + + + SAI4EN + SAI4 Peripheral Clocks + Enable + 21 + 1 + + + + + C1_APB4ENR + C1_APB4ENR + RCC APB4 Clock Register + 0x154 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clock + enable + 1 + 1 + + + LPUART1EN + LPUART1 Peripheral Clocks + Enable + 3 + 1 + + + SPI6EN + SPI6 Peripheral Clocks + Enable + 5 + 1 + + + I2C4EN + I2C4 Peripheral Clocks + Enable + 7 + 1 + + + LPTIM2EN + LPTIM2 Peripheral Clocks + Enable + 9 + 1 + + + LPTIM3EN + LPTIM3 Peripheral Clocks + Enable + 10 + 1 + + + LPTIM4EN + LPTIM4 Peripheral Clocks + Enable + 11 + 1 + + + LPTIM5EN + LPTIM5 Peripheral Clocks + Enable + 12 + 1 + + + COMP12EN + COMP1/2 peripheral clock + enable + 14 + 1 + + + VREFEN + VREF peripheral clock + enable + 15 + 1 + + + RTCAPBEN + RTC APB Clock Enable + 16 + 1 + + + SAI4EN + SAI4 Peripheral Clocks + Enable + 21 + 1 + + + + + C1_AHB3LPENR + C1_AHB3LPENR + RCC AHB3 Sleep Clock Register + 0x15C + 0x20 + read-write + 0x00000000 + + + MDMALPEN + MDMA Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2DLPEN + DMA2D Clock Enable During CSleep + Mode + 4 + 1 + + + JPGDECLPEN + JPGDEC Clock Enable During CSleep + Mode + 5 + 1 + + + FLITFLPEN + FLITF Clock Enable During CSleep + Mode + 8 + 1 + + + FMCLPEN + FMC Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + QSPILPEN + QUADSPI and QUADSPI Delay Clock Enable + During CSleep Mode + 14 + 1 + + + SDMMC1LPEN + SDMMC1 and SDMMC1 Delay Clock Enable + During CSleep Mode + 16 + 1 + + + D1DTCM1LPEN + D1DTCM1 Block Clock Enable During CSleep + mode + 28 + 1 + + + DTCM2LPEN + D1 DTCM2 Block Clock Enable During + CSleep mode + 29 + 1 + + + ITCMLPEN + D1ITCM Block Clock Enable During CSleep + mode + 30 + 1 + + + AXISRAMLPEN + AXISRAM Block Clock Enable During CSleep + mode + 31 + 1 + + + + + AHB3LPENR + AHB3LPENR + RCC AHB3 Sleep Clock Register + 0xFC + 0x20 + read-write + 0x00000000 + + + MDMALPEN + MDMA Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2DLPEN + DMA2D Clock Enable During CSleep + Mode + 4 + 1 + + + JPGDECLPEN + JPGDEC Clock Enable During CSleep + Mode + 5 + 1 + + + FLITFLPEN + FLITF Clock Enable During CSleep + Mode + 8 + 1 + + + FMCLPEN + FMC Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + QSPILPEN + QUADSPI and QUADSPI Delay Clock Enable + During CSleep Mode + 14 + 1 + + + SDMMC1LPEN + SDMMC1 and SDMMC1 Delay Clock Enable + During CSleep Mode + 16 + 1 + + + D1DTCM1LPEN + D1DTCM1 Block Clock Enable During CSleep + mode + 28 + 1 + + + DTCM2LPEN + D1 DTCM2 Block Clock Enable During + CSleep mode + 29 + 1 + + + ITCMLPEN + D1ITCM Block Clock Enable During CSleep + mode + 30 + 1 + + + AXISRAMLPEN + AXISRAM Block Clock Enable During CSleep + mode + 31 + 1 + + + + + AHB1LPENR + AHB1LPENR + RCC AHB1 Sleep Clock Register + 0x100 + 0x20 + read-write + 0x00000000 + + + DMA1LPEN + DMA1 Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2LPEN + DMA2 Clock Enable During CSleep + Mode + 1 + 1 + + + ADC12LPEN + ADC1/2 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + ETH1MACLPEN + Ethernet MAC bus interface Clock Enable + During CSleep Mode + 15 + 1 + + + ETH1TXLPEN + Ethernet Transmission Clock Enable + During CSleep Mode + 16 + 1 + + + ETH1RXLPEN + Ethernet Reception Clock Enable During + CSleep Mode + 17 + 1 + + + USB1OTGLPEN + USB1OTG peripheral clock enable during + CSleep mode + 25 + 1 + + + USB1ULPILPEN + USB_PHY1 clock enable during CSleep + mode + 26 + 1 + + + USB2OTGLPEN + USB2OTG peripheral clock enable during + CSleep mode + 27 + 1 + + + USB2ULPILPEN + USB_PHY2 clocks enable during CSleep + mode + 28 + 1 + + + + + C1_AHB1LPENR + C1_AHB1LPENR + RCC AHB1 Sleep Clock Register + 0x160 + 0x20 + read-write + 0x00000000 + + + DMA1LPEN + DMA1 Clock Enable During CSleep + Mode + 0 + 1 + + + DMA2LPEN + DMA2 Clock Enable During CSleep + Mode + 1 + 1 + + + ADC12LPEN + ADC1/2 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + ETH1MACLPEN + Ethernet MAC bus interface Clock Enable + During CSleep Mode + 15 + 1 + + + ETH1TXLPEN + Ethernet Transmission Clock Enable + During CSleep Mode + 16 + 1 + + + ETH1RXLPEN + Ethernet Reception Clock Enable During + CSleep Mode + 17 + 1 + + + USB1OTGLPEN + USB1OTG peripheral clock enable during + CSleep mode + 25 + 1 + + + USB1ULPILPEN + USB_PHY1 clock enable during CSleep + mode + 26 + 1 + + + USB2OTGLPEN + USB2OTG peripheral clock enable during + CSleep mode + 27 + 1 + + + USB2ULPILPEN + USB_PHY2 clocks enable during CSleep + mode + 28 + 1 + + + + + C1_AHB2LPENR + C1_AHB2LPENR + RCC AHB2 Sleep Clock Register + 0x164 + 0x20 + read-write + 0x00000000 + + + CAMITFLPEN + CAMITF peripheral clock enable during + CSleep mode + 0 + 1 + + + CRYPTLPEN + CRYPT peripheral clock enable during + CSleep mode + 4 + 1 + + + HASHLPEN + HASH peripheral clock enable during + CSleep mode + 5 + 1 + + + SDMMC2LPEN + SDMMC2 and SDMMC2 Delay Clock Enable + During CSleep Mode + 9 + 1 + + + RNGLPEN + RNG peripheral clock enable during + CSleep mode + 6 + 1 + + + SRAM1LPEN + SRAM1 Clock Enable During CSleep + Mode + 29 + 1 + + + SRAM2LPEN + SRAM2 Clock Enable During CSleep + Mode + 30 + 1 + + + SRAM3LPEN + SRAM3 Clock Enable During CSleep + Mode + 31 + 1 + + + + + AHB2LPENR + AHB2LPENR + RCC AHB2 Sleep Clock Register + 0x104 + 0x20 + read-write + 0x00000000 + + + CAMITFLPEN + CAMITF peripheral clock enable during + CSleep mode + 0 + 1 + + + CRYPTLPEN + CRYPT peripheral clock enable during + CSleep mode + 4 + 1 + + + HASHLPEN + HASH peripheral clock enable during + CSleep mode + 5 + 1 + + + SDMMC2LPEN + SDMMC2 and SDMMC2 Delay Clock Enable + During CSleep Mode + 9 + 1 + + + RNGLPEN + RNG peripheral clock enable during + CSleep mode + 6 + 1 + + + SRAM1LPEN + SRAM1 Clock Enable During CSleep + Mode + 29 + 1 + + + SRAM2LPEN + SRAM2 Clock Enable During CSleep + Mode + 30 + 1 + + + SRAM3LPEN + SRAM3 Clock Enable During CSleep + Mode + 31 + 1 + + + + + AHB4LPENR + AHB4LPENR + RCC AHB4 Sleep Clock Register + 0x108 + 0x20 + read-write + 0x00000000 + + + GPIOALPEN + GPIO peripheral clock enable during + CSleep mode + 0 + 1 + + + GPIOBLPEN + GPIO peripheral clock enable during + CSleep mode + 1 + 1 + + + GPIOCLPEN + GPIO peripheral clock enable during + CSleep mode + 2 + 1 + + + GPIODLPEN + GPIO peripheral clock enable during + CSleep mode + 3 + 1 + + + GPIOELPEN + GPIO peripheral clock enable during + CSleep mode + 4 + 1 + + + GPIOFLPEN + GPIO peripheral clock enable during + CSleep mode + 5 + 1 + + + GPIOGLPEN + GPIO peripheral clock enable during + CSleep mode + 6 + 1 + + + GPIOHLPEN + GPIO peripheral clock enable during + CSleep mode + 7 + 1 + + + GPIOILPEN + GPIO peripheral clock enable during + CSleep mode + 8 + 1 + + + GPIOJLPEN + GPIO peripheral clock enable during + CSleep mode + 9 + 1 + + + GPIOKLPEN + GPIO peripheral clock enable during + CSleep mode + 10 + 1 + + + CRCLPEN + CRC peripheral clock enable during + CSleep mode + 19 + 1 + + + BDMALPEN + BDMA Clock Enable During CSleep + Mode + 21 + 1 + + + ADC3LPEN + ADC3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + BKPRAMLPEN + Backup RAM Clock Enable During CSleep + Mode + 28 + 1 + + + SRAM4LPEN + SRAM4 Clock Enable During CSleep + Mode + 29 + 1 + + + + + C1_AHB4LPENR + C1_AHB4LPENR + RCC AHB4 Sleep Clock Register + 0x168 + 0x20 + read-write + 0x00000000 + + + GPIOALPEN + GPIO peripheral clock enable during + CSleep mode + 0 + 1 + + + GPIOBLPEN + GPIO peripheral clock enable during + CSleep mode + 1 + 1 + + + GPIOCLPEN + GPIO peripheral clock enable during + CSleep mode + 2 + 1 + + + GPIODLPEN + GPIO peripheral clock enable during + CSleep mode + 3 + 1 + + + GPIOELPEN + GPIO peripheral clock enable during + CSleep mode + 4 + 1 + + + GPIOFLPEN + GPIO peripheral clock enable during + CSleep mode + 5 + 1 + + + GPIOGLPEN + GPIO peripheral clock enable during + CSleep mode + 6 + 1 + + + GPIOHLPEN + GPIO peripheral clock enable during + CSleep mode + 7 + 1 + + + GPIOILPEN + GPIO peripheral clock enable during + CSleep mode + 8 + 1 + + + GPIOJLPEN + GPIO peripheral clock enable during + CSleep mode + 9 + 1 + + + GPIOKLPEN + GPIO peripheral clock enable during + CSleep mode + 10 + 1 + + + CRCLPEN + CRC peripheral clock enable during + CSleep mode + 19 + 1 + + + BDMALPEN + BDMA Clock Enable During CSleep + Mode + 21 + 1 + + + ADC3LPEN + ADC3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + BKPRAMLPEN + Backup RAM Clock Enable During CSleep + Mode + 28 + 1 + + + SRAM4LPEN + SRAM4 Clock Enable During CSleep + Mode + 29 + 1 + + + + + C1_APB3LPENR + C1_APB3LPENR + RCC APB3 Sleep Clock Register + 0x16C + 0x20 + read-write + 0x00000000 + + + LTDCLPEN + LTDC peripheral clock enable during + CSleep mode + 3 + 1 + + + WWDG1LPEN + WWDG1 Clock Enable During CSleep + Mode + 6 + 1 + + + + + APB3LPENR + APB3LPENR + RCC APB3 Sleep Clock Register + 0x10C + 0x20 + read-write + 0x00000000 + + + LTDCLPEN + LTDC peripheral clock enable during + CSleep mode + 3 + 1 + + + WWDG1LPEN + WWDG1 Clock Enable During CSleep + Mode + 6 + 1 + + + + + APB1LLPENR + APB1LLPENR + RCC APB1 Low Sleep Clock + Register + 0x110 + 0x20 + read-write + 0x00000000 + + + TIM2LPEN + TIM2 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM3LPEN + TIM3 peripheral clock enable during + CSleep mode + 1 + 1 + + + TIM4LPEN + TIM4 peripheral clock enable during + CSleep mode + 2 + 1 + + + TIM5LPEN + TIM5 peripheral clock enable during + CSleep mode + 3 + 1 + + + TIM6LPEN + TIM6 peripheral clock enable during + CSleep mode + 4 + 1 + + + TIM7LPEN + TIM7 peripheral clock enable during + CSleep mode + 5 + 1 + + + TIM12LPEN + TIM12 peripheral clock enable during + CSleep mode + 6 + 1 + + + TIM13LPEN + TIM13 peripheral clock enable during + CSleep mode + 7 + 1 + + + TIM14LPEN + TIM14 peripheral clock enable during + CSleep mode + 8 + 1 + + + LPTIM1LPEN + LPTIM1 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + SPI2LPEN + SPI2 Peripheral Clocks Enable During + CSleep Mode + 14 + 1 + + + SPI3LPEN + SPI3 Peripheral Clocks Enable During + CSleep Mode + 15 + 1 + + + SPDIFRXLPEN + SPDIFRX Peripheral Clocks Enable During + CSleep Mode + 16 + 1 + + + USART2LPEN + USART2 Peripheral Clocks Enable During + CSleep Mode + 17 + 1 + + + USART3LPEN + USART3 Peripheral Clocks Enable During + CSleep Mode + 18 + 1 + + + UART4LPEN + UART4 Peripheral Clocks Enable During + CSleep Mode + 19 + 1 + + + UART5LPEN + UART5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + I2C1LPEN + I2C1 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + I2C2LPEN + I2C2 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + I2C3LPEN + I2C3 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + HDMICECLPEN + HDMI-CEC Peripheral Clocks Enable During + CSleep Mode + 27 + 1 + + + DAC12LPEN + DAC1/2 peripheral clock enable during + CSleep mode + 29 + 1 + + + USART7LPEN + USART7 Peripheral Clocks Enable During + CSleep Mode + 30 + 1 + + + USART8LPEN + USART8 Peripheral Clocks Enable During + CSleep Mode + 31 + 1 + + + + + C1_APB1LLPENR + C1_APB1LLPENR + RCC APB1 Low Sleep Clock + Register + 0x170 + 0x20 + read-write + 0x00000000 + + + TIM2LPEN + TIM2 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM3LPEN + TIM3 peripheral clock enable during + CSleep mode + 1 + 1 + + + TIM4LPEN + TIM4 peripheral clock enable during + CSleep mode + 2 + 1 + + + TIM5LPEN + TIM5 peripheral clock enable during + CSleep mode + 3 + 1 + + + TIM6LPEN + TIM6 peripheral clock enable during + CSleep mode + 4 + 1 + + + TIM7LPEN + TIM7 peripheral clock enable during + CSleep mode + 5 + 1 + + + TIM12LPEN + TIM12 peripheral clock enable during + CSleep mode + 6 + 1 + + + TIM13LPEN + TIM13 peripheral clock enable during + CSleep mode + 7 + 1 + + + TIM14LPEN + TIM14 peripheral clock enable during + CSleep mode + 8 + 1 + + + LPTIM1LPEN + LPTIM1 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + SPI2LPEN + SPI2 Peripheral Clocks Enable During + CSleep Mode + 14 + 1 + + + SPI3LPEN + SPI3 Peripheral Clocks Enable During + CSleep Mode + 15 + 1 + + + SPDIFRXLPEN + SPDIFRX Peripheral Clocks Enable During + CSleep Mode + 16 + 1 + + + USART2LPEN + USART2 Peripheral Clocks Enable During + CSleep Mode + 17 + 1 + + + USART3LPEN + USART3 Peripheral Clocks Enable During + CSleep Mode + 18 + 1 + + + UART4LPEN + UART4 Peripheral Clocks Enable During + CSleep Mode + 19 + 1 + + + UART5LPEN + UART5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + I2C1LPEN + I2C1 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + I2C2LPEN + I2C2 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + I2C3LPEN + I2C3 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + HDMICECLPEN + HDMI-CEC Peripheral Clocks Enable During + CSleep Mode + 27 + 1 + + + DAC12LPEN + DAC1/2 peripheral clock enable during + CSleep mode + 29 + 1 + + + USART7LPEN + USART7 Peripheral Clocks Enable During + CSleep Mode + 30 + 1 + + + USART8LPEN + USART8 Peripheral Clocks Enable During + CSleep Mode + 31 + 1 + + + + + C1_APB1HLPENR + C1_APB1HLPENR + RCC APB1 High Sleep Clock + Register + 0x174 + 0x20 + read-write + 0x00000000 + + + CRSLPEN + Clock Recovery System peripheral clock + enable during CSleep mode + 1 + 1 + + + SWPLPEN + SWPMI Peripheral Clocks Enable During + CSleep Mode + 2 + 1 + + + OPAMPLPEN + OPAMP peripheral clock enable during + CSleep mode + 4 + 1 + + + MDIOSLPEN + MDIOS peripheral clock enable during + CSleep mode + 5 + 1 + + + FDCANLPEN + FDCAN Peripheral Clocks Enable During + CSleep Mode + 8 + 1 + + + + + APB1HLPENR + APB1HLPENR + RCC APB1 High Sleep Clock + Register + 0x114 + 0x20 + read-write + 0x00000000 + + + CRSLPEN + Clock Recovery System peripheral clock + enable during CSleep mode + 1 + 1 + + + SWPLPEN + SWPMI Peripheral Clocks Enable During + CSleep Mode + 2 + 1 + + + OPAMPLPEN + OPAMP peripheral clock enable during + CSleep mode + 4 + 1 + + + MDIOSLPEN + MDIOS peripheral clock enable during + CSleep mode + 5 + 1 + + + FDCANLPEN + FDCAN Peripheral Clocks Enable During + CSleep Mode + 8 + 1 + + + + + APB2LPENR + APB2LPENR + RCC APB2 Sleep Clock Register + 0x118 + 0x20 + read-write + 0x00000000 + + + TIM1LPEN + TIM1 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM8LPEN + TIM8 peripheral clock enable during + CSleep mode + 1 + 1 + + + USART1LPEN + USART1 Peripheral Clocks Enable During + CSleep Mode + 4 + 1 + + + USART6LPEN + USART6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + SPI1LPEN + SPI1 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + SPI4LPEN + SPI4 Peripheral Clocks Enable During + CSleep Mode + 13 + 1 + + + TIM15LPEN + TIM15 peripheral clock enable during + CSleep mode + 16 + 1 + + + TIM16LPEN + TIM16 peripheral clock enable during + CSleep mode + 17 + 1 + + + TIM17LPEN + TIM17 peripheral clock enable during + CSleep mode + 18 + 1 + + + SPI5LPEN + SPI5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + SAI1LPEN + SAI1 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + SAI2LPEN + SAI2 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + SAI3LPEN + SAI3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + DFSDM1LPEN + DFSDM1 Peripheral Clocks Enable During + CSleep Mode + 28 + 1 + + + HRTIMLPEN + HRTIM peripheral clock enable during + CSleep mode + 29 + 1 + + + + + C1_APB2LPENR + C1_APB2LPENR + RCC APB2 Sleep Clock Register + 0x178 + 0x20 + read-write + 0x00000000 + + + TIM1LPEN + TIM1 peripheral clock enable during + CSleep mode + 0 + 1 + + + TIM8LPEN + TIM8 peripheral clock enable during + CSleep mode + 1 + 1 + + + USART1LPEN + USART1 Peripheral Clocks Enable During + CSleep Mode + 4 + 1 + + + USART6LPEN + USART6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + SPI1LPEN + SPI1 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + SPI4LPEN + SPI4 Peripheral Clocks Enable During + CSleep Mode + 13 + 1 + + + TIM15LPEN + TIM15 peripheral clock enable during + CSleep mode + 16 + 1 + + + TIM16LPEN + TIM16 peripheral clock enable during + CSleep mode + 17 + 1 + + + TIM17LPEN + TIM17 peripheral clock enable during + CSleep mode + 18 + 1 + + + SPI5LPEN + SPI5 Peripheral Clocks Enable During + CSleep Mode + 20 + 1 + + + SAI1LPEN + SAI1 Peripheral Clocks Enable During + CSleep Mode + 22 + 1 + + + SAI2LPEN + SAI2 Peripheral Clocks Enable During + CSleep Mode + 23 + 1 + + + SAI3LPEN + SAI3 Peripheral Clocks Enable During + CSleep Mode + 24 + 1 + + + DFSDM1LPEN + DFSDM1 Peripheral Clocks Enable During + CSleep Mode + 28 + 1 + + + HRTIMLPEN + HRTIM peripheral clock enable during + CSleep mode + 29 + 1 + + + + + C1_APB4LPENR + C1_APB4LPENR + RCC APB4 Sleep Clock Register + 0x17C + 0x20 + read-write + 0x00000000 + + + SYSCFGLPEN + SYSCFG peripheral clock enable during + CSleep mode + 1 + 1 + + + LPUART1LPEN + LPUART1 Peripheral Clocks Enable During + CSleep Mode + 3 + 1 + + + SPI6LPEN + SPI6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + I2C4LPEN + I2C4 Peripheral Clocks Enable During + CSleep Mode + 7 + 1 + + + LPTIM2LPEN + LPTIM2 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + LPTIM3LPEN + LPTIM3 Peripheral Clocks Enable During + CSleep Mode + 10 + 1 + + + LPTIM4LPEN + LPTIM4 Peripheral Clocks Enable During + CSleep Mode + 11 + 1 + + + LPTIM5LPEN + LPTIM5 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + COMP12LPEN + COMP1/2 peripheral clock enable during + CSleep mode + 14 + 1 + + + VREFLPEN + VREF peripheral clock enable during + CSleep mode + 15 + 1 + + + RTCAPBLPEN + RTC APB Clock Enable During CSleep + Mode + 16 + 1 + + + SAI4LPEN + SAI4 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + + + APB4LPENR + APB4LPENR + RCC APB4 Sleep Clock Register + 0x11C + 0x20 + read-write + 0x00000000 + + + SYSCFGLPEN + SYSCFG peripheral clock enable during + CSleep mode + 1 + 1 + + + LPUART1LPEN + LPUART1 Peripheral Clocks Enable During + CSleep Mode + 3 + 1 + + + SPI6LPEN + SPI6 Peripheral Clocks Enable During + CSleep Mode + 5 + 1 + + + I2C4LPEN + I2C4 Peripheral Clocks Enable During + CSleep Mode + 7 + 1 + + + LPTIM2LPEN + LPTIM2 Peripheral Clocks Enable During + CSleep Mode + 9 + 1 + + + LPTIM3LPEN + LPTIM3 Peripheral Clocks Enable During + CSleep Mode + 10 + 1 + + + LPTIM4LPEN + LPTIM4 Peripheral Clocks Enable During + CSleep Mode + 11 + 1 + + + LPTIM5LPEN + LPTIM5 Peripheral Clocks Enable During + CSleep Mode + 12 + 1 + + + COMP12LPEN + COMP1/2 peripheral clock enable during + CSleep mode + 14 + 1 + + + VREFLPEN + VREF peripheral clock enable during + CSleep mode + 15 + 1 + + + RTCAPBLPEN + RTC APB Clock Enable During CSleep + Mode + 16 + 1 + + + SAI4LPEN + SAI4 Peripheral Clocks Enable During + CSleep Mode + 21 + 1 + + + + + + + LPTIM1 + Low power timer + LPTIM + 0x40002400 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIM1 global interrupt + 93 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + LPTIM Enable + 0 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + COUNTRST + Counter reset + 3 + 1 + + + RSTARE + Reset after read enable + 4 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + CFGR2 + CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + LPTIM Input 1 selection + 0 + 2 + + + IN2SEL + LPTIM Input 2 selection + 4 + 2 + + + + + + + LPTIM2 + 0x58002400 + + LPTIM2 + LPTIM2 timer interrupt + 138 + + + + LPTIM3 + Low power timer + LPTIM + 0x58002800 + + 0x0 + 0x400 + registers + + + LPTIM3 + LPTIM2 timer interrupt + 139 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + LPTIM Enable + 0 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + COUNTRST + Counter reset + 3 + 1 + + + RSTARE + Reset after read enable + 4 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + CFGR2 + CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + LPTIM Input 1 selection + 0 + 2 + + + + + + + LPTIM4 + 0x58002C00 + + LPTIM4 + LPTIM2 timer interrupt + 140 + + + + LPTIM5 + 0x58003000 + + LPTIM5 + LPTIM2 timer interrupt + 141 + + + + LPUART1 + LPUART1 + LPUART + 0x58000C00 + + 0x0 + 0x400 + registers + + + LPUART + LPUART global interrupt + 142 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFIFO Full interrupt + enable + 31 + 1 + + + TXFEIE + TXFIFO empty interrupt + enable + 30 + 1 + + + FIFOEN + FIFO mode enable + 29 + 1 + + + M1 + Word length + 28 + 1 + + + DEAT + Driver Enable assertion + time + 21 + 5 + + + DEDT + Driver Enable deassertion + time + 16 + 5 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD + Address of the USART node + 24 + 8 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + DATAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFIFO threshold + configuration + 29 + 3 + + + RXFTIE + RXFIFO threshold interrupt + enable + 28 + 1 + + + RXFTCFG + Receive FIFO threshold + configuration + 25 + 3 + + + TXFTIE + TXFIFO threshold interrupt + enable + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR + 0 + 20 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFIFO threshold flag + 27 + 1 + + + RXFT + RXFIFO threshold flag + 26 + 1 + + + RXFF + RXFIFO Full + 24 + 1 + + + TXFE + TXFIFO Empty + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NE + NE + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + Prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + Clock prescaler + 0 + 4 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x58000400 + + 0x0 + 0x400 + registers + + + + PMCR + PMCR + peripheral mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + I2C1FMP + I2C1 Fm+ + 0 + 1 + + + I2C2FMP + I2C2 Fm+ + 1 + 1 + + + I2C3FMP + I2C3 Fm+ + 2 + 1 + + + I2C4FMP + I2C4 Fm+ + 3 + 1 + + + PB6FMP + PB(6) Fm+ + 4 + 1 + + + PB7FMP + PB(7) Fast Mode Plus + 5 + 1 + + + PB8FMP + PB(8) Fast Mode Plus + 6 + 1 + + + PB9FMP + PB(9) Fm+ + 7 + 1 + + + BOOSTE + Booster Enable + 8 + 1 + + + EPIS + Ethernet PHY Interface + Selection + 21 + 3 + + + PA0SO + PA0 Switch Open + 24 + 1 + + + PA1SO + PA1 Switch Open + 25 + 1 + + + PC2SO + PC2 Switch Open + 26 + 1 + + + PC3SO + PC3 Switch Open + 27 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to + 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to + 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to + 15) + 0 + 4 + + + + + CCCSR + CCCSR + compensation cell control/status + register + 0x20 + 0x20 + read-write + 0x00000000 + + + EN + enable + 0 + 1 + + + CS + Code selection + 1 + 1 + + + READY + Compensation cell ready + flag + 8 + 1 + + + HSLV + High-speed at low-voltage + 16 + 1 + + + + + CCVR + CCVR + SYSCFG compensation cell value + register + 0x24 + 0x20 + read-only + 0x00000000 + + + NCV + NMOS compensation value + 0 + 4 + + + PCV + PMOS compensation value + 4 + 4 + + + + + CCCR + CCCR + SYSCFG compensation cell code + register + 0x28 + 0x20 + read-write + 0x00000000 + + + NCC + NMOS compensation code + 0 + 4 + + + PCC + PMOS compensation code + 4 + 4 + + + + + PKGR + PKGR + SYSCFG package register + 0x124 + 0x20 + read-only + 0x00000000 + + + PKG + Package + 0 + 4 + + + + + UR0 + UR0 + SYSCFG user register 0 + 0x300 + 0x20 + read-only + 0x00000000 + + + BKS + Bank Swap + 0 + 1 + + + RDP + Readout protection + 16 + 8 + + + + + UR2 + UR2 + SYSCFG user register 2 + 0x308 + 0x20 + read-write + 0x00000000 + + + BORH + BOR_LVL Brownout Reset Threshold + Level + 0 + 2 + + + BOOT_ADD0 + Boot Address 0 + 16 + 16 + + + + + UR3 + UR3 + SYSCFG user register 3 + 0x30C + 0x20 + read-write + 0x00000000 + + + BOOT_ADD1 + Boot Address 1 + 16 + 16 + + + + + UR4 + UR4 + SYSCFG user register 4 + 0x310 + 0x20 + read-only + 0x00000000 + + + MEPAD_1 + Mass Erase Protected Area Disabled for + bank 1 + 16 + 1 + + + + + UR5 + UR5 + SYSCFG user register 5 + 0x314 + 0x20 + read-only + 0x00000000 + + + MESAD_1 + Mass erase secured area disabled for + bank 1 + 0 + 1 + + + WRPN_1 + Write protection for flash bank + 1 + 16 + 8 + + + + + UR6 + UR6 + SYSCFG user register 6 + 0x318 + 0x20 + read-only + 0x00000000 + + + PA_BEG_1 + Protected area start address for bank + 1 + 0 + 12 + + + PA_END_1 + Protected area end address for bank + 1 + 16 + 12 + + + + + UR7 + UR7 + SYSCFG user register 7 + 0x31C + 0x20 + read-only + 0x00000000 + + + SA_BEG_1 + Secured area start address for bank + 1 + 0 + 12 + + + SA_END_1 + Secured area end address for bank + 1 + 16 + 12 + + + + + UR8 + UR8 + SYSCFG user register 8 + 0x320 + 0x20 + read-only + 0x00000000 + + + MEPAD_2 + Mass erase protected area disabled for + bank 2 + 0 + 1 + + + MESAD_2 + Mass erase secured area disabled for + bank 2 + 16 + 1 + + + + + UR9 + UR9 + SYSCFG user register 9 + 0x324 + 0x20 + read-only + 0x00000000 + + + WRPN_2 + Write protection for flash bank + 2 + 0 + 8 + + + PA_BEG_2 + Protected area start address for bank + 2 + 16 + 12 + + + + + UR10 + UR10 + SYSCFG user register 10 + 0x328 + 0x20 + read-only + 0x00000000 + + + PA_END_2 + Protected area end address for bank + 2 + 0 + 12 + + + SA_BEG_2 + Secured area start address for bank + 2 + 16 + 12 + + + + + UR11 + UR11 + SYSCFG user register 11 + 0x32C + 0x20 + read-only + 0x00000000 + + + SA_END_2 + Secured area end address for bank + 2 + 0 + 12 + + + IWDG1M + Independent Watchdog 1 + mode + 16 + 1 + + + + + UR12 + UR12 + SYSCFG user register 12 + 0x330 + 0x20 + read-only + 0x00000000 + + + SECURE + Secure mode + 16 + 1 + + + + + UR13 + UR13 + SYSCFG user register 13 + 0x334 + 0x20 + read-only + 0x00000000 + + + SDRS + Secured DTCM RAM Size + 0 + 2 + + + D1SBRST + D1 Standby reset + 16 + 1 + + + + + UR14 + UR14 + SYSCFG user register 14 + 0x338 + 0x20 + read-write + 0x00000000 + + + D1STPRST + D1 Stop Reset + 0 + 1 + + + + + UR15 + UR15 + SYSCFG user register 15 + 0x33C + 0x20 + read-only + 0x00000000 + + + FZIWDGSTB + Freeze independent watchdog in Standby + mode + 16 + 1 + + + + + UR16 + UR16 + SYSCFG user register 16 + 0x340 + 0x20 + read-only + 0x00000000 + + + FZIWDGSTP + Freeze independent watchdog in Stop + mode + 0 + 1 + + + PKP + Private key programmed + 16 + 1 + + + + + UR17 + UR17 + SYSCFG user register 17 + 0x344 + 0x20 + read-only + 0x00000000 + + + IO_HSLV + I/O high speed / low + voltage + 0 + 1 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x58000000 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD through EXTI line + 1 + + + EXTI0 + EXTI Line 0 interrupt + 6 + + + EXTI1 + EXTI Line 1 interrupt + 7 + + + EXTI2 + EXTI Line 2 interrupt + 8 + + + EXTI3 + EXTI Line 3interrupt + 9 + + + EXTI4 + EXTI Line 4interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + cm4_sev_it + Arm Cortex-M4 Send even + interrupt + 65 + + + WKUP + WKUP1 to WKUP6 pins + 149 + + + HOLD_CORE + CPU1 hold + 148 + + + + RTSR1 + RTSR1 + EXTI rising trigger selection + register + 0x0 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + TR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + TR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + TR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + TR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + TR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + TR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + TR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + TR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + TR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + TR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + TR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + TR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + TR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + TR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + TR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + TR16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + TR17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + TR18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + TR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + TR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + TR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + + + FTSR1 + FTSR1 + EXTI falling trigger selection + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + TR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + TR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + TR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + TR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + TR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + TR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + TR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + TR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + TR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + TR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + TR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + TR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + TR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + TR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + TR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + TR16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + TR17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + TR18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + TR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + TR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + TR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + + + SWIER1 + SWIER1 + EXTI software interrupt event + register + 0x8 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + SWIER1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + SWIER2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + SWIER3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + SWIER4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + SWIER5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + SWIER6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + SWIER7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + SWIER8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + SWIER9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + SWIER10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + SWIER11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + SWIER12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + SWIER13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + SWIER14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + SWIER15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + SWIER16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + SWIER17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + SWIER18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + SWIER19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + SWIER20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + SWIER21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + + + D3PMR1 + D3PMR1 + EXTI D3 pending mask register + 0xC + 0x20 + read-write + 0x00000000 + + + MR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + MR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + MR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + MR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + MR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + MR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + MR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + MR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + MR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + MR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + MR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + MR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + MR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + MR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + MR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + MR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + MR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + MR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + MR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + MR25 + Rising trigger event configuration bit + of Configurable Event input + 25 + 1 + + + + + D3PCR1L + D3PCR1L + EXTI D3 pending clear selection register + low + 0x10 + 0x20 + read-write + 0x00000000 + + + PCS0 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 0 + 2 + + + PCS1 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 2 + 2 + + + PCS2 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 4 + 2 + + + PCS3 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 6 + 2 + + + PCS4 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 8 + 2 + + + PCS5 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 10 + 2 + + + PCS6 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 12 + 2 + + + PCS7 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 14 + 2 + + + PCS8 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 16 + 2 + + + PCS9 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 18 + 2 + + + PCS10 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 20 + 2 + + + PCS11 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 22 + 2 + + + PCS12 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 24 + 2 + + + PCS13 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 26 + 2 + + + PCS14 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 28 + 2 + + + PCS15 + D3 Pending request clear input signal + selection on Event input x = truncate + (n/2) + 30 + 2 + + + + + D3PCR1H + D3PCR1H + EXTI D3 pending clear selection register + high + 0x14 + 0x20 + read-write + 0x00000000 + + + PCS19 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 6 + 2 + + + PCS20 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 8 + 2 + + + PCS21 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 10 + 2 + + + PCS25 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+32)/2) + 18 + 2 + + + + + RTSR2 + RTSR2 + EXTI rising trigger selection + register + 0x20 + 0x20 + read-write + 0x00000000 + + + TR49 + Rising trigger event configuration bit + of Configurable Event input x+32 + 17 + 1 + + + TR51 + Rising trigger event configuration bit + of Configurable Event input x+32 + 19 + 1 + + + + + FTSR2 + FTSR2 + EXTI falling trigger selection + register + 0x24 + 0x20 + read-write + 0x00000000 + + + TR49 + Falling trigger event configuration bit + of Configurable Event input x+32 + 17 + 1 + + + TR51 + Falling trigger event configuration bit + of Configurable Event input x+32 + 19 + 1 + + + + + SWIER2 + SWIER2 + EXTI software interrupt event + register + 0x28 + 0x20 + read-write + 0x00000000 + + + SWIER49 + Software interrupt on line + x+32 + 17 + 1 + + + SWIER51 + Software interrupt on line + x+32 + 19 + 1 + + + + + D3PMR2 + D3PMR2 + EXTI D3 pending mask register + 0x2C + 0x20 + read-write + 0x00000000 + + + MR34 + D3 Pending Mask on Event input + x+32 + 2 + 1 + + + MR35 + D3 Pending Mask on Event input + x+32 + 3 + 1 + + + MR41 + D3 Pending Mask on Event input + x+32 + 9 + 1 + + + MR48 + D3 Pending Mask on Event input + x+32 + 16 + 1 + + + MR49 + D3 Pending Mask on Event input + x+32 + 17 + 1 + + + MR50 + D3 Pending Mask on Event input + x+32 + 18 + 1 + + + MR51 + D3 Pending Mask on Event input + x+32 + 19 + 1 + + + MR52 + D3 Pending Mask on Event input + x+32 + 20 + 1 + + + MR53 + D3 Pending Mask on Event input + x+32 + 21 + 1 + + + + + D3PCR2L + D3PCR2L + EXTI D3 pending clear selection register + low + 0x30 + 0x20 + read-write + 0x00000000 + + + PCS35 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+64)/2) + 6 + 2 + + + PCS34 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+64)/2) + 4 + 2 + + + PCS41 + D3 Pending request clear input signal + selection on Event input x = truncate + ((n+64)/2) + 18 + 2 + + + + + D3PCR2H + D3PCR2H + EXTI D3 pending clear selection register + high + 0x34 + 0x20 + read-write + 0x00000000 + + + PCS48 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 0 + 2 + + + PCS49 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 2 + 2 + + + PCS50 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 4 + 2 + + + PCS51 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 6 + 2 + + + PCS52 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 8 + 2 + + + PCS53 + Pending request clear input signal + selection on Event input x= truncate + ((n+96)/2) + 10 + 2 + + + + + RTSR3 + RTSR3 + EXTI rising trigger selection + register + 0x40 + 0x20 + read-write + 0x00000000 + + + TR82 + Rising trigger event configuration bit + of Configurable Event input x+64 + 18 + 1 + + + TR84 + Rising trigger event configuration bit + of Configurable Event input x+64 + 20 + 1 + + + TR85 + Rising trigger event configuration bit + of Configurable Event input x+64 + 21 + 1 + + + TR86 + Rising trigger event configuration bit + of Configurable Event input x+64 + 22 + 1 + + + + + FTSR3 + FTSR3 + EXTI falling trigger selection + register + 0x44 + 0x20 + read-write + 0x00000000 + + + TR82 + Falling trigger event configuration bit + of Configurable Event input x+64 + 18 + 1 + + + TR84 + Falling trigger event configuration bit + of Configurable Event input x+64 + 20 + 1 + + + TR85 + Falling trigger event configuration bit + of Configurable Event input x+64 + 21 + 1 + + + TR86 + Falling trigger event configuration bit + of Configurable Event input x+64 + 22 + 1 + + + + + SWIER3 + SWIER3 + EXTI software interrupt event + register + 0x48 + 0x20 + read-write + 0x00000000 + + + SWIER82 + Software interrupt on line + x+64 + 18 + 1 + + + SWIER84 + Software interrupt on line + x+64 + 20 + 1 + + + SWIER85 + Software interrupt on line + x+64 + 21 + 1 + + + SWIER86 + Software interrupt on line + x+64 + 22 + 1 + + + + + D3PMR3 + D3PMR3 + EXTI D3 pending mask register + 0x4C + 0x20 + read-write + 0x00000000 + + + MR88 + D3 Pending Mask on Event input + x+64 + 24 + 1 + + + + + D3PCR3H + D3PCR3H + EXTI D3 pending clear selection register + high + 0x54 + 0x20 + read-write + 0x00000000 + + + PCS88 + D3 Pending request clear input signal + selection on Event input x= truncate + N+160/2 + 18 + 2 + + + + + CPUIMR1 + CPUIMR1 + EXTI interrupt mask register + 0x80 + 0x20 + read-write + 0xFFC00000 + + + MR0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + MR1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + MR2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + MR3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + MR4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + MR5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + MR6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + MR7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + MR8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + MR9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + MR10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + MR11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + MR12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + MR13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + MR14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + MR15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + MR16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + MR17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + MR18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + MR19 + Rising trigger event configuration bit + of Configurable Event input + 19 + 1 + + + MR20 + Rising trigger event configuration bit + of Configurable Event input + 20 + 1 + + + MR21 + Rising trigger event configuration bit + of Configurable Event input + 21 + 1 + + + MR22 + Rising trigger event configuration bit + of Configurable Event input + 22 + 1 + + + MR23 + Rising trigger event configuration bit + of Configurable Event input + 23 + 1 + + + MR24 + Rising trigger event configuration bit + of Configurable Event input + 24 + 1 + + + MR25 + Rising trigger event configuration bit + of Configurable Event input + 25 + 1 + + + MR26 + Rising trigger event configuration bit + of Configurable Event input + 26 + 1 + + + MR27 + Rising trigger event configuration bit + of Configurable Event input + 27 + 1 + + + MR28 + Rising trigger event configuration bit + of Configurable Event input + 28 + 1 + + + MR29 + Rising trigger event configuration bit + of Configurable Event input + 29 + 1 + + + MR30 + Rising trigger event configuration bit + of Configurable Event input + 30 + 1 + + + MR31 + Rising trigger event configuration bit + of Configurable Event input + 31 + 1 + + + + + CPUEMR1 + CPUEMR1 + EXTI event mask register + 0x84 + 0x20 + read-write + 0x00000000 + + + MR0 + CPU Event mask on Event input + x + 0 + 1 + + + MR1 + CPU Event mask on Event input + x + 1 + 1 + + + MR2 + CPU Event mask on Event input + x + 2 + 1 + + + MR3 + CPU Event mask on Event input + x + 3 + 1 + + + MR4 + CPU Event mask on Event input + x + 4 + 1 + + + MR5 + CPU Event mask on Event input + x + 5 + 1 + + + MR6 + CPU Event mask on Event input + x + 6 + 1 + + + MR7 + CPU Event mask on Event input + x + 7 + 1 + + + MR8 + CPU Event mask on Event input + x + 8 + 1 + + + MR9 + CPU Event mask on Event input + x + 9 + 1 + + + MR10 + CPU Event mask on Event input + x + 10 + 1 + + + MR11 + CPU Event mask on Event input + x + 11 + 1 + + + MR12 + CPU Event mask on Event input + x + 12 + 1 + + + MR13 + CPU Event mask on Event input + x + 13 + 1 + + + MR14 + CPU Event mask on Event input + x + 14 + 1 + + + MR15 + CPU Event mask on Event input + x + 15 + 1 + + + MR16 + CPU Event mask on Event input + x + 16 + 1 + + + MR17 + CPU Event mask on Event input + x + 17 + 1 + + + MR18 + CPU Event mask on Event input + x + 18 + 1 + + + MR19 + CPU Event mask on Event input + x + 19 + 1 + + + MR20 + CPU Event mask on Event input + x + 20 + 1 + + + MR21 + CPU Event mask on Event input + x + 21 + 1 + + + MR22 + CPU Event mask on Event input + x + 22 + 1 + + + MR23 + CPU Event mask on Event input + x + 23 + 1 + + + MR24 + CPU Event mask on Event input + x + 24 + 1 + + + MR25 + CPU Event mask on Event input + x + 25 + 1 + + + MR26 + CPU Event mask on Event input + x + 26 + 1 + + + MR27 + CPU Event mask on Event input + x + 27 + 1 + + + MR28 + CPU Event mask on Event input + x + 28 + 1 + + + MR29 + CPU Event mask on Event input + x + 29 + 1 + + + MR30 + CPU Event mask on Event input + x + 30 + 1 + + + MR31 + CPU Event mask on Event input + x + 31 + 1 + + + + + CPUPR1 + CPUPR1 + EXTI pending register + 0x88 + 0x20 + read-write + 0x00000000 + + + PR0 + CPU Event mask on Event input + x + 0 + 1 + + + PR1 + CPU Event mask on Event input + x + 1 + 1 + + + PR2 + CPU Event mask on Event input + x + 2 + 1 + + + PR3 + CPU Event mask on Event input + x + 3 + 1 + + + PR4 + CPU Event mask on Event input + x + 4 + 1 + + + PR5 + CPU Event mask on Event input + x + 5 + 1 + + + PR6 + CPU Event mask on Event input + x + 6 + 1 + + + PR7 + CPU Event mask on Event input + x + 7 + 1 + + + PR8 + CPU Event mask on Event input + x + 8 + 1 + + + PR9 + CPU Event mask on Event input + x + 9 + 1 + + + PR10 + CPU Event mask on Event input + x + 10 + 1 + + + PR11 + CPU Event mask on Event input + x + 11 + 1 + + + PR12 + CPU Event mask on Event input + x + 12 + 1 + + + PR13 + CPU Event mask on Event input + x + 13 + 1 + + + PR14 + CPU Event mask on Event input + x + 14 + 1 + + + PR15 + CPU Event mask on Event input + x + 15 + 1 + + + PR16 + CPU Event mask on Event input + x + 16 + 1 + + + PR17 + CPU Event mask on Event input + x + 17 + 1 + + + PR18 + CPU Event mask on Event input + x + 18 + 1 + + + PR19 + CPU Event mask on Event input + x + 19 + 1 + + + PR20 + CPU Event mask on Event input + x + 20 + 1 + + + PR21 + CPU Event mask on Event input + x + 21 + 1 + + + + + CPUIMR2 + CPUIMR2 + EXTI interrupt mask register + 0x90 + 0x20 + read-write + 0x00000000 + + + MR0 + CPU Interrupt Mask on Direct Event input + x+32 + 0 + 1 + + + MR1 + CPU Interrupt Mask on Direct Event input + x+32 + 1 + 1 + + + MR2 + CPU Interrupt Mask on Direct Event input + x+32 + 2 + 1 + + + MR3 + CPU Interrupt Mask on Direct Event input + x+32 + 3 + 1 + + + MR4 + CPU Interrupt Mask on Direct Event input + x+32 + 4 + 1 + + + MR5 + CPU Interrupt Mask on Direct Event input + x+32 + 5 + 1 + + + MR6 + CPU Interrupt Mask on Direct Event input + x+32 + 6 + 1 + + + MR7 + CPU Interrupt Mask on Direct Event input + x+32 + 7 + 1 + + + MR8 + CPU Interrupt Mask on Direct Event input + x+32 + 8 + 1 + + + MR9 + CPU Interrupt Mask on Direct Event input + x+32 + 9 + 1 + + + MR10 + CPU Interrupt Mask on Direct Event input + x+32 + 10 + 1 + + + MR11 + CPU Interrupt Mask on Direct Event input + x+32 + 11 + 1 + + + MR12 + CPU Interrupt Mask on Direct Event input + x+32 + 12 + 1 + + + MR14 + CPU Interrupt Mask on Direct Event input + x+32 + 14 + 1 + + + MR15 + CPU Interrupt Mask on Direct Event input + x+32 + 15 + 1 + + + MR16 + CPU Interrupt Mask on Direct Event input + x+32 + 16 + 1 + + + MR17 + CPU Interrupt Mask on Direct Event input + x+32 + 17 + 1 + + + MR18 + CPU Interrupt Mask on Direct Event input + x+32 + 18 + 1 + + + MR19 + CPU Interrupt Mask on Direct Event input + x+32 + 19 + 1 + + + MR20 + CPU Interrupt Mask on Direct Event input + x+32 + 20 + 1 + + + MR21 + CPU Interrupt Mask on Direct Event input + x+32 + 21 + 1 + + + MR22 + CPU Interrupt Mask on Direct Event input + x+32 + 22 + 1 + + + MR23 + CPU Interrupt Mask on Direct Event input + x+32 + 23 + 1 + + + MR24 + CPU Interrupt Mask on Direct Event input + x+32 + 24 + 1 + + + MR25 + CPU Interrupt Mask on Direct Event input + x+32 + 25 + 1 + + + MR26 + CPU Interrupt Mask on Direct Event input + x+32 + 26 + 1 + + + MR27 + CPU Interrupt Mask on Direct Event input + x+32 + 27 + 1 + + + MR28 + CPU Interrupt Mask on Direct Event input + x+32 + 28 + 1 + + + MR29 + CPU Interrupt Mask on Direct Event input + x+32 + 29 + 1 + + + MR30 + CPU Interrupt Mask on Direct Event input + x+32 + 30 + 1 + + + MR31 + CPU Interrupt Mask on Direct Event input + x+32 + 31 + 1 + + + + + CPUEMR2 + CPUEMR2 + EXTI event mask register + 0x94 + 0x20 + read-write + 0x00000000 + + + MR32 + CPU Interrupt Mask on Direct Event input + x+32 + 0 + 1 + + + MR33 + CPU Interrupt Mask on Direct Event input + x+32 + 1 + 1 + + + MR34 + CPU Interrupt Mask on Direct Event input + x+32 + 2 + 1 + + + MR35 + CPU Interrupt Mask on Direct Event input + x+32 + 3 + 1 + + + MR36 + CPU Interrupt Mask on Direct Event input + x+32 + 4 + 1 + + + MR37 + CPU Interrupt Mask on Direct Event input + x+32 + 5 + 1 + + + MR38 + CPU Interrupt Mask on Direct Event input + x+32 + 6 + 1 + + + MR39 + CPU Interrupt Mask on Direct Event input + x+32 + 7 + 1 + + + MR40 + CPU Interrupt Mask on Direct Event input + x+32 + 8 + 1 + + + MR41 + CPU Interrupt Mask on Direct Event input + x+32 + 9 + 1 + + + MR42 + CPU Interrupt Mask on Direct Event input + x+32 + 10 + 1 + + + MR43 + CPU Interrupt Mask on Direct Event input + x+32 + 11 + 1 + + + MR44 + CPU Interrupt Mask on Direct Event input + x+32 + 12 + 1 + + + MR46 + CPU Interrupt Mask on Direct Event input + x+32 + 14 + 1 + + + MR47 + CPU Interrupt Mask on Direct Event input + x+32 + 15 + 1 + + + MR48 + CPU Interrupt Mask on Direct Event input + x+32 + 16 + 1 + + + MR49 + CPU Interrupt Mask on Direct Event input + x+32 + 17 + 1 + + + MR50 + CPU Interrupt Mask on Direct Event input + x+32 + 18 + 1 + + + MR51 + CPU Interrupt Mask on Direct Event input + x+32 + 19 + 1 + + + MR52 + CPU Interrupt Mask on Direct Event input + x+32 + 20 + 1 + + + MR53 + CPU Interrupt Mask on Direct Event input + x+32 + 21 + 1 + + + MR54 + CPU Interrupt Mask on Direct Event input + x+32 + 22 + 1 + + + MR55 + CPU Interrupt Mask on Direct Event input + x+32 + 23 + 1 + + + MR56 + CPU Interrupt Mask on Direct Event input + x+32 + 24 + 1 + + + MR57 + CPU Interrupt Mask on Direct Event input + x+32 + 25 + 1 + + + MR58 + CPU Interrupt Mask on Direct Event input + x+32 + 26 + 1 + + + MR59 + CPU Interrupt Mask on Direct Event input + x+32 + 27 + 1 + + + MR60 + CPU Interrupt Mask on Direct Event input + x+32 + 28 + 1 + + + MR61 + CPU Interrupt Mask on Direct Event input + x+32 + 29 + 1 + + + MR62 + CPU Interrupt Mask on Direct Event input + x+32 + 30 + 1 + + + MR63 + CPU Interrupt Mask on Direct Event input + x+32 + 31 + 1 + + + + + CPUPR2 + CPUPR2 + EXTI pending register + 0x98 + 0x20 + read-only + 0x00000000 + + + PR49 + Configurable event inputs x+32 Pending + bit + 17 + 1 + + + PR51 + Configurable event inputs x+32 Pending + bit + 19 + 1 + + + + + CPUIMR3 + CPUIMR3 + EXTI interrupt mask register + 0xA0 + 0x20 + read-only + 0x00000000 + + + MR64 + CPU Interrupt Mask on Direct Event input + x+64 + 0 + 1 + + + MR65 + CPU Interrupt Mask on Direct Event input + x+64 + 1 + 1 + + + MR66 + CPU Interrupt Mask on Direct Event input + x+64 + 2 + 1 + + + MR67 + CPU Interrupt Mask on Direct Event input + x+64 + 3 + 1 + + + MR68 + CPU Interrupt Mask on Direct Event input + x+64 + 4 + 1 + + + MR69 + CPU Interrupt Mask on Direct Event input + x+64 + 5 + 1 + + + MR70 + CPU Interrupt Mask on Direct Event input + x+64 + 6 + 1 + + + MR71 + CPU Interrupt Mask on Direct Event input + x+64 + 7 + 1 + + + MR72 + CPU Interrupt Mask on Direct Event input + x+64 + 8 + 1 + + + MR73 + CPU Interrupt Mask on Direct Event input + x+64 + 9 + 1 + + + MR74 + CPU Interrupt Mask on Direct Event input + x+64 + 10 + 1 + + + MR75 + CPU Interrupt Mask on Direct Event input + x+64 + 11 + 1 + + + MR76 + CPU Interrupt Mask on Direct Event input + x+64 + 12 + 1 + + + MR77 + CPU Interrupt Mask on Direct Event input + x+64 + 13 + 1 + + + MR78 + CPU Interrupt Mask on Direct Event input + x+64 + 14 + 1 + + + MR79 + CPU Interrupt Mask on Direct Event input + x+64 + 15 + 1 + + + MR80 + CPU Interrupt Mask on Direct Event input + x+64 + 16 + 1 + + + MR82 + CPU Interrupt Mask on Direct Event input + x+64 + 18 + 1 + + + MR84 + CPU Interrupt Mask on Direct Event input + x+64 + 20 + 1 + + + MR85 + CPU Interrupt Mask on Direct Event input + x+64 + 21 + 1 + + + MR86 + CPU Interrupt Mask on Direct Event input + x+64 + 22 + 1 + + + MR87 + CPU Interrupt Mask on Direct Event input + x+64 + 23 + 1 + + + MR88 + CPU Interrupt Mask on Direct Event input + x+64 + 24 + 1 + + + + + CPUEMR3 + CPUEMR3 + EXTI event mask register + 0xA4 + 0x20 + read-only + 0x00000000 + + + MR64 + CPU Event mask on Event input + x+64 + 0 + 1 + + + MR65 + CPU Event mask on Event input + x+64 + 1 + 1 + + + MR66 + CPU Event mask on Event input + x+64 + 2 + 1 + + + MR67 + CPU Event mask on Event input + x+64 + 3 + 1 + + + MR68 + CPU Event mask on Event input + x+64 + 4 + 1 + + + MR69 + CPU Event mask on Event input + x+64 + 5 + 1 + + + MR70 + CPU Event mask on Event input + x+64 + 6 + 1 + + + MR71 + CPU Event mask on Event input + x+64 + 7 + 1 + + + MR72 + CPU Event mask on Event input + x+64 + 8 + 1 + + + MR73 + CPU Event mask on Event input + x+64 + 9 + 1 + + + MR74 + CPU Event mask on Event input + x+64 + 10 + 1 + + + MR75 + CPU Event mask on Event input + x+64 + 11 + 1 + + + MR76 + CPU Event mask on Event input + x+64 + 12 + 1 + + + MR77 + CPU Event mask on Event input + x+64 + 13 + 1 + + + MR78 + CPU Event mask on Event input + x+64 + 14 + 1 + + + MR79 + CPU Event mask on Event input + x+64 + 15 + 1 + + + MR80 + CPU Event mask on Event input + x+64 + 16 + 1 + + + MR82 + CPU Event mask on Event input + x+64 + 18 + 1 + + + MR84 + CPU Event mask on Event input + x+64 + 20 + 1 + + + MR85 + CPU Event mask on Event input + x+64 + 21 + 1 + + + MR86 + CPU Event mask on Event input + x+64 + 22 + 1 + + + MR87 + CPU Event mask on Event input + x+64 + 23 + 1 + + + MR88 + CPU Event mask on Event input + x+64 + 24 + 1 + + + + + CPUPR3 + CPUPR3 + EXTI pending register + 0xA8 + 0x20 + read-only + 0x00000000 + + + PR82 + Configurable event inputs x+64 Pending + bit + 18 + 1 + + + PR84 + Configurable event inputs x+64 Pending + bit + 20 + 1 + + + PR85 + Configurable event inputs x+64 Pending + bit + 21 + 1 + + + PR86 + Configurable event inputs x+64 Pending + bit + 22 + 1 + + + + + + + DELAY_Block_SDMMC1 + DELAY_Block_SDMMC1 + DLYB + 0x52008000 + + 0x0 + 0x100 + registers + + + + CR + CR + DLYB control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DEN + Delay block enable bit + 0 + 1 + + + SEN + Sampler length enable bit + 1 + 1 + + + + + CFGR + CFGR + DLYB configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + SEL + Select the phase for the Output + clock + 0 + 4 + + + UNIT + Delay Defines the delay of a Unit delay + cell + 8 + 7 + + + LNG + Delay line length value + 16 + 12 + + + LNGF + Length valid flag + 31 + 1 + + + + + + + DELAY_Block_QUADSPI + 0x52006000 + + + DELAY_Block_SDMMC2 + 0x48022800 + + + Flash + Flash + Flash + 0x52002000 + + 0x0 + 0x1000 + registers + + + FLASH + Flash memory + 4 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Read latency + 0 + 3 + + + WRHIGHFREQ + Flash signal delay + 4 + 2 + + + + + ACR_ + ACR_ + Access control register + 0x100 + 0x20 + read-write + 0x00000000 + + + LATENCY + Read latency + 0 + 3 + + + WRHIGHFREQ + Flash signal delay + 4 + 2 + + + + + KEYR1 + KEYR1 + FLASH key register for bank 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + KEYR1 + Bank 1 access configuration unlock + key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + FLASH option key register + 0x8 + 0x20 + read-write + 0x00000000 + + + OPTKEYR + Unlock key option bytes + 0 + 32 + + + + + OPTKEYR_ + OPTKEYR_ + FLASH option key register + 0x108 + 0x20 + read-write + 0x00000000 + + + OPTKEYR + Unlock key option bytes + 0 + 32 + + + + + CR1 + CR1 + FLASH control register for bank + 1 + 0xC + 0x20 + read-write + 0x00000000 + + + LOCK1 + Bank 1 configuration lock + bit + 0 + 1 + + + PG1 + Bank 1 program enable bit + 1 + 1 + + + SER1 + Bank 1 sector erase + request + 2 + 1 + + + BER1 + Bank 1 erase request + 3 + 1 + + + PSIZE1 + Bank 1 program size + 4 + 2 + + + FW1 + Bank 1 write forcing control + bit + 6 + 1 + + + START1 + Bank 1 bank or sector erase start + control bit + 7 + 1 + + + SNB1 + Bank 1 sector erase selection + number + 8 + 3 + + + CRC_EN + Bank 1 CRC control bit + 15 + 1 + + + EOPIE1 + Bank 1 end-of-program interrupt control + bit + 16 + 1 + + + WRPERRIE1 + Bank 1 write protection error interrupt + enable bit + 17 + 1 + + + PGSERRIE1 + Bank 1 programming sequence error + interrupt enable bit + 18 + 1 + + + STRBERRIE1 + Bank 1 strobe error interrupt enable + bit + 19 + 1 + + + INCERRIE1 + Bank 1 inconsistency error interrupt + enable bit + 21 + 1 + + + OPERRIE1 + Bank 1 write/erase error interrupt + enable bit + 22 + 1 + + + RDPERRIE1 + Bank 1 read protection error interrupt + enable bit + 23 + 1 + + + RDSERRIE1 + Bank 1 secure error interrupt enable + bit + 24 + 1 + + + SNECCERRIE1 + Bank 1 ECC single correction error + interrupt enable bit + 25 + 1 + + + DBECCERRIE1 + Bank 1 ECC double detection error + interrupt enable bit + 26 + 1 + + + CRCENDIE1 + Bank 1 end of CRC calculation interrupt + enable bit + 27 + 1 + + + + + SR1 + SR1 + FLASH status register for bank + 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + BSY1 + Bank 1 ongoing program + flag + 0 + 1 + + + WBNE1 + Bank 1 write buffer not empty + flag + 1 + 1 + + + QW1 + Bank 1 wait queue flag + 2 + 1 + + + CRC_BUSY1 + Bank 1 CRC busy flag + 3 + 1 + + + EOP1 + Bank 1 end-of-program flag + 16 + 1 + + + WRPERR1 + Bank 1 write protection error + flag + 17 + 1 + + + PGSERR1 + Bank 1 programming sequence error + flag + 18 + 1 + + + STRBERR1 + Bank 1 strobe error flag + 19 + 1 + + + INCERR1 + Bank 1 inconsistency error + flag + 21 + 1 + + + OPERR1 + Bank 1 write/erase error + flag + 22 + 1 + + + RDPERR1 + Bank 1 read protection error + flag + 23 + 1 + + + RDSERR1 + Bank 1 secure error flag + 24 + 1 + + + SNECCERR11 + Bank 1 single correction error + flag + 25 + 1 + + + DBECCERR1 + Bank 1 ECC double detection error + flag + 26 + 1 + + + CRCEND1 + Bank 1 CRC-complete flag + 27 + 1 + + + + + CCR1 + CCR1 + FLASH clear control register for bank + 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + CLR_EOP1 + Bank 1 EOP1 flag clear bit + 16 + 1 + + + CLR_WRPERR1 + Bank 1 WRPERR1 flag clear + bit + 17 + 1 + + + CLR_PGSERR1 + Bank 1 PGSERR1 flag clear + bi + 18 + 1 + + + CLR_STRBERR1 + Bank 1 STRBERR1 flag clear + bit + 19 + 1 + + + CLR_INCERR1 + Bank 1 INCERR1 flag clear + bit + 21 + 1 + + + CLR_OPERR1 + Bank 1 OPERR1 flag clear + bit + 22 + 1 + + + CLR_RDPERR1 + Bank 1 RDPERR1 flag clear + bit + 23 + 1 + + + CLR_RDSERR1 + Bank 1 RDSERR1 flag clear + bit + 24 + 1 + + + CLR_SNECCERR1 + Bank 1 SNECCERR1 flag clear + bit + 25 + 1 + + + CLR_DBECCERR1 + Bank 1 DBECCERR1 flag clear + bit + 26 + 1 + + + CLR_CRCEND1 + Bank 1 CRCEND1 flag clear + bit + 27 + 1 + + + + + OPTCR + OPTCR + FLASH option control register + 0x18 + 0x20 + read-write + 0x00000000 + + + OPTLOCK + FLASH_OPTCR lock option configuration + bit + 0 + 1 + + + OPTSTART + Option byte start change option + configuration bit + 1 + 1 + + + MER + Flash mass erase enable + bit + 4 + 1 + + + OPTCHANGEERRIE + Option byte change error interrupt + enable bit + 30 + 1 + + + SWAP_BANK + Bank swapping configuration + bit + 31 + 1 + + + + + OPTCR_ + OPTCR_ + FLASH option control register + 0x118 + 0x20 + read-write + 0x00000000 + + + OPTLOCK + FLASH_OPTCR lock option configuration + bit + 0 + 1 + + + OPTSTART + Option byte start change option + configuration bit + 1 + 1 + + + MER + Flash mass erase enable + bit + 4 + 1 + + + OPTCHANGEERRIE + Option byte change error interrupt + enable bit + 30 + 1 + + + SWAP_BANK + Bank swapping configuration + bit + 31 + 1 + + + + + OPTSR_CUR_ + OPTSR_CUR_ + FLASH option status register + 0x11C + 0x20 + read-write + 0x00000000 + + + OPT_BUSY + Option byte change ongoing + flag + 0 + 1 + + + BOR_LEV + Brownout level option status + bit + 2 + 2 + + + IWDG1_HW + IWDG1 control option status + bit + 4 + 1 + + + nRST_STOP_D1 + D1 DStop entry reset option status + bit + 6 + 1 + + + nRST_STBY_D1 + D1 DStandby entry reset option status + bit + 7 + 1 + + + RDP + Readout protection level option status + byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option status + bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option status + bit + 18 + 1 + + + ST_RAM_SIZE + DTCM RAM size option + status + 19 + 2 + + + SECURITY + Security enable option status + bit + 21 + 1 + + + RSS1 + User option bit 1 + 26 + 1 + + + PERSO_OK + Device personalization status + bit + 28 + 1 + + + IO_HSLV + I/O high-speed at low-voltage status bit + (PRODUCT_BELOW_25V) + 29 + 1 + + + OPTCHANGEERR + Option byte change error + flag + 30 + 1 + + + SWAP_BANK_OPT + Bank swapping option status + bit + 31 + 1 + + + + + OPTSR_CUR + OPTSR_CUR + FLASH option status register + 0x1C + 0x20 + read-write + 0x00000000 + + + OPT_BUSY + Option byte change ongoing + flag + 0 + 1 + + + BOR_LEV + Brownout level option status + bit + 2 + 2 + + + IWDG1_HW + IWDG1 control option status + bit + 4 + 1 + + + nRST_STOP_D1 + D1 DStop entry reset option status + bit + 6 + 1 + + + nRST_STBY_D1 + D1 DStandby entry reset option status + bit + 7 + 1 + + + RDP + Readout protection level option status + byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option status + bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option status + bit + 18 + 1 + + + ST_RAM_SIZE + DTCM RAM size option + status + 19 + 2 + + + SECURITY + Security enable option status + bit + 21 + 1 + + + RSS1 + User option bit 1 + 26 + 1 + + + PERSO_OK + Device personalization status + bit + 28 + 1 + + + IO_HSLV + I/O high-speed at low-voltage status bit + (PRODUCT_BELOW_25V) + 29 + 1 + + + OPTCHANGEERR + Option byte change error + flag + 30 + 1 + + + SWAP_BANK_OPT + Bank swapping option status + bit + 31 + 1 + + + + + OPTSR_PRG + OPTSR_PRG + FLASH option status register + 0x20 + 0x20 + read-write + 0x00000000 + + + BOR_LEV + BOR reset level option configuration + bits + 2 + 2 + + + IWDG1_HW + IWDG1 option configuration + bit + 4 + 1 + + + nRST_STOP_D1 + Option byte erase after D1 DStop option + configuration bit + 6 + 1 + + + nRST_STBY_D1 + Option byte erase after D1 DStandby + option configuration bit + 7 + 1 + + + RDP + Readout protection level option + configuration byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option + configuration bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option + configuration bit + 18 + 1 + + + ST_RAM_SIZE + DTCM size select option configuration + bits + 19 + 2 + + + SECURITY + Security option configuration + bit + 21 + 1 + + + RSS1 + User option configuration bit + 1 + 26 + 1 + + + RSS2 + User option configuration bit + 2 + 27 + 1 + + + IO_HSLV + I/O high-speed at low-voltage + (PRODUCT_BELOW_25V) + 29 + 1 + + + SWAP_BANK_OPT + Bank swapping option configuration + bit + 31 + 1 + + + + + OPTSR_PRG_ + OPTSR_PRG_ + FLASH option status register + 0x120 + 0x20 + read-write + 0x00000000 + + + BOR_LEV + BOR reset level option configuration + bits + 2 + 2 + + + IWDG1_HW + IWDG1 option configuration + bit + 4 + 1 + + + nRST_STOP_D1 + Option byte erase after D1 DStop option + configuration bit + 6 + 1 + + + nRST_STBY_D1 + Option byte erase after D1 DStandby + option configuration bit + 7 + 1 + + + RDP + Readout protection level option + configuration byte + 8 + 8 + + + FZ_IWDG_STOP + IWDG Stop mode freeze option + configuration bit + 17 + 1 + + + FZ_IWDG_SDBY + IWDG Standby mode freeze option + configuration bit + 18 + 1 + + + ST_RAM_SIZE + DTCM size select option configuration + bits + 19 + 2 + + + SECURITY + Security option configuration + bit + 21 + 1 + + + RSS1 + User option configuration bit + 1 + 26 + 1 + + + RSS2 + User option configuration bit + 2 + 27 + 1 + + + IO_HSLV + I/O high-speed at low-voltage + (PRODUCT_BELOW_25V) + 29 + 1 + + + SWAP_BANK_OPT + Bank swapping option configuration + bit + 31 + 1 + + + + + OPTCCR_ + OPTCCR_ + FLASH option clear control + register + 0x124 + 0x20 + write-only + 0x00000000 + + + CLR_OPTCHANGEERR + OPTCHANGEERR reset bit + 30 + 1 + + + + + OPTCCR + OPTCCR + FLASH option clear control + register + 0x24 + 0x20 + write-only + 0x00000000 + + + CLR_OPTCHANGEERR + OPTCHANGEERR reset bit + 30 + 1 + + + + + PRAR_CUR1 + PRAR_CUR1 + FLASH protection address for bank + 1 + 0x28 + 0x20 + read-only + 0x00000000 + + + PROT_AREA_START1 + Bank 1 lowest PCROP protected + address + 0 + 12 + + + PROT_AREA_END1 + Bank 1 highest PCROP protected + address + 16 + 12 + + + DMEP1 + Bank 1 PCROP protected erase enable + option status bit + 31 + 1 + + + + + PRAR_PRG1 + PRAR_PRG1 + FLASH protection address for bank + 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + PROT_AREA_START1 + Bank 1 lowest PCROP protected address + configuration + 0 + 12 + + + PROT_AREA_END1 + Bank 1 highest PCROP protected address + configuration + 16 + 12 + + + DMEP1 + Bank 1 PCROP protected erase enable + option configuration bit + 31 + 1 + + + + + SCAR_CUR1 + SCAR_CUR1 + FLASH secure address for bank + 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START1 + Bank 1 lowest secure protected + address + 0 + 12 + + + SEC_AREA_END1 + Bank 1 highest secure protected + address + 16 + 12 + + + DMES1 + Bank 1 secure protected erase enable + option status bit + 31 + 1 + + + + + SCAR_PRG1 + SCAR_PRG1 + FLASH secure address for bank + 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START1 + Bank 1 lowest secure protected address + configuration + 0 + 12 + + + SEC_AREA_END1 + Bank 1 highest secure protected address + configuration + 16 + 12 + + + DMES1 + Bank 1 secure protected erase enable + option configuration bit + 31 + 1 + + + + + WPSN_CUR1R + WPSN_CUR1R + FLASH write sector protection for bank + 1 + 0x38 + 0x20 + read-only + 0x00000000 + + + WRPSn1 + Bank 1 sector write protection option + status byte + 0 + 8 + + + + + WPSN_PRG1R + WPSN_PRG1R + FLASH write sector protection for bank + 1 + 0x3C + 0x20 + read-write + 0x00000000 + + + WRPSn1 + Bank 1 sector write protection + configuration byte + 0 + 8 + + + + + BOOT_CURR + BOOT_CURR + FLASH register with boot + address + 0x40 + 0x20 + read-only + 0x00000000 + + + BOOT_ADD0 + Boot address 0 + 0 + 16 + + + BOOT_ADD1 + Boot address 1 + 16 + 16 + + + + + BOOT_PRGR + BOOT_PRGR + FLASH register with boot + address + 0x44 + 0x20 + read-only + 0x00000000 + + + BOOT_ADD0 + Boot address 0 + 0 + 16 + + + BOOT_ADD1 + Boot address 1 + 16 + 16 + + + + + CRCCR1 + CRCCR1 + FLASH CRC control register for bank + 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + CRC_SECT + Bank 1 CRC sector number + 0 + 3 + + + ALL_BANK + Bank 1 CRC select bit + 7 + 1 + + + CRC_BY_SECT + Bank 1 CRC sector mode select + bit + 8 + 1 + + + ADD_SECT + Bank 1 CRC sector select + bit + 9 + 1 + + + CLEAN_SECT + Bank 1 CRC sector list clear + bit + 10 + 1 + + + START_CRC + Bank 1 CRC start bit + 16 + 1 + + + CLEAN_CRC + Bank 1 CRC clear bit + 17 + 1 + + + CRC_BURST + Bank 1 CRC burst size + 20 + 2 + + + + + CRCSADD1R + CRCSADD1R + FLASH CRC start address register for bank + 1 + 0x54 + 0x20 + read-write + 0x00000000 + + + CRC_START_ADDR + CRC start address on bank + 1 + 0 + 32 + + + + + CRCEADD1R + CRCEADD1R + FLASH CRC end address register for bank + 1 + 0x58 + 0x20 + read-write + 0x00000000 + + + CRC_END_ADDR + CRC end address on bank 1 + 0 + 32 + + + + + CRCDATAR + CRCDATAR + FLASH CRC data register + 0x5C + 0x20 + read-write + 0x00000000 + + + CRC_DATA + CRC result + 0 + 32 + + + + + ECC_FA1R + ECC_FA1R + FLASH ECC fail address for bank + 1 + 0x60 + 0x20 + read-only + 0x00000000 + + + FAIL_ECC_ADDR1 + Bank 1 ECC error address + 0 + 15 + + + + + KEYR2 + KEYR2 + FLASH key register for bank 2 + 0x104 + 0x20 + read-only + 0x00000000 + + + KEYR2 + Bank 2 access configuration unlock + key + 0 + 32 + + + + + CR2 + CR2 + FLASH control register for bank + 2 + 0x10C + 0x20 + read-write + 0x00000000 + + + LOCK2 + Bank 2 configuration lock + bit + 0 + 1 + + + PG2 + Bank 2 program enable bit + 1 + 1 + + + SER2 + Bank 2 sector erase + request + 2 + 1 + + + BER2 + Bank 2 erase request + 3 + 1 + + + PSIZE2 + Bank 2 program size + 4 + 2 + + + FW2 + Bank 2 write forcing control + bit + 6 + 1 + + + START2 + Bank 2 bank or sector erase start + control bit + 7 + 1 + + + SNB2 + Bank 2 sector erase selection + number + 8 + 3 + + + CRC_EN + Bank 2 CRC control bit + 15 + 1 + + + EOPIE2 + Bank 2 end-of-program interrupt control + bit + 16 + 1 + + + WRPERRIE2 + Bank 2 write protection error interrupt + enable bit + 17 + 1 + + + PGSERRIE2 + Bank 2 programming sequence error + interrupt enable bit + 18 + 1 + + + STRBERRIE2 + Bank 2 strobe error interrupt enable + bit + 19 + 1 + + + INCERRIE2 + Bank 2 inconsistency error interrupt + enable bit + 21 + 1 + + + OPERRIE2 + Bank 2 write/erase error interrupt + enable bit + 22 + 1 + + + RDPERRIE2 + Bank 2 read protection error interrupt + enable bit + 23 + 1 + + + RDSERRIE2 + Bank 2 secure error interrupt enable + bit + 24 + 1 + + + SNECCERRIE2 + Bank 2 ECC single correction error + interrupt enable bit + 25 + 1 + + + DBECCERRIE2 + Bank 2 ECC double detection error + interrupt enable bit + 26 + 1 + + + CRCENDIE2 + Bank 2 end of CRC calculation interrupt + enable bit + 27 + 1 + + + + + SR2 + SR2 + FLASH status register for bank + 2 + 0x110 + 0x20 + read-write + 0x00000000 + + + BSY2 + Bank 2 ongoing program + flag + 0 + 1 + + + WBNE2 + Bank 2 write buffer not empty + flag + 1 + 1 + + + QW2 + Bank 2 wait queue flag + 2 + 1 + + + CRC_BUSY2 + Bank 2 CRC busy flag + 3 + 1 + + + EOP2 + Bank 2 end-of-program flag + 16 + 1 + + + WRPERR2 + Bank 2 write protection error + flag + 17 + 1 + + + PGSERR2 + Bank 2 programming sequence error + flag + 18 + 1 + + + STRBERR2 + Bank 2 strobe error flag + 19 + 1 + + + INCERR2 + Bank 2 inconsistency error + flag + 21 + 1 + + + OPERR2 + Bank 2 write/erase error + flag + 22 + 1 + + + RDPERR2 + Bank 2 read protection error + flag + 23 + 1 + + + RDSERR2 + Bank 2 secure error flag + 24 + 1 + + + SNECCERR2 + Bank 2 single correction error + flag + 25 + 1 + + + DBECCERR2 + Bank 2 ECC double detection error + flag + 26 + 1 + + + CRCEND2 + Bank 2 CRC-complete flag + 27 + 1 + + + + + CCR2 + CCR2 + FLASH clear control register for bank + 2 + 0x114 + 0x20 + read-write + 0x00000000 + + + CLR_EOP2 + Bank 1 EOP1 flag clear bit + 16 + 1 + + + CLR_WRPERR2 + Bank 2 WRPERR1 flag clear + bit + 17 + 1 + + + CLR_PGSERR2 + Bank 2 PGSERR1 flag clear + bi + 18 + 1 + + + CLR_STRBERR2 + Bank 2 STRBERR1 flag clear + bit + 19 + 1 + + + CLR_INCERR2 + Bank 2 INCERR1 flag clear + bit + 21 + 1 + + + CLR_OPERR2 + Bank 2 OPERR1 flag clear + bit + 22 + 1 + + + CLR_RDPERR2 + Bank 2 RDPERR1 flag clear + bit + 23 + 1 + + + CLR_RDSERR1 + Bank 1 RDSERR1 flag clear + bit + 24 + 1 + + + CLR_SNECCERR2 + Bank 2 SNECCERR1 flag clear + bit + 25 + 1 + + + CLR_DBECCERR1 + Bank 1 DBECCERR1 flag clear + bit + 26 + 1 + + + CLR_CRCEND2 + Bank 2 CRCEND1 flag clear + bit + 27 + 1 + + + + + PRAR_CUR2 + PRAR_CUR2 + FLASH protection address for bank + 1 + 0x128 + 0x20 + read-only + 0x00000000 + + + PROT_AREA_START2 + Bank 2 lowest PCROP protected + address + 0 + 12 + + + PROT_AREA_END2 + Bank 2 highest PCROP protected + address + 16 + 12 + + + DMEP2 + Bank 2 PCROP protected erase enable + option status bit + 31 + 1 + + + + + PRAR_PRG2 + PRAR_PRG2 + FLASH protection address for bank + 2 + PRAR_PRG1 + 0x2C + 0x20 + read-write + 0x00000000 + + + PROT_AREA_START2 + Bank 2 lowest PCROP protected address + configuration + 0 + 12 + + + PROT_AREA_END2 + Bank 2 highest PCROP protected address + configuration + 16 + 12 + + + DMEP2 + Bank 2 PCROP protected erase enable + option configuration bit + 31 + 1 + + + + + SCAR_CUR2 + SCAR_CUR2 + FLASH secure address for bank + 2 + 0x130 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START2 + Bank 2 lowest secure protected + address + 0 + 12 + + + SEC_AREA_END2 + Bank 2 highest secure protected + address + 16 + 12 + + + DMES2 + Bank 2 secure protected erase enable + option status bit + 31 + 1 + + + + + SCAR_PRG2 + SCAR_PRG2 + FLASH secure address for bank + 2 + 0x134 + 0x20 + read-write + 0x00000000 + + + SEC_AREA_START2 + Bank 2 lowest secure protected address + configuration + 0 + 12 + + + SEC_AREA_END2 + Bank 2 highest secure protected address + configuration + 16 + 12 + + + DMES2 + Bank 2 secure protected erase enable + option configuration bit + 31 + 1 + + + + + WPSN_CUR2R + WPSN_CUR2R + FLASH write sector protection for bank + 2 + 0x138 + 0x20 + read-only + 0x00000000 + + + WRPSn2 + Bank 2 sector write protection option + status byte + 0 + 8 + + + + + WPSN_PRG2R + WPSN_PRG2R + FLASH write sector protection for bank + 2 + 0x13C + 0x20 + read-write + 0x00000000 + + + WRPSn2 + Bank 2 sector write protection + configuration byte + 0 + 8 + + + + + CRCCR2 + CRCCR2 + FLASH CRC control register for bank + 1 + 0x150 + 0x20 + read-write + 0x00000000 + + + CRC_SECT + Bank 2 CRC sector number + 0 + 3 + + + ALL_BANK + Bank 2 CRC select bit + 7 + 1 + + + CRC_BY_SECT + Bank 2 CRC sector mode select + bit + 8 + 1 + + + ADD_SECT + Bank 2 CRC sector select + bit + 9 + 1 + + + CLEAN_SECT + Bank 2 CRC sector list clear + bit + 10 + 1 + + + START_CRC + Bank 2 CRC start bit + 16 + 1 + + + CLEAN_CRC + Bank 2 CRC clear bit + 17 + 1 + + + CRC_BURST + Bank 2 CRC burst size + 20 + 2 + + + + + CRCSADD2R + CRCSADD2R + FLASH CRC start address register for bank + 2 + 0x154 + 0x20 + read-write + 0x00000000 + + + CRC_START_ADDR + CRC start address on bank + 2 + 0 + 32 + + + + + CRCEADD2R + CRCEADD2R + FLASH CRC end address register for bank + 2 + 0x158 + 0x20 + read-write + 0x00000000 + + + CRC_END_ADDR + CRC end address on bank 2 + 0 + 32 + + + + + ECC_FA2R + ECC_FA2R + FLASH ECC fail address for bank + 2 + 0x160 + 0x20 + read-only + 0x00000000 + + + FAIL_ECC_ADDR2 + Bank 2 ECC error address + 0 + 15 + + + + + + + AXI + AXI interconnect registers + AXI + 0x51000000 + + 0x0 + 0x100000 + registers + + + + AXI_PERIPH_ID_4 + AXI_PERIPH_ID_4 + AXI interconnect - peripheral ID4 + register + 0x1FD0 + 0x20 + read-only + 0x00000004 + + + JEP106CON + JEP106 continuation code + 0 + 4 + + + KCOUNT4 + Register file size + 4 + 4 + + + + + AXI_PERIPH_ID_0 + AXI_PERIPH_ID_0 + AXI interconnect - peripheral ID0 + register + 0x1FE0 + 0x20 + read-only + 0x00000004 + + + PARTNUM + Peripheral part number bits 0 to + 7 + 0 + 8 + + + + + AXI_PERIPH_ID_1 + AXI_PERIPH_ID_1 + AXI interconnect - peripheral ID1 + register + 0x1FE4 + 0x20 + read-only + 0x00000004 + + + PARTNUM + Peripheral part number bits 8 to + 11 + 0 + 4 + + + JEP106I + JEP106 identity bits 0 to + 3 + 4 + 4 + + + + + AXI_PERIPH_ID_2 + AXI_PERIPH_ID_2 + AXI interconnect - peripheral ID2 + register + 0x1FE8 + 0x20 + read-only + 0x00000004 + + + JEP106ID + JEP106 Identity bits 4 to + 6 + 0 + 3 + + + JEDEC + JEP106 code flag + 3 + 1 + + + REVISION + Peripheral revision number + 4 + 4 + + + + + AXI_PERIPH_ID_3 + AXI_PERIPH_ID_3 + AXI interconnect - peripheral ID3 + register + 0x1FEC + 0x20 + read-only + 0x00000004 + + + CUST_MOD_NUM + Customer modification + 0 + 4 + + + REV_AND + Customer version + 4 + 4 + + + + + AXI_COMP_ID_0 + AXI_COMP_ID_0 + AXI interconnect - component ID0 + register + 0x1FF0 + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 0 to 7 + 0 + 8 + + + + + AXI_COMP_ID_1 + AXI_COMP_ID_1 + AXI interconnect - component ID1 + register + 0x1FF4 + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 8 to 11 + 0 + 4 + + + CLASS + Component class + 4 + 4 + + + + + AXI_COMP_ID_2 + AXI_COMP_ID_2 + AXI interconnect - component ID2 + register + 0x1FF8 + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 12 to 19 + 0 + 8 + + + + + AXI_COMP_ID_3 + AXI_COMP_ID_3 + AXI interconnect - component ID3 + register + 0x1FFC + 0x20 + read-only + 0x00000004 + + + PREAMBLE + Preamble bits 20 to 27 + 0 + 8 + + + + + AXI_TARG1_FN_MOD_ISS_BM + AXI_TARG1_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x2008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG2_FN_MOD_ISS_BM + AXI_TARG2_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x3008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG3_FN_MOD_ISS_BM + AXI_TARG3_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x4008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG4_FN_MOD_ISS_BM + AXI_TARG4_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x5008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG5_FN_MOD_ISS_BM + AXI_TARG5_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x6008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG6_FN_MOD_ISS_BM + AXI_TARG6_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x7008 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG7_FN_MOD_ISS_BM + AXI_TARG7_FN_MOD_ISS_BM + AXI interconnect - TARG x bus matrix issuing + functionality register + 0x800C + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + + + WRITE_ISS_OVERRIDE + Switch matrix write issuing override for + target + 1 + 1 + + + + + AXI_TARG1_FN_MOD2 + AXI_TARG1_FN_MOD2 + AXI interconnect - TARG x bus matrix + functionality 2 register + 0x2024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disable packing of beats to match the + output data width + 0 + 1 + + + + + AXI_TARG2_FN_MOD2 + AXI_TARG2_FN_MOD2 + AXI interconnect - TARG x bus matrix + functionality 2 register + 0x3024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disable packing of beats to match the + output data width + 0 + 1 + + + + + AXI_TARG7_FN_MOD2 + AXI_TARG7_FN_MOD2 + AXI interconnect - TARG x bus matrix + functionality 2 register + 0x8024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disable packing of beats to match the + output data width + 0 + 1 + + + + + AXI_TARG1_FN_MOD_LB + AXI_TARG1_FN_MOD_LB + AXI interconnect - TARG x long burst + functionality modification + 0x202C + 0x20 + read-write + 0x00000004 + + + FN_MOD_LB + Controls burst breaking of long + bursts + 0 + 1 + + + + + AXI_TARG2_FN_MOD_LB + AXI_TARG2_FN_MOD_LB + AXI interconnect - TARG x long burst + functionality modification + 0x302C + 0x20 + read-write + 0x00000004 + + + FN_MOD_LB + Controls burst breaking of long + bursts + 0 + 1 + + + + + AXI_TARG1_FN_MOD + AXI_TARG1_FN_MOD + AXI interconnect - TARG x long burst + functionality modification + 0x2108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override AMIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override AMIB write issuing + capability + 1 + 1 + + + + + AXI_TARG2_FN_MOD + AXI_TARG2_FN_MOD + AXI interconnect - TARG x long burst + functionality modification + 0x3108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override AMIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override AMIB write issuing + capability + 1 + 1 + + + + + AXI_TARG7_FN_MOD + AXI_TARG7_FN_MOD + AXI interconnect - TARG x long burst + functionality modification + 0x8108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override AMIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override AMIB write issuing + capability + 1 + 1 + + + + + AXI_INI1_FN_MOD2 + AXI_INI1_FN_MOD2 + AXI interconnect - INI x functionality + modification 2 register + 0x42024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disables alteration of transactions by + the up-sizer unless required by the + protocol + 0 + 1 + + + + + AXI_INI3_FN_MOD2 + AXI_INI3_FN_MOD2 + AXI interconnect - INI x functionality + modification 2 register + 0x44024 + 0x20 + read-write + 0x00000004 + + + BYPASS_MERGE + Disables alteration of transactions by + the up-sizer unless required by the + protocol + 0 + 1 + + + + + AXI_INI1_FN_MOD_AHB + AXI_INI1_FN_MOD_AHB + AXI interconnect - INI x AHB functionality + modification register + 0x42028 + 0x20 + read-write + 0x00000004 + + + RD_INC_OVERRIDE + Converts all AHB-Lite write transactions + to a series of single beat AXI + 0 + 1 + + + WR_INC_OVERRIDE + Converts all AHB-Lite read transactions + to a series of single beat AXI + 1 + 1 + + + + + AXI_INI3_FN_MOD_AHB + AXI_INI3_FN_MOD_AHB + AXI interconnect - INI x AHB functionality + modification register + 0x44028 + 0x20 + read-write + 0x00000004 + + + RD_INC_OVERRIDE + Converts all AHB-Lite write transactions + to a series of single beat AXI + 0 + 1 + + + WR_INC_OVERRIDE + Converts all AHB-Lite read transactions + to a series of single beat AXI + 1 + 1 + + + + + AXI_INI1_READ_QOS + AXI_INI1_READ_QOS + AXI interconnect - INI x read QoS + register + 0x42100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI2_READ_QOS + AXI_INI2_READ_QOS + AXI interconnect - INI x read QoS + register + 0x43100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI3_READ_QOS + AXI_INI3_READ_QOS + AXI interconnect - INI x read QoS + register + 0x44100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI4_READ_QOS + AXI_INI4_READ_QOS + AXI interconnect - INI x read QoS + register + 0x45100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI5_READ_QOS + AXI_INI5_READ_QOS + AXI interconnect - INI x read QoS + register + 0x46100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI6_READ_QOS + AXI_INI6_READ_QOS + AXI interconnect - INI x read QoS + register + 0x47100 + 0x20 + read-write + 0x00000004 + + + AR_QOS + Read channel QoS setting + 0 + 4 + + + + + AXI_INI1_WRITE_QOS + AXI_INI1_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x42104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI2_WRITE_QOS + AXI_INI2_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x43104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI3_WRITE_QOS + AXI_INI3_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x44104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI4_WRITE_QOS + AXI_INI4_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x45104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI5_WRITE_QOS + AXI_INI5_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x46104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI6_WRITE_QOS + AXI_INI6_WRITE_QOS + AXI interconnect - INI x write QoS + register + 0x47104 + 0x20 + read-write + 0x00000004 + + + AW_QOS + Write channel QoS setting + 0 + 4 + + + + + AXI_INI1_FN_MOD + AXI_INI1_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x42108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI2_FN_MOD + AXI_INI2_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x43108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI3_FN_MOD + AXI_INI3_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x44108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI4_FN_MOD + AXI_INI4_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x45108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI5_FN_MOD + AXI_INI5_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x46108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + AXI_INI6_FN_MOD + AXI_INI6_FN_MOD + AXI interconnect - INI x issuing + functionality modification register + 0x47108 + 0x20 + read-write + 0x00000004 + + + READ_ISS_OVERRIDE + Override ASIB read issuing + capability + 0 + 1 + + + WRITE_ISS_OVERRIDE + Override ASIB write issuing + capability + 1 + 1 + + + + + + + DCMI + Digital camera interface + DCMI + 0x48020000 + + 0x0 + 0x400 + registers + + + DCMI + DCMI global interrupt + 78 + + + + CR + CR + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + OELS + Odd/Even Line Select (Line Select + Start) + 20 + 1 + + + LSM + Line Select mode + 19 + 1 + + + OEBS + Odd/Even Byte Select (Byte Select + Start) + 18 + 1 + + + BSM + Byte Select mode + 16 + 2 + + + ENABLE + DCMI enable + 14 + 1 + + + EDM + Extended data mode + 10 + 2 + + + FCRC + Frame capture rate control + 8 + 2 + + + VSPOL + Vertical synchronization + polarity + 7 + 1 + + + HSPOL + Horizontal synchronization + polarity + 6 + 1 + + + PCKPOL + Pixel clock polarity + 5 + 1 + + + ESS + Embedded synchronization + select + 4 + 1 + + + JPEG + JPEG format + 3 + 1 + + + CROP + Crop feature + 2 + 1 + + + CM + Capture mode + 1 + 1 + + + CAPTURE + Capture enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x0000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + HSYNC + HSYNC + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x0000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt + status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt + status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt + status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt + enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt + enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status + register + 0x10 + 0x20 + read-only + 0x0000 + + + LINE_MIS + Line masked interrupt + status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt + status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt + status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt + status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt + status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + LINE_ISC + line interrupt status + clear + 4 + 1 + + + VSYNC_ISC + Vertical synch interrupt status + clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status + clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status + clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status + clear + 0 + 1 + + + + + ESCR + ESCR + embedded synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter + unmask + 8 + 8 + + + FSU + Frame start delimiter + unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x0000 + + + Byte3 + Data byte 3 + 24 + 8 + + + Byte2 + Data byte 2 + 16 + 8 + + + Byte1 + Data byte 1 + 8 + 8 + + + Byte0 + Data byte 0 + 0 + 8 + + + + + + + OTG1_HS_GLOBAL + USB 1 on the go high speed + USB_OTG_HS + 0x40040000 + + 0x0 + 0x400 + registers + + + OTG_FS_EP1_OUT + OTG_FS out global interrupt + 98 + + + OTG_FS_EP1_IN + OTG_FS in global interrupt + 99 + + + OTG_FS_WKUP + OTG_FS wakeup + 100 + + + OTG_FS + OTG_FS global interrupt + 101 + + + + OTG_HS_GOTGCTL + OTG_HS_GOTGCTL + OTG_HS control and status + register + 0x0 + 32 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + EHEN + Embedded host enable + 12 + 1 + read-write + + + + + OTG_HS_GOTGINT + OTG_HS_GOTGINT + OTG_HS interrupt register + 0x4 + 32 + read-write + 0x0 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + IDCHNG + ID input pin changed + 20 + 1 + + + + + OTG_HS_GAHBCFG + OTG_HS_GAHBCFG + OTG_HS AHB configuration + register + 0x8 + 32 + read-write + 0x0 + + + GINT + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst length/type + 1 + 4 + + + DMAEN + DMA enable + 5 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + OTG_HS_GUSBCFG + OTG_HS_GUSBCFG + OTG_HS USB configuration + register + 0xC + 32 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + USB 2.0 high-speed ULPI PHY or USB 1.1 + full-speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + PHYLPCS + PHY Low-power clock select + 15 + 1 + read-write + + + ULPIFSLS + ULPI FS/LS select + 17 + 1 + read-write + + + ULPIAR + ULPI Auto-resume + 18 + 1 + read-write + + + ULPICSM + ULPI Clock SuspendM + 19 + 1 + read-write + + + ULPIEVBUSD + ULPI External VBUS Drive + 20 + 1 + read-write + + + ULPIEVBUSI + ULPI external VBUS + indicator + 21 + 1 + read-write + + + TSDPS + TermSel DLine pulsing + selection + 22 + 1 + read-write + + + PCCI + Indicator complement + 23 + 1 + read-write + + + PTCI + Indicator pass through + 24 + 1 + read-write + + + ULPIIPD + ULPI interface protect + disable + 25 + 1 + read-write + + + FHMOD + Forced host mode + 29 + 1 + read-write + + + FDMOD + Forced peripheral mode + 30 + 1 + read-write + + + + + OTG_HS_GRSTCTL + OTG_HS_GRSTCTL + OTG_HS reset register + 0x10 + 32 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + DMAREQ + DMA request signal enabled for USB OTG + HS + 30 + 1 + read-only + + + + + OTG_HS_GINTSTS + OTG_HS_GINTSTS + OTG_HS core interrupt register + 0x14 + 32 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO nonempty + 4 + 1 + read-only + + + NPTXFE + Nonperiodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN nonperiodic NAK + effective + 6 + 1 + read-only + + + BOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + PXFR_INCOMPISOOUT + Incomplete periodic + transfer + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended + 22 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + OTG_HS_GINTMSK + OTG_HS_GINTMSK + OTG_HS interrupt mask register + 0x18 + 32 + 0x0 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO nonempty mask + 4 + 1 + read-write + + + NPTXFEM + Nonperiodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global nonperiodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + PXFRM_IISOOXFRM + Incomplete periodic transfer + mask + 21 + 1 + read-write + + + FSUSPM + Data fetch suspended mask + 22 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + RSTDE + Reset detected interrupt + mask + 23 + 1 + read-write + + + LPMINTM + LPM interrupt mask + 27 + 1 + read-write + + + + + OTG_HS_GRXSTSR_Host + OTG_HS_GRXSTSR_Host + OTG_HS Receive status debug read register + (host mode) + 0x1C + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXSTSP_Host + OTG_HS_GRXSTSP_Host + OTG_HS status read and pop register (host + mode) + 0x20 + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXFSIZ + OTG_HS_GRXFSIZ + OTG_HS Receive FIFO size + register + 0x24 + 32 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + OTG_HS_HNPTXFSIZ_Host + OTG_HS_HNPTXFSIZ_Host + OTG_HS nonperiodic transmit FIFO size + register (host mode) + 0x28 + 32 + read-write + 0x00000200 + + + NPTXFSA + Nonperiodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Nonperiodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF0_Device + OTG_HS_DIEPTXF0_Device + Endpoint 0 transmit FIFO size (peripheral + mode) + OTG_HS_HNPTXFSIZ_Host + 0x28 + 32 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + OTG_HS_GNPTXSTS + OTG_HS_GNPTXSTS + OTG_HS nonperiodic transmit FIFO/queue + status register + 0x2C + 32 + read-only + 0x00080200 + + + NPTXFSAV + Nonperiodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Nonperiodic transmit request queue space + available + 16 + 8 + + + NPTXQTOP + Top of the nonperiodic transmit request + queue + 24 + 7 + + + + + OTG_HS_GCCFG + OTG_HS_GCCFG + OTG_HS general core configuration + register + 0x38 + 32 + read-write + 0x0 + + + PWRDWN + Power down + 16 + 1 + + + BCDEN + Battery charging detector (BCD) + enable + 17 + 1 + + + DCDEN + Data contact detection (DCD) mode + enable + 18 + 1 + + + PDEN + Primary detection (PD) mode + enable + 19 + 1 + + + SDEN + Secondary detection (SD) mode + enable + 20 + 1 + + + VBDEN + USB VBUS detection enable + 21 + 1 + + + DCDET + Data contact detection (DCD) + status + 0 + 1 + + + PDET + Primary detection (PD) + status + 1 + 1 + + + SDET + Secondary detection (SD) + status + 2 + 1 + + + PS2DET + DM pull-up detection + status + 3 + 1 + + + + + OTG_HS_CID + OTG_HS_CID + OTG_HS core ID register + 0x3C + 32 + read-write + 0x00001200 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + OTG_HS_HPTXFSIZ + OTG_HS_HPTXFSIZ + OTG_HS Host periodic transmit FIFO size + register + 0x100 + 32 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF1 + OTG_HS_DIEPTXF1 + OTG_HS device IN endpoint transmit FIFO size + register + 0x104 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF2 + OTG_HS_DIEPTXF2 + OTG_HS device IN endpoint transmit FIFO size + register + 0x108 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF3 + OTG_HS_DIEPTXF3 + OTG_HS device IN endpoint transmit FIFO size + register + 0x11C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF4 + OTG_HS_DIEPTXF4 + OTG_HS device IN endpoint transmit FIFO size + register + 0x120 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF5 + OTG_HS_DIEPTXF5 + OTG_HS device IN endpoint transmit FIFO size + register + 0x124 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF6 + OTG_HS_DIEPTXF6 + OTG_HS device IN endpoint transmit FIFO size + register + 0x128 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF7 + OTG_HS_DIEPTXF7 + OTG_HS device IN endpoint transmit FIFO size + register + 0x12C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_GRXSTSR_Device + OTG_HS_GRXSTSR_Device + OTG_HS Receive status debug read register + (peripheral mode mode) + OTG_HS_GRXSTSR_Host + 0x1C + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GRXSTSP_Device + OTG_HS_GRXSTSP_Device + OTG_HS status read and pop register + (peripheral mode) + OTG_HS_GRXSTSP_Host + 0x20 + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GLPMCFG + OTG_HS_GLPMCFG + OTG core LPM configuration + register + 0x54 + 32 + 0x0 + + + LPMEN + LPM support enable + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge + enable + 1 + 1 + read-write + + + BESL + Best effort service + latency + 2 + 4 + read-only + + + REMWAKE + bRemoteWake value + 6 + 1 + read-only + + + L1SSEN + L1 Shallow Sleep enable + 7 + 1 + read-write + + + BESLTHRS + BESL threshold + 8 + 4 + read-write + + + L1DSEN + L1 deep sleep enable + 12 + 1 + read-write + + + LPMRST + LPM response + 13 + 2 + read-only + + + SLPSTS + Port sleep status + 15 + 1 + read-only + + + L1RSMOK + Sleep State Resume OK + 16 + 1 + read-only + + + LPMCHIDX + LPM Channel Index + 17 + 4 + read-write + + + LPMRCNT + LPM retry count + 21 + 3 + read-write + + + SNDLPM + Send LPM transaction + 24 + 1 + read-write + + + LPMRCNTSTS + LPM retry count status + 25 + 3 + read-only + + + ENBESL + Enable best effort service + latency + 28 + 1 + read-write + + + + + + + OTG2_HS_GLOBAL + 0x40080000 + + OTG_HS_EP1_OUT + OTG_HS out global interrupt + 74 + + + OTG_HS_EP1_IN + OTG_HS in global interrupt + 75 + + + OTG_HS_WKUP + OTG_HS wakeup interrupt + 76 + + + OTG_HS + OTG_HS global interrupt + 77 + + + + OTG1_HS_HOST + USB 1 on the go high speed + USB_OTG_HS + 0x40040400 + + 0x0 + 0x400 + registers + + + + OTG_HS_HCFG + OTG_HS_HCFG + OTG_HS host configuration + register + 0x0 + 32 + 0x0 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + OTG_HS_HFIR + OTG_HS_HFIR + OTG_HS Host frame interval + register + 0x4 + 32 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + OTG_HS_HFNUM + OTG_HS_HFNUM + OTG_HS host frame number/frame time + remaining register + 0x8 + 32 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + OTG_HS_HPTXSTS + OTG_HS_HPTXSTS + OTG_HS_Host periodic transmit FIFO/queue + status register + 0x10 + 32 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + OTG_HS_HAINT + OTG_HS_HAINT + OTG_HS Host all channels interrupt + register + 0x14 + 32 + read-only + 0x0 + + + HAINT + Channel interrupts + 0 + 16 + + + + + OTG_HS_HAINTMSK + OTG_HS_HAINTMSK + OTG_HS host all channels interrupt mask + register + 0x18 + 32 + read-write + 0x0 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + OTG_HS_HPRT + OTG_HS_HPRT + OTG_HS host port control and status + register + 0x40 + 32 + 0x0 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + OTG_HS_HCCHAR0 + OTG_HS_HCCHAR0 + OTG_HS host channel-0 characteristics + register + 0x100 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR1 + OTG_HS_HCCHAR1 + OTG_HS host channel-1 characteristics + register + 0x120 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR2 + OTG_HS_HCCHAR2 + OTG_HS host channel-2 characteristics + register + 0x140 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR3 + OTG_HS_HCCHAR3 + OTG_HS host channel-3 characteristics + register + 0x160 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR4 + OTG_HS_HCCHAR4 + OTG_HS host channel-4 characteristics + register + 0x180 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR5 + OTG_HS_HCCHAR5 + OTG_HS host channel-5 characteristics + register + 0x1A0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR6 + OTG_HS_HCCHAR6 + OTG_HS host channel-6 characteristics + register + 0x1C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR7 + OTG_HS_HCCHAR7 + OTG_HS host channel-7 characteristics + register + 0x1E0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR8 + OTG_HS_HCCHAR8 + OTG_HS host channel-8 characteristics + register + 0x200 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR9 + OTG_HS_HCCHAR9 + OTG_HS host channel-9 characteristics + register + 0x220 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR10 + OTG_HS_HCCHAR10 + OTG_HS host channel-10 characteristics + register + 0x240 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR11 + OTG_HS_HCCHAR11 + OTG_HS host channel-11 characteristics + register + 0x260 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT0 + OTG_HS_HCSPLT0 + OTG_HS host channel-0 split control + register + 0x104 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT1 + OTG_HS_HCSPLT1 + OTG_HS host channel-1 split control + register + 0x124 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT2 + OTG_HS_HCSPLT2 + OTG_HS host channel-2 split control + register + 0x144 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT3 + OTG_HS_HCSPLT3 + OTG_HS host channel-3 split control + register + 0x164 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT4 + OTG_HS_HCSPLT4 + OTG_HS host channel-4 split control + register + 0x184 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT5 + OTG_HS_HCSPLT5 + OTG_HS host channel-5 split control + register + 0x1A4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT6 + OTG_HS_HCSPLT6 + OTG_HS host channel-6 split control + register + 0x1C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT7 + OTG_HS_HCSPLT7 + OTG_HS host channel-7 split control + register + 0x1E4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT8 + OTG_HS_HCSPLT8 + OTG_HS host channel-8 split control + register + 0x204 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT9 + OTG_HS_HCSPLT9 + OTG_HS host channel-9 split control + register + 0x224 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT10 + OTG_HS_HCSPLT10 + OTG_HS host channel-10 split control + register + 0x244 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT11 + OTG_HS_HCSPLT11 + OTG_HS host channel-11 split control + register + 0x264 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT0 + OTG_HS_HCINT0 + OTG_HS host channel-11 interrupt + register + 0x108 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT1 + OTG_HS_HCINT1 + OTG_HS host channel-1 interrupt + register + 0x128 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT2 + OTG_HS_HCINT2 + OTG_HS host channel-2 interrupt + register + 0x148 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT3 + OTG_HS_HCINT3 + OTG_HS host channel-3 interrupt + register + 0x168 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT4 + OTG_HS_HCINT4 + OTG_HS host channel-4 interrupt + register + 0x188 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT5 + OTG_HS_HCINT5 + OTG_HS host channel-5 interrupt + register + 0x1A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT6 + OTG_HS_HCINT6 + OTG_HS host channel-6 interrupt + register + 0x1C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT7 + OTG_HS_HCINT7 + OTG_HS host channel-7 interrupt + register + 0x1E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT8 + OTG_HS_HCINT8 + OTG_HS host channel-8 interrupt + register + 0x208 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT9 + OTG_HS_HCINT9 + OTG_HS host channel-9 interrupt + register + 0x228 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT10 + OTG_HS_HCINT10 + OTG_HS host channel-10 interrupt + register + 0x248 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT11 + OTG_HS_HCINT11 + OTG_HS host channel-11 interrupt + register + 0x268 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK0 + OTG_HS_HCINTMSK0 + OTG_HS host channel-11 interrupt mask + register + 0x10C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK1 + OTG_HS_HCINTMSK1 + OTG_HS host channel-1 interrupt mask + register + 0x12C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK2 + OTG_HS_HCINTMSK2 + OTG_HS host channel-2 interrupt mask + register + 0x14C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK3 + OTG_HS_HCINTMSK3 + OTG_HS host channel-3 interrupt mask + register + 0x16C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK4 + OTG_HS_HCINTMSK4 + OTG_HS host channel-4 interrupt mask + register + 0x18C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK5 + OTG_HS_HCINTMSK5 + OTG_HS host channel-5 interrupt mask + register + 0x1AC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK6 + OTG_HS_HCINTMSK6 + OTG_HS host channel-6 interrupt mask + register + 0x1CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK7 + OTG_HS_HCINTMSK7 + OTG_HS host channel-7 interrupt mask + register + 0x1EC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK8 + OTG_HS_HCINTMSK8 + OTG_HS host channel-8 interrupt mask + register + 0x20C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK9 + OTG_HS_HCINTMSK9 + OTG_HS host channel-9 interrupt mask + register + 0x22C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK10 + OTG_HS_HCINTMSK10 + OTG_HS host channel-10 interrupt mask + register + 0x24C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK11 + OTG_HS_HCINTMSK11 + OTG_HS host channel-11 interrupt mask + register + 0x26C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ0 + OTG_HS_HCTSIZ0 + OTG_HS host channel-11 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ1 + OTG_HS_HCTSIZ1 + OTG_HS host channel-1 transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ2 + OTG_HS_HCTSIZ2 + OTG_HS host channel-2 transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ3 + OTG_HS_HCTSIZ3 + OTG_HS host channel-3 transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ4 + OTG_HS_HCTSIZ4 + OTG_HS host channel-4 transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ5 + OTG_HS_HCTSIZ5 + OTG_HS host channel-5 transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ6 + OTG_HS_HCTSIZ6 + OTG_HS host channel-6 transfer size + register + 0x1D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ7 + OTG_HS_HCTSIZ7 + OTG_HS host channel-7 transfer size + register + 0x1F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ8 + OTG_HS_HCTSIZ8 + OTG_HS host channel-8 transfer size + register + 0x210 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ9 + OTG_HS_HCTSIZ9 + OTG_HS host channel-9 transfer size + register + 0x230 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ10 + OTG_HS_HCTSIZ10 + OTG_HS host channel-10 transfer size + register + 0x250 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ11 + OTG_HS_HCTSIZ11 + OTG_HS host channel-11 transfer size + register + 0x270 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA0 + OTG_HS_HCDMA0 + OTG_HS host channel-0 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA1 + OTG_HS_HCDMA1 + OTG_HS host channel-1 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA2 + OTG_HS_HCDMA2 + OTG_HS host channel-2 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA3 + OTG_HS_HCDMA3 + OTG_HS host channel-3 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA4 + OTG_HS_HCDMA4 + OTG_HS host channel-4 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA5 + OTG_HS_HCDMA5 + OTG_HS host channel-5 DMA address + register + 0x1B4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA6 + OTG_HS_HCDMA6 + OTG_HS host channel-6 DMA address + register + 0x1D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA7 + OTG_HS_HCDMA7 + OTG_HS host channel-7 DMA address + register + 0x1F4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA8 + OTG_HS_HCDMA8 + OTG_HS host channel-8 DMA address + register + 0x214 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA9 + OTG_HS_HCDMA9 + OTG_HS host channel-9 DMA address + register + 0x234 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA10 + OTG_HS_HCDMA10 + OTG_HS host channel-10 DMA address + register + 0x254 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA11 + OTG_HS_HCDMA11 + OTG_HS host channel-11 DMA address + register + 0x274 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR12 + OTG_HS_HCCHAR12 + OTG_HS host channel-12 characteristics + register + 0x278 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT12 + OTG_HS_HCSPLT12 + OTG_HS host channel-12 split control + register + 0x27C + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT12 + OTG_HS_HCINT12 + OTG_HS host channel-12 interrupt + register + 0x280 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK12 + OTG_HS_HCINTMSK12 + OTG_HS host channel-12 interrupt mask + register + 0x284 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ12 + OTG_HS_HCTSIZ12 + OTG_HS host channel-12 transfer size + register + 0x288 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA12 + OTG_HS_HCDMA12 + OTG_HS host channel-12 DMA address + register + 0x28C + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR13 + OTG_HS_HCCHAR13 + OTG_HS host channel-13 characteristics + register + 0x290 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT13 + OTG_HS_HCSPLT13 + OTG_HS host channel-13 split control + register + 0x294 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT13 + OTG_HS_HCINT13 + OTG_HS host channel-13 interrupt + register + 0x298 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK13 + OTG_HS_HCINTMSK13 + OTG_HS host channel-13 interrupt mask + register + 0x29C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALLM response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ13 + OTG_HS_HCTSIZ13 + OTG_HS host channel-13 transfer size + register + 0x2A0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA13 + OTG_HS_HCDMA13 + OTG_HS host channel-13 DMA address + register + 0x2A4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR14 + OTG_HS_HCCHAR14 + OTG_HS host channel-14 characteristics + register + 0x2A8 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT14 + OTG_HS_HCSPLT14 + OTG_HS host channel-14 split control + register + 0x2AC + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT14 + OTG_HS_HCINT14 + OTG_HS host channel-14 interrupt + register + 0x2B0 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK14 + OTG_HS_HCINTMSK14 + OTG_HS host channel-14 interrupt mask + register + 0x2B4 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAKM response received interrupt + mask + 4 + 1 + + + ACKM + ACKM response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ14 + OTG_HS_HCTSIZ14 + OTG_HS host channel-14 transfer size + register + 0x2B8 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA14 + OTG_HS_HCDMA14 + OTG_HS host channel-14 DMA address + register + 0x2BC + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCCHAR15 + OTG_HS_HCCHAR15 + OTG_HS host channel-15 characteristics + register + 0x2C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT15 + OTG_HS_HCSPLT15 + OTG_HS host channel-15 split control + register + 0x2C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT15 + OTG_HS_HCINT15 + OTG_HS host channel-15 interrupt + register + 0x2C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK15 + OTG_HS_HCINTMSK15 + OTG_HS host channel-15 interrupt mask + register + 0x2CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERRM + Transaction error + 7 + 1 + + + BBERRM + Babble error + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ15 + OTG_HS_HCTSIZ15 + OTG_HS host channel-15 transfer size + register + 0x2D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA15 + OTG_HS_HCDMA15 + OTG_HS host channel-15 DMA address + register + 0x2D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + + + OTG2_HS_HOST + 0x40080400 + + + OTG1_HS_DEVICE + USB 1 on the go high speed + USB_OTG_HS + 0x40040800 + + 0x0 + 0x400 + registers + + + + OTG_HS_DCFG + OTG_HS_DCFG + OTG_HS device configuration + register + 0x0 + 32 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Nonzero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic (micro)frame + interval + 11 + 2 + + + PERSCHIVL + Periodic scheduling + interval + 24 + 2 + + + + + OTG_HS_DCTL + OTG_HS_DCTL + OTG_HS device control register + 0x4 + 32 + 0x0 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + OTG_HS_DSTS + OTG_HS_DSTS + OTG_HS device status register + 0x8 + 32 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + OTG_HS_DIEPMSK + OTG_HS_DIEPMSK + OTG_HS device IN endpoint common interrupt + mask register + 0x10 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DOEPMSK + OTG_HS_DOEPMSK + OTG_HS device OUT endpoint common interrupt + mask register + 0x14 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + mask + 6 + 1 + + + OPEM + OUT packet error mask + 8 + 1 + + + BOIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DAINT + OTG_HS_DAINT + OTG_HS device all endpoints interrupt + register + 0x18 + 32 + read-only + 0x0 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + OTG_HS_DAINTMSK + OTG_HS_DAINTMSK + OTG_HS all endpoints interrupt mask + register + 0x1C + 32 + read-write + 0x0 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + OTG_HS_DVBUSDIS + OTG_HS_DVBUSDIS + OTG_HS device VBUS discharge time + register + 0x28 + 32 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + OTG_HS_DVBUSPULSE + OTG_HS_DVBUSPULSE + OTG_HS device VBUS pulsing time + register + 0x2C + 32 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + OTG_HS_DTHRCTL + OTG_HS_DTHRCTL + OTG_HS Device threshold control + register + 0x30 + 32 + read-write + 0x0 + + + NONISOTHREN + Nonisochronous IN endpoints threshold + enable + 0 + 1 + + + ISOTHREN + ISO IN endpoint threshold + enable + 1 + 1 + + + TXTHRLEN + Transmit threshold length + 2 + 9 + + + RXTHREN + Receive threshold enable + 16 + 1 + + + RXTHRLEN + Receive threshold length + 17 + 9 + + + ARPEN + Arbiter parking enable + 27 + 1 + + + + + OTG_HS_DIEPEMPMSK + OTG_HS_DIEPEMPMSK + OTG_HS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 32 + read-write + 0x0 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + OTG_HS_DEACHINT + OTG_HS_DEACHINT + OTG_HS device each endpoint interrupt + register + 0x38 + 32 + read-write + 0x0 + + + IEP1INT + IN endpoint 1interrupt bit + 1 + 1 + + + OEP1INT + OUT endpoint 1 interrupt + bit + 17 + 1 + + + + + OTG_HS_DEACHINTMSK + OTG_HS_DEACHINTMSK + OTG_HS device each endpoint interrupt + register mask + 0x3C + 32 + read-write + 0x0 + + + IEP1INTM + IN Endpoint 1 interrupt mask + bit + 1 + 1 + + + OEP1INTM + OUT Endpoint 1 interrupt mask + bit + 17 + 1 + + + + + OTG_HS_DIEPCTL0 + OTG_HS_DIEPCTL0 + OTG device endpoint-0 control + register + 0x100 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL1 + OTG_HS_DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL2 + OTG_HS_DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL3 + OTG_HS_DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL4 + OTG_HS_DIEPCTL4 + OTG device endpoint-4 control + register + 0x180 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL5 + OTG_HS_DIEPCTL5 + OTG device endpoint-5 control + register + 0x1A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL6 + OTG_HS_DIEPCTL6 + OTG device endpoint-6 control + register + 0x1C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL7 + OTG_HS_DIEPCTL7 + OTG device endpoint-7 control + register + 0x1E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPINT0 + OTG_HS_DIEPINT0 + OTG device endpoint-0 interrupt + register + 0x108 + 32 + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT1 + OTG_HS_DIEPINT1 + OTG device endpoint-1 interrupt + register + 0x128 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT2 + OTG_HS_DIEPINT2 + OTG device endpoint-2 interrupt + register + 0x148 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT3 + OTG_HS_DIEPINT3 + OTG device endpoint-3 interrupt + register + 0x168 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT4 + OTG_HS_DIEPINT4 + OTG device endpoint-4 interrupt + register + 0x188 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT5 + OTG_HS_DIEPINT5 + OTG device endpoint-5 interrupt + register + 0x1A8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT6 + OTG_HS_DIEPINT6 + OTG device endpoint-6 interrupt + register + 0x1C8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT7 + OTG_HS_DIEPINT7 + OTG device endpoint-7 interrupt + register + 0x1E8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPTSIZ0 + OTG_HS_DIEPTSIZ0 + OTG_HS device IN endpoint 0 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + OTG_HS_DIEPDMA1 + OTG_HS_DIEPDMA1 + OTG_HS device endpoint-1 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA2 + OTG_HS_DIEPDMA2 + OTG_HS device endpoint-2 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA3 + OTG_HS_DIEPDMA3 + OTG_HS device endpoint-3 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA4 + OTG_HS_DIEPDMA4 + OTG_HS device endpoint-4 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA5 + OTG_HS_DIEPDMA5 + OTG_HS device endpoint-5 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DTXFSTS0 + OTG_HS_DTXFSTS0 + OTG_HS device IN endpoint transmit FIFO + status register + 0x118 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS1 + OTG_HS_DTXFSTS1 + OTG_HS device IN endpoint transmit FIFO + status register + 0x138 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS2 + OTG_HS_DTXFSTS2 + OTG_HS device IN endpoint transmit FIFO + status register + 0x158 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS3 + OTG_HS_DTXFSTS3 + OTG_HS device IN endpoint transmit FIFO + status register + 0x178 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS4 + OTG_HS_DTXFSTS4 + OTG_HS device IN endpoint transmit FIFO + status register + 0x198 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS5 + OTG_HS_DTXFSTS5 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1B8 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ1 + OTG_HS_DIEPTSIZ1 + OTG_HS device endpoint transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ2 + OTG_HS_DIEPTSIZ2 + OTG_HS device endpoint transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ3 + OTG_HS_DIEPTSIZ3 + OTG_HS device endpoint transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ4 + OTG_HS_DIEPTSIZ4 + OTG_HS device endpoint transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ5 + OTG_HS_DIEPTSIZ5 + OTG_HS device endpoint transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DOEPCTL0 + OTG_HS_DOEPCTL0 + OTG_HS device control OUT endpoint 0 control + register + 0x300 + 32 + 0x00008000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-only + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + write-only + + + + + OTG_HS_DOEPCTL1 + OTG_HS_DOEPCTL1 + OTG device endpoint-1 control + register + 0x320 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL2 + OTG_HS_DOEPCTL2 + OTG device endpoint-2 control + register + 0x340 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL3 + OTG_HS_DOEPCTL3 + OTG device endpoint-3 control + register + 0x360 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPINT0 + OTG_HS_DOEPINT0 + OTG_HS device endpoint-0 interrupt + register + 0x308 + 32 + read-write + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT1 + OTG_HS_DOEPINT1 + OTG_HS device endpoint-1 interrupt + register + 0x328 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT2 + OTG_HS_DOEPINT2 + OTG_HS device endpoint-2 interrupt + register + 0x348 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT3 + OTG_HS_DOEPINT3 + OTG_HS device endpoint-3 interrupt + register + 0x368 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT4 + OTG_HS_DOEPINT4 + OTG_HS device endpoint-4 interrupt + register + 0x388 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT5 + OTG_HS_DOEPINT5 + OTG_HS device endpoint-5 interrupt + register + 0x3A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT6 + OTG_HS_DOEPINT6 + OTG_HS device endpoint-6 interrupt + register + 0x3C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT7 + OTG_HS_DOEPINT7 + OTG_HS device endpoint-7 interrupt + register + 0x3E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPTSIZ0 + OTG_HS_DOEPTSIZ0 + OTG_HS device endpoint-0 transfer size + register + 0x310 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + STUPCNT + SETUP packet count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ1 + OTG_HS_DOEPTSIZ1 + OTG_HS device endpoint-1 transfer size + register + 0x330 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ2 + OTG_HS_DOEPTSIZ2 + OTG_HS device endpoint-2 transfer size + register + 0x350 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ3 + OTG_HS_DOEPTSIZ3 + OTG_HS device endpoint-3 transfer size + register + 0x370 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ4 + OTG_HS_DOEPTSIZ4 + OTG_HS device endpoint-4 transfer size + register + 0x390 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ6 + OTG_HS_DIEPTSIZ6 + OTG_HS device endpoint transfer size + register + OTG_HS_DIEPCTL5 + 0x1A0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DTXFSTS6 + OTG_HS_DTXFSTS6 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1A4 + 32 + read-write + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ7 + OTG_HS_DIEPTSIZ7 + OTG_HS device endpoint transfer size + register + OTG_HS_DIEPINT5 + 0x1A8 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DTXFSTS7 + OTG_HS_DTXFSTS7 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1AC + 32 + read-write + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DOEPCTL4 + OTG_HS_DOEPCTL4 + OTG device endpoint-4 control + register + 0x380 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL5 + OTG_HS_DOEPCTL5 + OTG device endpoint-5 control + register + 0x3A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL6 + OTG_HS_DOEPCTL6 + OTG device endpoint-6 control + register + 0x3C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL7 + OTG_HS_DOEPCTL7 + OTG device endpoint-7 control + register + 0x3E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPTSIZ5 + OTG_HS_DOEPTSIZ5 + OTG_HS device endpoint-5 transfer size + register + 0x3B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ6 + OTG_HS_DOEPTSIZ6 + OTG_HS device endpoint-6 transfer size + register + 0x3D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ7 + OTG_HS_DOEPTSIZ7 + OTG_HS device endpoint-7 transfer size + register + 0x3F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + + + OTG2_HS_DEVICE + 0x40080800 + + + OTG1_HS_PWRCLK + USB 1 on the go high speed + USB_OTG_HS + 0x40040E00 + + 0x0 + 0x3F200 + registers + + + + OTG_HS_PCGCR + OTG_HS_PCGCR + Power and clock gating control + register + 0x0 + 32 + read-write + 0x0 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY suspended + 4 + 1 + + + + + + + OTG2_HS_PWRCLK + 0x40080E00 + + + Ethernet_MAC + Ethernet: media access control + (MAC) + Ethernet + 0x40028000 + + 0x0 + 0x1400 + registers + + + ETH + Ethernet global interrupt + 61 + + + ETH_WKUP + Ethernet wakeup through EXTI + 62 + + + + DMAMR + DMAMR + DMA mode register + 0x1000 + 0x20 + 0x00000000 + + + SWR + Software Reset + 0 + 1 + read-write + + + DA + DMA Tx or Rx Arbitration + Scheme + 1 + 1 + read-only + + + TXPR + Transmit priority + 11 + 1 + read-only + + + PR + Priority ratio + 12 + 3 + read-only + + + INTM + Interrupt Mode + 16 + 1 + read-write + + + + + DMASBMR + DMASBMR + System bus mode register + 0x1004 + 0x20 + 0x01010000 + + + FB + Fixed Burst Length + 0 + 1 + read-write + + + AAL + Address-Aligned Beats + 12 + 1 + read-write + + + MB + Mixed Burst + 14 + 1 + read-only + + + RB + Rebuild INCRx Burst + 15 + 1 + read-only + + + + + DMAISR + DMAISR + Interrupt status register + 0x1008 + 0x20 + read-only + 0x00000000 + + + DC0IS + DMA Channel Interrupt + Status + 0 + 1 + + + MTLIS + MTL Interrupt Status + 16 + 1 + + + MACIS + MAC Interrupt Status + 17 + 1 + + + + + DMADSR + DMADSR + Debug status register + 0x100C + 0x20 + read-only + 0x00000000 + + + AXWHSTS + AHB Master Write Channel + 0 + 1 + + + RPS0 + DMA Channel Receive Process + State + 8 + 4 + + + TPS0 + DMA Channel Transmit Process + State + 12 + 4 + + + + + DMACCR + DMACCR + Channel control register + 0x1100 + 0x20 + read-write + 0x00000000 + + + MSS + Maximum Segment Size + 0 + 14 + + + PBLX8 + 8xPBL mode + 16 + 1 + + + DSL + Descriptor Skip Length + 18 + 3 + + + + + DMACTxCR + DMACTxCR + Channel transmit control + register + 0x1104 + 0x20 + read-write + 0x00000000 + + + ST + Start or Stop Transmission + Command + 0 + 1 + + + OSF + Operate on Second Packet + 4 + 1 + + + TSE + TCP Segmentation Enabled + 12 + 1 + + + TXPBL + Transmit Programmable Burst + Length + 16 + 6 + + + + + DMACRxCR + DMACRxCR + Channel receive control + register + 0x1108 + 0x20 + read-write + 0x00000000 + + + SR + Start or Stop Receive + Command + 0 + 1 + + + RBSZ + Receive Buffer size + 1 + 14 + + + RXPBL + RXPBL + 16 + 6 + + + RPF + DMA Rx Channel Packet + Flush + 31 + 1 + + + + + DMACTxDLAR + DMACTxDLAR + Channel Tx descriptor list address + register + 0x1114 + 0x20 + read-write + 0x00000000 + + + TDESLA + Start of Transmit List + 2 + 30 + + + + + DMACRxDLAR + DMACRxDLAR + Channel Rx descriptor list address + register + 0x111C + 0x20 + read-write + 0x00000000 + + + RDESLA + Start of Receive List + 2 + 30 + + + + + DMACTxDTPR + DMACTxDTPR + Channel Tx descriptor tail pointer + register + 0x1120 + 0x20 + read-write + 0x00000000 + + + TDT + Transmit Descriptor Tail + Pointer + 2 + 30 + + + + + DMACRxDTPR + DMACRxDTPR + Channel Rx descriptor tail pointer + register + 0x1128 + 0x20 + read-write + 0x00000000 + + + RDT + Receive Descriptor Tail + Pointer + 2 + 30 + + + + + DMACTxRLR + DMACTxRLR + Channel Tx descriptor ring length + register + 0x112C + 0x20 + read-write + 0x00000000 + + + TDRL + Transmit Descriptor Ring + Length + 0 + 10 + + + + + DMACRxRLR + DMACRxRLR + Channel Rx descriptor ring length + register + 0x1130 + 0x20 + read-write + 0x00000000 + + + RDRL + Receive Descriptor Ring + Length + 0 + 10 + + + + + DMACIER + DMACIER + Channel interrupt enable + register + 0x1134 + 0x20 + read-write + 0x00000000 + + + TIE + Transmit Interrupt Enable + 0 + 1 + + + TXSE + Transmit Stopped Enable + 1 + 1 + + + TBUE + Transmit Buffer Unavailable + Enable + 2 + 1 + + + RIE + Receive Interrupt Enable + 6 + 1 + + + RBUE + Receive Buffer Unavailable + Enable + 7 + 1 + + + RSE + Receive Stopped Enable + 8 + 1 + + + RWTE + Receive Watchdog Timeout + Enable + 9 + 1 + + + ETIE + Early Transmit Interrupt + Enable + 10 + 1 + + + ERIE + Early Receive Interrupt + Enable + 11 + 1 + + + FBEE + Fatal Bus Error Enable + 12 + 1 + + + CDEE + Context Descriptor Error + Enable + 13 + 1 + + + AIE + Abnormal Interrupt Summary + Enable + 14 + 1 + + + NIE + Normal Interrupt Summary + Enable + 15 + 1 + + + + + DMACRxIWTR + DMACRxIWTR + Channel Rx interrupt watchdog timer + register + 0x1138 + 0x20 + read-write + 0x00000000 + + + RWT + Receive Interrupt Watchdog Timer + Count + 0 + 8 + + + + + DMACCATxDR + DMACCATxDR + Channel current application transmit + descriptor register + 0x1144 + 0x20 + read-only + 0x00000000 + + + CURTDESAPTR + Application Transmit Descriptor Address + Pointer + 0 + 32 + + + + + DMACCARxDR + DMACCARxDR + Channel current application receive + descriptor register + 0x114C + 0x20 + read-only + 0x00000000 + + + CURRDESAPTR + Application Receive Descriptor Address + Pointer + 0 + 32 + + + + + DMACCATxBR + DMACCATxBR + Channel current application transmit buffer + register + 0x1154 + 0x20 + read-only + 0x00000000 + + + CURTBUFAPTR + Application Transmit Buffer Address + Pointer + 0 + 32 + + + + + DMACCARxBR + DMACCARxBR + Channel current application receive buffer + register + 0x115C + 0x20 + read-only + 0x00000000 + + + CURRBUFAPTR + Application Receive Buffer Address + Pointer + 0 + 32 + + + + + DMACSR + DMACSR + Channel status register + 0x1160 + 0x20 + 0x00000000 + + + TI + Transmit Interrupt + 0 + 1 + read-write + + + TPS + Transmit Process Stopped + 1 + 1 + read-write + + + TBU + Transmit Buffer + Unavailable + 2 + 1 + read-write + + + RI + Receive Interrupt + 6 + 1 + read-write + + + RBU + Receive Buffer Unavailable + 7 + 1 + read-write + + + RPS + Receive Process Stopped + 8 + 1 + read-write + + + RWT + Receive Watchdog Timeout + 9 + 1 + read-write + + + ET + Early Transmit Interrupt + 10 + 1 + read-write + + + ER + Early Receive Interrupt + 11 + 1 + read-write + + + FBE + Fatal Bus Error + 12 + 1 + read-write + + + CDE + Context Descriptor Error + 13 + 1 + read-write + + + AIS + Abnormal Interrupt Summary + 14 + 1 + read-write + + + NIS + Normal Interrupt Summary + 15 + 1 + read-write + + + TEB + Tx DMA Error Bits + 16 + 3 + read-only + + + REB + Rx DMA Error Bits + 19 + 3 + read-only + + + + + DMACMFCR + DMACMFCR + Channel missed frame count + register + 0x116C + 0x20 + read-only + 0x00000000 + + + MFC + Dropped Packet Counters + 0 + 11 + + + MFCO + Overflow status of the MFC + Counter + 15 + 1 + + + + + MTLOMR + MTLOMR + Operating mode Register + 0xC00 + 0x20 + read-write + 0x00000000 + + + DTXSTS + DTXSTS + 1 + 1 + + + CNTPRST + CNTPRST + 8 + 1 + + + CNTCLR + CNTCLR + 9 + 1 + + + + + MTLISR + MTLISR + Interrupt status Register + 0xC20 + 0x20 + read-only + 0x00000000 + + + Q0IS + Queue interrupt status + 0 + 1 + + + + + MTLTxQOMR + MTLTxQOMR + Tx queue operating mode + Register + 0xD00 + 0x20 + 0x00070008 + + + FTQ + Flush Transmit Queue + 0 + 1 + read-write + + + TSF + Transmit Store and Forward + 1 + 1 + read-write + + + TXQEN + Transmit Queue Enable + 2 + 2 + read-only + + + TTC + Transmit Threshold Control + 4 + 3 + read-write + + + TQS + Transmit Queue Size + 16 + 9 + read-write + + + + + MTLTxQUR + MTLTxQUR + Tx queue underflow register + 0xD04 + 0x20 + read-only + 0x00000000 + + + UFFRMCNT + Underflow Packet Counter + 0 + 11 + + + UFCNTOVF + UFCNTOVF + 11 + 1 + + + + + MTLTxQDR + MTLTxQDR + Tx queue debug Register + 0xD08 + 0x20 + read-only + 0x00000000 + + + TXQPAUSED + TXQPAUSED + 0 + 1 + + + TRCSTS + TRCSTS + 1 + 2 + + + TWCSTS + TWCSTS + 3 + 1 + + + TXQSTS + TXQSTS + 4 + 1 + + + TXSTSFSTS + TXSTSFSTS + 5 + 1 + + + PTXQ + PTXQ + 16 + 3 + + + STXSTSF + STXSTSF + 20 + 3 + + + + + MTLQICSR + MTLQICSR + Queue interrupt control status + Register + 0xD2C + 0x20 + read-write + 0x00000000 + + + TXUNFIS + TXUNFIS + 0 + 1 + + + TXUIE + TXUIE + 8 + 1 + + + RXOVFIS + RXOVFIS + 16 + 1 + + + RXOIE + RXOIE + 24 + 1 + + + + + MTLRxQOMR + MTLRxQOMR + Rx queue operating mode + register + 0xD30 + 0x20 + 0x00700000 + + + RTC + RTC + 0 + 2 + read-write + + + FUP + FUP + 3 + 1 + read-write + + + FEP + FEP + 4 + 1 + read-write + + + RSF + RSF + 5 + 1 + read-write + + + DIS_TCP_EF + DIS_TCP_EF + 6 + 1 + read-write + + + EHFC + EHFC + 7 + 1 + read-write + + + RFA + RFA + 8 + 3 + read-write + + + RFD + RFD + 14 + 3 + read-write + + + RQS + RQS + 20 + 3 + read-only + + + + + MTLRxQMPOCR + MTLRxQMPOCR + Rx queue missed packet and overflow counter + register + 0xD34 + 0x20 + read-only + 0x00000000 + + + OVFPKTCNT + OVFPKTCNT + 0 + 11 + + + OVFCNTOVF + OVFCNTOVF + 11 + 1 + + + MISPKTCNT + MISPKTCNT + 16 + 11 + + + MISCNTOVF + MISCNTOVF + 27 + 1 + + + + + MTLRxQDR + MTLRxQDR + Rx queue debug register + 0xD38 + 0x20 + read-only + 0x00000000 + + + RWCSTS + RWCSTS + 0 + 1 + + + RRCSTS + RRCSTS + 1 + 2 + + + RXQSTS + RXQSTS + 4 + 2 + + + PRXQ + PRXQ + 16 + 14 + + + + + MACCR + MACCR + Operating mode configuration + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RE + Receiver Enable + 0 + 1 + + + TE + TE + 1 + 1 + + + PRELEN + PRELEN + 2 + 2 + + + DC + DC + 4 + 1 + + + BL + BL + 5 + 2 + + + DR + DR + 8 + 1 + + + DCRS + DCRS + 9 + 1 + + + DO + DO + 10 + 1 + + + ECRSFD + ECRSFD + 11 + 1 + + + LM + LM + 12 + 1 + + + DM + DM + 13 + 1 + + + FES + FES + 14 + 1 + + + JE + JE + 16 + 1 + + + JD + JD + 17 + 1 + + + WD + WD + 19 + 1 + + + ACS + ACS + 20 + 1 + + + CST + CST + 21 + 1 + + + S2KP + S2KP + 22 + 1 + + + GPSLCE + GPSLCE + 23 + 1 + + + IPG + IPG + 24 + 3 + + + IPC + IPC + 27 + 1 + + + SARC + SARC + 28 + 3 + + + ARPEN + ARPEN + 31 + 1 + + + + + MACECR + MACECR + Extended operating mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + GPSL + GPSL + 0 + 14 + + + DCRCC + DCRCC + 16 + 1 + + + SPEN + SPEN + 17 + 1 + + + USP + USP + 18 + 1 + + + EIPGEN + EIPGEN + 24 + 1 + + + EIPG + EIPG + 25 + 5 + + + + + MACPFR + MACPFR + Packet filtering control + register + 0x8 + 0x20 + read-write + 0x00000000 + + + PR + PR + 0 + 1 + + + HUC + HUC + 1 + 1 + + + HMC + HMC + 2 + 1 + + + DAIF + DAIF + 3 + 1 + + + PM + PM + 4 + 1 + + + DBF + DBF + 5 + 1 + + + PCF + PCF + 6 + 2 + + + SAIF + SAIF + 8 + 1 + + + SAF + SAF + 9 + 1 + + + HPF + HPF + 10 + 1 + + + VTFE + VTFE + 16 + 1 + + + IPFE + IPFE + 20 + 1 + + + DNTU + DNTU + 21 + 1 + + + RA + RA + 31 + 1 + + + + + MACWTR + MACWTR + Watchdog timeout register + 0xC + 0x20 + read-write + 0x00000000 + + + WTO + WTO + 0 + 4 + + + PWE + PWE + 8 + 1 + + + + + MACHT0R + MACHT0R + Hash Table 0 register + 0x10 + 0x20 + read-write + 0x00000000 + + + HT31T0 + HT31T0 + 0 + 32 + + + + + MACHT1R + MACHT1R + Hash Table 1 register + 0x14 + 0x20 + read-write + 0x00000000 + + + HT63T32 + HT63T32 + 0 + 32 + + + + + MACVTR + MACVTR + VLAN tag register + 0x50 + 0x20 + read-write + 0x00000000 + + + VL + VL + 0 + 16 + + + ETV + ETV + 16 + 1 + + + VTIM + VTIM + 17 + 1 + + + ESVL + ESVL + 18 + 1 + + + ERSVLM + ERSVLM + 19 + 1 + + + DOVLTC + DOVLTC + 20 + 1 + + + EVLS + EVLS + 21 + 2 + + + EVLRXS + EVLRXS + 24 + 1 + + + VTHM + VTHM + 25 + 1 + + + EDVLP + EDVLP + 26 + 1 + + + ERIVLT + ERIVLT + 27 + 1 + + + EIVLS + EIVLS + 28 + 2 + + + EIVLRXS + EIVLRXS + 31 + 1 + + + + + MACVHTR + MACVHTR + VLAN Hash table register + 0x58 + 0x20 + read-write + 0x00000000 + + + VLHT + VLHT + 0 + 16 + + + + + MACVIR + MACVIR + VLAN inclusion register + 0x60 + 0x20 + read-write + 0x00000000 + + + VLT + VLT + 0 + 16 + + + VLC + VLC + 16 + 2 + + + VLP + VLP + 18 + 1 + + + CSVL + CSVL + 19 + 1 + + + VLTI + VLTI + 20 + 1 + + + + + MACIVIR + MACIVIR + Inner VLAN inclusion register + 0x64 + 0x20 + read-write + 0x00000000 + + + VLT + VLT + 0 + 16 + + + VLC + VLC + 16 + 2 + + + VLP + VLP + 18 + 1 + + + CSVL + CSVL + 19 + 1 + + + VLTI + VLTI + 20 + 1 + + + + + MACQTxFCR + MACQTxFCR + Tx Queue flow control register + 0x70 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + FCB_BPA + 0 + 1 + + + TFE + TFE + 1 + 1 + + + PLT + PLT + 4 + 3 + + + DZPQ + DZPQ + 7 + 1 + + + PT + PT + 16 + 16 + + + + + MACRxFCR + MACRxFCR + Rx flow control register + 0x90 + 0x20 + read-write + 0x00000000 + + + RFE + RFE + 0 + 1 + + + UP + UP + 1 + 1 + + + + + MACISR + MACISR + Interrupt status register + 0xB0 + 0x20 + read-only + 0x00000000 + + + PHYIS + PHYIS + 3 + 1 + + + PMTIS + PMTIS + 4 + 1 + + + LPIIS + LPIIS + 5 + 1 + + + MMCIS + MMCIS + 8 + 1 + + + MMCRXIS + MMCRXIS + 9 + 1 + + + MMCTXIS + MMCTXIS + 10 + 1 + + + TSIS + TSIS + 12 + 1 + + + TXSTSIS + TXSTSIS + 13 + 1 + + + RXSTSIS + RXSTSIS + 14 + 1 + + + + + MACIER + MACIER + Interrupt enable register + 0xB4 + 0x20 + read-write + 0x00000000 + + + PHYIE + PHYIE + 3 + 1 + + + PMTIE + PMTIE + 4 + 1 + + + LPIIE + LPIIE + 5 + 1 + + + TSIE + TSIE + 12 + 1 + + + TXSTSIE + TXSTSIE + 13 + 1 + + + RXSTSIE + RXSTSIE + 14 + 1 + + + + + MACRxTxSR + MACRxTxSR + Rx Tx status register + 0xB8 + 0x20 + read-only + 0x00000000 + + + TJT + TJT + 0 + 1 + + + NCARR + NCARR + 1 + 1 + + + LCARR + LCARR + 2 + 1 + + + EXDEF + EXDEF + 3 + 1 + + + LCOL + LCOL + 4 + 1 + + + EXCOL + LCOL + 5 + 1 + + + RWT + RWT + 8 + 1 + + + + + MACPCSR + MACPCSR + PMT control status register + 0xC0 + 0x20 + 0x00000000 + + + PWRDWN + PWRDWN + 0 + 1 + read-write + + + MGKPKTEN + MGKPKTEN + 1 + 1 + read-write + + + RWKPKTEN + RWKPKTEN + 2 + 1 + read-write + + + MGKPRCVD + MGKPRCVD + 5 + 1 + read-only + + + RWKPRCVD + RWKPRCVD + 6 + 1 + read-only + + + GLBLUCAST + GLBLUCAST + 9 + 1 + read-write + + + RWKPFE + RWKPFE + 10 + 1 + read-write + + + RWKPTR + RWKPTR + 24 + 5 + read-write + + + RWKFILTRST + RWKFILTRST + 31 + 1 + read-write + + + + + MACRWKPFR + MACRWKPFR + Remove wakeup packet filter + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + WKUPFRMFTR + WKUPFRMFTR + 0 + 32 + + + + + MACLCSR + MACLCSR + LPI control status register + 0xD0 + 0x20 + 0x00000000 + + + TLPIEN + TLPIEN + 0 + 1 + read-only + + + TLPIEX + TLPIEX + 1 + 1 + read-only + + + RLPIEN + RLPIEN + 2 + 1 + read-only + + + RLPIEX + RLPIEX + 3 + 1 + read-only + + + TLPIST + TLPIST + 8 + 1 + read-only + + + RLPIST + RLPIST + 9 + 1 + read-only + + + LPIEN + LPIEN + 16 + 1 + read-write + + + PLS + PLS + 17 + 1 + read-write + + + PLSEN + PLSEN + 18 + 1 + read-write + + + LPITXA + LPITXA + 19 + 1 + read-write + + + LPITE + LPITE + 20 + 1 + read-write + + + LPITCSE + LPITCSE + 21 + 1 + read-write + + + + + MACLTCR + MACLTCR + LPI timers control register + 0xD4 + 0x20 + read-write + 0x03E80000 + + + TWT + TWT + 0 + 16 + + + LST + LST + 16 + 10 + + + + + MACLETR + MACLETR + LPI entry timer register + 0xD8 + 0x20 + read-write + 0x00000000 + + + LPIET + LPIET + 0 + 17 + + + + + MAC1USTCR + MAC1USTCR + 1-microsecond-tick counter + register + 0xDC + 0x20 + read-write + 0x00000000 + + + TIC_1US_CNTR + TIC_1US_CNTR + 0 + 12 + + + + + MACVR + MACVR + Version register + 0x110 + 0x20 + read-only + 0x00003041 + + + SNPSVER + SNPSVER + 0 + 8 + + + USERVER + USERVER + 8 + 8 + + + + + MACHWF1R + MACHWF1R + HW feature 1 register + 0x120 + 0x20 + read-only + 0x11841904 + + + RXFIFOSIZE + RXFIFOSIZE + 0 + 5 + + + TXFIFOSIZE + TXFIFOSIZE + 6 + 5 + + + OSTEN + OSTEN + 11 + 1 + + + PTOEN + PTOEN + 12 + 1 + + + ADVTHWORD + ADVTHWORD + 13 + 1 + + + DCBEN + DCBEN + 16 + 1 + + + SPHEN + SPHEN + 17 + 1 + + + TSOEN + TSOEN + 18 + 1 + + + DBGMEMA + DBGMEMA + 19 + 1 + + + AVSEL + AVSEL + 20 + 1 + + + HASHTBLSZ + HASHTBLSZ + 24 + 2 + + + L3L4FNUM + L3L4FNUM + 27 + 4 + + + + + MACHWF2R + MACHWF2R + HW feature 2 register + 0x124 + 0x20 + read-only + 0x41000000 + + + RXQCNT + RXQCNT + 0 + 4 + + + TXQCNT + TXQCNT + 6 + 4 + + + RXCHCNT + RXCHCNT + 12 + 4 + + + TXCHCNT + TXCHCNT + 18 + 4 + + + PPSOUTNUM + PPSOUTNUM + 24 + 3 + + + AUXSNAPNUM + AUXSNAPNUM + 28 + 3 + + + + + MACMDIOAR + MACMDIOAR + MDIO address register + 0x200 + 0x20 + read-write + 0x00000000 + + + MB + MB + 0 + 1 + + + C45E + C45E + 1 + 1 + + + GOC + GOC + 2 + 2 + + + SKAP + SKAP + 4 + 1 + + + CR + CR + 8 + 4 + + + NTC + NTC + 12 + 3 + + + RDA + RDA + 16 + 5 + + + PA + PA + 21 + 5 + + + BTB + BTB + 26 + 1 + + + PSE + PSE + 27 + 1 + + + + + MACMDIODR + MACMDIODR + MDIO data register + 0x204 + 0x20 + read-write + 0x00000000 + + + MD + MD + 0 + 16 + + + RA + RA + 16 + 16 + + + + + MACARPAR + MACARPAR + ARP address register + 0xAE0 + 0x20 + read-write + 0x00000000 + + + ARPPA + ARPPA + 0 + 32 + + + + + MACA0HR + MACA0HR + Address 0 high register + 0x300 + 0x20 + 0x8000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + read-write + + + AE + AE + 31 + 1 + read-only + + + + + MACA0LR + MACA0LR + Address 0 low register + 0x304 + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA1LR + MACA1LR + Address 1 low register + 0x30C + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA2LR + MACA2LR + Address 2 low register + 0x314 + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA3LR + MACA3LR + Address 3 low register + 0x31C + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + + + + + MACA1HR + MACA1HR + Address 1 high register + 0x308 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA2HR + MACA2HR + Address 2 high register + 0x310 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA3HR + MACA3HR + Address 3 high register + 0x318 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MMC_CONTROL + MMC_CONTROL + MMC control register + 0x700 + 0x20 + read-write + 0x00000000 + + + CNTRST + CNTRST + 0 + 1 + + + CNTSTOPRO + CNTSTOPRO + 1 + 1 + + + RSTONRD + RSTONRD + 2 + 1 + + + CNTFREEZ + CNTFREEZ + 3 + 1 + + + CNTPRST + CNTPRST + 4 + 1 + + + CNTPRSTLVL + CNTPRSTLVL + 5 + 1 + + + UCDBC + UCDBC + 8 + 1 + + + + + MMC_RX_INTERRUPT + MMC_RX_INTERRUPT + MMC Rx interrupt register + 0x704 + 0x20 + read-only + 0x00000000 + + + RXCRCERPIS + RXCRCERPIS + 5 + 1 + + + RXALGNERPIS + RXALGNERPIS + 6 + 1 + + + RXUCGPIS + RXUCGPIS + 17 + 1 + + + RXLPIUSCIS + RXLPIUSCIS + 26 + 1 + + + RXLPITRCIS + RXLPITRCIS + 27 + 1 + + + + + MMC_TX_INTERRUPT + MMC_TX_INTERRUPT + MMC Tx interrupt register + 0x708 + 0x20 + read-only + 0x00000000 + + + TXSCOLGPIS + TXSCOLGPIS + 14 + 1 + + + TXMCOLGPIS + TXMCOLGPIS + 15 + 1 + + + TXGPKTIS + TXGPKTIS + 21 + 1 + + + TXLPIUSCIS + TXLPIUSCIS + 26 + 1 + + + TXLPITRCIS + TXLPITRCIS + 27 + 1 + + + + + MMC_RX_INTERRUPT_MASK + MMC_RX_INTERRUPT_MASK + MMC Rx interrupt mask register + 0x70C + 0x20 + 0x00000000 + + + RXCRCERPIM + RXCRCERPIM + 5 + 1 + read-write + + + RXALGNERPIM + RXALGNERPIM + 6 + 1 + read-write + + + RXUCGPIM + RXUCGPIM + 17 + 1 + read-write + + + RXLPIUSCIM + RXLPIUSCIM + 26 + 1 + read-write + + + RXLPITRCIM + RXLPITRCIM + 27 + 1 + read-only + + + + + MMC_TX_INTERRUPT_MASK + MMC_TX_INTERRUPT_MASK + MMC Tx interrupt mask register + 0x710 + 0x20 + 0x00000000 + + + TXSCOLGPIM + TXSCOLGPIM + 14 + 1 + read-write + + + TXMCOLGPIM + TXMCOLGPIM + 15 + 1 + read-write + + + TXGPKTIM + TXGPKTIM + 21 + 1 + read-write + + + TXLPIUSCIM + TXLPIUSCIM + 26 + 1 + read-write + + + TXLPITRCIM + TXLPITRCIM + 27 + 1 + read-only + + + + + TX_SINGLE_COLLISION_GOOD_PACKETS + + TX_SINGLE_COLLISION_GOOD_PACKETS + Tx single collision good packets + register + 0x74C + 0x20 + read-only + 0x00000000 + + + TXSNGLCOLG + TXSNGLCOLG + 0 + 32 + + + + + TX_MULTIPLE_COLLISION_GOOD_PACKETS + + TX_MULTIPLE_COLLISION_GOOD_PACKETS + Tx multiple collision good packets + register + 0x750 + 0x20 + read-only + 0x00000000 + + + TXMULTCOLG + TXMULTCOLG + 0 + 32 + + + + + TX_PACKET_COUNT_GOOD + TX_PACKET_COUNT_GOOD + Tx packet count good register + 0x768 + 0x20 + read-only + 0x00000000 + + + TXPKTG + TXPKTG + 0 + 32 + + + + + RX_CRC_ERROR_PACKETS + RX_CRC_ERROR_PACKETS + Rx CRC error packets register + 0x794 + 0x20 + read-only + 0x00000000 + + + RXCRCERR + RXCRCERR + 0 + 32 + + + + + RX_ALIGNMENT_ERROR_PACKETS + RX_ALIGNMENT_ERROR_PACKETS + Rx alignment error packets + register + 0x798 + 0x20 + read-only + 0x00000000 + + + RXALGNERR + RXALGNERR + 0 + 32 + + + + + RX_UNICAST_PACKETS_GOOD + RX_UNICAST_PACKETS_GOOD + Rx unicast packets good + register + 0x7C4 + 0x20 + read-only + 0x00000000 + + + RXUCASTG + RXUCASTG + 0 + 32 + + + + + TX_LPI_USEC_CNTR + TX_LPI_USEC_CNTR + Tx LPI microsecond timer + register + 0x7EC + 0x20 + read-only + 0x00000000 + + + TXLPIUSC + TXLPIUSC + 0 + 32 + + + + + TX_LPI_TRAN_CNTR + TX_LPI_TRAN_CNTR + Tx LPI transition counter + register + 0x7F0 + 0x20 + read-only + 0x00000000 + + + TXLPITRC + TXLPITRC + 0 + 32 + + + + + RX_LPI_USEC_CNTR + RX_LPI_USEC_CNTR + Rx LPI microsecond counter + register + 0x7F4 + 0x20 + read-only + 0x00000000 + + + RXLPIUSC + RXLPIUSC + 0 + 32 + + + + + RX_LPI_TRAN_CNTR + RX_LPI_TRAN_CNTR + Rx LPI transition counter + register + 0x7F8 + 0x20 + read-only + 0x00000000 + + + RXLPITRC + RXLPITRC + 0 + 32 + + + + + MACL3L4C0R + MACL3L4C0R + L3 and L4 control 0 register + 0x900 + 0x20 + read-write + 0x00000000 + + + L3PEN0 + L3PEN0 + 0 + 1 + + + L3SAM0 + L3SAM0 + 2 + 1 + + + L3SAIM0 + L3SAIM0 + 3 + 1 + + + L3DAM0 + L3DAM0 + 4 + 1 + + + L3DAIM0 + L3DAIM0 + 5 + 1 + + + L3HSBM0 + L3HSBM0 + 6 + 5 + + + L3HDBM0 + L3HDBM0 + 11 + 5 + + + L4PEN0 + L4PEN0 + 16 + 1 + + + L4SPM0 + L4SPM0 + 18 + 1 + + + L4SPIM0 + L4SPIM0 + 19 + 1 + + + L4DPM0 + L4DPM0 + 20 + 1 + + + L4DPIM0 + L4DPIM0 + 21 + 1 + + + + + MACL4A0R + MACL4A0R + Layer4 address filter 0 + register + 0x904 + 0x20 + read-write + 0x00000000 + + + L4SP0 + L4SP0 + 0 + 16 + + + L4DP0 + L4DP0 + 16 + 16 + + + + + MACDR + MACDR + Debug register + 0x114 + 0x20 + read-only + 0x00000000 + + + RPESTS + RPESTS + 0 + 1 + + + RFCFCSTS + RFCFCSTS + 1 + 2 + + + TPESTS + TPESTS + 16 + 1 + + + TFCSTS + TFCSTS + 17 + 2 + + + + + MACL3A00R + MACL3A00R + MACL3A00R + 0x910 + 0x20 + read-write + 0x00000000 + + + L3A00 + L3A00 + 0 + 32 + + + + + MACL3A10R + MACL3A10R + Layer3 address 1 filter 0 + register + 0x914 + 0x20 + read-write + 0x00000000 + + + L3A10 + L3A10 + 0 + 32 + + + + + MACL3A20 + MACL3A20 + Layer3 Address 2 filter 0 + register + 0x918 + 0x20 + read-write + 0x00000000 + + + L3A20 + L3A20 + 0 + 32 + + + + + MACL3A30 + MACL3A30 + Layer3 Address 3 filter 0 + register + 0x91C + 0x20 + read-write + 0x00000000 + + + L3A30 + L3A30 + 0 + 32 + + + + + MACL3L4C1R + MACL3L4C1R + L3 and L4 control 1 register + 0x930 + 0x20 + read-write + 0x00000000 + + + L3PEN1 + L3PEN1 + 0 + 1 + + + L3SAM1 + L3SAM1 + 2 + 1 + + + L3SAIM1 + L3SAIM1 + 3 + 1 + + + L3DAM1 + L3DAM1 + 4 + 1 + + + L3DAIM1 + L3DAIM1 + 5 + 1 + + + L3HSBM1 + L3HSBM1 + 6 + 5 + + + L3HDBM1 + L3HDBM1 + 11 + 5 + + + L4PEN1 + L4PEN1 + 16 + 1 + + + L4SPM1 + L4SPM1 + 18 + 1 + + + L4SPIM1 + L4SPIM1 + 19 + 1 + + + L4DPM1 + L4DPM1 + 20 + 1 + + + L4DPIM1 + L4DPIM1 + 21 + 1 + + + + + MACL4A1R + MACL4A1R + Layer 4 address filter 1 + register + 0x934 + 0x20 + read-write + 0x00000000 + + + L4SP1 + L4SP1 + 0 + 16 + + + L4DP1 + L4DP1 + 16 + 16 + + + + + MACL3A01R + MACL3A01R + Layer3 address 0 filter 1 + Register + 0x940 + 0x20 + read-write + 0x00000000 + + + L3A01 + L3A01 + 0 + 32 + + + + + MACL3A11R + MACL3A11R + Layer3 address 1 filter 1 + register + 0x944 + 0x20 + read-write + 0x00000000 + + + L3A11 + L3A11 + 0 + 32 + + + + + MACL3A21R + MACL3A21R + Layer3 address 2 filter 1 + Register + 0x948 + 0x20 + read-write + 0x00000000 + + + L3A21 + L3A21 + 0 + 32 + + + + + MACL3A31R + MACL3A31R + Layer3 address 3 filter 1 + register + 0x94C + 0x20 + read-write + 0x00000000 + + + L3A31 + L3A31 + 0 + 32 + + + + + MACTSCR + MACTSCR + Timestamp control Register + 0xB00 + 0x20 + 0x00000200 + + + TSENA + TSENA + 0 + 1 + read-write + + + TSCFUPDT + TSCFUPDT + 1 + 1 + read-write + + + TSINIT + TSINIT + 2 + 1 + read-write + + + TSUPDT + TSUPDT + 3 + 1 + read-write + + + TSADDREG + TSADDREG + 5 + 1 + read-write + + + TSENALL + TSENALL + 8 + 1 + read-write + + + TSCTRLSSR + TSCTRLSSR + 9 + 1 + read-write + + + TSVER2ENA + TSVER2ENA + 10 + 1 + read-write + + + TSIPENA + TSIPENA + 11 + 1 + read-write + + + TSIPV6ENA + TSIPV6ENA + 12 + 1 + read-write + + + TSIPV4ENA + TSIPV4ENA + 13 + 1 + read-write + + + TSEVNTENA + TSEVNTENA + 14 + 1 + read-write + + + TSMSTRENA + TSMSTRENA + 15 + 1 + read-write + + + SNAPTYPSEL + SNAPTYPSEL + 16 + 2 + read-write + + + TSENMACADDR + TSENMACADDR + 18 + 1 + read-write + + + CSC + CSC + 19 + 1 + read-only + + + TXTSSTSM + TXTSSTSM + 24 + 1 + read-write + + + + + MACSSIR + MACSSIR + Sub-second increment register + 0xB04 + 0x20 + read-write + 0x00000000 + + + SNSINC + SNSINC + 8 + 8 + + + SSINC + SSINC + 16 + 8 + + + + + MACSTSR + MACSTSR + System time seconds register + 0xB08 + 0x20 + read-only + 0x00000000 + + + TSS + TSS + 0 + 32 + + + + + MACSTNR + MACSTNR + System time nanoseconds + register + 0xB0C + 0x20 + read-only + 0x00000000 + + + TSSS + TSSS + 0 + 31 + + + + + MACSTSUR + MACSTSUR + System time seconds update + register + 0xB10 + 0x20 + read-write + 0x00000000 + + + TSS + TSS + 0 + 32 + + + + + MACSTNUR + MACSTNUR + System time nanoseconds update + register + 0xB14 + 0x20 + read-write + 0x00000000 + + + TSSS + TSSS + 0 + 31 + + + ADDSUB + ADDSUB + 31 + 1 + + + + + MACTSAR + MACTSAR + Timestamp addend register + 0xB18 + 0x20 + read-write + 0x00000000 + + + TSAR + TSAR + 0 + 32 + + + + + MACTSSR + MACTSSR + Timestamp status register + 0xB20 + 0x20 + read-only + 0x00000000 + + + TSSOVF + TSSOVF + 0 + 1 + + + TSTARGT0 + TSTARGT0 + 1 + 1 + + + AUXTSTRIG + AUXTSTRIG + 2 + 1 + + + TSTRGTERR0 + TSTRGTERR0 + 3 + 1 + + + TXTSSIS + TXTSSIS + 15 + 1 + + + ATSSTN + ATSSTN + 16 + 4 + + + ATSSTM + ATSSTM + 24 + 1 + + + ATSNS + ATSNS + 25 + 5 + + + + + MACTxTSSNR + MACTxTSSNR + Tx timestamp status nanoseconds + register + 0xB30 + 0x20 + read-only + 0x00000000 + + + TXTSSLO + TXTSSLO + 0 + 31 + + + TXTSSMIS + TXTSSMIS + 31 + 1 + + + + + MACTxTSSSR + MACTxTSSSR + Tx timestamp status seconds + register + 0xB34 + 0x20 + read-only + 0x00000000 + + + TXTSSHI + TXTSSHI + 0 + 32 + + + + + MACACR + MACACR + Auxiliary control register + 0xB40 + 0x20 + read-write + 0x00000000 + + + ATSFC + ATSFC + 0 + 1 + + + ATSEN0 + ATSEN0 + 4 + 1 + + + ATSEN1 + ATSEN1 + 5 + 1 + + + ATSEN2 + ATSEN2 + 6 + 1 + + + ATSEN3 + ATSEN3 + 7 + 1 + + + + + MACATSNR + MACATSNR + Auxiliary timestamp nanoseconds + register + 0xB48 + 0x20 + read-only + 0x00000000 + + + AUXTSLO + AUXTSLO + 0 + 31 + + + + + MACATSSR + MACATSSR + Auxiliary timestamp seconds + register + 0xB4C + 0x20 + read-only + 0x00000000 + + + AUXTSHI + AUXTSHI + 0 + 32 + + + + + MACTSIACR + MACTSIACR + Timestamp Ingress asymmetric correction + register + 0xB50 + 0x20 + read-write + 0x00000000 + + + OSTIAC + OSTIAC + 0 + 32 + + + + + MACTSEACR + MACTSEACR + Timestamp Egress asymmetric correction + register + 0xB54 + 0x20 + read-write + 0x00000000 + + + OSTEAC + OSTEAC + 0 + 32 + + + + + MACTSICNR + MACTSICNR + Timestamp Ingress correction nanosecond + register + 0xB58 + 0x20 + read-write + 0x00000000 + + + TSIC + TSIC + 0 + 32 + + + + + MACTSECNR + MACTSECNR + Timestamp Egress correction nanosecond + register + 0xB5C + 0x20 + read-write + 0x00000000 + + + TSEC + TSEC + 0 + 32 + + + + + MACPPSCR + MACPPSCR + PPS control register + 0xB70 + 0x20 + read-write + 0x00000000 + + + PPSCTRL + PPSCTRL + 0 + 4 + + + PPSEN0 + PPSEN0 + 4 + 1 + + + TRGTMODSEL0 + TRGTMODSEL0 + 5 + 2 + + + + + MACPPSTTSR + MACPPSTTSR + PPS target time seconds + register + 0xB80 + 0x20 + read-write + 0x00000000 + + + TSTRH0 + TSTRH0 + 0 + 31 + + + + + MACPPSTTNR + MACPPSTTNR + PPS target time nanoseconds + register + 0xB84 + 0x20 + read-write + 0x00000000 + + + TTSL0 + TTSL0 + 0 + 31 + + + TRGTBUSY0 + TRGTBUSY0 + 31 + 1 + + + + + MACPPSIR + MACPPSIR + PPS interval register + 0xB88 + 0x20 + read-write + 0x00000000 + + + PPSINT0 + PPSINT0 + 0 + 32 + + + + + MACPPSWR + MACPPSWR + PPS width register + 0xB8C + 0x20 + read-write + 0x00000000 + + + PPSWIDTH0 + PPSWIDTH0 + 0 + 32 + + + + + MACPOCR + MACPOCR + PTP Offload control register + 0xBC0 + 0x20 + read-write + 0x00000000 + + + PTOEN + PTOEN + 0 + 1 + + + ASYNCEN + ASYNCEN + 1 + 1 + + + APDREQEN + APDREQEN + 2 + 1 + + + ASYNCTRIG + ASYNCTRIG + 4 + 1 + + + APDREQTRIG + APDREQTRIG + 5 + 1 + + + DRRDIS + DRRDIS + 6 + 1 + + + DN + DN + 8 + 8 + + + + + MACSPI0R + MACSPI0R + PTP Source Port Identity 0 + Register + 0xBC4 + 0x20 + read-write + 0x00000000 + + + SPI0 + SPI0 + 0 + 32 + + + + + MACSPI1R + MACSPI1R + PTP Source port identity 1 + register + 0xBC8 + 0x20 + read-write + 0x00000000 + + + SPI1 + SPI1 + 0 + 32 + + + + + MACSPI2R + MACSPI2R + PTP Source port identity 2 + register + 0xBCC + 0x20 + read-write + 0x00000000 + + + SPI2 + SPI2 + 0 + 16 + + + + + MACLMIR + MACLMIR + Log message interval register + 0xBD0 + 0x20 + read-write + 0x00000000 + + + LSI + LSI + 0 + 8 + + + DRSYNCR + DRSYNCR + 8 + 3 + + + LMPDRI + LMPDRI + 24 + 8 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA_STR0 + DMA1 Stream0 + 11 + + + DMA_STR1 + DMA1 Stream1 + 12 + + + DMA_STR2 + DMA1 Stream2 + 13 + + + DMA_STR3 + DMA1 Stream3 + 14 + + + DMA_STR4 + DMA1 Stream4 + 15 + + + DMA_STR5 + DMA1 Stream5 + 16 + + + DMA_STR6 + DMA1 Stream6 + 17 + + + DMA1_STR7 + DMA1 Stream7 + 47 + + + + LISR + LISR + low interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TCIF3 + Stream x transfer complete interrupt + flag (x = 3..0) + 27 + 1 + + + HTIF3 + Stream x half transfer interrupt flag + (x=3..0) + 26 + 1 + + + TEIF3 + Stream x transfer error interrupt flag + (x=3..0) + 25 + 1 + + + DMEIF3 + Stream x direct mode error interrupt + flag (x=3..0) + 24 + 1 + + + FEIF3 + Stream x FIFO error interrupt flag + (x=3..0) + 22 + 1 + + + TCIF2 + Stream x transfer complete interrupt + flag (x = 3..0) + 21 + 1 + + + HTIF2 + Stream x half transfer interrupt flag + (x=3..0) + 20 + 1 + + + TEIF2 + Stream x transfer error interrupt flag + (x=3..0) + 19 + 1 + + + DMEIF2 + Stream x direct mode error interrupt + flag (x=3..0) + 18 + 1 + + + FEIF2 + Stream x FIFO error interrupt flag + (x=3..0) + 16 + 1 + + + TCIF1 + Stream x transfer complete interrupt + flag (x = 3..0) + 11 + 1 + + + HTIF1 + Stream x half transfer interrupt flag + (x=3..0) + 10 + 1 + + + TEIF1 + Stream x transfer error interrupt flag + (x=3..0) + 9 + 1 + + + DMEIF1 + Stream x direct mode error interrupt + flag (x=3..0) + 8 + 1 + + + FEIF1 + Stream x FIFO error interrupt flag + (x=3..0) + 6 + 1 + + + TCIF0 + Stream x transfer complete interrupt + flag (x = 3..0) + 5 + 1 + + + HTIF0 + Stream x half transfer interrupt flag + (x=3..0) + 4 + 1 + + + TEIF0 + Stream x transfer error interrupt flag + (x=3..0) + 3 + 1 + + + DMEIF0 + Stream x direct mode error interrupt + flag (x=3..0) + 2 + 1 + + + FEIF0 + Stream x FIFO error interrupt flag + (x=3..0) + 0 + 1 + + + + + HISR + HISR + high interrupt status register + 0x4 + 0x20 + read-only + 0x00000000 + + + TCIF7 + Stream x transfer complete interrupt + flag (x=7..4) + 27 + 1 + + + HTIF7 + Stream x half transfer interrupt flag + (x=7..4) + 26 + 1 + + + TEIF7 + Stream x transfer error interrupt flag + (x=7..4) + 25 + 1 + + + DMEIF7 + Stream x direct mode error interrupt + flag (x=7..4) + 24 + 1 + + + FEIF7 + Stream x FIFO error interrupt flag + (x=7..4) + 22 + 1 + + + TCIF6 + Stream x transfer complete interrupt + flag (x=7..4) + 21 + 1 + + + HTIF6 + Stream x half transfer interrupt flag + (x=7..4) + 20 + 1 + + + TEIF6 + Stream x transfer error interrupt flag + (x=7..4) + 19 + 1 + + + DMEIF6 + Stream x direct mode error interrupt + flag (x=7..4) + 18 + 1 + + + FEIF6 + Stream x FIFO error interrupt flag + (x=7..4) + 16 + 1 + + + TCIF5 + Stream x transfer complete interrupt + flag (x=7..4) + 11 + 1 + + + HTIF5 + Stream x half transfer interrupt flag + (x=7..4) + 10 + 1 + + + TEIF5 + Stream x transfer error interrupt flag + (x=7..4) + 9 + 1 + + + DMEIF5 + Stream x direct mode error interrupt + flag (x=7..4) + 8 + 1 + + + FEIF5 + Stream x FIFO error interrupt flag + (x=7..4) + 6 + 1 + + + TCIF4 + Stream x transfer complete interrupt + flag (x=7..4) + 5 + 1 + + + HTIF4 + Stream x half transfer interrupt flag + (x=7..4) + 4 + 1 + + + TEIF4 + Stream x transfer error interrupt flag + (x=7..4) + 3 + 1 + + + DMEIF4 + Stream x direct mode error interrupt + flag (x=7..4) + 2 + 1 + + + FEIF4 + Stream x FIFO error interrupt flag + (x=7..4) + 0 + 1 + + + + + LIFCR + LIFCR + low interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTCIF3 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 27 + 1 + + + CHTIF3 + Stream x clear half transfer interrupt + flag (x = 3..0) + 26 + 1 + + + CTEIF3 + Stream x clear transfer error interrupt + flag (x = 3..0) + 25 + 1 + + + CDMEIF3 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 24 + 1 + + + CFEIF3 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 22 + 1 + + + CTCIF2 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 21 + 1 + + + CHTIF2 + Stream x clear half transfer interrupt + flag (x = 3..0) + 20 + 1 + + + CTEIF2 + Stream x clear transfer error interrupt + flag (x = 3..0) + 19 + 1 + + + CDMEIF2 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 18 + 1 + + + CFEIF2 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 16 + 1 + + + CTCIF1 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 11 + 1 + + + CHTIF1 + Stream x clear half transfer interrupt + flag (x = 3..0) + 10 + 1 + + + CTEIF1 + Stream x clear transfer error interrupt + flag (x = 3..0) + 9 + 1 + + + CDMEIF1 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 8 + 1 + + + CFEIF1 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 6 + 1 + + + CTCIF0 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 5 + 1 + + + CHTIF0 + Stream x clear half transfer interrupt + flag (x = 3..0) + 4 + 1 + + + CTEIF0 + Stream x clear transfer error interrupt + flag (x = 3..0) + 3 + 1 + + + CDMEIF0 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 2 + 1 + + + CFEIF0 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 0 + 1 + + + + + HIFCR + HIFCR + high interrupt flag clear + register + 0xC + 0x20 + read-write + 0x00000000 + + + CTCIF7 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 27 + 1 + + + CHTIF7 + Stream x clear half transfer interrupt + flag (x = 7..4) + 26 + 1 + + + CTEIF7 + Stream x clear transfer error interrupt + flag (x = 7..4) + 25 + 1 + + + CDMEIF7 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 24 + 1 + + + CFEIF7 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 22 + 1 + + + CTCIF6 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 21 + 1 + + + CHTIF6 + Stream x clear half transfer interrupt + flag (x = 7..4) + 20 + 1 + + + CTEIF6 + Stream x clear transfer error interrupt + flag (x = 7..4) + 19 + 1 + + + CDMEIF6 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 18 + 1 + + + CFEIF6 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 16 + 1 + + + CTCIF5 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 11 + 1 + + + CHTIF5 + Stream x clear half transfer interrupt + flag (x = 7..4) + 10 + 1 + + + CTEIF5 + Stream x clear transfer error interrupt + flag (x = 7..4) + 9 + 1 + + + CDMEIF5 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 8 + 1 + + + CFEIF5 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 6 + 1 + + + CTCIF4 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 5 + 1 + + + CHTIF4 + Stream x clear half transfer interrupt + flag (x = 7..4) + 4 + 1 + + + CTEIF4 + Stream x clear transfer error interrupt + flag (x = 7..4) + 3 + 1 + + + CDMEIF4 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 2 + 1 + + + CFEIF4 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 0 + 1 + + + + + S0CR + S0CR + stream x configuration + register + 0x10 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S0NDTR + S0NDTR + stream x number of data + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S0PAR + S0PAR + stream x peripheral address + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S0M0AR + S0M0AR + stream x memory 0 address + register + 0x1C + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S0M1AR + S0M1AR + stream x memory 1 address + register + 0x20 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S0FCR + S0FCR + stream x FIFO control register + 0x24 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S1CR + S1CR + stream x configuration + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + 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0 + 16 + + + + + CH5DATINR + CH5DATINR + CH5DATINR + 0xB0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH5DLYR + CH5DLYR + channel y delay register + 0xB4 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + CH6CFGR1 + CH6CFGR1 + CH6CFGR1 + 0xC0 + 0x20 + read-write + 0x0 + + + DATPACK + DATPACK + 14 + 2 + + + DATMPX + DATMPX + 12 + 2 + + + CHINSEL + CHINSEL + 8 + 1 + + + CHEN + CHEN + 7 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + SCDEN + SCDEN + 5 + 1 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SITP + SITP + 0 + 2 + + + + + CH6CFGR2 + CH6CFGR2 + CH6CFGR2 + 0xC4 + 0x20 + read-write + 0x0 + + + OFFSET + OFFSET + 8 + 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + CH6AWSCDR + CH6AWSCDR + CH6AWSCDR + 0xC8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CH6WDATR + CH6WDATR + CH6WDATR + 0xCC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CH6DATINR + CH6DATINR + CH6DATINR + 0xD0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH6DLYR + CH6DLYR + channel y delay register + 0xD4 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + CH7CFGR1 + CH7CFGR1 + CH7CFGR1 + 0xE0 + 0x20 + read-write + 0x0 + + + DATPACK + DATPACK + 14 + 2 + + + DATMPX + DATMPX + 12 + 2 + + + CHINSEL + CHINSEL + 8 + 1 + + + CHEN + CHEN + 7 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + SCDEN + SCDEN + 5 + 1 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SITP + SITP + 0 + 2 + + + + + CH7CFGR2 + CH7CFGR2 + CH7CFGR2 + 0xE4 + 0x20 + read-write + 0x0 + + + OFFSET + OFFSET + 8 + 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + CH7AWSCDR + CH7AWSCDR + CH7AWSCDR + 0xE8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CH7WDATR + CH7WDATR + CH7WDATR + 0xEC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CH7DATINR + CH7DATINR + CH7DATINR + 0xF0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CH7DLYR + CH7DLYR + channel y delay register + 0xF4 + 0x20 + read-write + 0x0 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_FLT0CR1 + DFSDM_FLT0CR1 + control register 1 + 0x100 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT0CR2 + DFSDM_FLT0CR2 + control register 2 + 0x104 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT0ISR + DFSDM_FLT0ISR + interrupt and status register + 0x108 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT0ICR + DFSDM_FLT0ICR + interrupt flag clear register + 0x10C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT0JCHGR + DFSDM_FLT0JCHGR + injected channel group selection + register + 0x110 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT0FCR + DFSDM_FLT0FCR + filter control register + 0x114 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT0JDATAR + DFSDM_FLT0JDATAR + data register for injected + group + 0x118 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT0RDATAR + DFSDM_FLT0RDATAR + data register for the regular + channel + 0x11C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT0AWHTR + DFSDM_FLT0AWHTR + analog watchdog high threshold + register + 0x120 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT0AWLTR + DFSDM_FLT0AWLTR + analog watchdog low threshold + register + 0x124 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT0AWSR + DFSDM_FLT0AWSR + analog watchdog status + register + 0x128 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT0AWCFR + DFSDM_FLT0AWCFR + analog watchdog clear flag + register + 0x12C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT0EXMAX + DFSDM_FLT0EXMAX + Extremes detector maximum + register + 0x130 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT0EXMIN + DFSDM_FLT0EXMIN + Extremes detector minimum + register + 0x134 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT0CNVTIMR + DFSDM_FLT0CNVTIMR + conversion timer register + 0x138 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT1CR1 + DFSDM_FLT1CR1 + control register 1 + 0x180 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT1CR2 + DFSDM_FLT1CR2 + control register 2 + 0x184 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT1ISR + DFSDM_FLT1ISR + interrupt and status register + 0x188 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT1ICR + DFSDM1_ICR + interrupt flag clear register + 0x18C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT1CHGR + DFSDM_FLT1JCHGR + injected channel group selection + register + 0x190 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT1FCR + DFSDM1_FCR + filter control register + 0x194 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT1JDATAR + DFSDM_FLT1JDATAR + data register for injected + group + 0x198 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT1RDATAR + DFSDM_FLT1RDATAR + data register for the regular + channel + 0x19C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT1AWHTR + DFSDM_FLT1AWHTR + analog watchdog high threshold + register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT1AWLTR + DFSDM_FLT1AWLTR + analog watchdog low threshold + register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT1AWSR + DFSDM_FLT1AWSR + analog watchdog status + register + 0x1A8 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT1AWCFR + DFSDM_FLT1AWCFR + analog watchdog clear flag + register + 0x1AC + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT1EXMAX + DFSDM_FLT1EXMAX + Extremes detector maximum + register + 0x1B0 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT1EXMIN + DFSDM_FLT1EXMIN + Extremes detector minimum + register + 0x1B4 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT1CNVTIMR + DFSDM_FLT1CNVTIMR + conversion timer register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT2CR1 + DFSDM_FLT2CR1 + control register 1 + 0x200 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT2CR2 + DFSDM_FLT2CR2 + control register 2 + 0x204 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT2ISR + DFSDM_FLT2ISR + interrupt and status register + 0x208 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT2ICR + DFSDM_FLT2ICR + interrupt flag clear register + 0x20C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT2JCHGR + DFSDM_FLT2JCHGR + injected channel group selection + register + 0x210 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT2FCR + DFSDM_FLT2FCR + filter control register + 0x214 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT2JDATAR + DFSDM_FLT2JDATAR + data register for injected + group + 0x218 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT2RDATAR + DFSDM_FLT2RDATAR + data register for the regular + channel + 0x21C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT2AWHTR + DFSDM_FLT2AWHTR + analog watchdog high threshold + register + 0x220 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT2AWLTR + DFSDM_FLT2AWLTR + analog watchdog low threshold + register + 0x224 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT2AWSR + DFSDM_FLT2AWSR + analog watchdog status + register + 0x228 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT2AWCFR + DFSDM_FLT2AWCFR + analog watchdog clear flag + register + 0x22C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT2EXMAX + DFSDM_FLT2EXMAX + Extremes detector maximum + register + 0x230 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT2EXMIN + DFSDM_FLT2EXMIN + Extremes detector minimum + register + 0x234 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT2CNVTIMR + DFSDM_FLT2CNVTIMR + conversion timer register + 0x238 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT3CR1 + DFSDM_FLT3CR1 + control register 1 + 0x280 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT3CR2 + DFSDM_FLT3CR2 + control register 2 + 0x284 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT3ISR + DFSDM_FLT3ISR + interrupt and status register + 0x288 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT3ICR + DFSDM_FLT3ICR + interrupt flag clear register + 0x28C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT3JCHGR + DFSDM_FLT3JCHGR + injected channel group selection + register + 0x290 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM_FLT3FCR + DFSDM_FLT3FCR + filter control register + 0x294 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM_FLT3JDATAR + DFSDM_FLT3JDATAR + data register for injected + group + 0x298 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT3RDATAR + DFSDM_FLT3RDATAR + data register for the regular + channel + 0x29C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM_FLT3AWHTR + DFSDM_FLT3AWHTR + analog watchdog high threshold + register + 0x2A0 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT3AWLTR + DFSDM_FLT3AWLTR + analog watchdog low threshold + register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM_FLT3AWSR + DFSDM_FLT3AWSR + analog watchdog status + register + 0x2A8 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT3AWCFR + DFSDM_FLT3AWCFR + analog watchdog clear flag + register + 0x2AC + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT3EXMAX + DFSDM_FLT3EXMAX + Extremes detector maximum + register + 0x2B0 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM_FLT3EXMIN + DFSDM_FLT3EXMIN + Extremes detector minimum + register + 0x2B4 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM_FLT3CNVTIMR + DFSDM_FLT3CNVTIMR + conversion timer register + 0x2B8 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + + + TIM16 + General-purpose-timers + TIMs + 0x40014400 + + 0x0 + 0x400 + registers + + + TIM16 + TIM16 global interrupt + 117 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + TIM16_AF1 + TIM16_AF1 + TIM16 alternate function register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK1E + BRK dfsdm1_break[1] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + + + TIM16_TISEL + TIM16_TISEL + TIM16 input selection register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + selects TI1[0] to TI1[15] + input + 0 + 4 + + + + + + + TIM17 + General-purpose-timers + TIMs + 0x40014800 + + 0x0 + 0x400 + registers + + + TIM17 + TIM17 global interrupt + 118 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + TIM17_AF1 + TIM17_AF1 + TIM17 alternate function register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK1E + BRK dfsdm1_break[1] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + + + TIM17_TISEL + TIM17_TISEL + TIM17 input selection register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + selects TI1[0] to TI1[15] + input + 0 + 4 + + + + + + + TIM15 + General purpose timers + TIMs + 0x40014000 + + 0x0 + 0x400 + registers + + + TIM15 + TIM15 global interrupt + 116 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + MMS + Master mode selection + 4 + 3 + + + TI1S + TI1 selection + 7 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + TS_2_0 + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + SMS_3 + Slave mode selection bit 3 + 16 + 1 + + + TS_4_3 + Trigger selection - bit + 4:3 + 20 + 2 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC1M_3 + Output Compare 1 mode bit + 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode bit + 3 + 24 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + AF1 + AF1 + TIM15 alternate fdfsdm1_breakon register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDF1BK0E + BRK dfsdm1_break[0] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + + + TISEL + TISEL + TIM15 input selection register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + selects TI1[0] to TI1[15] + input + 0 + 4 + + + TI2SEL + selects TI2[0] to TI2[15] + input + 8 + 4 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFIFO Full interrupt + enable + 31 + 1 + + + TXFEIE + TXFIFO empty interrupt + enable + 30 + 1 + + + FIFOEN + FIFO mode enable + 29 + 1 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt + enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt + enable + 26 + 1 + + + DEAT4 + Driver Enable assertion + time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion + time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + DIS_NSS + When the DSI_NSS bit is set, the NSS pin + input is ignored + 3 + 1 + + + SLVEN + Synchronous Slave mode + enable + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFIFO threshold + configuration + 29 + 3 + + + RXFTIE + RXFIFO threshold interrupt + enable + 28 + 1 + + + RXFTCFG + Receive FIFO threshold + configuration + 25 + 3 + + + TCBGTIE + Transmission Complete before guard time, + interrupt enable + 24 + 1 + + + TXFTIE + TXFIFO threshold interrupt + enable + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR_4_15 + DIV_Mantissa + 4 + 12 + + + BRR_0_3 + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFIFO threshold flag + 27 + 1 + + + RXFT + RXFIFO threshold flag + 26 + 1 + + + TCBGT + Transmission complete before guard time + flag + 25 + 1 + + + RXFF + RXFIFO Full + 24 + 1 + + + TXFE + TXFIFO Empty + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + SPI slave underrun error + flag + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + SPI slave underrun clear + flag + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear + flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear + flag + 8 + 1 + + + TCBGTC + Transmission complete before Guard time + clear flag + 7 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + TXFECF + TXFIFO empty clear flag + 5 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + Clock prescaler + 0 + 4 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + UART4 + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + UART7 + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + TIM1 + Advanced-timers + TIM + 0x40010000 + + 0x0 + 0x400 + registers + + + TIM1_BRK + TIM1 break interrupt + 24 + + + TIM1_UP + TIM1 update interrupt + 25 + + + TIM1_TRG_COM + TIM1 trigger and commutation + 26 + + + TIM_CC + TIM1 capture / compare + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 + 18 + 1 + + + OIS5 + Output Idle state 5 + 16 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + TS + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + ETF + External trigger filter + 8 + 4 + + + ETPS + External trigger prescaler + 12 + 2 + + + ECE + External clock enable + 14 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + SMS_3 + Slave mode selection - bit + 3 + 16 + 1 + + + TS_4_3 + Trigger selection - bit + 4:3 + 20 + 2 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + SBIF + System Break interrupt + flag + 13 + 1 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + TG + Trigger generation + 6 + 1 + + + BG + Break generation + 7 + 1 + + + B2G + Break 2 generation + 8 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC1M_3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC3M_3 + Output Compare 3 mode - bit + 3 + 16 + 1 + + + OC4M_4 + Output Compare 4 mode - bit + 3 + 24 + 1 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4NP + Capture/Compare 4 complementary output + polarity + 15 + 1 + + + CC5E + Capture/Compare 5 output + enable + 16 + 1 + + + CC5P + Capture/Compare 5 output + polarity + 17 + 1 + + + CC6E + Capture/Compare 6 output + enable + 20 + 1 + + + CC6P + Capture/Compare 6 output + polarity + 21 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BK2F + Break 2 filter + 20 + 4 + + + BK2E + Break 2 enable + 24 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 3 (output + mode) + 0x54 + 0x20 + read-write + 0x0000 + + + OC5FE + Output compare 5 fast + enable + 2 + 1 + + + OC5PE + Output compare 5 preload + enable + 3 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5CE + Output compare 5 clear + enable + 7 + 1 + + + OC6FE + Output compare 6 fast + enable + 10 + 1 + + + OC6PE + Output compare 6 preload + enable + 11 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6CE + Output compare 6 clear + enable + 15 + 1 + + + OC5M3 + Output Compare 5 mode + 16 + 1 + + + OC6M3 + Output Compare 6 mode + 24 + 1 + + + + + CCR5 + CCR5 + capture/compare register 5 + 0x58 + 0x20 + read-write + 0x0000 + + + CCR5 + Capture/Compare 5 value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel + 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel + 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel + 3 + 31 + 1 + + + + + CRR6 + CRR6 + capture/compare register 6 + 0x5C + 0x20 + read-write + 0x0000 + + + CCR6 + Capture/Compare 6 value + 0 + 16 + + + + + AF1 + AF1 + TIM1 alternate function option register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDF1BK0E + BRK dfsdm1_break[0] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + ETRSEL + ETR source selection + 14 + 4 + + + + + AF2 + AF2 + TIM1 Alternate function odfsdm1_breakster + 2 + 0x64 + 0x20 + read-write + 0x0000 + + + BK2INE + BRK2 BKIN input enable + 0 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2DF1BK1E + BRK2 dfsdm1_break[1] + enable + 8 + 1 + + + BK2INP + BRK2 BKIN2 input polarity + 9 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarit + 10 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + + + TISEL + TISEL + TIM1 timer input selection + register + 0x68 + 0x20 + read-write + 0x0000 + + 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read-write + 0x00000000 + + + SBCE + Start of Basic Cycle Interrupt + Enable + 0 + 1 + + + SMCE + Start of Matrix Cycle Interrupt + Enable + 1 + 1 + + + CSME + Change of Synchronization Mode Interrupt + Enable + 2 + 1 + + + SOGE + Start of Gap Interrupt + Enable + 3 + 1 + + + RTMIE + Register Time Mark Interrupt + Enable + 4 + 1 + + + TTMIE + Trigger Time Mark Event Internal + Interrupt Enable + 5 + 1 + + + SWEE + Stop Watch Event Interrupt + Enable + 6 + 1 + + + GTWE + Global Time Wrap Interrupt + Enable + 7 + 1 + + + GTDE + Global Time Discontinuity Interrupt + Enable + 8 + 1 + + + GTEE + Global Time Error Interrupt + Enable + 9 + 1 + + + TXUE + Tx Count Underflow Interrupt + Enable + 10 + 1 + + + TXOE + Tx Count Overflow Interrupt + Enable + 11 + 1 + + + SE1E + Scheduling Error 1 Interrupt + Enable + 12 + 1 + + + SE2E + Scheduling Error 2 Interrupt + Enable + 13 + 1 + + + ELCE + Change Error Level Interrupt + Enable + 14 + 1 + + + IWTGE + Initialization Watch Trigger Interrupt + Enable + 15 + 1 + + + WTE + Watch Trigger Interrupt + Enable + 16 + 1 + + + AWE + Application Watchdog Interrupt + Enable + 17 + 1 + + + CERE + Configuration Error Interrupt + Enable + 18 + 1 + + + + + FDCAN_TTILS + FDCAN_TTILS + FDCAN TT Interrupt Line Select + Register + 0x128 + 0x20 + read-write + 0x00000000 + + + SBCL + Start of Basic Cycle Interrupt + Line + 0 + 1 + + + SMCL + Start of Matrix Cycle Interrupt + Line + 1 + 1 + + + CSML + Change of Synchronization Mode Interrupt + Line + 2 + 1 + + + SOGL + Start of Gap Interrupt + Line + 3 + 1 + + + RTMIL + Register Time Mark Interrupt + Line + 4 + 1 + + + TTMIL + Trigger Time Mark Event Internal + Interrupt Line + 5 + 1 + + + SWEL + Stop Watch Event Interrupt + Line + 6 + 1 + + + GTWL + Global Time Wrap Interrupt + Line + 7 + 1 + + + GTDL + Global Time Discontinuity Interrupt + Line + 8 + 1 + + + GTEL + Global Time Error Interrupt + Line + 9 + 1 + + + TXUL + Tx Count Underflow Interrupt + Line + 10 + 1 + + + TXOL + Tx Count Overflow Interrupt + Line + 11 + 1 + + + SE1L + Scheduling Error 1 Interrupt + Line + 12 + 1 + + + SE2L + Scheduling Error 2 Interrupt + Line + 13 + 1 + + + ELCL + Change Error Level Interrupt + Line + 14 + 1 + + + IWTGL + Initialization Watch Trigger Interrupt + Line + 15 + 1 + + + WTL + Watch Trigger Interrupt + Line + 16 + 1 + + + AWL + Application Watchdog Interrupt + Line + 17 + 1 + + + CERL + Configuration Error Interrupt + Line + 18 + 1 + + + + + FDCAN_TTOST + FDCAN_TTOST + FDCAN TT Operation Status + Register + 0x12C + 0x20 + read-write + 0x00000000 + + + EL + Error Level + 0 + 2 + + + MS + Master State. + 2 + 2 + + + SYS + Synchronization State + 4 + 2 + + + GTP + Quality of Global Time + Phase + 6 + 1 + + + QCS + Quality of Clock Speed + 7 + 1 + + + RTO + Reference Trigger Offset + 8 + 8 + + + WGTD + Wait for Global Time + Discontinuity + 22 + 1 + + + GFI + Gap Finished Indicator. + 23 + 1 + + + TMP + Time Master Priority + 24 + 3 + + + GSI + Gap Started Indicator. + 27 + 1 + + + WFE + Wait for Event + 28 + 1 + + + AWE + Application Watchdog Event + 29 + 1 + + + WECS + Wait for External Clock + Synchronization + 30 + 1 + + + SPL + Schedule Phase Lock + 31 + 1 + + + + + FDCAN_TURNA + FDCAN_TURNA + FDCAN TUR Numerator Actual + Register + 0x130 + 0x20 + read-only + 0x00000000 + + + NAV + Numerator Actual Value + 0 + 18 + + + + + FDCAN_TTLGT + FDCAN_TTLGT + FDCAN TT Local and Global Time + Register + 0x134 + 0x20 + read-only + 0x00000000 + + + LT + Local Time + 0 + 16 + + + GT + Global Time + 16 + 16 + + + + + FDCAN_TTCTC + FDCAN_TTCTC + FDCAN TT Cycle Time and Count + Register + 0x138 + 0x20 + read-only + 0x00000000 + + + CT + Cycle Time + 0 + 16 + + + CC + Cycle Count + 16 + 6 + + + + + FDCAN_TTCPT + FDCAN_TTCPT + FDCAN TT Capture Time Register + 0x13C + 0x20 + read-only + 0x00000000 + + + CT + Cycle Count Value + 0 + 6 + + + SWV + Stop Watch Value + 16 + 16 + + + + + FDCAN_TTCSM + FDCAN_TTCSM + FDCAN TT Cycle Sync Mark + Register + 0x140 + 0x20 + read-only + 0x00000000 + + + CSM + Cycle Sync Mark + 0 + 16 + + + + + FDCAN_TTTS + FDCAN_TTTS + FDCAN TT Trigger Select + Register + 0x300 + 0x20 + read-write + 0x00000000 + + + SWTDEL + Stop watch trigger input + selection + 0 + 2 + + + EVTSEL + Event trigger input + selection + 4 + 2 + + + + + + + FDCAN2 + 0x4000A400 + + FDCAN2_IT0 + FDCAN2 Interrupt 0 + 20 + + + FDCAN2_IT1 + FDCAN2 Interrupt 1 + 22 + + + + CAN_CCU + CCU registers + FDCAN + 0x4000A800 + + 0x0 + 0x400 + registers + + + + CREL + CREL + Clock Calibration Unit Core Release + Register + 0x0 + 0x20 + read-write + 0x00000000 + + + DAY + Time Stamp Day + 0 + 8 + + + MON + Time Stamp Month + 8 + 8 + + + YEAR + Time Stamp Year + 16 + 4 + + + SUBSTEP + Sub-step of Core Release + 20 + 4 + + + STEP + Step of Core Release + 24 + 4 + + + REL + Core Release + 28 + 4 + + + + + CCFG + CCFG + Calibration Configuration + Register + 0x4 + 0x20 + read-write + 0x00000000 + + + TQBT + Time Quanta per Bit Time + 0 + 5 + + + BCC + Bypass Clock Calibration + 6 + 1 + + + CFL + Calibration Field Length + 7 + 1 + + + OCPM + Oscillator Clock Periods + Minimum + 8 + 8 + + + CDIV + Clock Divider + 16 + 4 + + + SWR + Software Reset + 31 + 1 + + + + + CSTAT + CSTAT + Calibration Status Register + 0x8 + 0x20 + read-write + 0x00000000 + + + OCPC + Oscillator Clock Period + Counter + 0 + 18 + + + TQC + Time Quanta Counter + 18 + 11 + + + CALS + Calibration State + 30 + 2 + + + + + CWD + CWD + Calibration Watchdog Register + 0xC + 0x20 + read-write + 0x00000000 + + + WDC + WDC + 0 + 16 + + + WDV + WDV + 16 + 16 + + + + + IR + IR + Clock Calibration Unit Interrupt + Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CWE + Calibration Watchdog Event + 0 + 1 + + + CSC + Calibration State Changed + 1 + 1 + + + + + IE + IE + Clock Calibration Unit Interrupt Enable + Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CWEE + Calibration Watchdog Event + Enable + 0 + 1 + + + CSCE + Calibration State Changed + Enable + 1 + 1 + + + + + + + MDIOS + Management data input/output slave + MDIOS + 0x40009400 + + 0x0 + 0x400 + registers + + + MDIOS_WKUP + MDIOS wakeup + 119 + + + MDIOS + MDIOS global interrupt + 120 + + + + MDIOS_CR + MDIOS_CR + MDIOS configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + Peripheral enable + 0 + 1 + + + WRIE + Register write interrupt + enable + 1 + 1 + + + RDIE + Register Read Interrupt + Enable + 2 + 1 + + + EIE + Error interrupt enable + 3 + 1 + + + DPC + Disable Preamble Check + 7 + 1 + + + PORT_ADDRESS + Slaves's address + 8 + 5 + + + + + MDIOS_WRFR + MDIOS_WRFR + MDIOS write flag register + 0x4 + 0x20 + read-only + 0x00000000 + + + WRF + Write flags for MDIO registers 0 to + 31 + 0 + 32 + + + + + MDIOS_CWRFR + MDIOS_CWRFR + MDIOS clear write flag + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CWRF + Clear the write flag + 0 + 32 + + + + + MDIOS_RDFR + MDIOS_RDFR + MDIOS read flag register + 0xC + 0x20 + read-only + 0x00000000 + + + RDF + Read flags for MDIO registers 0 to + 31 + 0 + 32 + + + + + MDIOS_CRDFR + MDIOS_CRDFR + MDIOS clear read flag register + 0x10 + 0x20 + read-write + 0x00000000 + + + CRDF + Clear the read flag + 0 + 32 + + + + + MDIOS_SR + MDIOS_SR + MDIOS status register + 0x14 + 0x20 + read-only + 0x00000000 + + + PERF + Preamble error flag + 0 + 1 + + + SERF + Start error flag + 1 + 1 + + + TERF + Turnaround error flag + 2 + 1 + + + + + MDIOS_CLRFR + MDIOS_CLRFR + MDIOS clear flag register + 0x18 + 0x20 + read-write + 0x00000000 + + + CPERF + Clear the preamble error + flag + 0 + 1 + + + CSERF + Clear the start error flag + 1 + 1 + + + CTERF + Clear the turnaround error + flag + 2 + 1 + + + + + MDIOS_DINR0 + MDIOS_DINR0 + MDIOS input data register 0 + 0x1C + 0x20 + read-only + 0x00000000 + + + DIN0 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR1 + MDIOS_DINR1 + MDIOS input data register 1 + 0x20 + 0x20 + read-only + 0x00000000 + + + DIN1 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR2 + MDIOS_DINR2 + MDIOS input data register 2 + 0x24 + 0x20 + read-only + 0x00000000 + + + DIN2 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR3 + MDIOS_DINR3 + MDIOS input data register 3 + 0x28 + 0x20 + read-only + 0x00000000 + + + DIN3 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR4 + MDIOS_DINR4 + MDIOS input data register 4 + 0x2C + 0x20 + read-only + 0x00000000 + + + DIN4 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR5 + MDIOS_DINR5 + MDIOS input data register 5 + 0x30 + 0x20 + read-only + 0x00000000 + + + DIN5 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR6 + MDIOS_DINR6 + MDIOS input data register 6 + 0x34 + 0x20 + read-only + 0x00000000 + + + DIN6 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR7 + MDIOS_DINR7 + MDIOS input data register 7 + 0x38 + 0x20 + read-only + 0x00000000 + + + DIN7 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR8 + MDIOS_DINR8 + MDIOS input data register 8 + 0x3C + 0x20 + read-only + 0x00000000 + + + DIN8 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR9 + MDIOS_DINR9 + MDIOS input data register 9 + 0x40 + 0x20 + read-only + 0x00000000 + + + DIN9 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR10 + MDIOS_DINR10 + MDIOS input data register 10 + 0x44 + 0x20 + read-only + 0x00000000 + + + DIN10 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR11 + MDIOS_DINR11 + MDIOS input data register 11 + 0x48 + 0x20 + read-only + 0x00000000 + + + DIN11 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR12 + MDIOS_DINR12 + MDIOS input data register 12 + 0x4C + 0x20 + read-only + 0x00000000 + + + DIN12 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR13 + MDIOS_DINR13 + MDIOS input data register 13 + 0x50 + 0x20 + read-only + 0x00000000 + + + DIN13 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR14 + MDIOS_DINR14 + MDIOS input data register 14 + 0x54 + 0x20 + read-only + 0x00000000 + + + DIN14 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR15 + MDIOS_DINR15 + MDIOS input data register 15 + 0x58 + 0x20 + read-only + 0x00000000 + + + DIN15 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR16 + MDIOS_DINR16 + MDIOS input data register 16 + 0x5C + 0x20 + read-only + 0x00000000 + + + DIN16 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR17 + MDIOS_DINR17 + MDIOS input data register 17 + 0x60 + 0x20 + read-only + 0x00000000 + + + DIN17 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR18 + MDIOS_DINR18 + MDIOS input data register 18 + 0x64 + 0x20 + read-only + 0x00000000 + + + DIN18 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR19 + MDIOS_DINR19 + MDIOS input data register 19 + 0x68 + 0x20 + read-only + 0x00000000 + + + DIN19 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR20 + MDIOS_DINR20 + MDIOS input data register 20 + 0x6C + 0x20 + read-only + 0x00000000 + + + DIN20 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR21 + MDIOS_DINR21 + MDIOS input data register 21 + 0x70 + 0x20 + read-only + 0x00000000 + + + DIN21 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR22 + MDIOS_DINR22 + MDIOS input data register 22 + 0x74 + 0x20 + read-only + 0x00000000 + + + DIN22 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR23 + MDIOS_DINR23 + MDIOS input data register 23 + 0x78 + 0x20 + read-only + 0x00000000 + + + DIN23 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR24 + MDIOS_DINR24 + MDIOS input data register 24 + 0x7C + 0x20 + read-only + 0x00000000 + + + DIN24 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR25 + MDIOS_DINR25 + MDIOS input data register 25 + 0x80 + 0x20 + read-only + 0x00000000 + + + DIN25 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR26 + MDIOS_DINR26 + MDIOS input data register 26 + 0x84 + 0x20 + read-only + 0x00000000 + + + DIN26 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR27 + MDIOS_DINR27 + MDIOS input data register 27 + 0x88 + 0x20 + read-only + 0x00000000 + + + DIN27 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR28 + MDIOS_DINR28 + MDIOS input data register 28 + 0x8C + 0x20 + read-only + 0x00000000 + + + DIN28 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR29 + MDIOS_DINR29 + MDIOS input data register 29 + 0x90 + 0x20 + read-only + 0x00000000 + + + DIN29 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR30 + MDIOS_DINR30 + MDIOS input data register 30 + 0x94 + 0x20 + read-only + 0x00000000 + + + DIN30 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DINR31 + MDIOS_DINR31 + MDIOS input data register 31 + 0x98 + 0x20 + read-only + 0x00000000 + + + DIN31 + Input data received from MDIO Master + during write frames + 0 + 16 + + + + + MDIOS_DOUTR0 + MDIOS_DOUTR0 + MDIOS output data register 0 + 0x9C + 0x20 + read-write + 0x00000000 + + + DOUT0 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR1 + MDIOS_DOUTR1 + MDIOS output data register 1 + 0xA0 + 0x20 + read-write + 0x00000000 + + + DOUT1 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR2 + MDIOS_DOUTR2 + MDIOS output data register 2 + 0xA4 + 0x20 + read-write + 0x00000000 + + + DOUT2 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR3 + MDIOS_DOUTR3 + MDIOS output data register 3 + 0xA8 + 0x20 + read-write + 0x00000000 + + + DOUT3 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR4 + MDIOS_DOUTR4 + MDIOS output data register 4 + 0xAC + 0x20 + read-write + 0x00000000 + + + DOUT4 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR5 + MDIOS_DOUTR5 + MDIOS output data register 5 + 0xB0 + 0x20 + read-write + 0x00000000 + + + DOUT5 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR6 + MDIOS_DOUTR6 + MDIOS output data register 6 + 0xB4 + 0x20 + read-write + 0x00000000 + + + DOUT6 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR7 + MDIOS_DOUTR7 + MDIOS output data register 7 + 0xB8 + 0x20 + read-write + 0x00000000 + + + DOUT7 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR8 + MDIOS_DOUTR8 + MDIOS output data register 8 + 0xBC + 0x20 + read-write + 0x00000000 + + + DOUT8 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR9 + MDIOS_DOUTR9 + MDIOS output data register 9 + 0xC0 + 0x20 + read-write + 0x00000000 + + + DOUT9 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR10 + MDIOS_DOUTR10 + MDIOS output data register 10 + 0xC4 + 0x20 + read-write + 0x00000000 + + + DOUT10 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR11 + MDIOS_DOUTR11 + MDIOS output data register 11 + 0xC8 + 0x20 + read-write + 0x00000000 + + + DOUT11 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR12 + MDIOS_DOUTR12 + MDIOS output data register 12 + 0xCC + 0x20 + read-write + 0x00000000 + + + DOUT12 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR13 + MDIOS_DOUTR13 + MDIOS output data register 13 + 0xD0 + 0x20 + read-write + 0x00000000 + + + DOUT13 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR14 + MDIOS_DOUTR14 + MDIOS output data register 14 + 0xD4 + 0x20 + read-write + 0x00000000 + + + DOUT14 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR15 + MDIOS_DOUTR15 + MDIOS output data register 15 + 0xD8 + 0x20 + read-write + 0x00000000 + + + DOUT15 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR16 + MDIOS_DOUTR16 + MDIOS output data register 16 + 0xDC + 0x20 + read-write + 0x00000000 + + + DOUT16 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR17 + MDIOS_DOUTR17 + MDIOS output data register 17 + 0xE0 + 0x20 + read-write + 0x00000000 + + + DOUT17 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR18 + MDIOS_DOUTR18 + MDIOS output data register 18 + 0xE4 + 0x20 + read-write + 0x00000000 + + + DOUT18 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR19 + MDIOS_DOUTR19 + MDIOS output data register 19 + 0xE8 + 0x20 + read-write + 0x00000000 + + + DOUT19 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR20 + MDIOS_DOUTR20 + MDIOS output data register 20 + 0xEC + 0x20 + read-write + 0x00000000 + + + DOUT20 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR21 + MDIOS_DOUTR21 + MDIOS output data register 21 + 0xF0 + 0x20 + read-write + 0x00000000 + + + DOUT21 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR22 + MDIOS_DOUTR22 + MDIOS output data register 22 + 0xF4 + 0x20 + read-write + 0x00000000 + + + DOUT22 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR23 + MDIOS_DOUTR23 + MDIOS output data register 23 + 0xF8 + 0x20 + read-write + 0x00000000 + + + DOUT23 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR24 + MDIOS_DOUTR24 + MDIOS output data register 24 + 0xFC + 0x20 + read-write + 0x00000000 + + + DOUT24 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR25 + MDIOS_DOUTR25 + MDIOS output data register 25 + 0x100 + 0x20 + read-write + 0x00000000 + + + DOUT25 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR26 + MDIOS_DOUTR26 + MDIOS output data register 26 + 0x104 + 0x20 + read-write + 0x00000000 + + + DOUT26 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR27 + MDIOS_DOUTR27 + MDIOS output data register 27 + 0x108 + 0x20 + read-write + 0x00000000 + + + DOUT27 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR28 + MDIOS_DOUTR28 + MDIOS output data register 28 + 0x10C + 0x20 + read-write + 0x00000000 + + + DOUT28 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR29 + MDIOS_DOUTR29 + MDIOS output data register 29 + 0x110 + 0x20 + read-write + 0x00000000 + + + DOUT29 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR30 + MDIOS_DOUTR30 + MDIOS output data register 30 + 0x114 + 0x20 + read-write + 0x00000000 + + + DOUT30 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + MDIOS_DOUTR31 + MDIOS_DOUTR31 + MDIOS output data register 31 + 0x118 + 0x20 + read-write + 0x00000000 + + + DOUT31 + Output data sent to MDIO Master during + read frames + 0 + 16 + + + + + + + OPAMP + Operational amplifiers + OPAMP + 0x40009000 + + 0x0 + 0x400 + registers + + + + OPAMP1_CSR + OPAMP1_CSR + OPAMP1 control/status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier + Enable + 0 + 1 + + + FORCE_VP + Force internal reference on VP (reserved + for test + 1 + 1 + + + VP_SEL + Operational amplifier PGA + mode + 2 + 2 + + + VM_SEL + Inverting input selection + 5 + 2 + + + OPAHSM + Operational amplifier high-speed + mode + 8 + 1 + + + CALON + Calibration mode enabled + 11 + 1 + + + CALSEL + Calibration selection + 12 + 2 + + + PGA_GAIN + allows to switch from AOP offset trimmed + values to AOP offset + 14 + 4 + + + USERTRIM + User trimming enable + 18 + 1 + + + TSTREF + OPAMP calibration reference voltage + output control (reserved for test) + 29 + 1 + + + CALOUT + Operational amplifier calibration + output + 30 + 1 + + + + + OPAMP1_OTR + OPAMP1_OTR + OPAMP1 offset trimming register in normal + mode + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIMOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP1_HSOTR + OPAMP1_HSOTR + OPAMP1 offset trimming register in low-power + mode + 0x8 + 0x20 + read-write + 0x00000000 + + + TRIMLPOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMLPOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP2_CSR + OPAMP2_CSR + OPAMP2 control/status register + 0x10 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier + Enable + 0 + 1 + + + FORCE_VP + Force internal reference on VP (reserved + for test) + 1 + 1 + + + VM_SEL + Inverting input selection + 5 + 2 + + + OPAHSM + Operational amplifier high-speed + mode + 8 + 1 + + + CALON + Calibration mode enabled + 11 + 1 + + + CALSEL + Calibration selection + 12 + 2 + + + PGA_GAIN + Operational amplifier Programmable + amplifier gain value + 14 + 4 + + + USERTRIM + User trimming enable + 18 + 1 + + + TSTREF + OPAMP calibration reference voltage + output control (reserved for test) + 29 + 1 + + + CALOUT + Operational amplifier calibration + output + 30 + 1 + + + + + OPAMP2_OTR + OPAMP2_OTR + OPAMP2 offset trimming register in normal + mode + 0x14 + 0x20 + read-write + 0x00000000 + + + TRIMOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP2_HSOTR + OPAMP2_HSOTR + OPAMP2 offset trimming register in low-power + mode + 0x18 + 0x20 + read-write + 0x00000000 + + + TRIMLPOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMLPOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + + + SWPMI + Single Wire Protocol Master + Interface + SWPMI + 0x40008800 + + 0x0 + 0x400 + registers + + + SWPMI1 + SWPMI global interrupt + 115 + + + + CR + CR + SWPMI Configuration/Control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RXDMA + Reception DMA enable + 0 + 1 + + + TXDMA + Transmission DMA enable + 1 + 1 + + + RXMODE + Reception buffering mode + 2 + 1 + + + TXMODE + Transmission buffering + mode + 3 + 1 + + + LPBK + Loopback mode enable + 4 + 1 + + + SWPACT + Single wire protocol master interface + activate + 5 + 1 + + + DEACT + Single wire protocol master interface + deactivate + 10 + 1 + + + SWPTEN + Single wire protocol master transceiver + enable + 11 + 1 + + + + + BRR + BRR + SWPMI Bitrate register + 0x4 + 0x20 + read-write + 0x00000001 + + + BR + Bitrate prescaler + 0 + 8 + + + + + ISR + ISR + SWPMI Interrupt and Status + register + 0xC + 0x20 + read-only + 0x000002C2 + + + RXBFF + Receive buffer full flag + 0 + 1 + + + TXBEF + Transmit buffer empty flag + 1 + 1 + + + RXBERF + Receive CRC error flag + 2 + 1 + + + RXOVRF + Receive overrun error flag + 3 + 1 + + + TXUNRF + Transmit underrun error + flag + 4 + 1 + + + RXNE + Receive data register not + empty + 5 + 1 + + + TXE + Transmit data register + empty + 6 + 1 + + + TCF + Transfer complete flag + 7 + 1 + + + SRF + Slave resume flag + 8 + 1 + + + SUSP + SUSPEND flag + 9 + 1 + + + DEACTF + DEACTIVATED flag + 10 + 1 + + + RDYF + transceiver ready flag + 11 + 1 + + + + + ICR + ICR + SWPMI Interrupt Flag Clear + register + 0x10 + 0x20 + write-only + 0x00000000 + + + CRXBFF + Clear receive buffer full + flag + 0 + 1 + + + CTXBEF + Clear transmit buffer empty + flag + 1 + 1 + + + CRXBERF + Clear receive CRC error + flag + 2 + 1 + + + CRXOVRF + Clear receive overrun error + flag + 3 + 1 + + + CTXUNRF + Clear transmit underrun error + flag + 4 + 1 + + + CTCF + Clear transfer complete + flag + 7 + 1 + + + CSRF + Clear slave resume flag + 8 + 1 + + + CRDYF + Clear transceiver ready + flag + 11 + 1 + + + + + IER + IER + SWPMI Interrupt Enable + register + 0x14 + 0x20 + read-write + 0x00000000 + + + RXBFIE + Receive buffer full interrupt + enable + 0 + 1 + + + TXBEIE + Transmit buffer empty interrupt + enable + 1 + 1 + + + RXBERIE + Receive CRC error interrupt + enable + 2 + 1 + + + RXOVRIE + Receive overrun error interrupt + enable + 3 + 1 + + + TXUNRIE + Transmit underrun error interrupt + enable + 4 + 1 + + + RIE + Receive interrupt enable + 5 + 1 + + + TIE + Transmit interrupt enable + 6 + 1 + + + TCIE + Transmit complete interrupt + enable + 7 + 1 + + + SRIE + Slave resume interrupt + enable + 8 + 1 + + + RDYIE + Transceiver ready interrupt + enable + 11 + 1 + + + + + RFL + RFL + SWPMI Receive Frame Length + register + 0x18 + 0x20 + read-only + 0x00000000 + + + RFL + Receive frame length + 0 + 5 + + + + + TDR + TDR + SWPMI Transmit data register + 0x1C + 0x20 + write-only + 0x00000000 + + + TD + Transmit data + 0 + 32 + + + + + RDR + RDR + SWPMI Receive data register + 0x20 + 0x20 + read-only + 0x00000000 + + + RD + received data + 0 + 32 + + + + + OR + OR + SWPMI Option register + 0x24 + 0x20 + read-write + 0x00000000 + + + SWP_TBYP + SWP transceiver bypass + 0 + 1 + + + SWP_CLASS + SWP class selection + 1 + 1 + + + + + + + TIM2 + General purpose timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + TS_4_3 + Trigger selection + 20 + 2 + + + SMS_3 + Slave mode selection - bit + 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + OC1FE + OC1FE + 2 + 1 + + + OC1PE + OC1PE + 3 + 1 + + + OC1M + OC1M + 4 + 3 + + + OC1CE + OC1CE + 7 + 1 + + + CC2S + CC2S + 8 + 2 + + + OC2FE + OC2FE + 10 + 1 + + + OC2PE + OC2PE + 11 + 1 + + + OC2M + OC2M + 12 + 3 + + + OC2CE + OC2CE + 15 + 1 + + + OC1M_3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + OC3M_3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC4CE + OC4CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + OC4PE + OC4PE + 11 + 1 + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + + OC3PE + OC3PE + 3 + 1 + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT_L + low counter value + 0 + 16 + + + CNT_H + High counter value + 16 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR_H + High Auto-reload value + 16 + 16 + + + ARR_L + Low Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1_H + High Capture/Compare 1 + value + 16 + 16 + + + CCR1_L + Low Capture/Compare 1 + value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2_H + High Capture/Compare 2 + value + 16 + 16 + + + CCR2_L + Low Capture/Compare 2 + value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3_H + High Capture/Compare value + 16 + 16 + + + CCR3_L + Low Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4_H + High Capture/Compare value + 16 + 16 + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + AF1 + AF1 + TIM alternate function option register + 1 + 0x60 + 0x20 + read-write + 0x0000 + + + ETRSEL + ETR source selection + 14 + 4 + + + + + TISEL + TISEL + TIM timer input selection + register + 0x68 + 0x20 + read-write + 0x0000 + + + TI1SEL + TI1[0] to TI1[15] input + selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input + selection + 8 + 4 + + + TI3SEL + TI3[0] to TI3[15] input + selection + 16 + 4 + + + TI4SEL + TI4[0] to TI4[15] input + selection + 24 + 4 + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 global interrupt + 29 + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 global interrupt + 30 + + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 global interrupt + 50 + + + + TIM12 + 0x40001800 + + + TIM13 + 0x40001C00 + + + TIM14 + 0x40002000 + + + TIM6 + Basic timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + UIFCPY + UIF Copy + 31 + 1 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 55 + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x401 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable + Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending + Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x208 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register + 0x350 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR21 + IPR21 + Interrupt Priority Register + 0x354 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR22 + IPR22 + Interrupt Priority Register + 0x358 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR23 + IPR23 + Interrupt Priority Register + 0x35C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR24 + IPR24 + Interrupt Priority Register + 0x360 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR25 + IPR25 + Interrupt Priority Register + 0x364 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR26 + IPR26 + Interrupt Priority Register + 0x368 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR27 + IPR27 + Interrupt Priority Register + 0x36C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR28 + IPR28 + Interrupt Priority Register + 0x370 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR29 + IPR29 + Interrupt Priority Register + 0x374 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR30 + IPR30 + Interrupt Priority Register + 0x378 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR31 + IPR31 + Interrupt Priority Register + 0x37C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR32 + IPR32 + Interrupt Priority Register + 0x380 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR33 + IPR33 + Interrupt Priority Register + 0x384 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR34 + IPR34 + Interrupt Priority Register + 0x388 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR35 + IPR35 + Interrupt Priority Register + 0x38C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR36 + IPR36 + Interrupt Priority Register + 0x390 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR37 + IPR37 + Interrupt Priority Register + 0x394 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR38 + IPR38 + Interrupt Priority Register + 0x398 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + ISER3 + ISER3 + Interrupt Set-Enable Register + 0xC + 0x20 + read-write + 0x00000000 + + + ICER3 + ICER3 + Interrupt Clear-Enable + Register + 0x8C + 0x20 + read-write + 0x00000000 + + + ISPR3 + ISPR3 + Interrupt Set-Pending Register + 0x10C + 0x20 + read-write + 0x00000000 + + + ICPR3 + ICPR3 + Interrupt Clear-Pending + Register + 0x1C0 + 0x20 + read-write + 0x00000000 + + + IABR3 + IABR3 + Interrupt Active Bit Register + 0x20C + 0x20 + read-write + 0x00000000 + + + + + DBGMCU + Microcontroller Debug Unit + DBGMCU + 0x5C001000 + + 0x0 + 0x400 + registers + + + + IDC + IDC + DBGMCU Identity Code Register + 0x0 + 0x20 + read-only + 0x10006450 + + + DEV_ID + Device ID + 0 + 12 + + + REV_ID + Revision + 16 + 16 + + + + + CR + CR + DBGMCU Configuration Register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBGSLPD1 + Allow D1 domain debug in Sleep mode + 0 + 1 + + + DBGSTPD1 + Allow D1 domain debug in Stop mode + 1 + 1 + + + DBGSTBD1 + Allow D1 domain debug in Standby mode + 2 + 1 + + + DBGSLPD2 + Allow D2 domain debug in Sleep mode + 3 + 1 + + + DBGSTPD2 + Allow D2 domain debug in Stop mode + 4 + 1 + + + DBGSTBD2 + Allow D2 domain debug in Standby mode + 5 + 1 + + + DBGSTPD3 + Allow debug in D3 Stop mode + 7 + 1 + + + DBGSTBD3 + Allow debug in D3 Standby mode + 8 + 1 + + + TRACECLKEN + Trace port clock enable + 20 + 1 + + + D1DBGCKEN + D1 debug clock enable + 21 + 1 + + + D3DBGCKEN + D3 debug clock enable + 22 + 1 + + + TRGOEN + External trigger output enable + 28 + 1 + + + + + APB3FZ1 + APB3FZ1 + DBGMCU APB3 peripheral freeze register CPU1 + 0x34 + 0x20 + read-write + 0x00000000 + + + WWDG1 + WWDG1 stop in debug + 6 + 1 + + + + + APB3FZ2 + APB3FZ2 + DBGMCU APB3 peripheral freeze register CPU2 + 0x38 + 0x20 + read-write + 0x00000000 + + + WWDG1 + WWDG1 stop in debug + 6 + 1 + + + + + APB1LFZ1 + APB1LFZ1 + DBGMCU APB1L peripheral freeze register + 0x3C + 0x20 + read-write + 0x00000000 + + + DBG_TIM2 + TIM2 stop in debug + 0 + 1 + + + DBG_TIM3 + TIM3 stop in debug + 1 + 1 + + + DBG_TIM4 + TIM4 stop in debug + 2 + 1 + + + DBG_TIM5 + TIM5 stop in debug + 3 + 1 + + + DBG_TIM6 + TIM6 stop in debug + 4 + 1 + + + DBG_TIM7 + TIM7 stop in debug + 5 + 1 + + + DBG_TIM12 + TIM12 stop in debug + 6 + 1 + + + DBG_TIM13 + TIM13 stop in debug + 7 + 1 + + + DBG_TIM14 + TIM14 stop in debug + 8 + 1 + + + DBG_LPTIM1 + LPTIM1 stop in debug + 9 + 1 + + + DBG_WWDG2 + WWDG2 stop in debug + 11 + 1 + + + DBG_I2C1 + I2C1 SMBUS timeout stop in debug + 21 + 1 + + + DBG_I2C2 + I2C2 SMBUS timeout stop in debug + 22 + 1 + + + DBG_I2C3 + I2C3 SMBUS timeout stop in debug + 23 + 1 + + + + + APB1LFZ2 + APB1LFZ2 + DBGMCU APB1L peripheral freeze register CPU2 + 0x40 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2 + TIM2 stop in debug + 0 + 1 + + + DBG_TIM3 + TIM3 stop in debug + 1 + 1 + + + DBG_TIM4 + TIM4 stop in debug + 2 + 1 + + + DBG_TIM5 + TIM5 stop in debug + 3 + 1 + + + DBG_TIM6 + TIM6 stop in debug + 4 + 1 + + + DBG_TIM7 + TIM4 stop in debug + 5 + 1 + + + DBG_TIM12 + TIM12 stop in debug + 6 + 1 + + + DBG_TIM13 + TIM13 stop in debug + 7 + 1 + + + DBG_TIM14 + TIM14 stop in debug + 8 + 1 + + + DBG_LPTIM1 + LPTIM1 stop in debug + 9 + 1 + + + DBG_WWDG2 + WWDG2 stop in debug + 11 + 1 + + + DBG_I2C1 + I2C1 SMBUS timeout stop in debug + 21 + 1 + + + DBG_I2C2 + I2C2 SMBUS timeout stop in debug + 22 + 1 + + + DBG_I2C3 + I2C3 SMBUS timeout stop in debug + 23 + 1 + + + + + APB2FZ1 + APB2FZ1 + DBGMCU APB2 peripheral freeze register + 0x4C + 0x20 + read-write + 0x00000000 + + + DBG_TIM1 + TIM1 stop in debug + 0 + 1 + + + DBG_TIM8 + TIM8 stop in debug + 1 + 1 + + + DBG_TIM15 + TIM15 stop in debug + 16 + 1 + + + DBG_TIM16 + TIM16 stop in debug + 17 + 1 + + + DBG_TIM17 + TIM17 stop in debug + 18 + 1 + + + DBG_HRTIM + HRTIM stop in debug + 29 + 1 + + + + + APB2FZ2 + APB2FZ2 + DBGMCU APB2 peripheral freeze register CPU2 + 0x50 + 0x20 + read-write + 0x00000000 + + + DBG_TIM1 + TIM1 stop in debug + 0 + 1 + + + DBG_TIM8 + TIM8 stop in debug + 1 + 1 + + + DBG_TIM15 + TIM15 stop in debug + 16 + 1 + + + DBG_TIM16 + TIM16 stop in debug + 17 + 1 + + + DBG_TIM17 + TIM17 stop in debug + 18 + 1 + + + DBG_HRTIM + HRTIM stop in debug + 29 + 1 + + + + + APB4FZ1 + APB4FZ1 + DBGMCU APB4 peripheral freeze register + 0x54 + 0x20 + read-write + 0x00000000 + + + DBG_I2C4 + I2C4 SMBUS timeout stop in debug + 7 + 1 + + + DBG_LPTIM2 + LPTIM2 stop in debug + 9 + 1 + + + DBG_LPTIM3 + LPTIM2 stop in debug + 10 + 1 + + + DBG_LPTIM4 + LPTIM4 stop in debug + 11 + 1 + + + DBG_LPTIM5 + LPTIM5 stop in debug + 12 + 1 + + + DBG_RTC + RTC stop in debug + 16 + 1 + + + DBG_WDGLSD1 + Independent watchdog for D1 stop in debug + 18 + 1 + + + DBG_WDGLSD2 + Independent watchdog for D2 stop in debug + 19 + 1 + + + + + APB4FZ2 + APB4FZ2 + DBGMCU APB4 peripheral freeze register CPU2 + 0x58 + 0x20 + read-write + 0x00000000 + + + DBG_I2C4 + I2C4 SMBUS timeout stop in debug + 7 + 1 + + + DBG_LPTIM2 + LPTIM2 stop in debug + 9 + 1 + + + DBG_LPTIM3 + LPTIM2 stop in debug + 10 + 1 + + + DBG_LPTIM4 + LPTIM4 stop in debug + 11 + 1 + + + DBG_LPTIM5 + LPTIM5 stop in debug + 12 + 1 + + + DBG_RTC + RTC stop in debug + 16 + 1 + + + DBG_WDGLSD1 + LS watchdog for D1 stop in debug + 18 + 1 + + + DBG_WDGLSD2 + LS watchdog for D2 stop in debug + 19 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-write + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CSR + CSR + SysTick control and status + register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + RVR + RVR + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + CVR + CVR + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control + register + 0x0 + 0x20 + read-write + 0x0000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISFOLD + DISFOLD + 2 + 1 + + + FPEXCODIS + FPEXCODIS + 10 + 1 + + + DISRAMODE + DISRAMODE + 11 + 1 + + + DISITMATBFLUSH + DISITMATBFLUSH + 12 + 1 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point unit interrupt + 81 + + + + FPCCR + FPCCR + Floating-point context control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address + register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated + floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control + register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception + bit + 0 + 1 + + + DZC + Division by zero cumulative exception + bit. + 1 + 1 + + + OFC + Overflow cumulative exception + bit + 2 + 1 + + + UFC + Underflow cumulative exception + bit + 3 + 1 + + + IXC + Inexact cumulative exception + bit + 4 + 1 + + + IDC + Input denormal cumulative exception + bit. + 7 + 1 + + + RMode + Rounding Mode control + field + 22 + 2 + + + FZ + Flush-to-zero mode control + bit: + 24 + 1 + + + DN + Default NaN mode control + bit + 25 + 1 + + + AHP + Alternative half-precision control + bit + 26 + 1 + + + V + Overflow condition code + flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code + flag + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + DC + DC + 16 + 1 + + + IC + IC + 17 + 1 + + + BP + BP + 18 + 1 + + + + + SHPR1 + SHPR1 + System handler priority + registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler + 4 + 0 + 8 + + + PRI_5 + Priority of system handler + 5 + 8 + 8 + + + PRI_6 + Priority of system handler + 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + SHCSR + SHCSR + System handler control and state + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active + bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active + bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active + bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active + bit + 10 + 1 + + + SYSTICKACT + SysTick exception active + bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending + bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception + pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending + bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable + bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status + register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + IACCVIOL + 0 + 1 + + + DACCVIOL + DACCVIOL + 1 + 1 + + + MUNSTKERR + MUNSTKERR + 3 + 1 + + + MSTKERR + MSTKERR + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + MMARVALID + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return + from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception + entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state + preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid + flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage + fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage + fault + 18 + 1 + + + NOCP + No coprocessor usage + fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage + fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Memory management fault + address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Bus fault address + 0 + 32 + + + + + + + PF + Processor features + PF + 0xE000ED78 + + 0x0 + 0xD + registers + + + + CLIDR + CLIDR + Cache Level ID register + 0x0 + 0x20 + read-only + 0x09000003 + + + CL1 + CL1 + 0 + 3 + + + CL2 + CL2 + 3 + 3 + + + CL3 + CL3 + 6 + 3 + + + CL4 + CL4 + 9 + 3 + + + CL5 + CL5 + 12 + 3 + + + CL6 + CL6 + 15 + 3 + + + CL7 + CL7 + 18 + 3 + + + LoUIS + LoUIS + 21 + 3 + + + LoC + LoC + 24 + 3 + + + LoU + LoU + 27 + 3 + + + + + CTR + CTR + Cache Type register + 0x4 + 0x20 + read-only + 0X8303C003 + + + _IminLine + IminLine + 0 + 4 + + + DMinLine + DMinLine + 16 + 4 + + + ERG + ERG + 20 + 4 + + + CWG + CWG + 24 + 4 + + + Format + Format + 29 + 3 + + + + + CCSIDR + CCSIDR + Cache Size ID register + 0x8 + 0x20 + read-only + 0X00000000 + + + LineSize + LineSize + 0 + 3 + + + Associativity + Associativity + 3 + 10 + + + NumSets + NumSets + 13 + 15 + + + WA + WA + 28 + 1 + + + RA + RA + 29 + 1 + + + WB + WB + 30 + 1 + + + WT + WT + 31 + 1 + + + + + + + AC + Access control + AC + 0xE000EF90 + + 0x0 + 0x1D + registers + + + + ITCMCR + ITCMCR + Instruction and Data Tightly-Coupled Memory + Control Registers + 0x0 + 0x20 + read-write + 0X00000000 + + + EN + EN + 0 + 1 + + + RMW + RMW + 1 + 1 + + + RETEN + RETEN + 2 + 1 + + + SZ + SZ + 3 + 4 + + + + + DTCMCR + DTCMCR + Instruction and Data Tightly-Coupled Memory + Control Registers + 0x4 + 0x20 + read-write + 0X00000000 + + + EN + EN + 0 + 1 + + + RMW + RMW + 1 + 1 + + + RETEN + RETEN + 2 + 1 + + + SZ + SZ + 3 + 4 + + + + + AHBPCR + AHBPCR + AHBP Control register + 0x8 + 0x20 + read-write + 0X00000000 + + + EN + EN + 0 + 1 + + + SZ + SZ + 1 + 3 + + + + + CACR + CACR + Auxiliary Cache Control + register + 0xC + 0x20 + read-write + 0X00000000 + + + SIWT + SIWT + 0 + 1 + + + ECCEN + ECCEN + 1 + 1 + + + FORCEWT + FORCEWT + 2 + 1 + + + + + AHBSCR + AHBSCR + AHB Slave Control register + 0x10 + 0x20 + read-write + 0X00000000 + + + CTL + CTL + 0 + 2 + + + TPRI + TPRI + 2 + 9 + + + INITCOUNT + INITCOUNT + 11 + 5 + + + + + ABFSR + ABFSR + Auxiliary Bus Fault Status + register + 0x18 + 0x20 + read-write + 0X00000000 + + + ITCM + ITCM + 0 + 1 + + + DTCM + DTCM + 1 + 1 + + + AHBP + AHBP + 2 + 1 + + + AXIM + AXIM + 3 + 1 + + + EPPB + EPPB + 4 + 1 + + + AXIMTYPE + AXIMTYPE + 8 + 2 + + + + + + + RAMECC1 + ECC controller is associated to each RAM + area + RAMECC + 0x52009000 + + 0x0 + 0x400 + registers + + + + IER + IER + RAMECC interrupt enable + register + 0x0 + 0x20 + read-write + 0x00000000 + + + GIE + Global interrupt enable + 0 + 1 + + + GECCSEIE_ + Global ECC single error interrupt + enable + 1 + 1 + + + GECCDEIE + Global ECC double error interrupt + enable + 2 + 1 + + + GECCDEBWIE + Global ECC double error on byte write + (BW) interrupt enable + 3 + 1 + + + + + M1CR + M1CR + RAMECC monitor x configuration + register + 0x20 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1SR + M1SR + RAMECC monitor x status + register + 0x24 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1FAR + M1FAR + RAMECC monitor x failing address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1FDRL + M1FDRL + RAMECC monitor x failing data low + register + 0x2C + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1FDRH + M1FDRH + RAMECC monitor x failing data high + register + 0x30 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1FECR + M1FECR + RAMECC monitor x failing ECC error code + register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2CR + M2CR + RAMECC monitor x configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2SR + M2SR + RAMECC monitor x status + register + 0x44 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2FAR + M2FAR + RAMECC monitor x failing address + register + 0x48 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2FDRL + M2FDRL + RAMECC monitor x failing data low + register + 0x4C + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2FDRH + M2FDRH + RAMECC monitor x failing data high + register + 0x50 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M2FECR + M2FECR + RAMECC monitor x failing ECC error code + register + 0x58 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3CR + M3CR + RAMECC monitor x configuration + register + 0x60 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3SR + M3SR + RAMECC monitor x status + register + 0x64 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3FAR + M3FAR + RAMECC monitor x failing address + register + 0x68 + 0x20 + read-write + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3FDRL + M3FDRL + RAMECC monitor x failing data low + register + 0x6C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M3FDRH + M3FDRH + RAMECC monitor x failing data high + register + 0x70 + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M3FECR + M3FECR + RAMECC monitor x failing ECC error code + register + 0x7C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M4CR + M4CR + RAMECC monitor x configuration + register + 0x80 + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M4SR + M4SR + RAMECC monitor x status + register + 0x84 + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M4FAR + M4FAR + RAMECC monitor x failing address + register + 0x88 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M4FDRL + M4FDRL + RAMECC monitor x failing data low + register + 0x8C + 0x20 + read-write + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M4FDRH + M4FDRH + RAMECC monitor x failing data high + register + 0x90 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M4FECR + M4FECR + RAMECC monitor x failing ECC error code + register + M4FDRH + 0x90 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M5CR + M5CR + RAMECC monitor x configuration + register + 0xA0 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5SR + M5SR + RAMECC monitor x status + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FAR + M5FAR + RAMECC monitor x failing address + register + 0xA8 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FDRL + M5FDRL + RAMECC monitor x failing data low + register + 0xAC + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FDRH + M5FDRH + RAMECC monitor x failing data high + register + 0xB0 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FECR + M5FECR + RAMECC monitor x failing ECC error code + register + 0xB4 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + + + RAMECC2 + ECC controller is associated to each RAM + area + RAMECC + 0x48023000 + + 0x0 + 0x400 + registers + + + + IER + IER + RAMECC interrupt enable + register + 0x0 + 0x20 + read-write + 0x00000000 + + + GIE + Global interrupt enable + 0 + 1 + + + GECCSEIE_ + Global ECC single error interrupt + enable + 1 + 1 + + + GECCDEIE + Global ECC double error interrupt + enable + 2 + 1 + + + GECCDEBWIE + Global ECC double error on byte write + (BW) interrupt enable + 3 + 1 + + + + + M1CR + M1CR + RAMECC monitor x configuration + register + 0x20 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M2CR + M2CR + RAMECC monitor x configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M3CR + M3CR + RAMECC monitor x configuration + register + 0x60 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M4CR + M4CR + RAMECC monitor x configuration + register + 0x80 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M5CR + M5CR + RAMECC monitor x configuration + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1SR + M1SR + RAMECC monitor x status + register + 0x24 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2SR + M2SR + RAMECC monitor x status + register + 0x44 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M3SR + M3SR + RAMECC monitor x status + register + 0x64 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M4SR + M4SR + RAMECC monitor x status + register + 0x84 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M5SR + M5SR + RAMECC monitor x status + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M1FAR + M1FAR + RAMECC monitor x failing address + register + 0x28 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M2FAR + M2FAR + RAMECC monitor x failing address + register + 0x48 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M3FAR + M3FAR + RAMECC monitor x failing address + register + 0x68 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M4FAR + M4FAR + RAMECC monitor x failing address + register + 0x88 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M5FAR + M5FAR + RAMECC monitor x failing address + register + 0xA8 + 0x20 + read-write + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M1FDRL + M1FDRL + RAMECC monitor x failing data low + register + 0x2C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M2FDRL + M2FDRL + RAMECC monitor x failing data low + register + 0x4C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M3FDRL + M3FDRL + RAMECC monitor x failing data low + register + 0x6C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M4FDRL + M4FDRL + RAMECC monitor x failing data low + register + 0x8C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M5FDRL + M5FDRL + RAMECC monitor x failing data low + register + 0xAC + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M1FDRH + M1FDRH + RAMECC monitor x failing data high + register + 0x30 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M2FDRH + M2FDRH + RAMECC monitor x failing data high + register + 0x50 + 0x20 + read-write + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M3FDRH + M3FDRH + RAMECC monitor x failing data high + register + 0x70 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M4FDRH + M4FDRH + RAMECC monitor x failing data high + register + 0x90 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M5FDRH + M5FDRH + RAMECC monitor x failing data high + register + 0xB0 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M1FECR + M1FECR + RAMECC monitor x failing ECC error code + register + 0x34 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M2FECR + M2FECR + RAMECC monitor x failing ECC error code + register + 0x58 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M3FECR + M3FECR + RAMECC monitor x failing ECC error code + register + 0x7C + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M4FECR + M4FECR + RAMECC monitor x failing ECC error code + register + M4FDRH + 0x90 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M5FECR + M5FECR + RAMECC monitor x failing ECC error code + register + 0xB4 + 0x20 + read-only + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + + + RAMECC3 + ECC controller is associated to each RAM + area + RAMECC + 0x58027000 + + 0x0 + 0x400 + registers + + + + IER + IER + RAMECC interrupt enable + register + 0x0 + 0x20 + read-write + 0x00000000 + + + GIE + Global interrupt enable + 0 + 1 + + + GECCSEIE_ + Global ECC single error interrupt + enable + 1 + 1 + + + GECCDEIE + Global ECC double error interrupt + enable + 2 + 1 + + + GECCDEBWIE + Global ECC double error on byte write + (BW) interrupt enable + 3 + 1 + + + + + M1CR + M1CR + RAMECC monitor x configuration + register + 0x20 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M2CR + M2CR + RAMECC monitor x configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + ECCSEIE + ECC single error interrupt + enable + 2 + 1 + + + ECCDEIE + ECC double error interrupt + enable + 3 + 1 + + + ECCDEBWIE + ECC double error on byte write (BW) + interrupt enable + 4 + 1 + + + ECCELEN + ECC error latching enable + 5 + 1 + + + + + M1SR + M1SR + RAMECC monitor x status + register + 0x24 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M2SR + M2SR + RAMECC monitor x status + register + 0x44 + 0x20 + read-write + 0x00000000 + + + SEDCF + ECC single error detected and corrected + flag + 0 + 1 + + + DEDF + ECC double error detected + flag + 1 + 1 + + + DEBWDF + ECC double error on byte write (BW) + detected flag + 2 + 1 + + + + + M1FAR + M1FAR + RAMECC monitor x failing address + register + 0x28 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M2FAR + M2FAR + RAMECC monitor x failing address + register + 0x48 + 0x20 + read-only + 0x00000000 + + + FADD + ECC error failing address + 0 + 32 + + + + + M1FDRL + M1FDRL + RAMECC monitor x failing data low + register + 0x2C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M2FDRL + M2FDRL + RAMECC monitor x failing data low + register + 0x4C + 0x20 + read-only + 0x00000000 + + + FDATAL + Failing data low + 0 + 32 + + + + + M1FDRH + M1FDRH + RAMECC monitor x failing data high + register + 0x30 + 0x20 + read-only + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M2FDRH + M2FDRH + RAMECC monitor x failing data high + register + 0x50 + 0x20 + read-write + 0x00000000 + + + FDATAH + Failing data high (64-bit + memory) + 0 + 32 + + + + + M1FECR + M1FECR + RAMECC monitor x failing ECC error code + register + 0x34 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + M2FECR + M2FECR + RAMECC monitor x failing ECC error code + register + 0x58 + 0x20 + read-write + 0x00000000 + + + FEC + Failing error code + 0 + 32 + + + + + + + ART + accelerator - control register + (ART_CTR) + ART + 0x40024400 + + 0x0 + 0x400 + registers + + + + CTR + CTR + control register + 0x0 + 0x20 + read-write + 0x00000004 + + + EN + Cache enable + 0 + 1 + + + PCACHEADDR + Cacheable page index + 8 + 12 + + + + + + + diff --git a/svd/nrf52833.svd b/svd/nrf52833.svd new file mode 100644 index 000000000..6b217ca14 --- /dev/null +++ b/svd/nrf52833.svd @@ -0,0 +1,54114 @@ + + + + Nordic Semiconductor + Nordic + nrf52833 + nrf52 + 1 + nRF52833 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA\n +\n +All rights reserved.\n +\n +Redistribution and use in source and binary forms, with or without modification,\n +are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form, except as embedded into a Nordic\n + Semiconductor ASA integrated circuit in a product or a software update for\n + such product, must reproduce the above copyright notice, this list of\n + conditions and the following disclaimer in the documentation and/or other\n + materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +4. This software, with or without modification, must only be used with a\n + Nordic Semiconductor ASA integrated circuit.\n +\n +5. Any software provided in binary form under this license must not be reverse\n + engineered, decompiled, modified and/or disassembled.\n +\n +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS\n +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE\n +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\n +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM4 + r0p1 + little + 1 + 1 + 3 + 0 + + system_nrf52833 + NRF_ + + 2048 + 2048 + 112 + + + + FICR + Factory information configuration registers + 0x10000000 + + 0 + 0x1000 + registers + + FICR + 0x20 + + + CODEPAGESIZE + Code memory page size + 0x010 + read-only + 0xFFFFFFFF + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + + + CODESIZE + Code memory size + 0x014 + read-only + 0xFFFFFFFF + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x060 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption root, word n + 0x080 + read-only + 0xFFFFFFFF + + + ER + Encryption root, word n + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity Root, word n + 0x090 + read-only + 0xFFFFFFFF + + + IR + Identity Root, word n + 0 + 31 + + + + + DEVICEADDRTYPE + Device address type + 0x0A0 + read-only + 0xFFFFFFFF + + + DEVICEADDRTYPE + Device address type + 0 + 0 + + + Public + Public address + 0 + + + Random + Random address + 1 + + + + + + + 0x2 + 0x4 + DEVICEADDR[%s] + Description collection: Device address n + 0x0A4 + read-only + 0xFFFFFFFF + + + DEVICEADDR + 48 bit device address + 0 + 31 + + + + + INFO + Device info + FICR_INFO + read-only + 0x100 + + PART + Part code + 0x000 + read-only + 0x00052833 + + + PART + Part code + 0 + 31 + + + N52820 + nRF52820 + 0x52820 + + + N52833 + nRF52833 + 0x52833 + + + N52840 + nRF52840 + 0x52840 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Build code (hardware version and production configuration) + 0x004 + read-only + 0xFFFFFFFF + + + VARIANT + Build code (hardware version and production configuration). Encoded as ASCII. + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + AAAB + AAAB + 0x41414142 + + + AAA0 + AAA0 + 0x41414130 + + + AAA1 + AAA1 + 0x41414131 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x008 + read-only + 0xFFFFFFFF + + + PACKAGE + Package option + 0 + 31 + + + QD + QDxx - 5x5 40-pin QFN + 0x2007 + + + QI + QIxx - 7x7 73-pin aQFN + 0x2004 + + + CJ + CJxx - 3.175 x 3.175 WLCSP + 0x2008 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x00C + read-only + 0xFFFFFFFF + + + RAM + RAM variant + 0 + 31 + + + K16 + 16 kByte RAM + 0x10 + + + K32 + 32 kByte RAM + 0x20 + + + K64 + 64 kByte RAM + 0x40 + + + K128 + 128 kByte RAM + 0x80 + + + K256 + 256 kByte RAM + 0x100 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x010 + read-only + 0xFFFFFFFF + + + FLASH + Flash variant + 0 + 31 + + + K128 + 128 kByte FLASH + 0x80 + + + K256 + 256 kByte FLASH + 0x100 + + + K512 + 512 kByte FLASH + 0x200 + + + K1024 + 1 MByte FLASH + 0x400 + + + K2048 + 2 MByte FLASH + 0x800 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + + 0x3 + 0x4 + PRODTEST[%s] + Description collection: Production test signature n + 0x350 + read-only + 0xFFFFFFFF + + + PRODTEST + Production test signature n + 0 + 31 + + + Done + Production tests done + 0xBB42319F + + + NotDone + Production tests not done + 0xFFFFFFFF + + + + + + + TEMP + Registers storing factory TEMP module linearization coefficients + FICR_TEMP + read-only + 0x404 + + A0 + Slope definition A0 + 0x000 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A1 + Slope definition A1 + 0x004 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A2 + Slope definition A2 + 0x008 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A3 + Slope definition A3 + 0x00C + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A4 + Slope definition A4 + 0x010 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A5 + Slope definition A5 + 0x014 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + B0 + Y-intercept B0 + 0x018 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B1 + Y-intercept B1 + 0x01C + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B2 + Y-intercept B2 + 0x020 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B3 + Y-intercept B3 + 0x024 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B4 + Y-intercept B4 + 0x028 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B5 + Y-intercept B5 + 0x02C + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + T0 + Segment end T0 + 0x030 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T1 + Segment end T1 + 0x034 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T2 + Segment end T2 + 0x038 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T3 + Segment end T3 + 0x03C + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T4 + Segment end T4 + 0x040 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + + NFC + Unspecified + FICR_NFC + read-write + 0x450 + + TAGHEADER0 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x000 + read-only + 0xFFFFFF5F + + + MFGID + Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + 0 + 7 + + + UD1 + Unique identifier byte 1 + 8 + 15 + + + UD2 + Unique identifier byte 2 + 16 + 23 + + + UD3 + Unique identifier byte 3 + 24 + 31 + + + + + TAGHEADER1 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x004 + read-only + 0xFFFFFFFF + + + UD4 + Unique identifier byte 4 + 0 + 7 + + + UD5 + Unique identifier byte 5 + 8 + 15 + + + UD6 + Unique identifier byte 6 + 16 + 23 + + + UD7 + Unique identifier byte 7 + 24 + 31 + + + + + TAGHEADER2 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x008 + read-only + 0xFFFFFFFF + + + UD8 + Unique identifier byte 8 + 0 + 7 + + + UD9 + Unique identifier byte 9 + 8 + 15 + + + UD10 + Unique identifier byte 10 + 16 + 23 + + + UD11 + Unique identifier byte 11 + 24 + 31 + + + + + TAGHEADER3 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x00C + read-only + 0xFFFFFFFF + + + UD12 + Unique identifier byte 12 + 0 + 7 + + + UD13 + Unique identifier byte 13 + 8 + 15 + + + UD14 + Unique identifier byte 14 + 16 + 23 + + + UD15 + Unique identifier byte 15 + 24 + 31 + + + + + + + + UICR + User information configuration registers + 0x10001000 + + 0 + 0x1000 + registers + + UICR + 0x20 + + + 0xD + 0x4 + NRFFW[%s] + Description collection: Reserved for Nordic firmware design + 0x014 + read-write + 0xFFFFFFFF + + + NRFFW + Reserved for Nordic firmware design + 0 + 31 + + + + + 0xC + 0x4 + NRFHW[%s] + Description collection: Reserved for Nordic hardware design + 0x050 + read-write + 0xFFFFFFFF + + + NRFHW + Reserved for Nordic hardware design + 0 + 31 + + + + + 0x20 + 0x4 + CUSTOMER[%s] + Description collection: Reserved for customer + 0x080 + read-write + 0xFFFFFFFF + + + CUSTOMER + Reserved for customer + 0 + 31 + + + + + 0x2 + 0x4 + PSELRESET[%s] + Description collection: Mapping of the nRESET function (see POWER chapter for details) + 0x200 + read-write + 0xFFFFFFFF + + + PIN + GPIO pin number onto which nRESET is exposed + 0 + 4 + + + PORT + Port number onto which nRESET is exposed + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + APPROTECT + Access port protection + 0x208 + read-write + 0xFFFFFFFF + + + PALL + Enable or disable access port protection. + 0 + 7 + + + Disabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware + 0xFF + + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + + + Enabled + Enable + 0x00 + + + + + + + NFCPINS + Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + 0x20C + read-write + 0xFFFFFFFF + + + PROTECT + Setting of pins dedicated to NFC functionality + 0 + 0 + + + Disabled + Operation as GPIO pins. Same protection as normal GPIO pins. + 0 + + + NFC + Operation as NFC antenna pins. Configures the protection for NFC operation. + 1 + + + + + + + DEBUGCTRL + Processor debug control + 0x210 + read-write + 0xFFFFFFFF + + + CPUNIDEN + Configure CPU non-intrusive debug features + 0 + 7 + + + Enabled + Enable CPU ITM and ETM functionality (default behavior) + 0xFF + + + Disabled + Disable CPU ITM and ETM functionality + 0x00 + + + + + CPUFPBEN + Configure CPU flash patch and breakpoint (FPB) unit behavior + 8 + 15 + + + Enabled + Enable CPU FPB unit (default behavior) + 0xFF + + + Disabled + Disable CPU FPB unit. Writes into the FPB registers will be ignored. + 0x00 + + + + + + + REGOUT0 + Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. + 0x304 + read-write + 0xFFFFFFFF + + + VOUT + Output voltage from REG0 regulator stage. + 0 + 2 + + + 1V8 + 1.8 V + 0 + + + 2V1 + 2.1 V + 1 + + + 2V4 + 2.4 V + 2 + + + 2V7 + 2.7 V + 3 + + + 3V0 + 3.0 V + 4 + + + 3V3 + 3.3 V + 5 + + + DEFAULT + Default voltage: 1.8 V + 7 + + + + + + + + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + + + CLOCK + Clock control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFXO crystal oscillator + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFXO crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFXO crystal oscillator + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFXO crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CAL + Start calibration of LFRC + 0x010 + write-only + + + TASKS_CAL + Start calibration of LFRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTART + Start calibration timer + 0x014 + write-only + + + TASKS_CTSTART + Start calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTOP + Stop calibration timer + 0x018 + write-only + + + TASKS_CTSTOP + Stop calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFXO crystal oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFXO crystal oscillator started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + Calibration of LFRC completed + 0x10C + read-write + + + EVENTS_DONE + Calibration of LFRC completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTTO + Calibration timer timeout + 0x110 + read-write + + + EVENTS_CTTO + Calibration timer timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTSTARTED + Calibration timer has been started and is ready to process new tasks + 0x128 + read-write + + + EVENTS_CTSTARTED + Calibration timer has been started and is ready to process new tasks + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTSTOPPED + Calibration timer has been stopped and is ready to process new tasks + 0x12C + read-write + + + EVENTS_CTSTOPPED + Calibration timer has been stopped and is ready to process new tasks + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTTO + Write '1' to enable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTARTED + Write '1' to enable interrupt for event CTSTARTED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTOPPED + Write '1' to enable interrupt for event CTSTOPPED + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTTO + Write '1' to disable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTSTARTED + Write '1' to disable interrupt for event CTSTARTED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTSTOPPED + Write '1' to disable interrupt for event CTSTOPPED + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + HFCLK status + 0x40C + read-only + + + SRC + Source of HFCLK + 0 + 0 + + + RC + 64 MHz internal oscillator (HFINT) + 0 + + + Xtal + 64 MHz crystal oscillator (HFXO) + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + LFCLK status + 0x418 + read-only + + + SRC + Source of LFCLK + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK + 0x518 + read-write + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 16 + 16 + + + Disabled + Disable (use with Xtal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + EXTERNAL + Enable or disable external source for LFCLK + 17 + 17 + + + Disabled + Disable external source (use with Xtal) + 0 + + + Enabled + Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + 1 + + + + + + + HFXODEBOUNCE + HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. + 0x528 + read-write + 0x00000010 + + + HFXODEBOUNCE + HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. + 0 + 7 + + + Db256us + 256 us debounce time. Recommended for 1.6 mm x 2.0 mm crystals and larger. + 0x10 + + + Db1024us + 1024 us debounce time. Recommended for 1.6 mm x 1.2 mm crystals and smaller. + 0x40 + + + + + + + LFXODEBOUNCE + LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the LFCLKSRC register is configured for Xtal. + 0x52C + read-write + 0x00000000 + + + LFXODEBOUNCE + LFXO debounce time. + 0 + 0 + + + Normal + 8192 32.768 kHz periods, or 0.25 s. Recommended for normal Operating Temperature conditions. + 0 + + + Extended + 16384 32.768 kHz periods, or 0.5 s. Recommended for Extended Operating Temperature conditions. + 1 + + + + + + + CTIV + Calibration timer interval + 0x538 + read-write + + + CTIV + Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + 0 + 6 + + + + + TRACECONFIG + Clocking options for the trace port debug interface + 0x55C + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. + 0 + 1 + + + 32MHz + 32 MHz trace port clock (TRACECLK = 16 MHz) + 0 + + + 16MHz + 16 MHz trace port clock (TRACECLK = 8 MHz) + 1 + + + 8MHz + 8 MHz trace port clock (TRACECLK = 4 MHz) + 2 + + + 4MHz + 4 MHz trace port clock (TRACECLK = 2 MHz) + 3 + + + + + TRACEMUX + Pin multiplexing of trace signals. See pin assignment chapter for more details. + 16 + 17 + + + GPIO + No trace signals routed to pins. All pins can be used as regular GPIOs. + 0 + + + Serial + SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. + 1 + + + Parallel + All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. + 2 + + + + + + + + + POWER + Power control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0x78 + write-only + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0x7C + write-only + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0x11C + read-write + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0x120 + read-write + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0x124 + read-write + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBDETECTED + Write '1' to enable interrupt for event USBDETECTED + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBREMOVED + Write '1' to enable interrupt for event USBREMOVED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBPWRRDY + Write '1' to enable interrupt for event USBPWRRDY + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBDETECTED + Write '1' to disable interrupt for event USBDETECTED + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBREMOVED + Write '1' to disable interrupt for event USBREMOVED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBPWRRDY + Write '1' to disable interrupt for event USBPWRRDY + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin-reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG + Reset from watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from soft reset detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from CPU lock-up detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LPCOMP + Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP + 17 + 17 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + NFC + Reset due to wake up from System OFF mode by NFC field detect + 19 + 19 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + VBUS + Reset due to wake up from System OFF mode by VBUS rising into valid range + 20 + 20 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + RAMSTATUS + Deprecated register - RAM status register + 0x428 + read-only + 0x00000000 + + + RAMBLOCK0 + RAM block 0 is on or off/powering up + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK1 + RAM block 1 is on or off/powering up + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK2 + RAM block 2 is on or off/powering up + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK3 + RAM block 3 is on or off/powering up + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + USBREGSTATUS + USB supply status + 0x438 + read-only + 0x00000000 + + + VBUSDETECT + VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) + 0 + 0 + + + NoVbus + VBUS voltage below valid threshold + 0 + + + VbusPresent + VBUS voltage above valid threshold + 1 + + + + + OUTPUTRDY + USB supply output settling time elapsed + 1 + 1 + + + NotReady + USBREG output settling time not elapsed + 0 + + + Ready + USBREG output settling time elapsed (same information as USBPWRRDY event) + 1 + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 1 + + + + + + + POFCON + Power-fail comparator configuration + 0x510 + read-write + + + POF + Enable or disable power failure warning + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + THRESHOLD + Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. + 1 + 4 + + + V17 + Set threshold to 1.7 V + 4 + + + V18 + Set threshold to 1.8 V + 5 + + + V19 + Set threshold to 1.9 V + 6 + + + V20 + Set threshold to 2.0 V + 7 + + + V21 + Set threshold to 2.1 V + 8 + + + V22 + Set threshold to 2.2 V + 9 + + + V23 + Set threshold to 2.3 V + 10 + + + V24 + Set threshold to 2.4 V + 11 + + + V25 + Set threshold to 2.5 V + 12 + + + V26 + Set threshold to 2.6 V + 13 + + + V27 + Set threshold to 2.7 V + 14 + + + V28 + Set threshold to 2.8 V + 15 + + + + + THRESHOLDVDDH + Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). + 8 + 11 + + + V27 + Set threshold to 2.7 V + 0 + + + V28 + Set threshold to 2.8 V + 1 + + + V29 + Set threshold to 2.9 V + 2 + + + V30 + Set threshold to 3.0 V + 3 + + + V31 + Set threshold to 3.1 V + 4 + + + V32 + Set threshold to 3.2 V + 5 + + + V33 + Set threshold to 3.3 V + 6 + + + V34 + Set threshold to 3.4 V + 7 + + + V35 + Set threshold to 3.5 V + 8 + + + V36 + Set threshold to 3.6 V + 9 + + + V37 + Set threshold to 3.7 V + 10 + + + V38 + Set threshold to 3.8 V + 11 + + + V39 + Set threshold to 3.9 V + 12 + + + V40 + Set threshold to 4.0 V + 13 + + + V41 + Set threshold to 4.1 V + 14 + + + V42 + Set threshold to 4.2 V + 15 + + + + + + + GPREGRET + General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + GPREGRET2 + General purpose retention register + 0x520 + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + DCDCEN + Enable DC/DC converter for REG1 stage + 0x578 + read-write + + + DCDCEN + Enable DC/DC converter for REG1 stage. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + MAINREGSTATUS + Main supply status + 0x640 + read-only + 0x00000000 + + + MAINREGSTATUS + Main supply status + 0 + 0 + + + Normal + Normal voltage mode. Voltage supplied on VDD. + 0 + + + High + High voltage mode. Voltage supplied on VDDH. + 1 + + + + + + + 9 + 0x010 + RAM[%s] + Unspecified + POWER_RAM + read-write + 0x900 + + POWER + Description cluster: RAMn power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 on or off in System ON mode. + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 on or off in System ON mode. + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 on or off in System ON mode. + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 on or off in System ON mode. + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 on or off in System ON mode. + 4 + 4 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 on or off in System ON mode. + 5 + 5 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 on or off in System ON mode. + 6 + 6 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 on or off in System ON mode. + 7 + 7 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 on or off in System ON mode. + 8 + 8 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 on or off in System ON mode. + 9 + 9 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 on or off in System ON mode. + 10 + 10 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 on or off in System ON mode. + 11 + 11 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 on or off in System ON mode. + 12 + 12 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 on or off in System ON mode. + 13 + 13 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 on or off in System ON mode. + 14 + 14 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 on or off in System ON mode. + 15 + 15 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is off + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is off + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 when RAM section is off + 18 + 18 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 when RAM section is off + 19 + 19 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 when RAM section is off + 20 + 20 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 when RAM section is off + 21 + 21 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 when RAM section is off + 22 + 22 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 when RAM section is off + 23 + 23 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 when RAM section is off + 24 + 24 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 when RAM section is off + 25 + 25 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 when RAM section is off + 26 + 26 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 when RAM section is off + 27 + 27 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 when RAM section is off + 28 + 28 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 when RAM section is off + 29 + 29 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 when RAM section is off + 30 + 30 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 when RAM section is off + 31 + 31 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAMn power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAMn on or off in System ON mode + 2 + 2 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAMn on or off in System ON mode + 3 + 3 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 of RAMn on or off in System ON mode + 4 + 4 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 of RAMn on or off in System ON mode + 5 + 5 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 of RAMn on or off in System ON mode + 6 + 6 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 of RAMn on or off in System ON mode + 7 + 7 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 of RAMn on or off in System ON mode + 8 + 8 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 of RAMn on or off in System ON mode + 9 + 9 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 of RAMn on or off in System ON mode + 10 + 10 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 of RAMn on or off in System ON mode + 11 + 11 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 of RAMn on or off in System ON mode + 12 + 12 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 of RAMn on or off in System ON mode + 13 + 13 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 of RAMn on or off in System ON mode + 14 + 14 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 of RAMn on or off in System ON mode + 15 + 15 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 when RAM section is switched off + 18 + 18 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 when RAM section is switched off + 19 + 19 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 when RAM section is switched off + 20 + 20 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 when RAM section is switched off + 21 + 21 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 when RAM section is switched off + 22 + 22 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 when RAM section is switched off + 23 + 23 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 when RAM section is switched off + 24 + 24 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 when RAM section is switched off + 25 + 25 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 when RAM section is switched off + 26 + 26 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 when RAM section is switched off + 27 + 27 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 when RAM section is switched off + 28 + 28 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 when RAM section is switched off + 29 + 29 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 when RAM section is switched off + 30 + 30 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 when RAM section is switched off + 31 + 31 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAMn power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S2POWER + Keep RAM section S2 of RAMn on or off in System ON mode + 2 + 2 + + + Off + Off + 1 + + + + + S3POWER + Keep RAM section S3 of RAMn on or off in System ON mode + 3 + 3 + + + Off + Off + 1 + + + + + S4POWER + Keep RAM section S4 of RAMn on or off in System ON mode + 4 + 4 + + + Off + Off + 1 + + + + + S5POWER + Keep RAM section S5 of RAMn on or off in System ON mode + 5 + 5 + + + Off + Off + 1 + + + + + S6POWER + Keep RAM section S6 of RAMn on or off in System ON mode + 6 + 6 + + + Off + Off + 1 + + + + + S7POWER + Keep RAM section S7 of RAMn on or off in System ON mode + 7 + 7 + + + Off + Off + 1 + + + + + S8POWER + Keep RAM section S8 of RAMn on or off in System ON mode + 8 + 8 + + + Off + Off + 1 + + + + + S9POWER + Keep RAM section S9 of RAMn on or off in System ON mode + 9 + 9 + + + Off + Off + 1 + + + + + S10POWER + Keep RAM section S10 of RAMn on or off in System ON mode + 10 + 10 + + + Off + Off + 1 + + + + + S11POWER + Keep RAM section S11 of RAMn on or off in System ON mode + 11 + 11 + + + Off + Off + 1 + + + + + S12POWER + Keep RAM section S12 of RAMn on or off in System ON mode + 12 + 12 + + + Off + Off + 1 + + + + + S13POWER + Keep RAM section S13 of RAMn on or off in System ON mode + 13 + 13 + + + Off + Off + 1 + + + + + S14POWER + Keep RAM section S14 of RAMn on or off in System ON mode + 14 + 14 + + + Off + Off + 1 + + + + + S15POWER + Keep RAM section S15 of RAMn on or off in System ON mode + 15 + 15 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 when RAM section is switched off + 18 + 18 + + + Off + Off + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 when RAM section is switched off + 19 + 19 + + + Off + Off + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 when RAM section is switched off + 20 + 20 + + + Off + Off + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 when RAM section is switched off + 21 + 21 + + + Off + Off + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 when RAM section is switched off + 22 + 22 + + + Off + Off + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 when RAM section is switched off + 23 + 23 + + + Off + Off + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 when RAM section is switched off + 24 + 24 + + + Off + Off + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 when RAM section is switched off + 25 + 25 + + + Off + Off + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 when RAM section is switched off + 26 + 26 + + + Off + Off + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 when RAM section is switched off + 27 + 27 + + + Off + Off + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 when RAM section is switched off + 28 + 28 + + + Off + Off + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 when RAM section is switched off + 29 + 29 + + + Off + Off + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 when RAM section is switched off + 30 + 30 + + + Off + Off + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 when RAM section is switched off + 31 + 31 + + + Off + Off + 1 + + + + + + + + + + P0 + GPIO Port 1 + 0x50000000 + GPIO + + 0 + 0x1000 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x504 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x508 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x50C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x510 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x514 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x518 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x51C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 + read-write + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0x524 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x700 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + + + + + P1 + GPIO Port 2 + 0x50000300 + P0 + + + RADIO + 2.4 GHz radio + 0x40001000 + + 0 + 0x1000 + registers + + + RADIO + 1 + + RADIO + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + + + TASKS_TXEN + Enable RADIO in TX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + + + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_START + Start RADIO + 0x008 + write-only + + + TASKS_START + Start RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + + + TASKS_STOP + Stop RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + + + TASKS_DISABLE + Disable RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 + write-only + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTART + Start the bit counter + 0x01C + write-only + + + TASKS_BCSTART + Start the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only + + + TASKS_BCSTOP + Stop the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0x024 + write-only + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTOP + Stop the energy detect measurement + 0x028 + write-only + + + TASKS_EDSTOP + Stop the energy detect measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x02C + write-only + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTOP + Stop the clear channel assessment + 0x030 + write-only + + + TASKS_CCASTOP + Stop the clear channel assessment + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 + read-write + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ADDRESS + Address sent or received + 0x104 + read-write + + + EVENTS_ADDRESS + Address sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 + read-write + + + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + + + EVENTS_END + Packet sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + + + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 + read-write + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0x11C + read-write + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x128 + read-write + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + + + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x138 + read-write + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0x13C + read-write + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x140 + read-write + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x144 + read-write + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x148 + read-write + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCASTOPPED + The CCA has stopped + 0x14C + read-write + + + EVENTS_CCASTOPPED + The CCA has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0x150 + read-write + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x154 + read-write + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x158 + read-write + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_MHRMATCH + MAC header match found + 0x15C + read-write + + + EVENTS_MHRMATCH + MAC header match found + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SYNC + Preamble indicator + 0x168 + read-write + + + EVENTS_SYNC + Preamble indicator + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PHYEND + Generated when last bit is sent on air, or received from air + 0x16C + read-write + + + EVENTS_PHYEND + Generated when last bit is sent on air, or received from air + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTEPRESENT + CTE is present (early warning right after receiving CTEInfo byte) + 0x170 + read-write + + + EVENTS_CTEPRESENT + CTE is present (early warning right after receiving CTEInfo byte) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_START + Shortcut between event READY and task START + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_DISABLE + Shortcut between event END and task DISABLE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_EDSTART + Shortcut between event READY and task EDSTART + 15 + 15 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 16 + 16 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXREADY_START + Shortcut between event TXREADY and task START + 18 + 18 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_START + Shortcut between event RXREADY and task START + 19 + 19 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 20 + 20 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_START + Shortcut between event PHYEND and task START + 21 + 21 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RSSIEND + Write '1' to enable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SYNC + Write '1' to enable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTEPRESENT + Write '1' to enable interrupt for event CTEPRESENT + 28 + 28 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SYNC + Write '1' to disable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTEPRESENT + Write '1' to disable interrupt for event CTEPRESENT + 28 + 28 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CRCSTATUS + CRC status + 0x400 + read-only + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0 + + + CRCOk + Packet received with CRC ok + 1 + + + + + + + RXMATCH + Received address + 0x408 + read-only + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + + + DAI + Device address match index + 0 + 2 + + + + + PDUSTAT + Payload status + 0x414 + read-only + + + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN + 0 + 0 + + + LessThan + Payload less than PCNF1.MAXLEN + 0 + + + GreaterThan + Payload greater than PCNF1.MAXLEN + 1 + + + + + CISTAT + Status on what rate packet is received with in Long Range + 1 + 2 + + + LR125kbit + Frame is received at 125 kbps + 0 + + + LR500kbit + Frame is received at 500 kbps + 1 + + + + + + + CTESTATUS + CTEInfo parsed from received packet + 0x44C + read-only + + + CTETIME + CTETime parsed from packet + 0 + 4 + + + RFU + RFU parsed from packet + 5 + 5 + + + CTETYPE + CTEType parsed from packet + 6 + 7 + + + + + DFESTATUS + DFE status information + 0x458 + read-only + + + SWITCHINGSTATE + Internal state of switching state machine + 0 + 2 + + + Idle + Switching state Idle + 0 + + + Offset + Switching state Offset + 1 + + + Guard + Switching state Guard + 2 + + + Ref + Switching state Ref + 3 + + + Switching + Switching state Switching + 4 + + + Ending + Switching state Ending + 5 + + + + + SAMPLINGSTATE + Internal state of sampling state machine + 4 + 4 + + + Idle + Sampling state Idle + 0 + + + Sampling + Sampling state Sampling + 1 + + + + + + + PACKETPTR + Packet pointer + 0x504 + read-write + 0x00000000 + + + PACKETPTR + Packet pointer + 0 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection + 8 + 8 + + + Default + Channel map between 2400 MHZ .. 2500 MHz + 0 + + + Low + Channel map between 2360 MHZ .. 2460 MHz + 1 + + + + + + + TXPOWER + Output power + 0x50C + read-write + + + TXPOWER + RADIO output power + 0 + 7 + + + Pos8dBm + +8 dBm + 0x8 + + + Pos7dBm + +7 dBm + 0x7 + + + Pos6dBm + +6 dBm + 0x6 + + + Pos5dBm + +5 dBm + 0x5 + + + Pos4dBm + +4 dBm + 0x4 + + + Pos3dBm + +3 dBm + 0x3 + + + Pos2dBm + +2 dBm + 0x2 + + + 0dBm + 0 dBm + 0x0 + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + Deprecated enumerator - -40 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 + + + + + + + MODE + Data rate and modulation + 0x510 + read-write + + + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbps Nordic proprietary radio mode + 0 + + + Nrf_2Mbit + 2 Mbps Nordic proprietary radio mode + 1 + + + Ble_1Mbit + 1 Mbps BLE + 3 + + + Ble_2Mbit + 2 Mbps BLE + 4 + + + Ble_LR125Kbit + Long range 125 kbps TX, 125 kbps and 500 kbps RX + 5 + + + Ble_LR500Kbit + Long range 500 kbps TX, 125 kbps and 500 kbps RX + 6 + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbps + 15 + + + + + + + PCNF0 + Packet configuration register 0 + 0x514 + read-write + + + LFLEN + Length on air of LENGTH field in number of bits + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0 + + + Include + Always include S1 field in RAM independent of S1LEN + 1 + + + + + CILEN + Length of code indicator - long range + 22 + 23 + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0 + + + 16bit + 16-bit preamble + 1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 2 + + + LongRange + Preamble - used for BLE long range + 3 + + + + + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0 + + + Include + LENGTH includes CRC + 1 + + + + + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 + + + + + PCNF1 + Packet configuration register 1 + 0x518 + read-write + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + BASE0 + Base address 0 + 0x51C + read-write + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0x520 + read-write + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 + read-write + + + AP0 + Address prefix 0. + 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 + read-write + + + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CRCCNF + CRC configuration + 0x534 + read-write + + + LEN + CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0 + + + One + CRC length is one byte and CRC calculation is enabled + 1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 3 + + + + + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 9 + + + Include + CRC calculation includes address field + 0 + + + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 1 + + + Ieee802154 + CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + 2 + + + + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Interframe spacing in us + 0x544 + read-write + + + TIFS + Interframe spacing in us. + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + + + RSSISAMPLE + RSSI sample. + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the Disabled state + 0 + + + RxRu + RADIO is in the RXRU state + 1 + + + RxIdle + RADIO is in the RXIDLE state + 2 + + + Rx + RADIO is in the RX state + 3 + + + RxDisable + RADIO is in the RXDISABLED state + 4 + + + TxRu + RADIO is in the TXRU state + 9 + + + TxIdle + RADIO is in the TXIDLE state + 10 + + + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 + + + + + + + DATAWHITEIV + Data whitening initial value + 0x554 + read-write + 0x00000040 + + + DATAWHITEIV + Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MHRMATCHCONF + Search pattern configuration + 0x644 + read-write + + + MHRMATCHCONF + Search pattern configuration + 0 + 31 + + + + + MHRMATCHMAS + Pattern mask + 0x648 + read-write + + + MHRMATCHMAS + Pattern mask + 0 + 31 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + + + Default + Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 + 0 + + + Fast + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information + 1 + + + + + DTX + Default TX value + 8 + 9 + + + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' + 1 + + + Center + Transmit center frequency + 2 + + + + + + + SFD + IEEE 802.15.4 start of frame delimiter + 0x660 + read-write + 0x000000A7 + + + SFD + IEEE 802.15.4 start of frame delimiter + 0 + 7 + + + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0x664 + read-write + 0x00000000 + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0 + 20 + + + + + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x668 + read-only + 0x00000000 + + + EDLVL + IEEE 802.15.4 energy detect level + 0 + 7 + + + + + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x66C + read-write + 0x052D0000 + + + CCAMODE + CCA mode of operation + 0 + 2 + + + EdMode + Energy above threshold + 0 + + + CarrierMode + Carrier seen + 1 + + + CarrierAndEdMode + Energy above threshold AND carrier seen + 2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 4 + + + + + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 + + + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. + 16 + 23 + + + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 + + + + + DFEMODE + Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) + 0x900 + read-write + 0x00000000 + + + DFEOPMODE + Direction finding operation mode + 0 + 1 + + + Disabled + Direction finding mode disabled + 0 + + + AoD + Direction finding mode set to AoD + 2 + + + AoA + Direction finding mode set to AoA + 3 + + + + + + + CTEINLINECONF + Configuration for CTE inline mode + 0x904 + read-write + 0x00002800 + + + CTEINLINECTRLEN + Enable parsing of CTEInfo from received packet in BLE modes + 0 + 0 + + + Enabled + Parsing of CTEInfo is enabled + 1 + + + Disabled + Parsing of CTEInfo is disabled + 0 + + + + + CTEINFOINS1 + CTEInfo is S1 byte or not + 3 + 3 + + + InS1 + CTEInfo is in S1 byte (data PDU) + 1 + + + NotInS1 + CTEInfo is NOT in S1 byte (advertising PDU) + 0 + + + + + CTEERRORHANDLING + Sampling/switching if CRC is not OK + 4 + 4 + + + Yes + Sampling and antenna switching also when CRC is not OK + 1 + + + No + No sampling and antenna switching when CRC is not OK + 0 + + + + + CTETIMEVALIDRANGE + Max range of CTETime + 6 + 7 + + + 20 + 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 + 0 + + + 31 + 31 in 8 us unit + 1 + + + 63 + 63 in 8 us unit + 2 + + + + + CTEINLINERXMODE1US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. + 10 + 12 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + CTEINLINERXMODE2US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. + 13 + 15 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + S0CONF + S0 bit pattern to match + 16 + 23 + + + S0MASK + S0 bit mask to set which bit to match + 24 + 31 + + + + + DFECTRL1 + Various configuration for Direction finding + 0x910 + read-write + 0x00023282 + + + NUMBEROF8US + Length of the AoA/AoD procedure in number of 8 us units + 0 + 5 + + + DFEINEXTENSION + Add CTE extension and do antenna switching/sampling in this extension + 7 + 7 + + + CRC + AoA/AoD procedure triggered at end of CRC + 1 + + + Payload + Antenna switching/sampling is done in the packet payload + 0 + + + + + TSWITCHSPACING + Interval between every time the antenna is changed in the SWITCHING state + 8 + 10 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + + + TSAMPLESPACINGREF + Interval between samples in the REFERENCE period + 12 + 14 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + SAMPLETYPE + Whether to sample I/Q or magnitude/phase + 15 + 15 + + + IQ + Complex samples in I and Q + 0 + + + MagPhase + Complex samples as magnitude and phase + 1 + + + + + TSAMPLESPACING + Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 + 16 + 18 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + REPEATPATTERN + Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. + 20 + 23 + + + NoRepeat + Do not repeat (1 time in total) + 0 + + + + + AGCBACKOFFGAIN + Gain will be lowered by the specified number of gain steps at the start of CTE + 24 + 27 + + + + + DFECTRL2 + Start offset for Direction finding + 0x914 + read-write + 0x00000000 + + + TSWITCHOFFSET + Signed value offset after the end of the CRC before starting switching in number of 16M cycles + 0 + 12 + + + TSAMPLEOFFSET + Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start + 16 + 27 + + + + + SWITCHPATTERN + GPIO patterns to be used for each antenna + 0x928 + read-write + 0x00000000 + + + SWITCHPATTERN + Fill array of GPIO patterns for antenna control. + 0 + 7 + + + + + CLEARPATTERN + Clear the GPIO pattern array for antenna control + 0x92C + read-write + + + CLEARPATTERN + Clears GPIO pattern array for antenna control + 0 + 0 + oneToClear + + + Clear + Clear the GPIO pattern + 1 + + + + + + + PSEL + Unspecified + RADIO_PSEL + read-write + 0x930 + + 0x8 + 0x4 + DFEGPIO[%s] + Description collection: Pin select for DFE pin n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DFEPACKET + DFE packet EasyDMA channel + RADIO_DFEPACKET + read-write + 0x950 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + 0x00001000 + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 13 + + + + + AMOUNT + Number of samples transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of samples transferred in the last transaction + 0 + 15 + + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0 + + + Enabled + Peripheral is powered on + 1 + + + + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UART + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + Suspend UART + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + CTS_STARTRX + Shortcut between event CTS and task STARTRX + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + NCTS_STOPRX + Shortcut between event NCTS and task STOPRX + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UART + 0 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + + + + + + PSEL + Unspecified + UART_PSEL + read-write + 0x508 + + RTS + Pin select for RTS + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + + + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0 + + + Odd + Odd parity + 1 + + + + + + + + + UARTE0 + UART with EasyDMA 0 + 0x40002000 + UART0 + UARTE + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source This register is read/write one to clear. + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0 + + + Odd + Odd parity + 1 + + + + + + + + + SPI0 + Serial Peripheral Interface 0 + 0x40003000 + SPI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPI + 0x20 + + + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 + read-write + + + EVENTS_READY + TXD byte sent and RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPI + 0x500 + read-write + + + ENABLE + Enable or disable SPI + 0 + 3 + + + Disabled + Disable SPI + 0 + + + Enabled + Enable SPI + 1 + + + + + + + PSEL + Unspecified + SPI_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TX data to send. Double buffered. + 0 + 7 + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + + + SPIM0 + Serial Peripheral Interface Master with EasyDMA 0 + 0x40003000 + SPI0 + SPIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STALLSTAT + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. + 0x400 + read-write + 0x00000000 + + + TX + Stall status for EasyDMA RAM reads + 0 + 0 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + RX + Stall status for EasyDMA RAM writes + 1 + 1 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + M16 + 16 Mbps + 0x0A000000 + + + M32 + 32 Mbps + 0x14000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x560 + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions + 0x004 + read-write + 0x00000002 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + 0 + 7 + + + + + + CSNPOL + Polarity of CSN output + 0x568 + read-write + 0x00000000 + + + CSNPOL + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0 + + + HIGH + Active high (idle state low) + 1 + + + + + + + PSELDCX + Pin select for DCX signal + 0x56C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DCXCNT + DCX configuration + 0x570 + read-write + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + + + SPIS0 + SPI Slave 0 + 0x40003000 + SPI0 + SPIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWI0 + I2C compatible Two-Wire Interface 0 + 0x40003000 + SPI0 + TWI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWI + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDREADY + TWI RXD byte received + 0x108 + read-write + + + EVENTS_RXDREADY + TWI RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C + read-write + + + EVENTS_TXDSENT + TWI TXD byte sent + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + BB_SUSPEND + Shortcut between event BB and task SUSPEND + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + BB_STOP + Shortcut between event BB and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDREADY + Write '1' to enable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDSENT + Write '1' to enable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BB + Write '1' to enable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDREADY + Write '1' to disable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDSENT + Write '1' to disable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BB + Write '1' to disable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0 + + + Present + Read: overrun occured + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable TWI + 0x500 + read-write + + + ENABLE + Enable or disable TWI + 0 + 3 + + + Disabled + Disable TWI + 0 + + + Enabled + Enable TWI + 5 + + + + + + + PSEL + Unspecified + TWI_PSEL + read-write + 0x508 + + SCL + Pin select for SCL + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_SUSPEND + Shortcut between event LASTRX and task SUSPEND + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Indication of which address in {ADDRESS} that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + SPI1 + Serial Peripheral Interface 1 + 0x40004000 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIM1 + Serial Peripheral Interface Master with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIS1 + SPI Slave 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWI1 + I2C compatible Two-Wire Interface 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIM1 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIS1 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + NFCT + NFC-A compatible radio + 0x40005000 + + 0 + 0x1000 + registers + + + NFCT + 5 + + NFCT + 0x20 + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0x000 + write-only + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable NFCT peripheral + 0x004 + write-only + + + TASKS_DISABLE + Disable NFCT peripheral + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0x008 + write-only + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0x00C + write-only + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C + write-only + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only + + + TASKS_GOIDLE + Force state machine to IDLE state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 + write-only + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0x100 + read-write + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 + read-write + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 + read-write + + + EVENTS_FIELDLOST + Remote NFC field lost + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C + read-write + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0x148 + read-write + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0x14C + read-write + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 + read-write + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + FIELDDETECTED_ACTIVATE + Shortcut between event FIELDDETECTED and task ACTIVATE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FIELDLOST_SENSE + Shortcut between event FIELDLOST and task SENSE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXFRAMEEND_ENABLERXDATA + Shortcut between event TXFRAMEEND and task ENABLERXDATA + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDDETECTED + Enable or disable interrupt for event FIELDDETECTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDLOST + Enable or disable interrupt for event FIELDLOST + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMESTART + Enable or disable interrupt for event TXFRAMESTART + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMEEND + Enable or disable interrupt for event TXFRAMEEND + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMESTART + Enable or disable interrupt for event RXFRAMESTART + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMEEND + Enable or disable interrupt for event RXFRAMEEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXERROR + Enable or disable interrupt for event RXERROR + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + AUTOCOLRESSTARTED + Enable or disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COLLISION + Enable or disable interrupt for event COLLISION + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SELECTED + Enable or disable interrupt for event SELECTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDDETECTED + Write '1' to enable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDLOST + Write '1' to enable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMESTART + Write '1' to enable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMEEND + Write '1' to enable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMESTART + Write '1' to enable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMEEND + Write '1' to enable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXERROR + Write '1' to enable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to enable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COLLISION + Write '1' to enable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SELECTED + Write '1' to enable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDDETECTED + Write '1' to disable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDLOST + Write '1' to disable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMESTART + Write '1' to disable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMEEND + Write '1' to disable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMESTART + Write '1' to disable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMEEND + Write '1' to disable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXERROR + Write '1' to disable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COLLISION + Write '1' to disable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SELECTED + Write '1' to disable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + oneToClear + + + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + 0 + 0 + + + + + FRAMESTATUS + Unspecified + NFCT_FRAMESTATUS + read-write + 0x40C + + RX + Result of last incoming frame + 0x000 + read-write + oneToClear + + + CRCERROR + No valid end of frame (EoF) detected + 0 + 0 + + + CRCCorrect + Valid CRC detected + 0 + + + CRCError + CRC received does not match local check + 1 + + + + + PARITYSTATUS + Parity status of received frame + 2 + 2 + + + ParityOK + Frame received with parity OK + 0 + + + ParityError + Frame received with parity error + 1 + + + + + OVERRUN + Overrun detected + 3 + 3 + + + NoOverrun + No overrun detected + 0 + + + Overrun + Overrun error + 1 + + + + + + + + NFCTAGSTATE + NfcTag state register + 0x410 + read-only + + + NFCTAGSTATE + NfcTag state + 0 + 2 + + + Disabled + Disabled or sense + 0 + + + RampUp + RampUp + 2 + + + Idle + Idle + 3 + + + Receive + Receive + 4 + + + FrameDelay + FrameDelay + 5 + + + Transmit + Transmit + 6 + + + + + + + SLEEPSTATE + Sleep state during automatic collision resolution + 0x420 + read-only + 0x00000000 + + + SLEEPSTATE + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. + 0 + 0 + + + Idle + State is IDLE. + 0 + + + SleepA + State is SLEEP_A. + 1 + + + + + + + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C + read-only + + + FIELDPRESENT + Indicates if a valid field is present. Available only in the activated state. + 0 + 0 + + + NoField + No valid field detected + 0 + + + FieldPresent + Valid field detected + 1 + + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + + + NotLocked + Not locked to field + 0 + + + Locked + Locked to field + 1 + + + + + + + FRAMEDELAYMIN + Minimum frame delay + 0x504 + read-write + 0x00000480 + + + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clocks + 0 + 15 + + + + + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + + + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clocks + 0 + 19 + + + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C + read-write + 0x00000001 + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0 + 1 + + + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + 0 + + + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + 1 + + + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX + 2 + + + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 3 + + + + + + + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 + read-write + 0x00000000 + + + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. + 0 + 31 + + + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0x514 + read-write + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0 + 8 + + + + + TXD + Unspecified + NFCT_TXD + read-write + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + + + PARITY + Indicates if parity is added to the frame + 0 + 0 + + + NoParity + Parity is not added to TX frames + 0 + + + Parity + Parity is added to TX frames + 1 + + + + + DISCARDMODE + Discarding unused bits at start or end of a frame + 1 + 1 + + + DiscardEnd + Unused bits are discarded at end of frame (EoF) + 0 + + + DiscardStart + Unused bits are discarded at start of frame (SoF) + 1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + SoF symbol not added + 0 + + + SoF + SoF symbol added + 1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing + 3 + 11 + + + + + + RXD + Unspecified + NFCT_RXD + read-write + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + + + PARITY + Indicates if parity expected in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0 + + + Parity + Parity is expected in RX frames + 1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + SoF symbol is not expected in RX frames + 0 + + + SoF + SoF symbol is expected in RX frames + 1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + + + MODULATIONCTRL + Enables the modulation output to a GPIO pin which can be connected to a second external antenna. + 0x52C + read-write + 0x00000001 + + + MODULATIONCTRL + Configuration of modulation control. + 0 + 1 + + + Invalid + Invalid, defaults to same behaviour as for Internal + 0x0 + + + Internal + Use internal modulator only + 0x1 + + + ModToGpio + Output digital modulation signal to a GPIO pin. + 0x2 + + + InternalAndModToGpio + Use internal modulator and output digital modulation signal to a GPIO pin. + 0x3 + + + + + + + MODULATIONPSEL + Pin select for Modulation control. + 0x538 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + NFCID1_LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x590 + read-write + 0x00006363 + + + NFCID1_Z + NFCID1 byte Z (very last byte sent) + 0 + 7 + + + NFCID1_Y + NFCID1 byte Y + 8 + 15 + + + NFCID1_X + NFCID1 byte X + 16 + 23 + + + NFCID1_W + NFCID1 byte W + 24 + 31 + + + + + NFCID1_2ND_LAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x594 + read-write + + + NFCID1_V + NFCID1 byte V + 0 + 7 + + + NFCID1_U + NFCID1 byte U + 8 + 15 + + + NFCID1_T + NFCID1 byte T + 16 + 23 + + + + + NFCID1_3RD_LAST + Third last NFCID1 part (10 bytes ID) + 0x598 + read-write + + + NFCID1_S + NFCID1 byte S + 0 + 7 + + + NFCID1_R + NFCID1 byte R + 8 + 15 + + + NFCID1_Q + NFCID1 byte Q + 16 + 23 + + + + + AUTOCOLRESCONFIG + Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. + 0x59C + read-write + 0x00000002 + + + MODE + Enables/disables auto collision resolution + 0 + 0 + + + Enabled + Auto collision resolution enabled + 0 + + + Disabled + Auto collision resolution disabled + 1 + + + + + + + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 + read-write + 0x00000001 + + + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 + + + SDD00000 + SDD pattern 00000 + 0 + + + SDD00001 + SDD pattern 00001 + 1 + + + SDD00010 + SDD pattern 00010 + 2 + + + SDD00100 + SDD pattern 00100 + 4 + + + SDD01000 + SDD pattern 01000 + 8 + + + SDD10000 + SDD pattern 10000 + 16 + + + + + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the auto collision resolution engine. + 6 + 7 + + + NFCID1Single + NFCID1 size: single (4 bytes) + 0 + + + NFCID1Double + NFCID1 size: double (7 bytes) + 1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 2 + + + + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + + + + + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 + read-write + + + RFU10 + Reserved for future use. Shall be 0. + 0 + 1 + + + CASCADE + Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) + 2 + 2 + + + RFU43 + Reserved for future use. Shall be 0. + 3 + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + + + GPIOTE + GPIO Tasks and Events + 0x40006000 + + 0 + 0x1000 + registers + + + GPIOTE + 6 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 8 + 12 + + + PORT + Port number + 13 + 13 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC + Successive approximation register (SAR) analog-to-digital converter + 0x40007000 + + 0 + 0x1000 + registers + + + SAADC + 7 + + SAADC + 0x20 + + + TASKS_START + Starts the SAADC and prepares the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Starts the SAADC and prepares the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Takes one SAADC sample + 0x004 + write-only + + + TASKS_SAMPLE + Takes one SAADC sample + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops the SAADC and terminates all on-going conversions + 0x008 + write-only + + + TASKS_STOP + Stops the SAADC and terminates all on-going conversions + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + The SAADC has started + 0x100 + read-write + + + EVENTS_STARTED + The SAADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The SAADC has filled up the result buffer + 0x104 + read-write + + + EVENTS_END + The SAADC has filled up the result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + Result ready for transfer to RAM + 0x10C + read-write + + + EVENTS_RESULTDONE + Result ready for transfer to RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The SAADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The SAADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last result is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last result is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last result is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last result is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + SAADC is ready. No on-going conversions. + 0 + + + Busy + SAADC is busy. Conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable SAADC + 0x500 + read-write + + + ENABLE + Enable or disable SAADC + 0 + 0 + + + Disabled + Disable SAADC + 0 + + + Enabled + Enable SAADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0x0D + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0x0D + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the SAADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring of a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bits + 0 + + + 10bit + 10 bits + 1 + + + 12bit + 12 bits + 2 + + + 14bit + 14 bits + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0x004 + read-write + + + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0 + 14 + + + + + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task + 0x008 + read-only + + + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + TIMER0 + Timer/Counter 0 + 0x40008000 + TIMER + + 0 + 0x1000 + registers + + + TIMER0 + 8 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER1 + Timer/Counter 1 + 0x40009000 + + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + 0x4000A000 + + TIMER2 + 10 + + + + RTC0 + Real time counter 0 + 0x4000B000 + RTC + + 0 + 0x1000 + registers + + + RTC0 + 11 + + RTC + 0x20 + + + TASKS_START + Start RTC COUNTER + 0x000 + write-only + + + TASKS_START + Start RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC COUNTER + 0x004 + write-only + + + TASKS_STOP + Stop RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC COUNTER + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TICK + Event on COUNTER increment + 0x100 + read-write + + + EVENTS_TICK + Event on COUNTER increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current COUNTER value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + TEMP + Temperature Sensor + 0x4000C000 + + 0 + 0x1000 + registers + + + TEMP + 12 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of first piecewise linear function + 0x520 + read-write + 0x00000326 + + + A0 + Slope of first piecewise linear function + 0 + 11 + + + + + A1 + Slope of second piecewise linear function + 0x524 + read-write + 0x00000348 + + + A1 + Slope of second piecewise linear function + 0 + 11 + + + + + A2 + Slope of third piecewise linear function + 0x528 + read-write + 0x000003AA + + + A2 + Slope of third piecewise linear function + 0 + 11 + + + + + A3 + Slope of fourth piecewise linear function + 0x52C + read-write + 0x0000040E + + + A3 + Slope of fourth piecewise linear function + 0 + 11 + + + + + A4 + Slope of fifth piecewise linear function + 0x530 + read-write + 0x000004BD + + + A4 + Slope of fifth piecewise linear function + 0 + 11 + + + + + A5 + Slope of sixth piecewise linear function + 0x534 + read-write + 0x000005A3 + + + A5 + Slope of sixth piecewise linear function + 0 + 11 + + + + + B0 + y-intercept of first piecewise linear function + 0x540 + read-write + 0x00003FEF + + + B0 + y-intercept of first piecewise linear function + 0 + 13 + + + + + B1 + y-intercept of second piecewise linear function + 0x544 + read-write + 0x00003FBE + + + B1 + y-intercept of second piecewise linear function + 0 + 13 + + + + + B2 + y-intercept of third piecewise linear function + 0x548 + read-write + 0x00003FBE + + + B2 + y-intercept of third piecewise linear function + 0 + 13 + + + + + B3 + y-intercept of fourth piecewise linear function + 0x54C + read-write + 0x00000012 + + + B3 + y-intercept of fourth piecewise linear function + 0 + 13 + + + + + B4 + y-intercept of fifth piecewise linear function + 0x550 + read-write + 0x00000124 + + + B4 + y-intercept of fifth piecewise linear function + 0 + 13 + + + + + B5 + y-intercept of sixth piecewise linear function + 0x554 + read-write + 0x0000027C + + + B5 + y-intercept of sixth piecewise linear function + 0 + 13 + + + + + T0 + End point of first piecewise linear function + 0x560 + read-write + 0x000000E2 + + + T0 + End point of first piecewise linear function + 0 + 7 + + + + + T1 + End point of second piecewise linear function + 0x564 + read-write + 0x00000000 + + + T1 + End point of second piecewise linear function + 0 + 7 + + + + + T2 + End point of third piecewise linear function + 0x568 + read-write + 0x00000019 + + + T2 + End point of third piecewise linear function + 0 + 7 + + + + + T3 + End point of fourth piecewise linear function + 0x56C + read-write + 0x0000003C + + + T3 + End point of fourth piecewise linear function + 0 + 7 + + + + + T4 + End point of fifth piecewise linear function + 0x570 + read-write + 0x00000050 + + + T4 + End point of fifth piecewise linear function + 0 + 7 + + + + + + + RNG + Random Number Generator + 0x4000D000 + + 0 + 0x1000 + registers + + + RNG + 13 + + RNG + 0x20 + + + TASKS_START + Task starting the random number generator + 0x000 + write-only + + + TASKS_START + Task starting the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + + + TASKS_STOP + Task stopping the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + VALRDY_STOP + Shortcut between event VALRDY and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + VALRDY + Write '1' to enable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + VALRDY + Write '1' to disable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + DERCEN + Bias correction + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + VALUE + Output random number + 0x508 + read-only + + + VALUE + Generated random number + 0 + 7 + + + + + + + ECB + AES ECB Mode Encryption + 0x4000E000 + + 0 + 0x1000 + registers + + + ECB + 14 + + ECB + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + + + TASKS_STARTECB + Start ECB block encrypt + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + + + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + + + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + AAR + Accelerated Address Resolver + 0x4000F000 + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + Address resolution procedure complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + + + EVENTS_RESOLVED + Address resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Resolution status + 0x400 + read-only + + + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 3 + + + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity Root Keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM Mode Encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x00C + write-only + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDKSGEN + Keystream generation complete + 0x100 + read-write + + + EVENTS_ENDKSGEN + Keystream generation complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Deprecated register - CCM error event + 0x108 + read-write + + + EVENTS_ERROR + Deprecated field - CCM error event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MICSTATUS + MIC check result + 0x400 + read-only + + + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MIC check failed + 0 + + + CheckPassed + MIC check passed + 1 + + + + + + + ENABLE + Enable + 0x500 + read-write + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + 0 + 0 + + + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode + 1 + + + + + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 + 17 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + LENGTH + Packet length configuration + 24 + 24 + + + Default + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. + 0 + + + Extended + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. + 1 + + + + + + + CNFPTR + Pointer to data structure holding AES key and NONCE vector + 0x508 + read-write + + + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during keystream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended. + 0x518 + read-write + 0x000000FB + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + 0 + 7 + + + + + RATEOVERRIDE + Data rate override setting. + 0x51C + read-write + 0x00000000 + + + RATEOVERRIDE + Data rate override setting. + 0 + 1 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + + + + + WDT + Watchdog Timer + 0x40010000 + + 0 + 0x1000 + registers + + + WDT + 16 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0 + + + Run + Keep the watchdog running while the CPU is sleeping + 1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 1 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + RTC1 + Real time counter 1 + 0x40011000 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + 0x40012000 + + 0 + 0x1000 + registers + + + QDEC + 18 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high + 1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0 + + + 256us + 256 us + 1 + + + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 + + + 4096us + 4096 us + 5 + + + 8192us + 8192 us + 6 + + + 16384us + 16384 us + 7 + + + 32ms + 32768 us + 8 + + + 65ms + 65536 us + 9 + + + 131ms + 131072 us + 10 + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0 + + + 40Smpl + 40 samples/report + 1 + + + 80Smpl + 80 samples/report + 2 + + + 120Smpl + 120 samples/report + 3 + + + 160Smpl + 160 samples/report + 4 + + + 200Smpl + 200 samples/report + 5 + + + 240Smpl + 240 samples/report + 6 + + + 280Smpl + 280 samples/report + 7 + + + 1Smpl + 1 sample/report + 8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0 + + + Enabled + Debounce input filters enabled + 1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + 0x40013000 + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + PSEL + Pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0 + + + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF + 5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 2 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0 + + + Normal + Normal mode + 1 + + + High + High-speed mode + 2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0 + + + Diff + Differential mode + 1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis enabled + 1 + + + + + + + + + LPCOMP + Low-power comparator + 0x40013000 + COMP + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 6 + + + ARef + External analog reference selected + 7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 10 + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 11 + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 12 + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 13 + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 14 + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 15 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 0 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0 + + + Up + Generate ANADETECT on upward crossing only + 1 + + + Down + Generate ANADETECT on downward crossing only + 2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0 + + + Enabled + Comparator hysteresis enabled + 1 + + + + + + + + + EGU0 + Event generator unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU1 + Event generator unit 1 + 0x40015000 + + SWI1_EGU1 + 21 + + + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 + + SWI1_EGU1 + 21 + + + + EGU2 + Event generator unit 2 + 0x40016000 + + SWI2_EGU2 + 22 + + + + SWI2 + Software interrupt 2 + 0x40016000 + EGU2 + + SWI2_EGU2 + 22 + + + + EGU3 + Event generator unit 3 + 0x40017000 + + SWI3_EGU3 + 23 + + + + SWI3 + Software interrupt 3 + 0x40017000 + EGU3 + + SWI3_EGU3 + 23 + + + + EGU4 + Event generator unit 4 + 0x40018000 + + SWI4_EGU4 + 24 + + + + SWI4 + Software interrupt 4 + 0x40018000 + EGU4 + + SWI4_EGU4 + 24 + + + + EGU5 + Event generator unit 5 + 0x40019000 + + SWI5_EGU5 + 25 + + + + SWI5 + Software interrupt 5 + 0x40019000 + EGU5 + + SWI5_EGU5 + 25 + + + + TIMER3 + Timer/Counter 3 + 0x4001A000 + + TIMER3 + 26 + + + + TIMER4 + Timer/Counter 4 + 0x4001B000 + + TIMER4 + 27 + + + + PWM0 + Pulse width modulation unit 0 + 0x4001C000 + PWM + + 0 + 0x1000 + registers + + + PWM0 + 28 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x4001D000 + + 0 + 0x1000 + registers + + + PDM + 29 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency configuration + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + + + RATIO + Selects the ratio between PDM_CLK and output sample rate + 0 + 0 + + + Ratio64 + Ratio of 64 + 0 + + + Ratio80 + Ratio of 80 + 1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + ACL + Access control lists + 0x4001E000 + + 0 + 0x1000 + registers + + ACL + 0x20 + + + 8 + 0x010 + ACL[%s] + Unspecified + ACL_ACL + read-write + 0x800 + + ADDR + Description cluster: Start address of region to protect. The start address must be word-aligned. + 0x000 + read-writeonce + 0x00000000 + + + ADDR + Start address of flash region n. The start address must point to a flash page boundary. + 0 + 31 + + + + + SIZE + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + 0x004 + read-writeonce + 0x00000000 + + + SIZE + Size of flash region n in bytes. Must be a multiple of the flash page size. + 0 + 31 + + + + + PERM + Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE + 0x008 + read-writeonce + 0x00000000 + + + WRITE + Configure write and erase permissions for region n. Write '0' has no effect. + 1 + 1 + + + Enable + Allow write and erase instructions to region n + 0 + + + Disable + Block write and erase instructions to region n + 1 + + + + + READ + Configure read permissions for region n. Write '0' has no effect. + 2 + 2 + + + Enable + Allow read instructions to region n + 0 + + + Disable + Block read instructions to region n + 1 + + + + + + + + + + NVMC + Non Volatile Memory Controller + 0x4001E000 + ACL + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + ERASEPAGE + Register for erasing a page in code area + 0x508 + write-only + + + ERASEPAGE + Register for starting erase of a page in code area + 0 + 31 + + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE + 0x508 + write-only + ERASEPAGE + + + ERASEPCR1 + Register for erasing a page in code area, equivalent to ERASEPAGE + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + + + ERASEALL + Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE + 0x510 + write-only + + + ERASEPCR0 + Register for starting erase of a page in code area, equivalent to ERASEPAGE + 0 + 31 + + + + + ERASEUICR + Register for erasing user information configuration registers + 0x514 + write-only + + + ERASEUICR + Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of UICR + 1 + + + + + + + ERASEPAGEPARTIAL + Register for partial erase of a page in code area + 0x518 + write-only + + + ERASEPAGEPARTIAL + Register for starting partial erase of a page in code area + 0 + 31 + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + ICACHECNF + I-code cache configuration register + 0x540 + read-write + 0x00000000 + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0 + + + Enabled + Enable cache + 1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0 + + + Enabled + Enable cache profiling + 1 + + + + + + + IHIT + I-code cache hit counter + 0x548 + read-write + + + HITS + Number of cache hits. Register is writable, but only to '0'. + 0 + 31 + + + + + IMISS + I-code cache miss counter + 0x54C + read-write + + + MISSES + Number of cache misses. Register is writable, but only to '0'. + 0 + 31 + + + + + + + PPI + Programmable Peripheral Interconnect + 0x4001F000 + + 0 + 0x1000 + registers + + PPI + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing '0' has no effect. + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing '0' has no effect. + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing '0' has no effect. + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing '0' has no effect. + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing '0' has no effect. + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing '0' has no effect. + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing '0' has no effect. + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing '0' has no effect. + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing '0' has no effect. + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing '0' has no effect. + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing '0' has no effect. + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing '0' has no effect. + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing '0' has no effect. + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing '0' has no effect. + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing '0' has no effect. + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing '0' has no effect. + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing '0' has no effect. + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing '0' has no effect. + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing '0' has no effect. + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing '0' has no effect. + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing '0' has no effect. + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing '0' has no effect. + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing '0' has no effect. + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing '0' has no effect. + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing '0' has no effect. + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing '0' has no effect. + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing '0' has no effect. + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing '0' has no effect. + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing '0' has no effect. + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing '0' has no effect. + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing '0' has no effect. + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing '0' has no effect. + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing '0' has no effect. + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing '0' has no effect. + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing '0' has no effect. + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing '0' has no effect. + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing '0' has no effect. + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing '0' has no effect. + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing '0' has no effect. + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing '0' has no effect. + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing '0' has no effect. + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing '0' has no effect. + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing '0' has no effect. + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing '0' has no effect. + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing '0' has no effect. + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing '0' has no effect. + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing '0' has no effect. + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing '0' has no effect. + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing '0' has no effect. + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing '0' has no effect. + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing '0' has no effect. + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing '0' has no effect. + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing '0' has no effect. + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing '0' has no effect. + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing '0' has no effect. + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing '0' has no effect. + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing '0' has no effect. + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing '0' has no effect. + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing '0' has no effect. + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing '0' has no effect. + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing '0' has no effect. + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing '0' has no effect. + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing '0' has no effect. + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing '0' has no effect. + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + + + 20 + 0x008 + CH[%s] + PPI Channel + PPI_CH + read-write + 0x510 + + EEP + Description cluster: Channel n event endpoint + 0x000 + read-write + + + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. + 0 + 31 + + + + + TEP + Description cluster: Channel n task endpoint + 0x004 + read-write + + + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. + 0 + 31 + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + 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channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + 32 + 0x004 + FORK[%s] + Fork + PPI_FORK + read-write + 0x910 + + TEP + Description cluster: Channel n task endpoint + 0x000 + read-write + + + TEP + Pointer to task register + 0 + 31 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Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION1RA + Write '1' to enable interrupt for event REGION1RA + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2WA + Write '1' to enable interrupt for event REGION2WA + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2RA + Write '1' to enable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3WA + Write '1' to enable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3RA + Write '1' to enable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1WA + Write '1' to enable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1RA + Write '1' to enable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + + + REGION0WA + Write '1' to disable interrupt for event REGION0WA + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION0RA + Write '1' to disable interrupt for event REGION0RA + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1WA + Write '1' to disable interrupt for event REGION1WA + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1RA + Write '1' to disable interrupt for event REGION1RA + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2WA + Write '1' to disable interrupt for event REGION2WA + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2RA + Write '1' to disable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3WA + Write '1' to disable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3RA + Write '1' to disable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0WA + Write '1' to disable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 2 + 0x008 + PERREGION[%s] + Unspecified + MWU_PERREGION + read-write + 0x400 + + SUBSTATWA + Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching + 0x000 + read-write + oneToClear + + + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + + + SUBSTATRA + Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching + 0x004 + read-write + oneToClear + + + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + + + + REGIONEN + Enable/disable regions watch + 0x510 + read-write + + + RGN0WA + Enable/disable write access watch in region[0] + 0 + 0 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable/disable read access watch in region[0] + 1 + 1 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable/disable write access watch in region[1] + 2 + 2 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable/disable read access watch in region[1] + 3 + 3 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable/disable write access watch in region[2] + 4 + 4 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable/disable read access watch in region[2] + 5 + 5 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable/disable write access watch in region[3] + 6 + 6 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable/disable read access watch in region[3] + 7 + 7 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable/disable write access watch in PREGION[0] + 24 + 24 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable/disable read access watch in PREGION[0] + 25 + 25 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable/disable write access watch in PREGION[1] + 26 + 26 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable/disable read access watch in PREGION[1] + 27 + 27 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENSET + Enable regions watch + 0x514 + read-write + + + RGN0WA + Enable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENCLR + Disable regions watch + 0x518 + read-write + + + RGN0WA + Disable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN0RA + Disable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN1WA + Disable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN1RA + Disable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN2WA + Disable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN2RA + Disable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN3WA + Disable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN3RA + Disable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + PRGN0WA + Disable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN0RA + Disable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + PRGN1WA + Disable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN1RA + Disable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + + + 4 + 0x010 + REGION[%s] + Unspecified + MWU_REGION + read-write + 0x600 + + START + Description cluster: Start address for region n + 0x000 + read-write + 0x00000000 + + + START + Start address for region + 0 + 31 + + + + + END + Description cluster: End address of region n + 0x004 + read-write + + + END + End address of region. + 0 + 31 + + + + + + 2 + 0x010 + PREGION[%s] + Unspecified + MWU_PREGION + read-write + 0x6C0 + + START + Description cluster: Reserved for future use + 0x000 + read-only + + + START + Reserved for future use + 0 + 31 + + + + + END + Description cluster: Reserved for future use + 0x004 + read-only + + + END + Reserved for future use + 0 + 31 + + + + + SUBS + Description cluster: Subregions of region n + 0x008 + read-write + 0x00000000 + + + SR0 + Include or exclude subregion 0 in region + 0 + 0 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR1 + Include or exclude subregion 1 in region + 1 + 1 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR2 + Include or exclude subregion 2 in region + 2 + 2 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR3 + Include or exclude subregion 3 in region + 3 + 3 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR4 + Include or exclude subregion 4 in region + 4 + 4 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR5 + Include or exclude subregion 5 in region + 5 + 5 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR6 + Include or exclude subregion 6 in region + 6 + 6 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR7 + Include or exclude subregion 7 in region + 7 + 7 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR8 + Include or exclude subregion 8 in region + 8 + 8 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR9 + Include or exclude subregion 9 in region + 9 + 9 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR10 + Include or exclude subregion 10 in region + 10 + 10 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR11 + Include or exclude subregion 11 in region + 11 + 11 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR12 + Include or exclude subregion 12 in region + 12 + 12 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR13 + Include or exclude subregion 13 in region + 13 + 13 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR14 + Include or exclude subregion 14 in region + 14 + 14 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR15 + Include or exclude subregion 15 in region + 15 + 15 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR16 + Include or exclude subregion 16 in region + 16 + 16 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR17 + Include or exclude subregion 17 in region + 17 + 17 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR18 + Include or exclude subregion 18 in region + 18 + 18 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR19 + Include or exclude subregion 19 in region + 19 + 19 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR20 + Include or exclude subregion 20 in region + 20 + 20 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR21 + Include or exclude subregion 21 in region + 21 + 21 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR22 + Include or exclude subregion 22 in region + 22 + 22 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR23 + Include or exclude subregion 23 in region + 23 + 23 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR24 + Include or exclude subregion 24 in region + 24 + 24 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR25 + Include or exclude subregion 25 in region + 25 + 25 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR26 + Include or exclude subregion 26 in region + 26 + 26 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR27 + Include or exclude subregion 27 in region + 27 + 27 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR28 + Include or exclude subregion 28 in region + 28 + 28 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR29 + Include or exclude subregion 29 in region + 29 + 29 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR30 + Include or exclude subregion 30 in region + 30 + 30 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR31 + Include or exclude subregion 31 in region + 31 + 31 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + + + + + + PWM1 + Pulse width modulation unit 1 + 0x40021000 + + PWM1 + 33 + + + + PWM2 + Pulse width modulation unit 2 + 0x40022000 + + PWM2 + 34 + + + + SPI2 + Serial Peripheral Interface 2 + 0x40023000 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIM2 + Serial Peripheral Interface Master with EasyDMA 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIS2 + SPI Slave 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + RTC2 + Real time counter 2 + 0x40024000 + + RTC2 + 36 + + + + I2S + Inter-IC Sound + 0x40025000 + + 0 + 0x1000 + registers + + + I2S + 37 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0x000 + write-only + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0x004 + write-only + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable I2S module. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode. + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode. + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable. + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable. + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + Master clock generator frequency. + 0x010 + read-write + 0x20000000 + + + MCKFREQ + Master clock generator frequency. + 0 + 31 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio. + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio. + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width. + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample width. + 0 + 1 + + + 8Bit + 8 bit. + 0 + + + 16Bit + 16 bit. + 1 + + + 24Bit + 24 bit. + 2 + + + + + + + ALIGN + Alignment of sample within a frame. + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame. + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format. + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format. + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels. + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels. + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal. + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal. + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + FPU + FPU + 0x40026000 + + 0 + 0x1000 + registers + + + FPU + 38 + + FPU + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + USBD + Universal serial bus device + 0x40027000 + + 0 + 0x1000 + registers + + + USBD + 39 + + USBD + 0x20 + + + 0x8 + 0x4 + TASKS_STARTEPIN[%s] + Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0x004 + write-only + + + TASKS_STARTEPIN + Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0x024 + write-only + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_STARTEPOUT[%s] + Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0x028 + write-only + + + TASKS_STARTEPOUT + Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0x048 + write-only + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0x04C + write-only + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0x050 + write-only + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0x054 + write-only + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0x058 + write-only + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0x05C + write-only + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0x100 + read-write + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0x104 + read-write + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPIN[%s] + Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x108 + read-write + + + EVENTS_ENDEPIN + The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0x128 + read-write + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0x12C + read-write + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPOUT[%s] + Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x130 + read-write + + + EVENTS_ENDEPOUT + The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0x150 + read-write + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0x154 + read-write + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0x158 + read-write + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0x15C + read-write + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0x160 + read-write + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + EP0DATADONE_STARTEPIN0 + Shortcut between event EP0DATADONE and task STARTEPIN[0] + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_STARTEPOUT0 + Shortcut between event EP0DATADONE and task STARTEPOUT[0] + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_EP0STATUS + Shortcut between event EP0DATADONE and task EP0STATUS + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0STATUS + Shortcut between event ENDEPOUT[0] and task EP0STATUS + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0RCVOUT + Shortcut between event ENDEPOUT[0] and task EP0RCVOUT + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + USBRESET + Enable or disable interrupt for event USBRESET + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN0 + Enable or disable interrupt for event ENDEPIN[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN1 + Enable or disable interrupt for event ENDEPIN[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN2 + Enable or disable interrupt for event ENDEPIN[2] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN3 + Enable or disable interrupt for event ENDEPIN[3] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN4 + Enable or disable interrupt for event ENDEPIN[4] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN5 + Enable or disable interrupt for event ENDEPIN[5] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN6 + Enable or disable interrupt for event ENDEPIN[6] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN7 + Enable or disable interrupt for event ENDEPIN[7] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0DATADONE + Enable or disable interrupt for event EP0DATADONE + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOIN + Enable or disable interrupt for event ENDISOIN + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT0 + Enable or disable interrupt for event ENDEPOUT[0] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT1 + Enable or disable interrupt for event ENDEPOUT[1] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT2 + Enable or disable interrupt for event ENDEPOUT[2] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT3 + Enable or disable interrupt for event ENDEPOUT[3] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT4 + Enable or disable interrupt for event ENDEPOUT[4] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT5 + Enable or disable interrupt for event ENDEPOUT[5] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT6 + Enable or disable interrupt for event ENDEPOUT[6] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT7 + Enable or disable interrupt for event ENDEPOUT[7] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOOUT + Enable or disable interrupt for event ENDISOOUT + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SOF + Enable or disable interrupt for event SOF + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + USBEVENT + Enable or disable interrupt for event USBEVENT + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0SETUP + Enable or disable interrupt for event EP0SETUP + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EPDATA + Enable or disable interrupt for event EPDATA + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + USBRESET + Write '1' to enable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN0 + Write '1' to enable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN1 + Write '1' to enable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN2 + Write '1' to enable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN3 + Write '1' to enable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN4 + Write '1' to enable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN5 + Write '1' to enable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN6 + Write '1' to enable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN7 + Write '1' to enable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0DATADONE + Write '1' to enable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOIN + Write '1' to enable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT0 + Write '1' to enable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT1 + Write '1' to enable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT2 + Write '1' to enable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT3 + Write '1' to enable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT4 + Write '1' to enable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT5 + Write '1' to enable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT6 + Write '1' to enable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT7 + Write '1' to enable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOOUT + Write '1' to enable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SOF + Write '1' to enable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBEVENT + Write '1' to enable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0SETUP + Write '1' to enable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EPDATA + Write '1' to enable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + USBRESET + Write '1' to disable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN0 + Write '1' to disable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN1 + Write '1' to disable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN2 + Write '1' to disable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN3 + Write '1' to disable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN4 + Write '1' to disable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN5 + Write '1' to disable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN6 + Write '1' to disable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN7 + Write '1' to disable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0DATADONE + Write '1' to disable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOIN + Write '1' to disable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT0 + Write '1' to disable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT1 + Write '1' to disable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT2 + Write '1' to disable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT3 + Write '1' to disable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT4 + Write '1' to disable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT5 + Write '1' to disable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT6 + Write '1' to disable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT7 + Write '1' to disable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOOUT + Write '1' to disable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SOF + Write '1' to disable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBEVENT + Write '1' to disable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0SETUP + Write '1' to disable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EPDATA + Write '1' to disable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVENTCAUSE + Details on what caused the USBEVENT event + 0x400 + read-write + oneToClear + + + ISOOUTCRC + CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. + 0 + 0 + + + NotDetected + No error detected + 0 + + + Detected + Error detected + 1 + + + + + SUSPEND + Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. + 8 + 8 + + + NotDetected + Suspend not detected + 0 + + + Detected + Suspend detected + 1 + + + + + RESUME + Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. + 9 + 9 + + + NotDetected + Resume not detected + 0 + + + Detected + Resume detected + 1 + + + + + USBWUALLOWED + USB MAC has been woken up and operational. Write '1' to clear. + 10 + 10 + + + NotAllowed + Wake up not allowed + 0 + + + Allowed + Wake up allowed + 1 + + + + + READY + USB device is ready for normal operation. Write '1' to clear. + 11 + 11 + + + NotDetected + USBEVENT was not issued due to USBD peripheral ready + 0 + + + Ready + USBD peripheral is ready + 1 + + + + + + + HALTED + Unspecified + USBD_HALTED + read-write + 0x420 + + 0x8 + 0x4 + EPIN[%s] + Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x000 + read-only + + + GETSTATUS + IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + 0x8 + 0x4 + EPOUT[%s] + Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x024 + read-only + + + GETSTATUS + OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + + EPSTATUS + Provides information on which endpoint's EasyDMA registers have been captured + 0x468 + read-write + oneToClear + + + EPIN0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 0 + 0 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 1 + 1 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 2 + 2 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 3 + 3 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 4 + 4 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 5 + 5 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 6 + 6 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 7 + 7 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 8 + 8 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 16 + 16 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 17 + 17 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 18 + 18 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 19 + 19 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 20 + 20 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 21 + 21 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 22 + 22 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 23 + 23 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 24 + 24 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + + + EPDATASTATUS + Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) + 0x46C + read-write + oneToClear + + + EPIN1 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 1 + 1 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN2 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 2 + 2 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN3 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 3 + 3 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN4 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 4 + 4 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN5 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 5 + 5 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN6 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 6 + 6 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN7 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 7 + 7 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT1 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 17 + 17 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT2 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 18 + 18 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT3 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 19 + 19 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT4 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 20 + 20 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT5 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 21 + 21 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT6 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 22 + 22 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT7 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 23 + 23 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + + + USBADDR + Device USB address + 0x470 + read-only + + + ADDR + Device USB address + 0 + 6 + + + + + BMREQUESTTYPE + SETUP data, byte 0, bmRequestType + 0x480 + read-only + 0x00000000 + + + RECIPIENT + Data transfer type + 0 + 4 + + + Device + Device + 0 + + + Interface + Interface + 1 + + + Endpoint + Endpoint + 2 + + + Other + Other + 3 + + + + + TYPE + Data transfer type + 5 + 6 + + + Standard + Standard + 0 + + + Class + Class + 1 + + + Vendor + Vendor + 2 + + + + + DIRECTION + Data transfer direction + 7 + 7 + + + HostToDevice + Host-to-device + 0 + + + DeviceToHost + Device-to-host + 1 + + + + + + + BREQUEST + SETUP data, byte 1, bRequest + 0x484 + read-only + 0x00000000 + + + BREQUEST + SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. + 0 + 7 + + + STD_GET_STATUS + Standard request GET_STATUS + 0 + + + STD_CLEAR_FEATURE + Standard request CLEAR_FEATURE + 1 + + + STD_SET_FEATURE + Standard request SET_FEATURE + 3 + + + STD_SET_ADDRESS + Standard request SET_ADDRESS + 5 + + + STD_GET_DESCRIPTOR + Standard request GET_DESCRIPTOR + 6 + + + STD_SET_DESCRIPTOR + Standard request SET_DESCRIPTOR + 7 + + + STD_GET_CONFIGURATION + Standard request GET_CONFIGURATION + 8 + + + STD_SET_CONFIGURATION + Standard request SET_CONFIGURATION + 9 + + + STD_GET_INTERFACE + Standard request GET_INTERFACE + 10 + + + STD_SET_INTERFACE + Standard request SET_INTERFACE + 11 + + + STD_SYNCH_FRAME + Standard request SYNCH_FRAME + 12 + + + + + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0x488 + read-only + 0x00000000 + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0 + 7 + + + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0x48C + read-only + 0x00000000 + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0 + 7 + + + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0x490 + read-only + 0x00000000 + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0 + 7 + + + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0x494 + read-only + 0x00000000 + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0 + 7 + + + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0x498 + read-only + 0x00000000 + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0 + 7 + + + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0x49C + read-only + 0x00000000 + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0 + 7 + + + + + SIZE + Unspecified + USBD_SIZE + read-write + 0x4A0 + + 0x8 + 0x4 + EPOUT[%s] + Description collection: Number of bytes received last in the data stage of this OUT endpoint + 0x000 + read-write + + + SIZE + Number of bytes received last in the data stage of this OUT endpoint + 0 + 6 + + + + + ISOOUT + Number of bytes received last on this ISO OUT data endpoint + 0x020 + read-only + 0x00010000 + + + SIZE + Number of bytes received last on this ISO OUT data endpoint + 0 + 9 + + + ZERO + Zero-length data packet received + 16 + 16 + + + Normal + No zero-length data received, use value in SIZE + 0 + + + ZeroData + Zero-length data received, ignore value in SIZE + 1 + + + + + + + + ENABLE + Enable USB + 0x500 + read-write + + + ENABLE + Enable USB + 0 + 0 + + + Disabled + USB peripheral is disabled + 0 + + + Enabled + USB peripheral is enabled + 1 + + + + + + + USBPULLUP + Control of the USB pull-up + 0x504 + read-write + + + CONNECT + Control of the USB pull-up on the D+ line + 0 + 0 + + + Disabled + Pull-up is disconnected + 0 + + + Enabled + Pull-up is connected to D+ + 1 + + + + + + + DPDMVALUE + State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). + 0x508 + read-write + + + STATE + State D+ and D- lines will be forced into by the DPDMDRIVE task + 0 + 4 + + + Resume + D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) + 1 + + + J + D+ forced high, D- forced low (J state) + 2 + + + K + D+ forced low, D- forced high (K state) + 4 + + + + + + + DTOGGLE + Data toggle control and status + 0x50C + read-write + 0x00000100 + + + EP + Select bulk endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + VALUE + Data toggle value + 8 + 9 + + + Nop + No action on data toggle when writing the register with this value + 0 + + + Data0 + Data toggle is DATA0 on endpoint set by EP and IO + 1 + + + Data1 + Data toggle is DATA1 on endpoint set by EP and IO + 2 + + + + + + + EPINEN + Endpoint IN enable + 0x510 + read-write + 0x00000001 + + + IN0 + Enable IN endpoint 0 + 0 + 0 + + + Disable + Disable endpoint IN 0 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 0 (response to IN tokens) + 1 + + + + + IN1 + Enable IN endpoint 1 + 1 + 1 + + + Disable + Disable endpoint IN 1 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 1 (response to IN tokens) + 1 + + + + + IN2 + Enable IN endpoint 2 + 2 + 2 + + + Disable + Disable endpoint IN 2 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 2 (response to IN tokens) + 1 + + + + + IN3 + Enable IN endpoint 3 + 3 + 3 + + + Disable + Disable endpoint IN 3 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 3 (response to IN tokens) + 1 + + + + + IN4 + Enable IN endpoint 4 + 4 + 4 + + + Disable + Disable endpoint IN 4 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 4 (response to IN tokens) + 1 + + + + + IN5 + Enable IN endpoint 5 + 5 + 5 + + + Disable + Disable endpoint IN 5 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 5 (response to IN tokens) + 1 + + + + + IN6 + Enable IN endpoint 6 + 6 + 6 + + + Disable + Disable endpoint IN 6 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 6 (response to IN tokens) + 1 + + + + + IN7 + Enable IN endpoint 7 + 7 + 7 + + + Disable + Disable endpoint IN 7 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 7 (response to IN tokens) + 1 + + + + + ISOIN + Enable ISO IN endpoint + 8 + 8 + + + Disable + Disable ISO IN endpoint 8 + 0 + + + Enable + Enable ISO IN endpoint 8 + 1 + + + + + + + EPOUTEN + Endpoint OUT enable + 0x514 + read-write + 0x00000001 + + + OUT0 + Enable OUT endpoint 0 + 0 + 0 + + + Disable + Disable endpoint OUT 0 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 0 (response to OUT tokens) + 1 + + + + + OUT1 + Enable OUT endpoint 1 + 1 + 1 + + + Disable + Disable endpoint OUT 1 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 1 (response to OUT tokens) + 1 + + + + + OUT2 + Enable OUT endpoint 2 + 2 + 2 + + + Disable + Disable endpoint OUT 2 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 2 (response to OUT tokens) + 1 + + + + + OUT3 + Enable OUT endpoint 3 + 3 + 3 + + + Disable + Disable endpoint OUT 3 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 3 (response to OUT tokens) + 1 + + + + + OUT4 + Enable OUT endpoint 4 + 4 + 4 + + + Disable + Disable endpoint OUT 4 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 4 (response to OUT tokens) + 1 + + + + + OUT5 + Enable OUT endpoint 5 + 5 + 5 + + + Disable + Disable endpoint OUT 5 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 5 (response to OUT tokens) + 1 + + + + + OUT6 + Enable OUT endpoint 6 + 6 + 6 + + + Disable + Disable endpoint OUT 6 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 6 (response to OUT tokens) + 1 + + + + + OUT7 + Enable OUT endpoint 7 + 7 + 7 + + + Disable + Disable endpoint OUT 7 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 7 (response to OUT tokens) + 1 + + + + + ISOOUT + Enable ISO OUT endpoint 8 + 8 + 8 + + + Disable + Disable ISO OUT endpoint 8 + 0 + + + Enable + Enable ISO OUT endpoint 8 + 1 + + + + + + + EPSTALL + STALL endpoints + 0x518 + write-only + 0x00000000 + modifyExternal + + + EP + Select endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + STALL + Stall selected endpoint + 8 + 8 + + + UnStall + Don't stall selected endpoint + 0 + + + Stall + Stall selected endpoint + 1 + + + + + + + ISOSPLIT + Controls the split of ISO buffers + 0x51C + read-write + + + SPLIT + Controls the split of ISO buffers + 0 + 15 + + + OneDir + Full buffer dedicated to either ISO IN or OUT + 0x0000 + + + HalfIN + Lower half for IN, upper half for OUT + 0x0080 + + + + + + + FRAMECNTR + Returns the current value of the start of frame counter + 0x520 + read-only + + + FRAMECNTR + Returns the current value of the start of frame counter + 0 + 10 + + + + + LOWPOWER + Controls USBD peripheral low power mode during USB suspend + 0x52C + read-write + 0x00000000 + + + LOWPOWER + Controls USBD peripheral low-power mode during USB suspend + 0 + 0 + + + ForceNormal + Software must write this value to exit low power mode and before performing a remote wake-up + 0 + + + LowPower + Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral + 1 + + + + + + + ISOINCONFIG + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0x530 + read-write + + + RESPONSE + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0 + 0 + + + NoResp + Endpoint does not respond in that case + 0 + + + ZeroData + Endpoint responds with a zero-length data packet in that case + 1 + + + + + + + 8 + 0x014 + EPIN[%s] + Unspecified + USBD_EPIN + read-write + 0x600 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOIN + Unspecified + USBD_ISOIN + read-write + 0x6A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + 8 + 0x014 + EPOUT[%s] + Unspecified + USBD_EPOUT + read-write + 0x700 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOOUT + Unspecified + USBD_ISOOUT + read-write + 0x7A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + + + UARTE1 + UART with EasyDMA 1 + 0x40028000 + + UARTE1 + 40 + + + + PWM3 + Pulse width modulation unit 3 + 0x4002D000 + + PWM3 + 45 + + + + SPIM3 + Serial Peripheral Interface Master with EasyDMA 3 + 0x4002F000 + + SPIM3 + 47 + + + + \ No newline at end of file diff --git a/svd/nrf52840.svd b/svd/nrf52840.svd new file mode 100644 index 000000000..a1e623408 --- /dev/null +++ b/svd/nrf52840.svd @@ -0,0 +1,54973 @@ + + + + Nordic Semiconductor + Nordic + nrf52840 + nrf52 + 1 + nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA\n +\n +All rights reserved.\n +\n +Redistribution and use in source and binary forms, with or without modification,\n +are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form, except as embedded into a Nordic\n + Semiconductor ASA integrated circuit in a product or a software update for\n + such product, must reproduce the above copyright notice, this list of\n + conditions and the following disclaimer in the documentation and/or other\n + materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +4. This software, with or without modification, must only be used with a\n + Nordic Semiconductor ASA integrated circuit.\n +\n +5. Any software provided in binary form under this license must not be reverse\n + engineered, decompiled, modified and/or disassembled.\n +\n +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS\n +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE\n +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\n +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM4 + r0p1 + little + 1 + 1 + 3 + 0 + + system_nrf52840 + NRF_ + + 2048 + 2048 + 112 + + + + FICR + Factory information configuration registers + 0x10000000 + + 0 + 0x1000 + registers + + FICR + 0x20 + + + CODEPAGESIZE + Code memory page size + 0x010 + read-only + 0xFFFFFFFF + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + + + CODESIZE + Code memory size + 0x014 + read-only + 0xFFFFFFFF + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x060 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption root, word n + 0x080 + read-only + 0xFFFFFFFF + + + ER + Encryption root, word n + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity Root, word n + 0x090 + read-only + 0xFFFFFFFF + + + IR + Identity Root, word n + 0 + 31 + + + + + DEVICEADDRTYPE + Device address type + 0x0A0 + read-only + 0xFFFFFFFF + + + DEVICEADDRTYPE + Device address type + 0 + 0 + + + Public + Public address + 0 + + + Random + Random address + 1 + + + + + + + 0x2 + 0x4 + DEVICEADDR[%s] + Description collection: Device address n + 0x0A4 + read-only + 0xFFFFFFFF + + + DEVICEADDR + 48 bit device address + 0 + 31 + + + + + INFO + Device info + FICR_INFO + read-only + 0x100 + + PART + Part code + 0x000 + read-only + 0x00052840 + + + PART + Part code + 0 + 31 + + + N52820 + nRF52820 + 0x52820 + + + N52833 + nRF52833 + 0x52833 + + + N52840 + nRF52840 + 0x52840 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Build code (hardware version and production configuration) + 0x004 + read-only + 0xFFFFFFFF + + + VARIANT + Build code (hardware version and production configuration). Encoded as ASCII. + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + BAAA + BAAA + 0x42414141 + + + CAAA + CAAA + 0x43414141 + + + AABA + AABA + 0x41414241 + + + AABB + AABB + 0x41414242 + + + AACA + AACA + 0x41414341 + + + AAAB + AAAB + 0x41414142 + + + AAC0 + AAC0 + 0x41414330 + + + AADA + AADA + 0x41414441 + + + AAD0 + AAD0 + 0x41414430 + + + AAD1 + AAD1 + 0x41414431 + + + AAEA + AAEA + 0x41414541 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x008 + read-only + 0xFFFFFFFF + + + PACKAGE + Package option + 0 + 31 + + + QI + QIxx - 7x7 73-pin aQFN + 0x2004 + + + CK + CKxx - 3.544 x 3.607 WLCSP + 0x2005 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x00C + read-only + 0xFFFFFFFF + + + RAM + RAM variant + 0 + 31 + + + K16 + 16 kByte RAM + 0x10 + + + K32 + 32 kByte RAM + 0x20 + + + K64 + 64 kByte RAM + 0x40 + + + K128 + 128 kByte RAM + 0x80 + + + K256 + 256 kByte RAM + 0x100 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x010 + read-only + 0xFFFFFFFF + + + FLASH + Flash variant + 0 + 31 + + + K128 + 128 kByte FLASH + 0x80 + + + K256 + 256 kByte FLASH + 0x100 + + + K512 + 512 kByte FLASH + 0x200 + + + K1024 + 1 MByte FLASH + 0x400 + + + K2048 + 2 MByte FLASH + 0x800 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + + 0x3 + 0x4 + PRODTEST[%s] + Description collection: Production test signature n + 0x350 + read-only + 0xFFFFFFFF + + + PRODTEST + Production test signature n + 0 + 31 + + + Done + Production tests done + 0xBB42319F + + + NotDone + Production tests not done + 0xFFFFFFFF + + + + + + + TEMP + Registers storing factory TEMP module linearization coefficients + FICR_TEMP + read-only + 0x404 + + A0 + Slope definition A0 + 0x000 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A1 + Slope definition A1 + 0x004 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A2 + Slope definition A2 + 0x008 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A3 + Slope definition A3 + 0x00C + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A4 + Slope definition A4 + 0x010 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A5 + Slope definition A5 + 0x014 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + B0 + Y-intercept B0 + 0x018 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B1 + Y-intercept B1 + 0x01C + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B2 + Y-intercept B2 + 0x020 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B3 + Y-intercept B3 + 0x024 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B4 + Y-intercept B4 + 0x028 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B5 + Y-intercept B5 + 0x02C + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + T0 + Segment end T0 + 0x030 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T1 + Segment end T1 + 0x034 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T2 + Segment end T2 + 0x038 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T3 + Segment end T3 + 0x03C + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T4 + Segment end T4 + 0x040 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + + NFC + Unspecified + FICR_NFC + read-write + 0x450 + + TAGHEADER0 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x000 + read-only + 0xFFFFFF5F + + + MFGID + Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + 0 + 7 + + + UD1 + Unique identifier byte 1 + 8 + 15 + + + UD2 + Unique identifier byte 2 + 16 + 23 + + + UD3 + Unique identifier byte 3 + 24 + 31 + + + + + TAGHEADER1 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x004 + read-only + 0xFFFFFFFF + + + UD4 + Unique identifier byte 4 + 0 + 7 + + + UD5 + Unique identifier byte 5 + 8 + 15 + + + UD6 + Unique identifier byte 6 + 16 + 23 + + + UD7 + Unique identifier byte 7 + 24 + 31 + + + + + TAGHEADER2 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x008 + read-only + 0xFFFFFFFF + + + UD8 + Unique identifier byte 8 + 0 + 7 + + + UD9 + Unique identifier byte 9 + 8 + 15 + + + UD10 + Unique identifier byte 10 + 16 + 23 + + + UD11 + Unique identifier byte 11 + 24 + 31 + + + + + TAGHEADER3 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x00C + read-only + 0xFFFFFFFF + + + UD12 + Unique identifier byte 12 + 0 + 7 + + + UD13 + Unique identifier byte 13 + 8 + 15 + + + UD14 + Unique identifier byte 14 + 16 + 23 + + + UD15 + Unique identifier byte 15 + 24 + 31 + + + + + + TRNG90B + NIST800-90B RNG calibration data + FICR_TRNG90B + read-write + 0xC00 + + BYTES + Amount of bytes for the required entropy bits + 0x000 + read-only + 0xFFFFFFFF + + + BYTES + Amount of bytes for the required entropy bits + 0 + 31 + + + + + RCCUTOFF + Repetition counter cutoff + 0x004 + read-only + 0xFFFFFFFF + + + RCCUTOFF + Repetition counter cutoff + 0 + 31 + + + + + APCUTOFF + Adaptive proportion cutoff + 0x008 + read-only + 0xFFFFFFFF + + + APCUTOFF + Adaptive proportion cutoff + 0 + 31 + + + + + STARTUP + Amount of bytes for the startup tests + 0x00C + read-only + 0xFFFFFFFF + + + STARTUP + Amount of bytes for the startup tests + 0 + 31 + + + + + ROSC1 + Sample count for ring oscillator 1 + 0x010 + read-only + 0xFFFFFFFF + + + ROSC1 + Sample count for ring oscillator 1 + 0 + 31 + + + + + ROSC2 + Sample count for ring oscillator 2 + 0x014 + read-only + 0xFFFFFFFF + + + ROSC2 + Sample count for ring oscillator 2 + 0 + 31 + + + + + ROSC3 + Sample count for ring oscillator 3 + 0x018 + read-only + 0xFFFFFFFF + + + ROSC3 + Sample count for ring oscillator 3 + 0 + 31 + + + + + ROSC4 + Sample count for ring oscillator 4 + 0x01C + read-only + 0xFFFFFFFF + + + ROSC4 + Sample count for ring oscillator 4 + 0 + 31 + + + + + + + + UICR + User information configuration registers + 0x10001000 + + 0 + 0x1000 + registers + + UICR + 0x20 + + + 0xD + 0x4 + NRFFW[%s] + Description collection: Reserved for Nordic firmware design + 0x014 + read-write + 0xFFFFFFFF + + + NRFFW + Reserved for Nordic firmware design + 0 + 31 + + + + + 0xC + 0x4 + NRFHW[%s] + Description collection: Reserved for Nordic hardware design + 0x050 + read-write + 0xFFFFFFFF + + + NRFHW + Reserved for Nordic hardware design + 0 + 31 + + + + + 0x20 + 0x4 + CUSTOMER[%s] + Description collection: Reserved for customer + 0x080 + read-write + 0xFFFFFFFF + + + CUSTOMER + Reserved for customer + 0 + 31 + + + + + 0x2 + 0x4 + PSELRESET[%s] + Description collection: Mapping of the nRESET function (see POWER chapter for details) + 0x200 + read-write + 0xFFFFFFFF + + + PIN + GPIO pin number onto which nRESET is exposed + 0 + 4 + + + PORT + Port number onto which nRESET is exposed + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + APPROTECT + Access port protection + 0x208 + read-write + 0xFFFFFFFF + + + PALL + Enable or disable access port protection. + 0 + 7 + + + Disabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware + 0xFF + + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + + + Enabled + Enable + 0x00 + + + + + + + NFCPINS + Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + 0x20C + read-write + 0xFFFFFFFF + + + PROTECT + Setting of pins dedicated to NFC functionality + 0 + 0 + + + Disabled + Operation as GPIO pins. Same protection as normal GPIO pins. + 0 + + + NFC + Operation as NFC antenna pins. Configures the protection for NFC operation. + 1 + + + + + + + DEBUGCTRL + Processor debug control + 0x210 + read-write + 0xFFFFFFFF + + + CPUNIDEN + Configure CPU non-intrusive debug features + 0 + 7 + + + Enabled + Enable CPU ITM and ETM functionality (default behavior) + 0xFF + + + Disabled + Disable CPU ITM and ETM functionality + 0x00 + + + + + CPUFPBEN + Configure CPU flash patch and breakpoint (FPB) unit behavior + 8 + 15 + + + Enabled + Enable CPU FPB unit (default behavior) + 0xFF + + + Disabled + Disable CPU FPB unit. Writes into the FPB registers will be ignored. + 0x00 + + + + + + + REGOUT0 + Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. + 0x304 + read-write + 0xFFFFFFFF + + + VOUT + Output voltage from REG0 regulator stage. + 0 + 2 + + + 1V8 + 1.8 V + 0 + + + 2V1 + 2.1 V + 1 + + + 2V4 + 2.4 V + 2 + + + 2V7 + 2.7 V + 3 + + + 3V0 + 3.0 V + 4 + + + 3V3 + 3.3 V + 5 + + + DEFAULT + Default voltage: 1.8 V + 7 + + + + + + + + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + + + CLOCK + Clock control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFXO crystal oscillator + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFXO crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFXO crystal oscillator + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFXO crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CAL + Start calibration of LFRC + 0x010 + write-only + + + TASKS_CAL + Start calibration of LFRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTART + Start calibration timer + 0x014 + write-only + + + TASKS_CTSTART + Start calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTOP + Stop calibration timer + 0x018 + write-only + + + TASKS_CTSTOP + Stop calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFXO crystal oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFXO crystal oscillator started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + Calibration of LFRC completed + 0x10C + read-write + + + EVENTS_DONE + Calibration of LFRC completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTTO + Calibration timer timeout + 0x110 + read-write + + + EVENTS_CTTO + Calibration timer timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTSTARTED + Calibration timer has been started and is ready to process new tasks + 0x128 + read-write + + + EVENTS_CTSTARTED + Calibration timer has been started and is ready to process new tasks + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTSTOPPED + Calibration timer has been stopped and is ready to process new tasks + 0x12C + read-write + + + EVENTS_CTSTOPPED + Calibration timer has been stopped and is ready to process new tasks + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTTO + Write '1' to enable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTARTED + Write '1' to enable interrupt for event CTSTARTED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTOPPED + Write '1' to enable interrupt for event CTSTOPPED + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTTO + Write '1' to disable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTSTARTED + Write '1' to disable interrupt for event CTSTARTED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTSTOPPED + Write '1' to disable interrupt for event CTSTOPPED + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + HFCLK status + 0x40C + read-only + + + SRC + Source of HFCLK + 0 + 0 + + + RC + 64 MHz internal oscillator (HFINT) + 0 + + + Xtal + 64 MHz crystal oscillator (HFXO) + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + LFCLK status + 0x418 + read-only + + + SRC + Source of LFCLK + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK + 0x518 + read-write + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 16 + 16 + + + Disabled + Disable (use with Xtal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + EXTERNAL + Enable or disable external source for LFCLK + 17 + 17 + + + Disabled + Disable external source (use with Xtal) + 0 + + + Enabled + Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + 1 + + + + + + + HFXODEBOUNCE + HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. + 0x528 + read-write + 0x00000010 + + + HFXODEBOUNCE + HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. + 0 + 7 + + + Db256us + 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. + 0x10 + + + Db1024us + 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. + 0x40 + + + + + + + CTIV + Calibration timer interval + 0x538 + read-write + + + CTIV + Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + 0 + 6 + + + + + TRACECONFIG + Clocking options for the trace port debug interface + 0x55C + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. + 0 + 1 + + + 32MHz + 32 MHz trace port clock (TRACECLK = 16 MHz) + 0 + + + 16MHz + 16 MHz trace port clock (TRACECLK = 8 MHz) + 1 + + + 8MHz + 8 MHz trace port clock (TRACECLK = 4 MHz) + 2 + + + 4MHz + 4 MHz trace port clock (TRACECLK = 2 MHz) + 3 + + + + + TRACEMUX + Pin multiplexing of trace signals. See pin assignment chapter for more details. + 16 + 17 + + + GPIO + No trace signals routed to pins. All pins can be used as regular GPIOs. + 0 + + + Serial + SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. + 1 + + + Parallel + All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. + 2 + + + + + + + LFRCMODE + LFRC mode configuration + 0x5B4 + read-write + 0x00000000 + + + MODE + Set LFRC mode + 0 + 0 + + + Normal + Normal mode + 0 + + + ULP + Ultra-low power mode (ULP) + 1 + + + + + STATUS + Active LFRC mode. This field is read only. + 16 + 16 + + + Normal + Normal mode + 0 + + + ULP + Ultra-low power mode (ULP) + 1 + + + + + + + + + POWER + Power control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0x78 + write-only + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0x7C + write-only + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0x11C + read-write + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0x120 + read-write + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0x124 + read-write + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBDETECTED + Write '1' to enable interrupt for event USBDETECTED + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBREMOVED + Write '1' to enable interrupt for event USBREMOVED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBPWRRDY + Write '1' to enable interrupt for event USBPWRRDY + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBDETECTED + Write '1' to disable interrupt for event USBDETECTED + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBREMOVED + Write '1' to disable interrupt for event USBREMOVED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBPWRRDY + Write '1' to disable interrupt for event USBPWRRDY + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin-reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG + Reset from watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from soft reset detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from CPU lock-up detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LPCOMP + Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP + 17 + 17 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + NFC + Reset due to wake up from System OFF mode by NFC field detect + 19 + 19 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + VBUS + Reset due to wake up from System OFF mode by VBUS rising into valid range + 20 + 20 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + RAMSTATUS + Deprecated register - RAM status register + 0x428 + read-only + 0x00000000 + + + RAMBLOCK0 + RAM block 0 is on or off/powering up + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK1 + RAM block 1 is on or off/powering up + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK2 + RAM block 2 is on or off/powering up + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK3 + RAM block 3 is on or off/powering up + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + USBREGSTATUS + USB supply status + 0x438 + read-only + 0x00000000 + + + VBUSDETECT + VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) + 0 + 0 + + + NoVbus + VBUS voltage below valid threshold + 0 + + + VbusPresent + VBUS voltage above valid threshold + 1 + + + + + OUTPUTRDY + USB supply output settling time elapsed + 1 + 1 + + + NotReady + USBREG output settling time not elapsed + 0 + + + Ready + USBREG output settling time elapsed (same information as USBPWRRDY event) + 1 + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 1 + + + + + + + POFCON + Power-fail comparator configuration + 0x510 + read-write + + + POF + Enable or disable power failure warning + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + THRESHOLD + Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. + 1 + 4 + + + V17 + Set threshold to 1.7 V + 4 + + + V18 + Set threshold to 1.8 V + 5 + + + V19 + Set threshold to 1.9 V + 6 + + + V20 + Set threshold to 2.0 V + 7 + + + V21 + Set threshold to 2.1 V + 8 + + + V22 + Set threshold to 2.2 V + 9 + + + V23 + Set threshold to 2.3 V + 10 + + + V24 + Set threshold to 2.4 V + 11 + + + V25 + Set threshold to 2.5 V + 12 + + + V26 + Set threshold to 2.6 V + 13 + + + V27 + Set threshold to 2.7 V + 14 + + + V28 + Set threshold to 2.8 V + 15 + + + + + THRESHOLDVDDH + Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). + 8 + 11 + + + V27 + Set threshold to 2.7 V + 0 + + + V28 + Set threshold to 2.8 V + 1 + + + V29 + Set threshold to 2.9 V + 2 + + + V30 + Set threshold to 3.0 V + 3 + + + V31 + Set threshold to 3.1 V + 4 + + + V32 + Set threshold to 3.2 V + 5 + + + V33 + Set threshold to 3.3 V + 6 + + + V34 + Set threshold to 3.4 V + 7 + + + V35 + Set threshold to 3.5 V + 8 + + + V36 + Set threshold to 3.6 V + 9 + + + V37 + Set threshold to 3.7 V + 10 + + + V38 + Set threshold to 3.8 V + 11 + + + V39 + Set threshold to 3.9 V + 12 + + + V40 + Set threshold to 4.0 V + 13 + + + V41 + Set threshold to 4.1 V + 14 + + + V42 + Set threshold to 4.2 V + 15 + + + + + + + GPREGRET + General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + GPREGRET2 + General purpose retention register + 0x520 + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + DCDCEN + Enable DC/DC converter for REG1 stage + 0x578 + read-write + + + DCDCEN + Enable DC/DC converter for REG1 stage. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + DCDCEN0 + Enable DC/DC converter for REG0 stage + 0x580 + read-write + + + DCDCEN + Enable DC/DC converter for REG0 stage. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + MAINREGSTATUS + Main supply status + 0x640 + read-only + 0x00000000 + + + MAINREGSTATUS + Main supply status + 0 + 0 + + + Normal + Normal voltage mode. Voltage supplied on VDD. + 0 + + + High + High voltage mode. Voltage supplied on VDDH. + 1 + + + + + + + 9 + 0x010 + RAM[%s] + Unspecified + POWER_RAM + read-write + 0x900 + + POWER + Description cluster: RAMn power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 on or off in System ON mode. + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 on or off in System ON mode. + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 on or off in System ON mode. + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 on or off in System ON mode. + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 on or off in System ON mode. + 4 + 4 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 on or off in System ON mode. + 5 + 5 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 on or off in System ON mode. + 6 + 6 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 on or off in System ON mode. + 7 + 7 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 on or off in System ON mode. + 8 + 8 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 on or off in System ON mode. + 9 + 9 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 on or off in System ON mode. + 10 + 10 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 on or off in System ON mode. + 11 + 11 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 on or off in System ON mode. + 12 + 12 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 on or off in System ON mode. + 13 + 13 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 on or off in System ON mode. + 14 + 14 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 on or off in System ON mode. + 15 + 15 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is off + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is off + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 when RAM section is off + 18 + 18 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 when RAM section is off + 19 + 19 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 when RAM section is off + 20 + 20 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 when RAM section is off + 21 + 21 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 when RAM section is off + 22 + 22 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 when RAM section is off + 23 + 23 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 when RAM section is off + 24 + 24 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 when RAM section is off + 25 + 25 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 when RAM section is off + 26 + 26 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 when RAM section is off + 27 + 27 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 when RAM section is off + 28 + 28 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 when RAM section is off + 29 + 29 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 when RAM section is off + 30 + 30 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 when RAM section is off + 31 + 31 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAMn power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAMn on or off in System ON mode + 2 + 2 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAMn on or off in System ON mode + 3 + 3 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 of RAMn on or off in System ON mode + 4 + 4 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 of RAMn on or off in System ON mode + 5 + 5 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 of RAMn on or off in System ON mode + 6 + 6 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 of RAMn on or off in System ON mode + 7 + 7 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 of RAMn on or off in System ON mode + 8 + 8 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 of RAMn on or off in System ON mode + 9 + 9 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 of RAMn on or off in System ON mode + 10 + 10 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 of RAMn on or off in System ON mode + 11 + 11 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 of RAMn on or off in System ON mode + 12 + 12 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 of RAMn on or off in System ON mode + 13 + 13 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 of RAMn on or off in System ON mode + 14 + 14 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 of RAMn on or off in System ON mode + 15 + 15 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 when RAM section is switched off + 18 + 18 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 when RAM section is switched off + 19 + 19 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 when RAM section is switched off + 20 + 20 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 when RAM section is switched off + 21 + 21 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 when RAM section is switched off + 22 + 22 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 when RAM section is switched off + 23 + 23 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 when RAM section is switched off + 24 + 24 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 when RAM section is switched off + 25 + 25 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 when RAM section is switched off + 26 + 26 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 when RAM section is switched off + 27 + 27 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 when RAM section is switched off + 28 + 28 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 when RAM section is switched off + 29 + 29 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 when RAM section is switched off + 30 + 30 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 when RAM section is switched off + 31 + 31 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAMn power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S2POWER + Keep RAM section S2 of RAMn on or off in System ON mode + 2 + 2 + + + Off + Off + 1 + + + + + S3POWER + Keep RAM section S3 of RAMn on or off in System ON mode + 3 + 3 + + + Off + Off + 1 + + + + + S4POWER + Keep RAM section S4 of RAMn on or off in System ON mode + 4 + 4 + + + Off + Off + 1 + + + + + S5POWER + Keep RAM section S5 of RAMn on or off in System ON mode + 5 + 5 + + + Off + Off + 1 + + + + + S6POWER + Keep RAM section S6 of RAMn on or off in System ON mode + 6 + 6 + + + Off + Off + 1 + + + + + S7POWER + Keep RAM section S7 of RAMn on or off in System ON mode + 7 + 7 + + + Off + Off + 1 + + + + + S8POWER + Keep RAM section S8 of RAMn on or off in System ON mode + 8 + 8 + + + Off + Off + 1 + + + + + S9POWER + Keep RAM section S9 of RAMn on or off in System ON mode + 9 + 9 + + + Off + Off + 1 + + + + + S10POWER + Keep RAM section S10 of RAMn on or off in System ON mode + 10 + 10 + + + Off + Off + 1 + + + + + S11POWER + Keep RAM section S11 of RAMn on or off in System ON mode + 11 + 11 + + + Off + Off + 1 + + + + + S12POWER + Keep RAM section S12 of RAMn on or off in System ON mode + 12 + 12 + + + Off + Off + 1 + + + + + S13POWER + Keep RAM section S13 of RAMn on or off in System ON mode + 13 + 13 + + + Off + Off + 1 + + + + + S14POWER + Keep RAM section S14 of RAMn on or off in System ON mode + 14 + 14 + + + Off + Off + 1 + + + + + S15POWER + Keep RAM section S15 of RAMn on or off in System ON mode + 15 + 15 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 when RAM section is switched off + 18 + 18 + + + Off + Off + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 when RAM section is switched off + 19 + 19 + + + Off + Off + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 when RAM section is switched off + 20 + 20 + + + Off + Off + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 when RAM section is switched off + 21 + 21 + + + Off + Off + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 when RAM section is switched off + 22 + 22 + + + Off + Off + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 when RAM section is switched off + 23 + 23 + + + Off + Off + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 when RAM section is switched off + 24 + 24 + + + Off + Off + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 when RAM section is switched off + 25 + 25 + + + Off + Off + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 when RAM section is switched off + 26 + 26 + + + Off + Off + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 when RAM section is switched off + 27 + 27 + + + Off + Off + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 when RAM section is switched off + 28 + 28 + + + Off + Off + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 when RAM section is switched off + 29 + 29 + + + Off + Off + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 when RAM section is switched off + 30 + 30 + + + Off + Off + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 when RAM section is switched off + 31 + 31 + + + Off + Off + 1 + + + + + + + + + + P0 + GPIO Port 1 + 0x50000000 + GPIO + + 0 + 0x1000 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x504 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x508 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + 1 + Write: a '1' sets the pin high; a '0' has no effect + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x50C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x510 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x514 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x518 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x51C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 + read-write + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0x524 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x700 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + + + + + P1 + GPIO Port 2 + 0x50000300 + P0 + + + RADIO + 2.4 GHz radio + 0x40001000 + + 0 + 0x1000 + registers + + + RADIO + 1 + + RADIO + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + + + TASKS_TXEN + Enable RADIO in TX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + + + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_START + Start RADIO + 0x008 + write-only + + + TASKS_START + Start RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + + + TASKS_STOP + Stop RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + + + TASKS_DISABLE + Disable RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 + write-only + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTART + Start the bit counter + 0x01C + write-only + + + TASKS_BCSTART + Start the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only + + + TASKS_BCSTOP + Stop the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0x024 + write-only + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTOP + Stop the energy detect measurement + 0x028 + write-only + + + TASKS_EDSTOP + Stop the energy detect measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x02C + write-only + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTOP + Stop the clear channel assessment + 0x030 + write-only + + + TASKS_CCASTOP + Stop the clear channel assessment + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 + read-write + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ADDRESS + Address sent or received + 0x104 + read-write + + + EVENTS_ADDRESS + Address sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 + read-write + + + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + + + EVENTS_END + Packet sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + + + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 + read-write + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0x11C + read-write + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x128 + read-write + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + + + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x138 + read-write + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0x13C + read-write + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x140 + read-write + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x144 + read-write + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x148 + read-write + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCASTOPPED + The CCA has stopped + 0x14C + read-write + + + EVENTS_CCASTOPPED + The CCA has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0x150 + read-write + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x154 + read-write + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x158 + read-write + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_MHRMATCH + MAC header match found + 0x15C + read-write + + + EVENTS_MHRMATCH + MAC header match found + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SYNC + Preamble indicator. + 0x168 + read-write + + + EVENTS_SYNC + Preamble indicator. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + 0x16C + read-write + + + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_START + Shortcut between event READY and task START + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_DISABLE + Shortcut between event END and task DISABLE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_EDSTART + Shortcut between event READY and task EDSTART + 15 + 15 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 16 + 16 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXREADY_START + Shortcut between event TXREADY and task START + 18 + 18 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_START + Shortcut between event RXREADY and task START + 19 + 19 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 20 + 20 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_START + Shortcut between event PHYEND and task START + 21 + 21 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RSSIEND + Write '1' to enable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SYNC + Write '1' to enable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SYNC + Write '1' to disable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CRCSTATUS + CRC status + 0x400 + read-only + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0 + + + CRCOk + Packet received with CRC ok + 1 + + + + + + + RXMATCH + Received address + 0x408 + read-only + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + + + DAI + Device address match index + 0 + 2 + + + + + PDUSTAT + Payload status + 0x414 + read-only + + + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN + 0 + 0 + + + LessThan + Payload less than PCNF1.MAXLEN + 0 + + + GreaterThan + Payload greater than PCNF1.MAXLEN + 1 + + + + + CISTAT + Status on what rate packet is received with in Long Range + 1 + 2 + + + LR125kbit + Frame is received at 125kbps + 0 + + + LR500kbit + Frame is received at 500kbps + 1 + + + + + + + PACKETPTR + Packet pointer + 0x504 + read-write + + + PACKETPTR + Packet pointer + 0 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection. + 8 + 8 + + + Default + Channel map between 2400 MHZ .. 2500 MHz + 0 + + + Low + Channel map between 2360 MHZ .. 2460 MHz + 1 + + + + + + + TXPOWER + Output power + 0x50C + read-write + + + TXPOWER + RADIO output power + 0 + 7 + + + Pos8dBm + +8 dBm + 0x8 + + + Pos7dBm + +7 dBm + 0x7 + + + Pos6dBm + +6 dBm + 0x6 + + + Pos5dBm + +5 dBm + 0x5 + + + Pos4dBm + +4 dBm + 0x4 + + + Pos3dBm + +3 dBm + 0x3 + + + Pos2dBm + +2 dBm + 0x2 + + + 0dBm + 0 dBm + 0x0 + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + Deprecated enumerator - -40 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 + + + + + + + MODE + Data rate and modulation + 0x510 + read-write + + + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbit/s Nordic proprietary radio mode + 0 + + + Nrf_2Mbit + 2 Mbit/s Nordic proprietary radio mode + 1 + + + Ble_1Mbit + 1 Mbit/s BLE + 3 + + + Ble_2Mbit + 2 Mbit/s BLE + 4 + + + Ble_LR125Kbit + Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 5 + + + Ble_LR500Kbit + Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 6 + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbit/s + 15 + + + + + + + PCNF0 + Packet configuration register 0 + 0x514 + read-write + + + LFLEN + Length on air of LENGTH field in number of bits. + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes. + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0 + + + Include + Always include S1 field in RAM independent of S1LEN + 1 + + + + + CILEN + Length of code indicator - long range + 22 + 23 + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0 + + + 16bit + 16-bit preamble + 1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 2 + + + LongRange + Preamble - used for BLE long range + 3 + + + + + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0 + + + Include + LENGTH includes CRC + 1 + + + + + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 + + + + + PCNF1 + Packet configuration register 1 + 0x518 + read-write + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + BASE0 + Base address 0 + 0x51C + read-write + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0x520 + read-write + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 + read-write + + + AP0 + Address prefix 0. + 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 + read-write + + + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CRCCNF + CRC configuration + 0x534 + read-write + + + LEN + CRC length in number of bytes. + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0 + + + One + CRC length is one byte and CRC calculation is enabled + 1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 3 + + + + + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 9 + + + Include + CRC calculation includes address field + 0 + + + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 1 + + + Ieee802154 + CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + 2 + + + + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Interframe spacing in us + 0x544 + read-write + + + TIFS + Interframe spacing in us + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + + + RSSISAMPLE + RSSI sample + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the Disabled state + 0 + + + RxRu + RADIO is in the RXRU state + 1 + + + RxIdle + RADIO is in the RXIDLE state + 2 + + + Rx + RADIO is in the RX state + 3 + + + RxDisable + RADIO is in the RXDISABLED state + 4 + + + TxRu + RADIO is in the TXRU state + 9 + + + TxIdle + RADIO is in the TXIDLE state + 10 + + + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 + + + + + + + DATAWHITEIV + Data whitening initial value + 0x554 + read-write + 0x00000040 + + + DATAWHITEIV + Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MHRMATCHCONF + Search pattern configuration + 0x644 + read-write + + + MHRMATCHCONF + Search pattern configuration + 0 + 31 + + + + + MHRMATCHMAS + Pattern mask + 0x648 + read-write + + + MHRMATCHMAS + Pattern mask + 0 + 31 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + + + Default + Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 + 0 + + + Fast + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + 1 + + + + + DTX + Default TX value + 8 + 9 + + + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' + 1 + + + Center + Transmit center frequency + 2 + + + + + + + SFD + IEEE 802.15.4 start of frame delimiter + 0x660 + read-write + 0x000000A7 + + + SFD + IEEE 802.15.4 start of frame delimiter + 0 + 7 + + + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0x664 + read-write + 0x00000000 + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0 + 20 + + + + + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x668 + read-write + 0x00000000 + + + EDLVL + IEEE 802.15.4 energy detect level + 0 + 7 + + + + + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x66C + read-write + 0x052D0000 + + + CCAMODE + CCA mode of operation + 0 + 2 + + + EdMode + Energy above threshold + 0 + + + CarrierMode + Carrier seen + 1 + + + CarrierAndEdMode + Energy above threshold AND carrier seen + 2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 4 + + + + + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 + + + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. + 16 + 23 + + + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0 + + + Enabled + Peripheral is powered on + 1 + + + + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UART + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + Suspend UART + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + CTS_STARTRX + Shortcut between event CTS and task STARTRX + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + NCTS_STOPRX + Shortcut between event NCTS and task STOPRX + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UART + 0 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + + + + + + PSEL + Unspecified + UART_PSEL + read-write + 0x508 + + RTS + Pin select for RTS + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + + + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + UARTE0 + UART with EasyDMA 0 + 0x40002000 + UART0 + UARTE + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source This register is read/write one to clear. + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + SPI0 + Serial Peripheral Interface 0 + 0x40003000 + SPI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPI + 0x20 + + + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 + read-write + + + EVENTS_READY + TXD byte sent and RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPI + 0x500 + read-write + + + ENABLE + Enable or disable SPI + 0 + 3 + + + Disabled + Disable SPI + 0 + + + Enabled + Enable SPI + 1 + + + + + + + PSEL + Unspecified + SPI_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TX data to send. Double buffered. + 0 + 7 + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + + + SPIM0 + Serial Peripheral Interface Master with EasyDMA 0 + 0x40003000 + SPI0 + SPIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STALLSTAT + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. + 0x400 + read-write + 0x00000000 + + + TX + Stall status for EasyDMA RAM reads + 0 + 0 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + RX + Stall status for EasyDMA RAM writes + 1 + 1 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + M16 + 16 Mbps + 0x0A000000 + + + M32 + 32 Mbps + 0x14000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x560 + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions + 0x004 + read-write + 0x00000002 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + 0 + 7 + + + + + + CSNPOL + Polarity of CSN output + 0x568 + read-write + 0x00000000 + + + CSNPOL + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0 + + + HIGH + Active high (idle state low) + 1 + + + + + + + PSELDCX + Pin select for DCX signal + 0x56C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DCXCNT + DCX configuration + 0x570 + read-write + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + + + SPIS0 + SPI Slave 0 + 0x40003000 + SPI0 + SPIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWI0 + I2C compatible Two-Wire Interface 0 + 0x40003000 + SPI0 + TWI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWI + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDREADY + TWI RXD byte received + 0x108 + read-write + + + EVENTS_RXDREADY + TWI RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C + read-write + + + EVENTS_TXDSENT + TWI TXD byte sent + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + BB_SUSPEND + Shortcut between event BB and task SUSPEND + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + BB_STOP + Shortcut between event BB and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDREADY + Write '1' to enable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDSENT + Write '1' to enable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BB + Write '1' to enable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDREADY + Write '1' to disable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDSENT + Write '1' to disable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BB + Write '1' to disable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0 + + + Present + Read: overrun occured + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable TWI + 0x500 + read-write + + + ENABLE + Enable or disable TWI + 0 + 3 + + + Disabled + Disable TWI + 0 + + + Enabled + Enable TWI + 5 + + + + + + + PSEL + Unspecified + TWI_PSEL + read-write + 0x508 + + SCL + Pin select for SCL + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_SUSPEND + Shortcut between event LASTRX and task SUSPEND + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Indication of which address in {ADDRESS} that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + SPI1 + Serial Peripheral Interface 1 + 0x40004000 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIM1 + Serial Peripheral Interface Master with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIS1 + SPI Slave 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWI1 + I2C compatible Two-Wire Interface 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIM1 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIS1 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + NFCT + NFC-A compatible radio + 0x40005000 + + 0 + 0x1000 + registers + + + NFCT + 5 + + NFCT + 0x20 + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0x000 + write-only + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable NFCT peripheral + 0x004 + write-only + + + TASKS_DISABLE + Disable NFCT peripheral + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0x008 + write-only + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0x00C + write-only + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C + write-only + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only + + + TASKS_GOIDLE + Force state machine to IDLE state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 + write-only + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0x100 + read-write + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 + read-write + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 + read-write + + + EVENTS_FIELDLOST + Remote NFC field lost + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C + read-write + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0x148 + read-write + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0x14C + read-write + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 + read-write + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + FIELDDETECTED_ACTIVATE + Shortcut between event FIELDDETECTED and task ACTIVATE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FIELDLOST_SENSE + Shortcut between event FIELDLOST and task SENSE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXFRAMEEND_ENABLERXDATA + Shortcut between event TXFRAMEEND and task ENABLERXDATA + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDDETECTED + Enable or disable interrupt for event FIELDDETECTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDLOST + Enable or disable interrupt for event FIELDLOST + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMESTART + Enable or disable interrupt for event TXFRAMESTART + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMEEND + Enable or disable interrupt for event TXFRAMEEND + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMESTART + Enable or disable interrupt for event RXFRAMESTART + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMEEND + Enable or disable interrupt for event RXFRAMEEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXERROR + Enable or disable interrupt for event RXERROR + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + AUTOCOLRESSTARTED + Enable or disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COLLISION + Enable or disable interrupt for event COLLISION + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SELECTED + Enable or disable interrupt for event SELECTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDDETECTED + Write '1' to enable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDLOST + Write '1' to enable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMESTART + Write '1' to enable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMEEND + Write '1' to enable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMESTART + Write '1' to enable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMEEND + Write '1' to enable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXERROR + Write '1' to enable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to enable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COLLISION + Write '1' to enable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SELECTED + Write '1' to enable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDDETECTED + Write '1' to disable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDLOST + Write '1' to disable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMESTART + Write '1' to disable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMEEND + Write '1' to disable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMESTART + Write '1' to disable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMEEND + Write '1' to disable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXERROR + Write '1' to disable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COLLISION + Write '1' to disable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SELECTED + Write '1' to disable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + oneToClear + + + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + 0 + 0 + + + + + FRAMESTATUS + Unspecified + NFCT_FRAMESTATUS + read-write + 0x40C + + RX + Result of last incoming frame + 0x000 + read-write + oneToClear + + + CRCERROR + No valid end of frame (EoF) detected + 0 + 0 + + + CRCCorrect + Valid CRC detected + 0 + + + CRCError + CRC received does not match local check + 1 + + + + + PARITYSTATUS + Parity status of received frame + 2 + 2 + + + ParityOK + Frame received with parity OK + 0 + + + ParityError + Frame received with parity error + 1 + + + + + OVERRUN + Overrun detected + 3 + 3 + + + NoOverrun + No overrun detected + 0 + + + Overrun + Overrun error + 1 + + + + + + + + NFCTAGSTATE + NfcTag state register + 0x410 + read-only + + + NFCTAGSTATE + NfcTag state + 0 + 2 + + + Disabled + Disabled or sense + 0 + + + RampUp + RampUp + 2 + + + Idle + Idle + 3 + + + Receive + Receive + 4 + + + FrameDelay + FrameDelay + 5 + + + Transmit + Transmit + 6 + + + + + + + SLEEPSTATE + Sleep state during automatic collision resolution + 0x420 + read-only + 0x00000000 + + + SLEEPSTATE + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. + 0 + 0 + + + Idle + State is IDLE. + 0 + + + SleepA + State is SLEEP_A. + 1 + + + + + + + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C + read-only + + + FIELDPRESENT + Indicates if a valid field is present. Available only in the activated state. + 0 + 0 + + + NoField + No valid field detected + 0 + + + FieldPresent + Valid field detected + 1 + + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + + + NotLocked + Not locked to field + 0 + + + Locked + Locked to field + 1 + + + + + + + FRAMEDELAYMIN + Minimum frame delay + 0x504 + read-write + 0x00000480 + + + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clocks + 0 + 15 + + + + + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + + + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clocks + 0 + 19 + + + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C + read-write + 0x00000001 + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0 + 1 + + + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + 0 + + + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + 1 + + + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX + 2 + + + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 3 + + + + + + + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 + read-write + 0x00000000 + + + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. + 0 + 31 + + + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0x514 + read-write + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0 + 8 + + + + + TXD + Unspecified + NFCT_TXD + read-write + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + + + PARITY + Indicates if parity is added to the frame + 0 + 0 + + + NoParity + Parity is not added to TX frames + 0 + + + Parity + Parity is added to TX frames + 1 + + + + + DISCARDMODE + Discarding unused bits at start or end of a frame + 1 + 1 + + + DiscardEnd + Unused bits are discarded at end of frame (EoF) + 0 + + + DiscardStart + Unused bits are discarded at start of frame (SoF) + 1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + SoF symbol not added + 0 + + + SoF + SoF symbol added + 1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing + 3 + 11 + + + + + + RXD + Unspecified + NFCT_RXD + read-write + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + + + PARITY + Indicates if parity expected in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0 + + + Parity + Parity is expected in RX frames + 1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + SoF symbol is not expected in RX frames + 0 + + + SoF + SoF symbol is expected in RX frames + 1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + + + NFCID1_LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x590 + read-write + 0x00006363 + + + NFCID1_Z + NFCID1 byte Z (very last byte sent) + 0 + 7 + + + NFCID1_Y + NFCID1 byte Y + 8 + 15 + + + NFCID1_X + NFCID1 byte X + 16 + 23 + + + NFCID1_W + NFCID1 byte W + 24 + 31 + + + + + NFCID1_2ND_LAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x594 + read-write + + + NFCID1_V + NFCID1 byte V + 0 + 7 + + + NFCID1_U + NFCID1 byte U + 8 + 15 + + + NFCID1_T + NFCID1 byte T + 16 + 23 + + + + + NFCID1_3RD_LAST + Third last NFCID1 part (10 bytes ID) + 0x598 + read-write + + + NFCID1_S + NFCID1 byte S + 0 + 7 + + + NFCID1_R + NFCID1 byte R + 8 + 15 + + + NFCID1_Q + NFCID1 byte Q + 16 + 23 + + + + + AUTOCOLRESCONFIG + Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. + 0x59C + read-write + 0x00000002 + + + MODE + Enables/disables auto collision resolution + 0 + 0 + + + Enabled + Auto collision resolution enabled + 0 + + + Disabled + Auto collision resolution disabled + 1 + + + + + + + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 + read-write + 0x00000001 + + + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 + + + SDD00000 + SDD pattern 00000 + 0 + + + SDD00001 + SDD pattern 00001 + 1 + + + SDD00010 + SDD pattern 00010 + 2 + + + SDD00100 + SDD pattern 00100 + 4 + + + SDD01000 + SDD pattern 01000 + 8 + + + SDD10000 + SDD pattern 10000 + 16 + + + + + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the auto collision resolution engine. + 6 + 7 + + + NFCID1Single + NFCID1 size: single (4 bytes) + 0 + + + NFCID1Double + NFCID1 size: double (7 bytes) + 1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 2 + + + + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + + + + + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 + read-write + + + RFU10 + Reserved for future use. Shall be 0. + 0 + 1 + + + CASCADE + Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) + 2 + 2 + + + RFU43 + Reserved for future use. Shall be 0. + 3 + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + + + GPIOTE + GPIO Tasks and Events + 0x40006000 + + 0 + 0x1000 + registers + + + GPIOTE + 6 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 8 + 12 + + + PORT + Port number + 13 + 13 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC + Successive approximation register (SAR) analog-to-digital converter + 0x40007000 + + 0 + 0x1000 + registers + + + SAADC + 7 + + SAADC + 0x20 + + + TASKS_START + Starts the SAADC and prepares the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Starts the SAADC and prepares the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Takes one SAADC sample + 0x004 + write-only + + + TASKS_SAMPLE + Takes one SAADC sample + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops the SAADC and terminates all on-going conversions + 0x008 + write-only + + + TASKS_STOP + Stops the SAADC and terminates all on-going conversions + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + The SAADC has started + 0x100 + read-write + + + EVENTS_STARTED + The SAADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The SAADC has filled up the result buffer + 0x104 + read-write + + + EVENTS_END + The SAADC has filled up the result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + Result ready for transfer to RAM + 0x10C + read-write + + + EVENTS_RESULTDONE + Result ready for transfer to RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The SAADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The SAADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last result is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last result is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last result is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last result is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + SAADC is ready. No on-going conversions. + 0 + + + Busy + SAADC is busy. Conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable SAADC + 0x500 + read-write + + + ENABLE + Enable or disable SAADC + 0 + 0 + + + Disabled + Disable SAADC + 0 + + + Enabled + Enable SAADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0x0D + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0x0D + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the SAADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring of a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bits + 0 + + + 10bit + 10 bits + 1 + + + 12bit + 12 bits + 2 + + + 14bit + 14 bits + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0x004 + read-write + + + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0 + 14 + + + + + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task + 0x008 + read-only + + + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + TIMER0 + Timer/Counter 0 + 0x40008000 + TIMER + + 0 + 0x1000 + registers + + + TIMER0 + 8 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER1 + Timer/Counter 1 + 0x40009000 + + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + 0x4000A000 + + TIMER2 + 10 + + + + RTC0 + Real time counter 0 + 0x4000B000 + RTC + + 0 + 0x1000 + registers + + + RTC0 + 11 + + RTC + 0x20 + + + TASKS_START + Start RTC COUNTER + 0x000 + write-only + + + TASKS_START + Start RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC COUNTER + 0x004 + write-only + + + TASKS_STOP + Stop RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC COUNTER + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TICK + Event on COUNTER increment + 0x100 + read-write + + + EVENTS_TICK + Event on COUNTER increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current COUNTER value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + TEMP + Temperature Sensor + 0x4000C000 + + 0 + 0x1000 + registers + + + TEMP + 12 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of first piecewise linear function + 0x520 + read-write + 0x00000326 + + + A0 + Slope of first piecewise linear function + 0 + 11 + + + + + A1 + Slope of second piecewise linear function + 0x524 + read-write + 0x00000348 + + + A1 + Slope of second piecewise linear function + 0 + 11 + + + + + A2 + Slope of third piecewise linear function + 0x528 + read-write + 0x000003AA + + + A2 + Slope of third piecewise linear function + 0 + 11 + + + + + A3 + Slope of fourth piecewise linear function + 0x52C + read-write + 0x0000040E + + + A3 + Slope of fourth piecewise linear function + 0 + 11 + + + + + A4 + Slope of fifth piecewise linear function + 0x530 + read-write + 0x000004BD + + + A4 + Slope of fifth piecewise linear function + 0 + 11 + + + + + A5 + Slope of sixth piecewise linear function + 0x534 + read-write + 0x000005A3 + + + A5 + Slope of sixth piecewise linear function + 0 + 11 + + + + + B0 + y-intercept of first piecewise linear function + 0x540 + read-write + 0x00003FEF + + + B0 + y-intercept of first piecewise linear function + 0 + 13 + + + + + B1 + y-intercept of second piecewise linear function + 0x544 + read-write + 0x00003FBE + + + B1 + y-intercept of second piecewise linear function + 0 + 13 + + + + + B2 + y-intercept of third piecewise linear function + 0x548 + read-write + 0x00003FBE + + + B2 + y-intercept of third piecewise linear function + 0 + 13 + + + + + B3 + y-intercept of fourth piecewise linear function + 0x54C + read-write + 0x00000012 + + + B3 + y-intercept of fourth piecewise linear function + 0 + 13 + + + + + B4 + y-intercept of fifth piecewise linear function + 0x550 + read-write + 0x00000124 + + + B4 + y-intercept of fifth piecewise linear function + 0 + 13 + + + + + B5 + y-intercept of sixth piecewise linear function + 0x554 + read-write + 0x0000027C + + + B5 + y-intercept of sixth piecewise linear function + 0 + 13 + + + + + T0 + End point of first piecewise linear function + 0x560 + read-write + 0x000000E2 + + + T0 + End point of first piecewise linear function + 0 + 7 + + + + + T1 + End point of second piecewise linear function + 0x564 + read-write + 0x00000000 + + + T1 + End point of second piecewise linear function + 0 + 7 + + + + + T2 + End point of third piecewise linear function + 0x568 + read-write + 0x00000019 + + + T2 + End point of third piecewise linear function + 0 + 7 + + + + + T3 + End point of fourth piecewise linear function + 0x56C + read-write + 0x0000003C + + + T3 + End point of fourth piecewise linear function + 0 + 7 + + + + + T4 + End point of fifth piecewise linear function + 0x570 + read-write + 0x00000050 + + + T4 + End point of fifth piecewise linear function + 0 + 7 + + + + + + + RNG + Random Number Generator + 0x4000D000 + + 0 + 0x1000 + registers + + + RNG + 13 + + RNG + 0x20 + + + TASKS_START + Task starting the random number generator + 0x000 + write-only + + + TASKS_START + Task starting the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + + + TASKS_STOP + Task stopping the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + VALRDY_STOP + Shortcut between event VALRDY and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + VALRDY + Write '1' to enable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + VALRDY + Write '1' to disable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + DERCEN + Bias correction + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + VALUE + Output random number + 0x508 + read-only + + + VALUE + Generated random number + 0 + 7 + + + + + + + ECB + AES ECB Mode Encryption + 0x4000E000 + + 0 + 0x1000 + registers + + + ECB + 14 + + ECB + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + + + TASKS_STARTECB + Start ECB block encrypt + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + + + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + + + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + AAR + Accelerated Address Resolver + 0x4000F000 + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + Address resolution procedure complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + + + EVENTS_RESOLVED + Address resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Resolution status + 0x400 + read-only + + + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 3 + + + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity Root Keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM Mode Encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x00C + write-only + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDKSGEN + Keystream generation complete + 0x100 + read-write + + + EVENTS_ENDKSGEN + Keystream generation complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Deprecated register - CCM error event + 0x108 + read-write + + + EVENTS_ERROR + Deprecated field - CCM error event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MICSTATUS + MIC check result + 0x400 + read-only + + + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MIC check failed + 0 + + + CheckPassed + MIC check passed + 1 + + + + + + + ENABLE + Enable + 0x500 + read-write + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + 0 + 0 + + + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode + 1 + + + + + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 + 17 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + LENGTH + Packet length configuration + 24 + 24 + + + Default + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. + 0 + + + Extended + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. + 1 + + + + + + + CNFPTR + Pointer to data structure holding AES key and NONCE vector + 0x508 + read-write + + + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during keystream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended. + 0x518 + read-write + 0x000000FB + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + 0 + 7 + + + + + RATEOVERRIDE + Data rate override setting. + 0x51C + read-write + 0x00000000 + + + RATEOVERRIDE + Data rate override setting. + 0 + 1 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + + + + + WDT + Watchdog Timer + 0x40010000 + + 0 + 0x1000 + registers + + + WDT + 16 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0 + + + Run + Keep the watchdog running while the CPU is sleeping + 1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 1 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + RTC1 + Real time counter 1 + 0x40011000 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + 0x40012000 + + 0 + 0x1000 + registers + + + QDEC + 18 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high + 1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0 + + + 256us + 256 us + 1 + + + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 + + + 4096us + 4096 us + 5 + + + 8192us + 8192 us + 6 + + + 16384us + 16384 us + 7 + + + 32ms + 32768 us + 8 + + + 65ms + 65536 us + 9 + + + 131ms + 131072 us + 10 + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0 + + + 40Smpl + 40 samples/report + 1 + + + 80Smpl + 80 samples/report + 2 + + + 120Smpl + 120 samples/report + 3 + + + 160Smpl + 160 samples/report + 4 + + + 200Smpl + 200 samples/report + 5 + + + 240Smpl + 240 samples/report + 6 + + + 280Smpl + 280 samples/report + 7 + + + 1Smpl + 1 sample/report + 8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0 + + + Enabled + Debounce input filters enabled + 1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + 0x40013000 + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + PSEL + Pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0 + + + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF + 5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 2 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0 + + + Normal + Normal mode + 1 + + + High + High-speed mode + 2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0 + + + Diff + Differential mode + 1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis enabled + 1 + + + + + + + + + LPCOMP + Low-power comparator + 0x40013000 + COMP + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 6 + + + ARef + External analog reference selected + 7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 10 + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 11 + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 12 + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 13 + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 14 + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 15 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 0 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0 + + + Up + Generate ANADETECT on upward crossing only + 1 + + + Down + Generate ANADETECT on downward crossing only + 2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0 + + + Enabled + Comparator hysteresis enabled + 1 + + + + + + + + + EGU0 + Event generator unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU1 + Event generator unit 1 + 0x40015000 + + SWI1_EGU1 + 21 + + + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 + + SWI1_EGU1 + 21 + + + + EGU2 + Event generator unit 2 + 0x40016000 + + SWI2_EGU2 + 22 + + + + SWI2 + Software interrupt 2 + 0x40016000 + EGU2 + + SWI2_EGU2 + 22 + + + + EGU3 + Event generator unit 3 + 0x40017000 + + SWI3_EGU3 + 23 + + + + SWI3 + Software interrupt 3 + 0x40017000 + EGU3 + + SWI3_EGU3 + 23 + + + + EGU4 + Event generator unit 4 + 0x40018000 + + SWI4_EGU4 + 24 + + + + SWI4 + Software interrupt 4 + 0x40018000 + EGU4 + + SWI4_EGU4 + 24 + + + + EGU5 + Event generator unit 5 + 0x40019000 + + SWI5_EGU5 + 25 + + + + SWI5 + Software interrupt 5 + 0x40019000 + EGU5 + + SWI5_EGU5 + 25 + + + + TIMER3 + Timer/Counter 3 + 0x4001A000 + + TIMER3 + 26 + + + + TIMER4 + Timer/Counter 4 + 0x4001B000 + + TIMER4 + 27 + + + + PWM0 + Pulse width modulation unit 0 + 0x4001C000 + PWM + + 0 + 0x1000 + registers + + + PWM0 + 28 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x4001D000 + + 0 + 0x1000 + registers + + + PDM + 29 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency configuration + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + + + RATIO + Selects the ratio between PDM_CLK and output sample rate + 0 + 0 + + + Ratio64 + Ratio of 64 + 0 + + + Ratio80 + Ratio of 80 + 1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + ACL + Access control lists + 0x4001E000 + + 0 + 0x1000 + registers + + ACL + 0x20 + + + 8 + 0x010 + ACL[%s] + Unspecified + ACL_ACL + read-write + 0x800 + + ADDR + Description cluster: Start address of region to protect. The start address must be word-aligned. + 0x000 + read-writeonce + 0x00000000 + + + ADDR + Start address of flash region n. The start address must point to a flash page boundary. + 0 + 31 + + + + + SIZE + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + 0x004 + read-writeonce + 0x00000000 + + + SIZE + Size of flash region n in bytes. Must be a multiple of the flash page size. + 0 + 31 + + + + + PERM + Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE + 0x008 + read-writeonce + 0x00000000 + + + WRITE + Configure write and erase permissions for region n. Write '0' has no effect. + 1 + 1 + + + Enable + Allow write and erase instructions to region n + 0 + + + Disable + Block write and erase instructions to region n + 1 + + + + + READ + Configure read permissions for region n. Write '0' has no effect. + 2 + 2 + + + Enable + Allow read instructions to region n + 0 + + + Disable + Block read instructions to region n + 1 + + + + + + + + + + NVMC + Non Volatile Memory Controller + 0x4001E000 + ACL + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + ERASEPAGE + Register for erasing a page in code area + 0x508 + write-only + + + ERASEPAGE + Register for starting erase of a page in code area + 0 + 31 + + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE + 0x508 + write-only + ERASEPAGE + + + ERASEPCR1 + Register for erasing a page in code area, equivalent to ERASEPAGE + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + + + ERASEALL + Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE + 0x510 + write-only + + + ERASEPCR0 + Register for starting erase of a page in code area, equivalent to ERASEPAGE + 0 + 31 + + + + + ERASEUICR + Register for erasing user information configuration registers + 0x514 + write-only + + + ERASEUICR + Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of UICR + 1 + + + + + + + ERASEPAGEPARTIAL + Register for partial erase of a page in code area + 0x518 + write-only + + + ERASEPAGEPARTIAL + Register for starting partial erase of a page in code area + 0 + 31 + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + ICACHECNF + I-code cache configuration register + 0x540 + read-write + 0x00000000 + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0 + + + Enabled + Enable cache + 1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0 + + + Enabled + Enable cache profiling + 1 + + + + + + + IHIT + I-code cache hit counter + 0x548 + read-write + + + HITS + Number of cache hits. Register is writable, but only to '0'. + 0 + 31 + + + + + IMISS + I-code cache miss counter + 0x54C + read-write + + + MISSES + Number of cache misses. Register is writable, but only to '0'. + 0 + 31 + + + + + + + PPI + Programmable Peripheral Interconnect + 0x4001F000 + + 0 + 0x1000 + registers + + PPI + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing '0' has no effect. + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing '0' has no effect. + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing '0' has no effect. + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing '0' has no effect. + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing '0' has no effect. + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing '0' has no effect. + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing '0' has no effect. + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing '0' has no effect. + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing '0' has no effect. + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing '0' has no effect. + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing '0' has no effect. + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing '0' has no effect. + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing '0' has no effect. + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing '0' has no effect. + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing '0' has no effect. + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing '0' has no effect. + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing '0' has no effect. + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing '0' has no effect. + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing '0' has no effect. + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing '0' has no effect. + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing '0' has no effect. + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing '0' has no effect. + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing '0' has no effect. + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing '0' has no effect. + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing '0' has no effect. + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing '0' has no effect. + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing '0' has no effect. + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing '0' has no effect. + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing '0' has no effect. + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing '0' has no effect. + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing '0' has no effect. + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing '0' has no effect. + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing '0' has no effect. + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing '0' has no effect. + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing '0' has no effect. + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing '0' has no effect. + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing '0' has no effect. + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing '0' has no effect. + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing '0' has no effect. + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing '0' has no effect. + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing '0' has no effect. + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing '0' has no effect. + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing '0' has no effect. + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing '0' has no effect. + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing '0' has no effect. + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing '0' has no effect. + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing '0' has no effect. + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing '0' has no effect. + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing '0' has no effect. + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing '0' has no effect. + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing '0' has no effect. + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing '0' has no effect. + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing '0' has no effect. + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing '0' has no effect. + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing '0' has no effect. + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing '0' has no effect. + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing '0' has no effect. + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing '0' has no effect. + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing '0' has no effect. + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing '0' has no effect. + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing '0' has no effect. + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing '0' has no effect. + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing '0' has no effect. + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing '0' has no effect. + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + + + 20 + 0x008 + CH[%s] + PPI Channel + PPI_CH + read-write + 0x510 + + EEP + Description cluster: Channel n event endpoint + 0x000 + read-write + + + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. + 0 + 31 + + + + + TEP + Description cluster: Channel n task endpoint + 0x004 + read-write + + + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. + 0 + 31 + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + 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channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + 32 + 0x004 + FORK[%s] + Fork + PPI_FORK + read-write + 0x910 + + TEP + Description cluster: Channel n task endpoint + 0x000 + read-write + + + TEP + Pointer to task register + 0 + 31 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Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1WA + Write '1' to enable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1RA + Write '1' to enable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + + + REGION0WA + Write '1' to disable interrupt for event REGION0WA + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION0RA + Write '1' to disable interrupt for event REGION0RA + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1WA + Write '1' to disable interrupt for event REGION1WA + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1RA + Write '1' to disable interrupt for event REGION1RA + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2WA + Write '1' to disable interrupt for event REGION2WA + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2RA + Write '1' to disable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3WA + Write '1' to disable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3RA + Write '1' to disable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0WA + Write '1' to disable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 2 + 0x008 + PERREGION[%s] + Unspecified + MWU_PERREGION + read-write + 0x400 + + SUBSTATWA + Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching + 0x000 + read-write + oneToClear + + + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + + + SUBSTATRA + Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching + 0x004 + read-write + oneToClear + + + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + + + + REGIONEN + Enable/disable regions watch + 0x510 + read-write + + + RGN0WA + Enable/disable write access watch in region[0] + 0 + 0 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable/disable read access watch in region[0] + 1 + 1 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable/disable write access watch in region[1] + 2 + 2 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable/disable read access watch in region[1] + 3 + 3 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable/disable write access watch in region[2] + 4 + 4 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable/disable read access watch in region[2] + 5 + 5 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable/disable write access watch in region[3] + 6 + 6 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable/disable read access watch in region[3] + 7 + 7 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable/disable write access watch in PREGION[0] + 24 + 24 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable/disable read access watch in PREGION[0] + 25 + 25 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable/disable write access watch in PREGION[1] + 26 + 26 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable/disable read access watch in PREGION[1] + 27 + 27 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENSET + Enable regions watch + 0x514 + read-write + + + RGN0WA + Enable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENCLR + Disable regions watch + 0x518 + read-write + + + RGN0WA + Disable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN0RA + Disable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN1WA + Disable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN1RA + Disable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN2WA + Disable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN2RA + Disable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN3WA + Disable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN3RA + Disable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + PRGN0WA + Disable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN0RA + Disable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + PRGN1WA + Disable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN1RA + Disable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + + + 4 + 0x010 + REGION[%s] + Unspecified + MWU_REGION + read-write + 0x600 + + START + Description cluster: Start address for region n + 0x000 + read-write + 0x00000000 + + + START + Start address for region + 0 + 31 + + + + + END + Description cluster: End address of region n + 0x004 + read-write + + + END + End address of region. + 0 + 31 + + + + + + 2 + 0x010 + PREGION[%s] + Unspecified + MWU_PREGION + read-write + 0x6C0 + + START + Description cluster: Reserved for future use + 0x000 + read-only + + + START + Reserved for future use + 0 + 31 + + + + + END + Description cluster: Reserved for future use + 0x004 + read-only + + + END + Reserved for future use + 0 + 31 + + + + + SUBS + Description cluster: Subregions of region n + 0x008 + read-write + 0x00000000 + + + SR0 + Include or exclude subregion 0 in region + 0 + 0 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR1 + Include or exclude subregion 1 in region + 1 + 1 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR2 + Include or exclude subregion 2 in region + 2 + 2 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR3 + Include or exclude subregion 3 in region + 3 + 3 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR4 + Include or exclude subregion 4 in region + 4 + 4 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR5 + Include or exclude subregion 5 in region + 5 + 5 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR6 + Include or exclude subregion 6 in region + 6 + 6 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR7 + Include or exclude subregion 7 in region + 7 + 7 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR8 + Include or exclude subregion 8 in region + 8 + 8 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR9 + Include or exclude subregion 9 in region + 9 + 9 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR10 + Include or exclude subregion 10 in region + 10 + 10 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR11 + Include or exclude subregion 11 in region + 11 + 11 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR12 + Include or exclude subregion 12 in region + 12 + 12 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR13 + Include or exclude subregion 13 in region + 13 + 13 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR14 + Include or exclude subregion 14 in region + 14 + 14 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR15 + Include or exclude subregion 15 in region + 15 + 15 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR16 + Include or exclude subregion 16 in region + 16 + 16 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR17 + Include or exclude subregion 17 in region + 17 + 17 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR18 + Include or exclude subregion 18 in region + 18 + 18 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR19 + Include or exclude subregion 19 in region + 19 + 19 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR20 + Include or exclude subregion 20 in region + 20 + 20 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR21 + Include or exclude subregion 21 in region + 21 + 21 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR22 + Include or exclude subregion 22 in region + 22 + 22 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR23 + Include or exclude subregion 23 in region + 23 + 23 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR24 + Include or exclude subregion 24 in region + 24 + 24 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR25 + Include or exclude subregion 25 in region + 25 + 25 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR26 + Include or exclude subregion 26 in region + 26 + 26 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR27 + Include or exclude subregion 27 in region + 27 + 27 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR28 + Include or exclude subregion 28 in region + 28 + 28 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR29 + Include or exclude subregion 29 in region + 29 + 29 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR30 + Include or exclude subregion 30 in region + 30 + 30 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR31 + Include or exclude subregion 31 in region + 31 + 31 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + + + + + + PWM1 + Pulse width modulation unit 1 + 0x40021000 + + PWM1 + 33 + + + + PWM2 + Pulse width modulation unit 2 + 0x40022000 + + PWM2 + 34 + + + + SPI2 + Serial Peripheral Interface 2 + 0x40023000 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIM2 + Serial Peripheral Interface Master with EasyDMA 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIS2 + SPI Slave 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + RTC2 + Real time counter 2 + 0x40024000 + + RTC2 + 36 + + + + I2S + Inter-IC Sound + 0x40025000 + + 0 + 0x1000 + registers + + + I2S + 37 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0x000 + write-only + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0x004 + write-only + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable I2S module. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode. + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode. + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable. + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable. + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + Master clock generator frequency. + 0x010 + read-write + 0x20000000 + + + MCKFREQ + Master clock generator frequency. + 0 + 31 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio. + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio. + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width. + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample width. + 0 + 1 + + + 8Bit + 8 bit. + 0 + + + 16Bit + 16 bit. + 1 + + + 24Bit + 24 bit. + 2 + + + + + + + ALIGN + Alignment of sample within a frame. + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame. + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format. + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format. + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels. + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels. + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal. + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal. + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + FPU + FPU + 0x40026000 + + 0 + 0x1000 + registers + + + FPU + 38 + + FPU + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + USBD + Universal serial bus device + 0x40027000 + + 0 + 0x1000 + registers + + + USBD + 39 + + USBD + 0x20 + + + 0x8 + 0x4 + TASKS_STARTEPIN[%s] + Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0x004 + write-only + + + TASKS_STARTEPIN + Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0x024 + write-only + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_STARTEPOUT[%s] + Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0x028 + write-only + + + TASKS_STARTEPOUT + Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0x048 + write-only + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0x04C + write-only + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0x050 + write-only + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0x054 + write-only + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0x058 + write-only + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0x05C + write-only + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0x100 + read-write + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0x104 + read-write + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPIN[%s] + Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x108 + read-write + + + EVENTS_ENDEPIN + The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0x128 + read-write + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0x12C + read-write + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPOUT[%s] + Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x130 + read-write + + + EVENTS_ENDEPOUT + The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0x150 + read-write + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0x154 + read-write + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0x158 + read-write + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0x15C + read-write + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0x160 + read-write + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + EP0DATADONE_STARTEPIN0 + Shortcut between event EP0DATADONE and task STARTEPIN[0] + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_STARTEPOUT0 + Shortcut between event EP0DATADONE and task STARTEPOUT[0] + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_EP0STATUS + Shortcut between event EP0DATADONE and task EP0STATUS + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0STATUS + Shortcut between event ENDEPOUT[0] and task EP0STATUS + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0RCVOUT + Shortcut between event ENDEPOUT[0] and task EP0RCVOUT + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + USBRESET + Enable or disable interrupt for event USBRESET + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN0 + Enable or disable interrupt for event ENDEPIN[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN1 + Enable or disable interrupt for event ENDEPIN[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN2 + Enable or disable interrupt for event ENDEPIN[2] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN3 + Enable or disable interrupt for event ENDEPIN[3] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN4 + Enable or disable interrupt for event ENDEPIN[4] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN5 + Enable or disable interrupt for event ENDEPIN[5] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN6 + Enable or disable interrupt for event ENDEPIN[6] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN7 + Enable or disable interrupt for event ENDEPIN[7] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0DATADONE + Enable or disable interrupt for event EP0DATADONE + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOIN + Enable or disable interrupt for event ENDISOIN + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT0 + Enable or disable interrupt for event ENDEPOUT[0] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT1 + Enable or disable interrupt for event ENDEPOUT[1] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT2 + Enable or disable interrupt for event ENDEPOUT[2] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT3 + Enable or disable interrupt for event ENDEPOUT[3] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT4 + Enable or disable interrupt for event ENDEPOUT[4] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT5 + Enable or disable interrupt for event ENDEPOUT[5] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT6 + Enable or disable interrupt for event ENDEPOUT[6] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT7 + Enable or disable interrupt for event ENDEPOUT[7] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOOUT + Enable or disable interrupt for event ENDISOOUT + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SOF + Enable or disable interrupt for event SOF + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + USBEVENT + Enable or disable interrupt for event USBEVENT + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0SETUP + Enable or disable interrupt for event EP0SETUP + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EPDATA + Enable or disable interrupt for event EPDATA + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + USBRESET + Write '1' to enable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN0 + Write '1' to enable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN1 + Write '1' to enable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN2 + Write '1' to enable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN3 + Write '1' to enable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN4 + Write '1' to enable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN5 + Write '1' to enable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN6 + Write '1' to enable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN7 + Write '1' to enable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0DATADONE + Write '1' to enable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOIN + Write '1' to enable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT0 + Write '1' to enable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT1 + Write '1' to enable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT2 + Write '1' to enable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT3 + Write '1' to enable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT4 + Write '1' to enable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT5 + Write '1' to enable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT6 + Write '1' to enable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT7 + Write '1' to enable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOOUT + Write '1' to enable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SOF + Write '1' to enable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBEVENT + Write '1' to enable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0SETUP + Write '1' to enable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EPDATA + Write '1' to enable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + USBRESET + Write '1' to disable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN0 + Write '1' to disable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN1 + Write '1' to disable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN2 + Write '1' to disable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN3 + Write '1' to disable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN4 + Write '1' to disable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN5 + Write '1' to disable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN6 + Write '1' to disable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN7 + Write '1' to disable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0DATADONE + Write '1' to disable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOIN + Write '1' to disable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT0 + Write '1' to disable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT1 + Write '1' to disable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT2 + Write '1' to disable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT3 + Write '1' to disable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT4 + Write '1' to disable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT5 + Write '1' to disable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT6 + Write '1' to disable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT7 + Write '1' to disable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOOUT + Write '1' to disable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SOF + Write '1' to disable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBEVENT + Write '1' to disable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0SETUP + Write '1' to disable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EPDATA + Write '1' to disable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVENTCAUSE + Details on what caused the USBEVENT event + 0x400 + read-write + oneToClear + + + ISOOUTCRC + CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. + 0 + 0 + + + NotDetected + No error detected + 0 + + + Detected + Error detected + 1 + + + + + SUSPEND + Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. + 8 + 8 + + + NotDetected + Suspend not detected + 0 + + + Detected + Suspend detected + 1 + + + + + RESUME + Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. + 9 + 9 + + + NotDetected + Resume not detected + 0 + + + Detected + Resume detected + 1 + + + + + USBWUALLOWED + USB MAC has been woken up and operational. Write '1' to clear. + 10 + 10 + + + NotAllowed + Wake up not allowed + 0 + + + Allowed + Wake up allowed + 1 + + + + + READY + USB device is ready for normal operation. Write '1' to clear. + 11 + 11 + + + NotDetected + USBEVENT was not issued due to USBD peripheral ready + 0 + + + Ready + USBD peripheral is ready + 1 + + + + + + + HALTED + Unspecified + USBD_HALTED + read-write + 0x420 + + 0x8 + 0x4 + EPIN[%s] + Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x000 + read-only + + + GETSTATUS + IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + 0x8 + 0x4 + EPOUT[%s] + Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x024 + read-only + + + GETSTATUS + OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + + EPSTATUS + Provides information on which endpoint's EasyDMA registers have been captured + 0x468 + read-write + oneToClear + + + EPIN0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 0 + 0 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 1 + 1 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 2 + 2 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 3 + 3 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 4 + 4 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 5 + 5 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 6 + 6 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 7 + 7 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 8 + 8 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 16 + 16 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 17 + 17 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 18 + 18 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 19 + 19 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 20 + 20 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 21 + 21 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 22 + 22 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 23 + 23 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 24 + 24 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + + + EPDATASTATUS + Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) + 0x46C + read-write + oneToClear + + + EPIN1 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 1 + 1 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN2 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 2 + 2 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN3 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 3 + 3 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN4 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 4 + 4 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN5 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 5 + 5 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN6 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 6 + 6 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN7 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 7 + 7 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT1 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 17 + 17 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT2 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 18 + 18 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT3 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 19 + 19 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT4 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 20 + 20 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT5 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 21 + 21 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT6 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 22 + 22 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT7 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 23 + 23 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + + + USBADDR + Device USB address + 0x470 + read-only + + + ADDR + Device USB address + 0 + 6 + + + + + BMREQUESTTYPE + SETUP data, byte 0, bmRequestType + 0x480 + read-only + 0x00000000 + + + RECIPIENT + Data transfer type + 0 + 4 + + + Device + Device + 0 + + + Interface + Interface + 1 + + + Endpoint + Endpoint + 2 + + + Other + Other + 3 + + + + + TYPE + Data transfer type + 5 + 6 + + + Standard + Standard + 0 + + + Class + Class + 1 + + + Vendor + Vendor + 2 + + + + + DIRECTION + Data transfer direction + 7 + 7 + + + HostToDevice + Host-to-device + 0 + + + DeviceToHost + Device-to-host + 1 + + + + + + + BREQUEST + SETUP data, byte 1, bRequest + 0x484 + read-only + 0x00000000 + + + BREQUEST + SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. + 0 + 7 + + + STD_GET_STATUS + Standard request GET_STATUS + 0 + + + STD_CLEAR_FEATURE + Standard request CLEAR_FEATURE + 1 + + + STD_SET_FEATURE + Standard request SET_FEATURE + 3 + + + STD_SET_ADDRESS + Standard request SET_ADDRESS + 5 + + + STD_GET_DESCRIPTOR + Standard request GET_DESCRIPTOR + 6 + + + STD_SET_DESCRIPTOR + Standard request SET_DESCRIPTOR + 7 + + + STD_GET_CONFIGURATION + Standard request GET_CONFIGURATION + 8 + + + STD_SET_CONFIGURATION + Standard request SET_CONFIGURATION + 9 + + + STD_GET_INTERFACE + Standard request GET_INTERFACE + 10 + + + STD_SET_INTERFACE + Standard request SET_INTERFACE + 11 + + + STD_SYNCH_FRAME + Standard request SYNCH_FRAME + 12 + + + + + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0x488 + read-only + 0x00000000 + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0 + 7 + + + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0x48C + read-only + 0x00000000 + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0 + 7 + + + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0x490 + read-only + 0x00000000 + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0 + 7 + + + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0x494 + read-only + 0x00000000 + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0 + 7 + + + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0x498 + read-only + 0x00000000 + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0 + 7 + + + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0x49C + read-only + 0x00000000 + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0 + 7 + + + + + SIZE + Unspecified + USBD_SIZE + read-write + 0x4A0 + + 0x8 + 0x4 + EPOUT[%s] + Description collection: Number of bytes received last in the data stage of this OUT endpoint + 0x000 + read-write + + + SIZE + Number of bytes received last in the data stage of this OUT endpoint + 0 + 6 + + + + + ISOOUT + Number of bytes received last on this ISO OUT data endpoint + 0x020 + read-only + 0x00010000 + + + SIZE + Number of bytes received last on this ISO OUT data endpoint + 0 + 9 + + + ZERO + Zero-length data packet received + 16 + 16 + + + Normal + No zero-length data received, use value in SIZE + 0 + + + ZeroData + Zero-length data received, ignore value in SIZE + 1 + + + + + + + + ENABLE + Enable USB + 0x500 + read-write + + + ENABLE + Enable USB + 0 + 0 + + + Disabled + USB peripheral is disabled + 0 + + + Enabled + USB peripheral is enabled + 1 + + + + + + + USBPULLUP + Control of the USB pull-up + 0x504 + read-write + + + CONNECT + Control of the USB pull-up on the D+ line + 0 + 0 + + + Disabled + Pull-up is disconnected + 0 + + + Enabled + Pull-up is connected to D+ + 1 + + + + + + + DPDMVALUE + State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). + 0x508 + read-write + + + STATE + State D+ and D- lines will be forced into by the DPDMDRIVE task + 0 + 4 + + + Resume + D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) + 1 + + + J + D+ forced high, D- forced low (J state) + 2 + + + K + D+ forced low, D- forced high (K state) + 4 + + + + + + + DTOGGLE + Data toggle control and status + 0x50C + read-write + 0x00000100 + + + EP + Select bulk endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + VALUE + Data toggle value + 8 + 9 + + + Nop + No action on data toggle when writing the register with this value + 0 + + + Data0 + Data toggle is DATA0 on endpoint set by EP and IO + 1 + + + Data1 + Data toggle is DATA1 on endpoint set by EP and IO + 2 + + + + + + + EPINEN + Endpoint IN enable + 0x510 + read-write + 0x00000001 + + + IN0 + Enable IN endpoint 0 + 0 + 0 + + + Disable + Disable endpoint IN 0 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 0 (response to IN tokens) + 1 + + + + + IN1 + Enable IN endpoint 1 + 1 + 1 + + + Disable + Disable endpoint IN 1 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 1 (response to IN tokens) + 1 + + + + + IN2 + Enable IN endpoint 2 + 2 + 2 + + + Disable + Disable endpoint IN 2 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 2 (response to IN tokens) + 1 + + + + + IN3 + Enable IN endpoint 3 + 3 + 3 + + + Disable + Disable endpoint IN 3 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 3 (response to IN tokens) + 1 + + + + + IN4 + Enable IN endpoint 4 + 4 + 4 + + + Disable + Disable endpoint IN 4 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 4 (response to IN tokens) + 1 + + + + + IN5 + Enable IN endpoint 5 + 5 + 5 + + + Disable + Disable endpoint IN 5 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 5 (response to IN tokens) + 1 + + + + + IN6 + Enable IN endpoint 6 + 6 + 6 + + + Disable + Disable endpoint IN 6 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 6 (response to IN tokens) + 1 + + + + + IN7 + Enable IN endpoint 7 + 7 + 7 + + + Disable + Disable endpoint IN 7 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 7 (response to IN tokens) + 1 + + + + + ISOIN + Enable ISO IN endpoint + 8 + 8 + + + Disable + Disable ISO IN endpoint 8 + 0 + + + Enable + Enable ISO IN endpoint 8 + 1 + + + + + + + EPOUTEN + Endpoint OUT enable + 0x514 + read-write + 0x00000001 + + + OUT0 + Enable OUT endpoint 0 + 0 + 0 + + + Disable + Disable endpoint OUT 0 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 0 (response to OUT tokens) + 1 + + + + + OUT1 + Enable OUT endpoint 1 + 1 + 1 + + + Disable + Disable endpoint OUT 1 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 1 (response to OUT tokens) + 1 + + + + + OUT2 + Enable OUT endpoint 2 + 2 + 2 + + + Disable + Disable endpoint OUT 2 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 2 (response to OUT tokens) + 1 + + + + + OUT3 + Enable OUT endpoint 3 + 3 + 3 + + + Disable + Disable endpoint OUT 3 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 3 (response to OUT tokens) + 1 + + + + + OUT4 + Enable OUT endpoint 4 + 4 + 4 + + + Disable + Disable endpoint OUT 4 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 4 (response to OUT tokens) + 1 + + + + + OUT5 + Enable OUT endpoint 5 + 5 + 5 + + + Disable + Disable endpoint OUT 5 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 5 (response to OUT tokens) + 1 + + + + + OUT6 + Enable OUT endpoint 6 + 6 + 6 + + + Disable + Disable endpoint OUT 6 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 6 (response to OUT tokens) + 1 + + + + + OUT7 + Enable OUT endpoint 7 + 7 + 7 + + + Disable + Disable endpoint OUT 7 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 7 (response to OUT tokens) + 1 + + + + + ISOOUT + Enable ISO OUT endpoint 8 + 8 + 8 + + + Disable + Disable ISO OUT endpoint 8 + 0 + + + Enable + Enable ISO OUT endpoint 8 + 1 + + + + + + + EPSTALL + STALL endpoints + 0x518 + write-only + 0x00000000 + modifyExternal + + + EP + Select endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + STALL + Stall selected endpoint + 8 + 8 + + + UnStall + Don't stall selected endpoint + 0 + + + Stall + Stall selected endpoint + 1 + + + + + + + ISOSPLIT + Controls the split of ISO buffers + 0x51C + read-write + + + SPLIT + Controls the split of ISO buffers + 0 + 15 + + + OneDir + Full buffer dedicated to either ISO IN or OUT + 0x0000 + + + HalfIN + Lower half for IN, upper half for OUT + 0x0080 + + + + + + + FRAMECNTR + Returns the current value of the start of frame counter + 0x520 + read-only + + + FRAMECNTR + Returns the current value of the start of frame counter + 0 + 10 + + + + + LOWPOWER + Controls USBD peripheral low power mode during USB suspend + 0x52C + read-write + 0x00000000 + + + LOWPOWER + Controls USBD peripheral low-power mode during USB suspend + 0 + 0 + + + ForceNormal + Software must write this value to exit low power mode and before performing a remote wake-up + 0 + + + LowPower + Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral + 1 + + + + + + + ISOINCONFIG + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0x530 + read-write + + + RESPONSE + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0 + 0 + + + NoResp + Endpoint does not respond in that case + 0 + + + ZeroData + Endpoint responds with a zero-length data packet in that case + 1 + + + + + + + 8 + 0x014 + EPIN[%s] + Unspecified + USBD_EPIN + read-write + 0x600 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOIN + Unspecified + USBD_ISOIN + read-write + 0x6A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + 8 + 0x014 + EPOUT[%s] + Unspecified + USBD_EPOUT + read-write + 0x700 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOOUT + Unspecified + USBD_ISOOUT + read-write + 0x7A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + + + UARTE1 + UART with EasyDMA 1 + 0x40028000 + + UARTE1 + 40 + + + + QSPI + External flash interface + 0x40029000 + + 0 + 0x1000 + registers + + + QSPI + 41 + + QSPI + 0x20 + + + TASKS_ACTIVATE + Activate QSPI interface + 0x000 + write-only + + + TASKS_ACTIVATE + Activate QSPI interface + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0x004 + write-only + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0x008 + write-only + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ERASESTART + Start external flash memory erase operation + 0x00C + write-only + + + TASKS_ERASESTART + Start external flash memory erase operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0x010 + write-only + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + 0x100 + read-write + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable QSPI peripheral and acquire the pins selected in PSELn registers + 0x500 + read-write + + + ENABLE + Enable or disable QSPI + 0 + 0 + + + Disabled + Disable QSPI + 0 + + + Enabled + Enable QSPI + 1 + + + + + + + READ + Unspecified + QSPI_READ + read-write + 0x504 + + SRC + Flash memory source address + 0x000 + read-write + + + SRC + Word-aligned flash memory source address. + 0 + 31 + + + + + DST + RAM destination address + 0x004 + read-write + + + DST + Word-aligned RAM destination address. + 0 + 31 + + + + + CNT + Read transfer length + 0x008 + read-write + + + CNT + Read transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 17 + + + + + + WRITE + Unspecified + QSPI_WRITE + read-write + 0x510 + + DST + Flash destination address + 0x000 + read-write + + + DST + Word-aligned flash destination address. + 0 + 31 + + + + + SRC + RAM source address + 0x004 + read-write + + + SRC + Word-aligned RAM source address. + 0 + 31 + + + + + CNT + Write transfer length + 0x008 + read-write + + + CNT + Write transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 17 + + + + + + ERASE + Unspecified + QSPI_ERASE + read-write + 0x51C + + PTR + Start address of flash block to be erased + 0x000 + read-write + + + PTR + Word-aligned start address of block to be erased. + 0 + 31 + + + + + LEN + Size of block to be erased. + 0x004 + read-write + + + LEN + LEN + 0 + 1 + + + 4KB + Erase 4 kB block (flash command 0x20) + 0 + + + 64KB + Erase 64 kB block (flash command 0xD8) + 1 + + + All + Erase all (flash command 0xC7) + 2 + + + + + + + + PSEL + Unspecified + QSPI_PSEL + read-write + 0x524 + + SCK + Pin select for serial clock SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for chip select signal CSN. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO0 + Pin select for serial data MOSI/IO0. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO1 + Pin select for serial data MISO/IO1. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO2 + Pin select for serial data IO2. + 0x014 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO3 + Pin select for serial data IO3. + 0x018 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. + 0x540 + read-write + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. + 0 + 31 + + + + + IFCONFIG0 + Interface configuration. + 0x544 + read-write + + + READOC + Configure number of data lines and opcode used for reading. + 0 + 2 + + + FASTREAD + Single data line SPI. FAST_READ (opcode 0x0B). + 0 + + + READ2O + Dual data line SPI. READ2O (opcode 0x3B). + 1 + + + READ2IO + Dual data line SPI. READ2IO (opcode 0xBB). + 2 + + + READ4O + Quad data line SPI. READ4O (opcode 0x6B). + 3 + + + READ4IO + Quad data line SPI. READ4IO (opcode 0xEB). + 4 + + + + + WRITEOC + Configure number of data lines and opcode used for writing. + 3 + 5 + + + PP + Single data line SPI. PP (opcode 0x02). + 0 + + + PP2O + Dual data line SPI. PP2O (opcode 0xA2). + 1 + + + PP4O + Quad data line SPI. PP4O (opcode 0x32). + 2 + + + PP4IO + Quad data line SPI. PP4IO (opcode 0x38). + 3 + + + + + ADDRMODE + Addressing mode. + 6 + 6 + + + 24BIT + 24-bit addressing. + 0 + + + 32BIT + 32-bit addressing. + 1 + + + + + DPMENABLE + Enable deep power-down mode (DPM) feature. + 7 + 7 + + + Disable + Disable DPM feature. + 0 + + + Enable + Enable DPM feature. + 1 + + + + + PPSIZE + Page size for commands PP, PP2O, PP4O and PP4IO. + 12 + 12 + + + 256Bytes + 256 bytes. + 0 + + + 512Bytes + 512 bytes. + 1 + + + + + + + IFCONFIG1 + Interface configuration. + 0x600 + read-write + 0x00040480 + + + SCKDELAY + Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). + 0 + 7 + + + DPMEN + Enter/exit deep power-down mode (DPM) for external flash memory. + 24 + 24 + + + Exit + Exit DPM. + 0 + + + Enter + Enter DPM. + 1 + + + + + SPIMODE + Select SPI mode. + 25 + 25 + + + MODE0 + Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). + 0 + + + MODE3 + Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). + 1 + + + + + SCKFREQ + SCK frequency is given as 32 MHz / (SCKFREQ + 1). + 28 + 31 + + + + + STATUS + Status register. + 0x604 + read-only + + + DPM + Deep power-down mode (DPM) status of external flash. + 2 + 2 + + + Disabled + External flash is not in DPM. + 0 + + + Enabled + External flash is in DPM. + 1 + + + + + READY + Ready status. + 3 + 3 + + + READY + QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. + 1 + + + BUSY + QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. + 0 + + + + + SREG + Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. + 24 + 31 + + + + + DPMDUR + Set the duration required to enter/exit deep power-down mode (DPM). + 0x614 + read-write + 0xFFFFFFFF + + + ENTER + Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. + 0 + 15 + + + EXIT + Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. + 16 + 31 + + + + + ADDRCONF + Extended address configuration. + 0x624 + read-write + 0x000000B7 + + + OPCODE + Opcode that enters the 32-bit addressing mode. + 0 + 7 + + + BYTE0 + Byte 0 following opcode. + 8 + 15 + + + BYTE1 + Byte 1 following byte 0. + 16 + 23 + + + MODE + Extended addressing mode. + 24 + 25 + + + NoInstr + Do not send any instruction. + 0 + + + Opcode + Send opcode. + 1 + + + OpByte0 + Send opcode, byte0. + 2 + + + All + Send opcode, byte0, byte1. + 3 + + + + + WIPWAIT + Wait for write complete before sending command. + 26 + 26 + + + Disable + No wait. + 0 + + + Enable + Wait. + 1 + + + + + WREN + Send WREN (write enable opcode 0x06) before instruction. + 27 + 27 + + + Disable + Do not send WREN. + 0 + + + Enable + Send WREN. + 1 + + + + + + + CINSTRCONF + Custom instruction configuration register. + 0x634 + read-write + 0x00002000 + + + OPCODE + Opcode of Custom instruction. + 0 + 7 + + + LENGTH + Length of custom instruction in number of bytes. + 8 + 11 + + + 1B + Send opcode only. + 1 + + + 2B + Send opcode, CINSTRDAT0.BYTE0. + 2 + + + 3B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. + 3 + + + 4B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. + 4 + + + 5B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. + 5 + + + 6B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. + 6 + + + 7B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. + 7 + + + 8B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. + 8 + + + 9B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. + 9 + + + + + LIO2 + Level of the IO2 pin (if connected) during transmission of custom instruction. + 12 + 12 + + + LIO3 + Level of the IO3 pin (if connected) during transmission of custom instruction. + 13 + 13 + + + WIPWAIT + Wait for write complete before sending command. + 14 + 14 + + + Disable + No wait. + 0 + + + Enable + Wait. + 1 + + + + + WREN + Send WREN (write enable opcode 0x06) before instruction. + 15 + 15 + + + Disable + Do not send WREN. + 0 + + + Enable + Send WREN. + 1 + + + + + LFEN + Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. + 16 + 16 + + + Disable + Long frame mode disabled + 0 + + + Enable + Long frame mode enabled + 1 + + + + + LFSTOP + Stop (finalize) long frame transaction + 17 + 17 + + + Stop + Stop + 1 + + + + + + + CINSTRDAT0 + Custom instruction data register 0. + 0x638 + read-write + + + BYTE0 + Data byte 0 + 0 + 7 + + + BYTE1 + Data byte 1 + 8 + 15 + + + BYTE2 + Data byte 2 + 16 + 23 + + + BYTE3 + Data byte 3 + 24 + 31 + + + + + CINSTRDAT1 + Custom instruction data register 1. + 0x63C + read-write + + + BYTE4 + Data byte 4 + 0 + 7 + + + BYTE5 + Data byte 5 + 8 + 15 + + + BYTE6 + Data byte 6 + 16 + 23 + + + BYTE7 + Data byte 7 + 24 + 31 + + + + + IFTIMING + SPI interface timing. + 0x640 + read-write + 0x00000200 + + + RXDELAY + Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. + 8 + 10 + + + + + + + CC_HOST_RGF + CRYPTOCELL HOST_RGF interface + 0x5002A000 + + 0 + 0x2000 + registers + + CC_HOST_RGF + 0x20 + + + HOST_CRYPTOKEY_SEL + AES hardware key select + 0x1A38 + read-write + 0x00000000 + + + HOST_CRYPTOKEY_SEL + Select the source of the HW key that is used by the AES engine + 0 + 1 + + + K_DR + Use device root key K_DR from CRYPTOCELL AO power domain + 0 + + + K_PRTL + Use hard-coded RTL key K_PRTL + 1 + + + Session + Use provided session key + 2 + + + + + + + HOST_IOT_KPRTL_LOCK + This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A4C + read-write + 0x00000000 + + + HOST_IOT_KPRTL_LOCK + This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0 + 0 + + + Disabled + K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL + 0 + + + Enabled + K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. + 1 + + + + + + + HOST_IOT_KDR0 + This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. + 0x1A50 + read-write + 0x00000000 + + + HOST_IOT_KDR0 + Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. + 0 + 31 + + + + + HOST_IOT_KDR1 + This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A54 + write-only + 0x00000000 + + + HOST_IOT_KDR1 + K_DR bits 63:32 + 0 + 31 + + + + + HOST_IOT_KDR2 + This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A58 + write-only + 0x00000000 + + + HOST_IOT_KDR2 + K_DR bits 95:64 + 0 + 31 + + + + + HOST_IOT_KDR3 + This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A5C + write-only + 0x00000000 + + + HOST_IOT_KDR3 + K_DR bits 127:96 + 0 + 31 + + + + + HOST_IOT_LCS + Controls lifecycle state (LCS) for CRYPTOCELL subsystem + 0x1A60 + read-write + 0x00000002 + + + LCS + Lifecycle state value. This field is write-once per reset. + 0 + 2 + + + Debug + CC310 operates in debug mode + 0 + + + Secure + CC310 operates in secure mode + 2 + + + + + LCS_IS_VALID + Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. + 8 + 8 + + + Invalid + Valid LCS not yet retained in the CRYPTOCELL AO power domain + 0 + + + Valid + Valid LCS successfully retained in the CRYPTOCELL AO power domain + 1 + + + + + + + + + CRYPTOCELL + ARM TrustZone CryptoCell register interface + 0x5002A000 + CC_HOST_RGF + + 0 + 0x2000 + registers + + + CRYPTOCELL + 42 + + CRYPTOCELL + 0x20 + + + ENABLE + Enable CRYPTOCELL subsystem + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable the CRYPTOCELL subsystem + 0 + 0 + + + Disabled + CRYPTOCELL subsystem disabled + 0 + + + Enabled + CRYPTOCELL subsystem enabled. + 1 + + + + + + + + + PWM3 + Pulse width modulation unit 3 + 0x4002D000 + + PWM3 + 45 + + + + SPIM3 + Serial Peripheral Interface Master with EasyDMA 3 + 0x4002F000 + + SPIM3 + 47 + + + + \ No newline at end of file diff --git a/svd/rp2040.svd b/svd/rp2040.svd new file mode 100644 index 000000000..afbc2aaab --- /dev/null +++ b/svd/rp2040.svd @@ -0,0 +1,46401 @@ + + + + Raspberry Pi + RP2040 + 0.1 + + Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz\n + 264KB on-chip SRAM\n + 2 x UART, 2 x SPI controllers, 2 x I2C controllers, 16 x PWM channels\n + 1 x USB 1.1 controller and PHY, with host and device support\n + 8 x Programmable I/O (PIO) state machines for custom peripheral support\n + Supported input power 1.8-5.5V DC\n + Operating temperature -20C to +85C\n + Drag-and-drop programming using mass storage over USB\n + Low-power sleep and dormant modes\n + Accurate on-chip clock\n + Temperature sensor\n + Accelerated integer and floating-point libraries on-chip + + + Copyright (c) 2020 Raspberry Pi (Trading) Ltd.\n + \n + SPDX-License-Identifier: BSD-3-Clause + + + CM0PLUS + r0p1 + little + true + false + 1 + 2 + false + 26 + + 8 + 32 + + + XIP_CTRL + 1 + QSPI flash execute-in-place block + 0x14000000 + 32 + + 0 + 0x0020 + registers + + + XIP_IRQ + 6 + + + + CTRL + Cache control + 0x0000 + 0x00000003 + + + POWER_DOWN + When 1, the cache memories are powered down. They retain state,\n + but can not be accessed. This reduces static power dissipation.\n + Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n + be enabled when powered down.\n + Cache-as-SRAM accesses will produce a bus error response when\n + the cache is powered down. + [3:3] + read-write + + + ERR_BADWRITE + When 1, writes to any alias other than 0x0 (caching, allocating)\n + will produce a bus fault. When 0, these writes are silently ignored.\n + In either case, writes to the 0x0 alias will deallocate on tag match,\n + as usual. + [1:1] + read-write + + + EN + When 1, enable the cache. When the cache is disabled, all XIP accesses\n + will go straight to the flash, without querying the cache. When enabled,\n + cacheable XIP accesses will query the cache, and the flash will\n + not be accessed if the tag matches and the valid bit is set.\n\n + If the cache is enabled, cache-as-SRAM accesses have no effect on the\n + cache data RAM, and will produce a bus error response. + [0:0] + read-write + + + + + FLUSH + Cache Flush control + 0x0004 + 0x00000000 + + + FLUSH + Write 1 to flush the cache. This clears the tag memory, but\n + the data memory retains its contents. (This means cache-as-SRAM\n + contents is not affected by flush or reset.)\n + Reading will hold the bus (stall the processor) until the flush\n + completes. Alternatively STAT can be polled until completion. + [0:0] + read-write + clear + + + + + STAT + Cache Status + 0x0008 + 0x00000002 + + + FIFO_FULL + When 1, indicates the XIP streaming FIFO is completely full.\n + The streaming FIFO is 2 entries deep, so the full and empty\n + flag allow its level to be ascertained. + [2:2] + read-only + + + FIFO_EMPTY + When 1, indicates the XIP streaming FIFO is completely empty. + [1:1] + read-only + + + FLUSH_READY + Reads as 0 while a cache flush is in progress, and 1 otherwise.\n + The cache is flushed whenever the XIP block is reset, and also\n + when requested via the FLUSH register. + [0:0] + read-only + + + + + CTR_HIT + Cache Hit counter\n + A 32 bit saturating counter that increments upon each cache hit,\n + i.e. when an XIP access is serviced directly from cached data.\n + Write any value to clear. + 0x000c + read-write + 0x00000000 + oneToClear + + + CTR_ACC + Cache Access counter\n + A 32 bit saturating counter that increments upon each XIP access,\n + whether the cache is hit or not. This includes noncacheable accesses.\n + Write any value to clear. + 0x0010 + read-write + 0x00000000 + oneToClear + + + STREAM_ADDR + FIFO stream address + 0x0014 + 0x00000000 + + + STREAM_ADDR + The address of the next word to be streamed from flash to the streaming FIFO.\n + Increments automatically after each flash access.\n + Write the initial access address here before starting a streaming read. + [31:2] + read-write + + + + + STREAM_CTR + FIFO stream control + 0x0018 + 0x00000000 + + + STREAM_CTR + Write a nonzero value to start a streaming read. This will then\n + progress in the background, using flash idle cycles to transfer\n + a linear data block from flash to the streaming FIFO.\n + Decrements automatically (1 at a time) as the stream\n + progresses, and halts on reaching 0.\n + Write 0 to halt an in-progress stream, and discard any in-flight\n + read, so that a new stream can immediately be started (after\n + draining the FIFO and reinitialising STREAM_ADDR) + [21:0] + read-write + + + + + STREAM_FIFO + FIFO stream data\n + Streamed data is buffered here, for retrieval by the system DMA.\n + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n + the DMA to bus stalls caused by other XIP traffic. + 0x001c + read-only + 0x00000000 + + + + + XIP_SSI + 1 + DW_apb_ssi has the following features:\n + * APB interface - Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n + * APB3 and APB4 protocol support.\n + * Scalable APB data bus width - Supports APB data bus widths of 8, 16, and 32 bits.\n + * Serial-master or serial-slave operation - Enables serial communication with serial-master or serial-slave peripheral devices.\n + * Programmable Dual/Quad/Octal SPI support in Master Mode.\n + * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n + * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n + * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n + * DMA Controller Interface - Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n + * Independent masking of interrupts - Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n + * Multi-master contention detection - Informs the processor of multiple serial-master accesses on the serial bus.\n + * Bypass of meta-stability flip-flops for synchronous clocks - When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n + * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n + * Programmable features:\n + - Serial interface operation - Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n + - Clock bit-rate - Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n + - Data Item size (4 to 32 bits) - Item size of each data transfer under the control of the programmer.\n + * Configured features:\n + - FIFO depth - 16 words deep. The FIFO width is fixed at 32 bits.\n + - 1 slave select output.\n + - Hardware slave-select - Dedicated hardware slave-select line.\n + - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n + - Interrupt polarity - active high interrupt lines.\n + - Serial clock polarity - low serial-clock polarity directly after reset.\n + - Serial clock phase - capture on first edge of serial-clock directly after reset. + 0x18000000 + 32 + + 0 + 0x0100 + registers + + + + CTRLR0 + Control register 0 + 0x0000 + 0x00000000 + + + SSTE + Slave select toggle enable + [24:24] + read-write + + + SPI_FRF + SPI frame format + [22:21] + read-write + + + STD + Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex + 0 + + + DUAL + Dual-SPI frame format; two bits per SCK, half-duplex + 1 + + + QUAD + Quad-SPI frame format; four bits per SCK, half-duplex + 2 + + + + + DFS_32 + Data frame size in 32b transfer mode\n + Value of n -> n+1 clocks per frame. + [20:16] + read-write + + + CFS + Control frame size\n + Value of n -> n+1 clocks per frame. + [15:12] + read-write + + + SRL + Shift register loop (test mode) + [11:11] + read-write + + + SLV_OE + Slave output enable + [10:10] + read-write + + + TMOD + Transfer mode + [9:8] + read-write + + + TX_AND_RX + Both transmit and receive + 0 + + + TX_ONLY + Transmit only (not for FRF == 0, standard SPI mode) + 1 + + + RX_ONLY + Receive only (not for FRF == 0, standard SPI mode) + 2 + + + EEPROM_READ + EEPROM read mode (TX then RX; RX starts after control data TX'd) + 3 + + + + + SCPOL + Serial clock polarity + [7:7] + read-write + + + SCPH + Serial clock phase + [6:6] + read-write + + + FRF + Frame format + [5:4] + read-write + + + DFS + Data frame size + [3:0] + read-write + + + + + CTRLR1 + Master Control register 1 + 0x0004 + 0x00000000 + + + NDF + Number of data frames + [15:0] + read-write + + + + + SSIENR + SSI Enable + 0x0008 + 0x00000000 + + + SSI_EN + SSI enable + [0:0] + read-write + + + + + MWCR + Microwire Control + 0x000c + 0x00000000 + + + MHS + Microwire handshaking + [2:2] + read-write + + + MDD + Microwire control + [1:1] + read-write + + + MWMOD + Microwire transfer mode + [0:0] + read-write + + + + + SER + Slave enable + 0x0010 + 0x00000000 + + + SER + For each bit:\n + 0 -> slave not selected\n + 1 -> slave selected + [0:0] + read-write + + + + + BAUDR + Baud rate + 0x0014 + 0x00000000 + + + SCKDV + SSI clock divider + [15:0] + read-write + + + + + TXFTLR + TX FIFO threshold level + 0x0018 + 0x00000000 + + + TFT + Transmit FIFO threshold + [7:0] + read-write + + + + + RXFTLR + RX FIFO threshold level + 0x001c + 0x00000000 + + + RFT + Receive FIFO threshold + [7:0] + read-write + + + + + TXFLR + TX FIFO level + 0x0020 + 0x00000000 + + + TFTFL + Transmit FIFO level + [7:0] + read-only + + + + + RXFLR + RX FIFO level + 0x0024 + 0x00000000 + + + RXTFL + Receive FIFO level + [7:0] + read-only + + + + + SR + Status register + 0x0028 + 0x00000000 + + + DCOL + Data collision error + [6:6] + read-only + + + TXE + Transmission error + [5:5] + read-only + + + RFF + Receive FIFO full + [4:4] + read-only + + + RFNE + Receive FIFO not empty + [3:3] + read-only + + + TFE + Transmit FIFO empty + [2:2] + read-only + + + TFNF + Transmit FIFO not full + [1:1] + read-only + + + BUSY + SSI busy flag + [0:0] + read-only + + + + + IMR + Interrupt mask + 0x002c + 0x00000000 + + + MSTIM + Multi-master contention interrupt mask + [5:5] + read-write + + + RXFIM + Receive FIFO full interrupt mask + [4:4] + read-write + + + RXOIM + Receive FIFO overflow interrupt mask + [3:3] + read-write + + + RXUIM + Receive FIFO underflow interrupt mask + [2:2] + read-write + + + TXOIM + Transmit FIFO overflow interrupt mask + [1:1] + read-write + + + TXEIM + Transmit FIFO empty interrupt mask + [0:0] + read-write + + + + + ISR + Interrupt status + 0x0030 + 0x00000000 + + + MSTIS + Multi-master contention interrupt status + [5:5] + read-only + + + RXFIS + Receive FIFO full interrupt status + [4:4] + read-only + + + RXOIS + Receive FIFO overflow interrupt status + [3:3] + read-only + + + RXUIS + Receive FIFO underflow interrupt status + [2:2] + read-only + + + TXOIS + Transmit FIFO overflow interrupt status + [1:1] + read-only + + + TXEIS + Transmit FIFO empty interrupt status + [0:0] + read-only + + + + + RISR + Raw interrupt status + 0x0034 + 0x00000000 + + + MSTIR + Multi-master contention raw interrupt status + [5:5] + read-only + + + RXFIR + Receive FIFO full raw interrupt status + [4:4] + read-only + + + RXOIR + Receive FIFO overflow raw interrupt status + [3:3] + read-only + + + RXUIR + Receive FIFO underflow raw interrupt status + [2:2] + read-only + + + TXOIR + Transmit FIFO overflow raw interrupt status + [1:1] + read-only + + + TXEIR + Transmit FIFO empty raw interrupt status + [0:0] + read-only + + + + + TXOICR + TX FIFO overflow interrupt clear + 0x0038 + 0x00000000 + + + TXOICR + Clear-on-read transmit FIFO overflow interrupt + [0:0] + read-only + + + + + RXOICR + RX FIFO overflow interrupt clear + 0x003c + 0x00000000 + + + RXOICR + Clear-on-read receive FIFO overflow interrupt + [0:0] + read-only + + + + + RXUICR + RX FIFO underflow interrupt clear + 0x0040 + 0x00000000 + + + RXUICR + Clear-on-read receive FIFO underflow interrupt + [0:0] + read-only + + + + + MSTICR + Multi-master interrupt clear + 0x0044 + 0x00000000 + + + MSTICR + Clear-on-read multi-master contention interrupt + [0:0] + read-only + + + + + ICR + Interrupt clear + 0x0048 + 0x00000000 + + + ICR + Clear-on-read all active interrupts + [0:0] + read-only + + + + + DMACR + DMA control + 0x004c + 0x00000000 + + + TDMAE + Transmit DMA enable + [1:1] + read-write + + + RDMAE + Receive DMA enable + [0:0] + read-write + + + + + DMATDLR + DMA TX data level + 0x0050 + 0x00000000 + + + DMATDL + Transmit data watermark level + [7:0] + read-write + + + + + DMARDLR + DMA RX data level + 0x0054 + 0x00000000 + + + DMARDL + Receive data watermark level (DMARDLR+1) + [7:0] + read-write + + + + + IDR + Identification register + 0x0058 + 0x51535049 + + + IDCODE + Peripheral dentification code + [31:0] + read-only + + + + + SSI_VERSION_ID + Version ID + 0x005c + 0x3430312a + + + SSI_COMP_VERSION + SNPS component version (format X.YY) + [31:0] + read-only + + + + + DR0 + Data Register 0 (of 36) + 0x0060 + 0x00000000 + + + DR + First data register of 36 + [31:0] + read-write + + + + + RX_SAMPLE_DLY + RX sample delay + 0x00f0 + 0x00000000 + + + RSD + RXD sample delay (in SCLK cycles) + [7:0] + read-write + + + + + SPI_CTRLR0 + SPI control + 0x00f4 + 0x03000000 + + + XIP_CMD + SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) + [31:24] + read-write + + + SPI_RXDS_EN + Read data strobe enable + [18:18] + read-write + + + INST_DDR_EN + Instruction DDR transfer enable + [17:17] + read-write + + + SPI_DDR_EN + SPI DDR transfer enable + [16:16] + read-write + + + WAIT_CYCLES + Wait cycles between control frame transmit and data reception (in SCLK cycles) + [15:11] + read-write + + + INST_L + Instruction length (0/4/8/16b) + [9:8] + read-write + + + NONE + No instruction + 0 + + + 4B + 4-bit instruction + 1 + + + 8B + 8-bit instruction + 2 + + + 16B + 16-bit instruction + 3 + + + + + ADDR_L + Address length (0b-60b in 4b increments) + [5:2] + read-write + + + TRANS_TYPE + Address and instruction transfer format + [1:0] + read-write + + + 1C1A + Command and address both in standard SPI frame format + 0 + + + 1C2A + Command in standard SPI format, address in format specified by FRF + 1 + + + 2C2A + Command and address both in format specified by FRF (e.g. Dual-SPI) + 2 + + + + + + + TXD_DRIVE_EDGE + TX drive edge + 0x00f8 + 0x00000000 + + + TDE + TXD drive edge + [7:0] + read-write + + + + + + + SYSINFO + 1 + 0x40000000 + 32 + + 0 + 0x1000 + registers + + + + CHIP_ID + JEDEC JEP-106 compliant chip identifier. + 0x0000 + 0x00000000 + + + REVISION + [31:28] + read-only + + + PART + [27:12] + read-only + + + MANUFACTURER + [11:0] + read-only + + + + + PLATFORM + Platform register. Allows software to know what environment it is running in. + 0x0004 + 0x00000000 + + + ASIC + [1:1] + read-only + + + FPGA + [0:0] + read-only + + + + + GITREF_RP2040 + Git hash of the chip source. Used to identify chip version. + 0x0040 + read-only + 0x00000000 + + + + + SYSCFG + 1 + Register block for various chip control signals + 0x40004000 + 32 + + 0 + 0x1000 + registers + + + + PROC0_NMI_MASK + Processor core 0 NMI source mask\n + Set a bit high to enable NMI from that IRQ + 0x0000 + read-write + 0x00000000 + + + PROC1_NMI_MASK + Processor core 1 NMI source mask\n + Set a bit high to enable NMI from that IRQ + 0x0004 + read-write + 0x00000000 + + + PROC_CONFIG + Configuration for processors + 0x0008 + 0x10000000 + + + PROC1_DAP_INSTID + Configure proc1 DAP instance ID.\n + Recommend that this is NOT changed until you require debug access in multi-chip environment\n + WARNING: do not set to 15 as this is reserved for RescueDP + [31:28] + read-write + + + PROC0_DAP_INSTID + Configure proc0 DAP instance ID.\n + Recommend that this is NOT changed until you require debug access in multi-chip environment\n + WARNING: do not set to 15 as this is reserved for RescueDP + [27:24] + read-write + + + PROC1_HALTED + Indication that proc1 has halted + [1:1] + read-only + + + PROC0_HALTED + Indication that proc0 has halted + [0:0] + read-only + + + + + PROC_IN_SYNC_BYPASS + For each bit, if 1, bypass the input synchronizer between that GPIO\n + and the GPIO input register in the SIO. The input synchronizers should\n + generally be unbypassed, to avoid injecting metastabilities into processors.\n + If you're feeling brave, you can bypass to save two cycles of input\n + latency. This register applies to GPIO 0...29. + 0x000c + 0x00000000 + + + PROC_IN_SYNC_BYPASS + [29:0] + read-write + + + + + PROC_IN_SYNC_BYPASS_HI + For each bit, if 1, bypass the input synchronizer between that GPIO\n + and the GPIO input register in the SIO. The input synchronizers should\n + generally be unbypassed, to avoid injecting metastabilities into processors.\n + If you're feeling brave, you can bypass to save two cycles of input\n + latency. This register applies to GPIO 30...35 (the QSPI IOs). + 0x0010 + 0x00000000 + + + PROC_IN_SYNC_BYPASS_HI + [5:0] + read-write + + + + + DBGFORCE + Directly control the SWD debug port of either processor + 0x0014 + 0x00000066 + + + PROC1_ATTACH + Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. + [7:7] + read-write + + + PROC1_SWCLK + Directly drive processor 1 SWCLK, if PROC1_ATTACH is set + [6:6] + read-write + + + PROC1_SWDI + Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set + [5:5] + read-write + + + PROC1_SWDO + Observe the value of processor 1 SWDIO output. + [4:4] + read-only + + + PROC0_ATTACH + Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. + [3:3] + read-write + + + PROC0_SWCLK + Directly drive processor 0 SWCLK, if PROC0_ATTACH is set + [2:2] + read-write + + + PROC0_SWDI + Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set + [1:1] + read-write + + + PROC0_SWDO + Observe the value of processor 0 SWDIO output. + [0:0] + read-only + + + + + MEMPOWERDOWN + Control power downs to memories. Set high to power down memories.\n + Use with extreme caution + 0x0018 + 0x00000000 + + + ROM + [7:7] + read-write + + + USB + [6:6] + read-write + + + SRAM5 + [5:5] + read-write + + + SRAM4 + [4:4] + read-write + + + SRAM3 + [3:3] + read-write + + + SRAM2 + [2:2] + read-write + + + SRAM1 + [1:1] + read-write + + + SRAM0 + [0:0] + read-write + + + + + + + CLOCKS + 1 + 0x40008000 + 32 + + 0 + 0x1000 + registers + + + CLOCKS_IRQ + 17 + + + + CLK_GPOUT0_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x0000 + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + + + + + CLK_GPOUT0_DIV + Clock divisor, can be changed on-the-fly + 0x0004 + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_GPOUT0_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + 0x0008 + read-only + 0x00000001 + + + CLK_GPOUT1_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x000c + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + + + + + CLK_GPOUT1_DIV + Clock divisor, can be changed on-the-fly + 0x0010 + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_GPOUT1_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + 0x0014 + read-only + 0x00000001 + + + CLK_GPOUT2_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x0018 + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + + + + + CLK_GPOUT2_DIV + Clock divisor, can be changed on-the-fly + 0x001c + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_GPOUT2_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + 0x0020 + read-only + 0x00000001 + + + CLK_GPOUT3_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x0024 + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + + + + + CLK_GPOUT3_DIV + Clock divisor, can be changed on-the-fly + 0x0028 + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_GPOUT3_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + 0x002c + read-only + 0x00000001 + + + CLK_REF_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x0030 + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [6:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [1:0] + read-write + + + rosc_clksrc_ph + 0 + + + clksrc_clk_ref_aux + 1 + + + xosc_clksrc + 2 + + + + + + + CLK_REF_DIV + Clock divisor, can be changed on-the-fly + 0x0034 + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [9:8] + read-write + + + + + CLK_REF_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + 0x0038 + read-only + 0x00000001 + + + CLK_SYS_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x003c + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_pll_usb + 1 + + + rosc_clksrc + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [0:0] + read-write + + + clk_ref + 0 + + + clksrc_clk_sys_aux + 1 + + + + + + + CLK_SYS_DIV + Clock divisor, can be changed on-the-fly + 0x0040 + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_SYS_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + 0x0044 + read-only + 0x00000001 + + + CLK_PERI_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x0048 + 0x00000000 + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + rosc_clksrc_ph + 3 + + + xosc_clksrc + 4 + + + clksrc_gpin0 + 5 + + + clksrc_gpin1 + 6 + + + + + + + CLK_PERI_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + 0x0050 + read-only + 0x00000001 + + + CLK_USB_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x0054 + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_USB_DIV + Clock divisor, can be changed on-the-fly + 0x0058 + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [9:8] + read-write + + + + + CLK_USB_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + 0x005c + read-only + 0x00000001 + + + CLK_ADC_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x0060 + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_ADC_DIV + Clock divisor, can be changed on-the-fly + 0x0064 + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [9:8] + read-write + + + + + CLK_ADC_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + 0x0068 + read-only + 0x00000001 + + + CLK_RTC_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x006c + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_RTC_DIV + Clock divisor, can be changed on-the-fly + 0x0070 + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_RTC_SELECTED + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + 0x0074 + read-only + 0x00000001 + + + CLK_SYS_RESUS_CTRL + 0x0078 + 0x000000ff + + + CLEAR + For clearing the resus after the fault that triggered it has been corrected + [16:16] + read-write + + + FRCE + Force a resus, for test purposes only + [12:12] + read-write + + + ENABLE + Enable resus + [8:8] + read-write + + + TIMEOUT + This is expressed as a number of clk_ref cycles\n + and must be >= 2x clk_ref_freq/min_clk_tst_freq + [7:0] + read-write + + + + + CLK_SYS_RESUS_STATUS + 0x007c + 0x00000000 + + + RESUSSED + Clock has been resuscitated, correct the error then send ctrl_clear=1 + [0:0] + read-only + + + + + FC0_REF_KHZ + Reference clock frequency in kHz + 0x0080 + 0x00000000 + + + FC0_REF_KHZ + [19:0] + read-write + + + + + FC0_MIN_KHZ + Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + 0x0084 + 0x00000000 + + + FC0_MIN_KHZ + [24:0] + read-write + + + + + FC0_MAX_KHZ + Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + 0x0088 + 0x01ffffff + + + FC0_MAX_KHZ + [24:0] + read-write + + + + + FC0_DELAY + Delays the start of frequency counting to allow the mux to settle\n + Delay is measured in multiples of the reference clock period + 0x008c + 0x00000001 + + + FC0_DELAY + [2:0] + read-write + + + + + FC0_INTERVAL + The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n + The default gives a test interval of 250us + 0x0090 + 0x00000008 + + + FC0_INTERVAL + [3:0] + read-write + + + + + FC0_SRC + Clock sent to frequency counter, set to 0 when not required\n + Writing to this register initiates the frequency count + 0x0094 + 0x00000000 + + + FC0_SRC + [7:0] + read-write + + + NULL + 0 + + + pll_sys_clksrc_primary + 1 + + + pll_usb_clksrc_primary + 2 + + + rosc_clksrc + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clksrc_gpin0 + 6 + + + clksrc_gpin1 + 7 + + + clk_ref + 8 + + + clk_sys + 9 + + + clk_peri + 10 + + + clk_usb + 11 + + + clk_adc + 12 + + + clk_rtc + 13 + + + + + + + FC0_STATUS + Frequency counter status + 0x0098 + 0x00000000 + + + DIED + Test clock stopped during test + [28:28] + read-only + + + FAST + Test clock faster than expected, only valid when status_done=1 + [24:24] + read-only + + + SLOW + Test clock slower than expected, only valid when status_done=1 + [20:20] + read-only + + + FAIL + Test failed + [16:16] + read-only + + + WAITING + Waiting for test clock to start + [12:12] + read-only + + + RUNNING + Test running + [8:8] + read-only + + + DONE + Test complete + [4:4] + read-only + + + PASS + Test passed + [0:0] + read-only + + + + + FC0_RESULT + Result of frequency measurement, only valid when status_done=1 + 0x009c + 0x00000000 + + + KHZ + [29:5] + read-only + + + FRAC + [4:0] + read-only + + + + + WAKE_EN0 + enable clock in wake mode + 0x00a0 + 0xffffffff + + + clk_sys_sram3 + [31:31] + read-write + + + clk_sys_sram2 + [30:30] + read-write + + + clk_sys_sram1 + [29:29] + read-write + + + clk_sys_sram0 + [28:28] + read-write + + + clk_sys_spi1 + [27:27] + read-write + + + clk_peri_spi1 + [26:26] + read-write + + + clk_sys_spi0 + [25:25] + read-write + + + clk_peri_spi0 + [24:24] + read-write + + + clk_sys_sio + [23:23] + read-write + + + clk_sys_rtc + [22:22] + read-write + + + clk_rtc_rtc + [21:21] + read-write + + + clk_sys_rosc + [20:20] + read-write + + + clk_sys_rom + [19:19] + read-write + + + clk_sys_resets + [18:18] + read-write + + + clk_sys_pwm + [17:17] + read-write + + + clk_sys_psm + [16:16] + read-write + + + clk_sys_pll_usb + [15:15] + read-write + + + clk_sys_pll_sys + [14:14] + read-write + + + clk_sys_pio1 + [13:13] + read-write + + + clk_sys_pio0 + [12:12] + read-write + + + clk_sys_pads + [11:11] + read-write + + + clk_sys_vreg_and_chip_reset + [10:10] + read-write + + + clk_sys_jtag + [9:9] + read-write + + + clk_sys_io + [8:8] + read-write + + + clk_sys_i2c1 + [7:7] + read-write + + + clk_sys_i2c0 + [6:6] + read-write + + + clk_sys_dma + [5:5] + read-write + + + clk_sys_busfabric + [4:4] + read-write + + + clk_sys_busctrl + [3:3] + read-write + + + clk_sys_adc + [2:2] + read-write + + + clk_adc_adc + [1:1] + read-write + + + clk_sys_clocks + [0:0] + read-write + + + + + WAKE_EN1 + enable clock in wake mode + 0x00a4 + 0x00007fff + + + clk_sys_xosc + [14:14] + read-write + + + clk_sys_xip + [13:13] + read-write + + + clk_sys_watchdog + [12:12] + read-write + + + clk_usb_usbctrl + [11:11] + read-write + + + clk_sys_usbctrl + [10:10] + read-write + + + clk_sys_uart1 + [9:9] + read-write + + + clk_peri_uart1 + [8:8] + read-write + + + clk_sys_uart0 + [7:7] + read-write + + + clk_peri_uart0 + [6:6] + read-write + + + clk_sys_timer + [5:5] + read-write + + + clk_sys_tbman + [4:4] + read-write + + + clk_sys_sysinfo + [3:3] + read-write + + + clk_sys_syscfg + [2:2] + read-write + + + clk_sys_sram5 + [1:1] + read-write + + + clk_sys_sram4 + [0:0] + read-write + + + + + SLEEP_EN0 + enable clock in sleep mode + 0x00a8 + 0xffffffff + + + clk_sys_sram3 + [31:31] + read-write + + + clk_sys_sram2 + [30:30] + read-write + + + clk_sys_sram1 + [29:29] + read-write + + + clk_sys_sram0 + [28:28] + read-write + + + clk_sys_spi1 + [27:27] + read-write + + + clk_peri_spi1 + [26:26] + read-write + + + clk_sys_spi0 + [25:25] + read-write + + + clk_peri_spi0 + [24:24] + read-write + + + clk_sys_sio + [23:23] + read-write + + + clk_sys_rtc + [22:22] + read-write + + + clk_rtc_rtc + [21:21] + read-write + + + clk_sys_rosc + [20:20] + read-write + + + clk_sys_rom + [19:19] + read-write + + + clk_sys_resets + [18:18] + read-write + + + clk_sys_pwm + [17:17] + read-write + + + clk_sys_psm + [16:16] + read-write + + + clk_sys_pll_usb + [15:15] + read-write + + + clk_sys_pll_sys + [14:14] + read-write + + + clk_sys_pio1 + [13:13] + read-write + + + clk_sys_pio0 + [12:12] + read-write + + + clk_sys_pads + [11:11] + read-write + + + clk_sys_vreg_and_chip_reset + [10:10] + read-write + + + clk_sys_jtag + [9:9] + read-write + + + clk_sys_io + [8:8] + read-write + + + clk_sys_i2c1 + [7:7] + read-write + + + clk_sys_i2c0 + [6:6] + read-write + + + clk_sys_dma + [5:5] + read-write + + + clk_sys_busfabric + [4:4] + read-write + + + clk_sys_busctrl + [3:3] + read-write + + + clk_sys_adc + [2:2] + read-write + + + clk_adc_adc + [1:1] + read-write + + + clk_sys_clocks + [0:0] + read-write + + + + + SLEEP_EN1 + enable clock in sleep mode + 0x00ac + 0x00007fff + + + clk_sys_xosc + [14:14] + read-write + + + clk_sys_xip + [13:13] + read-write + + + clk_sys_watchdog + [12:12] + read-write + + + clk_usb_usbctrl + [11:11] + read-write + + + clk_sys_usbctrl + [10:10] + read-write + + + clk_sys_uart1 + [9:9] + read-write + + + clk_peri_uart1 + [8:8] + read-write + + + clk_sys_uart0 + [7:7] + read-write + + + clk_peri_uart0 + [6:6] + read-write + + + clk_sys_timer + [5:5] + read-write + + + clk_sys_tbman + [4:4] + read-write + + + clk_sys_sysinfo + [3:3] + read-write + + + clk_sys_syscfg + [2:2] + read-write + + + clk_sys_sram5 + [1:1] + read-write + + + clk_sys_sram4 + [0:0] + read-write + + + + + ENABLED0 + indicates the state of the clock enable + 0x00b0 + 0x00000000 + + + clk_sys_sram3 + [31:31] + read-only + + + clk_sys_sram2 + [30:30] + read-only + + + clk_sys_sram1 + [29:29] + read-only + + + clk_sys_sram0 + [28:28] + read-only + + + clk_sys_spi1 + [27:27] + read-only + + + clk_peri_spi1 + [26:26] + read-only + + + clk_sys_spi0 + [25:25] + read-only + + + clk_peri_spi0 + [24:24] + read-only + + + clk_sys_sio + [23:23] + read-only + + + clk_sys_rtc + [22:22] + read-only + + + clk_rtc_rtc + [21:21] + read-only + + + clk_sys_rosc + [20:20] + read-only + + + clk_sys_rom + [19:19] + read-only + + + clk_sys_resets + [18:18] + read-only + + + clk_sys_pwm + [17:17] + read-only + + + clk_sys_psm + [16:16] + read-only + + + clk_sys_pll_usb + [15:15] + read-only + + + clk_sys_pll_sys + [14:14] + read-only + + + clk_sys_pio1 + [13:13] + read-only + + + clk_sys_pio0 + [12:12] + read-only + + + clk_sys_pads + [11:11] + read-only + + + clk_sys_vreg_and_chip_reset + [10:10] + read-only + + + clk_sys_jtag + [9:9] + read-only + + + clk_sys_io + [8:8] + read-only + + + clk_sys_i2c1 + [7:7] + read-only + + + clk_sys_i2c0 + [6:6] + read-only + + + clk_sys_dma + [5:5] + read-only + + + clk_sys_busfabric + [4:4] + read-only + + + clk_sys_busctrl + [3:3] + read-only + + + clk_sys_adc + [2:2] + read-only + + + clk_adc_adc + [1:1] + read-only + + + clk_sys_clocks + [0:0] + read-only + + + + + ENABLED1 + indicates the state of the clock enable + 0x00b4 + 0x00000000 + + + clk_sys_xosc + [14:14] + read-only + + + clk_sys_xip + [13:13] + read-only + + + clk_sys_watchdog + [12:12] + read-only + + + clk_usb_usbctrl + [11:11] + read-only + + + clk_sys_usbctrl + [10:10] + read-only + + + clk_sys_uart1 + [9:9] + read-only + + + clk_peri_uart1 + [8:8] + read-only + + + clk_sys_uart0 + [7:7] + read-only + + + clk_peri_uart0 + [6:6] + read-only + + + clk_sys_timer + [5:5] + read-only + + + clk_sys_tbman + [4:4] + read-only + + + clk_sys_sysinfo + [3:3] + read-only + + + clk_sys_syscfg + [2:2] + read-only + + + clk_sys_sram5 + [1:1] + read-only + + + clk_sys_sram4 + [0:0] + read-only + + + + + INTR + Raw Interrupts + 0x00b8 + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + INTE + Interrupt Enable + 0x00bc + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x00c0 + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x00c4 + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + + + RESETS + 1 + 0x4000c000 + 32 + + 0 + 0x1000 + registers + + + + RESET + Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. + 0x0000 + 0x01ffffff + + + usbctrl + [24:24] + read-write + + + uart1 + [23:23] + read-write + + + uart0 + [22:22] + read-write + + + timer + [21:21] + read-write + + + tbman + [20:20] + read-write + + + sysinfo + [19:19] + read-write + + + syscfg + [18:18] + read-write + + + spi1 + [17:17] + read-write + + + spi0 + [16:16] + read-write + + + rtc + [15:15] + read-write + + + pwm + [14:14] + read-write + + + pll_usb + [13:13] + read-write + + + pll_sys + [12:12] + read-write + + + pio1 + [11:11] + read-write + + + pio0 + [10:10] + read-write + + + pads_qspi + [9:9] + read-write + + + pads_bank0 + [8:8] + read-write + + + jtag + [7:7] + read-write + + + io_qspi + [6:6] + read-write + + + io_bank0 + [5:5] + read-write + + + i2c1 + [4:4] + read-write + + + i2c0 + [3:3] + read-write + + + dma + [2:2] + read-write + + + busctrl + [1:1] + read-write + + + adc + [0:0] + read-write + + + + + WDSEL + Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. + 0x0004 + 0x00000000 + + + usbctrl + [24:24] + read-write + + + uart1 + [23:23] + read-write + + + uart0 + [22:22] + read-write + + + timer + [21:21] + read-write + + + tbman + [20:20] + read-write + + + sysinfo + [19:19] + read-write + + + syscfg + [18:18] + read-write + + + spi1 + [17:17] + read-write + + + spi0 + [16:16] + read-write + + + rtc + [15:15] + read-write + + + pwm + [14:14] + read-write + + + pll_usb + [13:13] + read-write + + + pll_sys + [12:12] + read-write + + + pio1 + [11:11] + read-write + + + pio0 + [10:10] + read-write + + + pads_qspi + [9:9] + read-write + + + pads_bank0 + [8:8] + read-write + + + jtag + [7:7] + read-write + + + io_qspi + [6:6] + read-write + + + io_bank0 + [5:5] + read-write + + + i2c1 + [4:4] + read-write + + + i2c0 + [3:3] + read-write + + + dma + [2:2] + read-write + + + busctrl + [1:1] + read-write + + + adc + [0:0] + read-write + + + + + RESET_DONE + Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. + 0x0008 + 0x00000000 + + + usbctrl + [24:24] + read-only + + + uart1 + [23:23] + read-only + + + uart0 + [22:22] + read-only + + + timer + [21:21] + read-only + + + tbman + [20:20] + read-only + + + sysinfo + [19:19] + read-only + + + syscfg + [18:18] + read-only + + + spi1 + [17:17] + read-only + + + spi0 + [16:16] + read-only + + + rtc + [15:15] + read-only + + + pwm + [14:14] + read-only + + + pll_usb + [13:13] + read-only + + + pll_sys + [12:12] + read-only + + + pio1 + [11:11] + read-only + + + pio0 + [10:10] + read-only + + + pads_qspi + [9:9] + read-only + + + pads_bank0 + [8:8] + read-only + + + jtag + [7:7] + read-only + + + io_qspi + [6:6] + read-only + + + io_bank0 + [5:5] + read-only + + + i2c1 + [4:4] + read-only + + + i2c0 + [3:3] + read-only + + + dma + [2:2] + read-only + + + busctrl + [1:1] + read-only + + + adc + [0:0] + read-only + + + + + + + PSM + 1 + 0x40010000 + 32 + + 0 + 0x1000 + registers + + + + FRCE_ON + Force block out of reset (i.e. power it on) + 0x0000 + 0x00000000 + + + proc1 + [16:16] + read-write + + + proc0 + [15:15] + read-write + + + sio + [14:14] + read-write + + + vreg_and_chip_reset + [13:13] + read-write + + + xip + [12:12] + read-write + + + sram5 + [11:11] + read-write + + + sram4 + [10:10] + read-write + + + sram3 + [9:9] + read-write + + + sram2 + [8:8] + read-write + + + sram1 + [7:7] + read-write + + + sram0 + [6:6] + read-write + + + rom + [5:5] + read-write + + + busfabric + [4:4] + read-write + + + resets + [3:3] + read-write + + + clocks + [2:2] + read-write + + + xosc + [1:1] + read-write + + + rosc + [0:0] + read-write + + + + + FRCE_OFF + Force into reset (i.e. power it off) + 0x0004 + 0x00000000 + + + proc1 + [16:16] + read-write + + + proc0 + [15:15] + read-write + + + sio + [14:14] + read-write + + + vreg_and_chip_reset + [13:13] + read-write + + + xip + [12:12] + read-write + + + sram5 + [11:11] + read-write + + + sram4 + [10:10] + read-write + + + sram3 + [9:9] + read-write + + + sram2 + [8:8] + read-write + + + sram1 + [7:7] + read-write + + + sram0 + [6:6] + read-write + + + rom + [5:5] + read-write + + + busfabric + [4:4] + read-write + + + resets + [3:3] + read-write + + + clocks + [2:2] + read-write + + + xosc + [1:1] + read-write + + + rosc + [0:0] + read-write + + + + + WDSEL + Set to 1 if this peripheral should be reset when the watchdog fires. + 0x0008 + 0x00000000 + + + proc1 + [16:16] + read-write + + + proc0 + [15:15] + read-write + + + sio + [14:14] + read-write + + + vreg_and_chip_reset + [13:13] + read-write + + + xip + [12:12] + read-write + + + sram5 + [11:11] + read-write + + + sram4 + [10:10] + read-write + + + sram3 + [9:9] + read-write + + + sram2 + [8:8] + read-write + + + sram1 + [7:7] + read-write + + + sram0 + [6:6] + read-write + + + rom + [5:5] + read-write + + + busfabric + [4:4] + read-write + + + resets + [3:3] + read-write + + + clocks + [2:2] + read-write + + + xosc + [1:1] + read-write + + + rosc + [0:0] + read-write + + + + + DONE + Indicates the peripheral's registers are ready to access. + 0x000c + 0x00000000 + + + proc1 + [16:16] + read-only + + + proc0 + [15:15] + read-only + + + sio + [14:14] + read-only + + + vreg_and_chip_reset + [13:13] + read-only + + + xip + [12:12] + read-only + + + sram5 + [11:11] + read-only + + + sram4 + [10:10] + read-only + + + sram3 + [9:9] + read-only + + + sram2 + [8:8] + read-only + + + sram1 + [7:7] + read-only + + + sram0 + [6:6] + read-only + + + rom + [5:5] + read-only + + + busfabric + [4:4] + read-only + + + resets + [3:3] + read-only + + + clocks + [2:2] + read-only + + + xosc + [1:1] + read-only + + + rosc + [0:0] + read-only + + + + + + + IO_BANK0 + 1 + 0x40014000 + 32 + + 0 + 0x1000 + registers + + + IO_IRQ_BANK0 + 13 + + + + GPIO0_STATUS + GPIO status + 0x0000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO0_CTRL + GPIO control including function select and overrides. + 0x0004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + jtag_tck + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + sio_0 + 5 + + + pio0_0 + 6 + + + pio1_0 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO1_STATUS + GPIO status + 0x0008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO1_CTRL + GPIO control including function select and overrides. + 0x000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + jtag_tms + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + sio_1 + 5 + + + pio0_1 + 6 + + + pio1_1 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO2_STATUS + GPIO status + 0x0010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO2_CTRL + GPIO control including function select and overrides. + 0x0014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + jtag_tdi + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + sio_2 + 5 + + + pio0_2 + 6 + + + pio1_2 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO3_STATUS + GPIO status + 0x0018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO3_CTRL + GPIO control including function select and overrides. + 0x001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + jtag_tdo + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + sio_3 + 5 + + + pio0_3 + 6 + + + pio1_3 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO4_STATUS + GPIO status + 0x0020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO4_CTRL + GPIO control including function select and overrides. + 0x0024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + sio_4 + 5 + + + pio0_4 + 6 + + + pio1_4 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO5_STATUS + GPIO status + 0x0028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO5_CTRL + GPIO control including function select and overrides. + 0x002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + sio_5 + 5 + + + pio0_5 + 6 + + + pio1_5 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO6_STATUS + GPIO status + 0x0030 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO6_CTRL + GPIO control including function select and overrides. + 0x0034 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + sio_6 + 5 + + + pio0_6 + 6 + + + pio1_6 + 7 + + + usb_muxing_extphy_softcon + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO7_STATUS + GPIO status + 0x0038 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO7_CTRL + GPIO control including function select and overrides. + 0x003c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + sio_7 + 5 + + + pio0_7 + 6 + + + pio1_7 + 7 + + + usb_muxing_extphy_oe_n + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO8_STATUS + GPIO status + 0x0040 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO8_CTRL + GPIO control including function select and overrides. + 0x0044 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + sio_8 + 5 + + + pio0_8 + 6 + + + pio1_8 + 7 + + + usb_muxing_extphy_rcv + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO9_STATUS + GPIO status + 0x0048 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO9_CTRL + GPIO control including function select and overrides. + 0x004c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + sio_9 + 5 + + + pio0_9 + 6 + + + pio1_9 + 7 + + + usb_muxing_extphy_vp + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO10_STATUS + GPIO status + 0x0050 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO10_CTRL + GPIO control including function select and overrides. + 0x0054 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + sio_10 + 5 + + + pio0_10 + 6 + + + pio1_10 + 7 + + + usb_muxing_extphy_vm + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO11_STATUS + GPIO status + 0x0058 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO11_CTRL + GPIO control including function select and overrides. + 0x005c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + sio_11 + 5 + + + pio0_11 + 6 + + + pio1_11 + 7 + + + usb_muxing_extphy_suspnd + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO12_STATUS + GPIO status + 0x0060 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO12_CTRL + GPIO control including function select and overrides. + 0x0064 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + sio_12 + 5 + + + pio0_12 + 6 + + + pio1_12 + 7 + + + usb_muxing_extphy_speed + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO13_STATUS + GPIO status + 0x0068 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO13_CTRL + GPIO control including function select and overrides. + 0x006c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + sio_13 + 5 + + + pio0_13 + 6 + + + pio1_13 + 7 + + + usb_muxing_extphy_vpo + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO14_STATUS + GPIO status + 0x0070 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO14_CTRL + GPIO control including function select and overrides. + 0x0074 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + sio_14 + 5 + + + pio0_14 + 6 + + + pio1_14 + 7 + + + usb_muxing_extphy_vmo + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO15_STATUS + GPIO status + 0x0078 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO15_CTRL + GPIO control including function select and overrides. + 0x007c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + sio_15 + 5 + + + pio0_15 + 6 + + + pio1_15 + 7 + + + usb_muxing_digital_dp + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO16_STATUS + GPIO status + 0x0080 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO16_CTRL + GPIO control including function select and overrides. + 0x0084 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + sio_16 + 5 + + + pio0_16 + 6 + + + pio1_16 + 7 + + + usb_muxing_digital_dm + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO17_STATUS + GPIO status + 0x0088 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO17_CTRL + GPIO control including function select and overrides. + 0x008c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + sio_17 + 5 + + + pio0_17 + 6 + + + pio1_17 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO18_STATUS + GPIO status + 0x0090 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO18_CTRL + GPIO control including function select and overrides. + 0x0094 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + sio_18 + 5 + + + pio0_18 + 6 + + + pio1_18 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO19_STATUS + GPIO status + 0x0098 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO19_CTRL + GPIO control including function select and overrides. + 0x009c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + sio_19 + 5 + + + pio0_19 + 6 + + + pio1_19 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO20_STATUS + GPIO status + 0x00a0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO20_CTRL + GPIO control including function select and overrides. + 0x00a4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + sio_20 + 5 + + + pio0_20 + 6 + + + pio1_20 + 7 + + + clocks_gpin_0 + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO21_STATUS + GPIO status + 0x00a8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO21_CTRL + GPIO control including function select and overrides. + 0x00ac + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + sio_21 + 5 + + + pio0_21 + 6 + + + pio1_21 + 7 + + + clocks_gpout_0 + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO22_STATUS + GPIO status + 0x00b0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO22_CTRL + GPIO control including function select and overrides. + 0x00b4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + sio_22 + 5 + + + pio0_22 + 6 + + + pio1_22 + 7 + + + clocks_gpin_1 + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO23_STATUS + GPIO status + 0x00b8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO23_CTRL + GPIO control including function select and overrides. + 0x00bc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + sio_23 + 5 + + + pio0_23 + 6 + + + pio1_23 + 7 + + + clocks_gpout_1 + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO24_STATUS + GPIO status + 0x00c0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO24_CTRL + GPIO control including function select and overrides. + 0x00c4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + sio_24 + 5 + + + pio0_24 + 6 + + + pio1_24 + 7 + + + clocks_gpout_2 + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO25_STATUS + GPIO status + 0x00c8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO25_CTRL + GPIO control including function select and overrides. + 0x00cc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + sio_25 + 5 + + + pio0_25 + 6 + + + pio1_25 + 7 + + + clocks_gpout_3 + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO26_STATUS + GPIO status + 0x00d0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO26_CTRL + GPIO control including function select and overrides. + 0x00d4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + sio_26 + 5 + + + pio0_26 + 6 + + + pio1_26 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO27_STATUS + GPIO status + 0x00d8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO27_CTRL + GPIO control including function select and overrides. + 0x00dc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + sio_27 + 5 + + + pio0_27 + 6 + + + pio1_27 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO28_STATUS + GPIO status + 0x00e0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO28_CTRL + GPIO control including function select and overrides. + 0x00e4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + sio_28 + 5 + + + pio0_28 + 6 + + + pio1_28 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO29_STATUS + GPIO status + 0x00e8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO29_CTRL + GPIO control including function select and overrides. + 0x00ec + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + sio_29 + 5 + + + pio0_29 + 6 + + + pio1_29 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + INTR0 + Raw Interrupts + 0x00f0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO7_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO6_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO5_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO4_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO3_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO2_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO1_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO0_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + INTR1 + Raw Interrupts + 0x00f4 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO15_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO14_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO13_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO12_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO11_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO10_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO9_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO8_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + INTR2 + Raw Interrupts + 0x00f8 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO23_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO22_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO21_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO20_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO19_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO18_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO17_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO16_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + INTR3 + Raw Interrupts + 0x00fc + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO29_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO28_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO27_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO26_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO25_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO24_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE0 + Interrupt Enable for proc0 + 0x0100 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE1 + Interrupt Enable for proc0 + 0x0104 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE2 + Interrupt Enable for proc0 + 0x0108 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE3 + Interrupt Enable for proc0 + 0x010c + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF0 + Interrupt Force for proc0 + 0x0110 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF1 + Interrupt Force for proc0 + 0x0114 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF2 + Interrupt Force for proc0 + 0x0118 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF3 + Interrupt Force for proc0 + 0x011c + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS0 + Interrupt status after masking & forcing for proc0 + 0x0120 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS1 + Interrupt status after masking & forcing for proc0 + 0x0124 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS2 + Interrupt status after masking & forcing for proc0 + 0x0128 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS3 + Interrupt status after masking & forcing for proc0 + 0x012c + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE0 + Interrupt Enable for proc1 + 0x0130 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE1 + Interrupt Enable for proc1 + 0x0134 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE2 + Interrupt Enable for proc1 + 0x0138 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE3 + Interrupt Enable for proc1 + 0x013c + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF0 + Interrupt Force for proc1 + 0x0140 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF1 + Interrupt Force for proc1 + 0x0144 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF2 + Interrupt Force for proc1 + 0x0148 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF3 + Interrupt Force for proc1 + 0x014c + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS0 + Interrupt status after masking & forcing for proc1 + 0x0150 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS1 + Interrupt status after masking & forcing for proc1 + 0x0154 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS2 + Interrupt status after masking & forcing for proc1 + 0x0158 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS3 + Interrupt status after masking & forcing for proc1 + 0x015c + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE0 + Interrupt Enable for dormant_wake + 0x0160 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE1 + Interrupt Enable for dormant_wake + 0x0164 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE2 + Interrupt Enable for dormant_wake + 0x0168 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE3 + Interrupt Enable for dormant_wake + 0x016c + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF0 + Interrupt Force for dormant_wake + 0x0170 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF1 + Interrupt Force for dormant_wake + 0x0174 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF2 + Interrupt Force for dormant_wake + 0x0178 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF3 + Interrupt Force for dormant_wake + 0x017c + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS0 + Interrupt status after masking & forcing for dormant_wake + 0x0180 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS1 + Interrupt status after masking & forcing for dormant_wake + 0x0184 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS2 + Interrupt status after masking & forcing for dormant_wake + 0x0188 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS3 + Interrupt status after masking & forcing for dormant_wake + 0x018c + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + + + IO_QSPI + 1 + 0x40018000 + 32 + + 0 + 0x1000 + registers + + + IO_IRQ_QSPI + 14 + + + + GPIO_QSPI_SCLK_STATUS + GPIO status + 0x0000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SCLK_CTRL + GPIO control including function select and overrides. + 0x0004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + xip_sclk + 0 + + + sio_30 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SS_STATUS + GPIO status + 0x0008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SS_CTRL + GPIO control including function select and overrides. + 0x000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + xip_ss_n + 0 + + + sio_31 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD0_STATUS + GPIO status + 0x0010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SD0_CTRL + GPIO control including function select and overrides. + 0x0014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + xip_sd0 + 0 + + + sio_32 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD1_STATUS + GPIO status + 0x0018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SD1_CTRL + GPIO control including function select and overrides. + 0x001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + xip_sd1 + 0 + + + sio_33 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD2_STATUS + GPIO status + 0x0020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SD2_CTRL + GPIO control including function select and overrides. + 0x0024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + xip_sd2 + 0 + + + sio_34 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD3_STATUS + GPIO status + 0x0028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SD3_CTRL + GPIO control including function select and overrides. + 0x002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [13:12] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + [4:0] + read-write + + + xip_sd3 + 0 + + + sio_35 + 5 + + + null + 31 + + + + + + + INTR + Raw Interrupts + 0x0030 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE + Interrupt Enable for proc0 + 0x0034 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF + Interrupt Force for proc0 + 0x0038 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS + Interrupt status after masking & forcing for proc0 + 0x003c + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE + Interrupt Enable for proc1 + 0x0040 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF + Interrupt Force for proc1 + 0x0044 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS + Interrupt status after masking & forcing for proc1 + 0x0048 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE + Interrupt Enable for dormant_wake + 0x004c + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF + Interrupt Force for dormant_wake + 0x0050 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS + Interrupt status after masking & forcing for dormant_wake + 0x0054 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-only + + + + + + + PADS_BANK0 + 1 + 0x4001c000 + 32 + + 0 + 0x1000 + registers + + + + VOLTAGE_SELECT + Voltage select. Per bank control + 0x0000 + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + Set voltage to 3.3V (DVDD >= 2V5) + 0 + + + 1v8 + Set voltage to 1.8V (DVDD <= 1V8) + 1 + + + + + + + GPIO0 + Pad control register + 0x0004 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO1 + Pad control register + 0x0008 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO2 + Pad control register + 0x000c + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO3 + Pad control register + 0x0010 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO4 + Pad control register + 0x0014 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO5 + Pad control register + 0x0018 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO6 + Pad control register + 0x001c + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO7 + Pad control register + 0x0020 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO8 + Pad control register + 0x0024 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO9 + Pad control register + 0x0028 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO10 + Pad control register + 0x002c + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO11 + Pad control register + 0x0030 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO12 + Pad control register + 0x0034 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO13 + Pad control register + 0x0038 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO14 + Pad control register + 0x003c + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO15 + Pad control register + 0x0040 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO16 + Pad control register + 0x0044 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO17 + Pad control register + 0x0048 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO18 + Pad control register + 0x004c + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO19 + Pad control register + 0x0050 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO20 + Pad control register + 0x0054 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO21 + Pad control register + 0x0058 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO22 + Pad control register + 0x005c + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO23 + Pad control register + 0x0060 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO24 + Pad control register + 0x0064 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO25 + Pad control register + 0x0068 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO26 + Pad control register + 0x006c + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO27 + Pad control register + 0x0070 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO28 + Pad control register + 0x0074 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO29 + Pad control register + 0x0078 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWCLK + Pad control register + 0x007c + 0x000000da + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWD + Pad control register + 0x0080 + 0x0000005a + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + PADS_QSPI + 1 + 0x40020000 + 32 + + 0 + 0x1000 + registers + + + + VOLTAGE_SELECT + Voltage select. Per bank control + 0x0000 + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + Set voltage to 3.3V (DVDD >= 2V5) + 0 + + + 1v8 + Set voltage to 1.8V (DVDD <= 1V8) + 1 + + + + + + + GPIO_QSPI_SCLK + Pad control register + 0x0004 + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD0 + Pad control register + 0x0008 + 0x00000052 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD1 + Pad control register + 0x000c + 0x00000052 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD2 + Pad control register + 0x0010 + 0x00000052 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD3 + Pad control register + 0x0014 + 0x00000052 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SS + Pad control register + 0x0018 + 0x0000005a + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + XOSC + 1 + Controls the crystal oscillator + 0x40024000 + 32 + + 0 + 0x1000 + registers + + + + CTRL + Crystal Oscillator Control + 0x0000 + 0x00000000 + + + ENABLE + On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Frequency range. This resets to 0xAA0 and cannot be changed. + [11:0] + read-write + + + 1_15MHZ + 2720 + + + RESERVED_1 + 2721 + + + RESERVED_2 + 2722 + + + RESERVED_3 + 2723 + + + + + + + STATUS + Crystal Oscillator Status + 0x0004 + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + [24:24] + read-write + oneToClear + + + ENABLED + Oscillator is enabled but not necessarily running and stable, resets to 0 + [12:12] + read-only + + + FREQ_RANGE + The current frequency range setting, always reads 0 + [1:0] + read-only + + + 1_15MHZ + 0 + + + RESERVED_1 + 1 + + + RESERVED_2 + 2 + + + RESERVED_3 + 3 + + + + + + + DORMANT + Crystal Oscillator pause control\n + This is used to save power by pausing the XOSC\n + On power-up this field is initialised to WAKE\n + An invalid write will also select WAKE\n + WARNING: stop the PLLs before selecting dormant mode\n + WARNING: setup the irq before selecting dormant mode + 0x0008 + read-write + 0x00000000 + + + STARTUP + Controls the startup delay + 0x000c + 0x000000c4 + + + X4 + Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. + [20:20] + read-write + + + DELAY + in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. + [13:0] + read-write + + + + + COUNT + A down counter running at the xosc frequency which counts to zero and stops.\n + To start the counter write a non-zero value.\n + Can be used for short software pauses when setting up time sensitive hardware. + 0x001c + 0x00000000 + + + COUNT + [7:0] + read-write + + + + + + + PLL_SYS + 1 + 0x40028000 + 32 + + 0 + 0x1000 + registers + + + + CS + Control and Status\n + GENERAL CONSTRAINTS:\n + Reference clock frequency min=5MHz, max=800MHz\n + Feedback divider min=16, max=320\n + VCO frequency min=750MHz, max=1600MHz + 0x0000 + 0x00000001 + + + LOCK + PLL is locked + [31:31] + read-only + + + BYPASS + Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. + [8:8] + read-write + + + REFDIV + Divides the PLL input reference clock.\n + Behaviour is undefined for div=0.\n + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. + [5:0] + read-write + + + + + PWR + Controls the PLL power modes. + 0x0004 + 0x0000002d + + + VCOPD + PLL VCO powerdown\n + To save power set high when PLL output not required or bypass=1. + [5:5] + read-write + + + POSTDIVPD + PLL post divider powerdown\n + To save power set high when PLL output not required or bypass=1. + [3:3] + read-write + + + DSMPD + PLL DSM powerdown\n + Nothing is achieved by setting this low. + [2:2] + read-write + + + PD + PLL powerdown\n + To save power set high when PLL output not required. + [0:0] + read-write + + + + + FBDIV_INT + Feedback divisor\n + (note: this PLL does not support fractional division) + 0x0008 + 0x00000000 + + + FBDIV_INT + see ctrl reg description for constraints + [11:0] + read-write + + + + + PRIM + Controls the PLL post dividers for the primary output\n + (note: this PLL does not have a secondary output)\n + the primary output is driven from VCO divided by postdiv1*postdiv2 + 0x000c + 0x00077000 + + + POSTDIV1 + divide by 1-7 + [18:16] + read-write + + + POSTDIV2 + divide by 1-7 + [14:12] + read-write + + + + + + + PLL_USB + 0x4002c000 + + + BUSCTRL + 1 + Register block for busfabric control signals and performance counters + 0x40030000 + 32 + + 0 + 0x1000 + registers + + + + BUS_PRIORITY + Set the priority of each master for bus arbitration. + 0x0000 + 0x00000000 + + + DMA_W + 0 - low priority, 1 - high priority + [12:12] + read-write + + + DMA_R + 0 - low priority, 1 - high priority + [8:8] + read-write + + + PROC1 + 0 - low priority, 1 - high priority + [4:4] + read-write + + + PROC0 + 0 - low priority, 1 - high priority + [0:0] + read-write + + + + + BUS_PRIORITY_ACK + Bus priority acknowledge + 0x0004 + 0x00000000 + + + BUS_PRIORITY_ACK + Goes to 1 once all arbiters have registered the new global priority levels.\n + Arbiters update their local priority when servicing a new nonsequential access.\n + In normal circumstances this will happen almost immediately. + [0:0] + read-only + + + + + PERFCTR0 + Bus fabric performance counter 0 + 0x0008 + 0x00000000 + + + PERFCTR0 + Busfabric saturating performance counter 0\n + Count some event signal from the busfabric arbiters.\n + Write any value to clear. Select an event to count using PERFSEL0 + [23:0] + read-write + oneToClear + + + + + PERFSEL0 + Bus fabric performance event select for PERFCTR0 + 0x000c + 0x0000001f + + + PERFSEL0 + Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] + read-write + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + + PERFCTR1 + Bus fabric performance counter 1 + 0x0010 + 0x00000000 + + + PERFCTR1 + Busfabric saturating performance counter 1\n + Count some event signal from the busfabric arbiters.\n + Write any value to clear. Select an event to count using PERFSEL1 + [23:0] + read-write + oneToClear + + + + + PERFSEL1 + Bus fabric performance event select for PERFCTR1 + 0x0014 + 0x0000001f + + + PERFSEL1 + Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] + read-write + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + + PERFCTR2 + Bus fabric performance counter 2 + 0x0018 + 0x00000000 + + + PERFCTR2 + Busfabric saturating performance counter 2\n + Count some event signal from the busfabric arbiters.\n + Write any value to clear. Select an event to count using PERFSEL2 + [23:0] + read-write + oneToClear + + + + + PERFSEL2 + Bus fabric performance event select for PERFCTR2 + 0x001c + 0x0000001f + + + PERFSEL2 + Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] + read-write + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + + PERFCTR3 + Bus fabric performance counter 3 + 0x0020 + 0x00000000 + + + PERFCTR3 + Busfabric saturating performance counter 3\n + Count some event signal from the busfabric arbiters.\n + Write any value to clear. Select an event to count using PERFSEL3 + [23:0] + read-write + oneToClear + + + + + PERFSEL3 + Bus fabric performance event select for PERFCTR3 + 0x0024 + 0x0000001f + + + PERFSEL3 + Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] + read-write + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + + + + UART0 + 1 + 0x40034000 + 32 + + 0 + 0x1000 + registers + + + UART0_IRQ + 20 + + + + UARTDR + Data Register, UARTDR + 0x0000 + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. + [11:11] + read-only + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. + [10:10] + read-only + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. + [9:9] + read-only + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. + [8:8] + read-only + + + DATA + Receive (read) data character. Transmit (write) data character. + [7:0] + read-write + + + + + UARTRSR + Receive Status Register/Error Clear Register, UARTRSR/UARTECR + 0x0004 + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. + [3:3] + read-write + oneToClear + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. + [2:2] + read-write + oneToClear + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [1:1] + read-write + oneToClear + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [0:0] + read-write + oneToClear + + + + + UARTFR + Flag Register, UARTFR + 0x0018 + 0x00000090 + + + RI + Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. + [8:8] + read-only + + + TXFE + Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. + [7:7] + read-only + + + RXFF + Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. + [6:6] + read-only + + + TXFF + Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + [5:5] + read-only + + + RXFE + Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + [4:4] + read-only + + + BUSY + UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. + [3:3] + read-only + + + DCD + Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + [2:2] + read-only + + + DSR + Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. + [1:1] + read-only + + + CTS + Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. + [0:0] + read-only + + + + + UARTILPR + IrDA Low-Power Counter Register, UARTILPR + 0x0020 + 0x00000000 + + + ILPDVSR + 8-bit low-power divisor value. These bits are cleared to 0 at reset. + [7:0] + read-write + + + + + UARTIBRD + Integer Baud Rate Register, UARTIBRD + 0x0024 + 0x00000000 + + + BAUD_DIVINT + The integer baud rate divisor. These bits are cleared to 0 on reset. + [15:0] + read-write + + + + + UARTFBRD + Fractional Baud Rate Register, UARTFBRD + 0x0028 + 0x00000000 + + + BAUD_DIVFRAC + The fractional baud rate divisor. These bits are cleared to 0 on reset. + [5:0] + read-write + + + + + UARTLCR_H + Line Control Register, UARTLCR_H + 0x002c + 0x00000000 + + + SPS + Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. + [7:7] + read-write + + + WLEN + Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + [6:5] + read-write + + + FEN + Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). + [4:4] + read-write + + + STP2 + Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. + [3:3] + read-write + + + EPS + Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. + [2:2] + read-write + + + PEN + Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + [1:1] + read-write + + + BRK + Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + [0:0] + read-write + + + + + UARTCR + Control Register, UARTCR + 0x0030 + 0x00000300 + + + CTSEN + CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. + [15:15] + read-write + + + RTSEN + RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. + [14:14] + read-write + + + OUT2 + This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). + [13:13] + read-write + + + OUT1 + This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). + [12:12] + read-write + + + RTS + Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. + [11:11] + read-write + + + DTR + Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. + [10:10] + read-write + + + RXE + Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. + [9:9] + read-write + + + TXE + Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. + [8:8] + read-write + + + LBE + Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. + [7:7] + read-write + + + SIRLP + SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. + [2:2] + read-write + + + SIREN + SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. + [1:1] + read-write + + + UARTEN + UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. + [0:0] + read-write + + + + + UARTIFLS + Interrupt FIFO Level Select Register, UARTIFLS + 0x0034 + 0x00000012 + + + RXIFLSEL + Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. + [5:3] + read-write + + + TXIFLSEL + Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. + [2:0] + read-write + + + + + UARTIMSC + Interrupt Mask Set/Clear Register, UARTIMSC + 0x0038 + 0x00000000 + + + OEIM + Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. + [10:10] + read-write + + + BEIM + Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. + [9:9] + read-write + + + PEIM + Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. + [8:8] + read-write + + + FEIM + Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. + [7:7] + read-write + + + RTIM + Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. + [6:6] + read-write + + + TXIM + Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. + [5:5] + read-write + + + RXIM + Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. + [4:4] + read-write + + + DSRMIM + nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + [3:3] + read-write + + + DCDMIM + nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. + [2:2] + read-write + + + CTSMIM + nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + [1:1] + read-write + + + RIMIM + nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + [0:0] + read-write + + + + + UARTRIS + Raw Interrupt Status Register, UARTRIS + 0x003c + 0x00000000 + + + OERIS + Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BERIS + Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PERIS + Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FERIS + Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTRIS + Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a + [6:6] + read-only + + + TXRIS + Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXRIS + Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRRMIS + nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDRMIS + nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSRMIS + nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIRMIS + nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTMIS + Masked Interrupt Status Register, UARTMIS + 0x0040 + 0x00000000 + + + OEMIS + Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BEMIS + Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PEMIS + Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FEMIS + Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTMIS + Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. + [6:6] + read-only + + + TXMIS + Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXMIS + Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRMMIS + nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDMMIS + nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSMMIS + nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIMMIS + nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTICR + Interrupt Clear Register, UARTICR + 0x0044 + 0x00000000 + + + OEIC + Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + [10:10] + read-write + oneToClear + + + BEIC + Break error interrupt clear. Clears the UARTBEINTR interrupt. + [9:9] + read-write + oneToClear + + + PEIC + Parity error interrupt clear. Clears the UARTPEINTR interrupt. + [8:8] + read-write + oneToClear + + + FEIC + Framing error interrupt clear. Clears the UARTFEINTR interrupt. + [7:7] + read-write + oneToClear + + + RTIC + Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + [6:6] + read-write + oneToClear + + + TXIC + Transmit interrupt clear. Clears the UARTTXINTR interrupt. + [5:5] + read-write + oneToClear + + + RXIC + Receive interrupt clear. Clears the UARTRXINTR interrupt. + [4:4] + read-write + oneToClear + + + DSRMIC + nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + [3:3] + read-write + oneToClear + + + DCDMIC + nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + [2:2] + read-write + oneToClear + + + CTSMIC + nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + [1:1] + read-write + oneToClear + + + RIMIC + nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + [0:0] + read-write + oneToClear + + + + + UARTDMACR + DMA Control Register, UARTDMACR + 0x0048 + 0x00000000 + + + DMAONERR + DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. + [2:2] + read-write + + + TXDMAE + Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + UARTPERIPHID0 + UARTPeriphID0 Register + 0x0fe0 + 0x00000011 + + + PARTNUMBER0 + These bits read back as 0x11 + [7:0] + read-only + + + + + UARTPERIPHID1 + UARTPeriphID1 Register + 0x0fe4 + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + UARTPERIPHID2 + UARTPeriphID2 Register + 0x0fe8 + 0x00000034 + + + REVISION + This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + UARTPERIPHID3 + UARTPeriphID3 Register + 0x0fec + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + UARTPCELLID0 + UARTPCellID0 Register + 0x0ff0 + 0x0000000d + + + UARTPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + UARTPCELLID1 + UARTPCellID1 Register + 0x0ff4 + 0x000000f0 + + + UARTPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + UARTPCELLID2 + UARTPCellID2 Register + 0x0ff8 + 0x00000005 + + + UARTPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + UARTPCELLID3 + UARTPCellID3 Register + 0x0ffc + 0x000000b1 + + + UARTPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + UART1 + 0x40038000 + + UART1_IRQ + 21 + + + + SPI0 + 1 + 0x4003c000 + 32 + + 0 + 0x1000 + registers + + + SPI0_IRQ + 18 + + + + SSPCR0 + Control register 0, SSPCR0 on page 3-4 + 0x0000 + 0x00000000 + + + SCR + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. + [15:8] + read-write + + + SPH + SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [7:7] + read-write + + + SPO + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [6:6] + read-write + + + FRF + Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. + [5:4] + read-write + + + DSS + Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. + [3:0] + read-write + + + + + SSPCR1 + Control register 1, SSPCR1 on page 3-5 + 0x0004 + 0x00000000 + + + SOD + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + [3:3] + read-write + + + MS + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + [2:2] + read-write + + + SSE + Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. + [1:1] + read-write + + + LBM + Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. + [0:0] + read-write + + + + + SSPDR + Data register, SSPDR on page 3-6 + 0x0008 + 0x00000000 + + + DATA + Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write + + + + + SSPSR + Status register, SSPSR on page 3-7 + 0x000c + 0x00000003 + + + BSY + PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + RFF + Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + [3:3] + read-only + + + RNE + Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. + [2:2] + read-only + + + TNF + Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. + [1:1] + read-only + + + TFE + Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + [0:0] + read-only + + + + + SSPCPSR + Clock prescale register, SSPCPSR on page 3-8 + 0x0010 + 0x00000000 + + + CPSDVSR + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + SSPIMSC + Interrupt mask set or clear register, SSPIMSC on page 3-9 + 0x0014 + 0x00000000 + + + TXIM + Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + [3:3] + read-write + + + RXIM + Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + [2:2] + read-write + + + RTIM + Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + [1:1] + read-write + + + RORIM + Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + [0:0] + read-write + + + + + SSPRIS + Raw interrupt status register, SSPRIS on page 3-10 + 0x0018 + 0x00000008 + + + TXRIS + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXRIS + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTRIS + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORRIS + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPMIS + Masked interrupt status register, SSPMIS on page 3-11 + 0x001c + 0x00000000 + + + TXMIS + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXMIS + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTMIS + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORMIS + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPICR + Interrupt clear register, SSPICR on page 3-11 + 0x0020 + 0x00000000 + + + RTIC + Clears the SSPRTINTR interrupt + [1:1] + read-write + oneToClear + + + RORIC + Clears the SSPRORINTR interrupt + [0:0] + read-write + oneToClear + + + + + SSPDMACR + DMA control register, SSPDMACR on page 3-12 + 0x0024 + 0x00000000 + + + TXDMAE + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + SSPPERIPHID0 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x0fe0 + 0x00000022 + + + PARTNUMBER0 + These bits read back as 0x22 + [7:0] + read-only + + + + + SSPPERIPHID1 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x0fe4 + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + SSPPERIPHID2 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x0fe8 + 0x00000034 + + + REVISION + These bits return the peripheral revision + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + SSPPERIPHID3 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x0fec + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + SSPPCELLID0 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x0ff0 + 0x0000000d + + + SSPPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + SSPPCELLID1 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x0ff4 + 0x000000f0 + + + SSPPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + SSPPCELLID2 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x0ff8 + 0x00000005 + + + SSPPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + SSPPCELLID3 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x0ffc + 0x000000b1 + + + SSPPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + SPI1 + 0x40040000 + + SPI1_IRQ + 19 + + + + I2C0 + 1 + DW_apb_i2c address block\n\n + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n + IC_ULTRA_FAST_MODE ................ 0x0\n + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n + IC_UFM_SCL_LOW_COUNT .............. 0x0008\n + IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n + IC_TX_TL .......................... 0x0\n + IC_TX_CMD_BLOCK ................... 0x1\n + IC_HAS_DMA ........................ 0x1\n + IC_HAS_ASYNC_FIFO ................. 0x0\n + IC_SMBUS_ARP ...................... 0x0\n + IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n + IC_INTR_IO ........................ 0x1\n + IC_MASTER_MODE .................... 0x1\n + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n + IC_INTR_POL ....................... 0x1\n + IC_OPTIONAL_SAR ................... 0x0\n + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n + IC_DEFAULT_SLAVE_ADDR ............. 0x055\n + IC_DEFAULT_HS_SPKLEN .............. 0x1\n + IC_FS_SCL_HIGH_COUNT .............. 0x0006\n + IC_HS_SCL_LOW_COUNT ............... 0x0008\n + IC_DEVICE_ID_VALUE ................ 0x0\n + IC_10BITADDR_MASTER ............... 0x0\n + IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n + IC_DEFAULT_FS_SPKLEN .............. 0x7\n + IC_ADD_ENCODED_PARAMS ............. 0x0\n + IC_DEFAULT_SDA_HOLD ............... 0x000001\n + IC_DEFAULT_SDA_SETUP .............. 0x64\n + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n + IC_CLOCK_PERIOD ................... 100\n + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n + IC_RESTART_EN ..................... 0x1\n + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n + IC_BUS_CLEAR_FEATURE .............. 0x0\n + IC_CAP_LOADING .................... 100\n + IC_FS_SCL_LOW_COUNT ............... 0x000d\n + APB_DATA_WIDTH .................... 32\n + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + IC_SLV_DATA_NACK_ONLY ............. 0x1\n + IC_10BITADDR_SLAVE ................ 0x0\n + IC_CLK_TYPE ....................... 0x0\n + IC_SMBUS_UDID_MSB ................. 0x0\n + IC_SMBUS_SUSPEND_ALERT ............ 0x0\n + IC_HS_SCL_HIGH_COUNT .............. 0x0006\n + IC_SLV_RESTART_DET_EN ............. 0x1\n + IC_SMBUS .......................... 0x0\n + IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n + IC_USE_COUNTS ..................... 0x0\n + IC_RX_BUFFER_DEPTH ................ 16\n + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + IC_RX_FULL_HLD_BUS_EN ............. 0x1\n + IC_SLAVE_DISABLE .................. 0x1\n + IC_RX_TL .......................... 0x0\n + IC_DEVICE_ID ...................... 0x0\n + IC_HC_COUNT_VALUES ................ 0x0\n + I2C_DYNAMIC_TAR_UPDATE ............ 0\n + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n + IC_HS_MASTER_CODE ................. 0x1\n + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n + IC_SS_SCL_HIGH_COUNT .............. 0x0028\n + IC_SS_SCL_LOW_COUNT ............... 0x002f\n + IC_MAX_SPEED_MODE ................. 0x2\n + IC_STAT_FOR_CLK_STRETCH ........... 0x0\n + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n + IC_DEFAULT_UFM_SPKLEN ............. 0x1\n + IC_TX_BUFFER_DEPTH ................ 16 + 0x40044000 + 32 + + 0 + 0x0100 + registers + + + I2C0_IRQ + 23 + + + + IC_CON + I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + 0x0000 + 0x00000065 + + + STOP_DET_IF_MASTER_ACTIVE + Master issues the STOP_DET interrupt irrespective of whether master is active or not + [10:10] + read-only + + + RX_FIFO_FULL_HLD_CTRL + This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n + Reset value: 0x0. + [9:9] + read-write + + + DISABLED + Overflow when RX_FIFO is full + 0 + + + ENABLED + Hold bus when RX_FIFO is full + 1 + + + + + TX_EMPTY_CTRL + This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0. + [8:8] + read-write + + + DISABLED + Default behaviour of TX_EMPTY interrupt + 0 + + + ENABLED + Controlled generation of TX_EMPTY interrupt + 1 + + + + + STOP_DET_IFADDRESSED + In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + [7:7] + read-write + + + DISABLED + slave issues STOP_DET intr always + 0 + + + ENABLED + slave issues STOP_DET intr only if addressed + 1 + + + + + IC_SLAVE_DISABLE + This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + [6:6] + read-write + + + SLAVE_ENABLED + Slave mode is enabled + 0 + + + SLAVE_DISABLED + Slave mode is disabled + 1 + + + + + IC_RESTART_EN + Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n + Reset value: ENABLED + [5:5] + read-write + + + DISABLED + Master restart disabled + 0 + + + ENABLED + Master restart enabled + 1 + + + + + IC_10BITADDR_MASTER + Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + [4:4] + read-write + + + ADDR_7BITS + Master 7Bit addressing mode + 0 + + + ADDR_10BITS + Master 10Bit addressing mode + 1 + + + + + IC_10BITADDR_SLAVE + When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + [3:3] + read-write + + + ADDR_7BITS + Slave 7Bit addressing + 0 + + + ADDR_10BITS + Slave 10Bit addressing + 1 + + + + + SPEED + These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n + 1: standard mode (100 kbit/s)\n\n + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n + 3: high speed mode (3.4 Mbit/s)\n\n + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + [2:1] + read-write + + + STANDARD + Standard Speed mode of operation + 1 + + + FAST + Fast or Fast Plus mode of operation + 2 + + + HIGH + High Speed mode of operation + 3 + + + + + MASTER_MODE + This bit controls whether the DW_apb_i2c master is enabled.\n\n + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + [0:0] + read-write + + + DISABLED + Master mode is disabled + 0 + + + ENABLED + Master mode is enabled + 1 + + + + + + + IC_TAR + I2C Target Address Register\n\n + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + 0x0004 + 0x00000055 + + + SPECIAL + This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + [11:11] + read-write + + + DISABLED + Disables programming of GENERAL_CALL or START_BYTE transmission + 0 + + + ENABLED + Enables programming of GENERAL_CALL or START_BYTE transmission + 1 + + + + + GC_OR_START + If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + [10:10] + read-write + + + GENERAL_CALL + GENERAL_CALL byte transmission + 0 + + + START_BYTE + START byte transmission + 1 + + + + + IC_TAR + This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. + [9:0] + read-write + + + + + IC_SAR + I2C Slave Address Register + 0x0008 + 0x00000055 + + + IC_SAR + The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. + [9:0] + read-write + + + + + IC_DATA_CMD + I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n + The size of the register changes as follows:\n\n + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + 0x0010 + 0x00000000 + + + FIRST_DATA_BYTE + Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n + Reset value : 0x0\n\n + NOTE: In case of APB_DATA_WIDTH=8,\n\n + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n + 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n + 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. + [11:11] + read-only + + + INACTIVE + Sequential data byte received + 0 + + + ACTIVE + Non sequential data byte received + 1 + + + + + RESTART + This bit controls whether a RESTART is issued before the byte is sent or received.\n\n + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n + Reset value: 0x0 + [10:10] + read-write + clear + + + DISABLE + Don't Issue RESTART before this command + 0 + + + ENABLE + Issue RESTART before this command + 1 + + + + + STOP + This bit controls whether a STOP is issued after the byte is sent or received.\n\n + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + [9:9] + read-write + clear + + + DISABLE + Don't Issue STOP after this command + 0 + + + ENABLE + Issue STOP after this command + 1 + + + + + CMD + This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n + Reset value: 0x0 + [8:8] + read-write + clear + + + WRITE + Master Write Command + 0 + + + READ + Master Read Command + 1 + + + + + DAT + This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n + Reset value: 0x0 + [7:0] + read-write + + + + + IC_SS_SCL_HCNT + Standard Speed I2C Clock SCL High Count Register + 0x0014 + 0x00000028 + + + IC_SS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. + [15:0] + read-write + + + + + IC_SS_SCL_LCNT + Standard Speed I2C Clock SCL Low Count Register + 0x0018 + 0x0000002f + + + IC_SS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_HCNT + Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + 0x001c + 0x00000006 + + + IC_FS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_LCNT + Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + 0x0020 + 0x0000000d + + + IC_FS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. + [15:0] + read-write + + + + + IC_INTR_STAT + I2C Interrupt Status Register\n\n + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + 0x002c + 0x00000000 + + + R_RESTART_DET + See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + R_RESTART_DET interrupt is inactive + 0 + + + ACTIVE + R_RESTART_DET interrupt is active + 1 + + + + + R_GEN_CALL + See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + R_GEN_CALL interrupt is inactive + 0 + + + ACTIVE + R_GEN_CALL interrupt is active + 1 + + + + + R_START_DET + See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + R_START_DET interrupt is inactive + 0 + + + ACTIVE + R_START_DET interrupt is active + 1 + + + + + R_STOP_DET + See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n + Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + R_STOP_DET interrupt is inactive + 0 + + + ACTIVE + R_STOP_DET interrupt is active + 1 + + + + + R_ACTIVITY + See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + R_ACTIVITY interrupt is inactive + 0 + + + ACTIVE + R_ACTIVITY interrupt is active + 1 + + + + + R_RX_DONE + See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + R_RX_DONE interrupt is inactive + 0 + + + ACTIVE + R_RX_DONE interrupt is active + 1 + + + + + R_TX_ABRT + See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + R_TX_ABRT interrupt is inactive + 0 + + + ACTIVE + R_TX_ABRT interrupt is active + 1 + + + + + R_RD_REQ + See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + R_RD_REQ interrupt is inactive + 0 + + + ACTIVE + R_RD_REQ interrupt is active + 1 + + + + + R_TX_EMPTY + See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n + Reset value: 0x0 + [4:4] + read-only + + + INACTIVE + R_TX_EMPTY interrupt is inactive + 0 + + + ACTIVE + R_TX_EMPTY interrupt is active + 1 + + + + + R_TX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + R_TX_OVER interrupt is inactive + 0 + + + ACTIVE + R_TX_OVER interrupt is active + 1 + + + + + R_RX_FULL + See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + R_RX_FULL interrupt is inactive + 0 + + + ACTIVE + R_RX_FULL interrupt is active + 1 + + + + + R_RX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + R_RX_OVER interrupt is inactive + 0 + + + ACTIVE + R_RX_OVER interrupt is active + 1 + + + + + R_RX_UNDER + See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + RX_UNDER interrupt is inactive + 0 + + + ACTIVE + RX_UNDER interrupt is active + 1 + + + + + + + IC_INTR_MASK + I2C Interrupt Mask Register.\n\n + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + 0x0030 + 0x000008ff + + + M_RESTART_DET + This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x0 + [12:12] + read-write + + + ENABLED + RESTART_DET interrupt is masked + 0 + + + DISABLED + RESTART_DET interrupt is unmasked + 1 + + + + + M_GEN_CALL + This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + [11:11] + read-write + + + ENABLED + GEN_CALL interrupt is masked + 0 + + + DISABLED + GEN_CALL interrupt is unmasked + 1 + + + + + M_START_DET + This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x0 + [10:10] + read-write + + + ENABLED + START_DET interrupt is masked + 0 + + + DISABLED + START_DET interrupt is unmasked + 1 + + + + + M_STOP_DET + This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x0 + [9:9] + read-write + + + ENABLED + STOP_DET interrupt is masked + 0 + + + DISABLED + STOP_DET interrupt is unmasked + 1 + + + + + M_ACTIVITY + This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x0 + [8:8] + read-write + + + ENABLED + ACTIVITY interrupt is masked + 0 + + + DISABLED + ACTIVITY interrupt is unmasked + 1 + + + + + M_RX_DONE + This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + [7:7] + read-write + + + ENABLED + RX_DONE interrupt is masked + 0 + + + DISABLED + RX_DONE interrupt is unmasked + 1 + + + + + M_TX_ABRT + This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + [6:6] + read-write + + + ENABLED + TX_ABORT interrupt is masked + 0 + + + DISABLED + TX_ABORT interrupt is unmasked + 1 + + + + + M_RD_REQ + This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + [5:5] + read-write + + + ENABLED + RD_REQ interrupt is masked + 0 + + + DISABLED + RD_REQ interrupt is unmasked + 1 + + + + + M_TX_EMPTY + This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + [4:4] + read-write + + + ENABLED + TX_EMPTY interrupt is masked + 0 + + + DISABLED + TX_EMPTY interrupt is unmasked + 1 + + + + + M_TX_OVER + This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + [3:3] + read-write + + + ENABLED + TX_OVER interrupt is masked + 0 + + + DISABLED + TX_OVER interrupt is unmasked + 1 + + + + + M_RX_FULL + This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + [2:2] + read-write + + + ENABLED + RX_FULL interrupt is masked + 0 + + + DISABLED + RX_FULL interrupt is unmasked + 1 + + + + + M_RX_OVER + This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + [1:1] + read-write + + + ENABLED + RX_OVER interrupt is masked + 0 + + + DISABLED + RX_OVER interrupt is unmasked + 1 + + + + + M_RX_UNDER + This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + [0:0] + read-write + + + ENABLED + RX_UNDER interrupt is masked + 0 + + + DISABLED + RX_UNDER interrupt is unmasked + 1 + + + + + + + IC_RAW_INTR_STAT + I2C Raw Interrupt Status Register\n\n + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + 0x0034 + 0x00000000 + + + RESTART_DET + Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + RESTART_DET interrupt is inactive + 0 + + + ACTIVE + RESTART_DET interrupt is active + 1 + + + + + GEN_CALL + Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + GEN_CALL interrupt is inactive + 0 + + + ACTIVE + GEN_CALL interrupt is active + 1 + + + + + START_DET + Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + START_DET interrupt is inactive + 0 + + + ACTIVE + START_DET interrupt is active + 1 + + + + + STOP_DET + Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n + In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + STOP_DET interrupt is inactive + 0 + + + ACTIVE + STOP_DET interrupt is active + 1 + + + + + ACTIVITY + This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + RAW_INTR_ACTIVITY interrupt is inactive + 0 + + + ACTIVE + RAW_INTR_ACTIVITY interrupt is active + 1 + + + + + RX_DONE + When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + RX_DONE interrupt is inactive + 0 + + + ACTIVE + RX_DONE interrupt is active + 1 + + + + + TX_ABRT + This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + TX_ABRT interrupt is inactive + 0 + + + ACTIVE + TX_ABRT interrupt is active + 1 + + + + + RD_REQ + This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + RD_REQ interrupt is inactive + 0 + + + ACTIVE + RD_REQ interrupt is active + 1 + + + + + TX_EMPTY + The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n + Reset value: 0x0. + [4:4] + read-only + + + INACTIVE + TX_EMPTY interrupt is inactive + 0 + + + ACTIVE + TX_EMPTY interrupt is active + 1 + + + + + TX_OVER + Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + TX_OVER interrupt is inactive + 0 + + + ACTIVE + TX_OVER interrupt is active + 1 + + + + + RX_FULL + Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + RX_FULL interrupt is inactive + 0 + + + ACTIVE + RX_FULL interrupt is active + 1 + + + + + RX_OVER + Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + RX_OVER interrupt is inactive + 0 + + + ACTIVE + RX_OVER interrupt is active + 1 + + + + + RX_UNDER + Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + RX_UNDER interrupt is inactive + 0 + + + ACTIVE + RX_UNDER interrupt is active + 1 + + + + + + + IC_RX_TL + I2C Receive FIFO Threshold Register + 0x0038 + 0x00000000 + + + RX_TL + Receive FIFO Threshold Level.\n\n + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + [7:0] + read-write + + + + + IC_TX_TL + I2C Transmit FIFO Threshold Register + 0x003c + 0x00000000 + + + TX_TL + Transmit FIFO Threshold Level.\n\n + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + [7:0] + read-write + + + + + IC_CLR_INTR + Clear Combined and Individual Interrupt Register + 0x0040 + 0x00000000 + + + CLR_INTR + Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_UNDER + Clear RX_UNDER Interrupt Register + 0x0044 + 0x00000000 + + + CLR_RX_UNDER + Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_OVER + Clear RX_OVER Interrupt Register + 0x0048 + 0x00000000 + + + CLR_RX_OVER + Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_OVER + Clear TX_OVER Interrupt Register + 0x004c + 0x00000000 + + + CLR_TX_OVER + Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RD_REQ + Clear RD_REQ Interrupt Register + 0x0050 + 0x00000000 + + + CLR_RD_REQ + Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_ABRT + Clear TX_ABRT Interrupt Register + 0x0054 + 0x00000000 + + + CLR_TX_ABRT + Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_DONE + Clear RX_DONE Interrupt Register + 0x0058 + 0x00000000 + + + CLR_RX_DONE + Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_ACTIVITY + Clear ACTIVITY Interrupt Register + 0x005c + 0x00000000 + + + CLR_ACTIVITY + Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_STOP_DET + Clear STOP_DET Interrupt Register + 0x0060 + 0x00000000 + + + CLR_STOP_DET + Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_START_DET + Clear START_DET Interrupt Register + 0x0064 + 0x00000000 + + + CLR_START_DET + Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_GEN_CALL + Clear GEN_CALL Interrupt Register + 0x0068 + 0x00000000 + + + CLR_GEN_CALL + Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_ENABLE + I2C Enable Register + 0x006c + 0x00000000 + + + TX_CMD_BLOCK + In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + [2:2] + read-write + + + NOT_BLOCKED + Tx Command execution not blocked + 0 + + + BLOCKED + Tx Command execution blocked + 1 + + + + + ABORT + When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n + Reset value: 0x0 + [1:1] + read-write + + + DISABLE + ABORT operation not in progress + 0 + + + ENABLED + ABORT operation in progress + 1 + + + + + ENABLE + Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n + Reset value: 0x0 + [0:0] + read-write + + + DISABLED + I2C is disabled + 0 + + + ENABLED + I2C is enabled + 1 + + + + + + + IC_STATUS + I2C Status Register\n\n + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + 0x0070 + 0x00000006 + + + SLV_ACTIVITY + Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + [6:6] + read-only + + + IDLE + Slave is idle + 0 + + + ACTIVE + Slave not idle + 1 + + + + + MST_ACTIVITY + Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n + Reset value: 0x0 + [5:5] + read-only + + + IDLE + Master is idle + 0 + + + ACTIVE + Master not idle + 1 + + + + + RFF + Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + [4:4] + read-only + + + NOT_FULL + Rx FIFO not full + 0 + + + FULL + Rx FIFO is full + 1 + + + + + RFNE + Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + [3:3] + read-only + + + EMPTY + Rx FIFO is empty + 0 + + + NOT_EMPTY + Rx FIFO not empty + 1 + + + + + TFE + Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + [2:2] + read-only + + + NON_EMPTY + Tx FIFO not empty + 0 + + + EMPTY + Tx FIFO is empty + 1 + + + + + TFNF + Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + [1:1] + read-only + + + FULL + Tx FIFO is full + 0 + + + NOT_FULL + Tx FIFO not full + 1 + + + + + ACTIVITY + I2C Activity Status. Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + I2C is idle + 0 + + + ACTIVE + I2C is active + 1 + + + + + + + IC_TXFLR + I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + 0x0074 + 0x00000000 + + + TXFLR + Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n + Reset value: 0x0 + [4:0] + read-only + + + + + IC_RXFLR + I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + 0x0078 + 0x00000000 + + + RXFLR + Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n + Reset value: 0x0 + [4:0] + read-only + + + + + IC_SDA_HOLD + I2C SDA Hold Time Length Register\n\n + The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n + The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n + Writes to this register succeed only when IC_ENABLE[0]=0.\n\n + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + 0x007c + 0x00000001 + + + IC_SDA_RX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n + Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + [23:16] + read-write + + + IC_SDA_TX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n + Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + [15:0] + read-write + + + + + IC_TX_ABRT_SOURCE + I2C Transmit Abort Source Register\n\n + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + 0x0080 + 0x00000000 + + + TX_FLUSH_CNT + This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [31:23] + read-only + + + ABRT_USER_ABRT + This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter + [16:16] + read-only + + + ABRT_USER_ABRT_VOID + Transfer abort detected by master- scenario not present + 0 + + + ABRT_USER_ABRT_GENERATED + Transfer abort detected by master + 1 + + + + + ABRT_SLVRD_INTX + 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Slave-Transmitter + [15:15] + read-only + + + ABRT_SLVRD_INTX_VOID + Slave trying to transmit to remote master in read mode- scenario not present + 0 + + + ABRT_SLVRD_INTX_GENERATED + Slave trying to transmit to remote master in read mode + 1 + + + + + ABRT_SLV_ARBLOST + This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Slave-Transmitter + [14:14] + read-only + + + ABRT_SLV_ARBLOST_VOID + Slave lost arbitration to remote master- scenario not present + 0 + + + ABRT_SLV_ARBLOST_GENERATED + Slave lost arbitration to remote master + 1 + + + + + ABRT_SLVFLUSH_TXFIFO + This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Slave-Transmitter + [13:13] + read-only + + + ABRT_SLVFLUSH_TXFIFO_VOID + Slave flushes existing data in TX-FIFO upon getting read command- scenario not present + 0 + + + ABRT_SLVFLUSH_TXFIFO_GENERATED + Slave flushes existing data in TX-FIFO upon getting read command + 1 + + + + + ARB_LOST + This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [12:12] + read-only + + + ABRT_LOST_VOID + Master or Slave-Transmitter lost arbitration- scenario not present + 0 + + + ABRT_LOST_GENERATED + Master or Slave-Transmitter lost arbitration + 1 + + + + + ABRT_MASTER_DIS + This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [11:11] + read-only + + + ABRT_MASTER_DIS_VOID + User initiating master operation when MASTER disabled- scenario not present + 0 + + + ABRT_MASTER_DIS_GENERATED + User initiating master operation when MASTER disabled + 1 + + + + + ABRT_10B_RD_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Receiver + [10:10] + read-only + + + ABRT_10B_RD_VOID + Master not trying to read in 10Bit addressing mode when RESTART disabled + 0 + + + ABRT_10B_RD_GENERATED + Master trying to read in 10Bit addressing mode when RESTART disabled + 1 + + + + + ABRT_SBYTE_NORSTRT + To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master + [9:9] + read-only + + + ABRT_SBYTE_NORSTRT_VOID + User trying to send START byte when RESTART disabled- scenario not present + 0 + + + ABRT_SBYTE_NORSTRT_GENERATED + User trying to send START byte when RESTART disabled + 1 + + + + + ABRT_HS_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [8:8] + read-only + + + ABRT_HS_NORSTRT_VOID + User trying to switch Master to HS mode when RESTART disabled- scenario not present + 0 + + + ABRT_HS_NORSTRT_GENERATED + User trying to switch Master to HS mode when RESTART disabled + 1 + + + + + ABRT_SBYTE_ACKDET + This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master + [7:7] + read-only + + + ABRT_SBYTE_ACKDET_VOID + ACK detected for START byte- scenario not present + 0 + + + ABRT_SBYTE_ACKDET_GENERATED + ACK detected for START byte + 1 + + + + + ABRT_HS_ACKDET + This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master + [6:6] + read-only + + + ABRT_HS_ACK_VOID + HS Master code ACKed in HS Mode- scenario not present + 0 + + + ABRT_HS_ACK_GENERATED + HS Master code ACKed in HS Mode + 1 + + + + + ABRT_GCALL_READ + This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter + [5:5] + read-only + + + ABRT_GCALL_READ_VOID + GCALL is followed by read from bus-scenario not present + 0 + + + ABRT_GCALL_READ_GENERATED + GCALL is followed by read from bus + 1 + + + + + ABRT_GCALL_NOACK + This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter + [4:4] + read-only + + + ABRT_GCALL_NOACK_VOID + GCALL not ACKed by any slave-scenario not present + 0 + + + ABRT_GCALL_NOACK_GENERATED + GCALL not ACKed by any slave + 1 + + + + + ABRT_TXDATA_NOACK + This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter + [3:3] + read-only + + + ABRT_TXDATA_NOACK_VOID + Transmitted data non-ACKed by addressed slave-scenario not present + 0 + + + ABRT_TXDATA_NOACK_GENERATED + Transmitted data not ACKed by addressed slave + 1 + + + + + ABRT_10ADDR2_NOACK + This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [2:2] + read-only + + + INACTIVE + This abort is not generated + 0 + + + ACTIVE + Byte 2 of 10Bit Address not ACKed by any slave + 1 + + + + + ABRT_10ADDR1_NOACK + This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [1:1] + read-only + + + INACTIVE + This abort is not generated + 0 + + + ACTIVE + Byte 1 of 10Bit Address not ACKed by any slave + 1 + + + + + ABRT_7B_ADDR_NOACK + This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [0:0] + read-only + + + INACTIVE + This abort is not generated + 0 + + + ACTIVE + This abort is generated because of NOACK for 7-bit address + 1 + + + + + + + IC_SLV_DATA_NACK_ONLY + Generate Slave Data NACK Register\n\n + The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n + A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + 0x0084 + 0x00000000 + + + NACK + Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + [0:0] + read-write + + + DISABLED + Slave receiver generates NACK normally + 0 + + + ENABLED + Slave receiver generates NACK upon data reception only + 1 + + + + + + + IC_DMA_CR + DMA Control Register\n\n + The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + 0x0088 + 0x00000000 + + + TDMAE + Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + [1:1] + read-write + + + DISABLED + transmit FIFO DMA channel disabled + 0 + + + ENABLED + Transmit FIFO DMA channel enabled + 1 + + + + + RDMAE + Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + [0:0] + read-write + + + DISABLED + Receive FIFO DMA channel disabled + 0 + + + ENABLED + Receive FIFO DMA channel enabled + 1 + + + + + + + IC_DMA_TDLR + DMA Transmit Data Level Register + 0x008c + 0x00000000 + + + DMATDL + Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n + Reset value: 0x0 + [3:0] + read-write + + + + + IC_DMA_RDLR + I2C Receive Data Level Register + 0x0090 + 0x00000000 + + + DMARDL + Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n + Reset value: 0x0 + [3:0] + read-write + + + + + IC_SDA_SETUP + I2C SDA Setup Register\n\n + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n + Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n + Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + 0x0094 + 0x00000064 + + + SDA_SETUP + SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. + [7:0] + read-write + + + + + IC_ACK_GENERAL_CALL + I2C ACK General Call Register\n\n + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n + This register is applicable only when the DW_apb_i2c is in slave mode. + 0x0098 + 0x00000001 + + + ACK_GEN_CALL + ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + [0:0] + read-write + + + DISABLED + Generate NACK for a General Call + 0 + + + ENABLED + Generate ACK for a General Call + 1 + + + + + + + IC_ENABLE_STATUS + I2C Enable Status Register\n\n + The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n + If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n + Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + 0x009c + 0x00000000 + + + SLV_RX_DATA_LOST + Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + Slave RX Data is not lost + 0 + + + ACTIVE + Slave RX Data is lost + 1 + + + + + SLV_DISABLED_WHILE_BUSY + Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n + OR,\n\n + (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + Slave is disabled when it is idle + 0 + + + ACTIVE + Slave is disabled when it is active + 1 + + + + + IC_EN + ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n + Reset value: 0x0 + [0:0] + read-only + + + DISABLED + I2C disabled + 0 + + + ENABLED + I2C enabled + 1 + + + + + + + IC_FS_SPKLEN + I2C SS, FS or FM+ spike suppression limit\n\n + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + 0x00a0 + 0x00000007 + + + IC_FS_SPKLEN + This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. + [7:0] + read-write + + + + + IC_CLR_RESTART_DET + Clear RESTART_DET Interrupt Register + 0x00a8 + 0x00000000 + + + CLR_RESTART_DET + Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + [0:0] + read-only + + + + + IC_COMP_PARAM_1 + Component Parameter Register 1\n\n + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + 0x00f4 + 0x00000000 + + + TX_BUFFER_DEPTH + TX Buffer Depth = 16 + [23:16] + read-only + + + RX_BUFFER_DEPTH + RX Buffer Depth = 16 + [15:8] + read-only + + + ADD_ENCODED_PARAMS + Encoded parameters not visible + [7:7] + read-only + + + HAS_DMA + DMA handshaking signals are enabled + [6:6] + read-only + + + INTR_IO + COMBINED Interrupt outputs + [5:5] + read-only + + + HC_COUNT_VALUES + Programmable count values for each mode. + [4:4] + read-only + + + MAX_SPEED_MODE + MAX SPEED MODE = FAST MODE + [3:2] + read-only + + + APB_DATA_WIDTH + APB data bus width is 32 bits + [1:0] + read-only + + + + + IC_COMP_VERSION + I2C Component Version Register + 0x00f8 + 0x3230312a + + + IC_COMP_VERSION + [31:0] + read-only + + + + + IC_COMP_TYPE + I2C Component Type Register + 0x00fc + 0x44570140 + + + IC_COMP_TYPE + Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. + [31:0] + read-only + + + + + + + I2C1 + 0x40048000 + + I2C1_IRQ + 24 + + + + ADC + 2 + Control and data interface to SAR ADC + 0x4004c000 + 32 + + 0 + 0x1000 + registers + + + ADC_IRQ_FIFO + 22 + + + + CS + ADC Control and Status + 0x0000 + 0x00000000 + + + RROBIN + Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n + The first channel to be sampled will be the one currently indicated by AINSEL.\n + AINSEL will be updated after each conversion with the newly-selected channel. + [20:16] + read-write + + + AINSEL + Select analog mux input. Updated automatically in round-robin mode. + [14:12] + read-write + + + ERR_STICKY + Some past ADC conversion encountered an error. Write 1 to clear. + [10:10] + read-write + oneToClear + + + ERR + The most recent ADC conversion encountered an error; result is undefined or noisy. + [9:9] + read-only + + + READY + 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n + 0 whilst conversion in progress. + [8:8] + read-only + + + START_MANY + Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. + [3:3] + read-write + + + START_ONCE + Start a single conversion. Self-clearing. Ignored if start_many is asserted. + [2:2] + read-write + clear + + + TS_EN + Power on temperature sensor. 1 - enabled. 0 - disabled. + [1:1] + read-write + + + EN + Power on ADC and enable its clock.\n + 1 - enabled. 0 - disabled. + [0:0] + read-write + + + + + RESULT + Result of most recent ADC conversion + 0x0004 + 0x00000000 + + + RESULT + [11:0] + read-only + + + + + FCS + FIFO control and status + 0x0008 + 0x00000000 + + + THRESH + DREQ/IRQ asserted when level >= threshold + [27:24] + read-write + + + LEVEL + The number of conversion results currently waiting in the FIFO + [19:16] + read-only + + + OVER + 1 if the FIFO has been overflowed. Write 1 to clear. + [11:11] + read-write + oneToClear + + + UNDER + 1 if the FIFO has been underflowed. Write 1 to clear. + [10:10] + read-write + oneToClear + + + FULL + [9:9] + read-only + + + EMPTY + [8:8] + read-only + + + DREQ_EN + If 1: assert DMA requests when FIFO contains data + [3:3] + read-write + + + ERR + If 1: conversion error bit appears in the FIFO alongside the result + [2:2] + read-write + + + SHIFT + If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. + [1:1] + read-write + + + EN + If 1: write result to the FIFO after each conversion. + [0:0] + read-write + + + + + FIFO + Conversion result FIFO + 0x000c + 0x00000000 + + + ERR + 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + [15:15] + read-only + + + VAL + [11:0] + read-only + + + + + DIV + Clock divider. If non-zero, CS_START_MANY will start conversions\n + at regular intervals rather than back-to-back.\n + The divider is reset when either of these fields are written.\n + Total period is 1 + INT + FRAC / 256 + 0x0010 + 0x00000000 + + + INT + Integer part of clock divisor. + [23:8] + read-write + + + FRAC + Fractional part of clock divisor. First-order delta-sigma. + [7:0] + read-write + + + + + INTR + Raw Interrupts + 0x0014 + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level.\n + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + INTE + Interrupt Enable + 0x0018 + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level.\n + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x001c + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level.\n + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x0020 + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level.\n + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + + + PWM + 1 + Simple PWM + 0x40050000 + 32 + + 0 + 0x1000 + registers + + + PWM_IRQ_WRAP + 4 + + + + CH0_CSR + Control and status register + 0x0000 + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + read-write + clear + + + PH_RET + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + read-write + clear + + + DIVMODE + [5:4] + read-write + + + div + Free-running counting at rate dictated by fractional divider + 0 + + + level + Fractional divider operation is gated by the PWM B pin. + 1 + + + rise + Counter advances with each rising edge of the PWM B pin. + 2 + + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH0_DIV + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + 0x0004 + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH0_CTR + Direct access to the PWM counter + 0x0008 + 0x00000000 + + + CH0_CTR + [15:0] + read-write + + + + + CH0_CC + Counter compare values + 0x000c + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH0_TOP + Counter wrap value + 0x0010 + 0x0000ffff + + + CH0_TOP + [15:0] + read-write + + + + + CH1_CSR + Control and status register + 0x0014 + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + read-write + clear + + + PH_RET + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + read-write + clear + + + DIVMODE + [5:4] + read-write + + + div + Free-running counting at rate dictated by fractional divider + 0 + + + level + Fractional divider operation is gated by the PWM B pin. + 1 + + + rise + Counter advances with each rising edge of the PWM B pin. + 2 + + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH1_DIV + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + 0x0018 + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH1_CTR + Direct access to the PWM counter + 0x001c + 0x00000000 + + + CH1_CTR + [15:0] + read-write + + + + + CH1_CC + Counter compare values + 0x0020 + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH1_TOP + Counter wrap value + 0x0024 + 0x0000ffff + + + CH1_TOP + [15:0] + read-write + + + + + CH2_CSR + Control and status register + 0x0028 + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + read-write + clear + + + PH_RET + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + read-write + clear + + + DIVMODE + [5:4] + read-write + + + div + Free-running counting at rate dictated by fractional divider + 0 + + + level + Fractional divider operation is gated by the PWM B pin. + 1 + + + rise + Counter advances with each rising edge of the PWM B pin. + 2 + + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH2_DIV + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + 0x002c + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH2_CTR + Direct access to the PWM counter + 0x0030 + 0x00000000 + + + CH2_CTR + [15:0] + read-write + + + + + CH2_CC + Counter compare values + 0x0034 + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH2_TOP + Counter wrap value + 0x0038 + 0x0000ffff + + + CH2_TOP + [15:0] + read-write + + + + + CH3_CSR + Control and status register + 0x003c + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + read-write + clear + + + PH_RET + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + read-write + clear + + + DIVMODE + [5:4] + read-write + + + div + Free-running counting at rate dictated by fractional divider + 0 + + + level + Fractional divider operation is gated by the PWM B pin. + 1 + + + rise + Counter advances with each rising edge of the PWM B pin. + 2 + + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH3_DIV + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + 0x0040 + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH3_CTR + Direct access to the PWM counter + 0x0044 + 0x00000000 + + + CH3_CTR + [15:0] + read-write + + + + + CH3_CC + Counter compare values + 0x0048 + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH3_TOP + Counter wrap value + 0x004c + 0x0000ffff + + + CH3_TOP + [15:0] + read-write + + + + + CH4_CSR + Control and status register + 0x0050 + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + read-write + clear + + + PH_RET + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + read-write + clear + + + DIVMODE + [5:4] + read-write + + + div + Free-running counting at rate dictated by fractional divider + 0 + + + level + Fractional divider operation is gated by the PWM B pin. + 1 + + + rise + Counter advances with each rising edge of the PWM B pin. + 2 + + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH4_DIV + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + 0x0054 + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH4_CTR + Direct access to the PWM counter + 0x0058 + 0x00000000 + + + CH4_CTR + [15:0] + read-write + + + + + CH4_CC + Counter compare values + 0x005c + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH4_TOP + Counter wrap value + 0x0060 + 0x0000ffff + + + CH4_TOP + [15:0] + read-write + + + + + CH5_CSR + Control and status register + 0x0064 + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + read-write + clear + + + PH_RET + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + read-write + clear + + + DIVMODE + [5:4] + read-write + + + div + Free-running counting at rate dictated by fractional divider + 0 + + + level + Fractional divider operation is gated by the PWM B pin. + 1 + + + rise + Counter advances with each rising edge of the PWM B pin. + 2 + + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH5_DIV + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + 0x0068 + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH5_CTR + Direct access to the PWM counter + 0x006c + 0x00000000 + + + CH5_CTR + [15:0] + read-write + + + + + CH5_CC + Counter compare values + 0x0070 + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH5_TOP + Counter wrap value + 0x0074 + 0x0000ffff + + + CH5_TOP + [15:0] + read-write + + + + + CH6_CSR + Control and status register + 0x0078 + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + read-write + clear + + + PH_RET + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + read-write + clear + + + DIVMODE + [5:4] + read-write + + + div + Free-running counting at rate dictated by fractional divider + 0 + + + level + Fractional divider operation is gated by the PWM B pin. + 1 + + + rise + Counter advances with each rising edge of the PWM B pin. + 2 + + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH6_DIV + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + 0x007c + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH6_CTR + Direct access to the PWM counter + 0x0080 + 0x00000000 + + + CH6_CTR + [15:0] + read-write + + + + + CH6_CC + Counter compare values + 0x0084 + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH6_TOP + Counter wrap value + 0x0088 + 0x0000ffff + + + CH6_TOP + [15:0] + read-write + + + + + CH7_CSR + Control and status register + 0x008c + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + read-write + clear + + + PH_RET + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + read-write + clear + + + DIVMODE + [5:4] + read-write + + + div + Free-running counting at rate dictated by fractional divider + 0 + + + level + Fractional divider operation is gated by the PWM B pin. + 1 + + + rise + Counter advances with each rising edge of the PWM B pin. + 2 + + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH7_DIV + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + 0x0090 + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH7_CTR + Direct access to the PWM counter + 0x0094 + 0x00000000 + + + CH7_CTR + [15:0] + read-write + + + + + CH7_CC + Counter compare values + 0x0098 + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH7_TOP + Counter wrap value + 0x009c + 0x0000ffff + + + CH7_TOP + [15:0] + read-write + + + + + EN + This register aliases the CSR_EN bits for all channels.\n + Writing to this register allows multiple channels to be enabled\n + or disabled simultaneously, so they can run in perfect sync.\n + For each channel, there is only one physical EN register bit,\n + which can be accessed through here or CHx_CSR. + 0x00a0 + 0x00000000 + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTR + Raw Interrupts + 0x00a4 + 0x00000000 + + + CH7 + [7:7] + read-write + oneToClear + + + CH6 + [6:6] + read-write + oneToClear + + + CH5 + [5:5] + read-write + oneToClear + + + CH4 + [4:4] + read-write + oneToClear + + + CH3 + [3:3] + read-write + oneToClear + + + CH2 + [2:2] + read-write + oneToClear + + + CH1 + [1:1] + read-write + oneToClear + + + CH0 + [0:0] + read-write + oneToClear + + + + + INTE + Interrupt Enable + 0x00a8 + 0x00000000 + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x00ac + 0x00000000 + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x00b0 + 0x00000000 + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + + + TIMER + 1 + Controls time and alarms\n + time is a 64 bit value indicating the time in usec since power-on\n + timeh is the top 32 bits of time & timel is the bottom 32 bits\n + to change time write to timelw before timehw\n + to read time read from timelr before timehr\n + An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n + When an alarm is pending, the corresponding alarm_running signal will be high\n + An alarm can be cancelled before it has finished by clearing the alarm_enable\n + When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n + To clear the interrupt write a 1 to the corresponding alarm_irq + 0x40054000 + 32 + + 0 + 0x1000 + registers + + + TIMER_IRQ_0 + 0 + + + TIMER_IRQ_1 + 1 + + + TIMER_IRQ_2 + 2 + + + TIMER_IRQ_3 + 3 + + + + TIMEHW + Write to bits 63:32 of time\n + always write timelw before timehw + 0x0000 + write-only + 0x00000000 + + + TIMELW + Write to bits 31:0 of time\n + writes do not get copied to time until timehw is written + 0x0004 + write-only + 0x00000000 + + + TIMEHR + Read from bits 63:32 of time\n + always read timelr before timehr + 0x0008 + read-only + 0x00000000 + + + TIMELR + Read from bits 31:0 of time + 0x000c + read-only + 0x00000000 + + + ALARM0 + Arm alarm 0, and configure the time it will fire.\n + Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n + The alarm will disarm itself once it fires, and can\n + be disarmed early using the ARMED status register. + 0x0010 + read-write + 0x00000000 + + + ALARM1 + Arm alarm 1, and configure the time it will fire.\n + Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n + The alarm will disarm itself once it fires, and can\n + be disarmed early using the ARMED status register. + 0x0014 + read-write + 0x00000000 + + + ALARM2 + Arm alarm 2, and configure the time it will fire.\n + Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n + The alarm will disarm itself once it fires, and can\n + be disarmed early using the ARMED status register. + 0x0018 + read-write + 0x00000000 + + + ALARM3 + Arm alarm 3, and configure the time it will fire.\n + Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n + The alarm will disarm itself once it fires, and can\n + be disarmed early using the ARMED status register. + 0x001c + read-write + 0x00000000 + + + ARMED + Indicates the armed/disarmed status of each alarm.\n + A write to the corresponding ALARMx register arms the alarm.\n + Alarms automatically disarm upon firing, but writing ones here\n + will disarm immediately without waiting to fire. + 0x0020 + 0x00000000 + + + ARMED + [3:0] + read-write + oneToClear + + + + + TIMERAWH + Raw read from bits 63:32 of time (no side effects) + 0x0024 + read-only + 0x00000000 + + + TIMERAWL + Raw read from bits 31:0 of time (no side effects) + 0x0028 + read-only + 0x00000000 + + + DBGPAUSE + Set bits high to enable pause when the corresponding debug ports are active + 0x002c + 0x00000007 + + + DBG1 + Pause when processor 1 is in debug mode + [2:2] + read-write + + + DBG0 + Pause when processor 0 is in debug mode + [1:1] + read-write + + + + + PAUSE + Set high to pause the timer + 0x0030 + 0x00000000 + + + PAUSE + [0:0] + read-write + + + + + INTR + Raw Interrupts + 0x0034 + 0x00000000 + + + ALARM_3 + [3:3] + read-write + oneToClear + + + ALARM_2 + [2:2] + read-write + oneToClear + + + ALARM_1 + [1:1] + read-write + oneToClear + + + ALARM_0 + [0:0] + read-write + oneToClear + + + + + INTE + Interrupt Enable + 0x0038 + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x003c + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x0040 + 0x00000000 + + + ALARM_3 + [3:3] + read-only + + + ALARM_2 + [2:2] + read-only + + + ALARM_1 + [1:1] + read-only + + + ALARM_0 + [0:0] + read-only + + + + + + + WATCHDOG + 1 + 0x40058000 + 32 + + 0 + 0x1000 + registers + + + + CTRL + Watchdog control\n + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n + The watchdog can be triggered in software. + 0x0000 + 0x07000000 + + + TRIGGER + Trigger a watchdog reset + [31:31] + read-write + clear + + + ENABLE + When not enabled the watchdog timer is paused + [30:30] + read-write + + + PAUSE_DBG1 + Pause the watchdog timer when processor 1 is in debug mode + [26:26] + read-write + + + PAUSE_DBG0 + Pause the watchdog timer when processor 0 is in debug mode + [25:25] + read-write + + + PAUSE_JTAG + Pause the watchdog timer when JTAG is accessing the bus fabric + [24:24] + read-write + + + TIME + Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered + [23:0] + read-only + + + + + LOAD + Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). + 0x0004 + 0x00000000 + + + LOAD + [23:0] + write-only + + + + + REASON + Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + 0x0008 + 0x00000000 + + + FORCE + [1:1] + read-only + + + TIMER + [0:0] + read-only + + + + + SCRATCH0 + Scratch register. Information persists through soft reset of the chip. + 0x000c + read-write + 0x00000000 + + + SCRATCH1 + Scratch register. Information persists through soft reset of the chip. + 0x0010 + read-write + 0x00000000 + + + SCRATCH2 + Scratch register. Information persists through soft reset of the chip. + 0x0014 + read-write + 0x00000000 + + + SCRATCH3 + Scratch register. Information persists through soft reset of the chip. + 0x0018 + read-write + 0x00000000 + + + SCRATCH4 + Scratch register. Information persists through soft reset of the chip. + 0x001c + read-write + 0x00000000 + + + SCRATCH5 + Scratch register. Information persists through soft reset of the chip. + 0x0020 + read-write + 0x00000000 + + + SCRATCH6 + Scratch register. Information persists through soft reset of the chip. + 0x0024 + read-write + 0x00000000 + + + SCRATCH7 + Scratch register. Information persists through soft reset of the chip. + 0x0028 + read-write + 0x00000000 + + + TICK + Controls the tick generator + 0x002c + 0x00000200 + + + COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [19:11] + read-only + + + RUNNING + Is the tick generator running? + [10:10] + read-only + + + ENABLE + start / stop tick generation + [9:9] + read-write + + + CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + + + RTC + 1 + Register block to control RTC + 0x4005c000 + 32 + + 0 + 0x1000 + registers + + + RTC_IRQ + 25 + + + + CLKDIV_M1 + Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. + 0x0000 + 0x00000000 + + + CLKDIV_M1 + [15:0] + read-write + + + + + SETUP_0 + RTC setup register 0 + 0x0004 + 0x00000000 + + + YEAR + Year + [23:12] + read-write + + + MONTH + Month (1..12) + [11:8] + read-write + + + DAY + Day of the month (1..31) + [4:0] + read-write + + + + + SETUP_1 + RTC setup register 1 + 0x0008 + 0x00000000 + + + DOTW + Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 + [26:24] + read-write + + + HOUR + Hours + [20:16] + read-write + + + MIN + Minutes + [13:8] + read-write + + + SEC + Seconds + [5:0] + read-write + + + + + CTRL + RTC Control and status + 0x000c + 0x00000000 + + + FORCE_NOTLEAPYEAR + If set, leapyear is forced off.\n + Useful for years divisible by 100 but not by 400 + [8:8] + read-write + + + LOAD + Load RTC + [4:4] + read-write + clear + + + RTC_ACTIVE + RTC enabled (running) + [1:1] + read-only + + + RTC_ENABLE + Enable RTC + [0:0] + read-write + + + + + IRQ_SETUP_0 + Interrupt setup register 0 + 0x0010 + 0x00000000 + + + MATCH_ACTIVE + [29:29] + read-only + + + MATCH_ENA + Global match enable. Don't change any other value while this one is enabled + [28:28] + read-write + + + YEAR_ENA + Enable year matching + [26:26] + read-write + + + MONTH_ENA + Enable month matching + [25:25] + read-write + + + DAY_ENA + Enable day matching + [24:24] + read-write + + + YEAR + Year + [23:12] + read-write + + + MONTH + Month (1..12) + [11:8] + read-write + + + DAY + Day of the month (1..31) + [4:0] + read-write + + + + + IRQ_SETUP_1 + Interrupt setup register 1 + 0x0014 + 0x00000000 + + + DOTW_ENA + Enable day of the week matching + [31:31] + read-write + + + HOUR_ENA + Enable hour matching + [30:30] + read-write + + + MIN_ENA + Enable minute matching + [29:29] + read-write + + + SEC_ENA + Enable second matching + [28:28] + read-write + + + DOTW + Day of the week + [26:24] + read-write + + + HOUR + Hours + [20:16] + read-write + + + MIN + Minutes + [13:8] + read-write + + + SEC + Seconds + [5:0] + read-write + + + + + RTC_1 + RTC register 1. + 0x0018 + 0x00000000 + + + YEAR + Year + [23:12] + read-only + + + MONTH + Month (1..12) + [11:8] + read-only + + + DAY + Day of the month (1..31) + [4:0] + read-only + + + + + RTC_0 + RTC register 0\n + Read this before RTC 1! + 0x001c + 0x00000000 + + + DOTW + Day of the week + [26:24] + read-only + + + HOUR + Hours + [20:16] + read-only + + + MIN + Minutes + [13:8] + read-only + + + SEC + Seconds + [5:0] + read-only + + + + + INTR + Raw Interrupts + 0x0020 + 0x00000000 + + + RTC + [0:0] + read-only + + + + + INTE + Interrupt Enable + 0x0024 + 0x00000000 + + + RTC + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x0028 + 0x00000000 + + + RTC + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x002c + 0x00000000 + + + RTC + [0:0] + read-only + + + + + + + ROSC + 1 + 0x40060000 + 32 + + 0 + 0x1000 + registers + + + + CTRL + Ring Oscillator control + 0x0000 + 0x00000aa0 + + + ENABLE + On power-up this field is initialised to ENABLE\n + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Controls the number of delay stages in the ROSC ring\n + LOW uses stages 0 to 7\n + MEDIUM uses stages 0 to 5\n + HIGH uses stages 0 to 3\n + TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n + The clock output will not glitch when changing the range up one step at a time\n + The clock output will glitch when changing the range down\n + Note: the values here are gray coded which is why HIGH comes before TOOHIGH + [11:0] + read-write + + + LOW + 4004 + + + MEDIUM + 4005 + + + HIGH + 4007 + + + TOOHIGH + 4006 + + + + + + + FREQA + The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage\n + The drive strength has 4 levels determined by the number of bits set\n + Increasing the number of bits set increases the drive strength and increases the oscillation frequency\n + 0 bits set is the default drive strength\n + 1 bit set doubles the drive strength\n + 2 bits set triples drive strength\n + 3 bits set quadruples drive strength + 0x0004 + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings\n + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS3 + Stage 3 drive strength + [14:12] + read-write + + + DS2 + Stage 2 drive strength + [10:8] + read-write + + + DS1 + Stage 1 drive strength + [6:4] + read-write + + + DS0 + Stage 0 drive strength + [2:0] + read-write + + + + + FREQB + For a detailed description see freqa register + 0x0008 + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings\n + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS7 + Stage 7 drive strength + [14:12] + read-write + + + DS6 + Stage 6 drive strength + [10:8] + read-write + + + DS5 + Stage 5 drive strength + [6:4] + read-write + + + DS4 + Stage 4 drive strength + [2:0] + read-write + + + + + DORMANT + Ring Oscillator pause control\n + This is used to save power by pausing the ROSC\n + On power-up this field is initialised to WAKE\n + An invalid write will also select WAKE\n + Warning: setup the irq before selecting dormant mode + 0x000c + read-write + 0x00000000 + + + DIV + Controls the output divider + 0x0010 + 0x00000000 + + + DIV + set to 0xaa0 + div where\n + div = 0 divides by 32\n + div = 1-31 divides by div\n + any other value sets div=31\n + this register resets to div=16 + [11:0] + read-write + + + PASS + 2720 + + + + + + + PHASE + Controls the phase shifted output + 0x0014 + 0x00000008 + + + PASSWD + set to 0xaa\n + any other value enables the output with shift=0 + [11:4] + read-write + + + ENABLE + enable the phase-shifted output\n + this can be changed on-the-fly + [3:3] + read-write + + + FLIP + invert the phase-shifted output\n + this is ignored when div=1 + [2:2] + read-write + + + SHIFT + phase shift the phase-shifted output by SHIFT input clocks\n + this can be changed on-the-fly\n + must be set to 0 before setting div=1 + [1:0] + read-write + + + + + STATUS + Ring Oscillator Status + 0x0018 + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT + [24:24] + read-write + oneToClear + + + DIV_RUNNING + post-divider is running\n + this resets to 0 but transitions to 1 during chip startup + [16:16] + read-only + + + ENABLED + Oscillator is enabled but not necessarily running and stable\n + this resets to 0 but transitions to 1 during chip startup + [12:12] + read-only + + + + + RANDOMBIT + This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + 0x001c + 0x00000001 + + + RANDOMBIT + [0:0] + read-only + + + + + COUNT + A down counter running at the ROSC frequency which counts to zero and stops.\n + To start the counter write a non-zero value.\n + Can be used for short software pauses when setting up time sensitive hardware. + 0x0020 + 0x00000000 + + + COUNT + [7:0] + read-write + + + + + + + VREG_AND_CHIP_RESET + 1 + control and status for on-chip voltage regulator and chip level reset subsystem + 0x40064000 + 32 + + 0 + 0x1000 + registers + + + + VREG + Voltage regulator control and status + 0x0000 + 0x000000b1 + + + ROK + regulation status\n + 0=not in regulation, 1=in regulation + [12:12] + read-only + + + VSEL + output voltage select\n + 0000 to 0101 - 0.80V\n + 0110 - 0.85V\n + 0111 - 0.90V\n + 1000 - 0.95V\n + 1001 - 1.00V\n + 1010 - 1.05V\n + 1011 - 1.10V (default)\n + 1100 - 1.15V\n + 1101 - 1.20V\n + 1110 - 1.25V\n + 1111 - 1.30V + [7:4] + read-write + + + HIZ + high impedance mode select\n + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + EN + enable\n + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD + brown-out detection control + 0x0004 + 0x00000091 + + + VSEL + threshold select\n + 0000 - 0.473V\n + 0001 - 0.516V\n + 0010 - 0.559V\n + 0011 - 0.602V\n + 0100 - 0.645V\n + 0101 - 0.688V\n + 0110 - 0.731V\n + 0111 - 0.774V\n + 1000 - 0.817V\n + 1001 - 0.860V (default)\n + 1010 - 0.903V\n + 1011 - 0.946V\n + 1100 - 0.989V\n + 1101 - 1.032V\n + 1110 - 1.075V\n + 1111 - 1.118V + [7:4] + read-write + + + EN + enable\n + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + CHIP_RESET + Chip reset control and status + 0x0008 + 0x00000000 + + + PSM_RESTART_FLAG + This is set by psm_restart from the debugger.\n + Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n + In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. + [24:24] + read-write + oneToClear + + + HAD_PSM_RESTART + Last reset was from the debug port + [20:20] + read-only + + + HAD_RUN + Last reset was from the RUN pin + [16:16] + read-only + + + HAD_POR + Last reset was from the power-on reset or brown-out detection blocks + [8:8] + read-only + + + + + + + TBMAN + 1 + Testbench manager. Allows the programmer to know what platform their software is running on. + 0x4006c000 + 32 + + 0 + 0x1000 + registers + + + + PLATFORM + Indicates the type of platform in use + 0x0000 + 0x00000005 + + + FPGA + Indicates the platform is an FPGA + [1:1] + read-only + + + ASIC + Indicates the platform is an ASIC + [0:0] + read-only + + + + + + + DMA + 1 + DMA with separate read and write masters + 0x50000000 + 32 + + 0 + 0x1000 + registers + + + DMA_IRQ_0 + 11 + + + DMA_IRQ_1 + 12 + + + + CH0_READ_ADDR + DMA Channel 0 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x0000 + read-write + 0x00000000 + + + CH0_WRITE_ADDR + DMA Channel 0 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x0004 + read-write + 0x00000000 + + + CH0_TRANS_COUNT + DMA Channel 0 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x0008 + read-write + 0x00000000 + + + CH0_CTRL_TRIG + DMA Channel 0 Control and Status + 0x000c + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH0_AL1_CTRL + Alias for channel 0 CTRL register + 0x0010 + read-write + 0x00000000 + + + CH0_AL1_READ_ADDR + Alias for channel 0 READ_ADDR register + 0x0014 + read-write + 0x00000000 + + + CH0_AL1_WRITE_ADDR + Alias for channel 0 WRITE_ADDR register + 0x0018 + read-write + 0x00000000 + + + CH0_AL1_TRANS_COUNT_TRIG + Alias for channel 0 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x001c + read-write + 0x00000000 + + + CH0_AL2_CTRL + Alias for channel 0 CTRL register + 0x0020 + read-write + 0x00000000 + + + CH0_AL2_TRANS_COUNT + Alias for channel 0 TRANS_COUNT register + 0x0024 + read-write + 0x00000000 + + + CH0_AL2_READ_ADDR + Alias for channel 0 READ_ADDR register + 0x0028 + read-write + 0x00000000 + + + CH0_AL2_WRITE_ADDR_TRIG + Alias for channel 0 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x002c + read-write + 0x00000000 + + + CH0_AL3_CTRL + Alias for channel 0 CTRL register + 0x0030 + read-write + 0x00000000 + + + CH0_AL3_WRITE_ADDR + Alias for channel 0 WRITE_ADDR register + 0x0034 + read-write + 0x00000000 + + + CH0_AL3_TRANS_COUNT + Alias for channel 0 TRANS_COUNT register + 0x0038 + read-write + 0x00000000 + + + CH0_AL3_READ_ADDR_TRIG + Alias for channel 0 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x003c + read-write + 0x00000000 + + + CH1_READ_ADDR + DMA Channel 1 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x0040 + read-write + 0x00000000 + + + CH1_WRITE_ADDR + DMA Channel 1 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x0044 + read-write + 0x00000000 + + + CH1_TRANS_COUNT + DMA Channel 1 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x0048 + read-write + 0x00000000 + + + CH1_CTRL_TRIG + DMA Channel 1 Control and Status + 0x004c + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH1_AL1_CTRL + Alias for channel 1 CTRL register + 0x0050 + read-write + 0x00000000 + + + CH1_AL1_READ_ADDR + Alias for channel 1 READ_ADDR register + 0x0054 + read-write + 0x00000000 + + + CH1_AL1_WRITE_ADDR + Alias for channel 1 WRITE_ADDR register + 0x0058 + read-write + 0x00000000 + + + CH1_AL1_TRANS_COUNT_TRIG + Alias for channel 1 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x005c + read-write + 0x00000000 + + + CH1_AL2_CTRL + Alias for channel 1 CTRL register + 0x0060 + read-write + 0x00000000 + + + CH1_AL2_TRANS_COUNT + Alias for channel 1 TRANS_COUNT register + 0x0064 + read-write + 0x00000000 + + + CH1_AL2_READ_ADDR + Alias for channel 1 READ_ADDR register + 0x0068 + read-write + 0x00000000 + + + CH1_AL2_WRITE_ADDR_TRIG + Alias for channel 1 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x006c + read-write + 0x00000000 + + + CH1_AL3_CTRL + Alias for channel 1 CTRL register + 0x0070 + read-write + 0x00000000 + + + CH1_AL3_WRITE_ADDR + Alias for channel 1 WRITE_ADDR register + 0x0074 + read-write + 0x00000000 + + + CH1_AL3_TRANS_COUNT + Alias for channel 1 TRANS_COUNT register + 0x0078 + read-write + 0x00000000 + + + CH1_AL3_READ_ADDR_TRIG + Alias for channel 1 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x007c + read-write + 0x00000000 + + + CH2_READ_ADDR + DMA Channel 2 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x0080 + read-write + 0x00000000 + + + CH2_WRITE_ADDR + DMA Channel 2 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x0084 + read-write + 0x00000000 + + + CH2_TRANS_COUNT + DMA Channel 2 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x0088 + read-write + 0x00000000 + + + CH2_CTRL_TRIG + DMA Channel 2 Control and Status + 0x008c + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH2_AL1_CTRL + Alias for channel 2 CTRL register + 0x0090 + read-write + 0x00000000 + + + CH2_AL1_READ_ADDR + Alias for channel 2 READ_ADDR register + 0x0094 + read-write + 0x00000000 + + + CH2_AL1_WRITE_ADDR + Alias for channel 2 WRITE_ADDR register + 0x0098 + read-write + 0x00000000 + + + CH2_AL1_TRANS_COUNT_TRIG + Alias for channel 2 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x009c + read-write + 0x00000000 + + + CH2_AL2_CTRL + Alias for channel 2 CTRL register + 0x00a0 + read-write + 0x00000000 + + + CH2_AL2_TRANS_COUNT + Alias for channel 2 TRANS_COUNT register + 0x00a4 + read-write + 0x00000000 + + + CH2_AL2_READ_ADDR + Alias for channel 2 READ_ADDR register + 0x00a8 + read-write + 0x00000000 + + + CH2_AL2_WRITE_ADDR_TRIG + Alias for channel 2 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x00ac + read-write + 0x00000000 + + + CH2_AL3_CTRL + Alias for channel 2 CTRL register + 0x00b0 + read-write + 0x00000000 + + + CH2_AL3_WRITE_ADDR + Alias for channel 2 WRITE_ADDR register + 0x00b4 + read-write + 0x00000000 + + + CH2_AL3_TRANS_COUNT + Alias for channel 2 TRANS_COUNT register + 0x00b8 + read-write + 0x00000000 + + + CH2_AL3_READ_ADDR_TRIG + Alias for channel 2 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x00bc + read-write + 0x00000000 + + + CH3_READ_ADDR + DMA Channel 3 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x00c0 + read-write + 0x00000000 + + + CH3_WRITE_ADDR + DMA Channel 3 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x00c4 + read-write + 0x00000000 + + + CH3_TRANS_COUNT + DMA Channel 3 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x00c8 + read-write + 0x00000000 + + + CH3_CTRL_TRIG + DMA Channel 3 Control and Status + 0x00cc + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH3_AL1_CTRL + Alias for channel 3 CTRL register + 0x00d0 + read-write + 0x00000000 + + + CH3_AL1_READ_ADDR + Alias for channel 3 READ_ADDR register + 0x00d4 + read-write + 0x00000000 + + + CH3_AL1_WRITE_ADDR + Alias for channel 3 WRITE_ADDR register + 0x00d8 + read-write + 0x00000000 + + + CH3_AL1_TRANS_COUNT_TRIG + Alias for channel 3 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x00dc + read-write + 0x00000000 + + + CH3_AL2_CTRL + Alias for channel 3 CTRL register + 0x00e0 + read-write + 0x00000000 + + + CH3_AL2_TRANS_COUNT + Alias for channel 3 TRANS_COUNT register + 0x00e4 + read-write + 0x00000000 + + + CH3_AL2_READ_ADDR + Alias for channel 3 READ_ADDR register + 0x00e8 + read-write + 0x00000000 + + + CH3_AL2_WRITE_ADDR_TRIG + Alias for channel 3 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x00ec + read-write + 0x00000000 + + + CH3_AL3_CTRL + Alias for channel 3 CTRL register + 0x00f0 + read-write + 0x00000000 + + + CH3_AL3_WRITE_ADDR + Alias for channel 3 WRITE_ADDR register + 0x00f4 + read-write + 0x00000000 + + + CH3_AL3_TRANS_COUNT + Alias for channel 3 TRANS_COUNT register + 0x00f8 + read-write + 0x00000000 + + + CH3_AL3_READ_ADDR_TRIG + Alias for channel 3 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x00fc + read-write + 0x00000000 + + + CH4_READ_ADDR + DMA Channel 4 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x0100 + read-write + 0x00000000 + + + CH4_WRITE_ADDR + DMA Channel 4 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x0104 + read-write + 0x00000000 + + + CH4_TRANS_COUNT + DMA Channel 4 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x0108 + read-write + 0x00000000 + + + CH4_CTRL_TRIG + DMA Channel 4 Control and Status + 0x010c + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH4_AL1_CTRL + Alias for channel 4 CTRL register + 0x0110 + read-write + 0x00000000 + + + CH4_AL1_READ_ADDR + Alias for channel 4 READ_ADDR register + 0x0114 + read-write + 0x00000000 + + + CH4_AL1_WRITE_ADDR + Alias for channel 4 WRITE_ADDR register + 0x0118 + read-write + 0x00000000 + + + CH4_AL1_TRANS_COUNT_TRIG + Alias for channel 4 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x011c + read-write + 0x00000000 + + + CH4_AL2_CTRL + Alias for channel 4 CTRL register + 0x0120 + read-write + 0x00000000 + + + CH4_AL2_TRANS_COUNT + Alias for channel 4 TRANS_COUNT register + 0x0124 + read-write + 0x00000000 + + + CH4_AL2_READ_ADDR + Alias for channel 4 READ_ADDR register + 0x0128 + read-write + 0x00000000 + + + CH4_AL2_WRITE_ADDR_TRIG + Alias for channel 4 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x012c + read-write + 0x00000000 + + + CH4_AL3_CTRL + Alias for channel 4 CTRL register + 0x0130 + read-write + 0x00000000 + + + CH4_AL3_WRITE_ADDR + Alias for channel 4 WRITE_ADDR register + 0x0134 + read-write + 0x00000000 + + + CH4_AL3_TRANS_COUNT + Alias for channel 4 TRANS_COUNT register + 0x0138 + read-write + 0x00000000 + + + CH4_AL3_READ_ADDR_TRIG + Alias for channel 4 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x013c + read-write + 0x00000000 + + + CH5_READ_ADDR + DMA Channel 5 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x0140 + read-write + 0x00000000 + + + CH5_WRITE_ADDR + DMA Channel 5 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x0144 + read-write + 0x00000000 + + + CH5_TRANS_COUNT + DMA Channel 5 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x0148 + read-write + 0x00000000 + + + CH5_CTRL_TRIG + DMA Channel 5 Control and Status + 0x014c + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH5_AL1_CTRL + Alias for channel 5 CTRL register + 0x0150 + read-write + 0x00000000 + + + CH5_AL1_READ_ADDR + Alias for channel 5 READ_ADDR register + 0x0154 + read-write + 0x00000000 + + + CH5_AL1_WRITE_ADDR + Alias for channel 5 WRITE_ADDR register + 0x0158 + read-write + 0x00000000 + + + CH5_AL1_TRANS_COUNT_TRIG + Alias for channel 5 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x015c + read-write + 0x00000000 + + + CH5_AL2_CTRL + Alias for channel 5 CTRL register + 0x0160 + read-write + 0x00000000 + + + CH5_AL2_TRANS_COUNT + Alias for channel 5 TRANS_COUNT register + 0x0164 + read-write + 0x00000000 + + + CH5_AL2_READ_ADDR + Alias for channel 5 READ_ADDR register + 0x0168 + read-write + 0x00000000 + + + CH5_AL2_WRITE_ADDR_TRIG + Alias for channel 5 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x016c + read-write + 0x00000000 + + + CH5_AL3_CTRL + Alias for channel 5 CTRL register + 0x0170 + read-write + 0x00000000 + + + CH5_AL3_WRITE_ADDR + Alias for channel 5 WRITE_ADDR register + 0x0174 + read-write + 0x00000000 + + + CH5_AL3_TRANS_COUNT + Alias for channel 5 TRANS_COUNT register + 0x0178 + read-write + 0x00000000 + + + CH5_AL3_READ_ADDR_TRIG + Alias for channel 5 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x017c + read-write + 0x00000000 + + + CH6_READ_ADDR + DMA Channel 6 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x0180 + read-write + 0x00000000 + + + CH6_WRITE_ADDR + DMA Channel 6 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x0184 + read-write + 0x00000000 + + + CH6_TRANS_COUNT + DMA Channel 6 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x0188 + read-write + 0x00000000 + + + CH6_CTRL_TRIG + DMA Channel 6 Control and Status + 0x018c + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH6_AL1_CTRL + Alias for channel 6 CTRL register + 0x0190 + read-write + 0x00000000 + + + CH6_AL1_READ_ADDR + Alias for channel 6 READ_ADDR register + 0x0194 + read-write + 0x00000000 + + + CH6_AL1_WRITE_ADDR + Alias for channel 6 WRITE_ADDR register + 0x0198 + read-write + 0x00000000 + + + CH6_AL1_TRANS_COUNT_TRIG + Alias for channel 6 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x019c + read-write + 0x00000000 + + + CH6_AL2_CTRL + Alias for channel 6 CTRL register + 0x01a0 + read-write + 0x00000000 + + + CH6_AL2_TRANS_COUNT + Alias for channel 6 TRANS_COUNT register + 0x01a4 + read-write + 0x00000000 + + + CH6_AL2_READ_ADDR + Alias for channel 6 READ_ADDR register + 0x01a8 + read-write + 0x00000000 + + + CH6_AL2_WRITE_ADDR_TRIG + Alias for channel 6 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x01ac + read-write + 0x00000000 + + + CH6_AL3_CTRL + Alias for channel 6 CTRL register + 0x01b0 + read-write + 0x00000000 + + + CH6_AL3_WRITE_ADDR + Alias for channel 6 WRITE_ADDR register + 0x01b4 + read-write + 0x00000000 + + + CH6_AL3_TRANS_COUNT + Alias for channel 6 TRANS_COUNT register + 0x01b8 + read-write + 0x00000000 + + + CH6_AL3_READ_ADDR_TRIG + Alias for channel 6 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x01bc + read-write + 0x00000000 + + + CH7_READ_ADDR + DMA Channel 7 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x01c0 + read-write + 0x00000000 + + + CH7_WRITE_ADDR + DMA Channel 7 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x01c4 + read-write + 0x00000000 + + + CH7_TRANS_COUNT + DMA Channel 7 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x01c8 + read-write + 0x00000000 + + + CH7_CTRL_TRIG + DMA Channel 7 Control and Status + 0x01cc + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH7_AL1_CTRL + Alias for channel 7 CTRL register + 0x01d0 + read-write + 0x00000000 + + + CH7_AL1_READ_ADDR + Alias for channel 7 READ_ADDR register + 0x01d4 + read-write + 0x00000000 + + + CH7_AL1_WRITE_ADDR + Alias for channel 7 WRITE_ADDR register + 0x01d8 + read-write + 0x00000000 + + + CH7_AL1_TRANS_COUNT_TRIG + Alias for channel 7 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x01dc + read-write + 0x00000000 + + + CH7_AL2_CTRL + Alias for channel 7 CTRL register + 0x01e0 + read-write + 0x00000000 + + + CH7_AL2_TRANS_COUNT + Alias for channel 7 TRANS_COUNT register + 0x01e4 + read-write + 0x00000000 + + + CH7_AL2_READ_ADDR + Alias for channel 7 READ_ADDR register + 0x01e8 + read-write + 0x00000000 + + + CH7_AL2_WRITE_ADDR_TRIG + Alias for channel 7 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x01ec + read-write + 0x00000000 + + + CH7_AL3_CTRL + Alias for channel 7 CTRL register + 0x01f0 + read-write + 0x00000000 + + + CH7_AL3_WRITE_ADDR + Alias for channel 7 WRITE_ADDR register + 0x01f4 + read-write + 0x00000000 + + + CH7_AL3_TRANS_COUNT + Alias for channel 7 TRANS_COUNT register + 0x01f8 + read-write + 0x00000000 + + + CH7_AL3_READ_ADDR_TRIG + Alias for channel 7 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x01fc + read-write + 0x00000000 + + + CH8_READ_ADDR + DMA Channel 8 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x0200 + read-write + 0x00000000 + + + CH8_WRITE_ADDR + DMA Channel 8 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x0204 + read-write + 0x00000000 + + + CH8_TRANS_COUNT + DMA Channel 8 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x0208 + read-write + 0x00000000 + + + CH8_CTRL_TRIG + DMA Channel 8 Control and Status + 0x020c + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH8_AL1_CTRL + Alias for channel 8 CTRL register + 0x0210 + read-write + 0x00000000 + + + CH8_AL1_READ_ADDR + Alias for channel 8 READ_ADDR register + 0x0214 + read-write + 0x00000000 + + + CH8_AL1_WRITE_ADDR + Alias for channel 8 WRITE_ADDR register + 0x0218 + read-write + 0x00000000 + + + CH8_AL1_TRANS_COUNT_TRIG + Alias for channel 8 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x021c + read-write + 0x00000000 + + + CH8_AL2_CTRL + Alias for channel 8 CTRL register + 0x0220 + read-write + 0x00000000 + + + CH8_AL2_TRANS_COUNT + Alias for channel 8 TRANS_COUNT register + 0x0224 + read-write + 0x00000000 + + + CH8_AL2_READ_ADDR + Alias for channel 8 READ_ADDR register + 0x0228 + read-write + 0x00000000 + + + CH8_AL2_WRITE_ADDR_TRIG + Alias for channel 8 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x022c + read-write + 0x00000000 + + + CH8_AL3_CTRL + Alias for channel 8 CTRL register + 0x0230 + read-write + 0x00000000 + + + CH8_AL3_WRITE_ADDR + Alias for channel 8 WRITE_ADDR register + 0x0234 + read-write + 0x00000000 + + + CH8_AL3_TRANS_COUNT + Alias for channel 8 TRANS_COUNT register + 0x0238 + read-write + 0x00000000 + + + CH8_AL3_READ_ADDR_TRIG + Alias for channel 8 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x023c + read-write + 0x00000000 + + + CH9_READ_ADDR + DMA Channel 9 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x0240 + read-write + 0x00000000 + + + CH9_WRITE_ADDR + DMA Channel 9 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x0244 + read-write + 0x00000000 + + + CH9_TRANS_COUNT + DMA Channel 9 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x0248 + read-write + 0x00000000 + + + CH9_CTRL_TRIG + DMA Channel 9 Control and Status + 0x024c + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH9_AL1_CTRL + Alias for channel 9 CTRL register + 0x0250 + read-write + 0x00000000 + + + CH9_AL1_READ_ADDR + Alias for channel 9 READ_ADDR register + 0x0254 + read-write + 0x00000000 + + + CH9_AL1_WRITE_ADDR + Alias for channel 9 WRITE_ADDR register + 0x0258 + read-write + 0x00000000 + + + CH9_AL1_TRANS_COUNT_TRIG + Alias for channel 9 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x025c + read-write + 0x00000000 + + + CH9_AL2_CTRL + Alias for channel 9 CTRL register + 0x0260 + read-write + 0x00000000 + + + CH9_AL2_TRANS_COUNT + Alias for channel 9 TRANS_COUNT register + 0x0264 + read-write + 0x00000000 + + + CH9_AL2_READ_ADDR + Alias for channel 9 READ_ADDR register + 0x0268 + read-write + 0x00000000 + + + CH9_AL2_WRITE_ADDR_TRIG + Alias for channel 9 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x026c + read-write + 0x00000000 + + + CH9_AL3_CTRL + Alias for channel 9 CTRL register + 0x0270 + read-write + 0x00000000 + + + CH9_AL3_WRITE_ADDR + Alias for channel 9 WRITE_ADDR register + 0x0274 + read-write + 0x00000000 + + + CH9_AL3_TRANS_COUNT + Alias for channel 9 TRANS_COUNT register + 0x0278 + read-write + 0x00000000 + + + CH9_AL3_READ_ADDR_TRIG + Alias for channel 9 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x027c + read-write + 0x00000000 + + + CH10_READ_ADDR + DMA Channel 10 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x0280 + read-write + 0x00000000 + + + CH10_WRITE_ADDR + DMA Channel 10 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x0284 + read-write + 0x00000000 + + + CH10_TRANS_COUNT + DMA Channel 10 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x0288 + read-write + 0x00000000 + + + CH10_CTRL_TRIG + DMA Channel 10 Control and Status + 0x028c + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH10_AL1_CTRL + Alias for channel 10 CTRL register + 0x0290 + read-write + 0x00000000 + + + CH10_AL1_READ_ADDR + Alias for channel 10 READ_ADDR register + 0x0294 + read-write + 0x00000000 + + + CH10_AL1_WRITE_ADDR + Alias for channel 10 WRITE_ADDR register + 0x0298 + read-write + 0x00000000 + + + CH10_AL1_TRANS_COUNT_TRIG + Alias for channel 10 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x029c + read-write + 0x00000000 + + + CH10_AL2_CTRL + Alias for channel 10 CTRL register + 0x02a0 + read-write + 0x00000000 + + + CH10_AL2_TRANS_COUNT + Alias for channel 10 TRANS_COUNT register + 0x02a4 + read-write + 0x00000000 + + + CH10_AL2_READ_ADDR + Alias for channel 10 READ_ADDR register + 0x02a8 + read-write + 0x00000000 + + + CH10_AL2_WRITE_ADDR_TRIG + Alias for channel 10 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x02ac + read-write + 0x00000000 + + + CH10_AL3_CTRL + Alias for channel 10 CTRL register + 0x02b0 + read-write + 0x00000000 + + + CH10_AL3_WRITE_ADDR + Alias for channel 10 WRITE_ADDR register + 0x02b4 + read-write + 0x00000000 + + + CH10_AL3_TRANS_COUNT + Alias for channel 10 TRANS_COUNT register + 0x02b8 + read-write + 0x00000000 + + + CH10_AL3_READ_ADDR_TRIG + Alias for channel 10 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x02bc + read-write + 0x00000000 + + + CH11_READ_ADDR + DMA Channel 11 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + 0x02c0 + read-write + 0x00000000 + + + CH11_WRITE_ADDR + DMA Channel 11 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + 0x02c4 + read-write + 0x00000000 + + + CH11_TRANS_COUNT + DMA Channel 11 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + 0x02c8 + read-write + 0x00000000 + + + CH11_CTRL_TRIG + DMA Channel 11 Control and Status + 0x02cc + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH11_AL1_CTRL + Alias for channel 11 CTRL register + 0x02d0 + read-write + 0x00000000 + + + CH11_AL1_READ_ADDR + Alias for channel 11 READ_ADDR register + 0x02d4 + read-write + 0x00000000 + + + CH11_AL1_WRITE_ADDR + Alias for channel 11 WRITE_ADDR register + 0x02d8 + read-write + 0x00000000 + + + CH11_AL1_TRANS_COUNT_TRIG + Alias for channel 11 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x02dc + read-write + 0x00000000 + + + CH11_AL2_CTRL + Alias for channel 11 CTRL register + 0x02e0 + read-write + 0x00000000 + + + CH11_AL2_TRANS_COUNT + Alias for channel 11 TRANS_COUNT register + 0x02e4 + read-write + 0x00000000 + + + CH11_AL2_READ_ADDR + Alias for channel 11 READ_ADDR register + 0x02e8 + read-write + 0x00000000 + + + CH11_AL2_WRITE_ADDR_TRIG + Alias for channel 11 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x02ec + read-write + 0x00000000 + + + CH11_AL3_CTRL + Alias for channel 11 CTRL register + 0x02f0 + read-write + 0x00000000 + + + CH11_AL3_WRITE_ADDR + Alias for channel 11 WRITE_ADDR register + 0x02f4 + read-write + 0x00000000 + + + CH11_AL3_TRANS_COUNT + Alias for channel 11 TRANS_COUNT register + 0x02f8 + read-write + 0x00000000 + + + CH11_AL3_READ_ADDR_TRIG + Alias for channel 11 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + 0x02fc + read-write + 0x00000000 + + + INTR + Interrupt Status (raw) + 0x0400 + 0x00000000 + + + INTR + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n + Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n + This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n + It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. + [15:0] + read-write + oneToClear + + + + + INTE0 + Interrupt Enables for IRQ 0 + 0x0404 + 0x00000000 + + + INTE0 + Set bit n to pass interrupts from channel n to DMA IRQ 0. + [15:0] + read-write + + + + + INTF0 + Force Interrupts + 0x0408 + 0x00000000 + + + INTF0 + Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS0 + Interrupt Status for IRQ 0 + 0x040c + 0x00000000 + + + INTS0 + Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n + Channel interrupts can be cleared by writing a bit mask here. + [15:0] + read-write + oneToClear + + + + + INTE1 + Interrupt Enables for IRQ 1 + 0x0414 + 0x00000000 + + + INTE1 + Set bit n to pass interrupts from channel n to DMA IRQ 1. + [15:0] + read-write + + + + + INTF1 + Force Interrupts for IRQ 1 + 0x0418 + 0x00000000 + + + INTF1 + Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS1 + Interrupt Status (masked) for IRQ 1 + 0x041c + 0x00000000 + + + INTS1 + Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n + Channel interrupts can be cleared by writing a bit mask here. + [15:0] + read-write + oneToClear + + + + + TIMER0 + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x0420 + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER1 + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x0424 + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER2 + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x0428 + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER3 + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x042c + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + MULTI_CHAN_TRIGGER + Trigger one or more channels simultaneously + 0x0430 + 0x00000000 + + + MULTI_CHAN_TRIGGER + Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. + [15:0] + read-write + clear + + + + + SNIFF_CTRL + Sniffer Control + 0x0434 + 0x00000000 + + + OUT_INV + If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [11:11] + read-write + + + OUT_REV + If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [10:10] + read-write + + + BSWAP + Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + [9:9] + read-write + + + CALC + [8:5] + read-write + + + CRC32 + Calculate a CRC-32 (IEEE802.3 polynomial) + 0 + + + CRC32R + Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + 1 + + + CRC16 + Calculate a CRC-16-CCITT + 2 + + + CRC16R + Calculate a CRC-16-CCITT with bit reversed data + 3 + + + EVEN + XOR reduction over all data. == 1 if the total 1 population count is odd. + 14 + + + SUM + Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + 15 + + + + + DMACH + DMA channel for Sniffer to observe + [4:1] + read-write + + + EN + Enable sniffer + [0:0] + read-write + + + + + SNIFF_DATA + Data accumulator for sniff hardware\n + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + 0x0438 + read-write + 0x00000000 + + + FIFO_LEVELS + Debug RAF, WAF, TDF levels + 0x0440 + 0x00000000 + + + RAF_LVL + Current Read-Address-FIFO fill level + [23:16] + read-only + + + WAF_LVL + Current Write-Address-FIFO fill level + [15:8] + read-only + + + TDF_LVL + Current Transfer-Data-FIFO fill level + [7:0] + read-only + + + + + CHAN_ABORT + Abort an in-progress transfer sequence on one or more channels + 0x0444 + 0x00000000 + + + CHAN_ABORT + Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. + [15:0] + read-write + clear + + + + + N_CHANNELS + The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + 0x0448 + 0x00000000 + + + N_CHANNELS + [4:0] + read-only + + + + + CH0_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0800 + 0x00000000 + + + CH0_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH0_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0804 + read-only + 0x00000000 + + + CH1_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0840 + 0x00000000 + + + CH1_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH1_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0844 + read-only + 0x00000000 + + + CH2_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0880 + 0x00000000 + + + CH2_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH2_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0884 + read-only + 0x00000000 + + + CH3_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x08c0 + 0x00000000 + + + CH3_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH3_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x08c4 + read-only + 0x00000000 + + + CH4_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0900 + 0x00000000 + + + CH4_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH4_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0904 + read-only + 0x00000000 + + + CH5_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0940 + 0x00000000 + + + CH5_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH5_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0944 + read-only + 0x00000000 + + + CH6_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0980 + 0x00000000 + + + CH6_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH6_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0984 + read-only + 0x00000000 + + + CH7_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x09c0 + 0x00000000 + + + CH7_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH7_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x09c4 + read-only + 0x00000000 + + + CH8_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0a00 + 0x00000000 + + + CH8_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH8_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0a04 + read-only + 0x00000000 + + + CH9_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0a40 + 0x00000000 + + + CH9_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH9_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0a44 + read-only + 0x00000000 + + + CH10_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0a80 + 0x00000000 + + + CH10_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH10_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0a84 + read-only + 0x00000000 + + + CH11_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x0ac0 + 0x00000000 + + + CH11_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH11_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x0ac4 + read-only + 0x00000000 + + + + + USBCTRL_DPRAM + 1 + DPRAM layout for USB device. + 0x50100000 + 32 + + 0 + 0x0100 + registers + + + + SETUP_PACKET_LOW + Bytes 0-3 of the SETUP packet from the host. + 0x0000 + 0x00000000 + + + WVALUE + [31:16] + read-write + + + BREQUEST + [15:8] + read-write + + + BMREQUESTTYPE + [7:0] + read-write + + + + + SETUP_PACKET_HIGH + Bytes 4-7 of the setup packet from the host. + 0x0004 + 0x00000000 + + + WLENGTH + [31:16] + read-write + + + WINDEX + [15:0] + read-write + + + + + EP1_IN_CONTROL + 0x0008 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP1_OUT_CONTROL + 0x000c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_IN_CONTROL + 0x0010 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_OUT_CONTROL + 0x0014 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_IN_CONTROL + 0x0018 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_OUT_CONTROL + 0x001c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_IN_CONTROL + 0x0020 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_OUT_CONTROL + 0x0024 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_IN_CONTROL + 0x0028 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_OUT_CONTROL + 0x002c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_IN_CONTROL + 0x0030 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_OUT_CONTROL + 0x0034 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_IN_CONTROL + 0x0038 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_OUT_CONTROL + 0x003c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_IN_CONTROL + 0x0040 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_OUT_CONTROL + 0x0044 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_IN_CONTROL + 0x0048 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_OUT_CONTROL + 0x004c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_IN_CONTROL + 0x0050 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_OUT_CONTROL + 0x0054 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_IN_CONTROL + 0x0058 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_OUT_CONTROL + 0x005c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_IN_CONTROL + 0x0060 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_OUT_CONTROL + 0x0064 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_IN_CONTROL + 0x0068 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_OUT_CONTROL + 0x006c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_IN_CONTROL + 0x0070 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_OUT_CONTROL + 0x0074 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_IN_CONTROL + 0x0078 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_OUT_CONTROL + 0x007c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP0_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x0080 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP0_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x0084 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP1_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x0088 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP1_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x008c + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP2_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x0090 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP2_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x0094 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP3_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x0098 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP3_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x009c + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP4_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00a0 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP4_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00a4 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP5_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00a8 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP5_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00ac + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP6_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00b0 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP6_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00b4 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP7_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00b8 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP7_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00bc + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP8_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00c0 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP8_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00c4 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP9_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00c8 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP9_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00cc + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP10_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00d0 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP10_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00d4 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP11_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00d8 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP11_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00dc + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP12_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00e0 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP12_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00e4 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP13_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00e8 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP13_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00ec + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP14_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00f0 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP14_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00f4 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP15_IN_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00f8 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP15_OUT_BUFFER_CONTROL + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00fc + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + + + USBCTRL_REGS + 1 + USB FS/LS controller device registers + 0x50110000 + 32 + + 0 + 0x1000 + registers + + + USBCTRL_IRQ + 5 + + + + ADDR_ENDP + Device address and endpoint control + 0x0000 + 0x00000000 + + + ENDPOINT + Device endpoint to send data to. Only valid for HOST mode. + [19:16] + read-write + + + ADDRESS + In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. + [6:0] + read-write + + + + + ADDR_ENDP1 + Interrupt endpoint 1. Only valid for HOST mode. + 0x0004 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP2 + Interrupt endpoint 2. Only valid for HOST mode. + 0x0008 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP3 + Interrupt endpoint 3. Only valid for HOST mode. + 0x000c + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP4 + Interrupt endpoint 4. Only valid for HOST mode. + 0x0010 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP5 + Interrupt endpoint 5. Only valid for HOST mode. + 0x0014 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP6 + Interrupt endpoint 6. Only valid for HOST mode. + 0x0018 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP7 + Interrupt endpoint 7. Only valid for HOST mode. + 0x001c + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP8 + Interrupt endpoint 8. Only valid for HOST mode. + 0x0020 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP9 + Interrupt endpoint 9. Only valid for HOST mode. + 0x0024 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP10 + Interrupt endpoint 10. Only valid for HOST mode. + 0x0028 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP11 + Interrupt endpoint 11. Only valid for HOST mode. + 0x002c + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP12 + Interrupt endpoint 12. Only valid for HOST mode. + 0x0030 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP13 + Interrupt endpoint 13. Only valid for HOST mode. + 0x0034 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP14 + Interrupt endpoint 14. Only valid for HOST mode. + 0x0038 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP15 + Interrupt endpoint 15. Only valid for HOST mode. + 0x003c + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + MAIN_CTRL + Main control register + 0x0040 + 0x00000000 + + + SIM_TIMING + Reduced timings for simulation + [31:31] + read-write + + + HOST_NDEVICE + Device mode = 0, Host mode = 1 + [1:1] + read-write + + + CONTROLLER_EN + Enable controller + [0:0] + read-write + + + + + SOF_WR + Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + 0x0044 + 0x00000000 + + + COUNT + [10:0] + write-only + + + + + SOF_RD + Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + 0x0048 + 0x00000000 + + + COUNT + [10:0] + read-only + + + + + SIE_CTRL + SIE control register + 0x004c + 0x00000000 + + + EP0_INT_STALL + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + [31:31] + read-write + + + EP0_DOUBLE_BUF + Device: EP0 single buffered = 0, double buffered = 1 + [30:30] + read-write + + + EP0_INT_1BUF + Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + [29:29] + read-write + + + EP0_INT_2BUF + Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + [28:28] + read-write + + + EP0_INT_NAK + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + [27:27] + read-write + + + DIRECT_EN + Direct bus drive enable + [26:26] + read-write + + + DIRECT_DP + Direct control of DP + [25:25] + read-write + + + DIRECT_DM + Direct control of DM + [24:24] + read-write + + + TRANSCEIVER_PD + Power down bus transceiver + [18:18] + read-write + + + RPU_OPT + Device: Pull-up strength (0=1K2, 1=2k3) + [17:17] + read-write + + + PULLUP_EN + Device: Enable pull up resistor + [16:16] + read-write + + + PULLDOWN_EN + Host: Enable pull down resistors + [15:15] + read-write + + + RESET_BUS + Host: Reset bus + [13:13] + read-write + clear + + + RESUME + Device: Remote wakeup. Device can initiate its own resume after suspend. + [12:12] + read-write + clear + + + VBUS_EN + Host: Enable VBUS + [11:11] + read-write + + + KEEP_ALIVE_EN + Host: Enable keep alive packet (for low speed bus) + [10:10] + read-write + + + SOF_EN + Host: Enable SOF generation (for full speed bus) + [9:9] + read-write + + + SOF_SYNC + Host: Delay packet(s) until after SOF + [8:8] + read-write + + + PREAMBLE_EN + Host: Preable enable for LS device on FS hub + [6:6] + read-write + + + STOP_TRANS + Host: Stop transaction + [4:4] + read-write + clear + + + RECEIVE_DATA + Host: Receive transaction (IN to host) + [3:3] + read-write + + + SEND_DATA + Host: Send transaction (OUT from host) + [2:2] + read-write + + + SEND_SETUP + Host: Send Setup packet + [1:1] + read-write + + + START_TRANS + Host: Start transaction + [0:0] + read-write + clear + + + + + SIE_STATUS + SIE status register + 0x0050 + 0x00000000 + + + DATA_SEQ_ERROR + Data Sequence Error.\n\n + The device can raise a sequence error in the following conditions:\n\n + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n + The host can raise a data sequence error in the following conditions:\n\n + * An IN packet from the device has the wrong data PID + [31:31] + read-write + oneToClear + + + ACK_REC + ACK received. Raised by both host and device. + [30:30] + read-write + oneToClear + + + STALL_REC + Host: STALL received + [29:29] + read-write + oneToClear + + + NAK_REC + Host: NAK received + [28:28] + read-write + oneToClear + + + RX_TIMEOUT + RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. + [27:27] + read-write + oneToClear + + + RX_OVERFLOW + RX overflow is raised by the Serial RX engine if the incoming data is too fast. + [26:26] + read-write + oneToClear + + + BIT_STUFF_ERROR + Bit Stuff Error. Raised by the Serial RX engine. + [25:25] + read-write + oneToClear + + + CRC_ERROR + CRC Error. Raised by the Serial RX engine. + [24:24] + read-write + oneToClear + + + BUS_RESET + Device: bus reset received + [19:19] + read-write + oneToClear + + + TRANS_COMPLETE + Transaction complete.\n\n + Raised by device if:\n\n + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n + Raised by host if:\n\n + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set + [18:18] + read-write + oneToClear + + + SETUP_REC + Device: Setup packet received + [17:17] + read-write + oneToClear + + + CONNECTED + Device: connected + [16:16] + read-write + oneToClear + + + RESUME + Host: Device has initiated a remote resume. Device: host has initiated a resume. + [11:11] + read-write + oneToClear + + + VBUS_OVER_CURR + VBUS over current detected + [10:10] + read-only + + + SPEED + Host: device speed. Disconnected = 00, LS = 01, FS = 10 + [9:8] + read-write + oneToClear + + + SUSPENDED + Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. + [4:4] + read-write + oneToClear + + + LINE_STATE + USB bus line state + [3:2] + read-only + + + VBUS_DETECTED + Device: VBUS Detected + [0:0] + read-only + + + + + INT_EP_CTRL + interrupt endpoint control register + 0x0054 + 0x00000000 + + + INT_EP_ACTIVE + Host: Enable interrupt endpoint 1 -> 15 + [15:1] + read-write + + + + + BUFF_STATUS + Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + 0x0058 + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + BUFF_CPU_SHOULD_HANDLE + Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + 0x005c + 0x00000000 + + + EP15_OUT + [31:31] + read-only + + + EP15_IN + [30:30] + read-only + + + EP14_OUT + [29:29] + read-only + + + EP14_IN + [28:28] + read-only + + + EP13_OUT + [27:27] + read-only + + + EP13_IN + [26:26] + read-only + + + EP12_OUT + [25:25] + read-only + + + EP12_IN + [24:24] + read-only + + + EP11_OUT + [23:23] + read-only + + + EP11_IN + [22:22] + read-only + + + EP10_OUT + [21:21] + read-only + + + EP10_IN + [20:20] + read-only + + + EP9_OUT + [19:19] + read-only + + + EP9_IN + [18:18] + read-only + + + EP8_OUT + [17:17] + read-only + + + EP8_IN + [16:16] + read-only + + + EP7_OUT + [15:15] + read-only + + + EP7_IN + [14:14] + read-only + + + EP6_OUT + [13:13] + read-only + + + EP6_IN + [12:12] + read-only + + + EP5_OUT + [11:11] + read-only + + + EP5_IN + [10:10] + read-only + + + EP4_OUT + [9:9] + read-only + + + EP4_IN + [8:8] + read-only + + + EP3_OUT + [7:7] + read-only + + + EP3_IN + [6:6] + read-only + + + EP2_OUT + [5:5] + read-only + + + EP2_IN + [4:4] + read-only + + + EP1_OUT + [3:3] + read-only + + + EP1_IN + [2:2] + read-only + + + EP0_OUT + [1:1] + read-only + + + EP0_IN + [0:0] + read-only + + + + + EP_ABORT + Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + 0x0060 + 0x00000000 + + + EP15_OUT + [31:31] + read-write + + + EP15_IN + [30:30] + read-write + + + EP14_OUT + [29:29] + read-write + + + EP14_IN + [28:28] + read-write + + + EP13_OUT + [27:27] + read-write + + + EP13_IN + [26:26] + read-write + + + EP12_OUT + [25:25] + read-write + + + EP12_IN + [24:24] + read-write + + + EP11_OUT + [23:23] + read-write + + + EP11_IN + [22:22] + read-write + + + EP10_OUT + [21:21] + read-write + + + EP10_IN + [20:20] + read-write + + + EP9_OUT + [19:19] + read-write + + + EP9_IN + [18:18] + read-write + + + EP8_OUT + [17:17] + read-write + + + EP8_IN + [16:16] + read-write + + + EP7_OUT + [15:15] + read-write + + + EP7_IN + [14:14] + read-write + + + EP6_OUT + [13:13] + read-write + + + EP6_IN + [12:12] + read-write + + + EP5_OUT + [11:11] + read-write + + + EP5_IN + [10:10] + read-write + + + EP4_OUT + [9:9] + read-write + + + EP4_IN + [8:8] + read-write + + + EP3_OUT + [7:7] + read-write + + + EP3_IN + [6:6] + read-write + + + EP2_OUT + [5:5] + read-write + + + EP2_IN + [4:4] + read-write + + + EP1_OUT + [3:3] + read-write + + + EP1_IN + [2:2] + read-write + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + EP_ABORT_DONE + Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + 0x0064 + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + EP_STALL_ARM + Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + 0x0068 + 0x00000000 + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + NAK_POLL + Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + 0x006c + 0x00100010 + + + DELAY_FS + NAK polling interval for a full speed device + [25:16] + read-write + + + DELAY_LS + NAK polling interval for a low speed device + [9:0] + read-write + + + + + EP_STATUS_STALL_NAK + Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + 0x0070 + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + USB_MUXING + Where to connect the USB controller. Should be to_phy by default. + 0x0074 + 0x00000000 + + + SOFTCON + [3:3] + read-write + + + TO_DIGITAL_PAD + [2:2] + read-write + + + TO_EXTPHY + [1:1] + read-write + + + TO_PHY + [0:0] + read-write + + + + + USB_PWR + Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + 0x0078 + 0x00000000 + + + OVERCURR_DETECT_EN + [5:5] + read-write + + + OVERCURR_DETECT + [4:4] + read-write + + + VBUS_DETECT_OVERRIDE_EN + [3:3] + read-write + + + VBUS_DETECT + [2:2] + read-write + + + VBUS_EN_OVERRIDE_EN + [1:1] + read-write + + + VBUS_EN + [0:0] + read-write + + + + + USBPHY_DIRECT + This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + 0x007c + 0x00000000 + + + DM_OVV + DM over voltage + [22:22] + read-only + + + DP_OVV + DP over voltage + [21:21] + read-only + + + DM_OVCN + DM overcurrent + [20:20] + read-only + + + DP_OVCN + DP overcurrent + [19:19] + read-only + + + RX_DM + DPM pin state + [18:18] + read-only + + + RX_DP + DPP pin state + [17:17] + read-only + + + RX_DD + Differential RX + [16:16] + read-only + + + TX_DIFFMODE + TX_DIFFMODE=0: Single ended mode\n + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) + [15:15] + read-write + + + TX_FSSLEW + TX_FSSLEW=0: Low speed slew rate\n + TX_FSSLEW=1: Full speed slew rate + [14:14] + read-write + + + TX_PD + TX power down override (if override enable is set). 1 = powered down. + [13:13] + read-write + + + RX_PD + RX power down override (if override enable is set). 1 = powered down. + [12:12] + read-write + + + TX_DM + Output data. TX_DIFFMODE=1, Ignored\n + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + [11:11] + read-write + + + TX_DP + Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + [10:10] + read-write + + + TX_DM_OE + Output enable. If TX_DIFFMODE=1, Ignored.\n + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + [9:9] + read-write + + + TX_DP_OE + Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + [8:8] + read-write + + + DM_PULLDN_EN + DM pull down enable + [6:6] + read-write + + + DM_PULLUP_EN + DM pull up enable + [5:5] + read-write + + + DM_PULLUP_HISEL + Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [4:4] + read-write + + + DP_PULLDN_EN + DP pull down enable + [2:2] + read-write + + + DP_PULLUP_EN + DP pull up enable + [1:1] + read-write + + + DP_PULLUP_HISEL + Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [0:0] + read-write + + + + + USBPHY_DIRECT_OVERRIDE + Override enable for each control in usbphy_direct + 0x0080 + 0x00000000 + + + TX_DIFFMODE_OVERRIDE_EN + [15:15] + read-write + + + DM_PULLUP_OVERRIDE_EN + [12:12] + read-write + + + TX_FSSLEW_OVERRIDE_EN + [11:11] + read-write + + + TX_PD_OVERRIDE_EN + [10:10] + read-write + + + RX_PD_OVERRIDE_EN + [9:9] + read-write + + + TX_DM_OVERRIDE_EN + [8:8] + read-write + + + TX_DP_OVERRIDE_EN + [7:7] + read-write + + + TX_DM_OE_OVERRIDE_EN + [6:6] + read-write + + + TX_DP_OE_OVERRIDE_EN + [5:5] + read-write + + + DM_PULLDN_EN_OVERRIDE_EN + [4:4] + read-write + + + DP_PULLDN_EN_OVERRIDE_EN + [3:3] + read-write + + + DP_PULLUP_EN_OVERRIDE_EN + [2:2] + read-write + + + DM_PULLUP_HISEL_OVERRIDE_EN + [1:1] + read-write + + + DP_PULLUP_HISEL_OVERRIDE_EN + [0:0] + read-write + + + + + USBPHY_TRIM + Used to adjust trim values of USB phy pull down resistors. + 0x0084 + 0x00001f1f + + + DM_PULLDN_TRIM + Value to drive to USB PHY\n + DM pulldown resistor trim control\n + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [12:8] + read-write + + + DP_PULLDN_TRIM + Value to drive to USB PHY\n + DP pulldown resistor trim control\n + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [4:0] + read-write + + + + + INTR + Raw Interrupts + 0x008c + 0x00000000 + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + INTE + Interrupt Enable + 0x0090 + 0x00000000 + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x0094 + 0x00000000 + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x0098 + 0x00000000 + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + + + PIO0 + 1 + Programmable IO block + 0x50200000 + 32 + + 0 + 0x1000 + registers + + + PIO0_IRQ_0 + 7 + + + PIO0_IRQ_1 + 8 + + + + CTRL + PIO control register + 0x0000 + 0x00000000 + + + CLKDIV_RESTART + Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. + [11:8] + read-write + clear + + + SM_RESTART + Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.\n\n + The program counter, the contents of the output shift register and the X/Y scratch registers are not affected. + [7:4] + read-write + clear + + + SM_ENABLE + Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. + [3:0] + read-write + + + + + FSTAT + FIFO status register + 0x0004 + 0x0f000f00 + + + TXEMPTY + State machine TX FIFO is empty + [27:24] + read-only + + + TXFULL + State machine TX FIFO is full + [19:16] + read-only + + + RXEMPTY + State machine RX FIFO is empty + [11:8] + read-only + + + RXFULL + State machine RX FIFO is full + [3:0] + read-only + + + + + FDEBUG + FIFO debug register + 0x0008 + 0x00000000 + + + TXSTALL + State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + [27:24] + read-write + oneToClear + + + TXOVER + TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. + [19:16] + read-write + oneToClear + + + RXUNDER + RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. + [11:8] + read-write + oneToClear + + + RXSTALL + State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. + [3:0] + read-write + oneToClear + + + + + FLEVEL + FIFO levels + 0x000c + 0x00000000 + + + RX3 + [31:28] + read-only + + + TX3 + [27:24] + read-only + + + RX2 + [23:20] + read-only + + + TX2 + [19:16] + read-only + + + RX1 + [15:12] + read-only + + + TX1 + [11:8] + read-only + + + RX0 + [7:4] + read-only + + + TX0 + [3:0] + read-only + + + + + TXF0 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x0010 + write-only + 0x00000000 + + + TXF1 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x0014 + write-only + 0x00000000 + + + TXF2 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x0018 + write-only + 0x00000000 + + + TXF3 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x001c + write-only + 0x00000000 + + + RXF0 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x0020 + read-only + 0x00000000 + + + RXF1 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x0024 + read-only + 0x00000000 + + + RXF2 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x0028 + read-only + 0x00000000 + + + RXF3 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x002c + read-only + 0x00000000 + + + IRQ + State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n + Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + 0x0030 + 0x00000000 + + + IRQ + [7:0] + read-write + oneToClear + + + + + IRQ_FORCE + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + 0x0034 + 0x00000000 + + + IRQ_FORCE + [7:0] + write-only + + + + + INPUT_SYNC_BYPASS + There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n + 0 -> input is synchronized (default)\n + 1 -> synchronizer is bypassed\n + If in doubt, leave this register as all zeroes. + 0x0038 + read-write + 0x00000000 + + + DBG_PADOUT + Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x003c + read-only + 0x00000000 + + + DBG_PADOE + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x0040 + read-only + 0x00000000 + + + DBG_CFGINFO + The PIO hardware has some free parameters that may vary between chip products.\n + These should be provided in the chip datasheet, but are also exposed here. + 0x0044 + 0x00000000 + + + IMEM_SIZE + The size of the instruction memory, measured in units of one instruction + [21:16] + read-only + + + SM_COUNT + The number of state machines this PIO instance is equipped with. + [11:8] + read-only + + + FIFO_DEPTH + The depth of the state machine TX/RX FIFOs, measured in words.\n + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n + this depth. + [5:0] + read-only + + + + + INSTR_MEM0 + Write-only access to instruction memory location 0 + 0x0048 + 0x00000000 + + + INSTR_MEM0 + [15:0] + write-only + + + + + INSTR_MEM1 + Write-only access to instruction memory location 1 + 0x004c + 0x00000000 + + + INSTR_MEM1 + [15:0] + write-only + + + + + INSTR_MEM2 + Write-only access to instruction memory location 2 + 0x0050 + 0x00000000 + + + INSTR_MEM2 + [15:0] + write-only + + + + + INSTR_MEM3 + Write-only access to instruction memory location 3 + 0x0054 + 0x00000000 + + + INSTR_MEM3 + [15:0] + write-only + + + + + INSTR_MEM4 + Write-only access to instruction memory location 4 + 0x0058 + 0x00000000 + + + INSTR_MEM4 + [15:0] + write-only + + + + + INSTR_MEM5 + Write-only access to instruction memory location 5 + 0x005c + 0x00000000 + + + INSTR_MEM5 + [15:0] + write-only + + + + + INSTR_MEM6 + Write-only access to instruction memory location 6 + 0x0060 + 0x00000000 + + + INSTR_MEM6 + [15:0] + write-only + + + + + INSTR_MEM7 + Write-only access to instruction memory location 7 + 0x0064 + 0x00000000 + + + INSTR_MEM7 + [15:0] + write-only + + + + + INSTR_MEM8 + Write-only access to instruction memory location 8 + 0x0068 + 0x00000000 + + + INSTR_MEM8 + [15:0] + write-only + + + + + INSTR_MEM9 + Write-only access to instruction memory location 9 + 0x006c + 0x00000000 + + + INSTR_MEM9 + [15:0] + write-only + + + + + INSTR_MEM10 + Write-only access to instruction memory location 10 + 0x0070 + 0x00000000 + + + INSTR_MEM10 + [15:0] + write-only + + + + + INSTR_MEM11 + Write-only access to instruction memory location 11 + 0x0074 + 0x00000000 + + + INSTR_MEM11 + [15:0] + write-only + + + + + INSTR_MEM12 + Write-only access to instruction memory location 12 + 0x0078 + 0x00000000 + + + INSTR_MEM12 + [15:0] + write-only + + + + + INSTR_MEM13 + Write-only access to instruction memory location 13 + 0x007c + 0x00000000 + + + INSTR_MEM13 + [15:0] + write-only + + + + + INSTR_MEM14 + Write-only access to instruction memory location 14 + 0x0080 + 0x00000000 + + + INSTR_MEM14 + [15:0] + write-only + + + + + INSTR_MEM15 + Write-only access to instruction memory location 15 + 0x0084 + 0x00000000 + + + INSTR_MEM15 + [15:0] + write-only + + + + + INSTR_MEM16 + Write-only access to instruction memory location 16 + 0x0088 + 0x00000000 + + + INSTR_MEM16 + [15:0] + write-only + + + + + INSTR_MEM17 + Write-only access to instruction memory location 17 + 0x008c + 0x00000000 + + + INSTR_MEM17 + [15:0] + write-only + + + + + INSTR_MEM18 + Write-only access to instruction memory location 18 + 0x0090 + 0x00000000 + + + INSTR_MEM18 + [15:0] + write-only + + + + + INSTR_MEM19 + Write-only access to instruction memory location 19 + 0x0094 + 0x00000000 + + + INSTR_MEM19 + [15:0] + write-only + + + + + INSTR_MEM20 + Write-only access to instruction memory location 20 + 0x0098 + 0x00000000 + + + INSTR_MEM20 + [15:0] + write-only + + + + + INSTR_MEM21 + Write-only access to instruction memory location 21 + 0x009c + 0x00000000 + + + INSTR_MEM21 + [15:0] + write-only + + + + + INSTR_MEM22 + Write-only access to instruction memory location 22 + 0x00a0 + 0x00000000 + + + INSTR_MEM22 + [15:0] + write-only + + + + + INSTR_MEM23 + Write-only access to instruction memory location 23 + 0x00a4 + 0x00000000 + + + INSTR_MEM23 + [15:0] + write-only + + + + + INSTR_MEM24 + Write-only access to instruction memory location 24 + 0x00a8 + 0x00000000 + + + INSTR_MEM24 + [15:0] + write-only + + + + + INSTR_MEM25 + Write-only access to instruction memory location 25 + 0x00ac + 0x00000000 + + + INSTR_MEM25 + [15:0] + write-only + + + + + INSTR_MEM26 + Write-only access to instruction memory location 26 + 0x00b0 + 0x00000000 + + + INSTR_MEM26 + [15:0] + write-only + + + + + INSTR_MEM27 + Write-only access to instruction memory location 27 + 0x00b4 + 0x00000000 + + + INSTR_MEM27 + [15:0] + write-only + + + + + INSTR_MEM28 + Write-only access to instruction memory location 28 + 0x00b8 + 0x00000000 + + + INSTR_MEM28 + [15:0] + write-only + + + + + INSTR_MEM29 + Write-only access to instruction memory location 29 + 0x00bc + 0x00000000 + + + INSTR_MEM29 + [15:0] + write-only + + + + + INSTR_MEM30 + Write-only access to instruction memory location 30 + 0x00c0 + 0x00000000 + + + INSTR_MEM30 + [15:0] + write-only + + + + + INSTR_MEM31 + Write-only access to instruction memory location 31 + 0x00c4 + 0x00000000 + + + INSTR_MEM31 + [15:0] + write-only + + + + + SM0_CLKDIV + Clock divisor register for state machine 0\n + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00c8 + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256).\n + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM0_EXECCTRL + Execution/behavioural settings for state machine 0 + 0x00cc + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable\n + When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + deassert the latest pin write. This can create useful masking/override behaviour\n + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom.\n + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [4:4] + read-write + + + TXLEVEL + All-ones if TX FIFO level < N, otherwise all-zeroes + 0 + + + RXLEVEL + All-ones if RX FIFO level < N, otherwise all-zeroes + 1 + + + + + STATUS_N + Comparison level for the MOV x, STATUS instruction + [3:0] + read-write + + + + + SM0_SHIFTCTRL + Control behaviour of the input/output shift registers for state machine 0 + 0x00d0 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + TX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + RX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + + + SM0_ADDR + Current instruction address of state machine 0 + 0x00d4 + 0x00000000 + + + SM0_ADDR + [4:0] + read-only + + + + + SM0_INSTR + Read to see the instruction currently addressed by state machine 0's program counter\n + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00d8 + 0x00000000 + + + SM0_INSTR + [15:0] + read-write + + + + + SM0_PINCTRL + State machine pin control + 0x00dc + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM1_CLKDIV + Clock divisor register for state machine 1\n + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00e0 + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256).\n + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM1_EXECCTRL + Execution/behavioural settings for state machine 1 + 0x00e4 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable\n + When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + deassert the latest pin write. This can create useful masking/override behaviour\n + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom.\n + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [4:4] + read-write + + + TXLEVEL + All-ones if TX FIFO level < N, otherwise all-zeroes + 0 + + + RXLEVEL + All-ones if RX FIFO level < N, otherwise all-zeroes + 1 + + + + + STATUS_N + Comparison level for the MOV x, STATUS instruction + [3:0] + read-write + + + + + SM1_SHIFTCTRL + Control behaviour of the input/output shift registers for state machine 1 + 0x00e8 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + TX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + RX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + + + SM1_ADDR + Current instruction address of state machine 1 + 0x00ec + 0x00000000 + + + SM1_ADDR + [4:0] + read-only + + + + + SM1_INSTR + Read to see the instruction currently addressed by state machine 1's program counter\n + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00f0 + 0x00000000 + + + SM1_INSTR + [15:0] + read-write + + + + + SM1_PINCTRL + State machine pin control + 0x00f4 + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM2_CLKDIV + Clock divisor register for state machine 2\n + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00f8 + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256).\n + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM2_EXECCTRL + Execution/behavioural settings for state machine 2 + 0x00fc + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable\n + When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + deassert the latest pin write. This can create useful masking/override behaviour\n + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom.\n + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [4:4] + read-write + + + TXLEVEL + All-ones if TX FIFO level < N, otherwise all-zeroes + 0 + + + RXLEVEL + All-ones if RX FIFO level < N, otherwise all-zeroes + 1 + + + + + STATUS_N + Comparison level for the MOV x, STATUS instruction + [3:0] + read-write + + + + + SM2_SHIFTCTRL + Control behaviour of the input/output shift registers for state machine 2 + 0x0100 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + TX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + RX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + + + SM2_ADDR + Current instruction address of state machine 2 + 0x0104 + 0x00000000 + + + SM2_ADDR + [4:0] + read-only + + + + + SM2_INSTR + Read to see the instruction currently addressed by state machine 2's program counter\n + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x0108 + 0x00000000 + + + SM2_INSTR + [15:0] + read-write + + + + + SM2_PINCTRL + State machine pin control + 0x010c + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM3_CLKDIV + Clock divisor register for state machine 3\n + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x0110 + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256).\n + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM3_EXECCTRL + Execution/behavioural settings for state machine 3 + 0x0114 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable\n + When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + deassert the latest pin write. This can create useful masking/override behaviour\n + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom.\n + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [4:4] + read-write + + + TXLEVEL + All-ones if TX FIFO level < N, otherwise all-zeroes + 0 + + + RXLEVEL + All-ones if RX FIFO level < N, otherwise all-zeroes + 1 + + + + + STATUS_N + Comparison level for the MOV x, STATUS instruction + [3:0] + read-write + + + + + SM3_SHIFTCTRL + Control behaviour of the input/output shift registers for state machine 3 + 0x0118 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + TX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + RX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + + + SM3_ADDR + Current instruction address of state machine 3 + 0x011c + 0x00000000 + + + SM3_ADDR + [4:0] + read-only + + + + + SM3_INSTR + Read to see the instruction currently addressed by state machine 3's program counter\n + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x0120 + 0x00000000 + + + SM3_INSTR + [15:0] + read-write + + + + + SM3_PINCTRL + State machine pin control + 0x0124 + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + INTR + Raw Interrupts + 0x0128 + 0x00000000 + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ0_INTE + Interrupt Enable for irq0 + 0x012c + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTF + Interrupt Force for irq0 + 0x0130 + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTS + Interrupt status after masking & forcing for irq0 + 0x0134 + 0x00000000 + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ1_INTE + Interrupt Enable for irq1 + 0x0138 + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTF + Interrupt Force for irq1 + 0x013c + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTS + Interrupt status after masking & forcing for irq1 + 0x0140 + 0x00000000 + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + + + PIO1 + 0x50300000 + + PIO1_IRQ_0 + 9 + + + PIO1_IRQ_1 + 10 + + + + SIO + 1 + Single-cycle IO block\n + Provides core-local and inter-core hardware for the two processors, with single-cycle access. + 0xd0000000 + 32 + + 0 + 0x0200 + registers + + + SIO_IRQ_PROC0 + 15 + + + SIO_IRQ_PROC1 + 16 + + + + CPUID + Processor core identifier\n + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + 0x0000 + read-only + 0x00000000 + + + GPIO_IN + Input value for GPIO pins + 0x0004 + 0x00000000 + + + GPIO_IN + Input value for GPIO0...29 + [29:0] + read-only + + + + + GPIO_HI_IN + Input value for QSPI pins + 0x0008 + 0x00000000 + + + GPIO_HI_IN + Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 + [5:0] + read-only + + + + + GPIO_OUT + GPIO output value + 0x0010 + 0x00000000 + + + GPIO_OUT + Set output level (1/0 -> high/low) for GPIO0...29.\n + Reading back gives the last value written, NOT the input value from the pins.\n + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n + the result is as though the write from core 0 took place first,\n + and the write from core 1 was then applied to that intermediate result. + [29:0] + read-write + + + + + GPIO_OUT_SET + GPIO output value set + 0x0014 + 0x00000000 + + + GPIO_OUT_SET + Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` + [29:0] + write-only + + + + + GPIO_OUT_CLR + GPIO output value clear + 0x0018 + 0x00000000 + + + GPIO_OUT_CLR + Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` + [29:0] + write-only + + + + + GPIO_OUT_XOR + GPIO output value XOR + 0x001c + 0x00000000 + + + GPIO_OUT_XOR + Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` + [29:0] + write-only + + + + + GPIO_OE + GPIO output enable + 0x0020 + 0x00000000 + + + GPIO_OE + Set output enable (1/0 -> output/input) for GPIO0...29.\n + Reading back gives the last value written.\n + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n + the result is as though the write from core 0 took place first,\n + and the write from core 1 was then applied to that intermediate result. + [29:0] + read-write + + + + + GPIO_OE_SET + GPIO output enable set + 0x0024 + 0x00000000 + + + GPIO_OE_SET + Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` + [29:0] + write-only + + + + + GPIO_OE_CLR + GPIO output enable clear + 0x0028 + 0x00000000 + + + GPIO_OE_CLR + Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` + [29:0] + write-only + + + + + GPIO_OE_XOR + GPIO output enable XOR + 0x002c + 0x00000000 + + + GPIO_OE_XOR + Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` + [29:0] + write-only + + + + + GPIO_HI_OUT + QSPI output value + 0x0030 + 0x00000000 + + + GPIO_HI_OUT + Set output level (1/0 -> high/low) for QSPI IO0...5.\n + Reading back gives the last value written, NOT the input value from the pins.\n + If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n + the result is as though the write from core 0 took place first,\n + and the write from core 1 was then applied to that intermediate result. + [5:0] + read-write + + + + + GPIO_HI_OUT_SET + QSPI output value set + 0x0034 + 0x00000000 + + + GPIO_HI_OUT_SET + Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + [5:0] + write-only + + + + + GPIO_HI_OUT_CLR + QSPI output value clear + 0x0038 + 0x00000000 + + + GPIO_HI_OUT_CLR + Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + [5:0] + write-only + + + + + GPIO_HI_OUT_XOR + QSPI output value XOR + 0x003c + 0x00000000 + + + GPIO_HI_OUT_XOR + Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + [5:0] + write-only + + + + + GPIO_HI_OE + QSPI output enable + 0x0040 + 0x00000000 + + + GPIO_HI_OE + Set output enable (1/0 -> output/input) for QSPI IO0...5.\n + Reading back gives the last value written.\n + If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n + the result is as though the write from core 0 took place first,\n + and the write from core 1 was then applied to that intermediate result. + [5:0] + read-write + + + + + GPIO_HI_OE_SET + QSPI output enable set + 0x0044 + 0x00000000 + + + GPIO_HI_OE_SET + Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + [5:0] + write-only + + + + + GPIO_HI_OE_CLR + QSPI output enable clear + 0x0048 + 0x00000000 + + + GPIO_HI_OE_CLR + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + [5:0] + write-only + + + + + GPIO_HI_OE_XOR + QSPI output enable XOR + 0x004c + 0x00000000 + + + GPIO_HI_OE_XOR + Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + [5:0] + write-only + + + + + FIFO_ST + Status register for inter-core FIFOs (mailboxes).\n + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + 0x0050 + 0x00000002 + + + ROE + Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + [3:3] + read-write + oneToClear + + + WOF + Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + [2:2] + read-write + oneToClear + + + RDY + Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + [1:1] + read-only + + + VLD + Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + [0:0] + read-only + + + + + FIFO_WR + Write access to this core's TX FIFO + 0x0054 + write-only + 0x00000000 + + + FIFO_RD + Read access to this core's RX FIFO + 0x0058 + read-only + 0x00000000 + + + SPINLOCK_ST + Spinlock state\n + A bitmap containing the state of all 32 spinlocks (1=locked).\n + Mainly intended for debugging. + 0x005c + read-only + 0x00000000 + + + DIV_UDIVIDEND + Divider unsigned dividend\n + Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n + UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n + unsigned calculation, and the S alias starts a signed calculation. + 0x0060 + read-write + 0x00000000 + + + DIV_UDIVISOR + Divider unsigned divisor\n + Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n + UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an\n + unsigned calculation, and the S alias starts a signed calculation. + 0x0064 + read-write + 0x00000000 + + + DIV_SDIVIDEND + Divider signed dividend\n + The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. + 0x0068 + read-write + 0x00000000 + + + DIV_SDIVISOR + Divider signed divisor\n + The same as UDIVISOR, but starts a signed calculation, rather than unsigned. + 0x006c + read-write + 0x00000000 + + + DIV_QUOTIENT + Divider result quotient\n + The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\n + For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n + This register can be written to directly, for context save/restore purposes. This halts any\n + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n + Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n + REMAINDER, QUOTIENT if CSR_DIRTY is used. + 0x0070 + read-write + 0x00000000 + + + DIV_REMAINDER + Divider result remainder\n + The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\n + For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n + This register can be written to directly, for context save/restore purposes. This halts any\n + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. + 0x0074 + read-write + 0x00000000 + + + DIV_CSR + Control and status register for divider. + 0x0078 + 0x00000001 + + + DIRTY + Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n + Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n + If the flag is used in this way, it's recommended to either read QUOTIENT only,\n + or REMAINDER and then QUOTIENT, to prevent data loss on context switch. + [1:1] + read-only + + + READY + Reads as 0 when a calculation is in progress, 1 otherwise.\n + Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n + matter if one is already in progress.\n + Writing to a result register will immediately terminate any in-progress calculation\n + and set the READY and DIRTY flags. + [0:0] + read-only + + + + + INTERP0_ACCUM0 + Read/write access to accumulator 0 + 0x0080 + read-write + 0x00000000 + + + INTERP0_ACCUM1 + Read/write access to accumulator 1 + 0x0084 + read-write + 0x00000000 + + + INTERP0_BASE0 + Read/write access to BASE0 register. + 0x0088 + read-write + 0x00000000 + + + INTERP0_BASE1 + Read/write access to BASE1 register. + 0x008c + read-write + 0x00000000 + + + INTERP0_BASE2 + Read/write access to BASE2 register. + 0x0090 + read-write + 0x00000000 + + + INTERP0_POP_LANE0 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x0094 + read-only + 0x00000000 + + + INTERP0_POP_LANE1 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x0098 + read-only + 0x00000000 + + + INTERP0_POP_FULL + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x009c + read-only + 0x00000000 + + + INTERP0_PEEK_LANE0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00a0 + read-only + 0x00000000 + + + INTERP0_PEEK_LANE1 + Read LANE1 result, without altering any internal state (PEEK). + 0x00a4 + read-only + 0x00000000 + + + INTERP0_PEEK_FULL + Read FULL result, without altering any internal state (PEEK). + 0x00a8 + read-only + 0x00000000 + + + INTERP0_CTRL_LANE0 + Control register for lane 0 + 0x00ac + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + BLEND + Only present on INTERP0 on each core. If BLEND mode is enabled:\n + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n + by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n + 0 and 255/256ths)\n + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. + [21:21] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive)\n + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] + read-write + + + + + INTERP0_CTRL_LANE1 + Control register for lane 1 + 0x00b0 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive)\n + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] + read-write + + + + + INTERP0_ACCUM0_ADD + Values written here are atomically added to ACCUM0\n + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00b4 + 0x00000000 + + + INTERP0_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP0_ACCUM1_ADD + Values written here are atomically added to ACCUM1\n + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00b8 + 0x00000000 + + + INTERP0_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP0_BASE_1AND0 + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00bc + write-only + 0x00000000 + + + INTERP1_ACCUM0 + Read/write access to accumulator 0 + 0x00c0 + read-write + 0x00000000 + + + INTERP1_ACCUM1 + Read/write access to accumulator 1 + 0x00c4 + read-write + 0x00000000 + + + INTERP1_BASE0 + Read/write access to BASE0 register. + 0x00c8 + read-write + 0x00000000 + + + INTERP1_BASE1 + Read/write access to BASE1 register. + 0x00cc + read-write + 0x00000000 + + + INTERP1_BASE2 + Read/write access to BASE2 register. + 0x00d0 + read-write + 0x00000000 + + + INTERP1_POP_LANE0 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00d4 + read-only + 0x00000000 + + + INTERP1_POP_LANE1 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00d8 + read-only + 0x00000000 + + + INTERP1_POP_FULL + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00dc + read-only + 0x00000000 + + + INTERP1_PEEK_LANE0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00e0 + read-only + 0x00000000 + + + INTERP1_PEEK_LANE1 + Read LANE1 result, without altering any internal state (PEEK). + 0x00e4 + read-only + 0x00000000 + + + INTERP1_PEEK_FULL + Read FULL result, without altering any internal state (PEEK). + 0x00e8 + read-only + 0x00000000 + + + INTERP1_CTRL_LANE0 + Control register for lane 0 + 0x00ec + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + CLAMP + Only present on INTERP1 on each core. If CLAMP mode is enabled:\n + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n + BASE0 and an upper bound of BASE1.\n + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + [22:22] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive)\n + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] + read-write + + + + + INTERP1_CTRL_LANE1 + Control register for lane 1 + 0x00f0 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive)\n + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] + read-write + + + + + INTERP1_ACCUM0_ADD + Values written here are atomically added to ACCUM0\n + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00f4 + 0x00000000 + + + INTERP1_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP1_ACCUM1_ADD + Values written here are atomically added to ACCUM1\n + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00f8 + 0x00000000 + + + INTERP1_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP1_BASE_1AND0 + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00fc + write-only + 0x00000000 + + + SPINLOCK0 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0100 + read-write + 0x00000000 + + + SPINLOCK1 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0104 + read-write + 0x00000000 + + + SPINLOCK2 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0108 + read-write + 0x00000000 + + + SPINLOCK3 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x010c + read-write + 0x00000000 + + + SPINLOCK4 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0110 + read-write + 0x00000000 + + + SPINLOCK5 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0114 + read-write + 0x00000000 + + + SPINLOCK6 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0118 + read-write + 0x00000000 + + + SPINLOCK7 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x011c + read-write + 0x00000000 + + + SPINLOCK8 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0120 + read-write + 0x00000000 + + + SPINLOCK9 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0124 + read-write + 0x00000000 + + + SPINLOCK10 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0128 + read-write + 0x00000000 + + + SPINLOCK11 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x012c + read-write + 0x00000000 + + + SPINLOCK12 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0130 + read-write + 0x00000000 + + + SPINLOCK13 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0134 + read-write + 0x00000000 + + + SPINLOCK14 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0138 + read-write + 0x00000000 + + + SPINLOCK15 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x013c + read-write + 0x00000000 + + + SPINLOCK16 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0140 + read-write + 0x00000000 + + + SPINLOCK17 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0144 + read-write + 0x00000000 + + + SPINLOCK18 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0148 + read-write + 0x00000000 + + + SPINLOCK19 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x014c + read-write + 0x00000000 + + + SPINLOCK20 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0150 + read-write + 0x00000000 + + + SPINLOCK21 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0154 + read-write + 0x00000000 + + + SPINLOCK22 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0158 + read-write + 0x00000000 + + + SPINLOCK23 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x015c + read-write + 0x00000000 + + + SPINLOCK24 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0160 + read-write + 0x00000000 + + + SPINLOCK25 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0164 + read-write + 0x00000000 + + + SPINLOCK26 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0168 + read-write + 0x00000000 + + + SPINLOCK27 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x016c + read-write + 0x00000000 + + + SPINLOCK28 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0170 + read-write + 0x00000000 + + + SPINLOCK29 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0174 + read-write + 0x00000000 + + + SPINLOCK30 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x0178 + read-write + 0x00000000 + + + SPINLOCK31 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + 0x017c + read-write + 0x00000000 + + + + + PPB + 1 + 0xe0000000 + 32 + + 0 + 0x10000 + registers + + + + SYST_CSR + Use the SysTick Control and Status Register to enable the SysTick features. + 0xe010 + 0x00000000 + + + COUNTFLAG + Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. + [16:16] + read-only + + + CLKSOURCE + SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n + Selects the SysTick timer clock source:\n + 0 = External reference clock.\n + 1 = Processor clock. + [2:2] + read-write + + + TICKINT + Enables SysTick exception request:\n + 0 = Counting down to zero does not assert the SysTick exception request.\n + 1 = Counting down to zero to asserts the SysTick exception request. + [1:1] + read-write + + + ENABLE + Enable SysTick counter:\n + 0 = Counter disabled.\n + 1 = Counter enabled. + [0:0] + read-write + + + + + SYST_RVR + Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + 0xe014 + 0x00000000 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0. + [23:0] + read-write + + + + + SYST_CVR + Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + 0xe018 + 0x00000000 + + + CURRENT + Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. + [23:0] + read-write + + + + + SYST_CALIB + Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + 0xe01c + 0x00000000 + + + NOREF + If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. + [31:31] + read-only + + + SKEW + If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). + [30:30] + read-only + + + TENMS + An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. + [23:0] + read-only + + + + + NVIC_ISER + Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n + If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. + 0xe100 + 0x00000000 + + + SETENA + Interrupt set-enable bits.\n + Write:\n + 0 = No effect.\n + 1 = Enable interrupt.\n + Read:\n + 0 = Interrupt disabled.\n + 1 = Interrupt enabled. + [31:0] + read-write + + + + + NVIC_ICER + Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. + 0xe180 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits.\n + Write:\n + 0 = No effect.\n + 1 = Disable interrupt.\n + Read:\n + 0 = Interrupt disabled.\n + 1 = Interrupt enabled. + [31:0] + read-write + + + + + NVIC_ISPR + The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. + 0xe200 + 0x00000000 + + + SETPEND + Interrupt set-pending bits.\n + Write:\n + 0 = No effect.\n + 1 = Changes interrupt state to pending.\n + Read:\n + 0 = Interrupt is not pending.\n + 1 = Interrupt is pending.\n + Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n + An interrupt that is pending has no effect.\n + A disabled interrupt sets the state of that interrupt to pending. + [31:0] + read-write + + + + + NVIC_ICPR + Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. + 0xe280 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits.\n + Write:\n + 0 = No effect.\n + 1 = Removes pending state and interrupt.\n + Read:\n + 0 = Interrupt is not pending.\n + 1 = Interrupt is pending. + [31:0] + read-write + + + + + NVIC_IPR0 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n + Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n + These registers are only word-accessible + 0xe400 + 0x00000000 + + + IP_3 + Priority of interrupt 3 + [31:30] + read-write + + + IP_2 + Priority of interrupt 2 + [23:22] + read-write + + + IP_1 + Priority of interrupt 1 + [15:14] + read-write + + + IP_0 + Priority of interrupt 0 + [7:6] + read-write + + + + + NVIC_IPR1 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xe404 + 0x00000000 + + + IP_7 + Priority of interrupt 7 + [31:30] + read-write + + + IP_6 + Priority of interrupt 6 + [23:22] + read-write + + + IP_5 + Priority of interrupt 5 + [15:14] + read-write + + + IP_4 + Priority of interrupt 4 + [7:6] + read-write + + + + + NVIC_IPR2 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xe408 + 0x00000000 + + + IP_11 + Priority of interrupt 11 + [31:30] + read-write + + + IP_10 + Priority of interrupt 10 + [23:22] + read-write + + + IP_9 + Priority of interrupt 9 + [15:14] + read-write + + + IP_8 + Priority of interrupt 8 + [7:6] + read-write + + + + + NVIC_IPR3 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xe40c + 0x00000000 + + + IP_15 + Priority of interrupt 15 + [31:30] + read-write + + + IP_14 + Priority of interrupt 14 + [23:22] + read-write + + + IP_13 + Priority of interrupt 13 + [15:14] + read-write + + + IP_12 + Priority of interrupt 12 + [7:6] + read-write + + + + + NVIC_IPR4 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xe410 + 0x00000000 + + + IP_19 + Priority of interrupt 19 + [31:30] + read-write + + + IP_18 + Priority of interrupt 18 + [23:22] + read-write + + + IP_17 + Priority of interrupt 17 + [15:14] + read-write + + + IP_16 + Priority of interrupt 16 + [7:6] + read-write + + + + + NVIC_IPR5 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xe414 + 0x00000000 + + + IP_23 + Priority of interrupt 23 + [31:30] + read-write + + + IP_22 + Priority of interrupt 22 + [23:22] + read-write + + + IP_21 + Priority of interrupt 21 + [15:14] + read-write + + + IP_20 + Priority of interrupt 20 + [7:6] + read-write + + + + + NVIC_IPR6 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xe418 + 0x00000000 + + + IP_27 + Priority of interrupt 27 + [31:30] + read-write + + + IP_26 + Priority of interrupt 26 + [23:22] + read-write + + + IP_25 + Priority of interrupt 25 + [15:14] + read-write + + + IP_24 + Priority of interrupt 24 + [7:6] + read-write + + + + + NVIC_IPR7 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xe41c + 0x00000000 + + + IP_31 + Priority of interrupt 31 + [31:30] + read-write + + + IP_30 + Priority of interrupt 30 + [23:22] + read-write + + + IP_29 + Priority of interrupt 29 + [15:14] + read-write + + + IP_28 + Priority of interrupt 28 + [7:6] + read-write + + + + + CPUID + Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. + 0xed00 + 0x410cc601 + + + IMPLEMENTER + Implementor code: 0x41 = ARM + [31:24] + read-only + + + VARIANT + Major revision number n in the rnpm revision status:\n + 0x0 = Revision 0. + [23:20] + read-only + + + ARCHITECTURE + Constant that defines the architecture of the processor:\n + 0xC = ARMv6-M architecture. + [19:16] + read-only + + + PARTNO + Number of processor within family: 0xC60 = Cortex-M0+ + [15:4] + read-only + + + REVISION + Minor revision number m in the rnpm revision status:\n + 0x1 = Patch 1. + [3:0] + read-only + + + + + ICSR + Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. + 0xed04 + 0x00000000 + + + NMIPENDSET + Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n + NMI set-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Changes NMI exception state to pending.\n + Read:\n + 0 = NMI exception is not pending.\n + 1 = NMI exception is pending.\n + Because NMI is the highest-priority exception, normally the processor enters the NMI\n + exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n + this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n + NMI signal is reasserted while the processor is executing that handler. + [31:31] + read-write + + + PENDSVSET + PendSV set-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Changes PendSV exception state to pending.\n + Read:\n + 0 = PendSV exception is not pending.\n + 1 = PendSV exception is pending.\n + Writing 1 to this bit is the only way to set the PendSV exception state to pending. + [28:28] + read-write + + + PENDSVCLR + PendSV clear-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Removes the pending state from the PendSV exception. + [27:27] + read-write + + + PENDSTSET + SysTick exception set-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Changes SysTick exception state to pending.\n + Read:\n + 0 = SysTick exception is not pending.\n + 1 = SysTick exception is pending. + [26:26] + read-write + + + PENDSTCLR + SysTick exception clear-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Removes the pending state from the SysTick exception.\n + This bit is WO. On a register read its value is Unknown. + [25:25] + read-write + + + ISRPREEMPT + The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. + [23:23] + read-only + + + ISRPENDING + External interrupt pending flag + [22:22] + read-only + + + VECTPENDING + Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. + [20:12] + read-only + + + VECTACTIVE + Active exception number field. Reset clears the VECTACTIVE field. + [8:0] + read-only + + + + + VTOR + The VTOR holds the vector table offset address. + 0xed08 + 0x00000000 + + + TBLOFF + Bits [31:8] of the indicate the vector table offset address. + [31:8] + read-write + + + + + AIRCR + Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + 0xed0c + 0x00000000 + + + VECTKEY + Register key:\n + Reads as Unknown\n + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + [31:16] + read-write + + + ENDIANESS + Data endianness implemented:\n + 0 = Little-endian. + [15:15] + read-only + + + SYSRESETREQ + Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. + [2:2] + read-write + + + VECTCLRACTIVE + Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. + [1:1] + read-write + + + + + SCR + System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + 0xed10 + 0x00000000 + + + SEVONPEND + Send Event on Pending bit:\n + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n + processor is not waiting for an event, the event is registered and affects the next WFE.\n + The processor also wakes up on execution of an SEV instruction or an external event. + [4:4] + read-write + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode:\n + 0 = Sleep.\n + 1 = Deep sleep. + [2:2] + read-write + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n + 0 = Do not sleep when returning to Thread mode.\n + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. + [1:1] + read-write + + + + + CCR + The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. + 0xed14 + 0x00000000 + + + STKALIGN + Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. + [9:9] + read-only + + + UNALIGN_TRP + Always reads as one, indicates that all unaligned accesses generate a HardFault. + [3:3] + read-only + + + + + SHPR2 + System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. + 0xed1c + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + [31:30] + read-write + + + + + SHPR3 + System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. + 0xed20 + 0x00000000 + + + PRI_15 + Priority of system handler 15, SysTick + [31:30] + read-write + + + PRI_14 + Priority of system handler 14, PendSV + [23:22] + read-write + + + + + SHCSR + Use the System Handler Control and State Register to determine or clear the pending status of SVCall. + 0xed24 + 0x00000000 + + + SVCALLPENDED + Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. + [15:15] + read-write + + + + + MPU_TYPE + Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. + 0xed90 + 0x00000800 + + + IREGION + Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. + [23:16] + read-only + + + DREGION + Number of regions supported by the MPU. + [15:8] + read-only + + + SEPARATE + Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. + [0:0] + read-only + + + + + MPU_CTRL + Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. + 0xed94 + 0x00000000 + + + PRIVDEFENA + Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n + 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n + covered by any enabled region causes a fault.\n + 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n + When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. + [2:2] + read-write + + + HFNMIENA + Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n + When the MPU is enabled:\n + 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n + 1 = the MPU is enabled during HardFault and NMI handlers. + [1:1] + read-write + + + ENABLE + Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n + 0 = MPU disabled.\n + 1 = MPU enabled. + [0:0] + read-write + + + + + MPU_RNR + Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. + 0xed98 + 0x00000000 + + + REGION + Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n + The MPU supports 8 memory regions, so the permitted values of this field are 0-7. + [3:0] + read-write + + + + + MPU_RBAR + Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. + 0xed9c + 0x00000000 + + + ADDR + Base address of the region. + [31:8] + read-write + + + VALID + On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n + Write:\n + 0 = MPU_RNR not changed, and the processor:\n + Updates the base address for the region specified in the MPU_RNR.\n + Ignores the value of the REGION field.\n + 1 = The processor:\n + Updates the value of the MPU_RNR to the value of the REGION field.\n + Updates the base address for the region specified in the REGION field.\n + Always reads as zero. + [4:4] + read-write + + + REGION + On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. + [3:0] + read-write + + + + + MPU_RASR + Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. + 0xeda0 + 0x00000000 + + + ATTRS + The MPU Region Attribute field. Use to define the region attribute control.\n + 28 = XN: Instruction access disable bit:\n + 0 = Instruction fetches enabled.\n + 1 = Instruction fetches disabled.\n + 26:24 = AP: Access permission field\n + 18 = S: Shareable bit\n + 17 = C: Cacheable bit\n + 16 = B: Bufferable bit + [31:16] + read-write + + + SRD + Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. + [15:8] + read-write + + + SIZE + Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes + [5:1] + read-write + + + ENABLE + Enables the region. + [0:0] + read-write + + + + + + + \ No newline at end of file diff --git a/variants/EDGE_CONTROL/conf/.mbedignore b/variants/EDGE_CONTROL/conf/.mbedignore index 3562a46dc..d10167ba6 100644 --- a/variants/EDGE_CONTROL/conf/.mbedignore +++ b/variants/EDGE_CONTROL/conf/.mbedignore @@ -1,2 +1 @@ -mbed-os/connectivity/drivers/cellular/* mbed-os/connectivity/nanostack/* \ No newline at end of file diff --git a/variants/EDGE_CONTROL/conf/mbed_app.json b/variants/EDGE_CONTROL/conf/mbed_app.json index 065dece92..572df7428 100644 --- a/variants/EDGE_CONTROL/conf/mbed_app.json +++ b/variants/EDGE_CONTROL/conf/mbed_app.json @@ -4,6 +4,7 @@ "MBED_STACK_STATS_ENABLED=1", "MBED_MEM_TRACING_ENABLED=1", "NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS=8", + "MBEDTLS_SHA1_C=1", "NRFX_WDT_ENABLED=1" ], "target_overrides": { @@ -13,7 +14,11 @@ "platform.stdio-baud-rate": 115200, "platform.default-serial-baud-rate": 115200, "platform.callback-nontrivial": true, - "rtos.main-thread-stack-size": 32768, + "rtos.main-thread-stack-size": 4096, + "cellular.debug-at": true, + "cellular.offload-dns-queries": true, + "cellular.at-handler-buffer-size": 1024, + "mbed-trace.enable": true, "target.mbed_app_start": "0x10000" }, "EDGE_CONTROL": { diff --git a/variants/EDGE_CONTROL/defines.txt b/variants/EDGE_CONTROL/defines.txt index 0198e4a12..1d081f7a7 100644 --- a/variants/EDGE_CONTROL/defines.txt +++ b/variants/EDGE_CONTROL/defines.txt @@ -38,7 +38,7 @@ -DFEATURE_STORAGE=1 -D__FPU_PRESENT=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1690447154.5646534 +-DMBED_BUILD_TIMESTAMP=1700127377.3953335 -D__MBED_CMSIS_RTOS_CM -DMBED_MPU_CUSTOM -DMBED_TICKLESS diff --git a/variants/EDGE_CONTROL/includes.txt b/variants/EDGE_CONTROL/includes.txt index 238ddb925..cbd9ed0fd 100644 --- a/variants/EDGE_CONTROL/includes.txt +++ b/variants/EDGE_CONTROL/includes.txt @@ -94,6 +94,33 @@ -iwithprefixbefore/mbed/connectivity/drivers/802.15.4_RF/stm-s2lp-rf-driver/source -iwithprefixbefore/mbed/connectivity/drivers/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver -iwithprefixbefore/mbed/connectivity/drivers/ble/FEATURE_BLE/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x +-iwithprefixbefore/mbed/connectivity/drivers/cellular +-iwithprefixbefore/mbed/connectivity/drivers/cellular/Altair +-iwithprefixbefore/mbed/connectivity/drivers/cellular/Altair/ALT1250 +-iwithprefixbefore/mbed/connectivity/drivers/cellular/Altair/ALT1250/PPP +-iwithprefixbefore/mbed/connectivity/drivers/cellular/GEMALTO +-iwithprefixbefore/mbed/connectivity/drivers/cellular/GEMALTO/CINTERION +-iwithprefixbefore/mbed/connectivity/drivers/cellular/GENERIC +-iwithprefixbefore/mbed/connectivity/drivers/cellular/GENERIC/GENERIC_AT3GPP +-iwithprefixbefore/mbed/connectivity/drivers/cellular/MultiTech +-iwithprefixbefore/mbed/connectivity/drivers/cellular/MultiTech/DragonflyNano +-iwithprefixbefore/mbed/connectivity/drivers/cellular/MultiTech/DragonflyNano/PPP +-iwithprefixbefore/mbed/connectivity/drivers/cellular/QUECTEL +-iwithprefixbefore/mbed/connectivity/drivers/cellular/QUECTEL/BC95 +-iwithprefixbefore/mbed/connectivity/drivers/cellular/QUECTEL/BG96 +-iwithprefixbefore/mbed/connectivity/drivers/cellular/QUECTEL/EC2X +-iwithprefixbefore/mbed/connectivity/drivers/cellular/QUECTEL/M26 +-iwithprefixbefore/mbed/connectivity/drivers/cellular/QUECTEL/UG96 +-iwithprefixbefore/mbed/connectivity/drivers/cellular/RiotMicro +-iwithprefixbefore/mbed/connectivity/drivers/cellular/RiotMicro/AT +-iwithprefixbefore/mbed/connectivity/drivers/cellular/TELIT +-iwithprefixbefore/mbed/connectivity/drivers/cellular/TELIT/HE910 +-iwithprefixbefore/mbed/connectivity/drivers/cellular/TELIT/ME310 +-iwithprefixbefore/mbed/connectivity/drivers/cellular/TELIT/ME910 +-iwithprefixbefore/mbed/connectivity/drivers/cellular/UBLOX +-iwithprefixbefore/mbed/connectivity/drivers/cellular/UBLOX/AT +-iwithprefixbefore/mbed/connectivity/drivers/cellular/UBLOX/N2XX +-iwithprefixbefore/mbed/connectivity/drivers/cellular/UBLOX/PPP -iwithprefixbefore/mbed/connectivity/drivers/mbedtls/FEATURE_CRYPTOCELL310 -iwithprefixbefore/mbed/connectivity/drivers/mbedtls/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840 -iwithprefixbefore/mbed/connectivity/drivers/mbedtls/FEATURE_CRYPTOCELL310/include diff --git a/variants/EDGE_CONTROL/libs/libmbed.a b/variants/EDGE_CONTROL/libs/libmbed.a index 69085f107..3fc128d6b 100644 Binary files a/variants/EDGE_CONTROL/libs/libmbed.a and b/variants/EDGE_CONTROL/libs/libmbed.a differ diff --git a/variants/EDGE_CONTROL/mbed_config.h b/variants/EDGE_CONTROL/mbed_config.h index 83a45d8be..c61166166 100644 --- a/variants/EDGE_CONTROL/mbed_config.h +++ b/variants/EDGE_CONTROL/mbed_config.h @@ -58,6 +58,8 @@ #define L2C_COC_CHAN_MAX 1 // set by library:cordio #define L2C_COC_REG_MAX 1 // set by library:cordio #define LHCI_ENABLE_VS 0 // set by library:cordio-ll +#define MBED_CONF_ALT1250_PPP_BAUDRATE 115200 // set by library:ALT1250_PPP +#define MBED_CONF_ALT1250_PPP_PROVIDE_DEFAULT 0 // set by library:ALT1250_PPP #define MBED_CONF_ATMEL_RF_ASSUME_SPACED_SPI 0 // set by library:atmel-rf #define MBED_CONF_ATMEL_RF_FULL_SPI_SPEED 7500000 // set by library:atmel-rf #define MBED_CONF_ATMEL_RF_FULL_SPI_SPEED_BYTE_SPACING 250 // set by library:atmel-rf @@ -69,10 +71,11 @@ #define MBED_CONF_BLE_API_IMPLEMENTATION_MAX_CHARACTERISTIC_AUTHORISATION_COUNT 20 // set by library:ble-api-implementation #define MBED_CONF_BLE_PRESENT 1 // set by library:ble #define MBED_CONF_BLE_TRACE_HUMAN_READABLE_ENUMS 0 // set by library:ble -#define MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE 32 // set by library:cellular +#define MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE 1024 // set by application[*] #define MBED_CONF_CELLULAR_CONTROL_PLANE_OPT 0 // set by library:cellular -#define MBED_CONF_CELLULAR_DEBUG_AT 0 // set by library:cellular +#define MBED_CONF_CELLULAR_DEBUG_AT 1 // set by application[*] #define MBED_CONF_CELLULAR_MAX_CP_DATA_RECV_LEN 1358 // set by library:cellular +#define MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES 1 // set by application[*] #define MBED_CONF_CELLULAR_PRESENT 1 // set by library:cellular #define MBED_CONF_CELLULAR_RANDOM_MAX_START_DELAY 0 // set by library:cellular #define MBED_CONF_CELLULAR_USE_APN_LOOKUP 0 // set by library:cellular @@ -182,6 +185,10 @@ #define MBED_CONF_FILESYSTEM_PRESENT 1 // set by library:filesystem #define MBED_CONF_FLASHIAP_BLOCK_DEVICE_BASE_ADDRESS 0xFFFFFFFF // set by library:flashiap-block-device #define MBED_CONF_FLASHIAP_BLOCK_DEVICE_SIZE 0 // set by library:flashiap-block-device +#define MBED_CONF_GEMALTO_CINTERION_BAUDRATE 115200 // set by library:GEMALTO_CINTERION +#define MBED_CONF_GEMALTO_CINTERION_PROVIDE_DEFAULT 0 // set by library:GEMALTO_CINTERION +#define MBED_CONF_GENERIC_AT3GPP_BAUDRATE 115200 // set by library:GENERIC_AT3GPP +#define MBED_CONF_GENERIC_AT3GPP_PROVIDE_DEFAULT 0 // set by library:GENERIC_AT3GPP #define MBED_CONF_LORA_ADR_ON 1 // set by library:lora #define MBED_CONF_LORA_APPLICATION_EUI {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} // set by library:lora #define MBED_CONF_LORA_APPLICATION_KEY {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} // set by library:lora @@ -247,6 +254,7 @@ #define MBED_CONF_LWIP_TCP_WND (4 * TCP_MSS) // set by library:lwip #define MBED_CONF_LWIP_UDP_SOCKET_MAX 4 // set by library:lwip #define MBED_CONF_LWIP_USE_MBED_TRACE 0 // set by library:lwip +#define MBED_CONF_MBED_TRACE_ENABLE 1 // set by application[*] #define MBED_CONF_MCR20A_PROVIDE_DEFAULT 0 // set by library:mcr20a #define MBED_CONF_NANOSTACK_LIBSERVICE_NSDYNMEM_TRACKER_ENABLED 0 // set by library:nanostack-libservice #define MBED_CONF_NANOSTACK_LIBSERVICE_PRESENT 1 // set by library:nanostack-libservice @@ -307,13 +315,26 @@ #define MBED_CONF_QSPIF_QSPI_MIN_READ_SIZE 4 // set by library:qspif[MCU_NRF52840] #define MBED_CONF_QSPIF_QSPI_POLARITY_MODE 0 // set by library:qspif #define MBED_CONF_QSPIF_QSPI_SCK MBED_CONF_DRIVERS_QSPI_SCK // set by library:qspif +#define MBED_CONF_QUECTEL_BC95_BAUDRATE 9600 // set by library:QUECTEL_BC95 +#define MBED_CONF_QUECTEL_BC95_PROVIDE_DEFAULT 0 // set by library:QUECTEL_BC95 +#define MBED_CONF_QUECTEL_BG96_BAUDRATE 115200 // set by library:QUECTEL_BG96 +#define MBED_CONF_QUECTEL_BG96_PROVIDE_DEFAULT 0 // set by library:QUECTEL_BG96 +#define MBED_CONF_QUECTEL_EC2X_BAUDRATE 115200 // set by library:QUECTEL_EC2X +#define MBED_CONF_QUECTEL_EC2X_PROVIDE_DEFAULT 0 // set by library:QUECTEL_EC2X +#define MBED_CONF_QUECTEL_EC2X_START_TIMEOUT 15000 // set by library:QUECTEL_EC2X +#define MBED_CONF_QUECTEL_M26_BAUDRATE 115200 // set by library:QUECTEL_M26 +#define MBED_CONF_QUECTEL_M26_PROVIDE_DEFAULT 0 // set by library:QUECTEL_M26 +#define MBED_CONF_QUECTEL_UG96_BAUDRATE 115200 // set by library:QUECTEL_UG96 +#define MBED_CONF_QUECTEL_UG96_PROVIDE_DEFAULT 0 // set by library:QUECTEL_UG96 +#define MBED_CONF_RM1000_AT_BAUDRATE 230400 // set by library:RM1000_AT +#define MBED_CONF_RM1000_AT_PROVIDE_DEFAULT 0 // set by library:RM1000_AT #define MBED_CONF_RTOS_API_PRESENT 1 // set by library:rtos-api #define MBED_CONF_RTOS_ENABLE_ALL_RTX_EVENTS 0 // set by library:rtos #define MBED_CONF_RTOS_EVFLAGS_NUM 0 // set by library:rtos #define MBED_CONF_RTOS_IDLE_THREAD_STACK_SIZE 512 // set by library:rtos #define MBED_CONF_RTOS_IDLE_THREAD_STACK_SIZE_DEBUG_EXTRA 0 // set by library:rtos #define MBED_CONF_RTOS_IDLE_THREAD_STACK_SIZE_TICKLESS_EXTRA 256 // set by library:rtos -#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 32768 // set by application[*] +#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 4096 // set by application[*] #define MBED_CONF_RTOS_MSGQUEUE_DATA_SIZE 0 // set by library:rtos #define MBED_CONF_RTOS_MSGQUEUE_NUM 0 // set by library:rtos #define MBED_CONF_RTOS_MUTEX_NUM 0 // set by library:rtos @@ -325,6 +346,8 @@ #define MBED_CONF_RTOS_TIMER_NUM 0 // set by library:rtos #define MBED_CONF_RTOS_TIMER_THREAD_STACK_SIZE 768 // set by library:rtos #define MBED_CONF_S2LP_PROVIDE_DEFAULT 0 // set by library:s2lp +#define MBED_CONF_SARA4_PPP_BAUDRATE 115200 // set by library:SARA4_PPP +#define MBED_CONF_SARA4_PPP_PROVIDE_DEFAULT 0 // set by library:SARA4_PPP #define MBED_CONF_SD_CMD0_IDLE_STATE_RETRIES 5 // set by library:sd #define MBED_CONF_SD_CMD_TIMEOUT 10000 // set by library:sd #define MBED_CONF_SD_CRC_ENABLED 0 // set by library:sd @@ -380,6 +403,18 @@ #define MBED_CONF_TARGET_UART_0_FIFO_SIZE 32 // set by target:MCU_NRF52840 #define MBED_CONF_TARGET_UART_1_FIFO_SIZE 32 // set by target:MCU_NRF52840 #define MBED_CONF_TARGET_XIP_ENABLE 0 // set by target:Target +#define MBED_CONF_TELIT_HE910_BAUDRATE 115200 // set by library:TELIT_HE910 +#define MBED_CONF_TELIT_HE910_PROVIDE_DEFAULT 0 // set by library:TELIT_HE910 +#define MBED_CONF_TELIT_ME310_BAUDRATE 115200 // set by library:TELIT_ME310 +#define MBED_CONF_TELIT_ME310_PROVIDE_DEFAULT 0 // set by library:TELIT_ME310 +#define MBED_CONF_TELIT_ME910_BAUDRATE 115200 // set by library:TELIT_ME910 +#define MBED_CONF_TELIT_ME910_PROVIDE_DEFAULT 0 // set by library:TELIT_ME910 +#define MBED_CONF_UBLOX_AT_BAUDRATE 115200 // set by library:UBLOX_AT +#define MBED_CONF_UBLOX_AT_PROVIDE_DEFAULT 0 // set by library:UBLOX_AT +#define MBED_CONF_UBLOX_N2XX_BAUDRATE 9600 // set by library:UBLOX_N2XX +#define MBED_CONF_UBLOX_N2XX_PROVIDE_DEFAULT 0 // set by library:UBLOX_N2XX +#define MBED_CONF_UBLOX_PPP_BAUDRATE 115200 // set by library:UBLOX_PPP +#define MBED_CONF_UBLOX_PPP_PROVIDE_DEFAULT 0 // set by library:UBLOX_PPP #define MBED_CRC_TABLE_SIZE 16 // set by library:drivers #define MBED_LFS2_BLOCK_CYCLES 1024 // set by library:littlefs2 #define MBED_LFS2_BLOCK_SIZE 512 // set by library:littlefs2 @@ -412,6 +447,7 @@ #define LHCI_ENABLE_VS 0 // defined by library:cordio-nordic-ll #define LL_MAX_PER_SCAN 3 // defined by library:cordio-nordic-ll #define MBEDTLS_CIPHER_MODE_CTR // defined by library:SecureStore +#define MBEDTLS_SHA1_C 1 // defined by application #define MBED_HEAP_STATS_ENABLED 1 // defined by application #define MBED_MEM_TRACING_ENABLED 1 // defined by application #define MBED_STACK_STATS_ENABLED 1 // defined by application diff --git a/variants/PORTENTA_H7_M4/cflags.txt b/variants/GENERIC_STM32H747_M4/cflags.txt similarity index 78% rename from variants/PORTENTA_H7_M4/cflags.txt rename to variants/GENERIC_STM32H747_M4/cflags.txt index 5ea7d6111..846011196 100644 --- a/variants/PORTENTA_H7_M4/cflags.txt +++ b/variants/GENERIC_STM32H747_M4/cflags.txt @@ -1,11 +1,7 @@ -c -std=gnu11 -DAPPLICATION_ADDR=0x8100000 --DAPPLICATION_RAM_ADDR=0x10000000 --DAPPLICATION_RAM_SIZE=0x48000 -DAPPLICATION_SIZE=0x100000 --DMBED_RAM1_SIZE=0x80000 --DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x48000 -DMBED_RAM_START=0x10000000 -DMBED_ROM_SIZE=0x100000 diff --git a/variants/GENERIC_STM32H747_M4/clock_override.cpp b/variants/GENERIC_STM32H747_M4/clock_override.cpp new file mode 100644 index 000000000..dc41f3334 --- /dev/null +++ b/variants/GENERIC_STM32H747_M4/clock_override.cpp @@ -0,0 +1,93 @@ +#include "Arduino.h" + +#if defined(ARDUINO_GIGA) +#undef HSE_VALUE +#define HSE_VALUE 16000000 +#endif + +extern "C" uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue; + float_t fracn1, pllvco; + uint32_t sysclockfreq; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); + } + else + { + sysclockfreq = (uint32_t) HSI_VALUE; + } + + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + sysclockfreq = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + } + else + { + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + sysclockfreq = 0U; + } + break; + + default: + sysclockfreq = CSI_VALUE; + break; + } + + return sysclockfreq; +} \ No newline at end of file diff --git a/variants/PORTENTA_H7_M4/conf/.mbedignore b/variants/GENERIC_STM32H747_M4/conf/.mbedignore similarity index 100% rename from variants/PORTENTA_H7_M4/conf/.mbedignore rename to variants/GENERIC_STM32H747_M4/conf/.mbedignore diff --git a/variants/PORTENTA_H7_M4/conf/mbed_app.json b/variants/GENERIC_STM32H747_M4/conf/mbed_app.json similarity index 100% rename from variants/PORTENTA_H7_M4/conf/mbed_app.json rename to variants/GENERIC_STM32H747_M4/conf/mbed_app.json diff --git a/variants/PORTENTA_H7_M4/cxxflags.txt b/variants/GENERIC_STM32H747_M4/cxxflags.txt similarity index 78% rename from variants/PORTENTA_H7_M4/cxxflags.txt rename to variants/GENERIC_STM32H747_M4/cxxflags.txt index 0787fe177..fd71297d0 100644 --- a/variants/PORTENTA_H7_M4/cxxflags.txt +++ b/variants/GENERIC_STM32H747_M4/cxxflags.txt @@ -3,11 +3,7 @@ -fno-rtti -std=gnu++14 -DAPPLICATION_ADDR=0x8100000 --DAPPLICATION_RAM_ADDR=0x10000000 --DAPPLICATION_RAM_SIZE=0x48000 -DAPPLICATION_SIZE=0x100000 --DMBED_RAM1_SIZE=0x80000 --DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x48000 -DMBED_RAM_START=0x10000000 -DMBED_ROM_SIZE=0x100000 diff --git a/variants/PORTENTA_H7_M4/defines.txt b/variants/GENERIC_STM32H747_M4/defines.txt similarity index 91% rename from variants/PORTENTA_H7_M4/defines.txt rename to variants/GENERIC_STM32H747_M4/defines.txt index 90277e8fe..06f4094b8 100644 --- a/variants/PORTENTA_H7_M4/defines.txt +++ b/variants/GENERIC_STM32H747_M4/defines.txt @@ -42,7 +42,7 @@ -DFEATURE_BLE=1 -D__FPU_PRESENT=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1690447099.1347957 +-DMBED_BUILD_TIMESTAMP=1698330953.225854 -D__MBED_CMSIS_RTOS_CM -DMBED_MPU_CUSTOM -DMBED_TICKLESS @@ -52,21 +52,20 @@ -DMETAL_MAX_DEVICE_REGIONS=2 -DNO_ATOMIC_64_SUPPORT -DNO_VTOR_RELOCATE --DQSPI_NO_SAMPLE_SHIFT -DRPMSG_BUFFER_SIZE=2048 -DSTM32H747xx -DTARGET_CORDIO -DTARGET_CORTEX -DTARGET_CORTEX_M +-DTARGET_GENERIC_STM32H747_M4 -DTARGET_LIKE_CORTEX_M4 -DTARGET_LIKE_MBED -DTARGET_M4 -DTARGET_MCU_STM32 -DTARGET_MCU_STM32H7 -DTARGET_MCU_STM32H747xI --DTARGET_NAME=PORTENTA_H7_M4 --DTARGET_PORTENTA_H7 --DTARGET_PORTENTA_H7_M4 +-DTARGET_MCU_STM32H747xI_CM4 +-DTARGET_NAME=GENERIC_STM32H747_M4 -DTARGET_RELEASE -DTARGET_RTOS_M4_M7 -DTARGET_STM diff --git a/variants/GENERIC_STM32H747_M4/includes.txt b/variants/GENERIC_STM32H747_M4/includes.txt new file mode 100644 index 000000000..ad11516dc --- /dev/null +++ b/variants/GENERIC_STM32H747_M4/includes.txt @@ -0,0 +1,1504 @@ +-iwithprefixbefore/mbed +-iwithprefixbefore/mbed/cmsis +-iwithprefixbefore/mbed/cmsis/CMSIS_5 +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2 +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/Include +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Config +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Include +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Include1 +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/TARGET_CORTEX_M +-iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/TARGET_CORTEX_M/Include +-iwithprefixbefore/mbed/cmsis/device +-iwithprefixbefore/mbed/cmsis/device/RTE +-iwithprefixbefore/mbed/cmsis/device/RTE/include +-iwithprefixbefore/mbed/cmsis/device/rtos +-iwithprefixbefore/mbed/cmsis/device/rtos/include +-iwithprefixbefore/mbed/connectivity +-iwithprefixbefore/mbed/connectivity/FEATURE_BLE +-iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include +-iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble +-iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/common +-iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/compatibility +-iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/compatibility/ble +-iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/driver 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+-iwithprefixbefore/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs +-iwithprefixbefore/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base +-iwithprefixbefore/mbed/connectivity/nanostack/sal-stack-nanostack/source/ipv6_stack +-iwithprefixbefore/mbed/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6 +-iwithprefixbefore/mbed/connectivity/nanostack/sal-stack-nanostack/source/libNET +-iwithprefixbefore/mbed/connectivity/nanostack/sal-stack-nanostack/source/libNET/src +-iwithprefixbefore/mbed/connectivity/netsocket +-iwithprefixbefore/mbed/connectivity/netsocket/include +-iwithprefixbefore/mbed/connectivity/netsocket/include/netsocket +-iwithprefixbefore/mbed/connectivity/nfc +-iwithprefixbefore/mbed/connectivity/nfc/include +-iwithprefixbefore/mbed/connectivity/nfc/include/nfc +-iwithprefixbefore/mbed/connectivity/nfc/include/nfc/ndef +-iwithprefixbefore/mbed/connectivity/nfc/include/nfc/ndef/common +-iwithprefixbefore/mbed/connectivity/nfc/libraries +-iwithprefixbefore/mbed/connectivity/nfc/libraries/acore +-iwithprefixbefore/mbed/connectivity/nfc/libraries/acore/acore +-iwithprefixbefore/mbed/connectivity/nfc/libraries/stack +-iwithprefixbefore/mbed/connectivity/nfc/libraries/stack/ndef +-iwithprefixbefore/mbed/connectivity/nfc/libraries/stack/platform +-iwithprefixbefore/mbed/connectivity/nfc/libraries/stack/tech +-iwithprefixbefore/mbed/connectivity/nfc/libraries/stack/tech/iso7816 +-iwithprefixbefore/mbed/connectivity/nfc/libraries/stack/tech/isodep +-iwithprefixbefore/mbed/connectivity/nfc/libraries/stack/tech/type4 +-iwithprefixbefore/mbed/connectivity/nfc/libraries/stack/transceiver +-iwithprefixbefore/mbed/drivers +-iwithprefixbefore/mbed/drivers/device_key +-iwithprefixbefore/mbed/drivers/device_key/include +-iwithprefixbefore/mbed/drivers/device_key/include/device_key +-iwithprefixbefore/mbed/drivers/include +-iwithprefixbefore/mbed/drivers/include/drivers +-iwithprefixbefore/mbed/drivers/include/drivers/interfaces +-iwithprefixbefore/mbed/drivers/usb +-iwithprefixbefore/mbed/drivers/usb/include +-iwithprefixbefore/mbed/drivers/usb/include/usb +-iwithprefixbefore/mbed/drivers/usb/include/usb/internal +-iwithprefixbefore/mbed/events +-iwithprefixbefore/mbed/events/include +-iwithprefixbefore/mbed/events/include/events +-iwithprefixbefore/mbed/events/include/events/internal +-iwithprefixbefore/mbed/features +-iwithprefixbefore/mbed/features/frameworks +-iwithprefixbefore/mbed/features/frameworks/greentea-client +-iwithprefixbefore/mbed/features/frameworks/greentea-client/greentea-client +-iwithprefixbefore/mbed/features/frameworks/mbed-client-cli +-iwithprefixbefore/mbed/features/frameworks/mbed-client-cli/mbed-client-cli +-iwithprefixbefore/mbed/features/frameworks/unity +-iwithprefixbefore/mbed/features/frameworks/unity/unity +-iwithprefixbefore/mbed/features/frameworks/utest +-iwithprefixbefore/mbed/features/frameworks/utest/utest +-iwithprefixbefore/mbed/hal +-iwithprefixbefore/mbed/hal/include +-iwithprefixbefore/mbed/hal/include/hal +-iwithprefixbefore/mbed/hal/usb +-iwithprefixbefore/mbed/hal/usb/include +-iwithprefixbefore/mbed/hal/usb/include/usb +-iwithprefixbefore/mbed/platform +-iwithprefixbefore/mbed/platform/cxxsupport +-iwithprefixbefore/mbed/platform/include +-iwithprefixbefore/mbed/platform/include/platform +-iwithprefixbefore/mbed/platform/include/platform/internal +-iwithprefixbefore/mbed/platform/mbed-trace +-iwithprefixbefore/mbed/platform/mbed-trace/include +-iwithprefixbefore/mbed/platform/mbed-trace/include/mbed-trace +-iwithprefixbefore/mbed/platform/randlib +-iwithprefixbefore/mbed/platform/randlib/include +-iwithprefixbefore/mbed/platform/randlib/include/mbed-client-randlib +-iwithprefixbefore/mbed/platform/randlib/include/mbed-client-randlib/platform +-iwithprefixbefore/mbed/platform/source +-iwithprefixbefore/mbed/platform/source/minimal-printf +-iwithprefixbefore/mbed/rtos +-iwithprefixbefore/mbed/rtos/include +-iwithprefixbefore/mbed/rtos/include/rtos +-iwithprefixbefore/mbed/rtos/include/rtos/internal +-iwithprefixbefore/mbed/rtos/source +-iwithprefixbefore/mbed/storage +-iwithprefixbefore/mbed/storage/blockdevice +-iwithprefixbefore/mbed/storage/blockdevice/COMPONENT_FLASHIAP +-iwithprefixbefore/mbed/storage/blockdevice/COMPONENT_FLASHIAP/include +-iwithprefixbefore/mbed/storage/blockdevice/COMPONENT_FLASHIAP/include/FlashIAP +-iwithprefixbefore/mbed/storage/blockdevice/COMPONENT_QSPIF +-iwithprefixbefore/mbed/storage/blockdevice/COMPONENT_QSPIF/include +-iwithprefixbefore/mbed/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF +-iwithprefixbefore/mbed/storage/blockdevice/include +-iwithprefixbefore/mbed/storage/blockdevice/include/blockdevice +-iwithprefixbefore/mbed/storage/blockdevice/include/blockdevice/internal +-iwithprefixbefore/mbed/storage/filesystem +-iwithprefixbefore/mbed/storage/filesystem/fat +-iwithprefixbefore/mbed/storage/filesystem/fat/ChaN +-iwithprefixbefore/mbed/storage/filesystem/fat/include +-iwithprefixbefore/mbed/storage/filesystem/fat/include/fat +-iwithprefixbefore/mbed/storage/filesystem/include +-iwithprefixbefore/mbed/storage/filesystem/include/filesystem +-iwithprefixbefore/mbed/storage/filesystem/littlefs +-iwithprefixbefore/mbed/storage/filesystem/littlefs/include +-iwithprefixbefore/mbed/storage/filesystem/littlefs/include/littlefs +-iwithprefixbefore/mbed/storage/filesystem/littlefs/littlefs +-iwithprefixbefore/mbed/storage/filesystem/littlefsv2 +-iwithprefixbefore/mbed/storage/filesystem/littlefsv2/include +-iwithprefixbefore/mbed/storage/filesystem/littlefsv2/include/littlefsv2 +-iwithprefixbefore/mbed/storage/filesystem/littlefsv2/littlefs +-iwithprefixbefore/mbed/storage/kvstore +-iwithprefixbefore/mbed/storage/kvstore/direct_access_devicekey +-iwithprefixbefore/mbed/storage/kvstore/direct_access_devicekey/include +-iwithprefixbefore/mbed/storage/kvstore/direct_access_devicekey/include/direct_access_devicekey +-iwithprefixbefore/mbed/storage/kvstore/filesystemstore +-iwithprefixbefore/mbed/storage/kvstore/filesystemstore/include +-iwithprefixbefore/mbed/storage/kvstore/filesystemstore/include/filesystemstore +-iwithprefixbefore/mbed/storage/kvstore/include +-iwithprefixbefore/mbed/storage/kvstore/include/kvstore +-iwithprefixbefore/mbed/storage/kvstore/kv_config +-iwithprefixbefore/mbed/storage/kvstore/kv_config/include +-iwithprefixbefore/mbed/storage/kvstore/kv_config/include/kv_config +-iwithprefixbefore/mbed/storage/kvstore/kvstore_global_api +-iwithprefixbefore/mbed/storage/kvstore/kvstore_global_api/include +-iwithprefixbefore/mbed/storage/kvstore/kvstore_global_api/include/kvstore_global_api +-iwithprefixbefore/mbed/storage/kvstore/securestore +-iwithprefixbefore/mbed/storage/kvstore/securestore/include +-iwithprefixbefore/mbed/storage/kvstore/securestore/include/securestore +-iwithprefixbefore/mbed/storage/kvstore/tdbstore +-iwithprefixbefore/mbed/storage/kvstore/tdbstore/include +-iwithprefixbefore/mbed/storage/kvstore/tdbstore/include/tdbstore +-iwithprefixbefore/mbed/targets/TARGET_STM +-iwithprefixbefore/mbed/targets/TARGET_STM/TARGET_STM32H7 +-iwithprefixbefore/mbed/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW +-iwithprefixbefore/mbed/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS +-iwithprefixbefore/mbed/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver +-iwithprefixbefore/mbed/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy +-iwithprefixbefore/mbed/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4 diff --git a/variants/PORTENTA_H7_M4/ldflags.txt b/variants/GENERIC_STM32H747_M4/ldflags.txt similarity index 89% rename from variants/PORTENTA_H7_M4/ldflags.txt rename to variants/GENERIC_STM32H747_M4/ldflags.txt index e3666931b..914e1deff 100644 --- a/variants/PORTENTA_H7_M4/ldflags.txt +++ b/variants/GENERIC_STM32H747_M4/ldflags.txt @@ -1,8 +1,6 @@ -DMBED_APP_SIZE=0x100000 -DMBED_APP_START=0x8100000 -DMBED_BOOT_STACK_SIZE=1024 --DMBED_RAM1_SIZE=0x80000 --DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x48000 -DMBED_RAM_START=0x10000000 -DMBED_ROM_SIZE=0x100000 diff --git a/variants/PORTENTA_H7_M4/libs/libmbed.a b/variants/GENERIC_STM32H747_M4/libs/libmbed.a similarity index 91% rename from variants/PORTENTA_H7_M4/libs/libmbed.a rename to variants/GENERIC_STM32H747_M4/libs/libmbed.a index 297d3dfdd..821d7694b 100644 Binary files a/variants/PORTENTA_H7_M4/libs/libmbed.a and b/variants/GENERIC_STM32H747_M4/libs/libmbed.a differ diff --git a/variants/PORTENTA_H7_M4/linker_script.ld b/variants/GENERIC_STM32H747_M4/linker_script.ld similarity index 100% rename from variants/PORTENTA_H7_M4/linker_script.ld rename to variants/GENERIC_STM32H747_M4/linker_script.ld diff --git a/variants/PORTENTA_H7_M4/mbed_config.h b/variants/GENERIC_STM32H747_M4/mbed_config.h similarity index 98% rename from variants/PORTENTA_H7_M4/mbed_config.h rename to variants/GENERIC_STM32H747_M4/mbed_config.h index 20f47ae62..7b2806692 100644 --- a/variants/PORTENTA_H7_M4/mbed_config.h +++ b/variants/GENERIC_STM32H747_M4/mbed_config.h @@ -47,16 +47,15 @@ #define BLE_SECURITY_DATABASE_FILESYSTEM 1 // set by library:ble #define BLE_SECURITY_DATABASE_KVSTORE 0 // set by library:ble #define BLE_SECURITY_DATABASE_MAX_ENTRIES 5 // set by library:ble -#define CLOCK_SOURCE USE_PLL_HSE_EXTC // set by target:PORTENTA_H7 +#define CLOCK_SOURCE USE_PLL_HSI // set by target:GENERIC_STM32H747_M4 #define DM_CONN_MAX 5 // set by application[*] #define DM_NUM_ADV_SETS 3 // set by library:cordio #define DM_NUM_PHYS 3 // set by library:cordio #define DM_SYNC_MAX 1 // set by library:cordio #define EATT_CONN_CHAN_MAX 1 // set by library:cordio -#define HSE_VALUE 25000000 // set by target:PORTENTA_H7 #define L2C_COC_CHAN_MAX 1 // set by library:cordio #define L2C_COC_REG_MAX 1 // set by library:cordio -#define LPTICKER_DELAY_TICKS 0 // set by target:PORTENTA_H7 +#define LPTICKER_DELAY_TICKS 0 // set by target:GENERIC_STM32H747_M4 #define MBED_ALL_STATS_ENABLED 1 // set by application[*] #define MBED_CONF_ALT1250_PPP_BAUDRATE 115200 // set by library:ALT1250_PPP #define MBED_CONF_ALT1250_PPP_PROVIDE_DEFAULT 0 // set by library:ALT1250_PPP @@ -214,7 +213,7 @@ #define MBED_CONF_LWIP_MBOX_SIZE 8 // set by library:lwip #define MBED_CONF_LWIP_MEMP_NUM_TCPIP_MSG_INPKT 8 // set by library:lwip #define MBED_CONF_LWIP_MEMP_NUM_TCP_SEG 16 // set by library:lwip -#define MBED_CONF_LWIP_MEM_SIZE 16000 // set by library:lwip[PORTENTA_H7] +#define MBED_CONF_LWIP_MEM_SIZE 2310 // set by library:lwip[STM] #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip #define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip @@ -375,19 +374,17 @@ #define MBED_CONF_TARGET_DEEP_SLEEP_LATENCY 4 // set by target:MCU_STM32 #define MBED_CONF_TARGET_DEFAULT_ADC_VREF NAN // set by target:Target #define MBED_CONF_TARGET_GPIO_RESET_AT_INIT 0 // set by target:MCU_STM32 -#define MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO 1 // set by target:PORTENTA_H7 +#define MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO 1 // set by target:GENERIC_STM32H747_M4 #define MBED_CONF_TARGET_INIT_US_TICKER_AT_BOOT 1 // set by target:MCU_STM32 #define MBED_CONF_TARGET_INTERNAL_FLASH_UNIFORM_SECTORS 1 // set by target:Target #define MBED_CONF_TARGET_LPTICKER_LPTIM 1 // set by target:MCU_STM32H7 #define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:MCU_STM32 #define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1|USE_LPUART_CLK_PCLK3 // set by target:MCU_STM32 #define MBED_CONF_TARGET_LSE_AVAILABLE 0 // set by application[*] -#define MBED_CONF_TARGET_LSE_BYPASS 1 // set by target:PORTENTA_H7 #define MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW // set by target:MCU_STM32H7 #define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target -#define MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE ETHERNET // set by target:PORTENTA_H7 #define MBED_CONF_TARGET_RTC_CLOCK_SOURCE USE_RTC_CLK_LSE_OR_LSI // set by target:MCU_STM32 -#define MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY PWR_SMPS_1V8_SUPPLIES_LDO // set by target:PORTENTA_H7 +#define MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY PWR_LDO_SUPPLY // set by target:GENERIC_STM32H747_M4 #define MBED_CONF_TARGET_TICKLESS_FROM_US_TICKER 0 // set by target:Target #define MBED_CONF_TARGET_USB_SPEED USE_USB_OTG_FS // set by application[*] #define MBED_CONF_TARGET_XIP_ENABLE 0 // set by target:Target diff --git a/variants/PORTENTA_H7_M4/pinmode_arduino.h b/variants/GENERIC_STM32H747_M4/pinmode_arduino.h similarity index 100% rename from variants/PORTENTA_H7_M4/pinmode_arduino.h rename to variants/GENERIC_STM32H747_M4/pinmode_arduino.h diff --git a/variants/PORTENTA_H7_M4/pins_arduino.h b/variants/GENERIC_STM32H747_M4/pins_arduino.h similarity index 100% rename from variants/PORTENTA_H7_M4/pins_arduino.h rename to variants/GENERIC_STM32H747_M4/pins_arduino.h diff --git a/variants/PORTENTA_H7_M4/variant.cpp b/variants/GENERIC_STM32H747_M4/variant.cpp similarity index 100% rename from variants/PORTENTA_H7_M4/variant.cpp rename to variants/GENERIC_STM32H747_M4/variant.cpp diff --git a/variants/GIGA/variant.cpp b/variants/GIGA/variant.cpp index f2c9836d5..31038f320 100644 --- a/variants/GIGA/variant.cpp +++ b/variants/GIGA/variant.cpp @@ -162,16 +162,6 @@ extern "C" { } } -#include "drivers/I2C.h" - -void fixup3V1Rail() { - mbed::I2C i2c(PB_7, PB_6); - char data[2]; - data[0]=0x42; - data[1]=(1); - i2c.write(8 << 1, data, sizeof(data)); -} - void initVariant() { RTCHandle.Instance = RTC; // Turn off LED from bootloader diff --git a/variants/PORTENTA_H7_M4/includes.txt b/variants/PORTENTA_H7_M4/includes.txt deleted file mode 100644 index 14ff31f31..000000000 --- a/variants/PORTENTA_H7_M4/includes.txt +++ /dev/null @@ -1,286 +0,0 @@ --iwithprefixbefore/mbed --iwithprefixbefore/mbed/cmsis --iwithprefixbefore/mbed/cmsis/CMSIS_5 --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2 --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/Include --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Config --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Include --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Include1 --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/TARGET_CORTEX_M --iwithprefixbefore/mbed/cmsis/CMSIS_5/CMSIS/TARGET_CORTEX_M/Include --iwithprefixbefore/mbed/cmsis/device --iwithprefixbefore/mbed/cmsis/device/RTE --iwithprefixbefore/mbed/cmsis/device/RTE/include --iwithprefixbefore/mbed/cmsis/device/rtos --iwithprefixbefore/mbed/cmsis/device/rtos/include --iwithprefixbefore/mbed/connectivity --iwithprefixbefore/mbed/connectivity/FEATURE_BLE --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/common --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/compatibility --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/compatibility/ble --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/driver --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/gap --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/gatt --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/include/ble/services --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/include --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/hci --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/hci/dual_chip --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/sec --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/sec/common --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/att --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/cfg --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/dm --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/hci --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/l2c --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/smp --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/platform --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/platform/include --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/wsf --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/wsf/include --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/libraries/cordio_stack/wsf/include/util --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/source --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/source/common --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/source/cordio --iwithprefixbefore/mbed/connectivity/FEATURE_BLE/source/cordio/source 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