Skip to content

Commit 62031b8

Browse files
Jan Petrous (OSS)NipaLocal
Jan Petrous (OSS)
authored and
NipaLocal
committed
net: stmmac: dwmac-s32: add basic NXP S32G/S32R glue driver
NXP S32G2xx/S32G3xx and S32R45 are automotive grade SoCs that integrate one or two Synopsys DWMAC 5.10/5.20 IPs. The basic driver supports only RGMII interface. Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> Signed-off-by: NipaLocal <nipa@local>
1 parent 4211fd8 commit 62031b8

File tree

3 files changed

+217
-0
lines changed

3 files changed

+217
-0
lines changed

‎drivers/net/ethernet/stmicro/stmmac/Kconfig

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,18 @@ config DWMAC_RZN1
154154
the stmmac device driver. This support can make use of a custom MII
155155
converter PCS device.
156156

157+
config DWMAC_S32
158+
tristate "NXP S32G/S32R GMAC support"
159+
default ARCH_S32
160+
depends on OF && (ARCH_S32 || COMPILE_TEST)
161+
help
162+
Support for ethernet controller on NXP S32CC SOCs.
163+
164+
This selects NXP SoC glue layer support for the stmmac
165+
device driver. This driver is used for the S32CC series
166+
SOCs GMAC ethernet controller, ie. S32G2xx, S32G3xx and
167+
S32R45.
168+
157169
config DWMAC_SOCFPGA
158170
tristate "SOCFPGA dwmac support"
159171
default ARCH_INTEL_SOCFPGA

‎drivers/net/ethernet/stmicro/stmmac/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
2222
obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o
2323
obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
2424
obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o
25+
obj-$(CONFIG_DWMAC_S32) += dwmac-s32.o
2526
obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
2627
obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o
2728
obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o

‎drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c

Lines changed: 204 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,204 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* NXP S32G/R GMAC glue layer
4+
*
5+
* Copyright 2019-2024 NXP
6+
*
7+
*/
8+
9+
#include <linux/clk.h>
10+
#include <linux/clk-provider.h>
11+
#include <linux/device.h>
12+
#include <linux/ethtool.h>
13+
#include <linux/io.h>
14+
#include <linux/module.h>
15+
#include <linux/of_mdio.h>
16+
#include <linux/of_address.h>
17+
#include <linux/phy.h>
18+
#include <linux/phylink.h>
19+
#include <linux/platform_device.h>
20+
#include <linux/stmmac.h>
21+
22+
#include "stmmac_platform.h"
23+
24+
#define GMAC_TX_RATE_125M 125000000 /* 125MHz */
25+
26+
/* SoC PHY interface control register */
27+
#define PHY_INTF_SEL_MII 0x00
28+
#define PHY_INTF_SEL_SGMII 0x01
29+
#define PHY_INTF_SEL_RGMII 0x02
30+
#define PHY_INTF_SEL_RMII 0x08
31+
32+
struct s32_priv_data {
33+
void __iomem *ioaddr;
34+
void __iomem *ctrl_sts;
35+
struct device *dev;
36+
phy_interface_t intf_mode;
37+
struct clk *tx_clk;
38+
struct clk *rx_clk;
39+
};
40+
41+
static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac)
42+
{
43+
u32 intf_sel;
44+
45+
switch (gmac->intf_mode) {
46+
case PHY_INTERFACE_MODE_RGMII:
47+
case PHY_INTERFACE_MODE_RGMII_ID:
48+
case PHY_INTERFACE_MODE_RGMII_TXID:
49+
case PHY_INTERFACE_MODE_RGMII_RXID:
50+
intf_sel = PHY_INTF_SEL_RGMII;
51+
break;
52+
default:
53+
dev_err(gmac->dev, "Unsupported PHY interface: %s\n",
54+
phy_modes(gmac->intf_mode));
55+
return -EINVAL;
56+
}
57+
58+
writel(intf_sel, gmac->ctrl_sts);
59+
60+
dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(gmac->intf_mode));
61+
62+
return 0;
63+
}
64+
65+
static int s32_gmac_init(struct platform_device *pdev, void *priv)
66+
{
67+
struct s32_priv_data *gmac = priv;
68+
int ret;
69+
70+
ret = clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_125M);
71+
if (!ret)
72+
ret = clk_prepare_enable(gmac->tx_clk);
73+
74+
if (ret) {
75+
dev_err(&pdev->dev, "Can't set tx clock\n");
76+
return ret;
77+
}
78+
79+
ret = clk_prepare_enable(gmac->rx_clk);
80+
if (ret) {
81+
clk_disable_unprepare(gmac->tx_clk);
82+
dev_err(&pdev->dev, "Can't set rx clock\n");
83+
return ret;
84+
}
85+
86+
ret = s32_gmac_write_phy_intf_select(gmac);
87+
if (ret) {
88+
clk_disable_unprepare(gmac->tx_clk);
89+
clk_disable_unprepare(gmac->rx_clk);
90+
dev_err(&pdev->dev, "Can't set PHY interface mode\n");
91+
return ret;
92+
}
93+
94+
return 0;
95+
}
96+
97+
static void s32_gmac_exit(struct platform_device *pdev, void *priv)
98+
{
99+
struct s32_priv_data *gmac = priv;
100+
101+
clk_disable_unprepare(gmac->tx_clk);
102+
clk_disable_unprepare(gmac->rx_clk);
103+
}
104+
105+
static void s32_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
106+
{
107+
struct s32_priv_data *gmac = priv;
108+
long tx_clk_rate;
109+
int ret;
110+
111+
tx_clk_rate = rgmii_clock(speed);
112+
if (tx_clk_rate < 0) {
113+
dev_err(gmac->dev, "Unsupported/Invalid speed: %d\n", speed);
114+
return;
115+
}
116+
117+
dev_dbg(gmac->dev, "Set tx clock to %ld Hz\n", tx_clk_rate);
118+
ret = clk_set_rate(gmac->tx_clk, tx_clk_rate);
119+
if (ret)
120+
dev_err(gmac->dev, "Can't set tx clock\n");
121+
}
122+
123+
static int s32_dwmac_probe(struct platform_device *pdev)
124+
{
125+
struct plat_stmmacenet_data *plat;
126+
struct device *dev = &pdev->dev;
127+
struct stmmac_resources res;
128+
struct s32_priv_data *gmac;
129+
int ret;
130+
131+
gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL);
132+
if (!gmac)
133+
return -ENOMEM;
134+
135+
gmac->dev = &pdev->dev;
136+
137+
ret = stmmac_get_platform_resources(pdev, &res);
138+
if (ret)
139+
return dev_err_probe(dev, ret,
140+
"Failed to get platform resources\n");
141+
142+
plat = devm_stmmac_probe_config_dt(pdev, res.mac);
143+
if (IS_ERR(plat))
144+
return dev_err_probe(dev, PTR_ERR(plat),
145+
"dt configuration failed\n");
146+
147+
/* PHY interface mode control reg */
148+
gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
149+
if (IS_ERR(gmac->ctrl_sts))
150+
return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts),
151+
"S32CC config region is missing\n");
152+
153+
/* tx clock */
154+
gmac->tx_clk = devm_clk_get(&pdev->dev, "tx");
155+
if (IS_ERR(gmac->tx_clk))
156+
return dev_err_probe(dev, PTR_ERR(gmac->tx_clk),
157+
"tx clock not found\n");
158+
159+
/* rx clock */
160+
gmac->rx_clk = devm_clk_get(&pdev->dev, "rx");
161+
if (IS_ERR(gmac->rx_clk))
162+
return dev_err_probe(dev, PTR_ERR(gmac->rx_clk),
163+
"rx clock not found\n");
164+
165+
gmac->intf_mode = plat->phy_interface;
166+
gmac->ioaddr = res.addr;
167+
168+
/* S32CC core feature set */
169+
plat->has_gmac4 = true;
170+
plat->pmt = 1;
171+
plat->flags |= STMMAC_FLAG_SPH_DISABLE;
172+
plat->rx_fifo_size = 20480;
173+
plat->tx_fifo_size = 20480;
174+
175+
plat->init = s32_gmac_init;
176+
plat->exit = s32_gmac_exit;
177+
plat->fix_mac_speed = s32_fix_mac_speed;
178+
179+
plat->bsp_priv = gmac;
180+
181+
return stmmac_pltfr_probe(pdev, plat, &res);
182+
}
183+
184+
static const struct of_device_id s32_dwmac_match[] = {
185+
{ .compatible = "nxp,s32g2-dwmac" },
186+
{ }
187+
};
188+
MODULE_DEVICE_TABLE(of, s32_dwmac_match);
189+
190+
static struct platform_driver s32_dwmac_driver = {
191+
.probe = s32_dwmac_probe,
192+
.remove = stmmac_pltfr_remove,
193+
.driver = {
194+
.name = "s32-dwmac",
195+
.pm = &stmmac_pltfr_pm_ops,
196+
.of_match_table = s32_dwmac_match,
197+
},
198+
};
199+
module_platform_driver(s32_dwmac_driver);
200+
201+
MODULE_AUTHOR("Jan Petrous (OSS) <jan.petrous@oss.nxp.com>");
202+
MODULE_DESCRIPTION("NXP S32G/R common chassis GMAC driver");
203+
MODULE_LICENSE("GPL");
204+

0 commit comments

Comments
 (0)