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Minimal USART Driver (#6)
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‎minimal_drivers/README.md

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@@ -4,13 +4,18 @@
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- [Pre-requisites](#pre-requisites)
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- [GPIO](#gpio)
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- [Changelog](#changelog)
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- [L0 Layer - Controller](#l0-layer---controller)
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- [Global](#global)
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- [Utility](#utility)
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- [STM32L475xx](#stm32l475xx)
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- [L2 Layer - Utilities](#l2-layer---utilities)
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- [Own implementation](#own-implementation)
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- [Crates.io](#cratesio)
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- [L3 Layer - Interfaces](#l3-layer---interfaces)
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- [Rust interfaces used](#rust-interfaces-used)
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- [L3 Layer - Drivers](#l3-layer---drivers)
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- [L3 Layer - Miscellaneous](#l3-layer---miscellaneous)
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- [L4](#l4)
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- [L4 Sensor / Actuator](#l4-sensor--actuator)
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# Minimal Drivers
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@@ -40,6 +45,26 @@ This code has been tested on
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- L4 Sensor
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- L5 Application
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```
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application v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l5)
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├── l0 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l0)
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│ [build-dependencies]
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│ └── bindgen v0.63.0
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├── l3 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l3)
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│ ├── l0 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l0) (*)
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│ └── l2 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l2)
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└── l4 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l4)
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└── l3 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l3) (*)
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l0 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l0) (*)
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l2 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l2) (*)
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l3 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l3) (*)
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l4 v0.1.0 (D:\Repositories\lowlevel_rust\minimal_drivers\l4) (*)
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```
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## Pre-requisites
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- Pre-requisites from `minimal_controller_peripheral`
@@ -60,7 +85,7 @@ This code has been tested on
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graph BT;
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subgraph Port
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GPIOA-H
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subgraph Periphal
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subgraph Peripheral
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GPIO
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subgraph Register
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MODER
@@ -73,9 +98,27 @@ graph BT;
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end
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end
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```
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# Changelog
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## L0 Layer - Controller
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105+
### Global
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- System Clock
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- Every microcontroller will have a system clock in Hz
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110+
### Utility
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112+
- Common macros for port and register access
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- `get_port!`
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- `read_register!`
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- `write_register!`
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117+
### STM32L475xx
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- Controller initialization
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- For now it just updates the System Clock so that it can be used by upper layer (drivers etc)
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79122
## L2 Layer - Utilities
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81124
### Own implementation
@@ -89,23 +132,29 @@ graph BT;
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- GpioIn
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- GpioOut
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- UsartIn
92-
- UsartOut
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- UsartInOut
94-
- Port
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- Generic interface that creates a port using base address and peripheral register layout
96-
- In C it would be the equivalent of `GPIO_TypeDef * gpio = (GPIO_TypeDef *)BASE_ADDRESS`
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137+
### Rust interfaces used
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139+
- Write
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- Used instead of creating out own UsartOut interface
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98142
## L3 Layer - Drivers
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100144
- RCC
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- GPIO
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- [x] Input
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- [x] Output
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- USART
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- [x] Read
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- [x] Write
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103152
## L3 Layer - Miscellaneous
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105154
- Singleton
106155
- Safe access to global ports
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108-
## L4
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## L4 Sensor / Actuator
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110159
- Led
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- Button

‎minimal_drivers/l0/build.rs

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@@ -16,6 +16,8 @@ fn parse_header(input_filename: &str, output_path: &PathBuf) {
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.wrap_unsafe_ops(true)
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.translate_enum_integer_types(true)
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.explicit_padding(false)
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.generate_block(true)
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.default_enum_style(bindgen::EnumVariation::ModuleConsts)
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.parse_callbacks(Box::new(bindgen::CargoCallbacks))
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.generate()
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.expect("Unable to generate bindings");
@@ -35,6 +37,9 @@ fn main() {
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};
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// TODO, Make this user configurable to support multiple microcontroller formats
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// NOTE, This controller.rs contains both
41+
// - Architecture considerations (ARM specific peripherals)
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// - Microcontroller considerations (STM32 specific peripherals)
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const PARSE_INPUT_FILE: &str = "device/controller/stm32l475xx.h";
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const OUTPUT_FILE: &str = "src/controller.rs";
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if should_parse {

‎minimal_drivers/l0/src/entry_point.rs

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use crate::chip::controller_init;
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13
#[link_section = ".vector_table.reset_vector"]
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#[no_mangle]
35
pub static RESET_VECTOR: unsafe extern "C" fn() -> ! = Reset;
46

57
// NOTE, All the externed modules come here
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#[no_mangle]
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pub unsafe extern "C" fn Reset() -> ! {
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// Data and BSS sections
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extern "C" {
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// .data section
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static mut __data_end__: u8;
@@ -16,24 +19,30 @@ pub unsafe extern "C" fn Reset() -> ! {
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static mut __bss_end__: u8;
1720
}
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19-
// data
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// Copy from VMA to LMA
2023
let vma_data_end = &__data_end__ as *const u8;
2124
let vma_data_start = &__data_start__ as *const u8;
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let lma_data_start = &__etext as *const u8;
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let count: usize = vma_data_end as usize - vma_data_start as usize;
2427
// core::ptr::copy_nonoverlapping(lma_data_start, &mut __data_start__ as *mut u8, count);
2528
core::ptr::copy_nonoverlapping(lma_data_start, vma_data_start as *mut u8, count);
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27-
// end
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// Write 0 to .bss section
2831
let bss_end = &__bss_end__ as *const u8;
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let bss_start = &__bss_start__ as *const u8;
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let count = bss_end as usize - bss_start as usize;
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// core::ptr::write_bytes(&mut __bss_start__ as *mut u8, 0, count);
3235
core::ptr::write_bytes(bss_start as *mut u8, 0, count);
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37+
// Controller level startup system initialization
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39+
// Jump to L0 controller system init
40+
// TODO, Jump to L4 board init
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// Jump to L5 main function
3442
extern "Rust" {
3543
fn main() -> !;
3644
}
45+
controller_init();
3746
main();
3847
}
3948

@@ -68,7 +77,7 @@ pub static EXCEPTIONS: [Vector; 14] = [
6877
Vector { reserved: 0 },
6978
Vector { reserved: 0 },
7079
Vector { handler: SVCall },
71-
Vector { reserved: 0 },
80+
Vector { reserved: 0 }, // Debug Monitor Handler comes here
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Vector { reserved: 0 },
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Vector { handler: PendSV },
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Vector { handler: SysTick },

‎minimal_drivers/l0/src/global.rs

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use core::sync::atomic::AtomicU32;
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pub static SYSTEM_CLOCK: AtomicU32 = AtomicU32::new(4_000_000);
4+
5+
pub fn get_system_clock() -> u32 {
6+
use core::sync::atomic::Ordering;
7+
SYSTEM_CLOCK.load(Ordering::SeqCst)
8+
}

‎minimal_drivers/l0/src/lib.rs

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#![allow(non_camel_case_types)]
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#![allow(non_snake_case)]
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// * Private to l0
1112
mod entry_point;
13+
mod global;
1214
mod rust_entry_point;
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14-
// Generated controller bindings
15-
mod controller;
16-
pub use controller::*;
16+
// TODO, Add features
17+
// #[cfg(feature = "stm32l475xx")]
18+
mod stm32l475xx;
19+
use stm32l475xx as chip;
20+
21+
// * Public APIs usable when l0 is a dependency
22+
mod utility; // Macro export makes macros always public
23+
pub use global::get_system_clock;
24+
25+
// Generated controller bindings from C to Rust
26+
pub mod controller;
27+
28+
// Whats the difference between the chip module and controller module
29+
// controller.rs contains bindings for ARM Architecture + Chip specific peripheral structs (STM32L475xx)
30+
// chip.rs contains only Chip specific functionality (STM32L475xx)

‎minimal_drivers/l0/src/stm32l475xx/mod.rs

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mod private;
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pub use private::*;

‎minimal_drivers/l0/src/stm32l475xx/private.rs

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use crate::{get_port, global::SYSTEM_CLOCK, read_register};
2+
use core::ptr::read_volatile;
3+
use core::sync::atomic::Ordering;
4+
5+
use crate::controller::{RCC_TypeDef, RCC_BASE};
6+
7+
pub fn controller_init() {
8+
// Update the System clock
9+
let rcc_port = get_port!(RCC_TypeDef, RCC_BASE);
10+
let cr_data = read_register!(rcc_port.CR);
11+
let msi_range = (cr_data >> 4) & 0xF;
12+
let system_clock: u32 = match msi_range {
13+
0 => todo!(),
14+
1 => todo!(),
15+
2 => todo!(),
16+
3 => todo!(),
17+
4 => 1_000_000,
18+
5 => 2_000_000,
19+
6 => 4_000_000,
20+
7 => todo!(),
21+
8 => todo!(),
22+
9 => todo!(),
23+
10 => todo!(),
24+
11 => todo!(),
25+
_ => unreachable!(),
26+
};
27+
SYSTEM_CLOCK.store(system_clock, Ordering::SeqCst)
28+
29+
// TODO, Do more things
30+
}

‎minimal_drivers/l0/src/utility/mod.rs

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#[macro_export]
2+
macro_rules! get_port {
3+
($register_map_struct:ident, $address:ident) => {
4+
unsafe { &mut *($address as *mut $register_map_struct) }
5+
};
6+
}
7+
8+
#[macro_export]
9+
macro_rules! read_register {
10+
($register:expr) => {
11+
unsafe { read_volatile(&$register) }
12+
};
13+
}
14+
15+
// TODO, Overload this macro to support $data:literal
16+
#[macro_export]
17+
macro_rules! write_register {
18+
($register:expr, $data:expr) => {
19+
unsafe { write_volatile(&mut $register, $data) }
20+
};
21+
}

‎minimal_drivers/l2/Cargo.toml

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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
99

1010
[dependencies]
11-
l0 = { path = "../l0" }
1211
# Add libraries here
1312
bitflags = "1.3.2"

‎minimal_drivers/l3/src/interfaces/generic_interface.rs

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1-
pub trait Port<T, const B: u32> {
2-
fn get_port(&self) -> &'static mut T {
3-
let mutable_ref = unsafe { &mut *(B as *mut T) };
4-
mutable_ref
5-
}
6-
}
7-
81
pub trait PeripheralConfiguration {
92
type Config;
103
type Register;

‎minimal_drivers/l3/src/interfaces/mod.rs

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44
pub mod gpio_interface;
55
pub use gpio_interface::*;
66

7+
pub mod usart_interface;
8+
pub use usart_interface::*;
9+
710
pub mod utility_interface;
811
pub use utility_interface::*;

‎minimal_drivers/l3/src/interfaces/usart_interface.rs

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1+
use core::fmt::Write;
2+
3+
// * Instead of having an `UsartOut` trait, we can use the Rust core library `core::fmt::Write` trait
4+
5+
pub trait UsartIn {
6+
fn read_character(&mut self) -> char;
7+
}
8+
9+
pub trait UsartInOut: UsartIn + Write {}

‎minimal_drivers/l3/src/lib.rs

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33
mod interfaces;
44
pub use interfaces::*;
55

6-
pub mod peripheral;
7-
pub use peripheral::*;
6+
pub mod singleton;
7+
pub use singleton::*;
88

99
// TODO, Add features
1010
// #[cfg(feature = "stm32l475xx")]

‎minimal_drivers/l3/src/peripheral.rs renamed to ‎minimal_drivers/l3/src/singleton.rs

File renamed without changes.

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