diff --git a/minimal_interrupt/gcc_arm.ld b/minimal_interrupt/gcc_arm.ld
index e43c9cd..5460960 100644
--- a/minimal_interrupt/gcc_arm.ld
+++ b/minimal_interrupt/gcc_arm.ld
@@ -327,3 +327,97 @@ SECTIONS
   /* Check if data + heap + stack exceeds RAM limit */
   ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
 }
+
+/* Exceptions */
+PROVIDE(NMI = DefaultExceptionHandler);
+PROVIDE(HardFault = DefaultExceptionHandler);
+PROVIDE(MemManage = DefaultExceptionHandler);
+PROVIDE(BusFault = DefaultExceptionHandler);
+PROVIDE(UsageFault = DefaultExceptionHandler);
+PROVIDE(SVCall = DefaultExceptionHandler);
+PROVIDE(PendSV = DefaultExceptionHandler);
+PROVIDE(SysTick = DefaultExceptionHandler);
+
+/* Interrupts */
+PROVIDE(WWDG_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(PVD_PVM_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(RTC_TAMP_STAMP_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(RTC_WKUP_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(FLASH_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(RCC_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(EXTI0_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(EXTI1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(EXTI2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(EXTI3_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(EXTI4_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA1_CH1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA1_CH2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA1_CH3_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA1_CH4_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA1_CH5_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA1_CH6_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA1_CH7_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(ADC1_2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(CAN1_TX_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(CAN1_RX0_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(CAN1_RX1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(CAN1_SCE_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(EXTI9_5_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM1_BRK_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM1_UP_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM1_TRG_COM_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM1_CC_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM3_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM4_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(I2C1_EV_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(I2C1_ER_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(I2C2_EV_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(I2C2_ER_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(SPI1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(SPI2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(USART1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(USART2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(USART3_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(EXTI15_10_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(RTC_ALARM_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DFSDM1_FLT3_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM8_BRK_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM8_UP_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM8_TRG_COM_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM8_CC_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(ADC3_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(FMC_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(SDMMC1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM5_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(SPI3_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(UART4_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(UART5_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM6_DAC_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TIM7_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA2_CH1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA2_CH2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA2_CH3_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA2_CH4_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA2_CH5_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DFSDM1_FLT0_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DFSDM1_FLT1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DFSDM1_FLT2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(COMP_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(LPTIM1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(LPTIM2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(OTG_FS_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA2_CH6_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(DMA2_CH7_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(LPUART1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(QUADSPI_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(I2C3_EV_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(I2C3_ER_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(SAI1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(SAI2_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(SWPMI1_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(TSC_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(LCD_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(AES_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(RNG_Interrupt_Handler = DefaultExceptionHandler);
+PROVIDE(FPU_Interrupt_Handler = DefaultExceptionHandler);
diff --git a/minimal_interrupt/l0/src/stm32l475xx/entry_point.rs b/minimal_interrupt/l0/src/stm32l475xx/entry_point.rs
index cd2a3f7..443773a 100644
--- a/minimal_interrupt/l0/src/stm32l475xx/entry_point.rs
+++ b/minimal_interrupt/l0/src/stm32l475xx/entry_point.rs
@@ -43,7 +43,15 @@ pub unsafe extern "C" fn Reset() {
 }
 
 extern "C" {
-    fn __StackTop();
+    fn __StackTop(); // Check `gcc_arm.ld`
+    fn NMI();
+    fn HardFault();
+    fn MemManage();
+    fn BusFault();
+    fn UsageFault();
+    fn SVCall();
+    fn PendSV();
+    fn SysTick();
 }
 
 #[repr(C)]
@@ -59,38 +67,22 @@ pub static EXCEPTIONS: [Vector; 16] = [
         handler: __StackTop,
     },
     Vector { handler: Reset },
+    Vector { handler: NMI },
+    Vector { handler: HardFault },
+    Vector { handler: MemManage },
+    Vector { handler: BusFault },
     Vector {
-        handler: DefaultExceptionHandler,
-    }, // NMI
-    Vector {
-        handler: DefaultExceptionHandler,
-    }, // HardFault
-    Vector {
-        handler: DefaultExceptionHandler,
-    }, // MemManage
-    Vector {
-        handler: DefaultExceptionHandler,
-    }, // BusFault
-    Vector {
-        handler: DefaultExceptionHandler,
-    }, // UsageFault
+        handler: UsageFault,
+    },
     Vector { reserved: 0 },
     Vector { reserved: 0 },
     Vector { reserved: 0 },
     Vector { reserved: 0 },
-    Vector {
-        handler: DefaultExceptionHandler,
-    }, // SVCall
-    Vector {
-        handler: DefaultExceptionHandler,
-    }, // Debug
+    Vector { handler: SVCall },
+    Vector { reserved: 0 }, // Debug Monitor Handler comes here
     Vector { reserved: 0 },
-    Vector {
-        handler: DefaultExceptionHandler,
-    }, // PendSV
-    Vector {
-        handler: DefaultExceptionHandler,
-    }, // SysTick
+    Vector { handler: PendSV },
+    Vector { handler: SysTick },
 ];
 
 #[no_mangle]
diff --git a/minimal_interrupt/l0/src/stm32l475xx/interrupt.rs b/minimal_interrupt/l0/src/stm32l475xx/interrupt.rs
index 675699d..c93c95b 100644
--- a/minimal_interrupt/l0/src/stm32l475xx/interrupt.rs
+++ b/minimal_interrupt/l0/src/stm32l475xx/interrupt.rs
@@ -1,5 +1,3 @@
-use crate::{read_register, SCB_PORT};
-
 #[derive(Copy, Clone)]
 pub enum Interrupt {
     WWDG,
@@ -86,25 +84,174 @@ pub enum Interrupt {
     FPU,
 }
 
-static mut MY_INTERRUPTS: [fn(); 82] = [|| loop {}; 82];
-pub fn attach_interrupt_handler(interrupt: Interrupt, handler: fn()) {
-    let index: usize = interrupt as usize;
-    unsafe {
-        MY_INTERRUPTS[index] = handler;
-    }
+extern "C" {
+    fn WWDG_Interrupt_Handler();
+    fn PVD_PVM_Interrupt_Handler();
+    fn RTC_TAMP_STAMP_Interrupt_Handler();
+    fn RTC_WKUP_Interrupt_Handler();
+    fn FLASH_Interrupt_Handler();
+    fn RCC_Interrupt_Handler();
+    fn EXTI0_Interrupt_Handler();
+    fn EXTI1_Interrupt_Handler();
+    fn EXTI2_Interrupt_Handler();
+    fn EXTI3_Interrupt_Handler();
+    fn EXTI4_Interrupt_Handler();
+    fn DMA1_CH1_Interrupt_Handler();
+    fn DMA1_CH2_Interrupt_Handler();
+    fn DMA1_CH3_Interrupt_Handler();
+    fn DMA1_CH4_Interrupt_Handler();
+    fn DMA1_CH5_Interrupt_Handler();
+    fn DMA1_CH6_Interrupt_Handler();
+    fn DMA1_CH7_Interrupt_Handler();
+    fn ADC1_2_Interrupt_Handler();
+    fn CAN1_TX_Interrupt_Handler();
+    fn CAN1_RX0_Interrupt_Handler();
+    fn CAN1_RX1_Interrupt_Handler();
+    fn CAN1_SCE_Interrupt_Handler();
+    fn EXTI9_5_Interrupt_Handler();
+    fn TIM1_BRK_Interrupt_Handler();
+    fn TIM1_UP_Interrupt_Handler();
+    fn TIM1_TRG_COM_Interrupt_Handler();
+    fn TIM1_CC_Interrupt_Handler();
+    fn TIM2_Interrupt_Handler();
+    fn TIM3_Interrupt_Handler();
+    fn TIM4_Interrupt_Handler();
+    fn I2C1_EV_Interrupt_Handler();
+    fn I2C1_ER_Interrupt_Handler();
+    fn I2C2_EV_Interrupt_Handler();
+    fn I2C2_ER_Interrupt_Handler();
+    fn SPI1_Interrupt_Handler();
+    fn SPI2_Interrupt_Handler();
+    fn USART1_Interrupt_Handler();
+    fn USART2_Interrupt_Handler();
+    fn USART3_Interrupt_Handler();
+    fn EXTI15_10_Interrupt_Handler();
+    fn RTC_ALARM_Interrupt_Handler();
+    fn DFSDM1_FLT3_Interrupt_Handler();
+    fn TIM8_BRK_Interrupt_Handler();
+    fn TIM8_UP_Interrupt_Handler();
+    fn TIM8_TRG_COM_Interrupt_Handler();
+    fn TIM8_CC_Interrupt_Handler();
+    fn ADC3_Interrupt_Handler();
+    fn FMC_Interrupt_Handler();
+    fn SDMMC1_Interrupt_Handler();
+    fn TIM5_Interrupt_Handler();
+    fn SPI3_Interrupt_Handler();
+    fn UART4_Interrupt_Handler();
+    fn UART5_Interrupt_Handler();
+    fn TIM6_DAC_Interrupt_Handler();
+    fn TIM7_Interrupt_Handler();
+    fn DMA2_CH1_Interrupt_Handler();
+    fn DMA2_CH2_Interrupt_Handler();
+    fn DMA2_CH3_Interrupt_Handler();
+    fn DMA2_CH4_Interrupt_Handler();
+    fn DMA2_CH5_Interrupt_Handler();
+    fn DFSDM1_FLT0_Interrupt_Handler();
+    fn DFSDM1_FLT1_Interrupt_Handler();
+    fn DFSDM1_FLT2_Interrupt_Handler();
+    fn COMP_Interrupt_Handler();
+    fn LPTIM1_Interrupt_Handler();
+    fn LPTIM2_Interrupt_Handler();
+    fn OTG_FS_Interrupt_Handler();
+    fn DMA2_CH6_Interrupt_Handler();
+    fn DMA2_CH7_Interrupt_Handler();
+    fn LPUART1_Interrupt_Handler();
+    fn QUADSPI_Interrupt_Handler();
+    fn I2C3_EV_Interrupt_Handler();
+    fn I2C3_ER_Interrupt_Handler();
+    fn SAI1_Interrupt_Handler();
+    fn SAI2_Interrupt_Handler();
+    fn SWPMI1_Interrupt_Handler();
+    fn TSC_Interrupt_Handler();
+    fn LCD_Interrupt_Handler();
+    fn AES_Interrupt_Handler();
+    fn RNG_Interrupt_Handler();
+    fn FPU_Interrupt_Handler();
 }
 
 #[link_section = ".vector_table.interrupts"]
 #[no_mangle]
-static INTERRUPTS: [unsafe extern "C" fn(); 82] = [DefaultInterruptHandler; 82];
-
-#[no_mangle]
-extern "C" fn DefaultInterruptHandler() {
-    let scb_port = SCB_PORT::port();
-    let irq_num = (read_register!(scb_port.ICSR) & 0xFF) - 16;
-    unsafe {
-        MY_INTERRUPTS
-            .get(irq_num as usize)
-            .expect("No interrupt registered")();
-    }
-}
+static INTERRUPTS: [unsafe extern "C" fn(); 82] = [
+    WWDG_Interrupt_Handler,
+    PVD_PVM_Interrupt_Handler,
+    RTC_TAMP_STAMP_Interrupt_Handler,
+    RTC_WKUP_Interrupt_Handler,
+    FLASH_Interrupt_Handler,
+    RCC_Interrupt_Handler,
+    EXTI0_Interrupt_Handler,
+    EXTI1_Interrupt_Handler,
+    EXTI2_Interrupt_Handler,
+    EXTI3_Interrupt_Handler,
+    EXTI4_Interrupt_Handler,
+    DMA1_CH1_Interrupt_Handler,
+    DMA1_CH2_Interrupt_Handler,
+    DMA1_CH3_Interrupt_Handler,
+    DMA1_CH4_Interrupt_Handler,
+    DMA1_CH5_Interrupt_Handler,
+    DMA1_CH6_Interrupt_Handler,
+    DMA1_CH7_Interrupt_Handler,
+    ADC1_2_Interrupt_Handler,
+    CAN1_TX_Interrupt_Handler,
+    CAN1_RX0_Interrupt_Handler,
+    CAN1_RX1_Interrupt_Handler,
+    CAN1_SCE_Interrupt_Handler,
+    EXTI9_5_Interrupt_Handler,
+    TIM1_BRK_Interrupt_Handler,
+    TIM1_UP_Interrupt_Handler,
+    TIM1_TRG_COM_Interrupt_Handler,
+    TIM1_CC_Interrupt_Handler,
+    TIM2_Interrupt_Handler,
+    TIM3_Interrupt_Handler,
+    TIM4_Interrupt_Handler,
+    I2C1_EV_Interrupt_Handler,
+    I2C1_ER_Interrupt_Handler,
+    I2C2_EV_Interrupt_Handler,
+    I2C2_ER_Interrupt_Handler,
+    SPI1_Interrupt_Handler,
+    SPI2_Interrupt_Handler,
+    USART1_Interrupt_Handler,
+    USART2_Interrupt_Handler,
+    USART3_Interrupt_Handler,
+    EXTI15_10_Interrupt_Handler,
+    RTC_ALARM_Interrupt_Handler,
+    DFSDM1_FLT3_Interrupt_Handler,
+    TIM8_BRK_Interrupt_Handler,
+    TIM8_UP_Interrupt_Handler,
+    TIM8_TRG_COM_Interrupt_Handler,
+    TIM8_CC_Interrupt_Handler,
+    ADC3_Interrupt_Handler,
+    FMC_Interrupt_Handler,
+    SDMMC1_Interrupt_Handler,
+    TIM5_Interrupt_Handler,
+    SPI3_Interrupt_Handler,
+    UART4_Interrupt_Handler,
+    UART5_Interrupt_Handler,
+    TIM6_DAC_Interrupt_Handler,
+    TIM7_Interrupt_Handler,
+    DMA2_CH1_Interrupt_Handler,
+    DMA2_CH2_Interrupt_Handler,
+    DMA2_CH3_Interrupt_Handler,
+    DMA2_CH4_Interrupt_Handler,
+    DMA2_CH5_Interrupt_Handler,
+    DFSDM1_FLT0_Interrupt_Handler,
+    DFSDM1_FLT1_Interrupt_Handler,
+    DFSDM1_FLT2_Interrupt_Handler,
+    COMP_Interrupt_Handler,
+    LPTIM1_Interrupt_Handler,
+    LPTIM2_Interrupt_Handler,
+    OTG_FS_Interrupt_Handler,
+    DMA2_CH6_Interrupt_Handler,
+    DMA2_CH7_Interrupt_Handler,
+    LPUART1_Interrupt_Handler,
+    QUADSPI_Interrupt_Handler,
+    I2C3_EV_Interrupt_Handler,
+    I2C3_ER_Interrupt_Handler,
+    SAI1_Interrupt_Handler,
+    SAI2_Interrupt_Handler,
+    SWPMI1_Interrupt_Handler,
+    TSC_Interrupt_Handler,
+    LCD_Interrupt_Handler,
+    AES_Interrupt_Handler,
+    RNG_Interrupt_Handler,
+    FPU_Interrupt_Handler,
+];
diff --git a/minimal_interrupt/l3/src/stm32l475xx/usart.rs b/minimal_interrupt/l3/src/stm32l475xx/usart.rs
index 6dbeac2..3b8f8be 100644
--- a/minimal_interrupt/l3/src/stm32l475xx/usart.rs
+++ b/minimal_interrupt/l3/src/stm32l475xx/usart.rs
@@ -144,13 +144,13 @@ impl UsartInOut for USARTPolledFunction {}
 
 /// USARTBufferedFunction
 
-pub struct USARTBufferedFunction {
+pub struct USARTBufferedFunction<const N: usize> {
     port: &'static mut USART_TypeDef,
-    rx: Option<&'static mut Queue<char, 128>>,
-    tx: Option<&'static mut Queue<char, 128>>,
+    rx: Option<&'static mut Queue<char, N>>,
+    tx: Option<&'static mut Queue<char, N>>,
 }
 
-impl USARTBufferedFunction {
+impl<const N: usize> USARTBufferedFunction<N> {
     fn via_configure(&mut self, config: &USARTConfig) {
         // Disable USART
         self.reset_cr1(USART_CR1::UE);
@@ -203,7 +203,7 @@ impl USARTBufferedFunction {
     }
 }
 
-impl UsartBufferedIn for USARTBufferedFunction {
+impl<const N: usize> UsartBufferedIn for USARTBufferedFunction<N> {
     fn size(&self) -> usize {
         match &self.rx {
             Some(rx) => rx.len(),
@@ -219,7 +219,7 @@ impl UsartBufferedIn for USARTBufferedFunction {
     }
 }
 
-impl Write for USARTBufferedFunction {
+impl<const N: usize> Write for USARTBufferedFunction<N> {
     fn write_str(&mut self, s: &str) -> core::fmt::Result {
         if let None = self.tx {
             return Err(core::fmt::Error);
@@ -241,7 +241,7 @@ impl Write for USARTBufferedFunction {
     }
 }
 
-impl UsartBufferedInOut for USARTBufferedFunction {}
+impl<const N: usize> UsartBufferedInOut for USARTBufferedFunction<N> {}
 
 /// USARTPeripheral
 
@@ -284,7 +284,10 @@ impl<const B: u32> USARTPeripheral<B> {
         usart
     }
 
-    pub fn configure_buffered_rx(&self, rx: &'static mut Queue<char, 128>) -> impl UsartBufferedIn {
+    pub fn configure_buffered_rx<const N: usize>(
+        &self,
+        rx: &'static mut Queue<char, N>,
+    ) -> impl UsartBufferedIn {
         Self::buffered_configure(
             &USARTConfig {
                 mode: USARTMode::RxTx,
@@ -297,7 +300,10 @@ impl<const B: u32> USARTPeripheral<B> {
         )
     }
 
-    pub fn configure_buffered_tx(&self, tx: &'static mut Queue<char, 128>) -> impl Write {
+    pub fn configure_buffered_tx<const N: usize>(
+        &self,
+        tx: &'static mut Queue<char, N>,
+    ) -> impl Write {
         Self::buffered_configure(
             &USARTConfig {
                 mode: USARTMode::RxTx,
@@ -310,10 +316,10 @@ impl<const B: u32> USARTPeripheral<B> {
         )
     }
 
-    pub fn configure_buffered_rx_tx(
+    pub fn configure_buffered_rx_tx<const N: usize>(
         &self,
-        rx: &'static mut Queue<char, 128>,
-        tx: &'static mut Queue<char, 128>,
+        rx: &'static mut Queue<char, N>,
+        tx: &'static mut Queue<char, N>,
     ) -> impl UsartBufferedInOut {
         Self::buffered_configure(
             &USARTConfig {
@@ -327,11 +333,11 @@ impl<const B: u32> USARTPeripheral<B> {
         )
     }
 
-    fn buffered_configure(
+    fn buffered_configure<const N: usize>(
         config: &USARTConfig,
-        rx: Option<&'static mut Queue<char, 128>>,
-        tx: Option<&'static mut Queue<char, 128>>,
-    ) -> USARTBufferedFunction {
+        rx: Option<&'static mut Queue<char, N>>,
+        tx: Option<&'static mut Queue<char, N>>,
+    ) -> USARTBufferedFunction<N> {
         let mut usart = USARTBufferedFunction {
             port: get_port!(USART_TypeDef, B),
             rx,
diff --git a/minimal_interrupt/l5/src/main.rs b/minimal_interrupt/l5/src/main.rs
index b4333f3..586dd16 100644
--- a/minimal_interrupt/l5/src/main.rs
+++ b/minimal_interrupt/l5/src/main.rs
@@ -23,10 +23,10 @@ fn main() -> ! {
     use core::{
         fmt::Write,
         ptr,
-        sync::atomic::{AtomicBool, AtomicPtr, Ordering},
+        sync::atomic::{AtomicBool, Ordering},
     };
     use l0::*;
-    use l2::heapless::{spsc::Queue, String, Vec};
+    use l2::heapless::spsc::Queue;
     use l3::*;
     use l4::*;
 
@@ -90,29 +90,37 @@ fn main() -> ! {
     // Button module
     static BUTTON_PRESSED: AtomicBool = AtomicBool::new(false);
     configure_gpio_input();
-    attach_interrupt_handler(Interrupt::EXTI15_10, || {
+    #[no_mangle]
+    extern "C" fn EXTI15_10_Interrupt_Handler() {
         let mut exti_register = EXTI::get_register();
         if exti_register.is_pending_interrupt(13) {
             exti_register.clear_pending_interrupt(13);
             BUTTON_PRESSED.store(true, Ordering::SeqCst);
         }
-    });
+    }
     configure_gpio_input_interrupt();
 
     // USART
     let mut usart1_rx_tx = configure_usart_rx_tx();
-    static mut RX_BUF: Queue<char, 128> = Queue::new();
-    static mut TX_BUF: Queue<char, 128> = Queue::new();
-    attach_interrupt_handler(Interrupt::USART1, || {
+    // NOTE, Queue implementation is very heavy
+    // Uses 4 bytes per character
+    static mut RX_BUF: Queue<char, 64> = Queue::new();
+    static mut TX_BUF: Queue<char, 64> = Queue::new();
+    static IS_NEWLINE: AtomicBool = AtomicBool::new(false);
+    #[no_mangle]
+    extern "C" fn USART1_Interrupt_Handler() {
         let usart1_port = USART1_PORT::port();
         let isr_data = read_register!(usart1_port.ISR);
         const RXNE: u32 = 5;
-        const TC: u32 = 6;
+        // const TC: u32 = 6;
         const TXE: u32 = 7;
         const TXEIE: u32 = 7;
         if (isr_data >> RXNE) & 0x01 == 1 {
             // Read data
             let rdr_data = read_register!(usart1_port.RDR) as u8 as char;
+            if rdr_data == '\n' || rdr_data == '\r' {
+                IS_NEWLINE.store(true, Ordering::SeqCst);
+            }
             unsafe { RX_BUF.enqueue(rdr_data).unwrap() };
         }
 
@@ -129,44 +137,27 @@ fn main() -> ! {
                 }
             };
         }
-    });
+    }
     configure_usart_rx_tx_interrupt();
 
     const TIME: u32 = 100_000;
-    let mut counter = 0;
-    let mut line_buffer: String<50> = String::new();
     loop {
-        if let Ok(_) =
-            BUTTON_PRESSED.compare_exchange(true, false, Ordering::SeqCst, Ordering::SeqCst)
-        {
-            usart1_rx_tx.write_str("Button Pressed\r\n").unwrap();
+        if BUTTON_PRESSED.load(Ordering::SeqCst) {
+            led.on();
+            spin_delay(TIME);
+            led.off();
+            BUTTON_PRESSED.store(false, Ordering::SeqCst);
         }
 
-        while let Some(data) = usart1_rx_tx.try_read_character() {
-            if data == '\r' || data == '\n' {
-                usart1_rx_tx
-                    .write_fmt(format_args!("W: {} {:#?}\r\n", line_buffer, line_buffer))
-                    .unwrap();
-                line_buffer.clear();
-            } else {
-                line_buffer.push(data).unwrap();
+        if IS_NEWLINE.load(Ordering::SeqCst) {
+            usart1_rx_tx.write_str("Printing\r\n").unwrap();
+            while usart1_rx_tx.size() != 0 {
+                let c = usart1_rx_tx.try_read_character().unwrap();
+                usart1_rx_tx.write_char(c).unwrap();
             }
+            usart1_rx_tx.write_str("\r\n").unwrap();
+            IS_NEWLINE.store(false, Ordering::SeqCst);
         }
-
-        // Can also use write! and writeln!
-        led.on();
-        usart1_rx_tx
-            .write_fmt(format_args!("LED ON: {}\r\n", counter))
-            .unwrap();
-        spin_delay(TIME);
-
-        led.off();
-        usart1_rx_tx
-            .write_fmt(format_args!("LED OFF: {}\r\n", counter))
-            .unwrap();
-
-        spin_delay(TIME);
-        counter += 1;
     }
 }