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Sunil Gouthamdavem330
Sunil Goutham
authored and
davem330
committed
net: thunderx: Add support for 81xx and 83xx chips
This patch adds info on HW maximums of 81xx/83xx and also configures receive and transmit datapaths accordingly. Signed-off-by: Sunil Goutham <sgoutham@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent f7ff0ae commit 0025d93

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3 files changed

+73
-17
lines changed

3 files changed

+73
-17
lines changed

‎drivers/net/ethernet/cavium/thunder/nic_main.c

Lines changed: 70 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,8 @@ struct hw_info {
2424
u8 bgx_cnt;
2525
u8 chans_per_lmac;
2626
u8 chans_per_bgx; /* Rx/Tx chans */
27+
u8 chans_per_rgx;
28+
u8 chans_per_lbk;
2729
u16 cpi_cnt;
2830
u16 rssi_cnt;
2931
u16 rss_ind_tbl_size;
@@ -332,6 +334,33 @@ static void nic_get_hw_info(struct nicpf *nic)
332334
hw->tl1_cnt = 2;
333335
hw->tl1_per_bgx = true;
334336
break;
337+
case PCI_SUBSYS_DEVID_81XX_NIC_PF:
338+
hw->bgx_cnt = MAX_BGX_PER_CN81XX;
339+
hw->chans_per_lmac = 8;
340+
hw->chans_per_bgx = 32;
341+
hw->chans_per_rgx = 8;
342+
hw->chans_per_lbk = 24;
343+
hw->cpi_cnt = 512;
344+
hw->rssi_cnt = 256;
345+
hw->rss_ind_tbl_size = 32; /* Max RSSI / Max interfaces */
346+
hw->tl3_cnt = 64;
347+
hw->tl2_cnt = 16;
348+
hw->tl1_cnt = 10;
349+
hw->tl1_per_bgx = false;
350+
break;
351+
case PCI_SUBSYS_DEVID_83XX_NIC_PF:
352+
hw->bgx_cnt = MAX_BGX_PER_CN83XX;
353+
hw->chans_per_lmac = 8;
354+
hw->chans_per_bgx = 32;
355+
hw->chans_per_lbk = 64;
356+
hw->cpi_cnt = 2048;
357+
hw->rssi_cnt = 1024;
358+
hw->rss_ind_tbl_size = 64; /* Max RSSI / Max interfaces */
359+
hw->tl3_cnt = 256;
360+
hw->tl2_cnt = 64;
361+
hw->tl1_cnt = 18;
362+
hw->tl1_per_bgx = false;
363+
break;
335364
}
336365
hw->tl4_cnt = MAX_QUEUES_PER_QSET * pci_sriov_get_totalvfs(nic->pdev);
337366
}
@@ -353,11 +382,15 @@ static void nic_init_hw(struct nicpf *nic)
353382
/* Enable backpressure */
354383
nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
355384

356-
/* Disable TNS mode on both interfaces */
357-
nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
358-
(NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
359-
nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
360-
(NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
385+
/* TNS and TNS bypass modes are present only on 88xx */
386+
if (nic->pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF) {
387+
/* Disable TNS mode on both interfaces */
388+
nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
389+
(NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
390+
nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
391+
(NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
392+
}
393+
361394
nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
362395
(1ULL << 63) | BGX0_BLOCK);
363396
nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
@@ -525,7 +558,7 @@ static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
525558
/* 4 level transmit side scheduler configutation
526559
* for TNS bypass mode
527560
*
528-
* Sample configuration for SQ0
561+
* Sample configuration for SQ0 on 88xx
529562
* VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
530563
* VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
531564
* VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
@@ -560,17 +593,21 @@ static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
560593
/* For 88xx 0-511 TL4 transmits via BGX0 and
561594
* 512-1023 TL4s transmit via BGX1.
562595
*/
563-
tl4 = bgx * (hw->tl4_cnt / hw->bgx_cnt);
564-
if (!sq->sqs_mode) {
565-
tl4 += (lmac * MAX_QUEUES_PER_QSET);
566-
} else {
567-
for (svf = 0; svf < MAX_SQS_PER_VF; svf++) {
568-
if (nic->vf_sqs[pqs_vnic][svf] == vnic)
569-
break;
596+
if (hw->tl1_per_bgx) {
597+
tl4 = bgx * (hw->tl4_cnt / hw->bgx_cnt);
598+
if (!sq->sqs_mode) {
599+
tl4 += (lmac * MAX_QUEUES_PER_QSET);
600+
} else {
601+
for (svf = 0; svf < MAX_SQS_PER_VF; svf++) {
602+
if (nic->vf_sqs[pqs_vnic][svf] == vnic)
603+
break;
604+
}
605+
tl4 += (MAX_LMAC_PER_BGX * MAX_QUEUES_PER_QSET);
606+
tl4 += (lmac * MAX_QUEUES_PER_QSET * MAX_SQS_PER_VF);
607+
tl4 += (svf * MAX_QUEUES_PER_QSET);
570608
}
571-
tl4 += (MAX_LMAC_PER_BGX * MAX_QUEUES_PER_QSET);
572-
tl4 += (lmac * MAX_QUEUES_PER_QSET * MAX_SQS_PER_VF);
573-
tl4 += (svf * MAX_QUEUES_PER_QSET);
609+
} else {
610+
tl4 = (vnic * MAX_QUEUES_PER_QSET);
574611
}
575612
tl4 += sq_idx;
576613

@@ -585,9 +622,15 @@ static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
585622

586623
/* On 88xx 0-127 channels are for BGX0 and
587624
* 127-255 channels for BGX1.
625+
*
626+
* On 81xx/83xx TL3_CHAN reg should be configured with channel
627+
* within LMAC i.e 0-7 and not the actual channel number like on 88xx
588628
*/
589629
chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx);
590-
nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
630+
if (hw->tl1_per_bgx)
631+
nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
632+
else
633+
nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), 0);
591634

592635
/* Enable backpressure on the channel */
593636
nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
@@ -597,6 +640,16 @@ static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
597640
nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
598641
/* No priorities as of now */
599642
nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
643+
644+
/* Unlike 88xx where TL2s 0-31 transmits to TL1 '0' and rest to TL1 '1'
645+
* on 81xx/83xx TL2 needs to be configured to transmit to one of the
646+
* possible LMACs.
647+
*
648+
* This register doesn't exist on 88xx.
649+
*/
650+
if (!hw->tl1_per_bgx)
651+
nic_reg_write(nic, NIC_PF_TL2_LMAC | (tl2 << 3),
652+
lmac + (bgx * MAX_LMAC_PER_BGX));
600653
}
601654

602655
/* Send primary nicvf pointer to secondary QS's VF */

‎drivers/net/ethernet/cavium/thunder/nic_reg.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@
103103
#define NIC_PF_SW_SYNC_RX_DONE (0x490008)
104104
#define NIC_PF_TL2_0_63_CFG (0x500000)
105105
#define NIC_PF_TL2_0_63_PRI (0x520000)
106+
#define NIC_PF_TL2_LMAC (0x540000)
106107
#define NIC_PF_TL2_0_63_SH_STATUS (0x580000)
107108
#define NIC_PF_TL3A_0_63_CFG (0x5F0000)
108109
#define NIC_PF_TL3_0_255_CFG (0x600000)

‎drivers/net/ethernet/cavium/thunder/thunder_bgx.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@
1111

1212
#define MAX_BGX_THUNDER 8 /* Max 4 nodes, 2 per node */
1313
#define MAX_BGX_PER_CN88XX 2
14+
#define MAX_BGX_PER_CN81XX 2
15+
#define MAX_BGX_PER_CN83XX 4
1416
#define MAX_LMAC_PER_BGX 4
1517
#define MAX_BGX_CHANS_PER_LMAC 16
1618
#define MAX_DMAC_PER_LMAC 8

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