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torvaldstorvalds
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Merge tag 'drm-fixes-for-4.10-rc1' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Some fixes came in while I was out, mostly intel and amdgpu ones, with one ast fix" Daniel Vetter says: "This should also shut up the WARN_ON(!intel_dp->lane_count) noise" * tag 'drm-fixes-for-4.10-rc1' of git://people.freedesktop.org/~airlied/linux: (35 commits) drm/amdgpu: update tile table for oland/hainan drm/amdgpu: update tile table for verde drm/amdgpu: update rev id for verde drm/amdgpu: update golden setting for verde drm/amdgpu: update rev id for oland drm/amdgpu: update golden setting for oland drm/amdgpu: update rev id for hainan drm/amdgpu: update golden setting for hainan drm/amdgpu: update rev id for pitcairn drm/amdgpu: update golden setting for pitcairn drm/amdgpu: update golden setting/tiling table of tahiti drm/i915: skip the first 4k of stolen memory on everything >= gen8 drm/i915: Fallback to single PAGE_SIZE segments for DMA remapping drm/i915: Fix use after free in logical_render_ring_init drm/i915: disable PSR by default on HSW/BDW drm/i915: Fix setting of boost freq tunable drm/i915: tune down the fast link training vs boot fail drm/i915: Reorder phys backing storage release drm/i915/gen9: Fix PCODE polling during SAGV disabling drm/i915/gen9: Fix PCODE polling during CDCLK change notification ...
2 parents 2969159 + 4a401ce commit 01302aa

20 files changed

+1409
-728
lines changed

‎drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1944,9 +1944,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
19441944

19451945
dce_v6_0_lock_cursor(crtc, true);
19461946

1947-
if (width != amdgpu_crtc->cursor_width ||
1948-
height != amdgpu_crtc->cursor_height ||
1949-
hot_x != amdgpu_crtc->cursor_hot_x ||
1947+
if (hot_x != amdgpu_crtc->cursor_hot_x ||
19501948
hot_y != amdgpu_crtc->cursor_hot_y) {
19511949
int x, y;
19521950

@@ -1955,8 +1953,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
19551953

19561954
dce_v6_0_cursor_move_locked(crtc, x, y);
19571955

1958-
amdgpu_crtc->cursor_width = width;
1959-
amdgpu_crtc->cursor_height = height;
19601956
amdgpu_crtc->cursor_hot_x = hot_x;
19611957
amdgpu_crtc->cursor_hot_y = hot_y;
19621958
}

‎drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2438,8 +2438,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
24382438

24392439
dce_v8_0_cursor_move_locked(crtc, x, y);
24402440

2441-
amdgpu_crtc->cursor_width = width;
2442-
amdgpu_crtc->cursor_height = height;
24432441
amdgpu_crtc->cursor_hot_x = hot_x;
24442442
amdgpu_crtc->cursor_hot_y = hot_y;
24452443
}

‎drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

Lines changed: 665 additions & 270 deletions
Large diffs are not rendered by default.

‎drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

Lines changed: 161 additions & 88 deletions
Original file line numberDiff line numberDiff line change
@@ -3949,8 +3949,12 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
39493949
temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
39503950
data = mmRLC_SRM_INDEX_CNTL_DATA_0;
39513951
for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
3952-
amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
3953-
amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
3952+
if (unique_indices[i] != 0) {
3953+
amdgpu_mm_wreg(adev, temp + i,
3954+
unique_indices[i] & 0x3FFFF, false);
3955+
amdgpu_mm_wreg(adev, data + i,
3956+
unique_indices[i] >> 20, false);
3957+
}
39543958
}
39553959
kfree(register_list_format);
39563960

@@ -3966,20 +3970,17 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
39663970
{
39673971
uint32_t data;
39683972

3969-
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3970-
AMD_PG_SUPPORT_GFX_SMG |
3971-
AMD_PG_SUPPORT_GFX_DMG)) {
3972-
WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
3973+
WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
39733974

3974-
data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
3975-
data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
3976-
data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
3977-
data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
3978-
WREG32(mmRLC_PG_DELAY, data);
3975+
data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
3976+
data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
3977+
data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
3978+
data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
3979+
WREG32(mmRLC_PG_DELAY, data);
3980+
3981+
WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
3982+
WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
39793983

3980-
WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
3981-
WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
3982-
}
39833984
}
39843985

39853986
static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
@@ -3996,41 +3997,37 @@ static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
39963997

39973998
static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
39983999
{
3999-
WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0);
4000+
WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
40004001
}
40014002

40024003
static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
40034004
{
4004-
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4005-
AMD_PG_SUPPORT_GFX_SMG |
4006-
AMD_PG_SUPPORT_GFX_DMG |
4007-
AMD_PG_SUPPORT_CP |
4008-
AMD_PG_SUPPORT_GDS |
4009-
AMD_PG_SUPPORT_RLC_SMU_HS)) {
4005+
if ((adev->asic_type == CHIP_CARRIZO) ||
4006+
(adev->asic_type == CHIP_STONEY)) {
40104007
gfx_v8_0_init_csb(adev);
40114008
gfx_v8_0_init_save_restore_list(adev);
40124009
gfx_v8_0_enable_save_restore_machine(adev);
4013-
4014-
if ((adev->asic_type == CHIP_CARRIZO) ||
4015-
(adev->asic_type == CHIP_STONEY)) {
4016-
WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4017-
gfx_v8_0_init_power_gating(adev);
4018-
WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4019-
if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
4020-
cz_enable_sck_slow_down_on_power_up(adev, true);
4021-
cz_enable_sck_slow_down_on_power_down(adev, true);
4022-
} else {
4023-
cz_enable_sck_slow_down_on_power_up(adev, false);
4024-
cz_enable_sck_slow_down_on_power_down(adev, false);
4025-
}
4026-
if (adev->pg_flags & AMD_PG_SUPPORT_CP)
4027-
cz_enable_cp_power_gating(adev, true);
4028-
else
4029-
cz_enable_cp_power_gating(adev, false);
4030-
} else if (adev->asic_type == CHIP_POLARIS11) {
4031-
gfx_v8_0_init_power_gating(adev);
4010+
WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4011+
gfx_v8_0_init_power_gating(adev);
4012+
WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4013+
if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
4014+
cz_enable_sck_slow_down_on_power_up(adev, true);
4015+
cz_enable_sck_slow_down_on_power_down(adev, true);
4016+
} else {
4017+
cz_enable_sck_slow_down_on_power_up(adev, false);
4018+
cz_enable_sck_slow_down_on_power_down(adev, false);
40324019
}
4020+
if (adev->pg_flags & AMD_PG_SUPPORT_CP)
4021+
cz_enable_cp_power_gating(adev, true);
4022+
else
4023+
cz_enable_cp_power_gating(adev, false);
4024+
} else if (adev->asic_type == CHIP_POLARIS11) {
4025+
gfx_v8_0_init_csb(adev);
4026+
gfx_v8_0_init_save_restore_list(adev);
4027+
gfx_v8_0_enable_save_restore_machine(adev);
4028+
gfx_v8_0_init_power_gating(adev);
40334029
}
4030+
40344031
}
40354032

40364033
static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
@@ -5339,14 +5336,11 @@ static int gfx_v8_0_set_powergating_state(void *handle,
53395336
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
53405337
bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
53415338

5342-
if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5343-
return 0;
5344-
53455339
switch (adev->asic_type) {
53465340
case CHIP_CARRIZO:
53475341
case CHIP_STONEY:
5348-
if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
5349-
cz_update_gfx_cg_power_gating(adev, enable);
5342+
5343+
cz_update_gfx_cg_power_gating(adev, enable);
53505344

53515345
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
53525346
gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
@@ -5791,69 +5785,148 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
57915785
static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
57925786
enum amd_clockgating_state state)
57935787
{
5794-
uint32_t msg_id, pp_state;
5788+
uint32_t msg_id, pp_state = 0;
5789+
uint32_t pp_support_state = 0;
57955790
void *pp_handle = adev->powerplay.pp_handle;
57965791

5797-
if (state == AMD_CG_STATE_UNGATE)
5798-
pp_state = 0;
5799-
else
5800-
pp_state = PP_STATE_CG | PP_STATE_LS;
5792+
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5793+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5794+
pp_support_state = PP_STATE_SUPPORT_LS;
5795+
pp_state = PP_STATE_LS;
5796+
}
5797+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5798+
pp_support_state |= PP_STATE_SUPPORT_CG;
5799+
pp_state |= PP_STATE_CG;
5800+
}
5801+
if (state == AMD_CG_STATE_UNGATE)
5802+
pp_state = 0;
5803+
5804+
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5805+
PP_BLOCK_GFX_CG,
5806+
pp_support_state,
5807+
pp_state);
5808+
amd_set_clockgating_by_smu(pp_handle, msg_id);
5809+
}
58015810

5802-
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5803-
PP_BLOCK_GFX_CG,
5804-
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5805-
pp_state);
5806-
amd_set_clockgating_by_smu(pp_handle, msg_id);
5811+
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5812+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5813+
pp_support_state = PP_STATE_SUPPORT_LS;
5814+
pp_state = PP_STATE_LS;
5815+
}
58075816

5808-
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5809-
PP_BLOCK_GFX_MG,
5810-
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5811-
pp_state);
5812-
amd_set_clockgating_by_smu(pp_handle, msg_id);
5817+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5818+
pp_support_state |= PP_STATE_SUPPORT_CG;
5819+
pp_state |= PP_STATE_CG;
5820+
}
5821+
5822+
if (state == AMD_CG_STATE_UNGATE)
5823+
pp_state = 0;
5824+
5825+
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5826+
PP_BLOCK_GFX_MG,
5827+
pp_support_state,
5828+
pp_state);
5829+
amd_set_clockgating_by_smu(pp_handle, msg_id);
5830+
}
58135831

58145832
return 0;
58155833
}
58165834

58175835
static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
58185836
enum amd_clockgating_state state)
58195837
{
5820-
uint32_t msg_id, pp_state;
5838+
5839+
uint32_t msg_id, pp_state = 0;
5840+
uint32_t pp_support_state = 0;
58215841
void *pp_handle = adev->powerplay.pp_handle;
58225842

5823-
if (state == AMD_CG_STATE_UNGATE)
5824-
pp_state = 0;
5825-
else
5826-
pp_state = PP_STATE_CG | PP_STATE_LS;
5843+
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5844+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5845+
pp_support_state = PP_STATE_SUPPORT_LS;
5846+
pp_state = PP_STATE_LS;
5847+
}
5848+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5849+
pp_support_state |= PP_STATE_SUPPORT_CG;
5850+
pp_state |= PP_STATE_CG;
5851+
}
5852+
if (state == AMD_CG_STATE_UNGATE)
5853+
pp_state = 0;
5854+
5855+
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5856+
PP_BLOCK_GFX_CG,
5857+
pp_support_state,
5858+
pp_state);
5859+
amd_set_clockgating_by_smu(pp_handle, msg_id);
5860+
}
58275861

5828-
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5829-
PP_BLOCK_GFX_CG,
5830-
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5831-
pp_state);
5832-
amd_set_clockgating_by_smu(pp_handle, msg_id);
5862+
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
5863+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5864+
pp_support_state = PP_STATE_SUPPORT_LS;
5865+
pp_state = PP_STATE_LS;
5866+
}
5867+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5868+
pp_support_state |= PP_STATE_SUPPORT_CG;
5869+
pp_state |= PP_STATE_CG;
5870+
}
5871+
if (state == AMD_CG_STATE_UNGATE)
5872+
pp_state = 0;
5873+
5874+
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5875+
PP_BLOCK_GFX_3D,
5876+
pp_support_state,
5877+
pp_state);
5878+
amd_set_clockgating_by_smu(pp_handle, msg_id);
5879+
}
58335880

5834-
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5835-
PP_BLOCK_GFX_3D,
5836-
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5837-
pp_state);
5838-
amd_set_clockgating_by_smu(pp_handle, msg_id);
5881+
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5882+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5883+
pp_support_state = PP_STATE_SUPPORT_LS;
5884+
pp_state = PP_STATE_LS;
5885+
}
58395886

5840-
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5841-
PP_BLOCK_GFX_MG,
5842-
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5843-
pp_state);
5844-
amd_set_clockgating_by_smu(pp_handle, msg_id);
5887+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5888+
pp_support_state |= PP_STATE_SUPPORT_CG;
5889+
pp_state |= PP_STATE_CG;
5890+
}
58455891

5846-
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5847-
PP_BLOCK_GFX_RLC,
5848-
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5849-
pp_state);
5850-
amd_set_clockgating_by_smu(pp_handle, msg_id);
5892+
if (state == AMD_CG_STATE_UNGATE)
5893+
pp_state = 0;
5894+
5895+
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5896+
PP_BLOCK_GFX_MG,
5897+
pp_support_state,
5898+
pp_state);
5899+
amd_set_clockgating_by_smu(pp_handle, msg_id);
5900+
}
5901+
5902+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5903+
pp_support_state = PP_STATE_SUPPORT_LS;
58515904

5852-
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5905+
if (state == AMD_CG_STATE_UNGATE)
5906+
pp_state = 0;
5907+
else
5908+
pp_state = PP_STATE_LS;
5909+
5910+
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5911+
PP_BLOCK_GFX_RLC,
5912+
pp_support_state,
5913+
pp_state);
5914+
amd_set_clockgating_by_smu(pp_handle, msg_id);
5915+
}
5916+
5917+
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5918+
pp_support_state = PP_STATE_SUPPORT_LS;
5919+
5920+
if (state == AMD_CG_STATE_UNGATE)
5921+
pp_state = 0;
5922+
else
5923+
pp_state = PP_STATE_LS;
5924+
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
58535925
PP_BLOCK_GFX_CP,
5854-
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5926+
pp_support_state,
58555927
pp_state);
5856-
amd_set_clockgating_by_smu(pp_handle, msg_id);
5928+
amd_set_clockgating_by_smu(pp_handle, msg_id);
5929+
}
58575930

58585931
return 0;
58595932
}

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