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Merge branch 'hnx3-vf'
Salil Mehta says: ==================== Hisilicon Network Subsystem 3 VF Ethernet Driver This patch-set contains the support of the HNS3 (Hisilicon Network Subsystem 3) Virtual Function Ethernet driver for hip08 family of SoCs. The Physical Function driver is already part of the Linux mainline. This VF driver has its Hardware Compatibility Layer and has commom/unified ENET layer/client/ethtool code with the PF driver. It also has support of mailbox to communicate with the HNS3 PF driver. The basic architecture of VF driver is derivative of the PF driver. Just like PF driver, this driver is also PCI Express based. This driver is the ongoing development work and HNS3 VF Ethernet driver would be incrementally enhanced with more new features. High Level Architecture: [ Ethtool ] | [ Ethernet Client ] ... [ RoCE Client ] | | [ HNAE Device ] |________ | | | --------------------------------------------- | | [ HNAE3 Framework (Register/unregister) ] | | --------------------------------------------- | | | [ VF HCLGE Layer ] | | | | | | | | | | | [ VF Mailbox (To PF via IMP) ] | | | | [ IMP command Interface ] [ IMP command Interface ] | | | | (A B O V E R U N S O N G U E S T S Y S T E M) ------------------------------------------------------------- Q E M U / V F I O / K V M (on Host System) ------------------------------------------------------------- HIP08 H A R D W A R E (limited to VF by SMMU) [ IMP/Mgmt Processor (hardware common to system/cmd based) ] Fig 1. HNS3 Virtual Function Driver [ dcbnl ] [ Ethtool ] | | [ Ethernet Client ] [ ODP/UIO Client ] . . .[ RoCE Client ] |_____________________| | | _________| [ HNAE Device ] | | | | | --------------------------------------------- | | [ HNAE3 Framework (Register/unregister) ] | | --------------------------------------------- | | | [ HCLGE Layer ] | ________________|_________________ | | | | | [ DCB ] | | | | | | | [ Scheduler/Shaper ] [ MDIO ] [ PF Mailbox ] | | | | | |________________|_________________| | | | [ IMP command Interface ] [ IMP command Interface ] ---------------------------------------------------------------- HIP08 H A R D W A R E [ IMP/Mgmt Processor (hardware common to system/cmd based) ] Fig 2. Existing HNS3 PF Driver (added with mailbox) Change Log Summary: Patch V4: Addressed SPDX related comment by Philippe Ombredanne Patch V3: Addressed SPDX change requested by Philippe Ombredanne Patch V2: 1. Addressed some comments by David Miller. 2. Addressed some internal comments on various patches Patch V1: Initial Submit ==================== Acked-by: Philippe Ombredanne <pombredanne@nexb.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2 parents be17bbe + c1a8161 commit 020929d

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‎drivers/net/ethernet/hisilicon/Kconfig

Lines changed: 19 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -94,15 +94,6 @@ config HNS3_HCLGE
9494
compatibility layer. The engine would be used in Hisilicon hip08 family of
9595
SoCs and further upcoming SoCs.
9696

97-
config HNS3_ENET
98-
tristate "Hisilicon HNS3 Ethernet Device Support"
99-
depends on 64BIT && PCI
100-
depends on HNS3 && HNS3_HCLGE
101-
---help---
102-
This selects the Ethernet Driver for Hisilicon Network Subsystem 3 for hip08
103-
family of SoCs. This module depends upon HNAE3 driver to access the HNAE3
104-
devices and their associated operations.
105-
10697
config HNS3_DCB
10798
bool "Hisilicon HNS3 Data Center Bridge Support"
10899
default n
@@ -112,4 +103,23 @@ config HNS3_DCB
112103

113104
If unsure, say N.
114105

106+
config HNS3_HCLGEVF
107+
tristate "Hisilicon HNS3VF Acceleration Engine & Compatibility Layer Support"
108+
depends on PCI_MSI
109+
depends on HNS3
110+
depends on HNS3_HCLGE
111+
---help---
112+
This selects the HNS3 VF drivers network acceleration engine & its hardware
113+
compatibility layer. The engine would be used in Hisilicon hip08 family of
114+
SoCs and further upcoming SoCs.
115+
116+
config HNS3_ENET
117+
tristate "Hisilicon HNS3 Ethernet Device Support"
118+
depends on 64BIT && PCI
119+
depends on HNS3
120+
---help---
121+
This selects the Ethernet Driver for Hisilicon Network Subsystem 3 for hip08
122+
family of SoCs. This module depends upon HNAE3 driver to access the HNAE3
123+
devices and their associated operations.
124+
115125
endif # NET_VENDOR_HISILICON

‎drivers/net/ethernet/hisilicon/hns3/Makefile

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,14 @@
1+
# SPDX-License-Identifier: GPL-2.0+
12
#
23
# Makefile for the HISILICON network device drivers.
34
#
45

56
obj-$(CONFIG_HNS3) += hns3pf/
7+
obj-$(CONFIG_HNS3) += hns3vf/
68

79
obj-$(CONFIG_HNS3) += hnae3.o
10+
11+
obj-$(CONFIG_HNS3_ENET) += hns3.o
12+
hns3-objs = hns3_enet.o hns3_ethtool.o
13+
14+
hns3-$(CONFIG_HNS3_DCB) += hns3_dcbnl.o

‎drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
1+
/* SPDX-License-Identifier: GPL-2.0+ */
2+
/* Copyright (c) 2016-2017 Hisilicon Limited. */
3+
4+
#ifndef __HCLGE_MBX_H
5+
#define __HCLGE_MBX_H
6+
#include <linux/init.h>
7+
#include <linux/mutex.h>
8+
#include <linux/types.h>
9+
10+
#define HCLGE_MBX_VF_MSG_DATA_NUM 16
11+
12+
enum HCLGE_MBX_OPCODE {
13+
HCLGE_MBX_RESET = 0x01, /* (VF -> PF) assert reset */
14+
HCLGE_MBX_SET_UNICAST, /* (VF -> PF) set UC addr */
15+
HCLGE_MBX_SET_MULTICAST, /* (VF -> PF) set MC addr */
16+
HCLGE_MBX_SET_VLAN, /* (VF -> PF) set VLAN */
17+
HCLGE_MBX_MAP_RING_TO_VECTOR, /* (VF -> PF) map ring-to-vector */
18+
HCLGE_MBX_UNMAP_RING_TO_VECTOR, /* (VF -> PF) unamp ring-to-vector */
19+
HCLGE_MBX_SET_PROMISC_MODE, /* (VF -> PF) set promiscuous mode */
20+
HCLGE_MBX_SET_MACVLAN, /* (VF -> PF) set unicast filter */
21+
HCLGE_MBX_API_NEGOTIATE, /* (VF -> PF) negotiate API version */
22+
HCLGE_MBX_GET_QINFO, /* (VF -> PF) get queue config */
23+
HCLGE_MBX_GET_TCINFO, /* (VF -> PF) get TC config */
24+
HCLGE_MBX_GET_RETA, /* (VF -> PF) get RETA */
25+
HCLGE_MBX_GET_RSS_KEY, /* (VF -> PF) get RSS key */
26+
HCLGE_MBX_GET_MAC_ADDR, /* (VF -> PF) get MAC addr */
27+
HCLGE_MBX_PF_VF_RESP, /* (PF -> VF) generate respone to VF */
28+
HCLGE_MBX_GET_BDNUM, /* (VF -> PF) get BD num */
29+
HCLGE_MBX_GET_BUFSIZE, /* (VF -> PF) get buffer size */
30+
HCLGE_MBX_GET_STREAMID, /* (VF -> PF) get stream id */
31+
HCLGE_MBX_SET_AESTART, /* (VF -> PF) start ae */
32+
HCLGE_MBX_SET_TSOSTATS, /* (VF -> PF) get tso stats */
33+
HCLGE_MBX_LINK_STAT_CHANGE, /* (PF -> VF) link status has changed */
34+
HCLGE_MBX_GET_BASE_CONFIG, /* (VF -> PF) get config */
35+
HCLGE_MBX_BIND_FUNC_QUEUE, /* (VF -> PF) bind function and queue */
36+
HCLGE_MBX_GET_LINK_STATUS, /* (VF -> PF) get link status */
37+
HCLGE_MBX_QUEUE_RESET, /* (VF -> PF) reset queue */
38+
};
39+
40+
/* below are per-VF mac-vlan subcodes */
41+
enum hclge_mbx_mac_vlan_subcode {
42+
HCLGE_MBX_MAC_VLAN_UC_MODIFY = 0, /* modify UC mac addr */
43+
HCLGE_MBX_MAC_VLAN_UC_ADD, /* add a new UC mac addr */
44+
HCLGE_MBX_MAC_VLAN_UC_REMOVE, /* remove a new UC mac addr */
45+
HCLGE_MBX_MAC_VLAN_MC_MODIFY, /* modify MC mac addr */
46+
HCLGE_MBX_MAC_VLAN_MC_ADD, /* add new MC mac addr */
47+
HCLGE_MBX_MAC_VLAN_MC_REMOVE, /* remove MC mac addr */
48+
HCLGE_MBX_MAC_VLAN_MC_FUNC_MTA_ENABLE, /* config func MTA enable */
49+
};
50+
51+
/* below are per-VF vlan cfg subcodes */
52+
enum hclge_mbx_vlan_cfg_subcode {
53+
HCLGE_MBX_VLAN_FILTER = 0, /* set vlan filter */
54+
HCLGE_MBX_VLAN_TX_OFF_CFG, /* set tx side vlan offload */
55+
HCLGE_MBX_VLAN_RX_OFF_CFG, /* set rx side vlan offload */
56+
};
57+
58+
#define HCLGE_MBX_MAX_MSG_SIZE 16
59+
#define HCLGE_MBX_MAX_RESP_DATA_SIZE 8
60+
61+
struct hclgevf_mbx_resp_status {
62+
struct mutex mbx_mutex; /* protects against contending sync cmd resp */
63+
u32 origin_mbx_msg;
64+
bool received_resp;
65+
int resp_status;
66+
u8 additional_info[HCLGE_MBX_MAX_RESP_DATA_SIZE];
67+
};
68+
69+
struct hclge_mbx_vf_to_pf_cmd {
70+
u8 rsv;
71+
u8 mbx_src_vfid; /* Auto filled by IMP */
72+
u8 rsv1[2];
73+
u8 msg_len;
74+
u8 rsv2[3];
75+
u8 msg[HCLGE_MBX_MAX_MSG_SIZE];
76+
};
77+
78+
struct hclge_mbx_pf_to_vf_cmd {
79+
u8 dest_vfid;
80+
u8 rsv[3];
81+
u8 msg_len;
82+
u8 rsv1[3];
83+
u16 msg[8];
84+
};
85+
86+
#define hclge_mbx_ring_ptr_move_crq(crq) \
87+
(crq->next_to_use = (crq->next_to_use + 1) % crq->desc_num)
88+
#endif

‎drivers/net/ethernet/hisilicon/hns3/hnae3.c

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -196,9 +196,18 @@ int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev)
196196
const struct pci_device_id *id;
197197
struct hnae3_ae_algo *ae_algo;
198198
struct hnae3_client *client;
199-
int ret = 0;
199+
int ret = 0, lock_acquired;
200+
201+
/* we can get deadlocked if SRIOV is being enabled in context to probe
202+
* and probe gets called again in same context. This can happen when
203+
* pci_enable_sriov() is called to create VFs from PF probes context.
204+
* Therefore, for simplicity uniformly defering further probing in all
205+
* cases where we detect contention.
206+
*/
207+
lock_acquired = mutex_trylock(&hnae3_common_lock);
208+
if (!lock_acquired)
209+
return -EPROBE_DEFER;
200210

201-
mutex_lock(&hnae3_common_lock);
202211
list_add_tail(&ae_dev->node, &hnae3_ae_dev_list);
203212

204213
/* Check if there are matched ae_algo */
@@ -211,6 +220,7 @@ int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev)
211220

212221
if (!ae_dev->ops) {
213222
dev_err(&ae_dev->pdev->dev, "ae_dev ops are null\n");
223+
ret = -EOPNOTSUPP;
214224
goto out_err;
215225
}
216226

‎drivers/net/ethernet/hisilicon/hns3/hnae3.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -452,9 +452,10 @@ struct hnae3_unic_private_info {
452452
struct hnae3_queue **tqp; /* array base of all TQPs of this instance */
453453
};
454454

455-
#define HNAE3_SUPPORT_MAC_LOOPBACK 1
456-
#define HNAE3_SUPPORT_PHY_LOOPBACK 2
457-
#define HNAE3_SUPPORT_SERDES_LOOPBACK 4
455+
#define HNAE3_SUPPORT_MAC_LOOPBACK BIT(0)
456+
#define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1)
457+
#define HNAE3_SUPPORT_SERDES_LOOPBACK BIT(2)
458+
#define HNAE3_SUPPORT_VF BIT(3)
458459

459460
struct hnae3_handle {
460461
struct hnae3_client *client;

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_dcbnl.c renamed to ‎drivers/net/ethernet/hisilicon/hns3/hns3_dcbnl.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ void hns3_dcbnl_setup(struct hnae3_handle *handle)
9393
{
9494
struct net_device *dev = handle->kinfo.netdev;
9595

96-
if (!handle->kinfo.dcb_ops)
96+
if ((!handle->kinfo.dcb_ops) || (handle->flags & HNAE3_SUPPORT_VF))
9797
return;
9898

9999
dev->dcbnl_ops = &hns3_dcbnl_ops;

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_enet.c renamed to ‎drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,8 @@ static const struct pci_device_id hns3_pci_tbl[] = {
5252
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
5353
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
5454
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
55+
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
56+
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
5557
/* required last entry */
5658
{0, }
5759
};

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_enet.h renamed to ‎drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

File renamed without changes.

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_ethtool.c renamed to ‎drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -849,6 +849,21 @@ static int hns3_nway_reset(struct net_device *netdev)
849849
return genphy_restart_aneg(phy);
850850
}
851851

852+
static const struct ethtool_ops hns3vf_ethtool_ops = {
853+
.get_drvinfo = hns3_get_drvinfo,
854+
.get_ringparam = hns3_get_ringparam,
855+
.set_ringparam = hns3_set_ringparam,
856+
.get_strings = hns3_get_strings,
857+
.get_ethtool_stats = hns3_get_stats,
858+
.get_sset_count = hns3_get_sset_count,
859+
.get_rxnfc = hns3_get_rxnfc,
860+
.get_rxfh_key_size = hns3_get_rss_key_size,
861+
.get_rxfh_indir_size = hns3_get_rss_indir_size,
862+
.get_rxfh = hns3_get_rss,
863+
.set_rxfh = hns3_set_rss,
864+
.get_link_ksettings = hns3_get_link_ksettings,
865+
};
866+
852867
static const struct ethtool_ops hns3_ethtool_ops = {
853868
.self_test = hns3_self_test,
854869
.get_drvinfo = hns3_get_drvinfo,
@@ -872,5 +887,10 @@ static const struct ethtool_ops hns3_ethtool_ops = {
872887

873888
void hns3_ethtool_set_ops(struct net_device *netdev)
874889
{
875-
netdev->ethtool_ops = &hns3_ethtool_ops;
890+
struct hnae3_handle *h = hns3_get_handle(netdev);
891+
892+
if (h->flags & HNAE3_SUPPORT_VF)
893+
netdev->ethtool_ops = &hns3vf_ethtool_ops;
894+
else
895+
netdev->ethtool_ops = &hns3_ethtool_ops;
876896
}

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,11 @@
1+
# SPDX-License-Identifier: GPL-2.0+
12
#
23
# Makefile for the HISILICON network device drivers.
34
#
45

56
ccflags-y := -Idrivers/net/ethernet/hisilicon/hns3
67

78
obj-$(CONFIG_HNS3_HCLGE) += hclge.o
8-
hclge-objs = hclge_main.o hclge_cmd.o hclge_mdio.o hclge_tm.o
9+
hclge-objs = hclge_main.o hclge_cmd.o hclge_mdio.o hclge_tm.o hclge_mbx.o
910

1011
hclge-$(CONFIG_HNS3_DCB) += hclge_dcb.o
11-
12-
obj-$(CONFIG_HNS3_ENET) += hns3.o
13-
hns3-objs = hns3_enet.o hns3_ethtool.o
14-
15-
hns3-$(CONFIG_HNS3_DCB) += hns3_dcbnl.o

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