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airliedairlied
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Merge tag 'drm-intel-fixes-2019-03-28' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
drm/i915 fixes for v5.2-rc3: - fix mmap range checks - fix gvt ppgtt mm LRU list access races - fix selftest error pointer check - fix a macro definition (pre-emptive for potential further backports) - fix one AML SKU ULX status Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87sgv6ao7a.fsf@intel.com
2 parents ee41c2d + 26cdaac commit 0271ab1

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8 files changed

+41
-14
lines changed

8 files changed

+41
-14
lines changed

‎drivers/gpu/drm/i915/gvt/cmd_parser.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1441,7 +1441,7 @@ static inline int cmd_address_audit(struct parser_exec_state *s,
14411441
}
14421442

14431443
if (index_mode) {
1444-
if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1444+
if (guest_gma >= I915_GTT_PAGE_SIZE) {
14451445
ret = -EFAULT;
14461446
goto err;
14471447
}

‎drivers/gpu/drm/i915/gvt/gtt.c

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1882,7 +1882,11 @@ struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
18821882
}
18831883

18841884
list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1885+
1886+
mutex_lock(&gvt->gtt.ppgtt_mm_lock);
18851887
list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1888+
mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
1889+
18861890
return mm;
18871891
}
18881892

@@ -1967,9 +1971,10 @@ int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
19671971
if (ret)
19681972
return ret;
19691973

1974+
mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
19701975
list_move_tail(&mm->ppgtt_mm.lru_list,
19711976
&mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
1972-
1977+
mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
19731978
}
19741979

19751980
return 0;
@@ -1980,16 +1985,20 @@ static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
19801985
struct intel_vgpu_mm *mm;
19811986
struct list_head *pos, *n;
19821987

1988+
mutex_lock(&gvt->gtt.ppgtt_mm_lock);
1989+
19831990
list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
19841991
mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.lru_list);
19851992

19861993
if (atomic_read(&mm->pincount))
19871994
continue;
19881995

19891996
list_del_init(&mm->ppgtt_mm.lru_list);
1997+
mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
19901998
invalidate_ppgtt_mm(mm);
19911999
return 1;
19922000
}
2001+
mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
19932002
return 0;
19942003
}
19952004

@@ -2659,6 +2668,7 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
26592668
}
26602669
}
26612670
INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2671+
mutex_init(&gvt->gtt.ppgtt_mm_lock);
26622672
return 0;
26632673
}
26642674

@@ -2699,7 +2709,9 @@ void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
26992709
list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
27002710
mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
27012711
if (mm->type == INTEL_GVT_MM_PPGTT) {
2712+
mutex_lock(&vgpu->gvt->gtt.ppgtt_mm_lock);
27022713
list_del_init(&mm->ppgtt_mm.lru_list);
2714+
mutex_unlock(&vgpu->gvt->gtt.ppgtt_mm_lock);
27032715
if (mm->ppgtt_mm.shadowed)
27042716
invalidate_ppgtt_mm(mm);
27052717
}

‎drivers/gpu/drm/i915/gvt/gtt.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,7 @@ struct intel_gvt_gtt {
8888
void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
8989
struct list_head oos_page_use_list_head;
9090
struct list_head oos_page_free_list_head;
91+
struct mutex ppgtt_mm_lock;
9192
struct list_head ppgtt_mm_lru_list_head;
9293

9394
struct page *scratch_page;

‎drivers/gpu/drm/i915/gvt/mmio_context.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -132,6 +132,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
132132

133133
{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
134134
{RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
135+
{RCS, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
135136

136137
{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
137138
{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */

‎drivers/gpu/drm/i915/gvt/scheduler.c

Lines changed: 20 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -346,7 +346,7 @@ static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
346346
int i = 0;
347347

348348
if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed)
349-
return -1;
349+
return -EINVAL;
350350

351351
if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
352352
px_dma(&ppgtt->pml4) = mm->ppgtt_mm.shadow_pdps[0];
@@ -410,12 +410,6 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
410410
if (workload->shadow)
411411
return 0;
412412

413-
ret = set_context_ppgtt_from_shadow(workload, shadow_ctx);
414-
if (ret < 0) {
415-
gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
416-
return ret;
417-
}
418-
419413
/* pin shadow context by gvt even the shadow context will be pinned
420414
* when i915 alloc request. That is because gvt will update the guest
421415
* context from shadow context when workload is completed, and at that
@@ -678,6 +672,9 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
678672
{
679673
struct intel_vgpu *vgpu = workload->vgpu;
680674
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
675+
struct intel_vgpu_submission *s = &vgpu->submission;
676+
struct i915_gem_context *shadow_ctx = s->shadow_ctx;
677+
struct i915_request *rq;
681678
int ring_id = workload->ring_id;
682679
int ret;
683680

@@ -687,6 +684,12 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
687684
mutex_lock(&vgpu->vgpu_lock);
688685
mutex_lock(&dev_priv->drm.struct_mutex);
689686

687+
ret = set_context_ppgtt_from_shadow(workload, shadow_ctx);
688+
if (ret < 0) {
689+
gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
690+
goto err_req;
691+
}
692+
690693
ret = intel_gvt_workload_req_alloc(workload);
691694
if (ret)
692695
goto err_req;
@@ -703,6 +706,14 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
703706

704707
ret = prepare_workload(workload);
705708
out:
709+
if (ret) {
710+
/* We might still need to add request with
711+
* clean ctx to retire it properly..
712+
*/
713+
rq = fetch_and_zero(&workload->req);
714+
i915_request_put(rq);
715+
}
716+
706717
if (!IS_ERR_OR_NULL(workload->req)) {
707718
gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
708719
ring_id, workload->req);
@@ -739,7 +750,8 @@ static struct intel_vgpu_workload *pick_next_workload(
739750
goto out;
740751
}
741752

742-
if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
753+
if (!scheduler->current_vgpu->active ||
754+
list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
743755
goto out;
744756

745757
/*

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2346,7 +2346,8 @@ static inline unsigned int i915_sg_segment_size(void)
23462346
INTEL_DEVID(dev_priv) == 0x5915 || \
23472347
INTEL_DEVID(dev_priv) == 0x591E)
23482348
#define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
2349-
INTEL_DEVID(dev_priv) == 0x87C0)
2349+
INTEL_DEVID(dev_priv) == 0x87C0 || \
2350+
INTEL_DEVID(dev_priv) == 0x87CA)
23502351
#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
23512352
INTEL_INFO(dev_priv)->gt == 2)
23522353
#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2863,7 +2863,7 @@ enum i915_power_well_id {
28632863
#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
28642864
#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
28652865
#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
2866-
#define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
2866+
#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
28672867

28682868
#define GEN11_EU_DISABLE _MMIO(0x9134)
28692869
#define GEN11_EU_DIS_MASK 0xFF
@@ -9243,7 +9243,7 @@ enum skl_power_gate {
92439243
#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \
92449244
_TRANS_DDI_FUNC_CTL2_A)
92459245
#define PORT_SYNC_MODE_ENABLE (1 << 4)
9246-
#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) < 0)
9246+
#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) << 0)
92479247
#define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0)
92489248
#define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0
92499249

‎drivers/gpu/drm/i915/selftests/i915_gem_evict.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -455,7 +455,7 @@ static int igt_evict_contexts(void *arg)
455455
struct i915_gem_context *ctx;
456456

457457
ctx = live_context(i915, file);
458-
if (!ctx)
458+
if (IS_ERR(ctx))
459459
break;
460460

461461
/* We will need some GGTT space for the rq's context */

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