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tomeuvMichael Turquette
tomeuv
authored and
Michael Turquette
committed
clk: Make clk API return per-user struct clk instances
Moves clock state to struct clk_core, but takes care to change as little API as possible. struct clk_hw still has a pointer to a struct clk, which is the implementation's per-user clk instance, for backwards compatibility. The struct clk that clk_get_parent() returns isn't owned by the caller, but by the clock implementation, so the former shouldn't call clk_put() on it. Because some boards in mach-omap2 still register clocks statically, their clock registration had to be updated to take into account that the clock information is stored in struct clk_core now. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: adapted clk_has_parent to struct clk_core applied OMAP3+ DPLL fix from Tero & Tony]
1 parent af0f349 commit 035a61c

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9 files changed

+602
-303
lines changed

9 files changed

+602
-303
lines changed

‎arch/arm/mach-omap2/cclock3xxx_data.c

Lines changed: 73 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
8282
OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
8383
OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
8484

85-
DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
85+
DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck_core, 0x0,
8686
OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
8787
OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
8888

@@ -132,7 +132,7 @@ static struct clk_hw_omap dpll3_ck_hw = {
132132

133133
DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
134134

135-
DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
135+
DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck_core, 0x0,
136136
OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
137137
OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
138138
OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
@@ -149,12 +149,12 @@ static const struct clk_ops core_ck_ops = {};
149149
DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
150150
DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
151151

152-
DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
152+
DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck_core, 0x0,
153153
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
154154
OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
155155
CLK_DIVIDER_ONE_BASED, NULL);
156156

157-
DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
157+
DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick_core, 0x0,
158158
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
159159
OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
160160
CLK_DIVIDER_ONE_BASED, NULL);
@@ -275,9 +275,9 @@ static struct clk_hw_omap dpll1_ck_hw = {
275275

276276
DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
277277

278-
DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
278+
DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck_core, 0x0, 2, 1);
279279

280-
DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
280+
DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck_core, 0x0,
281281
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
282282
OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
283283
OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
@@ -292,7 +292,7 @@ static const char *mpu_ck_parent_names[] = {
292292
DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
293293
DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
294294

295-
DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
295+
DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck_core, 0x0,
296296
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
297297
OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
298298
0x0, NULL);
@@ -424,7 +424,7 @@ static const struct clk_div_table dpll4_mx_ck_div_table[] = {
424424
{ .div = 0 },
425425
};
426426

427-
DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
427+
DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
428428
OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
429429
OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
430430
CLK_DIVIDER_ONE_BASED, NULL);
@@ -466,7 +466,7 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = {
466466
DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
467467
dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
468468

469-
static struct clk dpll4_m5x2_ck_3630 = {
469+
static struct clk_core dpll4_m5x2_ck_3630_core = {
470470
.name = "dpll4_m5x2_ck",
471471
.hw = &dpll4_m5x2_ck_hw.hw,
472472
.parent_names = dpll4_m5x2_ck_parent_names,
@@ -475,6 +475,10 @@ static struct clk dpll4_m5x2_ck_3630 = {
475475
.flags = CLK_SET_RATE_PARENT,
476476
};
477477

478+
static struct clk dpll4_m5x2_ck_3630 = {
479+
.core = &dpll4_m5x2_ck_3630_core,
480+
};
481+
478482
static struct clk cam_mclk;
479483

480484
static const char *cam_mclk_parent_names[] = {
@@ -490,7 +494,7 @@ static struct clk_hw_omap cam_mclk_hw = {
490494
.clkdm_name = "cam_clkdm",
491495
};
492496

493-
static struct clk cam_mclk = {
497+
static struct clk_core cam_mclk_core = {
494498
.name = "cam_mclk",
495499
.hw = &cam_mclk_hw.hw,
496500
.parent_names = cam_mclk_parent_names,
@@ -499,6 +503,10 @@ static struct clk cam_mclk = {
499503
.flags = CLK_SET_RATE_PARENT,
500504
};
501505

506+
static struct clk cam_mclk = {
507+
.core = &cam_mclk_core,
508+
};
509+
502510
static const struct clksel_rate clkout2_src_core_rates[] = {
503511
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
504512
{ .div = 0 }
@@ -514,7 +522,7 @@ static const struct clksel_rate clkout2_src_96m_rates[] = {
514522
{ .div = 0 }
515523
};
516524

517-
DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
525+
DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
518526
OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
519527
OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
520528
CLK_DIVIDER_ONE_BASED, NULL);
@@ -538,14 +546,18 @@ static struct clk_hw_omap dpll4_m2x2_ck_hw = {
538546

539547
DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
540548

541-
static struct clk dpll4_m2x2_ck_3630 = {
549+
static struct clk_core dpll4_m2x2_ck_3630_core = {
542550
.name = "dpll4_m2x2_ck",
543551
.hw = &dpll4_m2x2_ck_hw.hw,
544552
.parent_names = dpll4_m2x2_ck_parent_names,
545553
.num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
546554
.ops = &dpll4_m5x2_ck_3630_ops,
547555
};
548556

557+
static struct clk dpll4_m2x2_ck_3630 = {
558+
.core = &dpll4_m2x2_ck_3630_core,
559+
};
560+
549561
static struct clk omap_96m_alwon_fck;
550562

551563
static const char *omap_96m_alwon_fck_parent_names[] = {
@@ -570,7 +582,7 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
570582
{ .div = 0 }
571583
};
572584

573-
DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
585+
DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
574586
OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
575587
OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
576588
0, dpll4_mx_ck_div_table, NULL);
@@ -594,14 +606,18 @@ static struct clk_hw_omap dpll4_m3x2_ck_hw = {
594606

595607
DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
596608

597-
static struct clk dpll4_m3x2_ck_3630 = {
609+
static struct clk_core dpll4_m3x2_ck_3630_core = {
598610
.name = "dpll4_m3x2_ck",
599611
.hw = &dpll4_m3x2_ck_hw.hw,
600612
.parent_names = dpll4_m3x2_ck_parent_names,
601613
.num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
602614
.ops = &dpll4_m5x2_ck_3630_ops,
603615
};
604616

617+
static struct clk dpll4_m3x2_ck_3630 = {
618+
.core = &dpll4_m3x2_ck_3630_core,
619+
};
620+
605621
static const char *omap_54m_fck_parent_names[] = {
606622
"dpll4_m3x2_ck", "sys_altclk",
607623
};
@@ -677,7 +693,8 @@ static struct clk_hw_omap omap_48m_fck_hw = {
677693

678694
DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
679695

680-
DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
696+
DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck_core, 0x0,
697+
1, 4);
681698

682699
static struct clk core_12m_fck;
683700

@@ -723,7 +740,8 @@ static const char *core_l3_ick_parent_names[] = {
723740
DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
724741
DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
725742

726-
DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
743+
DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck_core, 0x0,
744+
2, 1);
727745

728746
static struct clk corex2_fck;
729747

@@ -809,7 +827,7 @@ static struct clk_hw_omap des2_ick_hw = {
809827

810828
DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
811829

812-
DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
830+
DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck_core, 0x0,
813831
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
814832
OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
815833
CLK_DIVIDER_ONE_BASED, NULL);
@@ -852,18 +870,18 @@ static struct clk_hw_omap dpll2_ck_hw = {
852870

853871
DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
854872

855-
DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
873+
DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck_core, 0x0,
856874
OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
857875
OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
858876
CLK_DIVIDER_ONE_BASED, NULL);
859877

860-
DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
878+
DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck_core, 0x0,
861879
OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
862880
OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
863881
OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
864882
CLK_DIVIDER_ONE_BASED, NULL);
865883

866-
DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
884+
DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck_core, 0x0,
867885
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
868886
OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
869887
CLK_DIVIDER_ONE_BASED, NULL);
@@ -887,17 +905,21 @@ static struct clk_hw_omap dpll3_m3x2_ck_hw = {
887905

888906
DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
889907

890-
static struct clk dpll3_m3x2_ck_3630 = {
908+
static struct clk_core dpll3_m3x2_ck_3630_core = {
891909
.name = "dpll3_m3x2_ck",
892910
.hw = &dpll3_m3x2_ck_hw.hw,
893911
.parent_names = dpll3_m3x2_ck_parent_names,
894912
.num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
895913
.ops = &dpll4_m5x2_ck_3630_ops,
896914
};
897915

898-
DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
916+
static struct clk dpll3_m3x2_ck_3630 = {
917+
.core = &dpll3_m3x2_ck_3630_core,
918+
};
919+
920+
DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck_core, 0x0, 2, 1);
899921

900-
DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
922+
DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
901923
OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
902924
OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
903925
0, dpll4_mx_ck_div_table, NULL);
@@ -922,7 +944,7 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = {
922944
DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
923945
dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
924946

925-
static struct clk dpll4_m4x2_ck_3630 = {
947+
static struct clk_core dpll4_m4x2_ck_3630_core = {
926948
.name = "dpll4_m4x2_ck",
927949
.hw = &dpll4_m4x2_ck_hw.hw,
928950
.parent_names = dpll4_m4x2_ck_parent_names,
@@ -931,7 +953,11 @@ static struct clk dpll4_m4x2_ck_3630 = {
931953
.flags = CLK_SET_RATE_PARENT,
932954
};
933955

934-
DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
956+
static struct clk dpll4_m4x2_ck_3630 = {
957+
.core = &dpll4_m4x2_ck_3630_core,
958+
};
959+
960+
DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
935961
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
936962
OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
937963
CLK_DIVIDER_ONE_BASED, NULL);
@@ -955,15 +981,19 @@ static struct clk_hw_omap dpll4_m6x2_ck_hw = {
955981

956982
DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
957983

958-
static struct clk dpll4_m6x2_ck_3630 = {
984+
static struct clk_core dpll4_m6x2_ck_3630_core = {
959985
.name = "dpll4_m6x2_ck",
960986
.hw = &dpll4_m6x2_ck_hw.hw,
961987
.parent_names = dpll4_m6x2_ck_parent_names,
962988
.num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
963989
.ops = &dpll4_m5x2_ck_3630_ops,
964990
};
965991

966-
DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
992+
static struct clk dpll4_m6x2_ck_3630 = {
993+
.core = &dpll4_m6x2_ck_3630_core,
994+
};
995+
996+
DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck_core, 0x0, 2, 1);
967997

968998
static struct dpll_data dpll5_dd = {
969999
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
@@ -1000,7 +1030,7 @@ static struct clk_hw_omap dpll5_ck_hw = {
10001030

10011031
DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
10021032

1003-
DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
1033+
DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck_core, 0x0,
10041034
OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
10051035
OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
10061036
CLK_DIVIDER_ONE_BASED, NULL);
@@ -1247,7 +1277,7 @@ static struct clk_hw_omap emu_src_ck_hw = {
12471277

12481278
DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
12491279

1250-
DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1280+
DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
12511281
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
12521282
OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
12531283
CLK_DIVIDER_ONE_BASED, NULL);
@@ -1298,7 +1328,7 @@ static struct clk_hw_omap gfx_l3_ck_hw = {
12981328

12991329
DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
13001330

1301-
DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1331+
DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick_core, 0x0,
13021332
OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
13031333
OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
13041334
CLK_DIVIDER_ONE_BASED, NULL);
@@ -2498,14 +2528,18 @@ static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
24982528
.clksel_mask = OMAP3630_CLKSEL_96M_MASK,
24992529
};
25002530

2501-
static struct clk omap_96m_alwon_fck_3630 = {
2531+
static struct clk_core omap_96m_alwon_fck_3630_core = {
25022532
.name = "omap_96m_alwon_fck",
25032533
.hw = &omap_96m_alwon_fck_3630_hw.hw,
25042534
.parent_names = omap_96m_alwon_fck_3630_parent_names,
25052535
.num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
25062536
.ops = &omap_96m_alwon_fck_3630_ops,
25072537
};
25082538

2539+
static struct clk omap_96m_alwon_fck_3630 = {
2540+
.core = &omap_96m_alwon_fck_3630_core,
2541+
};
2542+
25092543
static struct clk omapctrl_ick;
25102544

25112545
static struct clk_hw_omap omapctrl_ick_hw = {
@@ -2521,12 +2555,12 @@ static struct clk_hw_omap omapctrl_ick_hw = {
25212555

25222556
DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
25232557

2524-
DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2558+
DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
25252559
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
25262560
OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
25272561
CLK_DIVIDER_ONE_BASED, NULL);
25282562

2529-
DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2563+
DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
25302564
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
25312565
OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
25322566
CLK_DIVIDER_ONE_BASED, NULL);
@@ -2558,7 +2592,7 @@ static struct clk_hw_omap pka_ick_hw = {
25582592

25592593
DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
25602594

2561-
DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2595+
DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick_core, 0x0,
25622596
OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
25632597
OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
25642598
CLK_DIVIDER_ONE_BASED, NULL);
@@ -2819,10 +2853,10 @@ DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
28192853
ssi_ssr_fck_3430es1_ops);
28202854

28212855
DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2822-
&ssi_ssr_fck_3430es1, 0x0, 1, 2);
2856+
&ssi_ssr_fck_3430es1_core, 0x0, 1, 2);
28232857

28242858
DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2825-
&ssi_ssr_fck_3430es2, 0x0, 1, 2);
2859+
&ssi_ssr_fck_3430es2_core, 0x0, 1, 2);
28262860

28272861
static struct clk sys_clkout1;
28282862

@@ -2840,7 +2874,7 @@ static struct clk_hw_omap sys_clkout1_hw = {
28402874

28412875
DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
28422876

2843-
DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2877+
DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck_core, 0x0,
28442878
OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
28452879
OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
28462880

@@ -2849,7 +2883,8 @@ DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
28492883
OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
28502884
0x0, NULL);
28512885

2852-
DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2886+
DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck_core,
2887+
0x0,
28532888
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
28542889
OMAP3430_CLKSEL_TRACECLK_SHIFT,
28552890
OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);

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