MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.

Markos Chandras · ralfbaechle · commit 038b0f536e45 · 2015-08-26T15:23:14.000+02:00
The CMGCRBase register (CP0, 15, 3) register is 64-bit on MIPS64 so we change its type to unsigned long. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10644/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
@@ -20,7 +20,7 @@ int mips_cm_is64;
 phys_addr_t __mips_cm_phys_base(void)
 {
 	u32 config3 = read_c0_config3();
-	u32 cmgcr;
+	unsigned long cmgcr;
 
 	/* Check the CMGCRBase register is implemented */
 	if (!(config3 & MIPS_CONF3_CMGCR))

Original file line number	Diff line number	Diff line change
`@@ -20,7 +20,7 @@ int mips_cm_is64;`
`20`	`20`	`phys_addr_t __mips_cm_phys_base(void)`
`21`	`21`	`{`
`22`	`22`	`u32 config3 = read_c0_config3();`
`23`		`- u32 cmgcr;`
	`23`	`+ unsigned long cmgcr;`
`24`	`24`
`25`	`25`	`/* Check the CMGCRBase register is implemented */`
`26`	`26`	`if (!(config3 & MIPS_CONF3_CMGCR))`