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westeri
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gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation
We added acpi_gpiochip_pin_to_gpio_offset() because there was a need to translate from ACPI GpioIo/GpioInt number to Linux GPIO number in the Cherryview pinctrl driver. This translation is necessary because Cherryview has gaps in the pin list and the driver used continuous GPIO number space in Linux side as follows: created GPIO range 0->7 ==> INT33FF:03 PIN 0->7 created GPIO range 8->19 ==> INT33FF:03 PIN 15->26 created GPIO range 20->25 ==> INT33FF:03 PIN 30->35 created GPIO range 26->33 ==> INT33FF:03 PIN 45->52 created GPIO range 34->43 ==> INT33FF:03 PIN 60->69 created GPIO range 44->54 ==> INT33FF:03 PIN 75->85 For example when ACPI GpioInt resource refers to GPIO 81 (SDMMC3_CD_B) we translate from pin 81 to the corresponding Linux GPIO number, which is 50. This number is then used when the GPIO is accessed through gpiolib. It turns out, this is not necessary at all. We can just pass 1:1 mapping between Linux GPIO numbers and pin numbers (including gaps) and the pinctrl core handles all the details automatically: created GPIO range 0->7 ==> INT33FF:03 PIN 0->7 created GPIO range 15->26 ==> INT33FF:03 PIN 15->26 created GPIO range 30->35 ==> INT33FF:03 PIN 30->35 created GPIO range 45->52 ==> INT33FF:03 PIN 45->52 created GPIO range 60->69 ==> INT33FF:03 PIN 60->69 created GPIO range 75->85 ==> INT33FF:03 PIN 75->85 Here GPIO 81 is exactly same than the hardware pin 81 (SDMMC3_CD_B). As an added bonus this simplifies both the ACPI GPIO core code and the Cherryview pinctrl driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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‎drivers/gpio/gpiolib-acpi.c

Lines changed: 2 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -58,58 +58,6 @@ static int acpi_gpiochip_find(struct gpio_chip *gc, void *data)
5858
return ACPI_HANDLE(gc->parent) == data;
5959
}
6060

61-
#ifdef CONFIG_PINCTRL
62-
/**
63-
* acpi_gpiochip_pin_to_gpio_offset() - translates ACPI GPIO to Linux GPIO
64-
* @gdev: GPIO device
65-
* @pin: ACPI GPIO pin number from GpioIo/GpioInt resource
66-
*
67-
* Function takes ACPI GpioIo/GpioInt pin number as a parameter and
68-
* translates it to a corresponding offset suitable to be passed to a
69-
* GPIO controller driver.
70-
*
71-
* Typically the returned offset is same as @pin, but if the GPIO
72-
* controller uses pin controller and the mapping is not contiguous the
73-
* offset might be different.
74-
*/
75-
static int acpi_gpiochip_pin_to_gpio_offset(struct gpio_device *gdev, int pin)
76-
{
77-
struct gpio_pin_range *pin_range;
78-
79-
/* If there are no ranges in this chip, use 1:1 mapping */
80-
if (list_empty(&gdev->pin_ranges))
81-
return pin;
82-
83-
list_for_each_entry(pin_range, &gdev->pin_ranges, node) {
84-
const struct pinctrl_gpio_range *range = &pin_range->range;
85-
int i;
86-
87-
if (range->pins) {
88-
for (i = 0; i < range->npins; i++) {
89-
if (range->pins[i] == pin)
90-
return range->base + i - gdev->base;
91-
}
92-
} else {
93-
if (pin >= range->pin_base &&
94-
pin < range->pin_base + range->npins) {
95-
unsigned gpio_base;
96-
97-
gpio_base = range->base - gdev->base;
98-
return gpio_base + pin - range->pin_base;
99-
}
100-
}
101-
}
102-
103-
return -EINVAL;
104-
}
105-
#else
106-
static inline int acpi_gpiochip_pin_to_gpio_offset(struct gpio_device *gdev,
107-
int pin)
108-
{
109-
return pin;
110-
}
111-
#endif
112-
11361
/**
11462
* acpi_get_gpiod() - Translate ACPI GPIO pin to GPIO descriptor usable with GPIO API
11563
* @path: ACPI GPIO controller full path name, (e.g. "\\_SB.GPO1")
@@ -125,7 +73,6 @@ static struct gpio_desc *acpi_get_gpiod(char *path, int pin)
12573
struct gpio_chip *chip;
12674
acpi_handle handle;
12775
acpi_status status;
128-
int offset;
12976

13077
status = acpi_get_handle(NULL, path, &handle);
13178
if (ACPI_FAILURE(status))
@@ -135,11 +82,7 @@ static struct gpio_desc *acpi_get_gpiod(char *path, int pin)
13582
if (!chip)
13683
return ERR_PTR(-EPROBE_DEFER);
13784

138-
offset = acpi_gpiochip_pin_to_gpio_offset(chip->gpiodev, pin);
139-
if (offset < 0)
140-
return ERR_PTR(offset);
141-
142-
return gpiochip_get_desc(chip, offset);
85+
return gpiochip_get_desc(chip, pin);
14386
}
14487

14588
static irqreturn_t acpi_gpio_irq_handler(int irq, void *data)
@@ -216,10 +159,6 @@ static acpi_status acpi_gpiochip_request_interrupt(struct acpi_resource *ares,
216159
if (!handler)
217160
return AE_OK;
218161

219-
pin = acpi_gpiochip_pin_to_gpio_offset(chip->gpiodev, pin);
220-
if (pin < 0)
221-
return AE_BAD_PARAMETER;
222-
223162
desc = gpiochip_request_own_desc(chip, pin, "ACPI:Event");
224163
if (IS_ERR(desc)) {
225164
dev_err(chip->parent, "Failed to request GPIO\n");
@@ -852,12 +791,6 @@ acpi_gpio_adr_space_handler(u32 function, acpi_physical_address address,
852791
struct gpio_desc *desc;
853792
bool found;
854793

855-
pin = acpi_gpiochip_pin_to_gpio_offset(chip->gpiodev, pin);
856-
if (pin < 0) {
857-
status = AE_BAD_PARAMETER;
858-
goto out;
859-
}
860-
861794
mutex_lock(&achip->conn_lock);
862795

863796
found = false;
@@ -990,11 +923,7 @@ static struct gpio_desc *acpi_gpiochip_parse_own_gpio(
990923
if (ret < 0)
991924
return ERR_PTR(ret);
992925

993-
ret = acpi_gpiochip_pin_to_gpio_offset(chip->gpiodev, gpios[0]);
994-
if (ret < 0)
995-
return ERR_PTR(ret);
996-
997-
desc = gpiochip_get_desc(chip, ret);
926+
desc = gpiochip_get_desc(chip, gpios[0]);
998927
if (IS_ERR(desc))
999928
return desc;
1000929

‎drivers/pinctrl/intel/pinctrl-cherryview.c

Lines changed: 20 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -131,10 +131,8 @@ struct chv_gpio_pinrange {
131131
* @ngroups: Number of groups
132132
* @functions: All functions in this community
133133
* @nfunctions: Number of functions
134-
* @ngpios: Number of GPIOs in this community
135134
* @gpio_ranges: An array of GPIO ranges in this community
136135
* @ngpio_ranges: Number of GPIO ranges
137-
* @ngpios: Total number of GPIOs in this community
138136
* @nirqs: Total number of IRQs this community can generate
139137
*/
140138
struct chv_community {
@@ -147,7 +145,6 @@ struct chv_community {
147145
size_t nfunctions;
148146
const struct chv_gpio_pinrange *gpio_ranges;
149147
size_t ngpio_ranges;
150-
size_t ngpios;
151148
size_t nirqs;
152149
acpi_adr_space_type acpi_space_id;
153150
};
@@ -399,7 +396,6 @@ static const struct chv_community southwest_community = {
399396
.nfunctions = ARRAY_SIZE(southwest_functions),
400397
.gpio_ranges = southwest_gpio_ranges,
401398
.ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
402-
.ngpios = ARRAY_SIZE(southwest_pins),
403399
/*
404400
* Southwest community can benerate GPIO interrupts only for the
405401
* first 8 interrupts. The upper half (8-15) can only be used to
@@ -489,7 +485,6 @@ static const struct chv_community north_community = {
489485
.npins = ARRAY_SIZE(north_pins),
490486
.gpio_ranges = north_gpio_ranges,
491487
.ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
492-
.ngpios = ARRAY_SIZE(north_pins),
493488
/*
494489
* North community can generate GPIO interrupts only for the first
495490
* 8 interrupts. The upper half (8-15) can only be used to trigger
@@ -538,7 +533,6 @@ static const struct chv_community east_community = {
538533
.npins = ARRAY_SIZE(east_pins),
539534
.gpio_ranges = east_gpio_ranges,
540535
.ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
541-
.ngpios = ARRAY_SIZE(east_pins),
542536
.nirqs = 16,
543537
.acpi_space_id = 0x93,
544538
};
@@ -665,7 +659,6 @@ static const struct chv_community southeast_community = {
665659
.nfunctions = ARRAY_SIZE(southeast_functions),
666660
.gpio_ranges = southeast_gpio_ranges,
667661
.ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
668-
.ngpios = ARRAY_SIZE(southeast_pins),
669662
.nirqs = 16,
670663
.acpi_space_id = 0x94,
671664
};
@@ -1253,21 +1246,14 @@ static struct pinctrl_desc chv_pinctrl_desc = {
12531246
.owner = THIS_MODULE,
12541247
};
12551248

1256-
static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl,
1257-
unsigned offset)
1258-
{
1259-
return pctrl->community->pins[offset].number;
1260-
}
1261-
12621249
static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
12631250
{
12641251
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1265-
int pin = chv_gpio_offset_to_pin(pctrl, offset);
12661252
unsigned long flags;
12671253
u32 ctrl0, cfg;
12681254

12691255
raw_spin_lock_irqsave(&chv_lock, flags);
1270-
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1256+
ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
12711257
raw_spin_unlock_irqrestore(&chv_lock, flags);
12721258

12731259
cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
@@ -1281,14 +1267,13 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
12811267
static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
12821268
{
12831269
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1284-
unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
12851270
unsigned long flags;
12861271
void __iomem *reg;
12871272
u32 ctrl0;
12881273

12891274
raw_spin_lock_irqsave(&chv_lock, flags);
12901275

1291-
reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1276+
reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
12921277
ctrl0 = readl(reg);
12931278

12941279
if (value)
@@ -1304,12 +1289,11 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
13041289
static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
13051290
{
13061291
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1307-
unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
13081292
u32 ctrl0, direction;
13091293
unsigned long flags;
13101294

13111295
raw_spin_lock_irqsave(&chv_lock, flags);
1312-
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1296+
ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
13131297
raw_spin_unlock_irqrestore(&chv_lock, flags);
13141298

13151299
direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
@@ -1345,7 +1329,7 @@ static void chv_gpio_irq_ack(struct irq_data *d)
13451329
{
13461330
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
13471331
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1348-
int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1332+
int pin = irqd_to_hwirq(d);
13491333
u32 intr_line;
13501334

13511335
raw_spin_lock(&chv_lock);
@@ -1362,7 +1346,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
13621346
{
13631347
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
13641348
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1365-
int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1349+
int pin = irqd_to_hwirq(d);
13661350
u32 value, intr_line;
13671351
unsigned long flags;
13681352

@@ -1407,8 +1391,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
14071391
if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
14081392
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
14091393
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1410-
unsigned offset = irqd_to_hwirq(d);
1411-
int pin = chv_gpio_offset_to_pin(pctrl, offset);
1394+
unsigned pin = irqd_to_hwirq(d);
14121395
irq_flow_handler_t handler;
14131396
unsigned long flags;
14141397
u32 intsel, value;
@@ -1426,7 +1409,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
14261409

14271410
if (!pctrl->intr_lines[intsel]) {
14281411
irq_set_handler_locked(d, handler);
1429-
pctrl->intr_lines[intsel] = offset;
1412+
pctrl->intr_lines[intsel] = pin;
14301413
}
14311414
raw_spin_unlock_irqrestore(&chv_lock, flags);
14321415
}
@@ -1439,8 +1422,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
14391422
{
14401423
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
14411424
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1442-
unsigned offset = irqd_to_hwirq(d);
1443-
int pin = chv_gpio_offset_to_pin(pctrl, offset);
1425+
unsigned pin = irqd_to_hwirq(d);
14441426
unsigned long flags;
14451427
u32 value;
14461428

@@ -1486,7 +1468,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
14861468
value &= CHV_PADCTRL0_INTSEL_MASK;
14871469
value >>= CHV_PADCTRL0_INTSEL_SHIFT;
14881470

1489-
pctrl->intr_lines[value] = offset;
1471+
pctrl->intr_lines[value] = pin;
14901472

14911473
if (type & IRQ_TYPE_EDGE_BOTH)
14921474
irq_set_handler_locked(d, handle_edge_irq);
@@ -1576,12 +1558,12 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
15761558
const struct chv_gpio_pinrange *range;
15771559
struct gpio_chip *chip = &pctrl->chip;
15781560
bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1579-
int ret, i, offset;
1580-
int irq_base;
1561+
const struct chv_community *community = pctrl->community;
1562+
int ret, i, irq_base;
15811563

15821564
*chip = chv_gpio_chip;
15831565

1584-
chip->ngpio = pctrl->community->ngpios;
1566+
chip->ngpio = community->pins[community->npins - 1].number + 1;
15851567
chip->label = dev_name(pctrl->dev);
15861568
chip->parent = pctrl->dev;
15871569
chip->base = -1;
@@ -1593,30 +1575,29 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
15931575
return ret;
15941576
}
15951577

1596-
for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) {
1597-
range = &pctrl->community->gpio_ranges[i];
1598-
ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset,
1599-
range->base, range->npins);
1578+
for (i = 0; i < community->ngpio_ranges; i++) {
1579+
range = &community->gpio_ranges[i];
1580+
ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1581+
range->base, range->base,
1582+
range->npins);
16001583
if (ret) {
16011584
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
16021585
return ret;
16031586
}
1604-
1605-
offset += range->npins;
16061587
}
16071588

16081589
/* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1609-
for (i = 0; i < pctrl->community->npins; i++) {
1590+
for (i = 0; i < community->npins; i++) {
16101591
const struct pinctrl_pin_desc *desc;
16111592
u32 intsel;
16121593

1613-
desc = &pctrl->community->pins[i];
1594+
desc = &community->pins[i];
16141595

16151596
intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
16161597
intsel &= CHV_PADCTRL0_INTSEL_MASK;
16171598
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
16181599

1619-
if (need_valid_mask && intsel >= pctrl->community->nirqs)
1600+
if (need_valid_mask && intsel >= community->nirqs)
16201601
clear_bit(i, chip->irq.valid_mask);
16211602
}
16221603

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