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bsingharorampe
bsingharora
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mpe
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powerpc/mm: Trace tlbie(l) instructions
Add a trace point for tlbie(l) (Translation Lookaside Buffer Invalidate Entry (Local)) instructions. The tlbie instruction has changed over the years, so not all versions accept the same operands. Use the ISA v3 field operands because they are the most verbose, we may change them in future. Example output: qemu-system-ppc-5371 [016] 1412.369519: tlbie: tlbie with lpid 0, local 1, rb=67bd8900174c11c1, rs=0, ric=0 prs=0 r=0 Signed-off-by: Balbir Singh <bsingharora@gmail.com> [mpe: Add some missing trace_tlbie()s, reword change log] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
1 parent d4cfb11 commit 0428491

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+67
-4
lines changed

7 files changed

+67
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lines changed

‎arch/powerpc/include/asm/trace.h

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,6 +168,39 @@ TRACE_EVENT(hash_fault,
168168
__entry->addr, __entry->access, __entry->trap)
169169
);
170170

171+
172+
TRACE_EVENT(tlbie,
173+
174+
TP_PROTO(unsigned long lpid, unsigned long local, unsigned long rb,
175+
unsigned long rs, unsigned long ric, unsigned long prs,
176+
unsigned long r),
177+
TP_ARGS(lpid, local, rb, rs, ric, prs, r),
178+
TP_STRUCT__entry(
179+
__field(unsigned long, lpid)
180+
__field(unsigned long, local)
181+
__field(unsigned long, rb)
182+
__field(unsigned long, rs)
183+
__field(unsigned long, ric)
184+
__field(unsigned long, prs)
185+
__field(unsigned long, r)
186+
),
187+
188+
TP_fast_assign(
189+
__entry->lpid = lpid;
190+
__entry->local = local;
191+
__entry->rb = rb;
192+
__entry->rs = rs;
193+
__entry->ric = ric;
194+
__entry->prs = prs;
195+
__entry->r = r;
196+
),
197+
198+
TP_printk("lpid=%ld, local=%ld, rb=0x%lx, rs=0x%lx, ric=0x%lx, "
199+
"prs=0x%lx, r=0x%lx", __entry->lpid, __entry->local,
200+
__entry->rb, __entry->rs, __entry->ric, __entry->prs,
201+
__entry->r)
202+
);
203+
171204
#endif /* _TRACE_POWERPC_H */
172205

173206
#undef TRACE_INCLUDE_PATH

‎arch/powerpc/kvm/book3s_hv_rm_mmu.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <linux/log2.h>
1616

1717
#include <asm/tlbflush.h>
18+
#include <asm/trace.h>
1819
#include <asm/kvm_ppc.h>
1920
#include <asm/kvm_book3s.h>
2021
#include <asm/book3s/64/mmu-hash.h>
@@ -443,17 +444,23 @@ static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues,
443444
cpu_relax();
444445
if (need_sync)
445446
asm volatile("ptesync" : : : "memory");
446-
for (i = 0; i < npages; ++i)
447+
for (i = 0; i < npages; ++i) {
447448
asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
448449
"r" (rbvalues[i]), "r" (kvm->arch.lpid));
450+
trace_tlbie(kvm->arch.lpid, 0, rbvalues[i],
451+
kvm->arch.lpid, 0, 0, 0);
452+
}
449453
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
450454
kvm->arch.tlbie_lock = 0;
451455
} else {
452456
if (need_sync)
453457
asm volatile("ptesync" : : : "memory");
454-
for (i = 0; i < npages; ++i)
458+
for (i = 0; i < npages; ++i) {
455459
asm volatile(PPC_TLBIEL(%0,%1,0,0,0) : :
456460
"r" (rbvalues[i]), "r" (0));
461+
trace_tlbie(kvm->arch.lpid, 1, rbvalues[i],
462+
0, 0, 0, 0);
463+
}
457464
asm volatile("ptesync" : : : "memory");
458465
}
459466
}

‎arch/powerpc/mm/hash_native_64.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323
#include <asm/mmu_context.h>
2424
#include <asm/pgtable.h>
2525
#include <asm/tlbflush.h>
26+
#include <asm/trace.h>
2627
#include <asm/tlb.h>
2728
#include <asm/cputable.h>
2829
#include <asm/udbg.h>
@@ -98,6 +99,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
9899
: "memory");
99100
break;
100101
}
102+
trace_tlbie(0, 0, va, 0, 0, 0, 0);
101103
}
102104

103105
static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
@@ -147,6 +149,7 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
147149
: "memory");
148150
break;
149151
}
152+
trace_tlbie(0, 1, va, 0, 0, 0, 0);
150153

151154
}
152155

‎arch/powerpc/mm/hash_utils_64.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -810,6 +810,8 @@ static void update_hid_for_hash(void)
810810
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
811811
: : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
812812
asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
813+
trace_tlbie(0, 0, rb, 0, 2, 0, 0);
814+
813815
/*
814816
* now switch the HID
815817
*/

‎arch/powerpc/mm/pgtable-radix.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include <asm/firmware.h>
2121
#include <asm/powernv.h>
2222
#include <asm/sections.h>
23+
#include <asm/trace.h>
2324

2425
#include <trace/events/thp.h>
2526

@@ -198,6 +199,7 @@ static void __init radix_init_pgtable(void)
198199
asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
199200
"r" (TLBIEL_INVAL_SET_LPID), "r" (0));
200201
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
202+
trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
201203
}
202204

203205
static void __init radix_init_partition_table(void)
@@ -324,6 +326,9 @@ static void update_hid_for_radix(void)
324326
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
325327
: : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
326328
asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
329+
trace_tlbie(0, 0, rb, 0, 2, 0, 1);
330+
trace_tlbie(0, 0, rb, 0, 2, 1, 1);
331+
327332
/*
328333
* now switch the HID
329334
*/

‎arch/powerpc/mm/pgtable_64.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@
4747
#include <asm/smp.h>
4848
#include <asm/machdep.h>
4949
#include <asm/tlb.h>
50+
#include <asm/trace.h>
5051
#include <asm/processor.h>
5152
#include <asm/cputable.h>
5253
#include <asm/sections.h>
@@ -477,12 +478,15 @@ void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
477478
* use of this partition ID was, not the new use.
478479
*/
479480
asm volatile("ptesync" : : : "memory");
480-
if (old & PATB_HR)
481+
if (old & PATB_HR) {
481482
asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :
482483
"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
483-
else
484+
trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
485+
} else {
484486
asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
485487
"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
488+
trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
489+
}
486490
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
487491
}
488492
EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry);

‎arch/powerpc/mm/tlb-radix.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616

1717
#include <asm/tlb.h>
1818
#include <asm/tlbflush.h>
19+
#include <asm/trace.h>
1920

2021

2122
#define RIC_FLUSH_TLB 0
@@ -35,6 +36,7 @@ static inline void __tlbiel_pid(unsigned long pid, int set,
3536

3637
asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
3738
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
39+
trace_tlbie(0, 1, rb, rs, ric, prs, r);
3840
}
3941

4042
/*
@@ -87,6 +89,7 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
8789
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
8890
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
8991
asm volatile("eieio; tlbsync; ptesync": : :"memory");
92+
trace_tlbie(0, 0, rb, rs, ric, prs, r);
9093
}
9194

9295
static inline void _tlbiel_va(unsigned long va, unsigned long pid,
@@ -104,6 +107,7 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
104107
asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
105108
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
106109
asm volatile("ptesync": : :"memory");
110+
trace_tlbie(0, 1, rb, rs, ric, prs, r);
107111
}
108112

109113
static inline void _tlbie_va(unsigned long va, unsigned long pid,
@@ -121,6 +125,7 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
121125
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
122126
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
123127
asm volatile("eieio; tlbsync; ptesync": : :"memory");
128+
trace_tlbie(0, 0, rb, rs, ric, prs, r);
124129
}
125130

126131
/*
@@ -377,6 +382,7 @@ void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
377382
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
378383
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
379384
asm volatile("eieio; tlbsync; ptesync": : :"memory");
385+
trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
380386
}
381387
EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
382388

@@ -394,6 +400,7 @@ void radix__flush_tlb_lpid(unsigned long lpid)
394400
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
395401
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
396402
asm volatile("eieio; tlbsync; ptesync": : :"memory");
403+
trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
397404
}
398405
EXPORT_SYMBOL(radix__flush_tlb_lpid);
399406

@@ -420,12 +427,14 @@ void radix__flush_tlb_all(void)
420427
*/
421428
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
422429
: : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
430+
trace_tlbie(0, 0, rb, rs, ric, prs, r);
423431
/*
424432
* now flush host entires by passing PRS = 0 and LPID == 0
425433
*/
426434
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
427435
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
428436
asm volatile("eieio; tlbsync; ptesync": : :"memory");
437+
trace_tlbie(0, 0, rb, 0, ric, prs, r);
429438
}
430439

431440
void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,

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