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Merge tag 'xtensa-20140830' of git://github.com/czankel/xtensa-linux
Pull Xtensa updates from Chris Zankel: "Xtensa improvements for 3.17: - support highmem on cores with aliasing data cache. Enable highmem on kc705 by default - simplify addition of new core variants (no need to modify Kconfig / Makefiles) - improve robustness of unaligned access handler and its interaction with window overflow/underflow exception handlers - deprecate atomic and spill registers syscalls - clean up Kconfig: remove orphan MATH_EMULATION, sort 'select' statements - wire up renameat2 syscall. Various fixes: - fix address checks in dma_{alloc,free}_coherent (runtime BUG) - fix access to THREAD_RA/THREAD_SP/THREAD_DS (debug build breakage) - fix TLBTEMP_BASE_2 region handling in fast_second_level_miss (runtime unrecoverable exception) - fix a6 and a7 handling in fast_syscall_xtensa (runtime userspace register clobbering) - fix kernel/user jump out of fast_unaligned (potential runtime unrecoverabl exception) - replace termios IOCTL code definitions with constants (userspace build breakage)" * tag 'xtensa-20140830' of git://github.com/czankel/xtensa-linux: (25 commits) xtensa: deprecate fast_xtensa and fast_spill_registers syscalls xtensa: don't allow overflow/underflow on unaligned stack xtensa: fix a6 and a7 handling in fast_syscall_xtensa xtensa: allow single-stepping through unaligned load/store xtensa: move invalid unaligned instruction handler closer to its users xtensa: make fast_unaligned store restartable xtensa: add double exception fixup handler for fast_unaligned xtensa: fix kernel/user jump out of fast_unaligned xtensa: configure kc705 for highmem xtensa: support highmem in aliasing cache flushing code xtensa: support aliasing cache in kmap xtensa: support aliasing cache in k[un]map_atomic xtensa: implement clear_user_highpage and copy_user_highpage xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss xtensa: allow fixmap and kmap span more than one page table xtensa: make fixmap region addressing grow with index xtensa: fix access to THREAD_RA/THREAD_SP/THREAD_DS xtensa: add renameat2 syscall xtensa: fix address checks in dma_{alloc,free}_coherent xtensa: replace IOCTL code definitions with constants ...
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‎arch/xtensa/Kconfig

Lines changed: 75 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -4,24 +4,23 @@ config ZONE_DMA
44
config XTENSA
55
def_bool y
66
select ARCH_WANT_FRAME_POINTERS
7-
select HAVE_IDE
8-
select GENERIC_ATOMIC64
9-
select GENERIC_CLOCKEVENTS
10-
select VIRT_TO_BUS
11-
select GENERIC_IRQ_SHOW
12-
select GENERIC_SCHED_CLOCK
13-
select MODULES_USE_ELF_RELA
14-
select GENERIC_PCI_IOMAP
157
select ARCH_WANT_IPC_PARSE_VERSION
168
select ARCH_WANT_OPTIONAL_GPIOLIB
179
select BUILDTIME_EXTABLE_SORT
1810
select CLONE_BACKWARDS
19-
select IRQ_DOMAIN
20-
select HAVE_OPROFILE
11+
select COMMON_CLK
12+
select GENERIC_ATOMIC64
13+
select GENERIC_CLOCKEVENTS
14+
select GENERIC_IRQ_SHOW
15+
select GENERIC_PCI_IOMAP
16+
select GENERIC_SCHED_CLOCK
2117
select HAVE_FUNCTION_TRACER
2218
select HAVE_IRQ_TIME_ACCOUNTING
19+
select HAVE_OPROFILE
2320
select HAVE_PERF_EVENTS
24-
select COMMON_CLK
21+
select IRQ_DOMAIN
22+
select MODULES_USE_ELF_RELA
23+
select VIRT_TO_BUS
2524
help
2625
Xtensa processors are 32-bit RISC machines designed by Tensilica
2726
primarily for embedded systems. These processors are both
@@ -62,7 +61,9 @@ config TRACE_IRQFLAGS_SUPPORT
6261
def_bool y
6362

6463
config MMU
65-
def_bool n
64+
bool
65+
default n if !XTENSA_VARIANT_CUSTOM
66+
default XTENSA_VARIANT_MMU if XTENSA_VARIANT_CUSTOM
6667

6768
config VARIANT_IRQ_SWITCH
6869
def_bool n
@@ -102,8 +103,40 @@ config XTENSA_VARIANT_S6000
102103
select VARIANT_IRQ_SWITCH
103104
select ARCH_REQUIRE_GPIOLIB
104105
select XTENSA_CALIBRATE_CCOUNT
106+
107+
config XTENSA_VARIANT_CUSTOM
108+
bool "Custom Xtensa processor configuration"
109+
select MAY_HAVE_SMP
110+
select HAVE_XTENSA_GPIO32
111+
help
112+
Select this variant to use a custom Xtensa processor configuration.
113+
You will be prompted for a processor variant CORENAME.
105114
endchoice
106115

116+
config XTENSA_VARIANT_CUSTOM_NAME
117+
string "Xtensa Processor Custom Core Variant Name"
118+
depends on XTENSA_VARIANT_CUSTOM
119+
help
120+
Provide the name of a custom Xtensa processor variant.
121+
This CORENAME selects arch/xtensa/variant/CORENAME.
122+
Dont forget you have to select MMU if you have one.
123+
124+
config XTENSA_VARIANT_NAME
125+
string
126+
default "dc232b" if XTENSA_VARIANT_DC232B
127+
default "dc233c" if XTENSA_VARIANT_DC233C
128+
default "fsf" if XTENSA_VARIANT_FSF
129+
default "s6000" if XTENSA_VARIANT_S6000
130+
default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
131+
132+
config XTENSA_VARIANT_MMU
133+
bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
134+
depends on XTENSA_VARIANT_CUSTOM
135+
default y
136+
help
137+
Build a Conventional Kernel with full MMU support,
138+
ie: it supports a TLB with auto-loading, page protection.
139+
107140
config XTENSA_UNALIGNED_USER
108141
bool "Unaligned memory access in use space"
109142
help
@@ -156,13 +189,9 @@ config HOTPLUG_CPU
156189

157190
Say N if you want to disable CPU hotplug.
158191

159-
config MATH_EMULATION
160-
bool "Math emulation"
161-
help
162-
Can we use information of configuration file?
163-
164192
config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
165193
bool "Initialize Xtensa MMU inside the Linux kernel code"
194+
depends on MMU
166195
default y
167196
help
168197
Earlier version initialized the MMU in the exception vector
@@ -192,6 +221,7 @@ config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
192221

193222
config HIGHMEM
194223
bool "High Memory Support"
224+
depends on MMU
195225
help
196226
Linux can use the full amount of RAM in the system by
197227
default. However, the default MMUv2 setup only maps the
@@ -208,6 +238,32 @@ config HIGHMEM
208238

209239
If unsure, say Y.
210240

241+
config FAST_SYSCALL_XTENSA
242+
bool "Enable fast atomic syscalls"
243+
default n
244+
help
245+
fast_syscall_xtensa is a syscall that can make atomic operations
246+
on UP kernel when processor has no s32c1i support.
247+
248+
This syscall is deprecated. It may have issues when called with
249+
invalid arguments. It is provided only for backwards compatibility.
250+
Only enable it if your userspace software requires it.
251+
252+
If unsure, say N.
253+
254+
config FAST_SYSCALL_SPILL_REGISTERS
255+
bool "Enable spill registers syscall"
256+
default n
257+
help
258+
fast_syscall_spill_registers is a syscall that spills all active
259+
register windows of a calling userspace task onto its stack.
260+
261+
This syscall is deprecated. It may have issues when called with
262+
invalid arguments. It is provided only for backwards compatibility.
263+
Only enable it if your userspace software requires it.
264+
265+
If unsure, say N.
266+
211267
endmenu
212268

213269
config XTENSA_CALIBRATE_CCOUNT
@@ -250,12 +306,14 @@ config XTENSA_PLATFORM_ISS
250306

251307
config XTENSA_PLATFORM_XT2000
252308
bool "XT2000"
309+
select HAVE_IDE
253310
help
254311
XT2000 is the name of Tensilica's feature-rich emulation platform.
255312
This hardware is capable of running a full Linux distribution.
256313

257314
config XTENSA_PLATFORM_S6105
258315
bool "S6105"
316+
select HAVE_IDE
259317
select SERIAL_CONSOLE
260318
select NO_IOPORT_MAP
261319

‎arch/xtensa/Makefile

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
# for more details.
55
#
66
# Copyright (C) 2001 - 2005 Tensilica Inc.
7+
# Copyright (C) 2014 Cadence Design Systems Inc.
78
#
89
# This file is included by the global makefile so that you can add your own
910
# architecture-specific flags and dependencies. Remember to do have actions
@@ -13,11 +14,7 @@
1314
# Core configuration.
1415
# (Use VAR=<xtensa_config> to use another default compiler.)
1516

16-
variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf
17-
variant-$(CONFIG_XTENSA_VARIANT_DC232B) := dc232b
18-
variant-$(CONFIG_XTENSA_VARIANT_DC233C) := dc233c
19-
variant-$(CONFIG_XTENSA_VARIANT_S6000) := s6000
20-
variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom
17+
variant-y := $(patsubst "%",%,$(CONFIG_XTENSA_VARIANT_NAME))
2118

2219
VARIANT = $(variant-y)
2320
export VARIANT

‎arch/xtensa/boot/dts/kc705.dts

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,11 @@
44

55
/ {
66
compatible = "cdns,xtensa-kc705";
7+
chosen {
8+
bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000";
9+
};
710
memory@0 {
811
device_type = "memory";
9-
reg = <0x00000000 0x08000000>;
12+
reg = <0x00000000 0x38000000>;
1013
};
1114
};

‎arch/xtensa/configs/common_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,6 @@ CONFIG_XTENSA_ARCH_LINUX_BE=y
6666
CONFIG_MMU=y
6767
# CONFIG_XTENSA_UNALIGNED_USER is not set
6868
# CONFIG_PREEMPT is not set
69-
# CONFIG_MATH_EMULATION is not set
7069
# CONFIG_HIGHMEM is not set
7170

7271
#

‎arch/xtensa/configs/iss_defconfig

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,6 @@ CONFIG_XTENSA_VARIANT_FSF=y
146146
# CONFIG_XTENSA_VARIANT_S6000 is not set
147147
# CONFIG_XTENSA_UNALIGNED_USER is not set
148148
# CONFIG_PREEMPT is not set
149-
# CONFIG_MATH_EMULATION is not set
150149
CONFIG_XTENSA_CALIBRATE_CCOUNT=y
151150
CONFIG_SERIAL_CONSOLE=y
152151
CONFIG_XTENSA_ISS_NETWORK=y
@@ -308,7 +307,7 @@ CONFIG_MISC_DEVICES=y
308307
# EEPROM support
309308
#
310309
# CONFIG_EEPROM_93CX6 is not set
311-
CONFIG_HAVE_IDE=y
310+
# CONFIG_HAVE_IDE is not set
312311
# CONFIG_IDE is not set
313312

314313
#

‎arch/xtensa/configs/s6105_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,6 @@ CONFIG_VARIANT_IRQ_SWITCH=y
109109
CONFIG_XTENSA_VARIANT_S6000=y
110110
# CONFIG_XTENSA_UNALIGNED_USER is not set
111111
CONFIG_PREEMPT=y
112-
# CONFIG_MATH_EMULATION is not set
113112
# CONFIG_HIGHMEM is not set
114113
CONFIG_XTENSA_CALIBRATE_CCOUNT=y
115114
CONFIG_SERIAL_CONSOLE=y

‎arch/xtensa/include/asm/cacheflush.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737
* specials for cache aliasing:
3838
*
3939
* __flush_invalidate_dcache_page_alias(vaddr,paddr)
40+
* __invalidate_dcache_page_alias(vaddr,paddr)
4041
* __invalidate_icache_page_alias(vaddr,paddr)
4142
*/
4243

@@ -62,6 +63,7 @@ extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
6263

6364
#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
6465
extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
66+
extern void __invalidate_dcache_page_alias(unsigned long, unsigned long);
6567
#else
6668
static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
6769
unsigned long phys) { }

‎arch/xtensa/include/asm/fixmap.h

Lines changed: 26 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,8 @@
2323
* Here we define all the compile-time 'special' virtual
2424
* addresses. The point is to have a constant address at
2525
* compile time, but to set the physical address only
26-
* in the boot process. We allocate these special addresses
27-
* from the end of the consistent memory region backwards.
26+
* in the boot process. We allocate these special addresses
27+
* from the start of the consistent memory region upwards.
2828
* Also this lets us do fail-safe vmalloc(), we
2929
* can guarantee that these special addresses and
3030
* vmalloc()-ed addresses never overlap.
@@ -38,7 +38,8 @@ enum fixed_addresses {
3838
#ifdef CONFIG_HIGHMEM
3939
/* reserved pte's for temporary kernel mappings */
4040
FIX_KMAP_BEGIN,
41-
FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1,
41+
FIX_KMAP_END = FIX_KMAP_BEGIN +
42+
(KM_TYPE_NR * NR_CPUS * DCACHE_N_COLORS) - 1,
4243
#endif
4344
__end_of_fixed_addresses
4445
};
@@ -47,7 +48,28 @@ enum fixed_addresses {
4748
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
4849
#define FIXADDR_START ((FIXADDR_TOP - FIXADDR_SIZE) & PMD_MASK)
4950

50-
#include <asm-generic/fixmap.h>
51+
#define __fix_to_virt(x) (FIXADDR_START + ((x) << PAGE_SHIFT))
52+
#define __virt_to_fix(x) (((x) - FIXADDR_START) >> PAGE_SHIFT)
53+
54+
#ifndef __ASSEMBLY__
55+
/*
56+
* 'index to address' translation. If anyone tries to use the idx
57+
* directly without translation, we catch the bug with a NULL-deference
58+
* kernel oops. Illegal ranges of incoming indices are caught too.
59+
*/
60+
static __always_inline unsigned long fix_to_virt(const unsigned int idx)
61+
{
62+
BUILD_BUG_ON(idx >= __end_of_fixed_addresses);
63+
return __fix_to_virt(idx);
64+
}
65+
66+
static inline unsigned long virt_to_fix(const unsigned long vaddr)
67+
{
68+
BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
69+
return __virt_to_fix(vaddr);
70+
}
71+
72+
#endif
5173

5274
#define kmap_get_fixmap_pte(vaddr) \
5375
pte_offset_kernel( \

‎arch/xtensa/include/asm/highmem.h

Lines changed: 38 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,19 +12,55 @@
1212
#ifndef _XTENSA_HIGHMEM_H
1313
#define _XTENSA_HIGHMEM_H
1414

15+
#include <linux/wait.h>
1516
#include <asm/cacheflush.h>
1617
#include <asm/fixmap.h>
1718
#include <asm/kmap_types.h>
1819
#include <asm/pgtable.h>
1920

20-
#define PKMAP_BASE (FIXADDR_START - PMD_SIZE)
21-
#define LAST_PKMAP PTRS_PER_PTE
21+
#define PKMAP_BASE ((FIXADDR_START - \
22+
(LAST_PKMAP + 1) * PAGE_SIZE) & PMD_MASK)
23+
#define LAST_PKMAP (PTRS_PER_PTE * DCACHE_N_COLORS)
2224
#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
2325
#define PKMAP_NR(virt) (((virt) - PKMAP_BASE) >> PAGE_SHIFT)
2426
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
2527

2628
#define kmap_prot PAGE_KERNEL
2729

30+
#if DCACHE_WAY_SIZE > PAGE_SIZE
31+
#define get_pkmap_color get_pkmap_color
32+
static inline int get_pkmap_color(struct page *page)
33+
{
34+
return DCACHE_ALIAS(page_to_phys(page));
35+
}
36+
37+
extern unsigned int last_pkmap_nr_arr[];
38+
39+
static inline unsigned int get_next_pkmap_nr(unsigned int color)
40+
{
41+
last_pkmap_nr_arr[color] =
42+
(last_pkmap_nr_arr[color] + DCACHE_N_COLORS) & LAST_PKMAP_MASK;
43+
return last_pkmap_nr_arr[color] + color;
44+
}
45+
46+
static inline int no_more_pkmaps(unsigned int pkmap_nr, unsigned int color)
47+
{
48+
return pkmap_nr < DCACHE_N_COLORS;
49+
}
50+
51+
static inline int get_pkmap_entries_count(unsigned int color)
52+
{
53+
return LAST_PKMAP / DCACHE_N_COLORS;
54+
}
55+
56+
extern wait_queue_head_t pkmap_map_wait_arr[];
57+
58+
static inline wait_queue_head_t *get_pkmap_wait_queue_head(unsigned int color)
59+
{
60+
return pkmap_map_wait_arr + color;
61+
}
62+
#endif
63+
2864
extern pte_t *pkmap_page_table;
2965

3066
void *kmap_high(struct page *page);

‎arch/xtensa/include/asm/page.h

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,9 @@
7878
# define DCACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & DCACHE_ALIAS_MASK) == 0)
7979
#else
8080
# define DCACHE_ALIAS_ORDER 0
81+
# define DCACHE_ALIAS(a) ((void)(a), 0)
8182
#endif
83+
#define DCACHE_N_COLORS (1 << DCACHE_ALIAS_ORDER)
8284

8385
#if ICACHE_WAY_SIZE > PAGE_SIZE
8486
# define ICACHE_ALIAS_ORDER (ICACHE_WAY_SHIFT - PAGE_SHIFT)
@@ -134,6 +136,7 @@ static inline __attribute_const__ int get_order(unsigned long size)
134136
#endif
135137

136138
struct page;
139+
struct vm_area_struct;
137140
extern void clear_page(void *page);
138141
extern void copy_page(void *to, void *from);
139142

@@ -143,8 +146,15 @@ extern void copy_page(void *to, void *from);
143146
*/
144147

145148
#if DCACHE_WAY_SIZE > PAGE_SIZE
146-
extern void clear_user_page(void*, unsigned long, struct page*);
147-
extern void copy_user_page(void*, void*, unsigned long, struct page*);
149+
extern void clear_page_alias(void *vaddr, unsigned long paddr);
150+
extern void copy_page_alias(void *to, void *from,
151+
unsigned long to_paddr, unsigned long from_paddr);
152+
153+
#define clear_user_highpage clear_user_highpage
154+
void clear_user_highpage(struct page *page, unsigned long vaddr);
155+
#define __HAVE_ARCH_COPY_USER_HIGHPAGE
156+
void copy_user_highpage(struct page *to, struct page *from,
157+
unsigned long vaddr, struct vm_area_struct *vma);
148158
#else
149159
# define clear_user_page(page, vaddr, pg) clear_page(page)
150160
# define copy_user_page(to, from, vaddr, pg) copy_page(to, from)

‎arch/xtensa/include/asm/pgtable.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,12 @@
6767
#define VMALLOC_START 0xC0000000
6868
#define VMALLOC_END 0xC7FEFFFF
6969
#define TLBTEMP_BASE_1 0xC7FF0000
70-
#define TLBTEMP_BASE_2 0xC7FF8000
70+
#define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
71+
#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
72+
#define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
73+
#else
74+
#define TLBTEMP_SIZE ICACHE_WAY_SIZE
75+
#endif
7176

7277
/*
7378
* For the Xtensa architecture, the PTE layout is as follows:

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