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jbrun3tsuperna9999
jbrun3t
authored and
superna9999
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clk: meson: add fdiv clock gates
Fdiv fixed dividers clocks of the fixed_pll can actually gate independently. We never had an issue so far because these clocks were provided 'enabled' by the bootloader. Add these gates to enable/disable the clocks when required. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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6 files changed

+278
-33
lines changed

6 files changed

+278
-33
lines changed

‎drivers/clk/meson/axg.c

Lines changed: 85 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -299,61 +299,126 @@ static struct clk_regmap axg_hifi_pll = {
299299
},
300300
};
301301

302-
static struct clk_fixed_factor axg_fclk_div2 = {
302+
static struct clk_fixed_factor axg_fclk_div2_div = {
303303
.mult = 1,
304304
.div = 2,
305305
.hw.init = &(struct clk_init_data){
306-
.name = "fclk_div2",
306+
.name = "fclk_div2_div",
307307
.ops = &clk_fixed_factor_ops,
308308
.parent_names = (const char *[]){ "fixed_pll" },
309309
.num_parents = 1,
310310
},
311311
};
312312

313-
static struct clk_fixed_factor axg_fclk_div3 = {
313+
static struct clk_regmap axg_fclk_div2 = {
314+
.data = &(struct clk_regmap_gate_data){
315+
.offset = HHI_MPLL_CNTL6,
316+
.bit_idx = 27,
317+
},
318+
.hw.init = &(struct clk_init_data){
319+
.name = "fclk_div2",
320+
.ops = &clk_regmap_gate_ops,
321+
.parent_names = (const char *[]){ "fclk_div2_div" },
322+
.num_parents = 1,
323+
},
324+
};
325+
326+
static struct clk_fixed_factor axg_fclk_div3_div = {
314327
.mult = 1,
315328
.div = 3,
316329
.hw.init = &(struct clk_init_data){
317-
.name = "fclk_div3",
330+
.name = "fclk_div3_div",
318331
.ops = &clk_fixed_factor_ops,
319332
.parent_names = (const char *[]){ "fixed_pll" },
320333
.num_parents = 1,
321334
},
322335
};
323336

324-
static struct clk_fixed_factor axg_fclk_div4 = {
337+
static struct clk_regmap axg_fclk_div3 = {
338+
.data = &(struct clk_regmap_gate_data){
339+
.offset = HHI_MPLL_CNTL6,
340+
.bit_idx = 28,
341+
},
342+
.hw.init = &(struct clk_init_data){
343+
.name = "fclk_div3",
344+
.ops = &clk_regmap_gate_ops,
345+
.parent_names = (const char *[]){ "fclk_div3_div" },
346+
.num_parents = 1,
347+
},
348+
};
349+
350+
static struct clk_fixed_factor axg_fclk_div4_div = {
325351
.mult = 1,
326352
.div = 4,
327353
.hw.init = &(struct clk_init_data){
328-
.name = "fclk_div4",
354+
.name = "fclk_div4_div",
329355
.ops = &clk_fixed_factor_ops,
330356
.parent_names = (const char *[]){ "fixed_pll" },
331357
.num_parents = 1,
332358
},
333359
};
334360

335-
static struct clk_fixed_factor axg_fclk_div5 = {
361+
static struct clk_regmap axg_fclk_div4 = {
362+
.data = &(struct clk_regmap_gate_data){
363+
.offset = HHI_MPLL_CNTL6,
364+
.bit_idx = 29,
365+
},
366+
.hw.init = &(struct clk_init_data){
367+
.name = "fclk_div4",
368+
.ops = &clk_regmap_gate_ops,
369+
.parent_names = (const char *[]){ "fclk_div4_div" },
370+
.num_parents = 1,
371+
},
372+
};
373+
374+
static struct clk_fixed_factor axg_fclk_div5_div = {
336375
.mult = 1,
337376
.div = 5,
338377
.hw.init = &(struct clk_init_data){
339-
.name = "fclk_div5",
378+
.name = "fclk_div5_div",
340379
.ops = &clk_fixed_factor_ops,
341380
.parent_names = (const char *[]){ "fixed_pll" },
342381
.num_parents = 1,
343382
},
344383
};
345384

346-
static struct clk_fixed_factor axg_fclk_div7 = {
385+
static struct clk_regmap axg_fclk_div5 = {
386+
.data = &(struct clk_regmap_gate_data){
387+
.offset = HHI_MPLL_CNTL6,
388+
.bit_idx = 30,
389+
},
390+
.hw.init = &(struct clk_init_data){
391+
.name = "fclk_div5",
392+
.ops = &clk_regmap_gate_ops,
393+
.parent_names = (const char *[]){ "fclk_div5_div" },
394+
.num_parents = 1,
395+
},
396+
};
397+
398+
static struct clk_fixed_factor axg_fclk_div7_div = {
347399
.mult = 1,
348400
.div = 7,
349401
.hw.init = &(struct clk_init_data){
350-
.name = "fclk_div7",
402+
.name = "fclk_div7_div",
351403
.ops = &clk_fixed_factor_ops,
352404
.parent_names = (const char *[]){ "fixed_pll" },
353405
.num_parents = 1,
354406
},
355407
};
356408

409+
static struct clk_regmap axg_fclk_div7 = {
410+
.data = &(struct clk_regmap_gate_data){
411+
.offset = HHI_MPLL_CNTL6,
412+
.bit_idx = 31,
413+
},
414+
.hw.init = &(struct clk_init_data){
415+
.name = "fclk_div7",
416+
.ops = &clk_regmap_gate_ops,
417+
.parent_names = (const char *[]){ "fclk_div7_div" },
418+
.num_parents = 1,
419+
},
420+
};
421+
357422
static struct clk_regmap axg_mpll_prediv = {
358423
.data = &(struct clk_regmap_div_data){
359424
.offset = HHI_MPLL_CNTL5,
@@ -836,6 +901,11 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
836901
[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
837902
[CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
838903
[CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
904+
[CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
905+
[CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
906+
[CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
907+
[CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
908+
[CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
839909
[NR_CLKS] = NULL,
840910
},
841911
.num = NR_CLKS,
@@ -909,6 +979,11 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
909979
&axg_gp0_pll,
910980
&axg_hifi_pll,
911981
&axg_mpll_prediv,
982+
&axg_fclk_div2,
983+
&axg_fclk_div3,
984+
&axg_fclk_div4,
985+
&axg_fclk_div5,
986+
&axg_fclk_div7,
912987
};
913988

914989
static const struct of_device_id clkc_match_table[] = {

‎drivers/clk/meson/axg.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -122,8 +122,13 @@
122122
#define CLKID_MPLL2_DIV 67
123123
#define CLKID_MPLL3_DIV 68
124124
#define CLKID_MPLL_PREDIV 70
125+
#define CLKID_FCLK_DIV2_DIV 71
126+
#define CLKID_FCLK_DIV3_DIV 72
127+
#define CLKID_FCLK_DIV4_DIV 73
128+
#define CLKID_FCLK_DIV5_DIV 74
129+
#define CLKID_FCLK_DIV7_DIV 75
125130

126-
#define NR_CLKS 71
131+
#define NR_CLKS 76
127132

128133
/* include the CLKIDs that have been made part of the DT binding */
129134
#include <dt-bindings/clock/axg-clkc.h>

‎drivers/clk/meson/gxbb.c

Lines changed: 90 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -490,61 +490,126 @@ static struct clk_regmap gxl_gp0_pll = {
490490
},
491491
};
492492

493-
static struct clk_fixed_factor gxbb_fclk_div2 = {
493+
static struct clk_fixed_factor gxbb_fclk_div2_div = {
494494
.mult = 1,
495495
.div = 2,
496496
.hw.init = &(struct clk_init_data){
497-
.name = "fclk_div2",
497+
.name = "fclk_div2_div",
498498
.ops = &clk_fixed_factor_ops,
499499
.parent_names = (const char *[]){ "fixed_pll" },
500500
.num_parents = 1,
501501
},
502502
};
503503

504-
static struct clk_fixed_factor gxbb_fclk_div3 = {
504+
static struct clk_regmap gxbb_fclk_div2 = {
505+
.data = &(struct clk_regmap_gate_data){
506+
.offset = HHI_MPLL_CNTL6,
507+
.bit_idx = 27,
508+
},
509+
.hw.init = &(struct clk_init_data){
510+
.name = "fclk_div2",
511+
.ops = &clk_regmap_gate_ops,
512+
.parent_names = (const char *[]){ "fclk_div2_div" },
513+
.num_parents = 1,
514+
},
515+
};
516+
517+
static struct clk_fixed_factor gxbb_fclk_div3_div = {
505518
.mult = 1,
506519
.div = 3,
507520
.hw.init = &(struct clk_init_data){
508-
.name = "fclk_div3",
521+
.name = "fclk_div3_div",
509522
.ops = &clk_fixed_factor_ops,
510523
.parent_names = (const char *[]){ "fixed_pll" },
511524
.num_parents = 1,
512525
},
513526
};
514527

515-
static struct clk_fixed_factor gxbb_fclk_div4 = {
528+
static struct clk_regmap gxbb_fclk_div3 = {
529+
.data = &(struct clk_regmap_gate_data){
530+
.offset = HHI_MPLL_CNTL6,
531+
.bit_idx = 28,
532+
},
533+
.hw.init = &(struct clk_init_data){
534+
.name = "fclk_div3",
535+
.ops = &clk_regmap_gate_ops,
536+
.parent_names = (const char *[]){ "fclk_div3_div" },
537+
.num_parents = 1,
538+
},
539+
};
540+
541+
static struct clk_fixed_factor gxbb_fclk_div4_div = {
516542
.mult = 1,
517543
.div = 4,
518544
.hw.init = &(struct clk_init_data){
519-
.name = "fclk_div4",
545+
.name = "fclk_div4_div",
520546
.ops = &clk_fixed_factor_ops,
521547
.parent_names = (const char *[]){ "fixed_pll" },
522548
.num_parents = 1,
523549
},
524550
};
525551

526-
static struct clk_fixed_factor gxbb_fclk_div5 = {
552+
static struct clk_regmap gxbb_fclk_div4 = {
553+
.data = &(struct clk_regmap_gate_data){
554+
.offset = HHI_MPLL_CNTL6,
555+
.bit_idx = 29,
556+
},
557+
.hw.init = &(struct clk_init_data){
558+
.name = "fclk_div4",
559+
.ops = &clk_regmap_gate_ops,
560+
.parent_names = (const char *[]){ "fclk_div4_div" },
561+
.num_parents = 1,
562+
},
563+
};
564+
565+
static struct clk_fixed_factor gxbb_fclk_div5_div = {
527566
.mult = 1,
528567
.div = 5,
529568
.hw.init = &(struct clk_init_data){
530-
.name = "fclk_div5",
569+
.name = "fclk_div5_div",
531570
.ops = &clk_fixed_factor_ops,
532571
.parent_names = (const char *[]){ "fixed_pll" },
533572
.num_parents = 1,
534573
},
535574
};
536575

537-
static struct clk_fixed_factor gxbb_fclk_div7 = {
576+
static struct clk_regmap gxbb_fclk_div5 = {
577+
.data = &(struct clk_regmap_gate_data){
578+
.offset = HHI_MPLL_CNTL6,
579+
.bit_idx = 30,
580+
},
581+
.hw.init = &(struct clk_init_data){
582+
.name = "fclk_div5",
583+
.ops = &clk_regmap_gate_ops,
584+
.parent_names = (const char *[]){ "fclk_div5_div" },
585+
.num_parents = 1,
586+
},
587+
};
588+
589+
static struct clk_fixed_factor gxbb_fclk_div7_div = {
538590
.mult = 1,
539591
.div = 7,
540592
.hw.init = &(struct clk_init_data){
541-
.name = "fclk_div7",
593+
.name = "fclk_div7_div",
542594
.ops = &clk_fixed_factor_ops,
543595
.parent_names = (const char *[]){ "fixed_pll" },
544596
.num_parents = 1,
545597
},
546598
};
547599

600+
static struct clk_regmap gxbb_fclk_div7 = {
601+
.data = &(struct clk_regmap_gate_data){
602+
.offset = HHI_MPLL_CNTL6,
603+
.bit_idx = 31,
604+
},
605+
.hw.init = &(struct clk_init_data){
606+
.name = "fclk_div7",
607+
.ops = &clk_regmap_gate_ops,
608+
.parent_names = (const char *[]){ "fclk_div7_div" },
609+
.num_parents = 1,
610+
},
611+
};
612+
548613
static struct clk_regmap gxbb_mpll_prediv = {
549614
.data = &(struct clk_regmap_div_data){
550615
.offset = HHI_MPLL_CNTL5,
@@ -1718,6 +1783,11 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
17181783
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
17191784
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
17201785
[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
1786+
[CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
1787+
[CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
1788+
[CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1789+
[CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1790+
[CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
17211791
[NR_CLKS] = NULL,
17221792
},
17231793
.num = NR_CLKS,
@@ -1869,6 +1939,11 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
18691939
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
18701940
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
18711941
[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
1942+
[CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
1943+
[CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
1944+
[CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1945+
[CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1946+
[CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
18721947
[NR_CLKS] = NULL,
18731948
},
18741949
.num = NR_CLKS,
@@ -2022,6 +2097,11 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
20222097
&gxbb_fixed_pll,
20232098
&gxbb_sys_pll,
20242099
&gxbb_mpll_prediv,
2100+
&gxbb_fclk_div2,
2101+
&gxbb_fclk_div3,
2102+
&gxbb_fclk_div4,
2103+
&gxbb_fclk_div5,
2104+
&gxbb_fclk_div7,
20252105
};
20262106

20272107
struct clkc_data {

‎drivers/clk/meson/gxbb.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -199,8 +199,13 @@
199199
#define CLKID_MPLL1_DIV 143
200200
#define CLKID_MPLL2_DIV 144
201201
#define CLKID_MPLL_PREDIV 145
202+
#define CLKID_FCLK_DIV2_DIV 146
203+
#define CLKID_FCLK_DIV3_DIV 147
204+
#define CLKID_FCLK_DIV4_DIV 148
205+
#define CLKID_FCLK_DIV5_DIV 149
206+
#define CLKID_FCLK_DIV7_DIV 150
202207

203-
#define NR_CLKS 146
208+
#define NR_CLKS 151
204209

205210
/* include the CLKIDs that have been made part of the DT binding */
206211
#include <dt-bindings/clock/gxbb-clkc.h>

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