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Russell Kinglinusw
Russell King
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linusw
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gpio: sa1100: convert to use IO accessors
Use IO accessors to access the SA1100 registers rather than accessing them directly. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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‎drivers/gpio/gpio-sa1100.c

Lines changed: 124 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -16,89 +16,125 @@
1616
#include <mach/hardware.h>
1717
#include <mach/irqs.h>
1818

19+
struct sa1100_gpio_chip {
20+
struct gpio_chip chip;
21+
void __iomem *membase;
22+
int irqbase;
23+
u32 irqmask;
24+
u32 irqrising;
25+
u32 irqfalling;
26+
u32 irqwake;
27+
};
28+
29+
#define sa1100_gpio_chip(x) container_of(x, struct sa1100_gpio_chip, chip)
30+
31+
enum {
32+
R_GPLR = 0x00,
33+
R_GPDR = 0x04,
34+
R_GPSR = 0x08,
35+
R_GPCR = 0x0c,
36+
R_GRER = 0x10,
37+
R_GFER = 0x14,
38+
R_GEDR = 0x18,
39+
R_GAFR = 0x1c,
40+
};
41+
1942
static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
2043
{
21-
return !!(GPLR & GPIO_GPIO(offset));
44+
return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) &
45+
BIT(offset);
2246
}
2347

2448
static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2549
{
26-
if (value)
27-
GPSR = GPIO_GPIO(offset);
28-
else
29-
GPCR = GPIO_GPIO(offset);
50+
int reg = value ? R_GPSR : R_GPCR;
51+
52+
writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);
3053
}
3154

3255
static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
3356
{
57+
void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
3458
unsigned long flags;
3559

3660
local_irq_save(flags);
37-
GPDR &= ~GPIO_GPIO(offset);
61+
writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr);
3862
local_irq_restore(flags);
63+
3964
return 0;
4065
}
4166

4267
static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
4368
{
69+
void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
4470
unsigned long flags;
4571

4672
local_irq_save(flags);
4773
sa1100_gpio_set(chip, offset, value);
48-
GPDR |= GPIO_GPIO(offset);
74+
writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr);
4975
local_irq_restore(flags);
76+
5077
return 0;
5178
}
5279

5380
static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
5481
{
55-
return IRQ_GPIO0 + offset;
82+
return sa1100_gpio_chip(chip)->irqbase + offset;
5683
}
5784

58-
static struct gpio_chip sa1100_gpio_chip = {
59-
.label = "gpio",
60-
.direction_input = sa1100_direction_input,
61-
.direction_output = sa1100_direction_output,
62-
.set = sa1100_gpio_set,
63-
.get = sa1100_gpio_get,
64-
.to_irq = sa1100_to_irq,
65-
.base = 0,
66-
.ngpio = GPIO_MAX + 1,
85+
static struct sa1100_gpio_chip sa1100_gpio_chip = {
86+
.chip = {
87+
.label = "gpio",
88+
.direction_input = sa1100_direction_input,
89+
.direction_output = sa1100_direction_output,
90+
.set = sa1100_gpio_set,
91+
.get = sa1100_gpio_get,
92+
.to_irq = sa1100_to_irq,
93+
.base = 0,
94+
.ngpio = GPIO_MAX + 1,
95+
},
96+
.membase = (void *)&GPLR,
97+
.irqbase = IRQ_GPIO0,
6798
};
6899

69100
/*
70101
* SA1100 GPIO edge detection for IRQs:
71102
* IRQs are generated on Falling-Edge, Rising-Edge, or both.
72103
* Use this instead of directly setting GRER/GFER.
73104
*/
74-
static int GPIO_IRQ_rising_edge;
75-
static int GPIO_IRQ_falling_edge;
76-
static int GPIO_IRQ_mask;
77-
static int GPIO_IRQ_wake;
105+
static void sa1100_update_edge_regs(struct sa1100_gpio_chip *sgc)
106+
{
107+
void *base = sgc->membase;
108+
u32 grer, gfer;
109+
110+
grer = sgc->irqrising & sgc->irqmask;
111+
gfer = sgc->irqfalling & sgc->irqmask;
112+
113+
writel_relaxed(grer, base + R_GRER);
114+
writel_relaxed(gfer, base + R_GFER);
115+
}
78116

79117
static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
80118
{
81-
unsigned int mask;
82-
83-
mask = BIT(d->hwirq);
119+
struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
120+
unsigned int mask = BIT(d->hwirq);
84121

85122
if (type == IRQ_TYPE_PROBE) {
86-
if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
123+
if ((sgc->irqrising | sgc->irqfalling) & mask)
87124
return 0;
88125
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
89126
}
90127

91128
if (type & IRQ_TYPE_EDGE_RISING)
92-
GPIO_IRQ_rising_edge |= mask;
129+
sgc->irqrising |= mask;
93130
else
94-
GPIO_IRQ_rising_edge &= ~mask;
131+
sgc->irqrising &= ~mask;
95132
if (type & IRQ_TYPE_EDGE_FALLING)
96-
GPIO_IRQ_falling_edge |= mask;
133+
sgc->irqfalling |= mask;
97134
else
98-
GPIO_IRQ_falling_edge &= ~mask;
135+
sgc->irqfalling &= ~mask;
99136

100-
GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
101-
GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
137+
sa1100_update_edge_regs(sgc);
102138

103139
return 0;
104140
}
@@ -108,37 +144,40 @@ static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
108144
*/
109145
static void sa1100_gpio_ack(struct irq_data *d)
110146
{
111-
GEDR = BIT(d->hwirq);
147+
struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
148+
149+
writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR);
112150
}
113151

114152
static void sa1100_gpio_mask(struct irq_data *d)
115153
{
154+
struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
116155
unsigned int mask = BIT(d->hwirq);
117156

118-
GPIO_IRQ_mask &= ~mask;
157+
sgc->irqmask &= ~mask;
119158

120-
GRER &= ~mask;
121-
GFER &= ~mask;
159+
sa1100_update_edge_regs(sgc);
122160
}
123161

124162
static void sa1100_gpio_unmask(struct irq_data *d)
125163
{
164+
struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
126165
unsigned int mask = BIT(d->hwirq);
127166

128-
GPIO_IRQ_mask |= mask;
167+
sgc->irqmask |= mask;
129168

130-
GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
131-
GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
169+
sa1100_update_edge_regs(sgc);
132170
}
133171

134172
static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
135173
{
174+
struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
136175
int ret = sa11x0_gpio_set_wake(d->hwirq, on);
137176
if (!ret) {
138177
if (on)
139-
GPIO_IRQ_wake |= BIT(d->hwirq);
178+
sgc->irqwake |= BIT(d->hwirq);
140179
else
141-
GPIO_IRQ_wake &= ~BIT(d->hwirq);
180+
sgc->irqwake &= ~BIT(d->hwirq);
142181
}
143182
return ret;
144183
}
@@ -158,8 +197,10 @@ static struct irq_chip sa1100_gpio_irq_chip = {
158197
static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
159198
unsigned int irq, irq_hw_number_t hwirq)
160199
{
161-
irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip,
162-
handle_edge_irq);
200+
struct sa1100_gpio_chip *sgc = d->host_data;
201+
202+
irq_set_chip_data(irq, sgc);
203+
irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip, handle_edge_irq);
163204
irq_set_probe(irq);
164205

165206
return 0;
@@ -179,48 +220,52 @@ static struct irq_domain *sa1100_gpio_irqdomain;
179220
*/
180221
static void sa1100_gpio_handler(struct irq_desc *desc)
181222
{
223+
struct sa1100_gpio_chip *sgc = irq_desc_get_handler_data(desc);
182224
unsigned int irq, mask;
225+
void __iomem *gedr = sgc->membase + R_GEDR;
183226

184-
mask = GEDR;
227+
mask = readl_relaxed(gedr);
185228
do {
186229
/*
187230
* clear down all currently active IRQ sources.
188231
* We will be processing them all.
189232
*/
190-
GEDR = mask;
233+
writel_relaxed(mask, gedr);
191234

192-
irq = IRQ_GPIO0;
235+
irq = sgc->irqbase;
193236
do {
194237
if (mask & 1)
195238
generic_handle_irq(irq);
196239
mask >>= 1;
197240
irq++;
198241
} while (mask);
199242

200-
mask = GEDR;
243+
mask = readl_relaxed(gedr);
201244
} while (mask);
202245
}
203246

204247
static int sa1100_gpio_suspend(void)
205248
{
249+
struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
250+
206251
/*
207252
* Set the appropriate edges for wakeup.
208253
*/
209-
GRER = GPIO_IRQ_wake & GPIO_IRQ_rising_edge;
210-
GFER = GPIO_IRQ_wake & GPIO_IRQ_falling_edge;
254+
writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER);
255+
writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER);
211256

212257
/*
213258
* Clear any pending GPIO interrupts.
214259
*/
215-
GEDR = GEDR;
260+
writel_relaxed(readl_relaxed(sgc->membase + R_GEDR),
261+
sgc->membase + R_GEDR);
216262

217263
return 0;
218264
}
219265

220266
static void sa1100_gpio_resume(void)
221267
{
222-
GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
223-
GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
268+
sa1100_update_edge_regs(&sa1100_gpio_chip);
224269
}
225270

226271
static struct syscore_ops sa1100_gpio_syscore_ops = {
@@ -236,36 +281,40 @@ static int __init sa1100_gpio_init_devicefs(void)
236281

237282
device_initcall(sa1100_gpio_init_devicefs);
238283

284+
static const int sa1100_gpio_irqs[] __initconst = {
285+
/* Install handlers for GPIO 0-10 edge detect interrupts */
286+
IRQ_GPIO0_SC,
287+
IRQ_GPIO1_SC,
288+
IRQ_GPIO2_SC,
289+
IRQ_GPIO3_SC,
290+
IRQ_GPIO4_SC,
291+
IRQ_GPIO5_SC,
292+
IRQ_GPIO6_SC,
293+
IRQ_GPIO7_SC,
294+
IRQ_GPIO8_SC,
295+
IRQ_GPIO9_SC,
296+
IRQ_GPIO10_SC,
297+
/* Install handler for GPIO 11-27 edge detect interrupts */
298+
IRQ_GPIO11_27,
299+
};
300+
239301
void __init sa1100_init_gpio(void)
240302
{
303+
struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
304+
int i;
305+
241306
/* clear all GPIO edge detects */
242-
GFER = 0;
243-
GRER = 0;
244-
GEDR = -1;
307+
writel_relaxed(0, sgc->membase + R_GFER);
308+
writel_relaxed(0, sgc->membase + R_GRER);
309+
writel_relaxed(-1, sgc->membase + R_GEDR);
245310

246-
gpiochip_add_data(&sa1100_gpio_chip, NULL);
311+
gpiochip_add_data(&sa1100_gpio_chip.chip, NULL);
247312

248313
sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
249314
28, IRQ_GPIO0,
250-
&sa1100_gpio_irqdomain_ops, NULL);
251-
252-
/*
253-
* Install handlers for GPIO 0-10 edge detect interrupts
254-
*/
255-
irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler);
256-
irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler);
257-
irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler);
258-
irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler);
259-
irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler);
260-
irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler);
261-
irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler);
262-
irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler);
263-
irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler);
264-
irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler);
265-
irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler);
266-
/*
267-
* Install handler for GPIO 11-27 edge detect interrupts
268-
*/
269-
irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler);
315+
&sa1100_gpio_irqdomain_ops, sgc);
270316

317+
for (i = 0; i < ARRAY_SIZE(sa1100_gpio_irqs); i++)
318+
irq_set_chained_handler_and_data(sa1100_gpio_irqs[i],
319+
sa1100_gpio_handler, sgc);
271320
}

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