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Min LiNipaLocal
Min Li
authored and
NipaLocal
committed
ptp: clockmatrix: support 32-bit address space
We used to assume 0x2010xxxx address. Now that we need to access 0x2011xxxx address, we need to support read/write the whole 32-bit address space. Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: NipaLocal <nipa@local>
1 parent 57fc4f4 commit 0911849

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3 files changed

+317
-316
lines changed

3 files changed

+317
-316
lines changed

‎drivers/ptp/ptp_clockmatrix.c

Lines changed: 30 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -41,17 +41,17 @@ module_param(firmware, charp, 0);
4141
static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
4242

4343
static inline int idtcm_read(struct idtcm *idtcm,
44-
u16 module,
45-
u16 regaddr,
44+
u32 module,
45+
u32 regaddr,
4646
u8 *buf,
4747
u16 count)
4848
{
4949
return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count);
5050
}
5151

5252
static inline int idtcm_write(struct idtcm *idtcm,
53-
u16 module,
54-
u16 regaddr,
53+
u32 module,
54+
u32 regaddr,
5555
u8 *buf,
5656
u16 count)
5757
{
@@ -62,16 +62,17 @@ static int contains_full_configuration(struct idtcm *idtcm,
6262
const struct firmware *fw)
6363
{
6464
struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
65-
u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
65+
u16 scratch = SCSR_ADDR(IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH));
66+
u16 gpio_control = SCSR_ADDR(GPIO_USER_CONTROL);
6667
s32 full_count;
6768
s32 count = 0;
6869
u16 regaddr;
6970
u8 loaddr;
7071
s32 len;
7172

7273
/* 4 bytes skipped every 0x80 */
73-
full_count = (scratch - GPIO_USER_CONTROL) -
74-
((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4;
74+
full_count = (scratch - gpio_control) -
75+
((scratch >> 7) - (gpio_control >> 7)) * 4;
7576

7677
/* If the firmware contains 'full configuration' SM_RESET can be used
7778
* to ensure proper configuration.
@@ -88,7 +89,7 @@ static int contains_full_configuration(struct idtcm *idtcm,
8889
rec++;
8990

9091
/* Top (status registers) and bottom are read-only */
91-
if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
92+
if (regaddr < gpio_control || regaddr >= scratch)
9293
continue;
9394

9495
/* Page size 128, last 4 bytes of page skipped */
@@ -506,8 +507,8 @@ static int _sync_pll_output(struct idtcm *idtcm,
506507
{
507508
int err;
508509
u8 val;
509-
u16 sync_ctrl0;
510-
u16 sync_ctrl1;
510+
u32 sync_ctrl0;
511+
u32 sync_ctrl1;
511512
u8 temp;
512513

513514
if (qn == 0 && qn_plus_1 == 0)
@@ -553,11 +554,11 @@ static int _sync_pll_output(struct idtcm *idtcm,
553554
val = SYNCTRL1_MASTER_SYNC_RST;
554555

555556
/* Place master sync in reset */
556-
err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
557+
err = idtcm_write(idtcm, sync_ctrl1, 0, &val, sizeof(val));
557558
if (err)
558559
return err;
559560

560-
err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
561+
err = idtcm_write(idtcm, sync_ctrl0, 0, &sync_src, sizeof(sync_src));
561562
if (err)
562563
return err;
563564

@@ -570,57 +571,57 @@ static int _sync_pll_output(struct idtcm *idtcm,
570571
if (qn_plus_1)
571572
val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
572573

573-
err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
574+
err = idtcm_write(idtcm, sync_ctrl1, 0, &val, sizeof(val));
574575
if (err)
575576
return err;
576577

577578
/* PLL5 can have OUT8 as second additional output. */
578579
if (pll == 5 && qn_plus_1 != 0) {
579-
err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
580+
err = idtcm_read(idtcm, HW_Q8_CTRL_SPARE, 0,
580581
&temp, sizeof(temp));
581582
if (err)
582583
return err;
583584

584585
temp &= ~(Q9_TO_Q8_SYNC_TRIG);
585586

586-
err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
587+
err = idtcm_write(idtcm, HW_Q8_CTRL_SPARE, 0,
587588
&temp, sizeof(temp));
588589
if (err)
589590
return err;
590591

591592
temp |= Q9_TO_Q8_SYNC_TRIG;
592593

593-
err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
594+
err = idtcm_write(idtcm, HW_Q8_CTRL_SPARE, 0,
594595
&temp, sizeof(temp));
595596
if (err)
596597
return err;
597598
}
598599

599600
/* PLL6 can have OUT11 as second additional output. */
600601
if (pll == 6 && qn_plus_1 != 0) {
601-
err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
602+
err = idtcm_read(idtcm, HW_Q11_CTRL_SPARE, 0,
602603
&temp, sizeof(temp));
603604
if (err)
604605
return err;
605606

606607
temp &= ~(Q10_TO_Q11_SYNC_TRIG);
607608

608-
err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
609+
err = idtcm_write(idtcm, HW_Q11_CTRL_SPARE, 0,
609610
&temp, sizeof(temp));
610611
if (err)
611612
return err;
612613

613614
temp |= Q10_TO_Q11_SYNC_TRIG;
614615

615-
err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
616+
err = idtcm_write(idtcm, HW_Q11_CTRL_SPARE, 0,
616617
&temp, sizeof(temp));
617618
if (err)
618619
return err;
619620
}
620621

621622
/* Place master sync out of reset */
622623
val &= ~(SYNCTRL1_MASTER_SYNC_RST);
623-
err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
624+
err = idtcm_write(idtcm, sync_ctrl1, 0, &val, sizeof(val));
624625

625626
return err;
626627
}
@@ -637,7 +638,7 @@ static int idtcm_sync_pps_output(struct idtcm_channel *channel)
637638
u8 temp;
638639
u16 output_mask = channel->output_mask;
639640

640-
err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
641+
err = idtcm_read(idtcm, HW_Q8_CTRL_SPARE, 0,
641642
&temp, sizeof(temp));
642643
if (err)
643644
return err;
@@ -646,7 +647,7 @@ static int idtcm_sync_pps_output(struct idtcm_channel *channel)
646647
Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
647648
out8_mux = 1;
648649

649-
err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
650+
err = idtcm_read(idtcm, HW_Q11_CTRL_SPARE, 0,
650651
&temp, sizeof(temp));
651652
if (err)
652653
return err;
@@ -1253,7 +1254,7 @@ static void display_pll_and_masks(struct idtcm *idtcm)
12531254
static int idtcm_load_firmware(struct idtcm *idtcm,
12541255
struct device *dev)
12551256
{
1256-
u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
1257+
u16 scratch = SCSR_ADDR(IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH));
12571258
char fname[128] = FW_FILENAME;
12581259
const struct firmware *fw;
12591260
struct idtcm_fwrc *rec;
@@ -1303,14 +1304,14 @@ static int idtcm_load_firmware(struct idtcm *idtcm,
13031304
err = 0;
13041305

13051306
/* Top (status registers) and bottom are read-only */
1306-
if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
1307+
if (regaddr < SCSR_ADDR(GPIO_USER_CONTROL) || regaddr >= scratch)
13071308
continue;
13081309

13091310
/* Page size 128, last 4 bytes of page skipped */
13101311
if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
13111312
continue;
13121313

1313-
err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1314+
err = idtcm_write(idtcm, SCSR_BASE, regaddr, &val, sizeof(val));
13141315
}
13151316

13161317
if (err)
@@ -1340,7 +1341,7 @@ static int idtcm_output_enable(struct idtcm_channel *channel,
13401341
return base;
13411342
}
13421343

1343-
err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1344+
err = idtcm_read(idtcm, (u32)base, OUT_CTRL_1, &val, sizeof(val));
13441345
if (err)
13451346
return err;
13461347

@@ -1349,7 +1350,7 @@ static int idtcm_output_enable(struct idtcm_channel *channel,
13491350
else
13501351
val &= ~SQUELCH_DISABLE;
13511352

1352-
return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1353+
return idtcm_write(idtcm, (u32)base, OUT_CTRL_1, &val, sizeof(val));
13531354
}
13541355

13551356
static int idtcm_perout_enable(struct idtcm_channel *channel,
@@ -1713,10 +1714,10 @@ static s32 idtcm_getmaxphase(struct ptp_clock_info *ptp __always_unused)
17131714
static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
17141715
{
17151716
struct idtcm *idtcm = channel->idtcm;
1716-
int err;
1717-
u8 i;
17181717
u8 buf[4] = {0};
17191718
s32 phase_50ps;
1719+
int err;
1720+
u8 i;
17201721

17211722
if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
17221723
err = channel->configure_write_phase(channel);

‎drivers/ptp/ptp_clockmatrix.h

Lines changed: 10 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -54,21 +54,9 @@
5454
#define LOCK_TIMEOUT_MS (2000)
5555
#define LOCK_POLL_INTERVAL_MS (10)
5656

57-
#define IDTCM_MAX_WRITE_COUNT (512)
58-
5957
#define PHASE_PULL_IN_MAX_PPB (144000)
6058
#define PHASE_PULL_IN_MIN_THRESHOLD_NS (2)
6159

62-
/*
63-
* Return register address based on passed in firmware version
64-
*/
65-
#define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
66-
enum fw_version {
67-
V_DEFAULT = 0,
68-
V487 = 1,
69-
V520 = 2,
70-
};
71-
7260
/* PTP PLL Mode */
7361
enum ptp_pll_mode {
7462
PTP_PLL_MODE_MIN = 0,
@@ -84,16 +72,16 @@ struct idtcm_channel {
8472
struct ptp_clock_info caps;
8573
struct ptp_clock *ptp_clock;
8674
struct idtcm *idtcm;
87-
u16 dpll_phase;
88-
u16 dpll_freq;
89-
u16 dpll_n;
90-
u16 dpll_ctrl_n;
91-
u16 dpll_phase_pull_in;
92-
u16 tod_read_primary;
93-
u16 tod_read_secondary;
94-
u16 tod_write;
95-
u16 tod_n;
96-
u16 hw_dpll_n;
75+
u32 dpll_phase;
76+
u32 dpll_freq;
77+
u32 dpll_n;
78+
u32 dpll_ctrl_n;
79+
u32 dpll_phase_pull_in;
80+
u32 tod_read_primary;
81+
u32 tod_read_secondary;
82+
u32 tod_write;
83+
u32 tod_n;
84+
u32 hw_dpll_n;
9785
u8 sync_src;
9886
enum ptp_pll_mode mode;
9987
int (*configure_write_frequency)(struct idtcm_channel *channel);

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