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drm/i915: Fix VIDEO_DIP_CTL bit shifts
The shifts for VSC_SELECT bits are wrong, fix it. Good thing is the definitions are unused. v2: Moves definitions in another patch (Manasi) Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Fixes: 7af2be6 ("drm/i915/icl: Add VIDEO_DIP registers") Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181005185643.31660-1-dhinakaran.pandiyan@intel.com
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‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4573,12 +4573,12 @@ enum {
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#define DRM_DIP_ENABLE (1 << 28)
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#define PSR_VSC_BIT_7_SET (1 << 27)
4576-
#define VSC_SELECT_MASK (0x3 << 26)
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#define VSC_SELECT_SHIFT 26
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#define VSC_DIP_HW_HEA_DATA (0 << 26)
4579-
#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
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#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
4581-
#define VSC_DIP_SW_HEA_DATA (3 << 26)
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#define VSC_SELECT_MASK (0x3 << 25)
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#define VSC_SELECT_SHIFT 25
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#define VSC_DIP_HW_HEA_DATA (0 << 25)
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#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
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#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
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#define VSC_DIP_SW_HEA_DATA (3 << 25)
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#define VDIP_ENABLE_PPS (1 << 24)
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/* Panel power sequencing */

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