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Russell KingRussell King
Russell King
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Russell King
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[ARM] cputype: separate definitions, use them
Add asm/cputype.h, moving functions and definitions from asm/system.h there. Convert all users of 'processor_id' to the more efficient read_cpuid_id() function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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18 files changed

+131
-114
lines changed

18 files changed

+131
-114
lines changed

‎arch/arm/include/asm/cputype.h

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,64 @@
1+
#ifndef __ASM_ARM_CPUTYPE_H
2+
#define __ASM_ARM_CPUTYPE_H
3+
4+
#include <linux/stringify.h>
5+
6+
#define CPUID_ID 0
7+
#define CPUID_CACHETYPE 1
8+
#define CPUID_TCM 2
9+
#define CPUID_TLBTYPE 3
10+
11+
#ifdef CONFIG_CPU_CP15
12+
#define read_cpuid(reg) \
13+
({ \
14+
unsigned int __val; \
15+
asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
16+
: "=r" (__val) \
17+
: \
18+
: "cc"); \
19+
__val; \
20+
})
21+
#else
22+
extern unsigned int processor_id;
23+
#define read_cpuid(reg) (processor_id)
24+
#endif
25+
26+
/*
27+
* The CPU ID never changes at run time, so we might as well tell the
28+
* compiler that it's constant. Use this function to read the CPU ID
29+
* rather than directly reading processor_id or read_cpuid() directly.
30+
*/
31+
static inline unsigned int __attribute_const__ read_cpuid_id(void)
32+
{
33+
return read_cpuid(CPUID_ID);
34+
}
35+
36+
static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
37+
{
38+
return read_cpuid(CPUID_CACHETYPE);
39+
}
40+
41+
/*
42+
* Intel's XScale3 core supports some v6 features (supersections, L2)
43+
* but advertises itself as v5 as it does not support the v6 ISA. For
44+
* this reason, we need a way to explicitly test for this type of CPU.
45+
*/
46+
#ifndef CONFIG_CPU_XSC3
47+
#define cpu_is_xsc3() 0
48+
#else
49+
static inline int cpu_is_xsc3(void)
50+
{
51+
if ((read_cpuid_id() & 0xffffe000) == 0x69056000)
52+
return 1;
53+
54+
return 0;
55+
}
56+
#endif
57+
58+
#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
59+
#define cpu_is_xscale() 0
60+
#else
61+
#define cpu_is_xscale() 1
62+
#endif
63+
64+
#endif

‎arch/arm/include/asm/system.h

Lines changed: 0 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -43,11 +43,6 @@
4343
#define CR_XP (1 << 23) /* Extended page tables */
4444
#define CR_VE (1 << 24) /* Vectored interrupts */
4545

46-
#define CPUID_ID 0
47-
#define CPUID_CACHETYPE 1
48-
#define CPUID_TCM 2
49-
#define CPUID_TLBTYPE 3
50-
5146
/*
5247
* This is used to ensure the compiler did actually allocate the register we
5348
* asked it for some inline assembly sequences. Apparently we can't trust
@@ -61,36 +56,8 @@
6156
#ifndef __ASSEMBLY__
6257

6358
#include <linux/linkage.h>
64-
#include <linux/stringify.h>
6559
#include <linux/irqflags.h>
6660

67-
#ifdef CONFIG_CPU_CP15
68-
#define read_cpuid(reg) \
69-
({ \
70-
unsigned int __val; \
71-
asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
72-
: "=r" (__val) \
73-
: \
74-
: "cc"); \
75-
__val; \
76-
})
77-
#else
78-
extern unsigned int processor_id;
79-
#define read_cpuid(reg) (processor_id)
80-
#endif
81-
82-
/*
83-
* The CPU ID never changes at run time, so we might as well tell the
84-
* compiler that it's constant. Use this function to read the CPU ID
85-
* rather than directly reading processor_id or read_cpuid() directly.
86-
*/
87-
static inline unsigned int read_cpuid_id(void) __attribute_const__;
88-
89-
static inline unsigned int read_cpuid_id(void)
90-
{
91-
return read_cpuid(CPUID_ID);
92-
}
93-
9461
#define __exception __attribute__((section(".exception.text")))
9562

9663
struct thread_info;
@@ -131,31 +98,6 @@ extern void cpu_init(void);
13198
void arm_machine_restart(char mode);
13299
extern void (*arm_pm_restart)(char str);
133100

134-
/*
135-
* Intel's XScale3 core supports some v6 features (supersections, L2)
136-
* but advertises itself as v5 as it does not support the v6 ISA. For
137-
* this reason, we need a way to explicitly test for this type of CPU.
138-
*/
139-
#ifndef CONFIG_CPU_XSC3
140-
#define cpu_is_xsc3() 0
141-
#else
142-
static inline int cpu_is_xsc3(void)
143-
{
144-
extern unsigned int processor_id;
145-
146-
if ((processor_id & 0xffffe000) == 0x69056000)
147-
return 1;
148-
149-
return 0;
150-
}
151-
#endif
152-
153-
#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
154-
#define cpu_is_xscale() 0
155-
#else
156-
#define cpu_is_xscale() 1
157-
#endif
158-
159101
#define UDBG_UNDEFINED (1 << 0)
160102
#define UDBG_SYSCALL (1 << 1)
161103
#define UDBG_BADABORT (1 << 2)

‎arch/arm/kernel/setup.c

Lines changed: 23 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
#include <linux/fs.h>
2727

2828
#include <asm/cpu.h>
29+
#include <asm/cputype.h>
2930
#include <asm/elf.h>
3031
#include <asm/procinfo.h>
3132
#include <asm/setup.h>
@@ -280,9 +281,9 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
280281

281282
static void __init dump_cpu_info(int cpu)
282283
{
283-
unsigned int info = read_cpuid(CPUID_CACHETYPE);
284+
unsigned int info = read_cpuid_cachetype();
284285

285-
if (info != processor_id) {
286+
if (info != read_cpuid_id()) {
286287
printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
287288
cache_types[CACHE_TYPE(info)]);
288289
if (CACHE_S(info)) {
@@ -301,15 +302,15 @@ int cpu_architecture(void)
301302
{
302303
int cpu_arch;
303304

304-
if ((processor_id & 0x0008f000) == 0) {
305+
if ((read_cpuid_id() & 0x0008f000) == 0) {
305306
cpu_arch = CPU_ARCH_UNKNOWN;
306-
} else if ((processor_id & 0x0008f000) == 0x00007000) {
307-
cpu_arch = (processor_id & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
308-
} else if ((processor_id & 0x00080000) == 0x00000000) {
309-
cpu_arch = (processor_id >> 16) & 7;
307+
} else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
308+
cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
309+
} else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
310+
cpu_arch = (read_cpuid_id() >> 16) & 7;
310311
if (cpu_arch)
311312
cpu_arch += CPU_ARCH_ARMv3;
312-
} else if ((processor_id & 0x000f0000) == 0x000f0000) {
313+
} else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
313314
unsigned int mmfr0;
314315

315316
/* Revised CPUID format. Read the Memory Model Feature
@@ -346,10 +347,10 @@ static void __init setup_processor(void)
346347
* types. The linker builds this table for us from the
347348
* entries in arch/arm/mm/proc-*.S
348349
*/
349-
list = lookup_processor_type(processor_id);
350+
list = lookup_processor_type(read_cpuid_id());
350351
if (!list) {
351352
printk("CPU configuration botched (ID %08x), unable "
352-
"to continue.\n", processor_id);
353+
"to continue.\n", read_cpuid_id());
353354
while (1);
354355
}
355356

@@ -369,7 +370,7 @@ static void __init setup_processor(void)
369370
#endif
370371

371372
printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
372-
cpu_name, processor_id, (int)processor_id & 15,
373+
cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
373374
proc_arch[cpu_architecture()], cr_alignment);
374375

375376
sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
@@ -922,7 +923,7 @@ static int c_show(struct seq_file *m, void *v)
922923
int i;
923924

924925
seq_printf(m, "Processor\t: %s rev %d (%s)\n",
925-
cpu_name, (int)processor_id & 15, elf_platform);
926+
cpu_name, read_cpuid_id() & 15, elf_platform);
926927

927928
#if defined(CONFIG_SMP)
928929
for_each_online_cpu(i) {
@@ -949,30 +950,30 @@ static int c_show(struct seq_file *m, void *v)
949950
if (elf_hwcap & (1 << i))
950951
seq_printf(m, "%s ", hwcap_str[i]);
951952

952-
seq_printf(m, "\nCPU implementer\t: 0x%02x\n", processor_id >> 24);
953+
seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
953954
seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
954955

955-
if ((processor_id & 0x0008f000) == 0x00000000) {
956+
if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
956957
/* pre-ARM7 */
957-
seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4);
958+
seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
958959
} else {
959-
if ((processor_id & 0x0008f000) == 0x00007000) {
960+
if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
960961
/* ARM7 */
961962
seq_printf(m, "CPU variant\t: 0x%02x\n",
962-
(processor_id >> 16) & 127);
963+
(read_cpuid_id() >> 16) & 127);
963964
} else {
964965
/* post-ARM7 */
965966
seq_printf(m, "CPU variant\t: 0x%x\n",
966-
(processor_id >> 20) & 15);
967+
(read_cpuid_id() >> 20) & 15);
967968
}
968969
seq_printf(m, "CPU part\t: 0x%03x\n",
969-
(processor_id >> 4) & 0xfff);
970+
(read_cpuid_id() >> 4) & 0xfff);
970971
}
971-
seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);
972+
seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
972973

973974
{
974-
unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
975-
if (cache_info != processor_id) {
975+
unsigned int cache_info = read_cpuid_cachetype();
976+
if (cache_info != read_cpuid_id()) {
976977
seq_printf(m, "Cache type\t: %s\n"
977978
"Cache clean\t: %s\n"
978979
"Cache lockdown\t: %s\n"

‎arch/arm/mach-iop32x/iq31244.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
#include <linux/mtd/physmap.h>
2828
#include <linux/platform_device.h>
2929
#include <mach/hardware.h>
30+
#include <asm/cputype.h>
3031
#include <asm/io.h>
3132
#include <asm/irq.h>
3233
#include <asm/mach/arch.h>
@@ -49,8 +50,7 @@ static int force_ep80219;
4950

5051
static int is_80219(void)
5152
{
52-
extern int processor_id;
53-
return !!((processor_id & 0xffffffe0) == 0x69052e20);
53+
return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
5454
}
5555

5656
static int is_ep80219(void)

‎arch/arm/mach-ixp4xx/common-pci.c

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
#include <linux/device.h>
2828
#include <asm/dma-mapping.h>
2929

30+
#include <asm/cputype.h>
3031
#include <asm/io.h>
3132
#include <asm/irq.h>
3233
#include <asm/sizes.h>
@@ -366,15 +367,13 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
366367

367368
void __init ixp4xx_pci_preinit(void)
368369
{
369-
unsigned long processor_id;
370-
371-
asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
370+
unsigned long cpuid = read_cpuid_id();
372371

373372
/*
374373
* Determine which PCI read method to use.
375374
* Rev 0 IXP425 requires workaround.
376375
*/
377-
if (!(processor_id & 0xf) && cpu_is_ixp42x()) {
376+
if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
378377
printk("PCI: IXP42x A0 silicon detected - "
379378
"PCI Non-Prefetch Workaround Enabled\n");
380379
ixp4xx_pci_read = ixp4xx_pci_read_errata;

‎arch/arm/mach-ixp4xx/include/mach/cpu.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,18 +14,19 @@
1414
#ifndef __ASM_ARCH_CPU_H__
1515
#define __ASM_ARCH_CPU_H__
1616

17-
extern unsigned int processor_id;
17+
#include <asm/cputype.h>
18+
1819
/* Processor id value in CP15 Register 0 */
1920
#define IXP425_PROCESSOR_ID_VALUE 0x690541c0
2021
#define IXP435_PROCESSOR_ID_VALUE 0x69054040
2122
#define IXP465_PROCESSOR_ID_VALUE 0x69054200
2223
#define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0
2324

24-
#define cpu_is_ixp42x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
25+
#define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
2526
IXP425_PROCESSOR_ID_VALUE)
26-
#define cpu_is_ixp43x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
27+
#define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
2728
IXP435_PROCESSOR_ID_VALUE)
28-
#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
29+
#define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
2930
IXP465_PROCESSOR_ID_VALUE)
3031

3132
static inline u32 ixp4xx_read_feature_bits(void)

‎arch/arm/mach-omap2/id.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <linux/kernel.h>
1616
#include <linux/init.h>
1717

18+
#include <asm/cputype.h>
1819
#include <asm/io.h>
1920

2021
#include <mach/control.h>

‎arch/arm/mach-pxa/include/mach/hardware.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,8 @@
6262

6363
#ifndef __ASSEMBLY__
6464

65+
#include <asm/cputype.h>
66+
6567
#ifdef CONFIG_PXA25x
6668
#define __cpu_is_pxa21x(id) \
6769
({ \

‎arch/arm/mach-sa1100/cpu-sa1100.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,8 @@
8888
#include <linux/init.h>
8989
#include <linux/cpufreq.h>
9090

91+
#include <asm/cputype.h>
92+
9193
#include <mach/hardware.h>
9294

9395
#include "generic.h"
@@ -240,7 +242,7 @@ static struct cpufreq_driver sa1100_driver = {
240242

241243
static int __init sa1100_dram_init(void)
242244
{
243-
if ((processor_id & CPU_SA1100_MASK) == CPU_SA1100_ID)
245+
if (cpu_is_sa1100())
244246
return cpufreq_register_driver(&sa1100_driver);
245247
else
246248
return -ENODEV;

‎arch/arm/mach-sa1100/cpu-sa1110.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@
2525
#include <linux/init.h>
2626

2727
#include <mach/hardware.h>
28+
#include <asm/cputype.h>
2829
#include <asm/mach-types.h>
2930
#include <asm/io.h>
3031
#include <asm/system.h>

‎arch/arm/mach-sa1100/include/mach/SA-1100.h

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2054,19 +2054,3 @@
20542054
/* active display mode) */
20552055
#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
20562056
#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
2057-
2058-
#ifndef __ASSEMBLY__
2059-
extern unsigned int processor_id;
2060-
#endif
2061-
2062-
#define CPU_REVISION (processor_id & 15)
2063-
#define CPU_SA1110_A0 (0)
2064-
#define CPU_SA1110_B0 (4)
2065-
#define CPU_SA1110_B1 (5)
2066-
#define CPU_SA1110_B2 (6)
2067-
#define CPU_SA1110_B4 (8)
2068-
2069-
#define CPU_SA1100_ID (0x4401a110)
2070-
#define CPU_SA1100_MASK (0xfffffff0)
2071-
#define CPU_SA1110_ID (0x6901b110)
2072-
#define CPU_SA1110_MASK (0xfffffff0)

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