Skip to content

Commit 0d7b6b1

Browse files
ideakdanvet
authored andcommitted
drm/i915/chv: fix HW readout of the port PLL fractional divider
Ville noticed that the PLL HW readout code parsed the fractional divider value as if the fractional divider was always enabled. This may result in a port clock state check mismatch if the preceeding modeset disabled the fractional divider, but left a non-zero divider value in the register. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
1 parent d770e55 commit 0d7b6b1

File tree

1 file changed

+5
-2
lines changed

1 file changed

+5
-2
lines changed

drivers/gpu/drm/i915/intel_display.c

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7887,18 +7887,21 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
78877887
int pipe = pipe_config->cpu_transcoder;
78887888
enum dpio_channel port = vlv_pipe_to_channel(pipe);
78897889
intel_clock_t clock;
7890-
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7890+
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
78917891
int refclk = 100000;
78927892

78937893
mutex_lock(&dev_priv->sb_lock);
78947894
cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
78957895
pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
78967896
pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
78977897
pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7898+
pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
78987899
mutex_unlock(&dev_priv->sb_lock);
78997900

79007901
clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7901-
clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7902+
clock.m2 = (pll_dw0 & 0xff) << 22;
7903+
if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7904+
clock.m2 |= pll_dw2 & 0x3fffff;
79027905
clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
79037906
clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
79047907
clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;

0 commit comments

Comments
 (0)