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davem330davem330
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Merge branch 'rockchip-internal-phy'
David Wu says: ==================== rockchip: Add the integrated PHY support The rk3228 and rk3328 support integrated PHY inside, let's enable it to work. And the integrated PHY need to do some special setting, so register the rockchip integrated PHY driver. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2 parents d24d39d + 4b05bc6 commit 0dd532e

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‎Documentation/devicetree/bindings/net/phy.txt

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@@ -52,6 +52,11 @@ Optional Properties:
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Mark the corresponding energy efficient ethernet mode as broken and
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request the ethernet to stop advertising it.
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- phy-is-integrated: If set, indicates that the PHY is integrated into the same
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physical package as the Ethernet MAC. If needed, muxers should be configured
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to ensure the integrated PHY is used. The absence of this property indicates
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the muxers should be configured so that the external PHY is used.
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Example:
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ethernet-phy@0 {

‎arch/arm/boot/dts/rk3228-evb.dts

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@@ -50,6 +50,16 @@
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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vcc_phy: vcc-phy-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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regulator-name = "vcc_phy";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&emmc {
@@ -60,6 +70,30 @@
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status = "okay";
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};
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&gmac {
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assigned-clocks = <&cru SCLK_MAC_SRC>;
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assigned-clock-rates = <50000000>;
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clock_in_out = "output";
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phy-supply = <&vcc_phy>;
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phy-mode = "rmii";
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phy-handle = <&phy0>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy@0 {
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compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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clocks = <&cru SCLK_MAC_PHY>;
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resets = <&cru SRST_MACPHY>;
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phy-is-integrated;
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};
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};
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};
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&tsadc {
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status = "okay";
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‎arch/arm/configs/multi_v7_defconfig

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@@ -270,6 +270,7 @@ CONFIG_ICPLUS_PHY=y
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CONFIG_REALTEK_PHY=y
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CONFIG_MICREL_PHY=y
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CONFIG_FIXED_PHY=y
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CONFIG_ROCKCHIP_PHY=y
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CONFIG_USB_PEGASUS=y
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CONFIG_USB_RTL8152=m
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CONFIG_USB_USBNET=y

‎arch/arm64/boot/dts/rockchip/rk3328-evb.dts

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@@ -50,6 +50,23 @@
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chosen {
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stdout-path = "serial2:1500000n8";
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};
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vcc_phy: vcc-phy-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_phy";
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&gmac2phy {
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phy-supply = <&vcc_phy>;
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clock_in_out = "output";
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assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
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assigned-clock-rate = <50000000>;
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assigned-clocks = <&cru SCLK_MAC2PHY>;
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assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
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status = "okay";
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};
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&uart2 {

‎arch/arm64/boot/dts/rockchip/rk3328.dtsi

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@@ -63,6 +63,8 @@
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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ethernet0 = &gmac2io;
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ethernet1 = &gmac2phy;
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};
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cpus {
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status = "disabled";
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};
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gmac2phy: ethernet@ff550000 {
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compatible = "rockchip,rk3328-gmac";
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reg = <0x0 0xff550000 0x0 0x10000>;
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rockchip,grf = <&grf>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
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<&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
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<&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
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<&cru SCLK_MAC2PHY_OUT>;
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clock-names = "stmmaceth", "mac_clk_rx",
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"mac_clk_tx", "clk_mac_ref",
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"aclk_mac", "pclk_mac",
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"clk_macphy";
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resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
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reset-names = "stmmaceth", "mac-phy";
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phy-mode = "rmii";
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phy-handle = <&phy>;
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status = "disabled";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy: phy@0 {
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compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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clocks = <&cru SCLK_MAC2PHY_OUT>;
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resets = <&cru SRST_MACPHY>;
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pinctrl-names = "default";
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pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
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phy-is-integrated;
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};
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};
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};
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gic: interrupt-controller@ff811000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;

‎arch/arm64/configs/defconfig

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@@ -203,6 +203,7 @@ CONFIG_MARVELL_PHY=m
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CONFIG_MESON_GXL_PHY=m
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CONFIG_MICREL_PHY=y
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CONFIG_REALTEK_PHY=m
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CONFIG_ROCKCHIP_PHY=y
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CONFIG_USB_PEGASUS=m
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CONFIG_USB_RTL8150=m
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CONFIG_USB_RTL8152=m

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