@@ -291,6 +291,33 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
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.error_clear = SCIF_ERROR_CLEAR ,
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},
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+ /*
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+ * The "SCIFA" that is in RZ/T and RZ/A2.
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+ * It looks like a normal SCIF with FIFO data, but with a
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+ * compressed address space. Also, the break out of interrupts
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+ * are different: ERI/BRI, RXI, TXI, TEI, DRI.
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+ */
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+ [SCIx_RZ_SCIFA_REGTYPE ] = {
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+ .regs = {
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+ [SCSMR ] = { 0x00 , 16 },
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+ [SCBRR ] = { 0x02 , 8 },
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+ [SCSCR ] = { 0x04 , 16 },
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+ [SCxTDR ] = { 0x06 , 8 },
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+ [SCxSR ] = { 0x08 , 16 },
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+ [SCxRDR ] = { 0x0A , 8 },
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+ [SCFCR ] = { 0x0C , 16 },
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+ [SCFDR ] = { 0x0E , 16 },
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+ [SCSPTR ] = { 0x10 , 16 },
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+ [SCLSR ] = { 0x12 , 16 },
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+ },
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+ .fifosize = 16 ,
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+ .overrun_reg = SCLSR ,
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+ .overrun_mask = SCLSR_ORER ,
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+ .sampling_rate_mask = SCI_SR (32 ),
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+ .error_mask = SCIF_DEFAULT_ERROR_MASK ,
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+ .error_clear = SCIF_ERROR_CLEAR ,
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+ },
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+
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/*
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* Common SH-3 SCIF definitions.
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*/
@@ -3110,6 +3137,10 @@ static const struct of_device_id of_sci_match[] = {
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.compatible = "renesas,scif-r7s72100" ,
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.data = SCI_OF_DATA (PORT_SCIF , SCIx_SH2_SCIF_FIFODATA_REGTYPE ),
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},
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+ {
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+ .compatible = "renesas,scif-r7s9210" ,
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+ .data = SCI_OF_DATA (PORT_SCIF , SCIx_RZ_SCIFA_REGTYPE ),
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+ },
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/* Family-specific types */
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{
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.compatible = "renesas,rcar-gen1-scif" ,
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