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30 | 30 | #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
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31 | 31 | #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
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32 | 32 |
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33 |
| -#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 |
34 |
| -#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 |
35 |
| -#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010 |
36 |
| -#define MV64XXX_I2C_REG_CONTROL_START 0x00000020 |
37 |
| -#define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040 |
38 |
| -#define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080 |
| 33 | +#define MV64XXX_I2C_REG_CONTROL_ACK BIT(2) |
| 34 | +#define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3) |
| 35 | +#define MV64XXX_I2C_REG_CONTROL_STOP BIT(4) |
| 36 | +#define MV64XXX_I2C_REG_CONTROL_START BIT(5) |
| 37 | +#define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6) |
| 38 | +#define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7) |
39 | 39 |
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40 | 40 | /* Ctlr status values */
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41 | 41 | #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
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68 | 68 | #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
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69 | 69 |
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70 | 70 | /* Bridge Control values */
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71 |
| -#define MV64XXX_I2C_BRIDGE_CONTROL_WR 0x00000001 |
72 |
| -#define MV64XXX_I2C_BRIDGE_CONTROL_RD 0x00000002 |
| 71 | +#define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0) |
| 72 | +#define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1) |
73 | 73 | #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
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74 |
| -#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT 0x00001000 |
| 74 | +#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12) |
75 | 75 | #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
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76 | 76 | #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
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77 |
| -#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE 0x00080000 |
| 77 | +#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19) |
78 | 78 |
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79 | 79 | /* Bridge Status values */
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80 |
| -#define MV64XXX_I2C_BRIDGE_STATUS_ERROR 0x00000001 |
| 80 | +#define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0) |
81 | 81 | #define MV64XXX_I2C_STATUS_OFFLOAD_ERROR 0xf0000001
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82 | 82 | #define MV64XXX_I2C_STATUS_OFFLOAD_OK 0xf0000000
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83 | 83 |
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