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IronShendavem330
IronShen
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net: hns3: Support "ethtool -d" for HNS3 VF driver
This patch adds "ethtool -d" support for HNS3 VF Driver. Signed-off-by: Jian Shen <shenjian15@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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‎drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,58 @@ static const struct pci_device_id ae_algovf_pci_tbl[] = {
2323

2424
MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
2525

26+
static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
27+
HCLGEVF_CMDQ_TX_ADDR_H_REG,
28+
HCLGEVF_CMDQ_TX_DEPTH_REG,
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HCLGEVF_CMDQ_TX_TAIL_REG,
30+
HCLGEVF_CMDQ_TX_HEAD_REG,
31+
HCLGEVF_CMDQ_RX_ADDR_L_REG,
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HCLGEVF_CMDQ_RX_ADDR_H_REG,
33+
HCLGEVF_CMDQ_RX_DEPTH_REG,
34+
HCLGEVF_CMDQ_RX_TAIL_REG,
35+
HCLGEVF_CMDQ_RX_HEAD_REG,
36+
HCLGEVF_VECTOR0_CMDQ_SRC_REG,
37+
HCLGEVF_CMDQ_INTR_STS_REG,
38+
HCLGEVF_CMDQ_INTR_EN_REG,
39+
HCLGEVF_CMDQ_INTR_GEN_REG};
40+
41+
static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
42+
HCLGEVF_RST_ING,
43+
HCLGEVF_GRO_EN_REG};
44+
45+
static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
46+
HCLGEVF_RING_RX_ADDR_H_REG,
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HCLGEVF_RING_RX_BD_NUM_REG,
48+
HCLGEVF_RING_RX_BD_LENGTH_REG,
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HCLGEVF_RING_RX_MERGE_EN_REG,
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HCLGEVF_RING_RX_TAIL_REG,
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HCLGEVF_RING_RX_HEAD_REG,
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HCLGEVF_RING_RX_FBD_NUM_REG,
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HCLGEVF_RING_RX_OFFSET_REG,
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HCLGEVF_RING_RX_FBD_OFFSET_REG,
55+
HCLGEVF_RING_RX_STASH_REG,
56+
HCLGEVF_RING_RX_BD_ERR_REG,
57+
HCLGEVF_RING_TX_ADDR_L_REG,
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HCLGEVF_RING_TX_ADDR_H_REG,
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HCLGEVF_RING_TX_BD_NUM_REG,
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HCLGEVF_RING_TX_PRIORITY_REG,
61+
HCLGEVF_RING_TX_TC_REG,
62+
HCLGEVF_RING_TX_MERGE_EN_REG,
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HCLGEVF_RING_TX_TAIL_REG,
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HCLGEVF_RING_TX_HEAD_REG,
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HCLGEVF_RING_TX_FBD_NUM_REG,
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HCLGEVF_RING_TX_OFFSET_REG,
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HCLGEVF_RING_TX_EBD_NUM_REG,
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HCLGEVF_RING_TX_EBD_OFFSET_REG,
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HCLGEVF_RING_TX_BD_ERR_REG,
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HCLGEVF_RING_EN_REG};
71+
72+
static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
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HCLGEVF_TQP_INTR_GL0_REG,
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HCLGEVF_TQP_INTR_GL1_REG,
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HCLGEVF_TQP_INTR_GL2_REG,
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HCLGEVF_TQP_INTR_RL_REG};
77+
2678
static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
2779
struct hnae3_handle *handle)
2880
{
@@ -2473,6 +2525,72 @@ static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
24732525
return hdev->reset_count;
24742526
}
24752527

2528+
#define MAX_SEPARATE_NUM 4
2529+
#define SEPARATOR_VALUE 0xFFFFFFFF
2530+
#define REG_NUM_PER_LINE 4
2531+
#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
2532+
2533+
static int hclgevf_get_regs_len(struct hnae3_handle *handle)
2534+
{
2535+
int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
2536+
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2537+
2538+
cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
2539+
common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
2540+
ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
2541+
tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
2542+
2543+
return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
2544+
tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
2545+
}
2546+
2547+
static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
2548+
void *data)
2549+
{
2550+
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2551+
int i, j, reg_um, separator_num;
2552+
u32 *reg = data;
2553+
2554+
*version = hdev->fw_version;
2555+
2556+
/* fetching per-VF registers values from VF PCIe register space */
2557+
reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
2558+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2559+
for (i = 0; i < reg_um; i++)
2560+
*reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
2561+
for (i = 0; i < separator_num; i++)
2562+
*reg++ = SEPARATOR_VALUE;
2563+
2564+
reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
2565+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2566+
for (i = 0; i < reg_um; i++)
2567+
*reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
2568+
for (i = 0; i < separator_num; i++)
2569+
*reg++ = SEPARATOR_VALUE;
2570+
2571+
reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
2572+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2573+
for (j = 0; j < hdev->num_tqps; j++) {
2574+
for (i = 0; i < reg_um; i++)
2575+
*reg++ = hclgevf_read_dev(&hdev->hw,
2576+
ring_reg_addr_list[i] +
2577+
0x200 * j);
2578+
for (i = 0; i < separator_num; i++)
2579+
*reg++ = SEPARATOR_VALUE;
2580+
}
2581+
2582+
reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
2583+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2584+
for (j = 0; j < hdev->num_msi_used - 1; j++) {
2585+
for (i = 0; i < reg_um; i++)
2586+
*reg++ = hclgevf_read_dev(&hdev->hw,
2587+
tqp_intr_reg_addr_list[i] +
2588+
4 * j);
2589+
for (i = 0; i < separator_num; i++)
2590+
*reg++ = SEPARATOR_VALUE;
2591+
}
2592+
}
2593+
24762594
static const struct hnae3_ae_ops hclgevf_ops = {
24772595
.init_ae_dev = hclgevf_init_ae_dev,
24782596
.uninit_ae_dev = hclgevf_uninit_ae_dev,
@@ -2514,6 +2632,8 @@ static const struct hnae3_ae_ops hclgevf_ops = {
25142632
.set_default_reset_request = hclgevf_set_def_reset_request,
25152633
.get_channels = hclgevf_get_channels,
25162634
.get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
2635+
.get_regs_len = hclgevf_get_regs_len,
2636+
.get_regs = hclgevf_get_regs,
25172637
.get_status = hclgevf_get_status,
25182638
.get_ksettings_an_result = hclgevf_get_ksettings_an_result,
25192639
.get_media_type = hclgevf_get_media_type,

‎drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,60 @@
2727
#define HCLGEVF_VECTOR_REG_OFFSET 0x4
2828
#define HCLGEVF_VECTOR_VF_OFFSET 0x100000
2929

30+
/* bar registers for cmdq */
31+
#define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000
32+
#define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004
33+
#define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008
34+
#define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010
35+
#define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014
36+
#define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018
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#define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C
38+
#define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020
39+
#define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024
40+
#define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028
41+
#define HCLGEVF_CMDQ_INTR_SRC_REG 0x27100
42+
#define HCLGEVF_CMDQ_INTR_STS_REG 0x27104
43+
#define HCLGEVF_CMDQ_INTR_EN_REG 0x27108
44+
#define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C
45+
46+
/* bar registers for common func */
47+
#define HCLGEVF_GRO_EN_REG 0x28000
48+
49+
/* bar registers for rcb */
50+
#define HCLGEVF_RING_RX_ADDR_L_REG 0x80000
51+
#define HCLGEVF_RING_RX_ADDR_H_REG 0x80004
52+
#define HCLGEVF_RING_RX_BD_NUM_REG 0x80008
53+
#define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C
54+
#define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014
55+
#define HCLGEVF_RING_RX_TAIL_REG 0x80018
56+
#define HCLGEVF_RING_RX_HEAD_REG 0x8001C
57+
#define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020
58+
#define HCLGEVF_RING_RX_OFFSET_REG 0x80024
59+
#define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028
60+
#define HCLGEVF_RING_RX_STASH_REG 0x80030
61+
#define HCLGEVF_RING_RX_BD_ERR_REG 0x80034
62+
#define HCLGEVF_RING_TX_ADDR_L_REG 0x80040
63+
#define HCLGEVF_RING_TX_ADDR_H_REG 0x80044
64+
#define HCLGEVF_RING_TX_BD_NUM_REG 0x80048
65+
#define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C
66+
#define HCLGEVF_RING_TX_TC_REG 0x80050
67+
#define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054
68+
#define HCLGEVF_RING_TX_TAIL_REG 0x80058
69+
#define HCLGEVF_RING_TX_HEAD_REG 0x8005C
70+
#define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060
71+
#define HCLGEVF_RING_TX_OFFSET_REG 0x80064
72+
#define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068
73+
#define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070
74+
#define HCLGEVF_RING_TX_BD_ERR_REG 0x80074
75+
#define HCLGEVF_RING_EN_REG 0x80090
76+
77+
/* bar registers for tqp interrupt */
78+
#define HCLGEVF_TQP_INTR_CTRL_REG 0x20000
79+
#define HCLGEVF_TQP_INTR_GL0_REG 0x20100
80+
#define HCLGEVF_TQP_INTR_GL1_REG 0x20200
81+
#define HCLGEVF_TQP_INTR_GL2_REG 0x20300
82+
#define HCLGEVF_TQP_INTR_RL_REG 0x20900
83+
3084
/* Vector0 interrupt CMDQ event source register(RW) */
3185
#define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100
3286
/* CMDQ register bits for RX event(=MBX event) */

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