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Andi KleenKAGA-KOKO
Andi Kleen
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KAGA-KOKO
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x86/speculation/l1tf: Add sysfs reporting for l1tf
L1TF core kernel workarounds are cheap and normally always enabled, However they still should be reported in sysfs if the system is vulnerable or mitigated. Add the necessary CPU feature/bug bits. - Extend the existing checks for Meltdowns to determine if the system is vulnerable. All CPUs which are not vulnerable to Meltdown are also not vulnerable to L1TF - Check for 32bit non PAE and emit a warning as there is no practical way for mitigation due to the limited physical address bits - If the system has more than MAX_PA/2 physical memory the invert page workarounds don't protect the system against the L1TF attack anymore, because an inverted physical address will also point to valid memory. Print a warning in this case and report that the system is vulnerable. Add a function which returns the PFN limit for the L1TF mitigation, which will be used in follow up patches for sanity and range checks. [ tglx: Renamed the CPU feature bit to L1TF_PTEINV ] Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Acked-by: Dave Hansen <dave.hansen@intel.com>
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‎arch/x86/include/asm/cpufeatures.h

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Original file line numberDiff line numberDiff line change
@@ -219,6 +219,7 @@
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#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
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#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
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223224
/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
@@ -373,5 +374,6 @@
373374
#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */
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#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
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#define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */
377+
#define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
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377379
#endif /* _ASM_X86_CPUFEATURES_H */

‎arch/x86/include/asm/processor.h

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@@ -181,6 +181,11 @@ extern const struct seq_operations cpuinfo_op;
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182182
extern void cpu_detect(struct cpuinfo_x86 *c);
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184+
static inline unsigned long l1tf_pfn_limit(void)
185+
{
186+
return BIT(boot_cpu_data.x86_phys_bits - 1 - PAGE_SHIFT) - 1;
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}
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184189
extern void early_cpu_init(void);
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extern void identify_boot_cpu(void);
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extern void identify_secondary_cpu(struct cpuinfo_x86 *);

‎arch/x86/kernel/cpu/bugs.c

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Original file line numberDiff line numberDiff line change
@@ -27,9 +27,11 @@
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#include <asm/pgtable.h>
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#include <asm/set_memory.h>
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#include <asm/intel-family.h>
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#include <asm/e820/api.h>
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3132
static void __init spectre_v2_select_mitigation(void);
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static void __init ssb_select_mitigation(void);
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static void __init l1tf_select_mitigation(void);
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/*
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* Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
@@ -81,6 +83,8 @@ void __init check_bugs(void)
8183
*/
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ssb_select_mitigation();
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86+
l1tf_select_mitigation();
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#ifdef CONFIG_X86_32
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/*
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* Check whether we are able to run this kernel safely on SMP.
@@ -205,6 +209,32 @@ static void x86_amd_ssb_disable(void)
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wrmsrl(MSR_AMD64_LS_CFG, msrval);
206210
}
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212+
static void __init l1tf_select_mitigation(void)
213+
{
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u64 half_pa;
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if (!boot_cpu_has_bug(X86_BUG_L1TF))
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return;
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219+
#if CONFIG_PGTABLE_LEVELS == 2
220+
pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
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return;
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#endif
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/*
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* This is extremely unlikely to happen because almost all
226+
* systems have far more MAX_PA/2 than RAM can be fit into
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* DIMM slots.
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*/
229+
half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
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if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
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pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
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return;
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}
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setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
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}
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#ifdef RETPOLINE
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static bool spectre_v2_bad_module;
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@@ -678,6 +708,11 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr
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case X86_BUG_SPEC_STORE_BYPASS:
679709
return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
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711+
case X86_BUG_L1TF:
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if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
713+
return sprintf(buf, "Mitigation: Page Table Inversion\n");
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break;
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681716
default:
682717
break;
683718
}
@@ -704,4 +739,9 @@ ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *
704739
{
705740
return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
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}
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ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
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{
745+
return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
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}
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#endif

‎arch/x86/kernel/cpu/common.c

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@@ -984,6 +984,21 @@ static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
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{}
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};
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static const __initconst struct x86_cpu_id cpu_no_l1tf[] = {
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/* in addition to cpu_no_speculation */
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MOOREFIELD },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_DENVERTON },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GEMINI_LAKE },
997+
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
999+
{}
1000+
};
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static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
9881003
{
9891004
u64 ia32_cap = 0;
@@ -1010,6 +1025,11 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
10101025
return;
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10121027
setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
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1029+
if (x86_match_cpu(cpu_no_l1tf))
1030+
return;
1031+
1032+
setup_force_cpu_bug(X86_BUG_L1TF);
10131033
}
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10151035
/*

‎drivers/base/cpu.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -540,16 +540,24 @@ ssize_t __weak cpu_show_spec_store_bypass(struct device *dev,
540540
return sprintf(buf, "Not affected\n");
541541
}
542542

543+
ssize_t __weak cpu_show_l1tf(struct device *dev,
544+
struct device_attribute *attr, char *buf)
545+
{
546+
return sprintf(buf, "Not affected\n");
547+
}
548+
543549
static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL);
544550
static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL);
545551
static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL);
546552
static DEVICE_ATTR(spec_store_bypass, 0444, cpu_show_spec_store_bypass, NULL);
553+
static DEVICE_ATTR(l1tf, 0444, cpu_show_l1tf, NULL);
547554

548555
static struct attribute *cpu_root_vulnerabilities_attrs[] = {
549556
&dev_attr_meltdown.attr,
550557
&dev_attr_spectre_v1.attr,
551558
&dev_attr_spectre_v2.attr,
552559
&dev_attr_spec_store_bypass.attr,
560+
&dev_attr_l1tf.attr,
553561
NULL
554562
};
555563

‎include/linux/cpu.h

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@@ -55,6 +55,8 @@ extern ssize_t cpu_show_spectre_v2(struct device *dev,
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struct device_attribute *attr, char *buf);
5656
extern ssize_t cpu_show_spec_store_bypass(struct device *dev,
5757
struct device_attribute *attr, char *buf);
58+
extern ssize_t cpu_show_l1tf(struct device *dev,
59+
struct device_attribute *attr, char *buf);
5860

5961
extern __printf(4, 5)
6062
struct device *cpu_device_create(struct device *parent, void *drvdata,

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