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Stephane EranianIngo Molnar
Stephane Eranian
authored and
Ingo Molnar
committed
perf_events: Update PEBS event constraints
This patch updates PEBS event constraints for Intel Atom, Nehalem, Westmere. This patch also reorganizes the PEBS format/constraint detection code. It is now based on processor model and not PEBS format. Two processors may use the same PEBS format without have the same list of PEBS events. In this second version, we simplified the initialization of the PEBS constraints by leveraging the existing switch() statement in perf_event_intel.c. We also renamed the constraint tables to be more consistent with regular constraints. In this 3rd version, we drop BR_INST_RETIRED.MISPRED from Intel Atom as it does not seem to work. Use MISPREDICTED_BRANCH_RETIRED instead. Also add FP_ASSIST.* o both Intel Nehalem and Westmere. I misssed those in the earlier patches. Events were tested using libpfm4 perf_examples. Signed-off-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <4d6e6b02.815bdf0a.637b.07a7@mx.google.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
1 parent 0830937 commit 17e3162

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+42
-21
lines changed

2 files changed

+42
-21
lines changed

‎arch/x86/kernel/cpu/perf_event_intel.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1137,6 +1137,7 @@ static __init int intel_pmu_init(void)
11371137
intel_pmu_lbr_init_core();
11381138

11391139
x86_pmu.event_constraints = intel_core2_event_constraints;
1140+
x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
11401141
pr_cont("Core2 events, ");
11411142
break;
11421143

@@ -1149,6 +1150,7 @@ static __init int intel_pmu_init(void)
11491150
intel_pmu_lbr_init_nhm();
11501151

11511152
x86_pmu.event_constraints = intel_nehalem_event_constraints;
1153+
x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11521154
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
11531155
pr_cont("Nehalem events, ");
11541156
break;
@@ -1160,6 +1162,7 @@ static __init int intel_pmu_init(void)
11601162
intel_pmu_lbr_init_atom();
11611163

11621164
x86_pmu.event_constraints = intel_gen_event_constraints;
1165+
x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
11631166
pr_cont("Atom events, ");
11641167
break;
11651168

@@ -1172,6 +1175,7 @@ static __init int intel_pmu_init(void)
11721175

11731176
x86_pmu.event_constraints = intel_westmere_event_constraints;
11741177
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
1178+
x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
11751179
pr_cont("Westmere events, ");
11761180
break;
11771181

‎arch/x86/kernel/cpu/perf_event_intel_ds.c

Lines changed: 38 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -361,30 +361,50 @@ static int intel_pmu_drain_bts_buffer(void)
361361
/*
362362
* PEBS
363363
*/
364-
365-
static struct event_constraint intel_core_pebs_events[] = {
366-
PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
364+
static struct event_constraint intel_core2_pebs_event_constraints[] = {
365+
PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
367366
PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
368367
PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
369368
PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
370-
PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */
371-
PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
372-
PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */
373-
PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
374-
PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */
369+
INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
375370
EVENT_CONSTRAINT_END
376371
};
377372

378-
static struct event_constraint intel_nehalem_pebs_events[] = {
379-
PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */
380-
PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */
381-
PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */
382-
PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */
383-
PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */
384-
PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
385-
PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */
386-
PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
387-
PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */
373+
static struct event_constraint intel_atom_pebs_event_constraints[] = {
374+
PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
375+
PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
376+
INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
377+
EVENT_CONSTRAINT_END
378+
};
379+
380+
static struct event_constraint intel_nehalem_pebs_event_constraints[] = {
381+
INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
382+
INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
383+
PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
384+
INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
385+
INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
386+
INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
387+
PEBS_EVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
388+
INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
389+
PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
390+
INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
391+
INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
392+
EVENT_CONSTRAINT_END
393+
};
394+
395+
static struct event_constraint intel_westmere_pebs_event_constraints[] = {
396+
INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
397+
INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
398+
PEBS_EVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
399+
INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
400+
INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
401+
402+
INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
403+
INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
404+
INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
405+
PEBS_EVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
406+
INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
407+
INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
388408
EVENT_CONSTRAINT_END
389409
};
390410

@@ -733,20 +753,17 @@ static void intel_ds_init(void)
733753
printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
734754
x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
735755
x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
736-
x86_pmu.pebs_constraints = intel_core_pebs_events;
737756
break;
738757

739758
case 1:
740759
printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
741760
x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
742761
x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
743-
x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
744762
break;
745763

746764
default:
747765
printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
748766
x86_pmu.pebs = 0;
749-
break;
750767
}
751768
}
752769
}

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