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irqchip: mips-gic: Stop using per-platform mapping tables
Now that the GIC properly uses IRQ domains, kill off the per-platform routing tables that were used to make the GIC appear transparent. This includes: - removing the mapping tables and the support for applying them, - moving GIC IPI support to the GIC driver, - properly routing the i8259 through the GIC on Malta, and - updating IRQ assignments on SEAD-3 when the GIC is present. Platforms no longer will pass an interrupt mapping table to gic_init. Instead, they will pass the CPU interrupt vector (2 - 7) that they expect the GIC to route interrupts to. Note that in EIC mode this value is ignored and all GIC interrupts are routed to EIC vector 1. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7816/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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-325
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10 files changed

+198
-325
lines changed

‎arch/mips/include/asm/gic.h

Lines changed: 6 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -316,31 +316,6 @@
316316
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
317317
GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
318318

319-
/*
320-
* Interrupt Meta-data specification. The ipiflag helps
321-
* in building ipi_map.
322-
*/
323-
struct gic_intr_map {
324-
unsigned int cpunum; /* Directed to this CPU */
325-
#define GIC_UNUSED 0xdead /* Dummy data */
326-
unsigned int pin; /* Directed to this Pin */
327-
unsigned int polarity; /* Polarity : +/- */
328-
unsigned int trigtype; /* Trigger : Edge/Levl */
329-
unsigned int flags; /* Misc flags */
330-
#define GIC_FLAG_TRANSPARENT 0x01
331-
};
332-
333-
/*
334-
* This is only used in EIC mode. This helps to figure out which
335-
* shared interrupts we need to process when we get a vector interrupt.
336-
*/
337-
#define GIC_MAX_SHARED_INTR 0x5
338-
struct gic_shared_intr_map {
339-
unsigned int num_shared_intr;
340-
unsigned int intr_list[GIC_MAX_SHARED_INTR];
341-
unsigned int local_intr_mask;
342-
};
343-
344319
/* GIC nomenclature for Core Interrupt Pins. */
345320
#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
346321
#define GIC_CPU_INT1 1 /* . */
@@ -349,6 +324,9 @@ struct gic_shared_intr_map {
349324
#define GIC_CPU_INT4 4 /* . */
350325
#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
351326

327+
/* Add 2 to convert GIC CPU pin to core interrupt */
328+
#define GIC_CPU_PIN_OFFSET 2
329+
352330
/* Local GIC interrupts. */
353331
#define GIC_INT_TMR (GIC_CPU_INT5)
354332
#define GIC_INT_PERFCTR (GIC_CPU_INT5)
@@ -365,13 +343,12 @@ struct gic_shared_intr_map {
365343
extern unsigned int gic_present;
366344
extern unsigned int gic_frequency;
367345
extern unsigned long _gic_base;
368-
extern unsigned int gic_irq_base;
369346
extern unsigned int gic_irq_flags[];
370-
extern struct gic_shared_intr_map gic_shared_intr_map[];
347+
extern unsigned int gic_cpu_pin;
371348

372349
extern void gic_init(unsigned long gic_base_addr,
373-
unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
374-
unsigned int intrmap_size, unsigned int irqbase);
350+
unsigned long gic_addrspace_size, unsigned int cpu_vec,
351+
unsigned int irqbase);
375352
extern void gic_clocksource_init(unsigned int);
376353
extern unsigned int gic_compare_int (void);
377354
extern cycle_t gic_read_count(void);

‎arch/mips/include/asm/mips-boards/maltaint.h

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -20,11 +20,10 @@
2020
#define MIPSCPU_INT_SW1 1
2121
#define MIPSCPU_INT_MB0 2
2222
#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
23+
#define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */
2324
#define MIPSCPU_INT_MB1 3
2425
#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
25-
#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */
2626
#define MIPSCPU_INT_MB2 4
27-
#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */
2827
#define MIPSCPU_INT_MB3 5
2928
#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
3029
#define MIPSCPU_INT_MB4 6
@@ -61,14 +60,7 @@
6160
#define MSC01E_INT_PERFCTR 10
6261
#define MSC01E_INT_CPUCTR 11
6362

64-
/* External Interrupts used for IPI */
65-
#define GIC_IPI_EXT_INTR_RESCHED_VPE0 16
66-
#define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17
67-
#define GIC_IPI_EXT_INTR_RESCHED_VPE1 18
68-
#define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19
69-
#define GIC_IPI_EXT_INTR_RESCHED_VPE2 20
70-
#define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21
71-
#define GIC_IPI_EXT_INTR_RESCHED_VPE3 22
72-
#define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23
63+
/* GIC external interrupts */
64+
#define GIC_INT_I8259A 3
7365

7466
#endif /* !(_MIPS_MALTAINT_H) */

‎arch/mips/include/asm/mips-boards/sead3int.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,4 +14,17 @@
1414
#define GIC_BASE_ADDR 0x1b1c0000
1515
#define GIC_ADDRSPACE_SZ (128 * 1024)
1616

17+
/* CPU interrupt offsets */
18+
#define CPU_INT_GIC 2
19+
#define CPU_INT_EHCI 2
20+
#define CPU_INT_UART0 4
21+
#define CPU_INT_UART1 4
22+
#define CPU_INT_NET 6
23+
24+
/* GIC interrupt offsets */
25+
#define GIC_INT_NET 0
26+
#define GIC_INT_UART1 2
27+
#define GIC_INT_UART0 3
28+
#define GIC_INT_EHCI 5
29+
1730
#endif /* !(_MIPS_SEAD3INT_H) */

‎arch/mips/kernel/cevt-gic.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,8 @@ int gic_clockevent_init(void)
9191

9292
clockevents_register_device(cd);
9393

94-
GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_MAP), 0x80000002);
94+
GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_MAP),
95+
GIC_MAP_TO_PIN_MSK | gic_cpu_pin);
9596
GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), GIC_VPE_SMASK_CMP_MSK);
9697

9798
if (gic_timer_irq_installed)

‎arch/mips/mti-malta/malta-int.c

Lines changed: 36 additions & 153 deletions
Original file line numberDiff line numberDiff line change
@@ -38,14 +38,9 @@
3838
#include <asm/rtlx.h>
3939

4040
static unsigned long _msc01_biu_base;
41-
static unsigned int ipi_map[NR_CPUS];
4241

4342
static DEFINE_RAW_SPINLOCK(mips_irq_lock);
4443

45-
#ifdef CONFIG_MIPS_GIC_IPI
46-
DECLARE_BITMAP(ipi_ints, GIC_NUM_INTRS);
47-
#endif
48-
4944
static inline int mips_pcibios_iack(void)
5045
{
5146
int irq;
@@ -127,24 +122,10 @@ static void malta_hw0_irqdispatch(void)
127122
#endif
128123
}
129124

130-
static void malta_ipi_irqdispatch(void)
125+
static irqreturn_t i8259_handler(int irq, void *dev_id)
131126
{
132-
#ifdef CONFIG_MIPS_GIC_IPI
133-
unsigned long irq;
134-
DECLARE_BITMAP(pending, GIC_NUM_INTRS);
135-
136-
gic_get_int_mask(pending, ipi_ints);
137-
138-
irq = find_first_bit(pending, GIC_NUM_INTRS);
139-
140-
while (irq < GIC_NUM_INTRS) {
141-
do_IRQ(MIPS_GIC_IRQ_BASE + irq);
142-
143-
irq = find_next_bit(pending, GIC_NUM_INTRS, irq + 1);
144-
}
145-
#endif
146-
if (gic_compare_int())
147-
do_IRQ(MIPS_GIC_IRQ_BASE);
127+
malta_hw0_irqdispatch();
128+
return IRQ_HANDLED;
148129
}
149130

150131
static void corehi_irqdispatch(void)
@@ -203,6 +184,12 @@ static void corehi_irqdispatch(void)
203184
die("CoreHi interrupt", regs);
204185
}
205186

187+
static irqreturn_t corehi_handler(int irq, void *dev_id)
188+
{
189+
corehi_irqdispatch();
190+
return IRQ_HANDLED;
191+
}
192+
206193
static inline int clz(unsigned long x)
207194
{
208195
__asm__(
@@ -286,10 +273,9 @@ asmlinkage void plat_irq_dispatch(void)
286273

287274
irq = irq_ffs(pending);
288275

289-
if (irq == MIPSCPU_INT_I8259A)
290-
malta_hw0_irqdispatch();
291-
else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
292-
malta_ipi_irqdispatch();
276+
/* HACK: GIC doesn't properly dispatch local interrupts yet */
277+
if (gic_present && irq == MIPSCPU_INT_GIC && gic_compare_int())
278+
do_IRQ(MIPS_GIC_IRQ_BASE);
293279
else
294280
do_IRQ(MIPS_CPU_IRQ_BASE + irq);
295281
}
@@ -312,13 +298,6 @@ static void ipi_call_dispatch(void)
312298
do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
313299
}
314300

315-
#endif /* CONFIG_MIPS_MT_SMP */
316-
317-
#ifdef CONFIG_MIPS_GIC_IPI
318-
319-
#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3
320-
#define GIC_MIPS_CPU_IPI_CALL_IRQ 4
321-
322301
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
323302
{
324303
#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
@@ -349,31 +328,16 @@ static struct irqaction irq_call = {
349328
.flags = IRQF_PERCPU,
350329
.name = "IPI_call"
351330
};
352-
#endif /* CONFIG_MIPS_GIC_IPI */
353-
354-
static int gic_resched_int_base;
355-
static int gic_call_int_base;
356-
#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
357-
#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
358-
359-
unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
360-
{
361-
return GIC_CALL_INT(cpu);
362-
}
363-
364-
unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
365-
{
366-
return GIC_RESCHED_INT(cpu);
367-
}
331+
#endif /* CONFIG_MIPS_MT_SMP */
368332

369333
static struct irqaction i8259irq = {
370-
.handler = no_action,
334+
.handler = i8259_handler,
371335
.name = "XT-PIC cascade",
372336
.flags = IRQF_NO_THREAD,
373337
};
374338

375339
static struct irqaction corehi_irqaction = {
376-
.handler = no_action,
340+
.handler = corehi_handler,
377341
.name = "CoreHi",
378342
.flags = IRQF_NO_THREAD,
379343
};
@@ -399,60 +363,6 @@ static msc_irqmap_t msc_eicirqmap[] __initdata = {
399363

400364
static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
401365

402-
/*
403-
* This GIC specific tabular array defines the association between External
404-
* Interrupts and CPUs/Core Interrupts. The nature of the External
405-
* Interrupts is also defined here - polarity/trigger.
406-
*/
407-
408-
#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
409-
#define X GIC_UNUSED
410-
411-
static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
412-
{ X, X, X, X, 0 },
413-
{ X, X, X, X, 0 },
414-
{ X, X, X, X, 0 },
415-
{ 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
416-
{ 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
417-
{ 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
418-
{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
419-
{ 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
420-
{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
421-
{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
422-
{ X, X, X, X, 0 },
423-
{ X, X, X, X, 0 },
424-
{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
425-
{ 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
426-
{ 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
427-
{ X, X, X, X, 0 },
428-
/* The remainder of this table is initialised by fill_ipi_map */
429-
};
430-
#undef X
431-
432-
#ifdef CONFIG_MIPS_GIC_IPI
433-
static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
434-
{
435-
int intr = baseintr + cpu;
436-
gic_intr_map[intr].cpunum = cpu;
437-
gic_intr_map[intr].pin = cpupin;
438-
gic_intr_map[intr].polarity = GIC_POL_POS;
439-
gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
440-
gic_intr_map[intr].flags = 0;
441-
ipi_map[cpu] |= (1 << (cpupin + 2));
442-
bitmap_set(ipi_ints, intr, 1);
443-
}
444-
445-
static void __init fill_ipi_map(void)
446-
{
447-
int cpu;
448-
449-
for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
450-
fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
451-
fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
452-
}
453-
}
454-
#endif
455-
456366
void __init arch_init_ipiirq(int irq, struct irqaction *action)
457367
{
458368
setup_irq(irq, action);
@@ -461,6 +371,8 @@ void __init arch_init_ipiirq(int irq, struct irqaction *action)
461371

462372
void __init arch_init_irq(void)
463373
{
374+
int corehi_irq, i8259_irq;
375+
464376
init_i8259_irqs();
465377

466378
if (!cpu_has_veic)
@@ -507,63 +419,20 @@ void __init arch_init_irq(void)
507419
msc_nr_irqs);
508420
}
509421

510-
if (cpu_has_veic) {
511-
set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
512-
set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
513-
setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
514-
setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
515-
} else if (cpu_has_vint) {
516-
set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
517-
set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
518-
setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
519-
setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
520-
&corehi_irqaction);
521-
} else {
522-
setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
523-
setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
524-
&corehi_irqaction);
525-
}
526-
527422
if (gic_present) {
528-
/* FIXME */
529423
int i;
530-
#if defined(CONFIG_MIPS_GIC_IPI)
531-
gic_call_int_base = GIC_NUM_INTRS -
532-
(NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids;
533-
gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
534-
fill_ipi_map();
535-
#endif
536-
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
537-
ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
424+
425+
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC,
426+
MIPS_GIC_IRQ_BASE);
538427
if (!mips_cm_present()) {
539428
/* Enable the GIC */
540429
i = REG(_msc01_biu_base, MSC01_SC_CFG);
541430
REG(_msc01_biu_base, MSC01_SC_CFG) =
542431
(i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
543432
pr_debug("GIC Enabled\n");
544433
}
545-
#if defined(CONFIG_MIPS_GIC_IPI)
546-
/* set up ipi interrupts */
547-
if (cpu_has_vint) {
548-
set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
549-
set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
550-
}
551-
/* Argh.. this really needs sorting out.. */
552-
pr_info("CPU%d: status register was %08x\n",
553-
smp_processor_id(), read_c0_status());
554-
write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
555-
pr_info("CPU%d: status register now %08x\n",
556-
smp_processor_id(), read_c0_status());
557-
write_c0_status(0x1100dc00);
558-
pr_info("CPU%d: status register frc %08x\n",
559-
smp_processor_id(), read_c0_status());
560-
for (i = 0; i < nr_cpu_ids; i++) {
561-
arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
562-
GIC_RESCHED_INT(i), &irq_resched);
563-
arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
564-
GIC_CALL_INT(i), &irq_call);
565-
}
566-
#endif
434+
i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
435+
corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
567436
} else {
568437
#if defined(CONFIG_MIPS_MT_SMP)
569438
/* set up ipi interrupts */
@@ -587,7 +456,21 @@ void __init arch_init_irq(void)
587456
arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
588457
arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
589458
#endif
459+
if (cpu_has_veic) {
460+
set_vi_handler(MSC01E_INT_I8259A,
461+
malta_hw0_irqdispatch);
462+
set_vi_handler(MSC01E_INT_COREHI,
463+
corehi_irqdispatch);
464+
i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A;
465+
corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
466+
} else {
467+
i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A;
468+
corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
469+
}
590470
}
471+
472+
setup_irq(i8259_irq, &i8259irq);
473+
setup_irq(corehi_irq, &corehi_irqaction);
591474
}
592475

593476
void malta_be_init(void)

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