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aikmpe
aik
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mpe
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powerpc/powernv: Move TCE manupulation code to its own file
Right now we have allocation code in pci-ioda.c and traversing code in pci.c, let's keep them toghether. However both files are big enough already so let's move this business to a new file. While we at it, move the code which links IOMMU table groups to IOMMU tables as it is not specific to any PNV PHB model. These puts exported symbols from the new file together. This fixes several warnings from checkpatch.pl like this: "WARNING: Prefer 'unsigned int' to bare use of 'unsigned'". As this is almost cut-n-paste, there should be no behavioral change. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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‎arch/powerpc/platforms/powernv/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ obj-y += opal-msglog.o opal-hmi.o opal-power.o opal-irqchip.o
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obj-y += opal-kmsg.o opal-powercap.o opal-psr.o opal-sensor-groups.o
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obj-$(CONFIG_SMP) += smp.o subcore.o subcore-asm.o
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obj-$(CONFIG_PCI) += pci.o pci-ioda.o npu-dma.o
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obj-$(CONFIG_PCI) += pci.o pci-ioda.o npu-dma.o pci-ioda-tce.o
1010
obj-$(CONFIG_CXL_BASE) += pci-cxl.o
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obj-$(CONFIG_EEH) += eeh-powernv.o
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obj-$(CONFIG_PPC_SCOM) += opal-xscom.o

‎arch/powerpc/platforms/powernv/pci-ioda-tce.c

Lines changed: 313 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,313 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* TCE helpers for IODA PCI/PCIe on PowerNV platforms
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*
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* Copyright 2018 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/iommu.h>
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#include <asm/iommu.h>
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#include <asm/tce.h>
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#include "pci.h"
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void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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void *tce_mem, u64 tce_size,
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u64 dma_offset, unsigned int page_shift)
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{
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tbl->it_blocksize = 16;
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tbl->it_base = (unsigned long)tce_mem;
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tbl->it_page_shift = page_shift;
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tbl->it_offset = dma_offset >> tbl->it_page_shift;
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tbl->it_index = 0;
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tbl->it_size = tce_size >> 3;
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tbl->it_busno = 0;
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tbl->it_type = TCE_PCI;
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}
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static __be64 *pnv_tce(struct iommu_table *tbl, long idx)
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{
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__be64 *tmp = ((__be64 *)tbl->it_base);
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int level = tbl->it_indirect_levels;
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const long shift = ilog2(tbl->it_level_size);
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unsigned long mask = (tbl->it_level_size - 1) << (level * shift);
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while (level) {
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int n = (idx & mask) >> (level * shift);
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unsigned long tce = be64_to_cpu(tmp[n]);
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tmp = __va(tce & ~(TCE_PCI_READ | TCE_PCI_WRITE));
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idx &= ~mask;
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mask >>= shift;
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--level;
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}
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return tmp + idx;
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}
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int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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unsigned long uaddr, enum dma_data_direction direction,
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unsigned long attrs)
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{
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u64 proto_tce = iommu_direction_to_tce_perm(direction);
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u64 rpn = __pa(uaddr) >> tbl->it_page_shift;
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long i;
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if (proto_tce & TCE_PCI_WRITE)
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proto_tce |= TCE_PCI_READ;
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for (i = 0; i < npages; i++) {
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unsigned long newtce = proto_tce |
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((rpn + i) << tbl->it_page_shift);
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unsigned long idx = index - tbl->it_offset + i;
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*(pnv_tce(tbl, idx)) = cpu_to_be64(newtce);
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}
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return 0;
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}
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#ifdef CONFIG_IOMMU_API
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int pnv_tce_xchg(struct iommu_table *tbl, long index,
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unsigned long *hpa, enum dma_data_direction *direction)
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{
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u64 proto_tce = iommu_direction_to_tce_perm(*direction);
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unsigned long newtce = *hpa | proto_tce, oldtce;
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unsigned long idx = index - tbl->it_offset;
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BUG_ON(*hpa & ~IOMMU_PAGE_MASK(tbl));
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if (newtce & TCE_PCI_WRITE)
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newtce |= TCE_PCI_READ;
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oldtce = be64_to_cpu(xchg(pnv_tce(tbl, idx), cpu_to_be64(newtce)));
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*hpa = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE);
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*direction = iommu_tce_direction(oldtce);
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return 0;
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}
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#endif
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void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
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{
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long i;
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for (i = 0; i < npages; i++) {
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unsigned long idx = index - tbl->it_offset + i;
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*(pnv_tce(tbl, idx)) = cpu_to_be64(0);
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}
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}
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unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
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{
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return be64_to_cpu(*(pnv_tce(tbl, index - tbl->it_offset)));
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}
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static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
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unsigned long size, unsigned int levels)
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{
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const unsigned long addr_ul = (unsigned long) addr &
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~(TCE_PCI_READ | TCE_PCI_WRITE);
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if (levels) {
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long i;
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u64 *tmp = (u64 *) addr_ul;
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for (i = 0; i < size; ++i) {
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unsigned long hpa = be64_to_cpu(tmp[i]);
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if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
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continue;
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pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
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levels - 1);
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}
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}
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free_pages(addr_ul, get_order(size << 3));
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}
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void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
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{
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const unsigned long size = tbl->it_indirect_levels ?
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tbl->it_level_size : tbl->it_size;
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if (!tbl->it_size)
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return;
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pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
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tbl->it_indirect_levels);
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}
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static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned int shift,
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unsigned int levels, unsigned long limit,
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unsigned long *current_offset, unsigned long *total_allocated)
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{
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struct page *tce_mem = NULL;
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__be64 *addr, *tmp;
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unsigned int order = max_t(unsigned int, shift, PAGE_SHIFT) -
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PAGE_SHIFT;
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unsigned long allocated = 1UL << (order + PAGE_SHIFT);
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unsigned int entries = 1UL << (shift - 3);
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long i;
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tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
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if (!tce_mem) {
163+
pr_err("Failed to allocate a TCE memory, order=%d\n", order);
164+
return NULL;
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}
166+
addr = page_address(tce_mem);
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memset(addr, 0, allocated);
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*total_allocated += allocated;
169+
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--levels;
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if (!levels) {
172+
*current_offset += allocated;
173+
return addr;
174+
}
175+
176+
for (i = 0; i < entries; ++i) {
177+
tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
178+
levels, limit, current_offset, total_allocated);
179+
if (!tmp)
180+
break;
181+
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addr[i] = cpu_to_be64(__pa(tmp) |
183+
TCE_PCI_READ | TCE_PCI_WRITE);
184+
185+
if (*current_offset >= limit)
186+
break;
187+
}
188+
189+
return addr;
190+
}
191+
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long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
193+
__u32 page_shift, __u64 window_size, __u32 levels,
194+
struct iommu_table *tbl)
195+
{
196+
void *addr;
197+
unsigned long offset = 0, level_shift, total_allocated = 0;
198+
const unsigned int window_shift = ilog2(window_size);
199+
unsigned int entries_shift = window_shift - page_shift;
200+
unsigned int table_shift = max_t(unsigned int, entries_shift + 3,
201+
PAGE_SHIFT);
202+
const unsigned long tce_table_size = 1UL << table_shift;
203+
204+
if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
205+
return -EINVAL;
206+
207+
if (!is_power_of_2(window_size))
208+
return -EINVAL;
209+
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/* Adjust direct table size from window_size and levels */
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entries_shift = (entries_shift + levels - 1) / levels;
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level_shift = entries_shift + 3;
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level_shift = max_t(unsigned int, level_shift, PAGE_SHIFT);
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if ((level_shift - 3) * levels + page_shift >= 60)
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return -EINVAL;
217+
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/* Allocate TCE table */
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addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
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levels, tce_table_size, &offset, &total_allocated);
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/* addr==NULL means that the first level allocation failed */
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if (!addr)
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return -ENOMEM;
225+
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/*
227+
* First level was allocated but some lower level failed as
228+
* we did not allocate as much as we wanted,
229+
* release partially allocated table.
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*/
231+
if (offset < tce_table_size) {
232+
pnv_pci_ioda2_table_do_free_pages(addr,
233+
1ULL << (level_shift - 3), levels - 1);
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return -ENOMEM;
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}
236+
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/* Setup linux iommu table */
238+
pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
239+
page_shift);
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tbl->it_level_size = 1ULL << (level_shift - 3);
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tbl->it_indirect_levels = levels - 1;
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tbl->it_allocated_size = total_allocated;
243+
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pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
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window_size, tce_table_size, bus_offset);
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return 0;
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}
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static void pnv_iommu_table_group_link_free(struct rcu_head *head)
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{
252+
struct iommu_table_group_link *tgl = container_of(head,
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struct iommu_table_group_link, rcu);
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kfree(tgl);
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}
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void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
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struct iommu_table_group *table_group)
260+
{
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long i;
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bool found;
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struct iommu_table_group_link *tgl;
264+
265+
if (!tbl || !table_group)
266+
return;
267+
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/* Remove link to a group from table's list of attached groups */
269+
found = false;
270+
list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
271+
if (tgl->table_group == table_group) {
272+
list_del_rcu(&tgl->next);
273+
call_rcu(&tgl->rcu, pnv_iommu_table_group_link_free);
274+
found = true;
275+
break;
276+
}
277+
}
278+
if (WARN_ON(!found))
279+
return;
280+
281+
/* Clean a pointer to iommu_table in iommu_table_group::tables[] */
282+
found = false;
283+
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
284+
if (table_group->tables[i] == tbl) {
285+
table_group->tables[i] = NULL;
286+
found = true;
287+
break;
288+
}
289+
}
290+
WARN_ON(!found);
291+
}
292+
293+
long pnv_pci_link_table_and_group(int node, int num,
294+
struct iommu_table *tbl,
295+
struct iommu_table_group *table_group)
296+
{
297+
struct iommu_table_group_link *tgl = NULL;
298+
299+
if (WARN_ON(!tbl || !table_group))
300+
return -EINVAL;
301+
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tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL,
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node);
304+
if (!tgl)
305+
return -ENOMEM;
306+
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tgl->table_group = table_group;
308+
list_add_rcu(&tgl->next, &tbl->it_group_list);
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table_group->tables[num] = tbl;
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return 0;
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}

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