irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor

Tirumalesh Chalamarla · Marc Zyngier · commit 1a1ebd5fb1e2 · 2016-02-11T10:20:02.000Z
The ARM GICv3 specification mentions the need for dsb after a read
from the ICC_IAR1_EL1 register:

	4.1.1 Physical CPU Interface:
	The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1
	on the state of a returned INTID are not guaranteed
	to be visible until after the execution of a DSB.

Not having this could result in missed interrupts, so let's add the
required barrier.

[Marc: fixed commit message]

Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Tirumalesh Chalamarla &lt;tchalamarla@caviumnetworks.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
@@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void)
 	u64 irqstat;
 
 	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
+	dsb(sy);
 	return irqstat;
 }
 

Original file line number	Diff line number	Diff line change
`@@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void)`
`103`	`103`	`u64 irqstat;`
`104`	`104`
`105`	`105`	`asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));`
	`106`	`+ dsb(sy);`
`106`	`107`	`return irqstat;`
`107`	`108`	`}`
`108`	`109`