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tlendackydavem330
tlendacky
authored and
davem330
committed
amd-xgbe: Add support for VXLAN offload capabilities
The hardware has the capability to perform checksum offload support (both Tx and Rx) and TSO support for VXLAN packets. Add the support required to enable this. The hardware can only support a single VXLAN port for offload. If more than one VXLAN port is added then the offload capabilities have to be disabled and can no longer be advertised. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent 85f9feb commit 1a510cc

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+520
-6
lines changed

5 files changed

+520
-6
lines changed

‎drivers/net/ethernet/amd/xgbe/xgbe-common.h

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -298,6 +298,7 @@
298298
#define MAC_RWKPFR 0x00c4
299299
#define MAC_LPICSR 0x00d0
300300
#define MAC_LPITCR 0x00d4
301+
#define MAC_TIR 0x00e0
301302
#define MAC_VR 0x0110
302303
#define MAC_DR 0x0114
303304
#define MAC_HWF0R 0x011c
@@ -364,6 +365,8 @@
364365
#define MAC_HWF0R_TXCOESEL_WIDTH 1
365366
#define MAC_HWF0R_VLHASH_INDEX 4
366367
#define MAC_HWF0R_VLHASH_WIDTH 1
368+
#define MAC_HWF0R_VXN_INDEX 29
369+
#define MAC_HWF0R_VXN_WIDTH 1
367370
#define MAC_HWF1R_ADDR64_INDEX 14
368371
#define MAC_HWF1R_ADDR64_WIDTH 2
369372
#define MAC_HWF1R_ADVTHWORD_INDEX 13
@@ -448,6 +451,8 @@
448451
#define MAC_PFR_PR_WIDTH 1
449452
#define MAC_PFR_VTFE_INDEX 16
450453
#define MAC_PFR_VTFE_WIDTH 1
454+
#define MAC_PFR_VUCC_INDEX 22
455+
#define MAC_PFR_VUCC_WIDTH 1
451456
#define MAC_PMTCSR_MGKPKTEN_INDEX 1
452457
#define MAC_PMTCSR_MGKPKTEN_WIDTH 1
453458
#define MAC_PMTCSR_PWRDWN_INDEX 0
@@ -510,6 +515,12 @@
510515
#define MAC_TCR_SS_WIDTH 2
511516
#define MAC_TCR_TE_INDEX 0
512517
#define MAC_TCR_TE_WIDTH 1
518+
#define MAC_TCR_VNE_INDEX 24
519+
#define MAC_TCR_VNE_WIDTH 1
520+
#define MAC_TCR_VNM_INDEX 25
521+
#define MAC_TCR_VNM_WIDTH 1
522+
#define MAC_TIR_TNID_INDEX 0
523+
#define MAC_TIR_TNID_WIDTH 16
513524
#define MAC_TSCR_AV8021ASMEN_INDEX 28
514525
#define MAC_TSCR_AV8021ASMEN_WIDTH 1
515526
#define MAC_TSCR_SNAPTYPSEL_INDEX 16
@@ -1153,11 +1164,17 @@
11531164
#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
11541165
#define RX_PACKET_ATTRIBUTES_FIRST_INDEX 7
11551166
#define RX_PACKET_ATTRIBUTES_FIRST_WIDTH 1
1167+
#define RX_PACKET_ATTRIBUTES_TNP_INDEX 8
1168+
#define RX_PACKET_ATTRIBUTES_TNP_WIDTH 1
1169+
#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX 9
1170+
#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH 1
11561171

11571172
#define RX_NORMAL_DESC0_OVT_INDEX 0
11581173
#define RX_NORMAL_DESC0_OVT_WIDTH 16
11591174
#define RX_NORMAL_DESC2_HL_INDEX 0
11601175
#define RX_NORMAL_DESC2_HL_WIDTH 10
1176+
#define RX_NORMAL_DESC2_TNP_INDEX 11
1177+
#define RX_NORMAL_DESC2_TNP_WIDTH 1
11611178
#define RX_NORMAL_DESC3_CDA_INDEX 27
11621179
#define RX_NORMAL_DESC3_CDA_WIDTH 1
11631180
#define RX_NORMAL_DESC3_CTXT_INDEX 30
@@ -1184,9 +1201,11 @@
11841201
#define RX_DESC3_L34T_IPV4_TCP 1
11851202
#define RX_DESC3_L34T_IPV4_UDP 2
11861203
#define RX_DESC3_L34T_IPV4_ICMP 3
1204+
#define RX_DESC3_L34T_IPV4_UNKNOWN 7
11871205
#define RX_DESC3_L34T_IPV6_TCP 9
11881206
#define RX_DESC3_L34T_IPV6_UDP 10
11891207
#define RX_DESC3_L34T_IPV6_ICMP 11
1208+
#define RX_DESC3_L34T_IPV6_UNKNOWN 15
11901209

11911210
#define RX_CONTEXT_DESC3_TSA_INDEX 4
11921211
#define RX_CONTEXT_DESC3_TSA_WIDTH 1
@@ -1201,6 +1220,8 @@
12011220
#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
12021221
#define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
12031222
#define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
1223+
#define TX_PACKET_ATTRIBUTES_VXLAN_INDEX 4
1224+
#define TX_PACKET_ATTRIBUTES_VXLAN_WIDTH 1
12041225

12051226
#define TX_CONTEXT_DESC2_MSS_INDEX 0
12061227
#define TX_CONTEXT_DESC2_MSS_WIDTH 15
@@ -1241,8 +1262,11 @@
12411262
#define TX_NORMAL_DESC3_TCPPL_WIDTH 18
12421263
#define TX_NORMAL_DESC3_TSE_INDEX 18
12431264
#define TX_NORMAL_DESC3_TSE_WIDTH 1
1265+
#define TX_NORMAL_DESC3_VNP_INDEX 23
1266+
#define TX_NORMAL_DESC3_VNP_WIDTH 3
12441267

12451268
#define TX_NORMAL_DESC2_VLAN_INSERT 0x2
1269+
#define TX_NORMAL_DESC3_VXLAN_PACKET 0x3
12461270

12471271
/* MDIO undefined or vendor specific registers */
12481272
#ifndef MDIO_PMA_10GBR_PMD_CTRL

‎drivers/net/ethernet/amd/xgbe/xgbe-dev.c

Lines changed: 88 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -479,6 +479,50 @@ static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata,
479479
return false;
480480
}
481481

482+
static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata)
483+
{
484+
/* Program the VXLAN port */
485+
XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port);
486+
487+
netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n",
488+
pdata->vxlan_port);
489+
}
490+
491+
static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata)
492+
{
493+
if (!pdata->hw_feat.vxn)
494+
return;
495+
496+
/* Program the VXLAN port */
497+
xgbe_set_vxlan_id(pdata);
498+
499+
/* Allow for IPv6/UDP zero-checksum VXLAN packets */
500+
XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1);
501+
502+
/* Enable VXLAN tunneling mode */
503+
XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0);
504+
XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1);
505+
506+
netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n");
507+
}
508+
509+
static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata)
510+
{
511+
if (!pdata->hw_feat.vxn)
512+
return;
513+
514+
/* Disable tunneling mode */
515+
XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0);
516+
517+
/* Clear IPv6/UDP zero-checksum VXLAN packets setting */
518+
XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0);
519+
520+
/* Clear the VXLAN port */
521+
XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0);
522+
523+
netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n");
524+
}
525+
482526
static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
483527
{
484528
unsigned int max_q_count, q_count;
@@ -1610,7 +1654,7 @@ static void xgbe_dev_xmit(struct xgbe_channel *channel)
16101654
struct xgbe_ring_desc *rdesc;
16111655
struct xgbe_packet_data *packet = &ring->packet_data;
16121656
unsigned int tx_packets, tx_bytes;
1613-
unsigned int csum, tso, vlan;
1657+
unsigned int csum, tso, vlan, vxlan;
16141658
unsigned int tso_context, vlan_context;
16151659
unsigned int tx_set_ic;
16161660
int start_index = ring->cur;
@@ -1628,6 +1672,8 @@ static void xgbe_dev_xmit(struct xgbe_channel *channel)
16281672
TSO_ENABLE);
16291673
vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
16301674
VLAN_CTAG);
1675+
vxlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1676+
VXLAN);
16311677

16321678
if (tso && (packet->mss != ring->tx.cur_mss))
16331679
tso_context = 1;
@@ -1759,6 +1805,10 @@ static void xgbe_dev_xmit(struct xgbe_channel *channel)
17591805
packet->length);
17601806
}
17611807

1808+
if (vxlan)
1809+
XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, VNP,
1810+
TX_NORMAL_DESC3_VXLAN_PACKET);
1811+
17621812
for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
17631813
cur_index++;
17641814
rdata = XGBE_GET_DESC_DATA(ring, cur_index);
@@ -1920,9 +1970,27 @@ static int xgbe_dev_read(struct xgbe_channel *channel)
19201970
rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
19211971

19221972
/* Set checksum done indicator as appropriate */
1923-
if (netdev->features & NETIF_F_RXCSUM)
1973+
if (netdev->features & NETIF_F_RXCSUM) {
19241974
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
19251975
CSUM_DONE, 1);
1976+
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1977+
TNPCSUM_DONE, 1);
1978+
}
1979+
1980+
/* Set the tunneled packet indicator */
1981+
if (XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, TNP)) {
1982+
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1983+
TNP, 1);
1984+
1985+
l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1986+
switch (l34t) {
1987+
case RX_DESC3_L34T_IPV4_UNKNOWN:
1988+
case RX_DESC3_L34T_IPV6_UNKNOWN:
1989+
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1990+
TNPCSUM_DONE, 0);
1991+
break;
1992+
}
1993+
}
19261994

19271995
/* Check for errors (only valid in last descriptor) */
19281996
err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
@@ -1942,12 +2010,23 @@ static int xgbe_dev_read(struct xgbe_channel *channel)
19422010
packet->vlan_ctag);
19432011
}
19442012
} else {
1945-
if ((etlt == 0x05) || (etlt == 0x06))
2013+
unsigned int tnp = XGMAC_GET_BITS(packet->attributes,
2014+
RX_PACKET_ATTRIBUTES, TNP);
2015+
2016+
if ((etlt == 0x05) || (etlt == 0x06)) {
19462017
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
19472018
CSUM_DONE, 0);
1948-
else
2019+
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2020+
TNPCSUM_DONE, 0);
2021+
} else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) {
2022+
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2023+
CSUM_DONE, 0);
2024+
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2025+
TNPCSUM_DONE, 0);
2026+
} else {
19492027
XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
19502028
FRAME, 1);
2029+
}
19512030
}
19522031

19532032
pdata->ext_stats.rxq_packets[channel->queue_index]++;
@@ -3536,5 +3615,10 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
35363615
hw_if->disable_ecc_ded = xgbe_disable_ecc_ded;
35373616
hw_if->disable_ecc_sec = xgbe_disable_ecc_sec;
35383617

3618+
/* For VXLAN */
3619+
hw_if->enable_vxlan = xgbe_enable_vxlan;
3620+
hw_if->disable_vxlan = xgbe_disable_vxlan;
3621+
hw_if->set_vxlan_id = xgbe_set_vxlan_id;
3622+
35393623
DBGPR("<--xgbe_init_function_ptrs\n");
35403624
}

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