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author
Ingo Molnar
committed
Merge branch 'clockevents/3.14' of git://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clocksource/clockevent updates from Daniel Lezcano: * Axel Lin removed an unused structure defining the ids for the bcm kona driver. * Ezequiel Garcia enabled the timer divider only when the 25MHz timer is not used for the armada 370 XP. * Jingoo Han removed a pointless platform data initialization for the sh_mtu and sh_mtu2. * Laurent Pinchart added the clk_prepare/clk_unprepare for sh_cmt. * Linus Walleij added a useful warning in clk_of when no clocks are found while the old behavior was to silently hang at boot time. * Maxime Ripard added the high speed timer drivers for the Allwinner SoCs (A10, A13, A20). He increased the rating, shared the irq across all available cpus and fixed the clockevent's irq initialization for the sun4i. * Michael Opdenacker removed the usage of the IRQF_DISABLED for the all the timers driver located in drivers/clocksource. * Stephen Boyd switched to sched_clock_register for the arm_global_timer, cadence_ttc, sun4i and orion timers. Conflicts: drivers/clocksource/clksrc-of.c Signed-off-by: Ingo Molnar <mingo@kernel.org>
2 parents d05d24a + 98aefbe commit 1b3f828

24 files changed

+295
-47
lines changed

‎Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
Allwinner SoCs High Speed Timer Controller
2+
3+
Required properties:
4+
5+
- compatible : should be "allwinner,sun5i-a13-hstimer" or
6+
"allwinner,sun7i-a20-hstimer"
7+
- reg : Specifies base physical address and size of the registers.
8+
- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
9+
one)
10+
- clocks: phandle to the source clock (usually the AHB clock)
11+
12+
Example:
13+
14+
timer@01c60000 {
15+
compatible = "allwinner,sun7i-a20-hstimer";
16+
reg = <0x01c60000 0x1000>;
17+
interrupts = <0 51 1>,
18+
<0 52 1>,
19+
<0 53 1>,
20+
<0 54 1>;
21+
clocks = <&ahb1_gates 19>;
22+
};

‎arch/arm/boot/dts/sun5i-a10s.dtsi

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -332,5 +332,12 @@
332332
clock-frequency = <100000>;
333333
status = "disabled";
334334
};
335+
336+
timer@01c60000 {
337+
compatible = "allwinner,sun5i-a13-hstimer";
338+
reg = <0x01c60000 0x1000>;
339+
interrupts = <82>, <83>;
340+
clocks = <&ahb_gates 28>;
341+
};
335342
};
336343
};

‎arch/arm/boot/dts/sun5i-a13.dtsi

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -273,5 +273,12 @@
273273
clock-frequency = <100000>;
274274
status = "disabled";
275275
};
276+
277+
timer@01c60000 {
278+
compatible = "allwinner,sun5i-a13-hstimer";
279+
reg = <0x01c60000 0x1000>;
280+
interrupts = <82>, <83>;
281+
clocks = <&ahb_gates 28>;
282+
};
276283
};
277284
};

‎arch/arm/boot/dts/sun7i-a20.dtsi

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -395,6 +395,16 @@
395395
status = "disabled";
396396
};
397397

398+
hstimer@01c60000 {
399+
compatible = "allwinner,sun7i-a20-hstimer";
400+
reg = <0x01c60000 0x1000>;
401+
interrupts = <0 81 1>,
402+
<0 82 1>,
403+
<0 83 1>,
404+
<0 84 1>;
405+
clocks = <&ahb_gates 28>;
406+
};
407+
398408
gic: interrupt-controller@01c81000 {
399409
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
400410
reg = <0x01c81000 0x1000>,

‎arch/arm/mach-sunxi/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,3 +12,4 @@ config ARCH_SUNXI
1212
select PINCTRL_SUNXI
1313
select SPARSE_IRQ
1414
select SUN4I_TIMER
15+
select SUN5I_HSTIMER

‎drivers/clocksource/Kconfig

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,10 @@ config SUN4I_TIMER
3737
select CLKSRC_MMIO
3838
bool
3939

40+
config SUN5I_HSTIMER
41+
select CLKSRC_MMIO
42+
bool
43+
4044
config VT8500_TIMER
4145
bool
4246

‎drivers/clocksource/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
2222
obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
2323
obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
2424
obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
25+
obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o
2526
obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
2627
obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
2728
obj-$(CONFIG_ARCH_NSPIRE) += zevio-timer.o

‎drivers/clocksource/arm_global_timer.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,7 @@ static struct clocksource gt_clocksource = {
202202
};
203203

204204
#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
205-
static u32 notrace gt_sched_clock_read(void)
205+
static u64 notrace gt_sched_clock_read(void)
206206
{
207207
return gt_counter_read();
208208
}
@@ -217,7 +217,7 @@ static void __init gt_clocksource_init(void)
217217
writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
218218

219219
#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
220-
setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate);
220+
sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
221221
#endif
222222
clocksource_register_hz(&gt_clocksource, gt_clk_rate);
223223
}

‎drivers/clocksource/bcm_kona_timer.c

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -98,12 +98,6 @@ kona_timer_get_counter(void *timer_base, uint32_t *msw, uint32_t *lsw)
9898
return;
9999
}
100100

101-
static const struct of_device_id bcm_timer_ids[] __initconst = {
102-
{.compatible = "brcm,kona-timer"},
103-
{.compatible = "bcm,kona-timer"}, /* deprecated name */
104-
{},
105-
};
106-
107101
static void __init kona_timers_init(struct device_node *node)
108102
{
109103
u32 freq;

‎drivers/clocksource/cadence_ttc_timer.c

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -158,7 +158,7 @@ static cycle_t __ttc_clocksource_read(struct clocksource *cs)
158158
TTC_COUNT_VAL_OFFSET);
159159
}
160160

161-
static u32 notrace ttc_sched_clock_read(void)
161+
static u64 notrace ttc_sched_clock_read(void)
162162
{
163163
return __raw_readl(ttc_sched_clock_val_reg);
164164
}
@@ -306,7 +306,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
306306
}
307307

308308
ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
309-
setup_sched_clock(ttc_sched_clock_read, 16,
309+
sched_clock_register(ttc_sched_clock_read, 16,
310310
clk_get_rate(ttccs->ttc.clk) / PRESCALE);
311311
}
312312

@@ -388,8 +388,7 @@ static void __init ttc_setup_clockevent(struct clk *clk,
388388
__raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
389389

390390
err = request_irq(irq, ttc_clock_event_interrupt,
391-
IRQF_DISABLED | IRQF_TIMER,
392-
ttcce->ce.name, ttcce);
391+
IRQF_TIMER, ttcce->ce.name, ttcce);
393392
if (WARN_ON(err)) {
394393
kfree(ttcce);
395394
return;

‎drivers/clocksource/clksrc-of.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,12 +28,16 @@ void __init clocksource_of_init(void)
2828
struct device_node *np;
2929
const struct of_device_id *match;
3030
clocksource_of_init_fn init_func;
31+
unsigned clocksources = 0;
3132

3233
for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
3334
if (!of_device_is_available(np))
3435
continue;
3536

3637
init_func = match->data;
3738
init_func(np);
39+
clocksources++;
3840
}
41+
if (!clocksources)
42+
pr_crit("%s: no matching clocksources found\n", __func__);
3943
}

‎drivers/clocksource/cs5535-clockevt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@ static irqreturn_t mfgpt_tick(int irq, void *dev_id)
131131

132132
static struct irqaction mfgptirq = {
133133
.handler = mfgpt_tick,
134-
.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
134+
.flags = IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
135135
.name = DRV_NAME,
136136
};
137137

‎drivers/clocksource/dw_apb_timer.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -243,8 +243,7 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
243243
dw_ced->irqaction.dev_id = &dw_ced->ced;
244244
dw_ced->irqaction.irq = irq;
245245
dw_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL |
246-
IRQF_NOBALANCING |
247-
IRQF_DISABLED;
246+
IRQF_NOBALANCING;
248247

249248
dw_ced->eoi = apbt_eoi;
250249
err = setup_irq(irq, &dw_ced->irqaction);

‎drivers/clocksource/nomadik-mtu.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
187187

188188
static struct irqaction nmdk_timer_irq = {
189189
.name = "Nomadik Timer Tick",
190-
.flags = IRQF_DISABLED | IRQF_TIMER,
190+
.flags = IRQF_TIMER,
191191
.handler = nmdk_timer_interrupt,
192192
.dev_id = &nmdk_clkevt,
193193
};

‎drivers/clocksource/samsung_pwm_timer.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -264,7 +264,7 @@ static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
264264

265265
static struct irqaction samsung_clock_event_irq = {
266266
.name = "samsung_time_irq",
267-
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
267+
.flags = IRQF_TIMER | IRQF_IRQPOLL,
268268
.handler = samsung_clock_event_isr,
269269
.dev_id = &time_event_device,
270270
};

‎drivers/clocksource/sh_cmt.c

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -634,12 +634,18 @@ static int sh_cmt_clock_event_next(unsigned long delta,
634634

635635
static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
636636
{
637-
pm_genpd_syscore_poweroff(&ced_to_sh_cmt(ced)->pdev->dev);
637+
struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
638+
639+
pm_genpd_syscore_poweroff(&p->pdev->dev);
640+
clk_unprepare(p->clk);
638641
}
639642

640643
static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
641644
{
642-
pm_genpd_syscore_poweron(&ced_to_sh_cmt(ced)->pdev->dev);
645+
struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
646+
647+
clk_prepare(p->clk);
648+
pm_genpd_syscore_poweron(&p->pdev->dev);
643649
}
644650

645651
static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
@@ -726,8 +732,7 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
726732
p->irqaction.name = dev_name(&p->pdev->dev);
727733
p->irqaction.handler = sh_cmt_interrupt;
728734
p->irqaction.dev_id = p;
729-
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
730-
IRQF_IRQPOLL | IRQF_NOBALANCING;
735+
p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
731736

732737
/* get hold of clock */
733738
p->clk = clk_get(&p->pdev->dev, "cmt_fck");
@@ -737,6 +742,10 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
737742
goto err2;
738743
}
739744

745+
ret = clk_prepare(p->clk);
746+
if (ret < 0)
747+
goto err3;
748+
740749
if (res2 && (resource_size(res2) == 4)) {
741750
/* assume both CMSTR and CMCSR to be 32-bit */
742751
p->read_control = sh_cmt_read32;
@@ -773,19 +782,21 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
773782
cfg->clocksource_rating);
774783
if (ret) {
775784
dev_err(&p->pdev->dev, "registration failed\n");
776-
goto err3;
785+
goto err4;
777786
}
778787
p->cs_enabled = false;
779788

780789
ret = setup_irq(irq, &p->irqaction);
781790
if (ret) {
782791
dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
783-
goto err3;
792+
goto err4;
784793
}
785794

786795
platform_set_drvdata(pdev, p);
787796

788797
return 0;
798+
err4:
799+
clk_unprepare(p->clk);
789800
err3:
790801
clk_put(p->clk);
791802
err2:

‎drivers/clocksource/sh_mtu2.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -302,8 +302,7 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
302302
p->irqaction.handler = sh_mtu2_interrupt;
303303
p->irqaction.dev_id = p;
304304
p->irqaction.irq = irq;
305-
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
306-
IRQF_IRQPOLL | IRQF_NOBALANCING;
305+
p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
307306

308307
/* get hold of clock */
309308
p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
@@ -358,7 +357,6 @@ static int sh_mtu2_probe(struct platform_device *pdev)
358357
ret = sh_mtu2_setup(p, pdev);
359358
if (ret) {
360359
kfree(p);
361-
platform_set_drvdata(pdev, NULL);
362360
pm_runtime_idle(&pdev->dev);
363361
return ret;
364362
}

‎drivers/clocksource/sh_tmu.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -462,8 +462,7 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
462462
p->irqaction.handler = sh_tmu_interrupt;
463463
p->irqaction.dev_id = p;
464464
p->irqaction.irq = irq;
465-
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
466-
IRQF_IRQPOLL | IRQF_NOBALANCING;
465+
p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
467466

468467
/* get hold of clock */
469468
p->clk = clk_get(&p->pdev->dev, "tmu_fck");
@@ -523,7 +522,6 @@ static int sh_tmu_probe(struct platform_device *pdev)
523522
ret = sh_tmu_setup(p, pdev);
524523
if (ret) {
525524
kfree(p);
526-
platform_set_drvdata(pdev, NULL);
527525
pm_runtime_idle(&pdev->dev);
528526
return ret;
529527
}

‎drivers/clocksource/sun4i_timer.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ static int sun4i_clkevt_next_event(unsigned long evt,
114114

115115
static struct clock_event_device sun4i_clockevent = {
116116
.name = "sun4i_tick",
117-
.rating = 300,
117+
.rating = 350,
118118
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
119119
.set_mode = sun4i_clkevt_mode,
120120
.set_next_event = sun4i_clkevt_next_event,
@@ -138,7 +138,7 @@ static struct irqaction sun4i_timer_irq = {
138138
.dev_id = &sun4i_clockevent,
139139
};
140140

141-
static u32 sun4i_timer_sched_read(void)
141+
static u64 notrace sun4i_timer_sched_read(void)
142142
{
143143
return ~readl(timer_base + TIMER_CNTVAL_REG(1));
144144
}
@@ -170,9 +170,9 @@ static void __init sun4i_timer_init(struct device_node *node)
170170
TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
171171
timer_base + TIMER_CTL_REG(1));
172172

173-
setup_sched_clock(sun4i_timer_sched_read, 32, rate);
173+
sched_clock_register(sun4i_timer_sched_read, 32, rate);
174174
clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
175-
rate, 300, 32, clocksource_mmio_readl_down);
175+
rate, 350, 32, clocksource_mmio_readl_down);
176176

177177
ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
178178

@@ -190,7 +190,8 @@ static void __init sun4i_timer_init(struct device_node *node)
190190
val = readl(timer_base + TIMER_IRQ_EN_REG);
191191
writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
192192

193-
sun4i_clockevent.cpumask = cpumask_of(0);
193+
sun4i_clockevent.cpumask = cpu_possible_mask;
194+
sun4i_clockevent.irq = irq;
194195

195196
clockevents_config_and_register(&sun4i_clockevent, rate,
196197
TIMER_SYNC_TICKS, 0xffffffff);

‎drivers/clocksource/tegra20_timer.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
149149

150150
static struct irqaction tegra_timer_irq = {
151151
.name = "timer0",
152-
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
152+
.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
153153
.handler = tegra_timer_interrupt,
154154
.dev_id = &tegra_clockevent,
155155
};

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