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Peter UjfalusiVinod Koul
Peter Ujfalusi
authored and
Vinod Koul
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dmaengine: edma: New device tree binding
With the old binding and driver architecture we had many issues: No way to assign eDMA channels to event queues, thus not able to tune the system by moving specific DMA channels to low/high priority servicing. We moved the cyclic channels to high priority within the code, but that was just a workaround to this issue. Memcopy was fundamentally broken: even if the driver scanned the DT/devices in the booted system for direct DMA users (which is not effective when the events are going through a crossbar) and created a map of 'used' channels, this information was not really usable. Since via dmaengien API the eDMA driver will be called with _some_ channel number, we would try to request this channel when any channel is requested for memcpy. By luck we got channel which is not used by any device most of the time so things worked, but if a device would have been using the given channel, but not requested it, the memcpy channel would have been waiting for HW event. The old code had the am33xx/am43xx DMA event router handling embedded. This should have been done in a separate driver since it is not part of the actual eDMA IP. There were no way to 'lock' PaRAM slots to be used by the DSP for example when booting with DT. In DT boot the edma node used more than one hwmod which is not a good practice and the kernel prints warning because of this. With the new bindings and the changes in the driver we can: - No regression with Legacy binding and non DT boot - DMA channels can be assigned to any TC (to set priority) - PaRAM slots can be reserved for other cores to use - Dynamic power management for CC and TCs, if only TC0 is used all other TC can be powered down for example Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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‎Documentation/devicetree/bindings/dma/ti-edma.txt

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TI EDMA
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Texas Instruments eDMA
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The eDMA3 consists of two components: Channel controller (CC) and Transfer
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Controller(s) (TC). The CC is the main entry for DMA users since it is
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responsible for the DMA channel handling, while the TCs are responsible to
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execute the actual DMA tansfer.
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------------------------------------------------------------------------------
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eDMA3 Channel Controller
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Required properties:
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- compatible: "ti,edma3-tpcc" for the channel controller(s)
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- #dma-cells: Should be set to <2>. The first number is the DMA request
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number and the second is the TC the channel is serviced on.
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- reg: Memory map of eDMA CC
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- reg-names: "edma3_cc"
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- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
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- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint"
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- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
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<&tptc_phandle TC_priority_number>. The highest priority is 0.
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Optional properties:
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- ti,hwmods: Name of the hwmods associated to the eDMA CC
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- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
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these channels will be SW triggered channels. The list must
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contain 16 bits numbers, see example.
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- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
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the driver, they are allocated to be used by for example the
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DSP. See example.
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------------------------------------------------------------------------------
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eDMA3 Transfer Controller
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Required properties:
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- compatible: "ti,edma3-tptc" for the transfer controller(s)
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- reg: Memory map of eDMA TC
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- interrupts: Interrupt number for TCerrint.
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Optional properties:
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- ti,hwmods: Name of the hwmods associated to the given eDMA TC
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- interrupt-names: "edma3_tcerrint"
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------------------------------------------------------------------------------
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Example:
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edma: edma@49000000 {
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compatible = "ti,edma3-tpcc";
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ti,hwmods = "tpcc";
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reg = <0x49000000 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
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/* Channel 20 and 21 is allocated for memcpy */
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ti,edma-memcpy-channels = /bits/ 16 <20 21>;
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/* The following PaRAM slots are reserved: 35-45 and 100-110 */
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ti,edma-reserved-slot-ranges = /bits/ 16 <35 10>,
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/bits/ 16 <100 10>;
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};
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edma_tptc0: tptc@49800000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc0";
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reg = <0x49800000 0x100000>;
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interrupts = <112>;
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interrupt-names = "edm3_tcerrint";
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};
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edma_tptc1: tptc@49900000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc1";
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reg = <0x49900000 0x100000>;
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interrupts = <113>;
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interrupt-names = "edm3_tcerrint";
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};
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edma_tptc2: tptc@49a00000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc2";
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reg = <0x49a00000 0x100000>;
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interrupts = <114>;
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interrupt-names = "edm3_tcerrint";
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};
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sham: sham@53100000 {
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compatible = "ti,omap4-sham";
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ti,hwmods = "sham";
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reg = <0x53100000 0x200>;
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interrupts = <109>;
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/* DMA channel 36 executed on eDMA TC0 - low priority queue */
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dmas = <&edma 36 0>;
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dma-names = "rx";
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};
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mcasp0: mcasp@48038000 {
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compatible = "ti,am33xx-mcasp-audio";
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ti,hwmods = "mcasp0";
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reg = <0x48038000 0x2000>,
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<0x46000000 0x400000>;
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reg-names = "mpu", "dat";
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interrupts = <80>, <81>;
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interrupt-names = "tx", "rx";
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status = "disabled";
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/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
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dmas = <&edma 8 2>,
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<&edma 9 2>;
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dma-names = "tx", "rx";
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};
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------------------------------------------------------------------------------
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DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
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binding.
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Required properties:
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- compatible : "ti,edma3"

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