drm/i915/gen9: Write dc state debugmask bits only once

mikuint · ideak · commit 1e657ad7a48f · 2016-02-22T17:21:04.000+02:00
DMC debugmask bits should stick so no need to write them everytime dc state is changed. v2: Write after firmware has been successfully loaded (Ville) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455808874-22089-5-git-send-email-mika.kuoppala@intel.com
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
@@ -220,19 +220,19 @@ static const struct stepping_info *intel_get_stepping_info(struct drm_device *de
  * Everytime display comes back from low power state this function is called to
  * copy the firmware from internal memory to registers.
  */
-void intel_csr_load_program(struct drm_i915_private *dev_priv)
+bool intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
 	u32 *payload = dev_priv->csr.dmc_payload;
 	uint32_t i, fw_size;
 
 	if (!IS_GEN9(dev_priv)) {
 		DRM_ERROR("No CSR support available for this platform\n");
-		return;
+		return false;
 	}
 
 	if (!dev_priv->csr.dmc_payload) {
 		DRM_ERROR("Tried to program CSR with empty payload\n");
-		return;
+		return false;
 	}
 
 	fw_size = dev_priv->csr.dmc_fw_size;
@@ -245,6 +245,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 	}
 
 	dev_priv->csr.dc_state = 0;
+
+	return true;
 }
 
 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
@@ -1225,7 +1225,7 @@ u32 skl_plane_ctl_rotation(unsigned int rotation);
 
 /* intel_csr.c */
 void intel_csr_ucode_init(struct drm_i915_private *);
-void intel_csr_load_program(struct drm_i915_private *);
+bool intel_csr_load_program(struct drm_i915_private *);
 void intel_csr_ucode_fini(struct drm_i915_private *);
 
 /* intel_dp.c */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -529,9 +529,6 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 	else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
 		state = DC_STATE_EN_UPTO_DC5;
 
-	if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
-		gen9_set_dc_state_debugmask(dev_priv);
-
 	val = I915_READ(DC_STATE_EN);
 	DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 		      val & mask, state);
@@ -2122,8 +2119,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 
 	skl_init_cdclk(dev_priv);
 
-	if (dev_priv->csr.dmc_payload)
-		intel_csr_load_program(dev_priv);
+	if (dev_priv->csr.dmc_payload && intel_csr_load_program(dev_priv))
+		gen9_set_dc_state_debugmask(dev_priv);
 }
 
 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)

Original file line number	Diff line number	Diff line change
`@@ -220,19 +220,19 @@ static const struct stepping_info intel_get_stepping_info(struct drm_device de`
`220`	`220`	`* Everytime display comes back from low power state this function is called to`
`221`	`221`	`* copy the firmware from internal memory to registers.`
`222`	`222`	`*/`
`223`		`-void intel_csr_load_program(struct drm_i915_private *dev_priv)`
	`223`	`+bool intel_csr_load_program(struct drm_i915_private *dev_priv)`
`224`	`224`	`{`
`225`	`225`	`u32 *payload = dev_priv->csr.dmc_payload;`
`226`	`226`	`uint32_t i, fw_size;`
`227`	`227`
`228`	`228`	`if (!IS_GEN9(dev_priv)) {`
`229`	`229`	`DRM_ERROR("No CSR support available for this platform\n");`
`230`		`- return;`
	`230`	`+ return false;`
`231`	`231`	`}`
`232`	`232`
`233`	`233`	`if (!dev_priv->csr.dmc_payload) {`
`234`	`234`	`DRM_ERROR("Tried to program CSR with empty payload\n");`
`235`		`- return;`
	`235`	`+ return false;`
`236`	`236`	`}`
`237`	`237`
`238`	`238`	`fw_size = dev_priv->csr.dmc_fw_size;`
`@@ -245,6 +245,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)`
`245`	`245`	`}`
`246`	`246`
`247`	`247`	`dev_priv->csr.dc_state = 0;`
	`248`	`+`
	`249`	`+ return true;`
`248`	`250`	`}`
`249`	`251`
`250`	`252`	`static uint32_t parse_csr_fw(struct drm_i915_private dev_priv,`