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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
Jeff Kirsher says: ==================== Intel Wired LAN Driver Updates 2015-08-05 This series contains updates to i40e, i40evf and e1000e. Anjali adds support for x772 devices to i40e and i40evf. With the added support, x772 supports offloading of the outer UDP transmit and receive checksum for tunneled packets. Also supports evicting ATR filters in the hardware, so update the driver with this new feature set. Raanan provides several fixes for e1000e, first rectifies the Energy Efficient Ethernet in Sx code so that it only applies to parts that actually support EEE in Sx. Fix whitespace and moved ICH8 related define to the proper context. Fixed the ASPM locking which was reported by Bjorn Helgaas. Fix a workaround implementation for systime which could experience a large non-linear increment of the systime value when checking for overflow. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2 parents d92cff8 + d2d7d4e commit 1ebd08a

23 files changed

+3136
-136
lines changed

‎drivers/net/ethernet/intel/e1000e/ich8lan.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -106,14 +106,14 @@
106106
#define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000
107107

108108
/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
109-
#define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000
109+
#define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000
110110

111111
#define K1_ENTRY_LATENCY 0
112112
#define K1_MIN_TIME 1
113113
#define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field */
114114
#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */
115115
#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
116-
116+
#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29)
117117
#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
118118

119119
#define E1000_ICH_RAR_ENTRIES 7

‎drivers/net/ethernet/intel/e1000e/netdev.c

Lines changed: 51 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@
4848

4949
#define DRV_EXTRAVERSION "-k"
5050

51-
#define DRV_VERSION "3.2.5" DRV_EXTRAVERSION
51+
#define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
5252
char e1000e_driver_name[] = "e1000e";
5353
const char e1000e_driver_version[] = DRV_VERSION;
5454

@@ -4280,18 +4280,29 @@ static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
42804280
struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
42814281
cc);
42824282
struct e1000_hw *hw = &adapter->hw;
4283+
u32 systimel_1, systimel_2, systimeh;
42834284
cycle_t systim, systim_next;
4284-
/* SYSTIMH latching upon SYSTIML read does not work well. To fix that
4285-
* we don't want to allow overflow of SYSTIML and a change to SYSTIMH
4286-
* to occur between reads, so if we read a vale close to overflow, we
4287-
* wait for overflow to occur and read both registers when its safe.
4285+
/* SYSTIMH latching upon SYSTIML read does not work well.
4286+
* This means that if SYSTIML overflows after we read it but before
4287+
* we read SYSTIMH, the value of SYSTIMH has been incremented and we
4288+
* will experience a huge non linear increment in the systime value
4289+
* to fix that we test for overflow and if true, we re-read systime.
42884290
*/
4289-
u32 systim_overflow_latch_fix = 0x3FFFFFFF;
4290-
4291-
do {
4292-
systim = (cycle_t)er32(SYSTIML);
4293-
} while (systim > systim_overflow_latch_fix);
4294-
systim |= (cycle_t)er32(SYSTIMH) << 32;
4291+
systimel_1 = er32(SYSTIML);
4292+
systimeh = er32(SYSTIMH);
4293+
systimel_2 = er32(SYSTIML);
4294+
/* Check for overflow. If there was no overflow, use the values */
4295+
if (systimel_1 < systimel_2) {
4296+
systim = (cycle_t)systimel_1;
4297+
systim |= (cycle_t)systimeh << 32;
4298+
} else {
4299+
/* There was an overflow, read again SYSTIMH, and use
4300+
* systimel_2
4301+
*/
4302+
systimeh = er32(SYSTIMH);
4303+
systim = (cycle_t)systimel_2;
4304+
systim |= (cycle_t)systimeh << 32;
4305+
}
42954306

42964307
if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) {
42974308
u64 incvalue, time_delta, rem, temp;
@@ -6317,6 +6328,33 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
63176328
return retval;
63186329
}
63196330

6331+
/* Ensure that the appropriate bits are set in LPI_CTRL
6332+
* for EEE in Sx
6333+
*/
6334+
if ((hw->phy.type >= e1000_phy_i217) &&
6335+
adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6336+
u16 lpi_ctrl = 0;
6337+
6338+
retval = hw->phy.ops.acquire(hw);
6339+
if (!retval) {
6340+
retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6341+
&lpi_ctrl);
6342+
if (!retval) {
6343+
if (adapter->eee_advert &
6344+
hw->dev_spec.ich8lan.eee_lp_ability &
6345+
I82579_EEE_100_SUPPORTED)
6346+
lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6347+
if (adapter->eee_advert &
6348+
hw->dev_spec.ich8lan.eee_lp_ability &
6349+
I82579_EEE_1000_SUPPORTED)
6350+
lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6351+
6352+
retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6353+
lpi_ctrl);
6354+
}
6355+
}
6356+
hw->phy.ops.release(hw);
6357+
}
63206358

63216359
/* Release control of h/w to f/w. If f/w is AMT enabled, this
63226360
* would have already happened in close and is redundant.
@@ -6466,7 +6504,7 @@ static int __e1000_resume(struct pci_dev *pdev)
64666504
if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
64676505
aspm_disable_flag |= PCIE_LINK_STATE_L1;
64686506
if (aspm_disable_flag)
6469-
e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
6507+
e1000e_disable_aspm(pdev, aspm_disable_flag);
64706508

64716509
pci_set_master(pdev);
64726510

@@ -6744,7 +6782,7 @@ static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
67446782
if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
67456783
aspm_disable_flag |= PCIE_LINK_STATE_L1;
67466784
if (aspm_disable_flag)
6747-
e1000e_disable_aspm(pdev, aspm_disable_flag);
6785+
e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
67486786

67496787
err = pci_enable_device_mem(pdev);
67506788
if (err) {

‎drivers/net/ethernet/intel/e1000e/regs.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,8 @@
3838
#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
3939
#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
4040
#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
41-
#define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */
42-
#define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */
41+
#define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */
42+
#define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */
4343
#define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */
4444
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
4545
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
@@ -125,7 +125,6 @@
125125
(0x054E4 + ((_i - 16) * 8)))
126126
#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
127127
#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
128-
#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29)
129128
#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
130129
#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
131130
#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */

‎drivers/net/ethernet/intel/i40e/i40e.h

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -79,10 +79,13 @@
7979
#define I40E_MIN_MSIX 2
8080
#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
8181
#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */
82-
#define I40E_DEFAULT_QUEUES_PER_VMDQ 2 /* max 16 qps */
82+
/* max 16 qps */
83+
#define i40e_default_queues_per_vmdq(pf) \
84+
(((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
8385
#define I40E_DEFAULT_QUEUES_PER_VF 4
8486
#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
85-
#define I40E_MAX_QUEUES_PER_TC 64 /* should be a power of 2 */
87+
#define i40e_pf_get_max_q_per_tc(pf) \
88+
(((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
8689
#define I40E_FDIR_RING 0
8790
#define I40E_FDIR_RING_COUNT 32
8891
#ifdef I40E_FCOE
@@ -298,6 +301,7 @@ struct i40e_pf {
298301
#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
299302
#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
300303
#define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
304+
#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
301305
#ifdef I40E_FCOE
302306
#define I40E_FLAG_FCOE_ENABLED BIT_ULL(11)
303307
#endif /* I40E_FCOE */
@@ -318,6 +322,12 @@ struct i40e_pf {
318322
#endif
319323
#define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)
320324
#define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
325+
#define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31)
326+
#define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32)
327+
#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33)
328+
#define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34)
329+
#define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35)
330+
#define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38)
321331
#define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)
322332

323333
/* tracks features that get auto disabled by errors */
@@ -550,6 +560,7 @@ struct i40e_q_vector {
550560
cpumask_t affinity_mask;
551561
struct rcu_head rcu; /* to avoid race with update stats on free */
552562
char name[I40E_INT_NAME_STR_LEN];
563+
bool arm_wb_state;
553564
} ____cacheline_internodealigned_in_smp;
554565

555566
/* lan device */

‎drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -257,6 +257,10 @@ enum i40e_admin_queue_opc {
257257
/* Tunnel commands */
258258
i40e_aqc_opc_add_udp_tunnel = 0x0B00,
259259
i40e_aqc_opc_del_udp_tunnel = 0x0B01,
260+
i40e_aqc_opc_set_rss_key = 0x0B02,
261+
i40e_aqc_opc_set_rss_lut = 0x0B03,
262+
i40e_aqc_opc_get_rss_key = 0x0B04,
263+
i40e_aqc_opc_get_rss_lut = 0x0B05,
260264

261265
/* Async Events */
262266
i40e_aqc_opc_event_lan_overflow = 0x1001,
@@ -821,8 +825,12 @@ struct i40e_aqc_vsi_properties_data {
821825
I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
822826
/* queueing option section */
823827
u8 queueing_opt_flags;
828+
#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
829+
#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
824830
#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
825831
#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
832+
#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
833+
#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
826834
u8 queueing_opt_reserved[3];
827835
/* scheduler section */
828836
u8 up_enable_bits;
@@ -2179,6 +2187,46 @@ struct i40e_aqc_del_udp_tunnel_completion {
21792187

21802188
I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
21812189

2190+
struct i40e_aqc_get_set_rss_key {
2191+
#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2192+
#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2193+
#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2194+
I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2195+
__le16 vsi_id;
2196+
u8 reserved[6];
2197+
__le32 addr_high;
2198+
__le32 addr_low;
2199+
};
2200+
2201+
I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2202+
2203+
struct i40e_aqc_get_set_rss_key_data {
2204+
u8 standard_rss_key[0x28];
2205+
u8 extended_hash_key[0xc];
2206+
};
2207+
2208+
I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2209+
2210+
struct i40e_aqc_get_set_rss_lut {
2211+
#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2212+
#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2213+
#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2214+
I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2215+
__le16 vsi_id;
2216+
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2217+
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2218+
I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2219+
2220+
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2221+
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2222+
__le16 flags;
2223+
u8 reserved[4];
2224+
__le32 addr_high;
2225+
__le32 addr_low;
2226+
};
2227+
2228+
I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2229+
21822230
/* tunnel key structure 0x0B10 */
21832231

21842232
struct i40e_aqc_tunnel_key_structure {

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