Skip to content

Commit 1fa11ee

Browse files
pzanoni-intelpzanoni-intel
committed
drm/i915/icl: start adding the TBT pll
This commit just adds the register addresses and the basic skeleton of the code. The next commits will expand on more specific functions. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-15-paulo.r.zanoni@intel.com
1 parent 00c92d9 commit 1fa11ee

File tree

4 files changed

+47
-9
lines changed

4 files changed

+47
-9
lines changed

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8836,6 +8836,10 @@ enum skl_power_gate {
88368836
#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
88378837
#define DDI_CLK_SEL_NONE (0x0 << 28)
88388838
#define DDI_CLK_SEL_MG (0x8 << 28)
8839+
#define DDI_CLK_SEL_TBT_162 (0xC << 28)
8840+
#define DDI_CLK_SEL_TBT_270 (0xD << 28)
8841+
#define DDI_CLK_SEL_TBT_540 (0xE << 28)
8842+
#define DDI_CLK_SEL_TBT_810 (0xF << 28)
88398843
#define DDI_CLK_SEL_MASK (0xF << 28)
88408844

88418845
/* Transcoder clock selection */
@@ -8985,6 +8989,8 @@ enum skl_power_gate {
89858989
#define PLL_POWER_STATE (1 << 26)
89868990
#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
89878991

8992+
#define TBT_PLL_ENABLE _MMIO(0x46020)
8993+
89888994
#define _MG_PLL1_ENABLE 0x46030
89898995
#define _MG_PLL2_ENABLE 0x46034
89908996
#define _MG_PLL3_ENABLE 0x46038

‎drivers/gpu/drm/i915/intel_ddi.c

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1062,6 +1062,8 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
10621062
static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
10631063
const struct intel_shared_dpll *pll)
10641064
{
1065+
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1066+
int clock = crtc->config->port_clock;
10651067
const enum intel_dpll_id id = pll->info->id;
10661068

10671069
switch (id) {
@@ -1070,6 +1072,20 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
10701072
case DPLL_ID_ICL_DPLL0:
10711073
case DPLL_ID_ICL_DPLL1:
10721074
return DDI_CLK_SEL_NONE;
1075+
case DPLL_ID_ICL_TBTPLL:
1076+
switch (clock) {
1077+
case 162000:
1078+
return DDI_CLK_SEL_TBT_162;
1079+
case 270000:
1080+
return DDI_CLK_SEL_TBT_270;
1081+
case 540000:
1082+
return DDI_CLK_SEL_TBT_540;
1083+
case 810000:
1084+
return DDI_CLK_SEL_TBT_810;
1085+
default:
1086+
MISSING_CASE(clock);
1087+
break;
1088+
}
10731089
case DPLL_ID_ICL_MGPLL1:
10741090
case DPLL_ID_ICL_MGPLL2:
10751091
case DPLL_ID_ICL_MGPLL3:

‎drivers/gpu/drm/i915/intel_dpll_mgr.c

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2857,10 +2857,17 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
28572857
case PORT_D:
28582858
case PORT_E:
28592859
case PORT_F:
2860-
min = icl_port_to_mg_pll_id(port);
2861-
max = min;
2862-
ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
2863-
&pll_state);
2860+
if (0 /* TODO: TBT PLLs */) {
2861+
min = DPLL_ID_ICL_TBTPLL;
2862+
max = min;
2863+
ret = icl_calc_dpll_state(crtc_state, encoder, clock,
2864+
&pll_state);
2865+
} else {
2866+
min = icl_port_to_mg_pll_id(port);
2867+
max = min;
2868+
ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
2869+
&pll_state);
2870+
}
28642871
break;
28652872
default:
28662873
MISSING_CASE(port);
@@ -2893,6 +2900,8 @@ static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
28932900
case DPLL_ID_ICL_DPLL0:
28942901
case DPLL_ID_ICL_DPLL1:
28952902
return CNL_DPLL_ENABLE(id);
2903+
case DPLL_ID_ICL_TBTPLL:
2904+
return TBT_PLL_ENABLE;
28962905
case DPLL_ID_ICL_MGPLL1:
28972906
case DPLL_ID_ICL_MGPLL2:
28982907
case DPLL_ID_ICL_MGPLL3:
@@ -2920,6 +2929,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
29202929
switch (id) {
29212930
case DPLL_ID_ICL_DPLL0:
29222931
case DPLL_ID_ICL_DPLL1:
2932+
case DPLL_ID_ICL_TBTPLL:
29232933
hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
29242934
hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
29252935
break;
@@ -3006,6 +3016,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
30063016
switch (id) {
30073017
case DPLL_ID_ICL_DPLL0:
30083018
case DPLL_ID_ICL_DPLL1:
3019+
case DPLL_ID_ICL_TBTPLL:
30093020
icl_dpll_write(dev_priv, pll);
30103021
break;
30113022
case DPLL_ID_ICL_MGPLL1:
@@ -3104,6 +3115,7 @@ static const struct intel_shared_dpll_funcs icl_pll_funcs = {
31043115
static const struct dpll_info icl_plls[] = {
31053116
{ "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
31063117
{ "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
3118+
{ "TBT PLL", &icl_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
31073119
{ "MG PLL 1", &icl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
31083120
{ "MG PLL 2", &icl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
31093121
{ "MG PLL 3", &icl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },

‎drivers/gpu/drm/i915/intel_dpll_mgr.h

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -113,24 +113,28 @@ enum intel_dpll_id {
113113
* @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
114114
*/
115115
DPLL_ID_ICL_DPLL1 = 1,
116+
/**
117+
* @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
118+
*/
119+
DPLL_ID_ICL_TBTPLL = 2,
116120
/**
117121
* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
118122
*/
119-
DPLL_ID_ICL_MGPLL1 = 2,
123+
DPLL_ID_ICL_MGPLL1 = 3,
120124
/**
121125
* @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
122126
*/
123-
DPLL_ID_ICL_MGPLL2 = 3,
127+
DPLL_ID_ICL_MGPLL2 = 4,
124128
/**
125129
* @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
126130
*/
127-
DPLL_ID_ICL_MGPLL3 = 4,
131+
DPLL_ID_ICL_MGPLL3 = 5,
128132
/**
129133
* @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
130134
*/
131-
DPLL_ID_ICL_MGPLL4 = 5,
135+
DPLL_ID_ICL_MGPLL4 = 6,
132136
};
133-
#define I915_NUM_PLLS 6
137+
#define I915_NUM_PLLS 7
134138

135139
struct intel_dpll_hw_state {
136140
/* i9xx, pch plls */

0 commit comments

Comments
 (0)