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Merge tag 'perf-urgent-for-mingo-5.1-20190329' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent
Pull perf/urgent fixes from Arnaldo: Core libraries: Jiri Olsa: - Fix max perf_event_attr.precise_ip detection. Kan Liang: - Fix parser error for uncore event alias Wei Lin: - Fixup ordering of kernel maps after obtaining the main kernel map address. Intel PT: Adrian Hunter: - Fix TSC slip where A TSC packet can slip past MTC packets so that the timestamp appears to go backwards. - Fixes for exported-sql-viewer GUI conversion to python3. ARM coresight: Solomon Tan: - Fix the build by adding a missing case value for enumeration value introduced in newer library, that now is the required one. tool headers: Arnaldo Carvalho de Melo: - Syncronize kernel headers with the kernel, getting new io_uring and pidfd_send_signal syscalls so that 'perf trace' can handle them. Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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‎Documentation/filesystems/mount_api.txt

Lines changed: 195 additions & 172 deletions
Large diffs are not rendered by default.

‎arch/arm/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -596,6 +596,7 @@ config ARCH_DAVINCI
596596
select HAVE_IDE
597597
select PM_GENERIC_DOMAINS if PM
598598
select PM_GENERIC_DOMAINS_OF if PM && OF
599+
select REGMAP_MMIO
599600
select RESET_CONTROLLER
600601
select SPARSE_IRQ
601602
select USE_OF

‎arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@
9393
};
9494

9595
&hdmi {
96-
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
96+
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
9797
};
9898

9999
&pwm {

‎arch/arm/boot/dts/imx6dl-yapp4-common.dtsi

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -114,9 +114,9 @@
114114
reg = <2>;
115115
};
116116

117-
switch@0 {
117+
switch@10 {
118118
compatible = "qca,qca8334";
119-
reg = <0>;
119+
reg = <10>;
120120

121121
switch_ports: ports {
122122
#address-cells = <1>;
@@ -125,7 +125,7 @@
125125
ethphy0: port@0 {
126126
reg = <0>;
127127
label = "cpu";
128-
phy-mode = "rgmii";
128+
phy-mode = "rgmii-id";
129129
ethernet = <&fec>;
130130

131131
fixed-link {

‎arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -264,7 +264,7 @@
264264
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
265265
vmcc-supply = <&reg_sd3_vmmc>;
266266
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
267-
bus-witdh = <4>;
267+
bus-width = <4>;
268268
no-1-8-v;
269269
status = "okay";
270270
};
@@ -275,7 +275,7 @@
275275
pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
276276
pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
277277
vmcc-supply = <&reg_sd4_vmmc>;
278-
bus-witdh = <8>;
278+
bus-width = <8>;
279279
no-1-8-v;
280280
non-removable;
281281
status = "okay";

‎arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,7 @@
9191
pinctrl-0 = <&pinctrl_enet>;
9292
phy-handle = <&ethphy>;
9393
phy-mode = "rgmii";
94+
phy-reset-duration = <10>; /* in msecs */
9495
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
9596
phy-supply = <&vdd_eth_io_reg>;
9697
status = "disabled";

‎arch/arm/boot/dts/imx6ull-pinfunc-snvs.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-License-Identifier: GPL-2.0
1+
/* SPDX-License-Identifier: GPL-2.0 */
22
/*
33
* Copyright (C) 2016 Freescale Semiconductor, Inc.
44
* Copyright (C) 2017 NXP

‎arch/arm/boot/dts/ste-nomadik-nhk15.dts

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -213,12 +213,13 @@
213213
gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>;
214214
gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>;
215215
/*
216-
* It's not actually active high, but the frameworks assume
217-
* the polarity of the passed-in GPIO is "normal" (active
218-
* high) then actively drives the line low to select the
219-
* chip.
216+
* This chipselect is active high. Just setting the flags
217+
* to GPIO_ACTIVE_HIGH is not enough for the SPI DT bindings,
218+
* it will be ignored, only the special "spi-cs-high" flag
219+
* really counts.
220220
*/
221221
cs-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
222+
spi-cs-high;
222223
num-chipselects = <1>;
223224

224225
/*

‎arch/arm/configs/imx_v4_v5_defconfig

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -170,6 +170,9 @@ CONFIG_IMX_SDMA=y
170170
# CONFIG_IOMMU_SUPPORT is not set
171171
CONFIG_IIO=y
172172
CONFIG_FSL_MX25_ADC=y
173+
CONFIG_PWM=y
174+
CONFIG_PWM_IMX1=y
175+
CONFIG_PWM_IMX27=y
173176
CONFIG_EXT4_FS=y
174177
# CONFIG_DNOTIFY is not set
175178
CONFIG_VFAT_FS=y

‎arch/arm/configs/imx_v6_v7_defconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -398,7 +398,7 @@ CONFIG_MAG3110=y
398398
CONFIG_MPL3115=y
399399
CONFIG_PWM=y
400400
CONFIG_PWM_FSL_FTM=y
401-
CONFIG_PWM_IMX=y
401+
CONFIG_PWM_IMX27=y
402402
CONFIG_NVMEM_IMX_OCOTP=y
403403
CONFIG_NVMEM_VF610_OCOTP=y
404404
CONFIG_TEE=y

‎arch/arm/mach-imx/cpuidle-imx6q.c

Lines changed: 10 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -16,30 +16,23 @@
1616
#include "cpuidle.h"
1717
#include "hardware.h"
1818

19-
static atomic_t master = ATOMIC_INIT(0);
20-
static DEFINE_SPINLOCK(master_lock);
19+
static int num_idle_cpus = 0;
20+
static DEFINE_SPINLOCK(cpuidle_lock);
2121

2222
static int imx6q_enter_wait(struct cpuidle_device *dev,
2323
struct cpuidle_driver *drv, int index)
2424
{
25-
if (atomic_inc_return(&master) == num_online_cpus()) {
26-
/*
27-
* With this lock, we prevent other cpu to exit and enter
28-
* this function again and become the master.
29-
*/
30-
if (!spin_trylock(&master_lock))
31-
goto idle;
25+
spin_lock(&cpuidle_lock);
26+
if (++num_idle_cpus == num_online_cpus())
3227
imx6_set_lpm(WAIT_UNCLOCKED);
33-
cpu_do_idle();
34-
imx6_set_lpm(WAIT_CLOCKED);
35-
spin_unlock(&master_lock);
36-
goto done;
37-
}
28+
spin_unlock(&cpuidle_lock);
3829

39-
idle:
4030
cpu_do_idle();
41-
done:
42-
atomic_dec(&master);
31+
32+
spin_lock(&cpuidle_lock);
33+
if (num_idle_cpus-- == num_online_cpus())
34+
imx6_set_lpm(WAIT_CLOCKED);
35+
spin_unlock(&cpuidle_lock);
4336

4437
return index;
4538
}

‎arch/arm/mach-imx/mach-imx51.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ static void __init imx51_m4if_setup(void)
5959
return;
6060

6161
m4if_base = of_iomap(np, 0);
62+
of_node_put(np);
6263
if (!m4if_base) {
6364
pr_err("Unable to map M4IF registers\n");
6465
return;

‎arch/arm64/Kconfig.platforms

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ config ARCH_BCM2835
2727
bool "Broadcom BCM2835 family"
2828
select TIMER_OF
2929
select GPIOLIB
30+
select MFD_CORE
3031
select PINCTRL
3132
select PINCTRL_BCM2835
3233
select ARM_AMBA

‎arch/arm64/boot/dts/nvidia/tegra186.dtsi

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -321,7 +321,6 @@
321321
nvidia,default-trim = <0x9>;
322322
nvidia,dqs-trim = <63>;
323323
mmc-hs400-1_8v;
324-
supports-cqe;
325324
status = "disabled";
326325
};
327326

‎arch/arm64/boot/dts/renesas/r8a774c0.dtsi

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
/*
33
* Device Tree Source for the RZ/G2E (R8A774C0) SoC
44
*
5-
* Copyright (C) 2018 Renesas Electronics Corp.
5+
* Copyright (C) 2018-2019 Renesas Electronics Corp.
66
*/
77

88
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
@@ -1150,9 +1150,8 @@
11501150
<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
11511151
<&scif_clk>;
11521152
clock-names = "fck", "brg_int", "scif_clk";
1153-
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1154-
<&dmac2 0x5b>, <&dmac2 0x5a>;
1155-
dma-names = "tx", "rx", "tx", "rx";
1153+
dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1154+
dma-names = "tx", "rx";
11561155
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
11571156
resets = <&cpg 202>;
11581157
status = "disabled";

‎arch/arm64/boot/dts/renesas/r8a77990.dtsi

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
/*
33
* Device Tree Source for the R-Car E3 (R8A77990) SoC
44
*
5-
* Copyright (C) 2018 Renesas Electronics Corp.
5+
* Copyright (C) 2018-2019 Renesas Electronics Corp.
66
*/
77

88
#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
@@ -1067,9 +1067,8 @@
10671067
<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
10681068
<&scif_clk>;
10691069
clock-names = "fck", "brg_int", "scif_clk";
1070-
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1071-
<&dmac2 0x5b>, <&dmac2 0x5a>;
1072-
dma-names = "tx", "rx", "tx", "rx";
1070+
dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1071+
dma-names = "tx", "rx";
10731072
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
10741073
resets = <&cpg 202>;
10751074
status = "disabled";

‎arch/s390/include/asm/ap.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -360,4 +360,15 @@ static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
360360
return reg1;
361361
}
362362

363+
/*
364+
* Interface to tell the AP bus code that a configuration
365+
* change has happened. The bus code should at least do
366+
* an ap bus resource rescan.
367+
*/
368+
#if IS_ENABLED(CONFIG_ZCRYPT)
369+
void ap_bus_cfg_chg(void);
370+
#else
371+
static inline void ap_bus_cfg_chg(void){};
372+
#endif
373+
363374
#endif /* _ASM_S390_AP_H_ */

‎arch/s390/include/asm/elf.h

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -252,11 +252,14 @@ do { \
252252

253253
/*
254254
* Cache aliasing on the latest machines calls for a mapping granularity
255-
* of 512KB. For 64-bit processes use a 512KB alignment and a randomization
256-
* of up to 1GB. For 31-bit processes the virtual address space is limited,
257-
* use no alignment and limit the randomization to 8MB.
255+
* of 512KB for the anonymous mapping base. For 64-bit processes use a
256+
* 512KB alignment and a randomization of up to 1GB. For 31-bit processes
257+
* the virtual address space is limited, use no alignment and limit the
258+
* randomization to 8MB.
259+
* For the additional randomization of the program break use 32MB for
260+
* 64-bit and 8MB for 31-bit.
258261
*/
259-
#define BRK_RND_MASK (is_compat_task() ? 0x7ffUL : 0x3ffffUL)
262+
#define BRK_RND_MASK (is_compat_task() ? 0x7ffUL : 0x1fffUL)
260263
#define MMAP_RND_MASK (is_compat_task() ? 0x7ffUL : 0x3ff80UL)
261264
#define MMAP_ALIGN_MASK (is_compat_task() ? 0 : 0x7fUL)
262265
#define STACK_RND_MASK MMAP_RND_MASK

‎arch/s390/include/asm/lowcore.h

Lines changed: 31 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -91,52 +91,53 @@ struct lowcore {
9191
__u64 hardirq_timer; /* 0x02e8 */
9292
__u64 softirq_timer; /* 0x02f0 */
9393
__u64 steal_timer; /* 0x02f8 */
94-
__u64 last_update_timer; /* 0x0300 */
95-
__u64 last_update_clock; /* 0x0308 */
96-
__u64 int_clock; /* 0x0310 */
97-
__u64 mcck_clock; /* 0x0318 */
98-
__u64 clock_comparator; /* 0x0320 */
99-
__u64 boot_clock[2]; /* 0x0328 */
94+
__u64 avg_steal_timer; /* 0x0300 */
95+
__u64 last_update_timer; /* 0x0308 */
96+
__u64 last_update_clock; /* 0x0310 */
97+
__u64 int_clock; /* 0x0318*/
98+
__u64 mcck_clock; /* 0x0320 */
99+
__u64 clock_comparator; /* 0x0328 */
100+
__u64 boot_clock[2]; /* 0x0330 */
100101

101102
/* Current process. */
102-
__u64 current_task; /* 0x0338 */
103-
__u64 kernel_stack; /* 0x0340 */
103+
__u64 current_task; /* 0x0340 */
104+
__u64 kernel_stack; /* 0x0348 */
104105

105106
/* Interrupt, DAT-off and restartstack. */
106-
__u64 async_stack; /* 0x0348 */
107-
__u64 nodat_stack; /* 0x0350 */
108-
__u64 restart_stack; /* 0x0358 */
107+
__u64 async_stack; /* 0x0350 */
108+
__u64 nodat_stack; /* 0x0358 */
109+
__u64 restart_stack; /* 0x0360 */
109110

110111
/* Restart function and parameter. */
111-
__u64 restart_fn; /* 0x0360 */
112-
__u64 restart_data; /* 0x0368 */
113-
__u64 restart_source; /* 0x0370 */
112+
__u64 restart_fn; /* 0x0368 */
113+
__u64 restart_data; /* 0x0370 */
114+
__u64 restart_source; /* 0x0378 */
114115

115116
/* Address space pointer. */
116-
__u64 kernel_asce; /* 0x0378 */
117-
__u64 user_asce; /* 0x0380 */
118-
__u64 vdso_asce; /* 0x0388 */
117+
__u64 kernel_asce; /* 0x0380 */
118+
__u64 user_asce; /* 0x0388 */
119+
__u64 vdso_asce; /* 0x0390 */
119120

120121
/*
121122
* The lpp and current_pid fields form a
122123
* 64-bit value that is set as program
123124
* parameter with the LPP instruction.
124125
*/
125-
__u32 lpp; /* 0x0390 */
126-
__u32 current_pid; /* 0x0394 */
126+
__u32 lpp; /* 0x0398 */
127+
__u32 current_pid; /* 0x039c */
127128

128129
/* SMP info area */
129-
__u32 cpu_nr; /* 0x0398 */
130-
__u32 softirq_pending; /* 0x039c */
131-
__u32 preempt_count; /* 0x03a0 */
132-
__u32 spinlock_lockval; /* 0x03a4 */
133-
__u32 spinlock_index; /* 0x03a8 */
134-
__u32 fpu_flags; /* 0x03ac */
135-
__u64 percpu_offset; /* 0x03b0 */
136-
__u64 vdso_per_cpu_data; /* 0x03b8 */
137-
__u64 machine_flags; /* 0x03c0 */
138-
__u64 gmap; /* 0x03c8 */
139-
__u8 pad_0x03d0[0x0400-0x03d0]; /* 0x03d0 */
130+
__u32 cpu_nr; /* 0x03a0 */
131+
__u32 softirq_pending; /* 0x03a4 */
132+
__u32 preempt_count; /* 0x03a8 */
133+
__u32 spinlock_lockval; /* 0x03ac */
134+
__u32 spinlock_index; /* 0x03b0 */
135+
__u32 fpu_flags; /* 0x03b4 */
136+
__u64 percpu_offset; /* 0x03b8 */
137+
__u64 vdso_per_cpu_data; /* 0x03c0 */
138+
__u64 machine_flags; /* 0x03c8 */
139+
__u64 gmap; /* 0x03d0 */
140+
__u8 pad_0x03d8[0x0400-0x03d8]; /* 0x03d8 */
140141

141142
/* br %r1 trampoline */
142143
__u16 br_r1_trampoline; /* 0x0400 */

‎arch/s390/kernel/perf_cpum_cf_diag.c

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -196,23 +196,30 @@ static void cf_diag_perf_event_destroy(struct perf_event *event)
196196
*/
197197
static int __hw_perf_event_init(struct perf_event *event)
198198
{
199-
struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events);
200199
struct perf_event_attr *attr = &event->attr;
200+
struct cpu_cf_events *cpuhw;
201201
enum cpumf_ctr_set i;
202202
int err = 0;
203203

204-
debug_sprintf_event(cf_diag_dbg, 5,
205-
"%s event %p cpu %d authorized %#x\n", __func__,
206-
event, event->cpu, cpuhw->info.auth_ctl);
204+
debug_sprintf_event(cf_diag_dbg, 5, "%s event %p cpu %d\n", __func__,
205+
event, event->cpu);
207206

208207
event->hw.config = attr->config;
209208
event->hw.config_base = 0;
210-
local64_set(&event->count, 0);
211209

212-
/* Add all authorized counter sets to config_base */
210+
/* Add all authorized counter sets to config_base. The
211+
* the hardware init function is either called per-cpu or just once
212+
* for all CPUS (event->cpu == -1). This depends on the whether
213+
* counting is started for all CPUs or on a per workload base where
214+
* the perf event moves from one CPU to another CPU.
215+
* Checking the authorization on any CPU is fine as the hardware
216+
* applies the same authorization settings to all CPUs.
217+
*/
218+
cpuhw = &get_cpu_var(cpu_cf_events);
213219
for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i)
214220
if (cpuhw->info.auth_ctl & cpumf_ctr_ctl[i])
215221
event->hw.config_base |= cpumf_ctr_ctl[i];
222+
put_cpu_var(cpu_cf_events);
216223

217224
/* No authorized counter sets, nothing to count/sample */
218225
if (!event->hw.config_base) {

‎arch/s390/kernel/smp.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -266,7 +266,8 @@ static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
266266
lc->percpu_offset = __per_cpu_offset[cpu];
267267
lc->kernel_asce = S390_lowcore.kernel_asce;
268268
lc->machine_flags = S390_lowcore.machine_flags;
269-
lc->user_timer = lc->system_timer = lc->steal_timer = 0;
269+
lc->user_timer = lc->system_timer =
270+
lc->steal_timer = lc->avg_steal_timer = 0;
270271
__ctl_store(lc->cregs_save_area, 0, 15);
271272
save_access_regs((unsigned int *) lc->access_regs_save_area);
272273
memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,

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